Correct width mismatches between memory controller and x_addr0

[nathanielnrn]

No description provided.

[nathanielnrn]

Seems like here is the right place to start, need to make sure the widths aren't used elsewhere

[nathanielnrn]

I've made some progress on this and seem to be able to generate parametrically sized brams in a given axi-memory-controller. I still have to correctly wire up the memory controllers to the correct brams but it should be doable.

The thing is, I'm not really happy with my implementation. There is quite a lot of code duplication and it's a pretty hacky way of making things wortk. I was wondering if I should open a draft PR to get some notes from @rachitnigam or @sampsyo (or anyone else) on things before I go any further?

[rachitnigam]

Yeah, draft PR would be a good idea