Fix order of operations of addr calculations (bit shift must occur before addition)

[nathanielnrn]

No description provided.

[nathanielnrn]

Another one I'm not sure about @rachitnigam. The relevant generation occurs here. Could you point me in the direction of parentheses logic//forcing parentheses?

[sampsyo]

This looks to me like a bug in the VAST library! In fact, it looks extremely similar to a previous bug already fixed by @rachitnigam in vegaluisjose/vast#6. VAST uses a Verilog operator precedence function defined here:
https://github.com/vegaluisjose/vast/blob/ae19379034a2d520cd572c0a1cac2f735f8269a6/src/subset/pretty_print.rs#L41-L42

…and it doesn't seem to explicitly consider shifts. Seems like this needs a tweak to make the parens appear in the right place.

A possible workaround for now would be to assign the shift expression to a temporary variable and then use that (which would obviate the need for parentheses).

[rachitnigam]

@nathanielnrn can you open an issue in the vast library saying what the expected behavior vs. actual behavior is and tag me? I can fix it once I have a test. An easy way to figure this out would be to clone the vast repo and add a new test here: https://github.com/vegaluisjose/vast/blob/ae19379034a2d520cd572c0a1cac2f735f8269a6/tests/v05.rs

The test would let you specify what the output verilog should look like

[nathanielnrn]

Addressed as an issue in the vast repository as well.