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Regarding @sampsyo comments, goal is to have small, contained Runt tests that verify that AXI code is being generated correctly
Here's a meta-level idea: maybe we should have a simple Runt test or two for this AXI generation stuff. Then it would be possible, in a PR, to see the changes in the generated Verilog for a couple of examples.
Regarding @sampsyo comments, goal is to have small, contained Runt tests that verify that AXI code is being generated correctly
Originally posted by @sampsyo in #1101 (review)
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