fud as a synthesis rule checker

[rachitnigam]

In our pursuit of building an ever more powerful fud, I have the following proposal to enable fud to monitor output logs from various tools (initially, synthesis) and allow specification of design rule checks for things we expect to happen.

For a particular compilation target (like an FPGA), we would like fud to be able to filter specific log lines. For example, we would like to ensure that when something is marked as an FSM register, the synthesis step can recognize it as an FSM. The fud flow should be configurable (through a JSON file) and be able to check for such log lines and emit errors when they are not present. Then, the compiler can generate a configuration for each program that fud ingests and ensures that all parts of that program are compiled correctly by the later parts of the compilation flow.

To summarize, the flow should have two configurations:

• A per-compilation file generated by the compiler to monitor events for specific code entities in that program (for example, fsm_reg0 is recognized as an FSM by the synthesis tools)
• A tool-specific configuration file that tells fud how to look for a particular event (for example, in vivado2024.2, the is_onehot_fsm event is in file synthesis.log using the regex \(1\) was inferred as a regex

These kinds of rules will make it easier for end-user of fud + calyx to find out problem to debug/report to us!

[sampsyo]

This would be really useful!!