Skip to content

Commit 1d59145

Browse files
moste00moste00
committed
add additional files generated from ASUpdate and update CMakeLists
1 parent e1eaf2e commit 1d59145

File tree

6 files changed

+2386
-7
lines changed

6 files changed

+2386
-7
lines changed

‎CMakeLists.txt‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -609,6 +609,7 @@ if(CAPSTONE_RISCV_SUPPORT)
609609
arch/RISCV/RISCVInstPrinter.h
610610
arch/RISCV/RISCVMapping.h
611611
arch/RISCV/RISCVModule.h
612+
arch/RISCV/RISCVLinkage.h
612613
arch/RISCV/RISCVGenAsmWriter.inc
613614
arch/RISCV/RISCVGenCSAliasMnemMap.inc
614615
arch/RISCV/RISCVGenCSFeatureName.inc
@@ -622,6 +623,11 @@ if(CAPSTONE_RISCV_SUPPORT)
622623
arch/RISCV/RISCVGenRegisterInfo.inc
623624
arch/RISCV/RISCVGenSubtargetInfo.inc
624625
arch/RISCV/RISCVGenSystemOperands.inc
626+
arch/RISCV/RISCVGenCompressedInstructionsInfo.inc
627+
arch/RISCV/RISCVGenCSAliasEnum.inc
628+
arch/RISCV/RISCVGenCSFeatureEnum.inc
629+
arch/RISCV/RISCVGenCSInsnEnum.inc
630+
arch/RISCV/RISCVGenCSRegEnum.inc
625631
)
626632
endif()
627633

‎arch/RISCV/RISCVGenCSAliasEnum.inc‎

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,99 @@
1+
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
2+
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
3+
/* Rot127 <[email protected]> 2022-2024 */
4+
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
5+
6+
/* LLVM-commit: <commit> */
7+
/* LLVM-tag: <tag> */
8+
9+
/* Do not edit. */
10+
11+
/* Capstone's LLVM TableGen Backends: */
12+
/* https://github.com/capstone-engine/llvm-capstone */
13+
14+
RISCV_INS_ALIAS_NOP, // Real instr.: RISCV_ADDI
15+
RISCV_INS_ALIAS_LI, // Real instr.: RISCV_ADDI
16+
RISCV_INS_ALIAS_MV, // Real instr.: RISCV_ADDI
17+
RISCV_INS_ALIAS_NOT, // Real instr.: RISCV_XORI
18+
RISCV_INS_ALIAS_NEG, // Real instr.: RISCV_SUB
19+
RISCV_INS_ALIAS_NEGW, // Real instr.: RISCV_SUBW
20+
RISCV_INS_ALIAS_SEXT_W, // Real instr.: RISCV_ADDIW
21+
RISCV_INS_ALIAS_SEQZ, // Real instr.: RISCV_SLTIU
22+
RISCV_INS_ALIAS_SNEZ, // Real instr.: RISCV_SLTU
23+
RISCV_INS_ALIAS_SLTZ, // Real instr.: RISCV_SLT
24+
RISCV_INS_ALIAS_SGTZ, // Real instr.: RISCV_SLT
25+
RISCV_INS_ALIAS_BEQZ, // Real instr.: RISCV_BEQ
26+
RISCV_INS_ALIAS_BNEZ, // Real instr.: RISCV_BNE
27+
RISCV_INS_ALIAS_BLEZ, // Real instr.: RISCV_BGE
28+
RISCV_INS_ALIAS_BGEZ, // Real instr.: RISCV_BGE
29+
RISCV_INS_ALIAS_BLTZ, // Real instr.: RISCV_BLT
30+
RISCV_INS_ALIAS_BGTZ, // Real instr.: RISCV_BLT
31+
RISCV_INS_ALIAS_J, // Real instr.: RISCV_JAL
32+
RISCV_INS_ALIAS_JAL, // Real instr.: RISCV_JAL
33+
RISCV_INS_ALIAS_JR, // Real instr.: RISCV_JALR
34+
RISCV_INS_ALIAS_JALR, // Real instr.: RISCV_JALR
35+
RISCV_INS_ALIAS_RET, // Real instr.: RISCV_JALR
36+
RISCV_INS_ALIAS_FENCE, // Real instr.: RISCV_FENCE
37+
RISCV_INS_ALIAS_PAUSE, // Real instr.: RISCV_FENCE
38+
RISCV_INS_ALIAS_RDINSTRET, // Real instr.: RISCV_CSRRS
39+
RISCV_INS_ALIAS_RDCYCLE, // Real instr.: RISCV_CSRRS
40+
RISCV_INS_ALIAS_RDTIME, // Real instr.: RISCV_CSRRS
41+
RISCV_INS_ALIAS_RDINSTRETH, // Real instr.: RISCV_CSRRS
42+
RISCV_INS_ALIAS_RDCYCLEH, // Real instr.: RISCV_CSRRS
43+
RISCV_INS_ALIAS_RDTIMEH, // Real instr.: RISCV_CSRRS
44+
RISCV_INS_ALIAS_CSRR, // Real instr.: RISCV_CSRRS
45+
RISCV_INS_ALIAS_CSRW, // Real instr.: RISCV_CSRRW
46+
RISCV_INS_ALIAS_CSRS, // Real instr.: RISCV_CSRRS
47+
RISCV_INS_ALIAS_CSRC, // Real instr.: RISCV_CSRRC
48+
RISCV_INS_ALIAS_CSRWI, // Real instr.: RISCV_CSRRWI
49+
RISCV_INS_ALIAS_CSRSI, // Real instr.: RISCV_CSRRSI
50+
RISCV_INS_ALIAS_CSRCI, // Real instr.: RISCV_CSRRCI
51+
RISCV_INS_ALIAS_SFENCE_VMA, // Real instr.: RISCV_SFENCE_VMA
52+
RISCV_INS_ALIAS_HFENCE_GVMA, // Real instr.: RISCV_HFENCE_GVMA
53+
RISCV_INS_ALIAS_HFENCE_VVMA, // Real instr.: RISCV_HFENCE_VVMA
54+
RISCV_INS_ALIAS_NTL_P1, // Real instr.: RISCV_ADD
55+
RISCV_INS_ALIAS_NTL_PALL, // Real instr.: RISCV_ADD
56+
RISCV_INS_ALIAS_NTL_S1, // Real instr.: RISCV_ADD
57+
RISCV_INS_ALIAS_NTL_ALL, // Real instr.: RISCV_ADD
58+
RISCV_INS_ALIAS_LPAD, // Real instr.: RISCV_AUIPC
59+
RISCV_INS_ALIAS_FMV_S, // Real instr.: RISCV_FSGNJ_S
60+
RISCV_INS_ALIAS_FABS_S, // Real instr.: RISCV_FSGNJX_S
61+
RISCV_INS_ALIAS_FNEG_S, // Real instr.: RISCV_FSGNJN_S
62+
RISCV_INS_ALIAS_FRCSR, // Real instr.: RISCV_CSRRS
63+
RISCV_INS_ALIAS_FSCSR, // Real instr.: RISCV_CSRRW
64+
RISCV_INS_ALIAS_FRRM, // Real instr.: RISCV_CSRRS
65+
RISCV_INS_ALIAS_FSRM, // Real instr.: RISCV_CSRRW
66+
RISCV_INS_ALIAS_FSRMI, // Real instr.: RISCV_CSRRWI
67+
RISCV_INS_ALIAS_FRFLAGS, // Real instr.: RISCV_CSRRS
68+
RISCV_INS_ALIAS_FSFLAGS, // Real instr.: RISCV_CSRRW
69+
RISCV_INS_ALIAS_FSFLAGSI, // Real instr.: RISCV_CSRRWI
70+
RISCV_INS_ALIAS_FMV_D, // Real instr.: RISCV_FSGNJ_D
71+
RISCV_INS_ALIAS_FABS_D, // Real instr.: RISCV_FSGNJX_D
72+
RISCV_INS_ALIAS_FNEG_D, // Real instr.: RISCV_FSGNJN_D
73+
RISCV_INS_ALIAS_FMV_H, // Real instr.: RISCV_FSGNJ_H
74+
RISCV_INS_ALIAS_FABS_H, // Real instr.: RISCV_FSGNJX_H
75+
RISCV_INS_ALIAS_FNEG_H, // Real instr.: RISCV_FSGNJN_H
76+
RISCV_INS_ALIAS_ZEXT_W, // Real instr.: RISCV_ADD_UW
77+
RISCV_INS_ALIAS_VL1R_V, // Real instr.: RISCV_VL1RE8_V
78+
RISCV_INS_ALIAS_VL2R_V, // Real instr.: RISCV_VL2RE8_V
79+
RISCV_INS_ALIAS_VL4R_V, // Real instr.: RISCV_VL4RE8_V
80+
RISCV_INS_ALIAS_VL8R_V, // Real instr.: RISCV_VL8RE8_V
81+
RISCV_INS_ALIAS_VNEG_V, // Real instr.: RISCV_VRSUB_VX
82+
RISCV_INS_ALIAS_VWCVT_X_X_V, // Real instr.: RISCV_VWADD_VX
83+
RISCV_INS_ALIAS_VWCVTU_X_X_V, // Real instr.: RISCV_VWADDU_VX
84+
RISCV_INS_ALIAS_VNOT_V, // Real instr.: RISCV_VXOR_VI
85+
RISCV_INS_ALIAS_VNCVT_X_X_W, // Real instr.: RISCV_VNSRL_WX
86+
RISCV_INS_ALIAS_VFNEG_V, // Real instr.: RISCV_VFSGNJN_VV
87+
RISCV_INS_ALIAS_VFABS_V, // Real instr.: RISCV_VFSGNJX_VV
88+
RISCV_INS_ALIAS_VMMV_M, // Real instr.: RISCV_VMAND_MM
89+
RISCV_INS_ALIAS_VMCLR_M, // Real instr.: RISCV_VMXOR_MM
90+
RISCV_INS_ALIAS_VMSET_M, // Real instr.: RISCV_VMXNOR_MM
91+
RISCV_INS_ALIAS_VMNOT_M, // Real instr.: RISCV_VMNAND_MM
92+
RISCV_INS_ALIAS_C_NTL_P1, // Real instr.: RISCV_C_ADD_HINT
93+
RISCV_INS_ALIAS_C_NTL_PALL, // Real instr.: RISCV_C_ADD_HINT
94+
RISCV_INS_ALIAS_C_NTL_S1, // Real instr.: RISCV_C_ADD_HINT
95+
RISCV_INS_ALIAS_C_NTL_ALL, // Real instr.: RISCV_C_ADD_HINT
96+
RISCV_INS_ALIAS_CV_MULS, // Real instr.: RISCV_CV_MULSN
97+
RISCV_INS_ALIAS_CV_MULHHS, // Real instr.: RISCV_CV_MULHHSN
98+
RISCV_INS_ALIAS_CV_MULU, // Real instr.: RISCV_CV_MULUN
99+
RISCV_INS_ALIAS_CV_MULHHU, // Real instr.: RISCV_CV_MULHHUN

‎arch/RISCV/RISCVGenCSFeatureEnum.inc‎

Lines changed: 113 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,113 @@
1+
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
2+
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
3+
/* Rot127 <[email protected]> 2022-2024 */
4+
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
5+
6+
/* LLVM-commit: <commit> */
7+
/* LLVM-tag: <tag> */
8+
9+
/* Do not edit. */
10+
11+
/* Capstone's LLVM TableGen Backends: */
12+
/* https://github.com/capstone-engine/llvm-capstone */
13+
14+
RISCV_FEATURE_HASSTDEXTI = 128,
15+
RISCV_FEATURE_HASSTDEXTZICBOM,
16+
RISCV_FEATURE_HASSTDEXTZICBOP,
17+
RISCV_FEATURE_HASSTDEXTZICBOZ,
18+
RISCV_FEATURE_HASSTDEXTZICSR,
19+
RISCV_FEATURE_HASSTDEXTZICOND,
20+
RISCV_FEATURE_HASSTDEXTZIFENCEI,
21+
RISCV_FEATURE_HASSTDEXTZIHINTPAUSE,
22+
RISCV_FEATURE_HASSTDEXTZIHINTNTL,
23+
RISCV_FEATURE_HASSTDEXTZIMOP,
24+
RISCV_FEATURE_HASSTDEXTZICFILP,
25+
RISCV_FEATURE_HASSTDEXTZICFISS,
26+
RISCV_FEATURE_HASSTDEXTM,
27+
RISCV_FEATURE_HASSTDEXTMORZMMUL,
28+
RISCV_FEATURE_HASSTDEXTA,
29+
RISCV_FEATURE_HASSTDEXTZTSO,
30+
RISCV_FEATURE_HASSTDEXTZACAS,
31+
RISCV_FEATURE_HASSTDEXTZAWRS,
32+
RISCV_FEATURE_HASSTDEXTF,
33+
RISCV_FEATURE_HASSTDEXTD,
34+
RISCV_FEATURE_HASSTDEXTZFHMIN,
35+
RISCV_FEATURE_HASSTDEXTZFH,
36+
RISCV_FEATURE_HASSTDEXTZFBFMIN,
37+
RISCV_FEATURE_HASHALFFPLOADSTOREMOVE,
38+
RISCV_FEATURE_HASSTDEXTZFA,
39+
RISCV_FEATURE_HASSTDEXTZFINX,
40+
RISCV_FEATURE_HASSTDEXTZDINX,
41+
RISCV_FEATURE_HASSTDEXTZHINXMIN,
42+
RISCV_FEATURE_HASSTDEXTZHINX,
43+
RISCV_FEATURE_HASSTDEXTC,
44+
RISCV_FEATURE_HASRVCHINTS,
45+
RISCV_FEATURE_HASSTDEXTCORZCA,
46+
RISCV_FEATURE_HASSTDEXTZCB,
47+
RISCV_FEATURE_HASSTDEXTCORZCD,
48+
RISCV_FEATURE_HASSTDEXTZCMP,
49+
RISCV_FEATURE_HASSTDEXTZCMT,
50+
RISCV_FEATURE_HASSTDEXTCORZCFORZCE,
51+
RISCV_FEATURE_HASSTDEXTZCMOP,
52+
RISCV_FEATURE_HASSTDEXTZBA,
53+
RISCV_FEATURE_HASSTDEXTZBB,
54+
RISCV_FEATURE_HASSTDEXTZBC,
55+
RISCV_FEATURE_HASSTDEXTZBS,
56+
RISCV_FEATURE_HASSTDEXTZBKB,
57+
RISCV_FEATURE_HASSTDEXTZBKX,
58+
RISCV_FEATURE_HASSTDEXTZBBORZBKB,
59+
RISCV_FEATURE_HASSTDEXTZBKC,
60+
RISCV_FEATURE_HASSTDEXTZBCORZBKC,
61+
RISCV_FEATURE_HASSTDEXTZKND,
62+
RISCV_FEATURE_HASSTDEXTZKNE,
63+
RISCV_FEATURE_HASSTDEXTZKNDORZKNE,
64+
RISCV_FEATURE_HASSTDEXTZKNH,
65+
RISCV_FEATURE_HASSTDEXTZKSED,
66+
RISCV_FEATURE_HASSTDEXTZKSH,
67+
RISCV_FEATURE_HASSTDEXTZKR,
68+
RISCV_FEATURE_HASSTDEXTZVFBFMIN,
69+
RISCV_FEATURE_HASSTDEXTZVFBFWMA,
70+
RISCV_FEATURE_HASSTDEXTZFHORZVFH,
71+
RISCV_FEATURE_HASSTDEXTZVKB,
72+
RISCV_FEATURE_HASSTDEXTZVBB,
73+
RISCV_FEATURE_HASSTDEXTZVBC,
74+
RISCV_FEATURE_HASSTDEXTZVKG,
75+
RISCV_FEATURE_HASSTDEXTZVKNED,
76+
RISCV_FEATURE_HASSTDEXTZVKNHA,
77+
RISCV_FEATURE_HASSTDEXTZVKNHB,
78+
RISCV_FEATURE_HASSTDEXTZVKNHAORZVKNHB,
79+
RISCV_FEATURE_HASSTDEXTZVKSED,
80+
RISCV_FEATURE_HASSTDEXTZVKSH,
81+
RISCV_FEATURE_HASVINSTRUCTIONS,
82+
RISCV_FEATURE_HASVINSTRUCTIONSI64,
83+
RISCV_FEATURE_HASVINSTRUCTIONSANYF,
84+
RISCV_FEATURE_HASVINSTRUCTIONSF16MINIMAL,
85+
RISCV_FEATURE_HASSTDEXTH,
86+
RISCV_FEATURE_HASSTDEXTSVINVAL,
87+
RISCV_FEATURE_HASVENDORXVENTANACONDOPS,
88+
RISCV_FEATURE_HASVENDORXTHEADBA,
89+
RISCV_FEATURE_HASVENDORXTHEADBB,
90+
RISCV_FEATURE_HASVENDORXTHEADBS,
91+
RISCV_FEATURE_HASVENDORXTHEADCONDMOV,
92+
RISCV_FEATURE_HASVENDORXTHEADCMO,
93+
RISCV_FEATURE_HASVENDORXTHEADFMEMIDX,
94+
RISCV_FEATURE_HASVENDORXTHEADMAC,
95+
RISCV_FEATURE_HASVENDORXTHEADMEMIDX,
96+
RISCV_FEATURE_HASVENDORXTHEADMEMPAIR,
97+
RISCV_FEATURE_HASVENDORXTHEADSYNC,
98+
RISCV_FEATURE_HASVENDORXTHEADVDOT,
99+
RISCV_FEATURE_HASVENDORXSFVCP,
100+
RISCV_FEATURE_HASVENDORXSFVQMACCDOD,
101+
RISCV_FEATURE_HASVENDORXSFVQMACCQOQ,
102+
RISCV_FEATURE_HASVENDORXSFVFWMACCQQQ,
103+
RISCV_FEATURE_HASVENDORXSFVFNRCLIPXFQF,
104+
RISCV_FEATURE_HASVENDORXCVELW,
105+
RISCV_FEATURE_HASVENDORXCVBITMANIP,
106+
RISCV_FEATURE_HASVENDORXCVMAC,
107+
RISCV_FEATURE_HASVENDORXCVMEM,
108+
RISCV_FEATURE_HASVENDORXCVALU,
109+
RISCV_FEATURE_HASVENDORXCVSIMD,
110+
RISCV_FEATURE_HASVENDORXCVBI,
111+
RISCV_FEATURE_ISRV64,
112+
RISCV_FEATURE_ISRV32,
113+
RISCV_FEATURE_ISRVE,

0 commit comments

Comments
 (0)