diff --git a/ADDITIONAL-README.md b/ADDITIONAL-README.md new file mode 100644 index 00000000..8f450974 --- /dev/null +++ b/ADDITIONAL-README.md @@ -0,0 +1,572 @@ +#Install CaribouLite with Raspberry Pi OS Bookworm (Lite) (64bit) + +My goal is to install the cariboulite on a Raspberry Pi0_2W and/or a Pi4. Requirements: +- Connecetd to the Pi over etehernet and ultimately provide power to the Pi with POE +- Use SDR++ server and SDR++ +- Use gnu-radio + +All of the software fits on a sdcard of 16GByte. The CarubouLite uses SoapySDR as an hardware abstraction layer and needs to be installed as well. This can be done manually or automatically with the CaribouLite install script. + +This 'recipe' was create and tested on a Pi0 and a Pi4 on May 1st 2025. + +###Initial steps +Download & install the latest version of PiOS using the Raspberry Pi Imager. Ensure that you have enabled ssh under services and that you have provided basic information to the general settings of the OS Customisation. + +I make the assumption that all of this is familiar to you and you know how to ssh over the local network to your Pi and know how to work with nano the text editor. + +After you have logged on, update the Pi OS: + +``` +sudo apt upate +sudo apt upgrade +``` +###Modifying the boot config.txt file +Modify the `/boot/firmware/config.txt` file to ensure the parameters are set so that the cariboulite can communicate with the CPU. The last two lines disable Bluetooth and WiFi, to minimise RF interference. So the Pi needs to be connected to the local network through an ethernet cable, else you can no longer communicate with the Pi after the next reboot. + +`sudo nano /boot/firmware/config.txt` + +Add the lines below just above the line that reads: +`# Enable audio (loads snd_bcm2835)` + +``` +dtparam=i2c_arm=off +dtparam=spi=off + +# CaribouLite +dtparam=i2c_vc=on +dtoverlay=spi1-3cs + +# Disable WiFi and Bluetooth +dtoverlay=disable-wifi +dtoverlay=disable-bt +``` + +Save the file and reboot + +###Install linux kernel header files: + +```sudo apt install linux-headers-rpi-v8``` +>Note: I think this step is only required if you want build SDR++. + +###Monitoring the Pi's activity +The next steps will often take a while, during which you might want to periodically check that everything is still moving along. +In separate terminals watch what is going on during any of the following steps with `htop` and/or `dmesg`. This is how I discovered that `make` ran out of memory. + +``` +htop +sudo dmesg -wH +``` +###Install `git` & `cmake` + +``` +sudo apt install git cmake +``` + +#SoapySDR (optional) +If you want to have more control over where SoapySDR en SoapyRemote are installed, execute these steps first. If you use these steps, you should say `No` to the `install SoapySDR` question from the CaribouLite install script. + +Create a directory where you want to keep your source code. I call mine: `src`. + +``` +mkdir src && cd src +``` + +Get the source code: + +``` +git clone https://github.com/pothosware/SoapySDR.git +git clone https://github.com/pothosware/Soapyremote.git + +``` +Or: + +``` +git clone https://github.com/Habraken/SoapySDR.git +git clone https://github.com/Habraken/SoapyRemote.git +``` +The following library is not available by default and SoapyRemakemote will complain but not fail: + +``` +sudo apt install libavahi-client-dev +``` + +In both repositories run the below commands to build and install SoapySDR and SoapyRemote starting with SoapySDR as SoapyRemote depends on it. + +``` +mkdir build && cd build +cmake .. -DENABLE_PYTHON3=ON +make -j`nproc` +sudo make install -j`nproc` +sudo ldconfig #needed on debian systems +SoapySDRUtil --info +``` + +#CaribouLite +Create a directory where you want to keep your source code. I call mine: `src`. + +``` +mkdir src && cd src +``` + +Get the source code: + +``` +git clone https://github.com/cariboulabs/cariboulite.git +``` + +Or if you don't want to patch yourself: + +``` +git clone https://github.com/Habraken/cariboulite.git +``` + +Before you can install anything make the following three changes to `~/src/cariboulite/driver/smi_stream_dev.c`. + +``` +cd ~/src/cariboulite/driver +sudo nano smi_stream_dev.c +``` + +Add this include statement near the other include statements: `#include ` + +Then Hit Ctl+W and type `‘create sysfs’` and change the line with the `-` in front to the line with the `+` in front. + +``` +// Create sysfs entries with "smi-stream-dev" +-smi_stream_class = class_create(THIS_MODULE, DEVICE_NAME); ++smi_stream_class = class_create(DEVICE_NAME); +``` + +Then Hit Ctl+W and type ‘smi_stream_dev_remove’ and change the line with the - in front to the line with the + in front and remove the return statement with the - in front. + +``` +* smi_stream_remove - called when the driver is unloaded. +* +***************************************************************************/ + +-static int smi_stream_dev_remove(struct platform_device *pdev) ++static void smi_stream_dev_remove(struct platform_device *pdev) + { + //if (inst->reader_thread != NULL) kthread_stop(inst->reader_thread); + //inst->reader_thread = NULL; + + device_destroy(smi_stream_class, smi_stream_devid); + class_destroy(smi_stream_class); + cdev_del(&smi_stream_cdev); + unregister_chrdev_region(smi_stream_devid, 1); + + dev_info(inst->dev, DRIVER_NAME": smi-stream dev removed"); +- return 0; + } +``` + +In the `cariboulite/driver` directory: + +``` +./install.sh install +``` + +Then in the cariboulite directory: + +``` +./install.sh +``` +This takes ‘a while’ on a Pi0. At a certain point the script will ask if you want to `install SoapySDR`, if you did not install it before. Say `Yes`. After the script has completed, reboot the Pi. Now we need to check with SMI driver is working correctly. + +``` +lsmod | grep smi +``` +The ouput should look like this: + +``` +pi@pi0b-bookworm:~ $ lsmod | grep smi +smi_stream_dev 16384 0 +bcm2835_smi 20480 1 smi_stream_dev +pi@pi0b-bookworm:~ $ +``` +Also check if the permissions are set correclty: + +``` +ls -l /dev/smi +``` +the ouput shoudl look like this: + +``` +pi@pi0b-bookworm:~ $ ls -l /dev/smi +crw-rw-rw- 1 root root 239, 0 May 1 13:40 /dev/smi +pi@pi0b-bookworm:~ $ +``` + +###Testing SoapySDR + +As SoapySDR was install by the install script of cariboulite it should be possible to communicate with the CaribouLite. + +``` +SoapySDRUtil --find +``` +The ouput should look like this: + +``` +###################################################### +## Soapy SDR -- the SDR abstraction library ## +###################################################### + +[INFO] SoapyCaribouliteSession, sessionCount: 0 +05-01 13:51:14.339 627 627 I CARIBOU_PROG caribou_prog_configure_from_buffer@caribou_prog.c:260 Sending bitstream of size 32220 +05-01 13:51:16.644 627 627 I CARIBOU_PROG caribou_prog_configure_from_buffer@caribou_prog.c:292 FPGA programming - Success! + +Printing 'findCariboulite' Request: +Found device 0 + channel = S1G + device_id = 0 + driver = Cariboulite + label = CaribouLite S1G[1e3bc7c2] + name = CaribouLite RPI Hat + serial = 1e3bc7c2 + uuid = 11884996-87f4-4b07-9961-a38c1b78fa08 + vendor = CaribouLabs LTD + version = 0x0001 + +Found device 1 + channel = HiF + device_id = 1 + driver = Cariboulite + label = CaribouLite HiF[1e3bc7c3] + name = CaribouLite RPI Hat + serial = 1e3bc7c3 + uuid = 11884996-87f4-4b07-9961-a38c1b78fa08 + vendor = CaribouLabs LTD + version = 0x0001 +``` + +Now it is also possible to interact with the CaribouLite board with the provided `cariboulite_test_app` in the `~/src/cariboulite/build` directory. + +``` +./cariboulite_test_app +``` +At the end of a lot of ouput there should be something like this: + +``` + + ____ _ _ _ _ _ + / ___|__ _ _ __(_) |__ ___ _ _| | (_) |_ ___ + | | / _` | '__| | '_ \ / _ \| | | | | | | __/ _ \ + | |__| (_| | | | | |_) | (_) | |_| | |___| | || __/ + \____\__,_|_| |_|_.__/ \___/ \__,_|_____|_|\__\___| + + + Select a function: + [0] Hard reset FPGA + [1] Soft reset FPGA + [2] Print board info and versions + [3] Program FPGA + [4] Perform a Self-Test + [5] FPGA Digital I/O + [6] FPGA RFFE control + [7] FPGA SMI fifo status + [8] Modem transmit CW signal + [9] Modem receive I/Q stream + [10] Synthesizer 85-4200 MHz + [99] Quit + Choice: +``` +>Note: If you try option `9` and then select option `2` there will errors that look like this: +> +``` +FF D0 FF F4 FF 02 C0 D8 FF C0 FF FC FF C2 FF E6 | ................ +05-01 14:00:45.038 644 648 E CARIBOULITE Radio cariboulite_radio_read_samples@cariboulite_radio.c:1276 SMI data synchronization failed +FF E0 FF D2 C0 12 C0 1A C0 DA FF 02 C0 00 C0 EE | ................ +05-01 14:00:45.046 644 648 E CARIBOULITE Radio cariboulite_radio_read_samples@cariboulite_radio.c:1276 SMI data synchronization failed +C0 C0 C0 C4 C0 FA C0 E6 C0 30 C0 22 C0 C0 C0 CC | .........0.".... +05-01 14:00:45.055 644 648 E CARIBOULITE Radio cariboulite_radio_read_samples@cariboulite_radio.c:1276 SMI data synchronization failed +``` + +>~~~This is caused by the Pi0 not being able to handle 4 MSPS. During the configuration of SoapyRemote or SDR++ server we shall change this to 2 MSPS.~~~ + +>I have just discovered that this behaviour is in fact due to a defective cariboulite board. It appears to function normally until you try to start the smi stream. Wait on feedback fromCaribouLabs. (May 1st 2025) + +> Also the Pi0 can do 4 MSPS if the data type is set CS8 instead of CS16 or CF32. + +###Increase the swapfile size +During the SDR++ build `make` ran out of memory. Hence I increased the swap file from 512 to 1024. + +``` +sudo dphys-swapfile swapoff +sudo nano /etc/dphys-swapfile +``` +Chnage the line `CONF_SWAPSIZE=512` to `CONF_SWAPSIZE=1024`. Save the file. + +``` +sudo dphys-swapfile setup +sudo dphys-swapfile swapon +``` + +Or: + +``` +sudo reboot +``` +#SDR++ + +Install dependencies for SDR++: + +``` +sudo apt install libglfw3 // maybe not needed. +sudo apt install libglfw3-dev +sudo apt install libfftw3-dev +sudo apt install libvolk2-dev +sudo apt install libzstd-dev +sudo apt install librtaudio-dev +``` + +or in one go: + +``` +sudo apt install libglfw3-dev libfftw3-dev libvolk2-dev libzstd-dev librtaudio-dev + +``` +### Install via the nightly build package + +The easiest method is to download and install the nightly builds of SDR++. First download the package: + +``` +curl https://github.com/AlexandreRouma/SDRPlusPlus/releases/download/nightly/sdrpp_debian_bookworm_aarch64.deb +``` + +Then run the following: + +``` +sudo apt install ~/Downloads/sdrpp_debian_bookworm_aarch64.db +``` + +### Build from source + +Get the source code: + +``` +git clone https://github.com/AlexandreRouma/SDRPlusPlus.git +``` + +``` +git clone https://github.com/Habraken/SDRPlusPlus.git +``` +In the `~/src/SDRPlusPLus` directory: + +``` +mkdir build && cd build +``` + +``` +cmake -DOPT_BUILD_SOAPY_SOURCE=ON -DOPT_BUILD_HERMES_SOURCE=ON -DOPT_BUILD_PLUTOSDR_SOURCE=OFF -DOPT_BUILD_AIRSPY_SOURCE=OFF -DOPT_BUILD_AIRSPYHF_SOURCE=OFF -DOPT_BUILD_HACKRF_SOURCE=OFF -DOPT_BUILD_RTL_SDR_SOURCE=OFF .. +``` + +``` +make -j2 +``` + +``` +cd .. +``` +``` +sh ./create_root.sh +``` +``` +cd build +``` +``` +sudo make install +``` +``` +sudo ldconfig +``` + + +>Note: There is no need to start the SoapySDR service! Instead we will use the SDR++ Server. For gnu-radio the Soapy server is needed though... + +###Desktop version SDR++ +Before the `soapy_source` is available it needs to be added, in the ‘Module Manager’ of SDR++ if you are running the desktop app on the Pi4. In the 'module manager' select ‘soapy_source’, add a name to the left e.g. ‘Soapy Source’ and click on the tiny plus sign on the right… + +Or... + +###Headless version SDR++ +If you are working from the cli you need to first run SDR++ so that the default config files are created. + +``` +sdrpp --server +``` +Hit ^c to stop the server again. + +Edit the `~/.config/sdrpp/config.json` and add the soapy_source module: + +``` + , + "Soapy Source": { + "enabled": true, + "module": "soapy_source" + } +``` + +>Note: mind the comma above the double quote! + +Save the file and start the SDR++ server. + +``` +sdrpp --server +``` +When the server starts watch the cli output and confirm that the 'Soapy Source' is loaded. + +On your remote computer you should now start SDR++ and select SDR++ Server as Source. Provide the correct IP address of the Pi running the SDR++ server. Press `Connect`. At the `Source [REMOTE]` use the drop down menu to select `SoapySDR`. You ay have to press the `Refresh` button first. In the dropdown menu below that make sure you select the device appropriate for your selected frequency. + +>Observations: The Pi4 can easily handle 4 MSPS but somehow when the `bandwidth` setting is set to `auto` there is no data coming from the radio. When the bandwidth setting is changed to 2 MHz data is streaming again. However the display bandwidth is 4 MHz! +>The analog bandwidth is only 2.5 MHz according to the datasheet. With `SoapySDRUtil --probe` you'll find a max. sample rate = 4 MSPS and the max. filter bandwidth = 2 MHz. + + +#Trouble shooting faulty board + +###System + +``` +uname -a +``` +``` +Linux pi0c-bookworm 6.12.20+rpt-rpi-v8 #1 SMP PREEMPT Debian 1:6.12.20-1+rpt1~bpo12+1 (2025-03-19) aarch64 GNU/Linux +``` + +###SoapySDRUtil + +``` +SoapySDRUtil --find +``` + +``` +###################################################### +## Soapy SDR -- the SDR abstraction library ## +###################################################### + +[INFO] SoapyCaribouliteSession, sessionCount: 0 +05-02 07:55:11.142 644 644 I FPGA caribou_fpga_program_to_fpga@caribou_fpga.c:210 FPGA already operational - not programming (use 'force_prog=true' to force update) +Printing 'findCariboulite' Request: +Found device 0 + channel = S1G + device_id = 0 + driver = Cariboulite + label = CaribouLite S1G[1e3bc7c2] + name = CaribouLite RPI Hat + serial = 1e3bc7c2 + uuid = 11884996-87f4-4b07-9961-a38c1b78fa08 + vendor = CaribouLabs LTD + version = 0x0001 + +Found device 1 + channel = HiF + device_id = 1 + driver = Cariboulite + label = CaribouLite HiF[1e3bc7c3] + name = CaribouLite RPI Hat + serial = 1e3bc7c3 + uuid = 11884996-87f4-4b07-9961-a38c1b78fa08 + vendor = CaribouLabs LTD + version = 0x0001 +``` + +``` +SoapySDRUtil --probe +``` + +``` +###################################################### +## Soapy SDR -- the SDR abstraction library ## +###################################################### + +Probe device +[INFO] SoapyCaribouliteSession, sessionCount: 0 +05-02 08:03:21.048 712 712 I FPGA caribou_fpga_program_to_fpga@caribou_fpga.c:210 FPGA already operational - not programming (use 'force_prog=true' to force update) +Printing 'findCariboulite' Request: +[INFO] Initializing DeviceID: 0, Label: CaribouLite S1G[1e3bc7c2], ChannelType: S1G +[INFO] Creating SampleQueue MTU: 131072 I/Q samples (524288 bytes) + +---------------------------------------------------- +-- Device identification +---------------------------------------------------- + driver=Cariboulite + hardware=Cariboulite Rev2.8 + device_id=0 + fpga_revision=1 + hardware_revision=0x0001 + product_name=CaribouLite RPI Hat + serial_number=253617121 + vendor_name=CaribouLabs LTD + +---------------------------------------------------- +-- Peripheral summary +---------------------------------------------------- + Channels: 1 Rx, 1 Tx + Timestamps: NO + +---------------------------------------------------- +-- RX Channel 0 +---------------------------------------------------- + Full-duplex: NO + Supports AGC: YES + Stream formats: CS16, CS8, CF32, CF64 + Native format: CS16 [full-scale=4095] + Antennas: TX/RX Sub1GHz + Full gain range: [0, 69] dB + Modem AGC gain range: [0, 69] dB + Full freq range: [389.5, 510], [779, 1020] MHz + RF freq range: [389.5, 510], [779, 1020] MHz + Sample rates: 4, 2, 1.33333, 1, 0.8, 0.666667, 0.5, 0.4 MSps + Filter bandwidths: 0.02, 0.05, 0.1, 0.16, 0.2, 0.8, 1, 1.25, 1.6, 2 MHz + Sensors: RSSI, ENERGY, PLL_LOCK_MODEM + * RSSI (RX RSSI):[-127, 4] 0.000000 + Modem level RSSI measurment + * ENERGY (RX ENERGY):[-127, 4] 0.000000 + Modem level ENERGY (EDC) measurment + * PLL_LOCK_MODEM (PLL Lock Modem): 1.000000 + Modem PLL locking indication + +---------------------------------------------------- +-- TX Channel 0 +---------------------------------------------------- + Full-duplex: NO + Supports AGC: NO + Stream formats: CS16, CS8, CF32, CF64 + Native format: CS16 [full-scale=4095] + Antennas: TX/RX Sub1GHz + Full gain range: [0, 31] dB + Modem PA gain range: [0, 31] dB + Full freq range: [389.5, 510], [779, 1020] MHz + RF freq range: [389.5, 510], [779, 1020] MHz + Sample rates: 4, 2, 1.33333, 1, 0.8, 0.666667, 0.5, 0.4 MSps + Filter bandwidths: 0.08, 0.1, 0.125, 0.16, 0.2, 0.4, 0.5, 0.625, 0.8, 1 MHz + Sensors: PLL_LOCK_MODEM + * PLL_LOCK_MODEM (PLL Lock Modem): 1.000000 + Modem PLL locking indication +``` + +###Self test + +Error messages during the selftest using the `cariboulite_test_app`: + +``` +05-02 07:38:08.605 622 622 D CARIBOULITE Setup +cariboulite_self_test@cariboulite_setup.c:480 Testing modem communication and versions +05-02 07:38:08.606 622 622 W AT86RF215_Main +at86rf215_print_version@at86rf215.c:294 MODEM Version: not AT86RF215 IQ capable modem (product number: 0x0d, versions 03) +05-02 07:38:08.606 622 622 E CARIBOULITE Setup +cariboulite_self_test@cariboulite_setup.c:486 The assembled modem is not AT86RF215 / IQ variant (product number: 0x0d) +05-02 07:38:08.606 622 622 D CARIBOULITE Setup +cariboulite_self_test@cariboulite_setup.c:495 Testing mixer communication and versions +05-02 07:38:08.608 622 622 E CARIBOULITE Setup +cariboulite_self_test@cariboulite_setup.c:513 Self-test process finished with errors +``` + +I have also tried all the other options such as hard reset of the fpga, soft reset of the fpga, reprogramming of the fpga. During the receive test there are always smi sync errors. + + + + +#GNU-RADIO (WIP) +``` +sudp apt install gnuradio +``` \ No newline at end of file diff --git a/driver/smi_stream_dev.c b/driver/smi_stream_dev.c index e0d6618e..643ad08a 100644 --- a/driver/smi_stream_dev.c +++ b/driver/smi_stream_dev.c @@ -62,9 +62,15 @@ #include #include #include +#include #include "smi_stream_dev.h" +#include // for READ_ONCE +#include // dev_info_ratelimited +#include // hrtimer +#include // ktime_get + // MODULE SPECIFIC PARAMETERS // the modules.d line is as follows: "options smi_stream_dev fifo_mtu_multiplier=6 addr_dir_offset=2 addr_ch_offset=3" @@ -73,6 +79,9 @@ static int addr_dir_offset = 2; // GPIO_SA[4:0] offset of the ch static int addr_ch_offset = 3; // GPIO_SA[4:0] offset of the channel select #define SMI_TRANSFER_MULTIPLIER 64 +/* Bump this if you want an even longer run between refreshes */ +#define SMI_REFRESH_CHUNKS 1024 /* quarters per SMIL window */ +#define SMI_TOPUP_MARGIN 4 /* refresh before it fully drains */ module_param(fifo_mtu_multiplier, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); module_param(addr_dir_offset, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); @@ -113,6 +122,16 @@ struct bcm2835_smi_dev_instance bool transfer_thread_running; bool reader_waiting_sema; bool writer_waiting_sema; + + /* ---- TX watchdog (read-only) ---- */ + struct delayed_work tx_watch_work; + unsigned int tx_watch_period_us; + u32 tx_watch_last_smil; + bool tx_watch_last_active; + u32 tx_watch_min_smil; + /* ---- TX SMIL keepalive ---- */ + struct hrtimer tx_hr; + ktime_t tx_hr_period; }; @@ -128,7 +147,10 @@ static void stream_smi_read_dma_callback(void *param); static void stream_smi_write_dma_callback(void *param); void transfer_thread_stop(struct bcm2835_smi_dev_instance *inst); void print_smil_registers(void); - +void print_smil_registers_ext(const char* b); +static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int num_transfers); +static inline void smi_rearm_if_idle(struct bcm2835_smi_dev_instance *i); +static enum hrtimer_restart tx_hr_keepalive(struct hrtimer *t); static struct bcm2835_smi_dev_instance *inst = NULL; @@ -216,91 +238,178 @@ static inline int smi_is_active(struct bcm2835_smi_instance *inst) } /***************************************************************************/ +// static int set_state(smi_stream_state_en new_state) +// { +// int ret = -1; +// unsigned int new_address = calc_address_from_state(new_state); + +// if (inst == NULL) return 0; +// dev_info(inst->dev, "Set STREAMING_STATUS = %d, cur_addr = %d", new_state, new_address); + +// spin_lock(&inst->state_lock); + +// // in any case if we want to change the state +// // then stop the current transfer and update the new state. +// if(new_state != inst->state) +// { +// // Log once per transition to see *who* is causing it +// dev_info(inst->dev, "set_state transition %d -> %d\n", inst->state, new_state); +// dump_stack(); // temporary: shows the callers in dmesg + +// // stop the transter +// spin_unlock(&inst->state_lock); +// transfer_thread_stop(inst); +// spin_lock(&inst->state_lock); + +// if(smi_is_active(inst->smi_inst)) +// { +// spin_unlock(&inst->state_lock); +// return -EAGAIN; +// } + +// // update the state from current state +// inst->state = smi_stream_idle; +// bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + +// ret = 0; +// //now state is idle +// } +// // else if the state is the same, do nothing +// else +// { +// spin_unlock(&inst->state_lock); +// dev_info(inst->dev, "State is the same as before"); +// return 0; +// } + +// // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer +// if(new_state != smi_stream_idle) +// { +// bcm2835_smi_set_address(inst->smi_inst, new_address); + +// if (new_state == smi_stream_tx_channel) +// { +// // remove all data inside the tx_fifo +// if (mutex_lock_interruptible(&inst->write_lock)) +// { +// return -EINTR; +// } +// kfifo_reset(&inst->tx_fifo); +// mutex_unlock(&inst->write_lock); + +// inst->writeable = true; +// wake_up_interruptible(&inst->poll_event); + +// ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback); +// //mb(); +// spin_unlock(&inst->state_lock); + +// // return the success +// return ret; +// } +// else +// { +// ret = transfer_thread_init(inst, DMA_DEV_TO_MEM, stream_smi_read_dma_callback); +// } + +// // if starting the transfer succeeded update the state +// if (!ret) +// { +// inst->state = new_state; +// } +// // if failed, go back to idle +// else +// { +// bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); +// inst->state = smi_stream_idle; +// } +// } +// mb(); // memory barrier to ensure that the state is updated before we return + +// spin_unlock(&inst->state_lock); + +// // return the success +// return ret; +// } + static int set_state(smi_stream_state_en new_state) { - int ret = -1; - unsigned int new_address = calc_address_from_state(new_state); - - if (inst == NULL) return 0; - dev_info(inst->dev, "Set STREAMING_STATUS = %d, cur_addr = %d", new_state, new_address); - - spin_lock(&inst->state_lock); - - // in any case if we want to change the state - // then stop the current transfer and update the new state. - if(new_state != inst->state) - { - // stop the transter - transfer_thread_stop(inst); + int ret = 0; + unsigned int new_address; - if(smi_is_active(inst->smi_inst)) - { - spin_unlock(&inst->state_lock); - return -EAGAIN; - } - - // update the state from current state - inst->state = smi_stream_idle; - bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); - - ret = 0; - //now state is idle - } - // else if the state is the same, do nothing - else - { - spin_unlock(&inst->state_lock); - dev_info(inst->dev, "State is the same as before"); + if (!inst) return 0; + + /* Fast no-op */ + if (new_state == inst->state) { + dev_info(inst->dev, "IOCTL SET_STREAM_STATUS old=%d new=%d (noop)", inst->state, new_state); return 0; } + + dev_info(inst->dev, "set_state transition %d -> %d", inst->state, new_state); + + /* Stop previous transfer outside the spinlock to avoid atomic scheduling warnings */ + if (inst->transfer_thread_running) { + transfer_thread_stop(inst); + } + /* These may sleep; cancel them outside the spinlock too */ + hrtimer_cancel(&inst->tx_hr); + cancel_delayed_work_sync(&inst->tx_watch_work); - // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer - if(new_state != smi_stream_idle) - { - bcm2835_smi_set_address(inst->smi_inst, new_address); + /* Now switch under lock */ + spin_lock(&inst->state_lock); - if (new_state == smi_stream_tx_channel) - { - // remove all data inside the tx_fifo - if (mutex_lock_interruptible(&inst->write_lock)) - { - return -EINTR; - } - kfifo_reset(&inst->tx_fifo); - mutex_unlock(&inst->write_lock); - - inst->writeable = true; - wake_up_interruptible(&inst->poll_event); - - //ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback); - mb(); + /* Put HW into a known idle/address before starting a new direction */ + bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + inst->state = smi_stream_idle; + + new_address = calc_address_from_state(new_state); + bcm2835_smi_set_address(inst->smi_inst, new_address); + + if (new_state == smi_stream_tx_channel) { + /* Reset TX FIFO so we start clean */ + if (mutex_lock_interruptible(&inst->write_lock)) { spin_unlock(&inst->state_lock); - - // return the success - return ret; - } - else - { - ret = transfer_thread_init(inst, DMA_DEV_TO_MEM, stream_smi_read_dma_callback); + return -EINTR; } - - // if starting the transfer succeeded update the state - if (!ret) - { + kfifo_reset(&inst->tx_fifo); + mutex_unlock(&inst->write_lock); + + inst->writeable = true; + wake_up_interruptible(&inst->poll_event); + + /* Start cyclic DMA (TX) */ + ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback); + if (!ret) { + /* Arm a long window right away */ inst->state = new_state; + } else { + /* Failed → stay idle */ + bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); + inst->state = smi_stream_idle; } - // if failed, go back to idle - else - { + } else if (new_state == smi_stream_rx_channel_0 || new_state == smi_stream_rx_channel_1) { + /* Start cyclic DMA (RX) */ + ret = transfer_thread_init(inst, DMA_DEV_TO_MEM, stream_smi_read_dma_callback); + if (!ret) { + /* Same idea for RX: keep it armed long */ + //smi_refresh_dma_command(inst->smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); + inst->state = new_state; + } else { bcm2835_smi_set_address(inst->smi_inst, calc_address_from_state(smi_stream_idle)); inst->state = smi_stream_idle; } + } else { + /* Explicit idle */ + inst->state = smi_stream_idle; } + mb(); - spin_unlock(&inst->state_lock); - - // return the success + /* Start helpers AFTER we've left the spinlock and only if TX started OK */ + if (!ret && new_state == smi_stream_tx_channel) { + schedule_delayed_work(&inst->tx_watch_work, usecs_to_jiffies(inst->tx_watch_period_us)); + hrtimer_start(&inst->tx_hr, inst->tx_hr_period, HRTIMER_MODE_REL_PINNED); + } return ret; } @@ -345,20 +454,124 @@ static int smi_disable_sync(struct bcm2835_smi_instance *smi_inst) } /***************************************************************************/ -static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int num_transfers) +// static void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, int num_transfers) +// { +// int smics_temp = 0; +// print_smil_registers_ext("refresh 1"); +// smics_temp = read_smi_reg(smi_inst, SMICS); +// //write_smi_reg(smi_inst, SMI_TRANSFER_MULTIPLIER*num_transfers, SMIL); //to avoid stopping and restarting +// //print_smil_registers_ext("refresh 2"); + +// // Start the transaction +// //smics_temp = read_smi_reg(smi_inst, SMICS); +// smics_temp |= SMICS_START; +// //smics_temp &= ~(SMICS_PVMODE); +// write_smi_reg(smi_inst, smics_temp, SMICS); +// inst->count_since_refresh = 0; +// print_smil_registers_ext("refresh 3"); +// } + +/* Nudge-only refresh: DO NOT modify SMIL here */ +static inline void smi_refresh_dma_command(struct bcm2835_smi_instance *smi_inst, + int num_transfers) { - int smics_temp = 0; - //print_smil_registers_ext("refresh 1"); - write_smi_reg(smi_inst, SMI_TRANSFER_MULTIPLIER*num_transfers, SMIL); //to avoid stopping and restarting - //print_smil_registers_ext("refresh 2"); + /* Give a long window (N quarters) so DREQ keeps flowing. */ + write_smi_reg(smi_inst, SMI_REFRESH_CHUNKS * num_transfers, SMIL); + + /* START (safe to set repeatedly). */ + u32 smics = read_smi_reg(smi_inst, SMICS); + smics |= SMICS_START; + write_smi_reg(smi_inst, smics, SMICS); + mb(); +} + +/* Read-only watchdog: sample ACTIVE and SMIL, log only on edges/low watermark */ +static void tx_watch_workfn(struct work_struct *ws) +{ + struct delayed_work *dw = container_of(ws, struct delayed_work, work); + struct bcm2835_smi_dev_instance *i = + container_of(dw, struct bcm2835_smi_dev_instance, tx_watch_work); + struct bcm2835_smi_instance *smi = i->smi_inst; + + /* Only watch while we're actually in TX */ + if (READ_ONCE(i->state) == smi_stream_tx_channel) { + + u32 smics = read_smi_reg(smi, SMICS); + bool active = !!(smics & SMICS_ACTIVE); + bool enabled = !!(smics & SMICS_ENABLE); + + if (i->tx_watch_last_active && !active) { + dev_info(i->dev, "ACTIVE→0 (EN=%d) last_smil=%u min_smil=%u\n", + enabled, i->tx_watch_last_smil, i->tx_watch_min_smil); + } + + u32 smil = read_smi_reg(smi, SMIL); + + /* Track minimum SMIL seen while active (before any refresh) */ + if (active) { + if (i->tx_watch_min_smil == 0 || smil < i->tx_watch_min_smil) + i->tx_watch_min_smil = smil; + + /* Log when SMIL gets very small (imminent idle) */ + if (smil <= 512) { + dev_info_ratelimited(i->dev, + "tx_watch: ACTIVE=1, SMIL=%u (near zero)\n", smil); + } + } + + /* Edge: ACTIVE 1 -> 0 (this is the “burst ended” moment) */ + // if (i->tx_watch_last_active && !active) { + // dev_info(i->dev, + // "tx_watch: ACTIVE dropped to 0. Last SMIL=%u, min_smil=%u\n", + // i->tx_watch_last_smil, i->tx_watch_min_smil); + // } + if (i->tx_watch_last_active && !active) { + dev_info(i->dev, + "tx_watch: ACTIVE dropped to 0. Last SMIL=%u, min_smil=%u\n", + i->tx_watch_last_smil, i->tx_watch_min_smil); + /* Immediately re-arm for the next window */ + smi_rearm_if_idle(i); + i->tx_watch_min_smil = 0; + } + + /* Edge: ACTIVE 0 -> 1 (restart happened elsewhere) */ + if (!i->tx_watch_last_active && active) { + dev_info(i->dev, + "tx_watch: ACTIVE rose to 1. SMIL=%u\n", smil); + i->tx_watch_min_smil = 0; /* reset for this active stretch */ + } + + /* Occasionally log state if nothing interesting is happening */ + if ((jiffies & 0x3F) == 0) { /* ~once per 64 jiffies */ + dev_dbg(i->dev, "tx_watch: A=%u SMIL=%u\n", active, smil); + } + + i->tx_watch_last_smil = smil; + i->tx_watch_last_active = active; + } + + /* Re-arm */ + schedule_delayed_work(&i->tx_watch_work, usecs_to_jiffies(i->tx_watch_period_us)); +} + +/* High-resolution periodic keepalive that tops up SMIL while TX is active. */ +static enum hrtimer_restart tx_hr_keepalive(struct hrtimer *t) +{ + struct bcm2835_smi_dev_instance *i = container_of(t, struct bcm2835_smi_dev_instance, tx_hr); - // Start the transaction - smics_temp = read_smi_reg(smi_inst, SMICS); - smics_temp |= SMICS_START; - //smics_temp &= ~(SMICS_PVMODE); - write_smi_reg(smi_inst, smics_temp & 0xffff, SMICS); - inst->count_since_refresh = 0; - //print_smil_registers_ext("refresh 3"); + /* Only run while TX is actually live */ + if (READ_ONCE(i->state) != smi_stream_tx_channel || + !READ_ONCE(i->transfer_thread_running)) + return HRTIMER_NORESTART; + + /* Only do work at the idle boundary */ + if (!smi_is_active(i->smi_inst)) + smi_rearm_if_idle(i); + + + /* Re-arm for the next tick */ + hrtimer_forward_now(t, i->tx_hr_period); + return HRTIMER_RESTART; } /***************************************************************************/ @@ -407,6 +620,7 @@ static int smi_init_programmed_transfer(struct bcm2835_smi_instance *smi_inst, e // Clear the FIFO (reset it to zero contents) write_smi_reg(smi_inst, smics_temp, SMICS); print_smil_registers_ext("init 5"); + mb(); return 0; } @@ -482,13 +696,34 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long break; } //------------------------------- - case SMI_STREAM_IOC_SET_STREAM_STATUS: - { - ret = set_state((smi_stream_state_en)arg); + // case SMI_STREAM_IOC_SET_STREAM_STATUS: + // { + // ret = set_state((smi_stream_state_en)arg); + // break; + // } + + //------------------------------- + case SMI_STREAM_IOC_SET_STREAM_STATUS: + { + smi_stream_state_en req = (smi_stream_state_en)arg; + smi_stream_state_en old = READ_ONCE(inst->state); // snapshot without taking the lock + + if (req == old) { + // Ignore redundant TX->TX (or RX->same RX) requests; they cause noisy re-inits + dev_info_ratelimited(inst->dev, + "IOCTL SET_STREAM_STATUS old=%d new=%d (noop)\n", old, req); + ret = 0; + break; + } + + dev_info_ratelimited(inst->dev, + "IOCTL SET_STREAM_STATUS old=%d new=%d\n", old, req); + ret = set_state(req); break; } - //------------------------------- + + //------------------------------- case SMI_STREAM_IOC_SET_FIFO_MULT: { int temp = (int)arg; @@ -583,103 +818,226 @@ static long smi_stream_ioctl(struct file *file, unsigned int cmd, unsigned long static void stream_smi_read_dma_callback(void *param) { - /* Notify the bottom half that a chunk is ready for user copy */ - struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; + struct bcm2835_smi_dev_instance *inst = param; struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - uint8_t* buffer_pos; - - + uint8_t *buffer_pos; + + /* Top-up only every ~SMI_REFRESH_CHUNKS quarters */ + // if (++inst->count_since_refresh >= (SMI_REFRESH_CHUNKS - SMI_TOPUP_MARGIN)) { + // smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); + // inst->count_since_refresh = 0; + // } + + /* Always ensure SMIL stays well above zero */ smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); - - buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; - buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; - if(kfifo_avail(&inst->rx_fifo) >=DMA_BOUNCE_BUFFER_SIZE/4) - { + + buffer_pos = (uint8_t *)smi_inst->bounce.buffer[0]; + buffer_pos += (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4); + + if (kfifo_avail(&inst->rx_fifo) >= DMA_BOUNCE_BUFFER_SIZE/4) { kfifo_in(&inst->rx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); - } - else - { + } else { inst->counter_missed++; } - - if(!(inst->current_read_chunk % 100 )) - { - dev_info(inst->dev,"init programmed read. missed: %u, sema %u",inst->counter_missed,smi_inst->bounce.callback_sem.count); + + if (!(inst->current_read_chunk % 100)) { + dev_info(inst->dev, "init programmed read. missed:%u, sema %u", + inst->counter_missed, smi_inst->bounce.callback_sem.count); } - + up(&smi_inst->bounce.callback_sem); - inst->readable = true; wake_up_interruptible(&inst->poll_event); inst->current_read_chunk++; } +static inline void smi_kick_if_idle(struct bcm2835_smi_instance *smi_inst) +{ + /* If the SMI just finished a programmed chunk (ACTIVE==0), start the next one. */ + if (!smi_is_active(smi_inst)) { + /* Program a long window for the next run */ + u32 len = (u32)SMI_REFRESH_CHUNKS * (DMA_BOUNCE_BUFFER_SIZE/4); + if (len > 0x00FFFFFF) len = 0x00FFFFFF; /* SMIL is effectively 24-bit */ + write_smi_reg(smi_inst, len, SMIL); + + /* START latches SMIL only when ACTIVE==0 */ + u32 smics = read_smi_reg(smi_inst, SMICS); + smics |= SMICS_START; + write_smi_reg(smi_inst, smics, SMICS); + mb(); + } +} -/***************************************************************************/ -static void stream_smi_check_and_restart(struct bcm2835_smi_dev_instance *inst) +/* Re-arm from a context that continues running even when DMA is paused */ +static inline void smi_rearm_if_idle(struct bcm2835_smi_dev_instance *i) { - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - inst->count_since_refresh++; - if( (inst->count_since_refresh )>= SMI_TRANSFER_MULTIPLIER) - { - int i; - for(i = 0; i < 1000; i++) - { - if(!smi_is_active(smi_inst)) - { - break; - } - udelay(1); - } - if(i == 1000) - { - print_smil_registers_ext("write dma callback error 1000"); - } + struct bcm2835_smi_instance *smi = i->smi_inst; + + if (READ_ONCE(i->state) != smi_stream_tx_channel || + !READ_ONCE(i->transfer_thread_running)) + return; + + if (!smi_is_active(smi)) { + u32 len = (u32)SMI_REFRESH_CHUNKS * (DMA_BOUNCE_BUFFER_SIZE/4); + if (len > 0x00FFFFFF) len = 0x00FFFFFF; + write_smi_reg(smi, len, SMIL); - smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); + u32 smics = read_smi_reg(smi, SMICS); + smics |= SMICS_CLEAR | SMICS_ENABLE | SMICS_WRITE; + + smics |= SMICS_START; + write_smi_reg(smi, smics, SMICS); + mb(); + dev_dbg(i->dev, "rearm: EN=1 WRITE=1 START=1 SMIL=%u\n", len); } } -/***************************************************************************/ +// static inline void smi_kick_if_idle(struct bcm2835_smi_instance *smi_inst) +// { +// /* If the SMI just finished a programmed chunk (ACTIVE==0), start the next one. */ +// if (!smi_is_active(smi_inst)) { +// u32 smics = read_smi_reg(smi_inst, SMICS); +// smics |= SMICS_START; // pulse START; SMIL already holds “one quarter” +// write_smi_reg(smi_inst, smics, SMICS); +// mb(); +// } +// } + +/* Reload SMIL with a long window at the idle boundary and pulse START. */ +// static inline void smi_refresh_at_idle(struct bcm2835_smi_instance *smi_inst, +// int quarters /* e.g. SMI_REFRESH_CHUNKS * (DMA_BOUNCE_BUFFER_SIZE/4) */) +// { +// int i; +// /* Wait briefly for ACTIVE=0 (bounded ~2ms max) */ +// for (i = 0; i < 2000; i++) { +// if (!smi_is_active(smi_inst)) break; +// udelay(1); +// } +// /* Program next window */ +// write_smi_reg(smi_inst, quarters, SMIL); +// /* START is idempotent; safe to set repeatedly */ +// { +// u32 smics = read_smi_reg(smi_inst, SMICS); +// smics |= SMICS_START; +// write_smi_reg(smi_inst, smics, SMICS); +// mb(); +// } +// } + static void stream_smi_write_dma_callback(void *param) { - /* Notify the bottom half that a chunk is ready for user copy */ - struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; + struct bcm2835_smi_dev_instance *inst = param; struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - uint8_t* buffer_pos; - stream_smi_check_and_restart(inst); - - inst->current_read_chunk++; - - buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; - buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; - - if(kfifo_len (&inst->tx_fifo) >= DMA_BOUNCE_BUFFER_SIZE/4) - { - int num_copied = kfifo_out(&inst->tx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); - (void)num_copied; + const size_t q = DMA_BOUNCE_BUFFER_SIZE / 4; + uint8_t *base = (uint8_t *)smi_inst->bounce.buffer[0]; + uint8_t *cur, *prev; + + /* Refill the period that just finished */ + cur = base + q * (inst->current_read_chunk & 3); + prev = base + q * ((inst->current_read_chunk + 3) & 3); + + // if (kfifo_len(&inst->tx_fifo) >= q) { + // (void)kfifo_out(&inst->tx_fifo, cur, q); + // } else { + // /* Producer starved -> repeat previous quarter (or memset to carrier) */ + // memcpy(cur, prev, q); + // inst->counter_missed++; + // } + + if (kfifo_len(&inst->tx_fifo) >= q) { + unsigned int copied = kfifo_out(&inst->tx_fifo, cur, q); + if (copied != q) { + /* producer underrun: pad the remainder (reuse previous or zero) */ + memcpy(cur + copied, prev + copied, q - copied); + inst->counter_missed++; } - else - { + } else { + /* not enough data: repeat previous quarter (or memset to carrier) */ + memcpy(cur, prev, q); inst->counter_missed++; } - - if(!(inst->current_read_chunk % 111 )) - { - dev_info(inst->dev,"init programmed write. missed: %u, sema %u, val %08X",inst->counter_missed,smi_inst->bounce.callback_sem.count,*(uint32_t*) &buffer_pos[0]); + + inst->current_read_chunk++; + + if (!(inst->current_read_chunk % 111)) { + dev_info(inst->dev, "init programmed write. missed:%u, sema %u, val %08X", + inst->counter_missed, smi_inst->bounce.callback_sem.count, + *(u32 *)cur); } - + up(&smi_inst->bounce.callback_sem); - inst->writeable = true; wake_up_interruptible(&inst->poll_event); - } +/***************************************************************************/ +// static void stream_smi_check_and_restart(struct bcm2835_smi_dev_instance *inst) +// { +// struct bcm2835_smi_instance *smi_inst = inst->smi_inst; +// inst->count_since_refresh++; +// if( (inst->count_since_refresh )>= SMI_TRANSFER_MULTIPLIER) +// { +// int i; +// for(i = 0; i < 1000; i++) +// { +// if(!smi_is_active(smi_inst)) +// { +// break; +// } +// udelay(1); +// } +// if(i == 1000) +// { +// print_smil_registers_ext("write dma callback error 1000"); +// } + +// smi_refresh_dma_command(smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); +// } +// } + +/***************************************************************************/ +// static void stream_smi_write_dma_callback(void *param) +// { +// /* Notify the bottom half that a chunk is ready for user copy */ +// struct bcm2835_smi_dev_instance *inst = (struct bcm2835_smi_dev_instance *)param; +// struct bcm2835_smi_instance *smi_inst = inst->smi_inst; +// uint8_t* buffer_pos; +// //stream_smi_check_and_restart(inst); // removed to avoid restarts + +// inst->current_read_chunk++; + +// buffer_pos = (uint8_t*) smi_inst->bounce.buffer[0]; +// buffer_pos = &buffer_pos[ (DMA_BOUNCE_BUFFER_SIZE/4) * (inst->current_read_chunk % 4)]; + +// if(kfifo_len (&inst->tx_fifo) >= DMA_BOUNCE_BUFFER_SIZE/4) +// { +// int num_copied = kfifo_out(&inst->tx_fifo, buffer_pos, DMA_BOUNCE_BUFFER_SIZE/4); +// (void)num_copied; +// } +// else +// { +// inst->counter_missed++; +// } + +// if(!(inst->current_read_chunk % 111 )) +// { +// dev_info(inst->dev,"init programmed write. missed: %u, sema %u, val %08X",inst->counter_missed,smi_inst->bounce.callback_sem.count,*(uint32_t*) &buffer_pos[0]); +// } + +// up(&smi_inst->bounce.callback_sem); + +// inst->writeable = true; +// wake_up_interruptible(&inst->poll_event); + +// } + /***************************************************************************/ static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic( struct bcm2835_smi_instance *inst, enum dma_transfer_direction dir, dma_async_tx_callback callback, void*param) { + + dev_info(inst->dev, "stream_smi_dma_init_cyclic() called for direction %s", + (dir == DMA_DEV_TO_MEM) ? "RX" : "TX"); struct dma_async_tx_descriptor *desc = NULL; //printk(KERN_ERR DRIVER_NAME": SUBMIT_PREP %lu\n", (long unsigned int)(inst->dma_chan)); @@ -687,7 +1045,7 @@ static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic( struct bcm28 inst->bounce.phys[0], DMA_BOUNCE_BUFFER_SIZE, DMA_BOUNCE_BUFFER_SIZE/4, - dir,DMA_PREP_INTERRUPT | DMA_CTRL_ACK | DMA_PREP_FENCE); + dir,DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!desc) { dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); @@ -710,61 +1068,168 @@ static struct dma_async_tx_descriptor *stream_smi_dma_init_cyclic( struct bcm28 * ***************************************************************************/ -int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfer_direction dir, dma_async_tx_callback callback) +static void smi_enable_streaming(struct bcm2835_smi_instance *smi_inst, + enum dma_transfer_direction dir) { - unsigned int errors = 0; - int ret; - int success; - + u32 smics = read_smi_reg(smi_inst, SMICS); + smics |= SMICS_CLEAR | SMICS_ENABLE; + if (dir == DMA_MEM_TO_DEV) smics |= SMICS_WRITE; + write_smi_reg(smi_inst, smics, SMICS); + mb(); +} + +// int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfer_direction dir, dma_async_tx_callback callback) +// { +// unsigned int errors = 0; +// int ret; +// int success; + +// dev_info(inst->dev, "Starting cyclic transfer, dma dir: %d", dir); +// inst->transfer_thread_running = true; + +// /* Disable the peripheral: */ +// if(smi_disable_sync(inst->smi_inst)) +// { +// dev_err(inst->smi_inst->dev, "smi_disable_sync failed"); +// return -1; +// } +// //write_smi_reg(inst->smi_inst, 0, SMIL); +// sema_init(&inst->smi_inst->bounce.callback_sem, 0); + +// spin_lock(&inst->smi_inst->transaction_lock); +// ret = smi_init_programmed_transfer(inst->smi_inst, dir, DMA_BOUNCE_BUFFER_SIZE/4); +// if (ret != 0) +// { +// spin_unlock(&inst->smi_inst->transaction_lock); +// dev_err(inst->smi_inst->dev, "smi_init_programmed_transfer returned %d", ret); +// smi_disable_sync(inst->smi_inst); +// return -2; +// } +// else +// { +// spin_unlock(&inst->smi_inst->transaction_lock); +// } + +// inst->current_read_chunk = 0; +// inst->counter_missed = 0; +// if(!errors) +// { +// struct dma_async_tx_descriptor *desc = NULL; +// struct bcm2835_smi_instance *smi_inst = inst->smi_inst; +// spin_lock(&smi_inst->transaction_lock); +// desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback, inst); + +// if(desc) +// { +// dma_async_issue_pending(smi_inst->dma_chan); +// } +// else +// { +// errors = 1; +// } +// spin_unlock(&smi_inst->transaction_lock); +// } +// smi_refresh_dma_command(inst->smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); +// BUSY_WAIT_WHILE_TIMEOUT(!smi_is_active(inst->smi_inst), 1000000U, success); +// print_smil_registers_ext("post init 0"); +// return errors; +// } + + +int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, + enum dma_transfer_direction dir, + dma_async_tx_callback callback) +{ + int errors = 0; + dev_info(inst->dev, "Starting cyclic transfer, dma dir: %d", dir); - inst->transfer_thread_running = true; - /* Disable the peripheral: */ - if(smi_disable_sync(inst->smi_inst)) - { + /* Ensure clean peripheral */ + if (smi_disable_sync(inst->smi_inst)) { dev_err(inst->smi_inst->dev, "smi_disable_sync failed"); return -1; } - write_smi_reg(inst->smi_inst, 0, SMIL); + + int ret = smi_init_programmed_transfer(inst->smi_inst, dir, DMA_BOUNCE_BUFFER_SIZE/4); + if (ret) dev_warn(inst->dev, "smi_init_programmed_transfer ret=%d (continuing)", ret); + sema_init(&inst->smi_inst->bounce.callback_sem, 0); - + inst->current_read_chunk = 0; + inst->counter_missed = 0; + inst->count_since_refresh = 0; + + /* Prepare cyclic DMA */ spin_lock(&inst->smi_inst->transaction_lock); - ret = smi_init_programmed_transfer(inst->smi_inst, dir, DMA_BOUNCE_BUFFER_SIZE/4); - if (ret != 0) { - spin_unlock(&inst->smi_inst->transaction_lock); - dev_err(inst->smi_inst->dev, "smi_init_programmed_transfer returned %d", ret); - smi_disable_sync(inst->smi_inst); - return -2; + struct dma_async_tx_descriptor *desc = + stream_smi_dma_init_cyclic(inst->smi_inst, dir, callback, inst); + if (!desc) { + dev_err(inst->dev, "DMA init failed: prep_cyclic returned NULL"); + errors = 1; + } else { + dma_async_issue_pending(inst->smi_inst->dma_chan); + } } - else - { - spin_unlock(&inst->smi_inst->transaction_lock); + spin_unlock(&inst->smi_inst->transaction_lock); + if (errors) return -2; + + /* If TX, prefill the 4 periods so DMA has data immediately */ + // if (dir == DMA_MEM_TO_DEV) { + // uint8_t *base = (uint8_t *)inst->smi_inst->bounce.buffer[0]; + // const size_t q = DMA_BOUNCE_BUFFER_SIZE / 4; + // int i; + // for (i = 0; i < 4; i++) { + // if (kfifo_len(&inst->tx_fifo) >= q) { + // (void)kfifo_out(&inst->tx_fifo, base + i * q, q); + // } else { + // memset(base + i * q, 0, q); /* steady I/Q if underrun at start */ + // } + // } + // } + + /* If TX, prefill the 4 periods so DMA has data immediately */ + if (dir == DMA_MEM_TO_DEV) { + uint8_t *base = (uint8_t *)inst->smi_inst->bounce.buffer[0]; + const size_t q = DMA_BOUNCE_BUFFER_SIZE / 4; + + for (int i = 0; i < 4; i++) { + if (kfifo_len(&inst->tx_fifo) >= q) { + unsigned int copied = kfifo_out(&inst->tx_fifo, base + i * q, q); + if (copied != q) { + memset(base + i * q + copied, 0, q - copied); + inst->counter_missed++; + } + } else { + memset(base + i * q, 0, q); /* steady I/Q at start */ + } + } } + + /* Enable SMI and arm a long window */ + smi_enable_streaming(inst->smi_inst, dir); + //#define SMIL_INIT_QUARTERS (SMI_REFRESH_CHUNKS * (DMA_BOUNCE_BUFFER_SIZE/4)) + //const size_t q = DMA_BOUNCE_BUFFER_SIZE / 4; + //write_smi_reg(inst->smi_inst, q, SMIL); + //write_smi_reg(inst->smi_inst, SMI_REFRESH_CHUNKS * q, SMIL); - inst->current_read_chunk = 0; - inst->counter_missed = 0; - if(!errors) - { - struct dma_async_tx_descriptor *desc = NULL; - struct bcm2835_smi_instance *smi_inst = inst->smi_inst; - spin_lock(&smi_inst->transaction_lock); - desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback, inst); + const u32 q = (u32)(DMA_BOUNCE_BUFFER_SIZE / 4); + u32 len = (u32)SMI_REFRESH_CHUNKS * q; /* long window */ + if (len > 0x00FFFFFF) len = 0x00FFFFFF; /* SMIL is ~24-bit */ + write_smi_reg(inst->smi_inst, len, SMIL); - if(desc) - { - dma_async_issue_pending(smi_inst->dma_chan); - } - else - { - errors = 1; - } - spin_unlock(&smi_inst->transaction_lock); - } - smi_refresh_dma_command(inst->smi_inst, DMA_BOUNCE_BUFFER_SIZE/4); - BUSY_WAIT_WHILE_TIMEOUT(!smi_is_active(inst->smi_inst), 1000000U, success); - print_smil_registers_ext("post init 0"); - return errors; + + /* One-time START pulse */ + u32 smics = read_smi_reg(inst->smi_inst, SMICS); + smics |= SMICS_START; + write_smi_reg(inst->smi_inst, smics, SMICS); + mb(); + + + inst->transfer_thread_running = 1; + + dev_info(inst->dev, "smi_init_cyclic_transfer active..."); + print_smil_registers_ext("post init (cyclic)"); + return 0; } /***************************************************************************/ @@ -773,9 +1238,8 @@ void transfer_thread_stop(struct bcm2835_smi_dev_instance *inst) //int errors = 0; //dev_info(inst->dev, "Reader state became idle, terminating dma %u %u", (inst->address_changed) ,errors); print_smil_registers_ext("thread stop 0"); - spin_lock(&inst->smi_inst->transaction_lock); + /* terminate_sync may sleep; do NOT hold a spinlock here */ dmaengine_terminate_sync(inst->smi_inst->dma_chan); - spin_unlock(&inst->smi_inst->transaction_lock); //dev_info(inst->dev, "Reader state became idle, terminating smi transaction"); smi_disable_sync(inst->smi_inst); @@ -926,7 +1390,7 @@ static unsigned int smi_stream_poll(struct file *filp, struct poll_table_struct mask |= ( POLLIN | POLLRDNORM ); } - if (!kfifo_is_full(&inst->rx_fifo)) + if (!kfifo_is_full(&inst->tx_fifo)) { //dev_info(inst->dev, "poll_wait result => writeable=%d", inst->writeable); inst->writeable = false; @@ -1050,7 +1514,7 @@ static int smi_stream_dev_probe(struct platform_device *pdev) } // Create sysfs entries with "smi-stream-dev" - smi_stream_class = class_create(THIS_MODULE, DEVICE_NAME); + smi_stream_class = class_create(DEVICE_NAME); ptr_err = smi_stream_class; if (IS_ERR(ptr_err)) { @@ -1091,8 +1555,19 @@ static int smi_stream_dev_probe(struct platform_device *pdev) mutex_init(&inst->read_lock); mutex_init(&inst->write_lock); spin_lock_init(&inst->state_lock); - - dev_info(inst->dev, "initialised"); + + /* TX watch (read-only): default 1000 us period */ + INIT_DELAYED_WORK(&inst->tx_watch_work, tx_watch_workfn); + inst->tx_watch_period_us = 1000; + inst->tx_watch_last_smil = 0; + inst->tx_watch_last_active = false; + inst->tx_watch_min_smil = 0; + /* TX SMIL keepalive: check ACTIVE frequently so idle gaps are ~eliminated. + Start with 5 µs; you can relax later if stable. */ + hrtimer_init(&inst->tx_hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); + inst->tx_hr.function = tx_hr_keepalive; + inst->tx_hr_period = ktime_set(0, 5 * 1000); /* 5 µs */ + return 0; } @@ -1102,7 +1577,7 @@ static int smi_stream_dev_probe(struct platform_device *pdev) * ***************************************************************************/ -static int smi_stream_dev_remove(struct platform_device *pdev) +static void smi_stream_dev_remove(struct platform_device *pdev) { //if (inst->reader_thread != NULL) kthread_stop(inst->reader_thread); //inst->reader_thread = NULL; @@ -1113,7 +1588,6 @@ static int smi_stream_dev_remove(struct platform_device *pdev) unregister_chrdev_region(smi_stream_devid, 1); dev_info(inst->dev, DRIVER_NAME": smi-stream dev removed"); - return 0; } /**************************************************************************** diff --git a/driver/smi_stream_ioctl.h b/driver/smi_stream_ioctl.h new file mode 100644 index 00000000..278886bd --- /dev/null +++ b/driver/smi_stream_ioctl.h @@ -0,0 +1,25 @@ + +#ifndef __SMI_STREAM_IOCTL_H__ +#define __SMI_STREAM_IOCTL_H__ + +#ifdef __KERNEL__ + #include // u32, etc. +#else + #include // uint32_t +#endif + +// Unique magic number for our ioctl calls (arbitrary, must be unique) +#define SMI_STREAM_IOCTL_MAGIC 's' + +// IOCTL command to read all key SMI registers +#define SMI_IOCTL_READ_REGS _IOR(SMI_STREAM_IOCTL_MAGIC, 0x01, struct smi_registers_t) + +// Struct to carry SMI register values between kernel and user space +struct smi_registers_t { + uint32_t smics; // Control and Status + uint32_t smil; // Length + uint32_t smids; // DMA status + uint32_t smisw0; // Write register 0 +}; + +#endif // __SMI_STREAM_IOCTL_H__ \ No newline at end of file diff --git a/examples/python/soapy_rf_sweep_generator.py b/examples/python/soapy_rf_sweep_generator.py index 495c7090..602f1933 100644 --- a/examples/python/soapy_rf_sweep_generator.py +++ b/examples/python/soapy_rf_sweep_generator.py @@ -77,7 +77,7 @@ def setup_freq_power(sdr, stream, freq_KHz, power=10.0): sdr.setGain(SOAPY_SDR_TX, 0, power+10) def setup_transmitter(sdr, freq_KHz=2304100): - stream = sdr.setupStream(SOAPY_SDR_TX, SOAPY_SDR_CS16, [0], dict(CW="1")) + stream = sdr.setupStream(SOAPY_SDR_TX, SOAPY_SDR_CS16, [0]) setup_freq_power(sdr, stream, freq_KHz) return stream @@ -115,7 +115,7 @@ def main(): #--------------------------------------------- if (event == "Exit" or event == WIN_CLOSED): - break; + break #--------------------------------------------- elif event == "Set Power": diff --git a/firmware/Makefile b/firmware/Makefile index 0386c53d..4b572dce 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -6,7 +6,7 @@ top.bin: yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v #nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc - nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --parallel-refine --opt-timing --seed 16 --timing-allow-fail + nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --parallel-refine --opt-timing --seed 16 --timing-allow-fail --no-promote-globals --report nextpnr_timing.json 2>&1 | tee nextpnr.log icepack $(filename).asc $(filename).bin build: top.bin diff --git a/firmware/complex_fifo.v b/firmware/complex_fifo.v index d4abb290..ea38ec6d 100644 --- a/firmware/complex_fifo.v +++ b/firmware/complex_fifo.v @@ -14,7 +14,7 @@ module complex_fifo #( output reg [2*DATA_WIDTH-1:0] rd_data_o, output reg full_o, - output reg empty_o, + output reg empty_o ); reg [ADDR_WIDTH-1:0] wr_addr; diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h index e610570b..0833f112 100644 --- a/firmware/h-files/cariboulite_fpga_firmware.h +++ b/firmware/h-files/cariboulite_fpga_firmware.h @@ -17,16 +17,16 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2024-04-09 - * Time: 13:13:50 + * Date: 2025-10-04 + * Time: 11:07:28 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 50, - .tm_min = 13, - .tm_hour = 13, - .tm_mday = 9, - .tm_mon = 3, /* +1 */ - .tm_year = 124, /* +1900 */ + .tm_sec = 28, + .tm_min = 7, + .tm_hour = 11, + .tm_mday = 4, + .tm_mon = 9, /* +1 */ + .tm_year = 125, /* +1900 */ }; /* @@ -38,382 +38,382 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x20, 0x01, - 0xE0, 0x01, 0x50, 0x00, 0x00, 0x80, 0x08, 0x00, 0x03, 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0x00, 0x00, 0x00, 0x0C, 0x00, 0x80, 0x22, 0xD9, 0x80, 0x40, 0x11, 0x00, 0x09, 0x09, 0x00, 0x00, + 0x00, 0x2C, 0x00, 0x20, 0x04, 0x00, 0x00, 0x05, 0x00, 0x01, 0x00, 0x20, 0x00, 0x44, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x11, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -421,16 +421,16 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x50, 0x00, 0x54, 0x80, 0x00, 0x00, 0x01, 0x33, 0x02, 0x40, 0x00, 0x05, 0x22, + 0x00, 0x00, 0x0A, 0x00, 0x02, 0x08, 0x80, 0x03, 0xC4, 0x00, 0x05, 0x30, 0x28, 0x40, 0x08, 0xB8, + 0xC0, 0x00, 0xC1, 0x00, 0x00, 0x80, 0x03, 0x80, 0x20, 0x20, 0x10, 0xBC, 0xD0, 0x8F, 0x0C, 0x08, 0x00, 0x00, 0x11, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1165,373 +1165,373 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 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0x80, 0xB4, 0x08, 0x00, 0xA4, 0x0C, 0x80, 0x00, 0x00, 0x01, 0x0D, 0xB7, 0x46, 0x80, + 0x51, 0x00, 0x00, 0x00, 0x0F, 0x0A, 0x00, 0x14, 0x01, 0x20, 0xC3, 0x40, 0x21, 0x00, 0x00, 0x00, + 0x00, 0x0D, 0x00, 0x94, 0x04, 0x5A, 0x06, 0x80, 0x40, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xC1, + 0xD0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x56, 0x5E, 0x28, 0x02, 0x50, 0x00, 0x20, 0x60, 0x80, 0x00, + 0x09, 0x00, 0x87, 0x20, 0x3C, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x18, 0x51, 0x00, 0x0F, 0xF0, + 0x24, 0x03, 0x80, 0x05, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0xC0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20, 0x00, 0x03, 0x25, 0xC0, 0x00, 0x00, + 0x02, 0x80, 0x1C, 0x07, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x09, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x60, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x81, 0x80, 0x00, 0x00, 0x60, 0x70, 0x00, 0x00, 0x09, 0x00, 0x00, 0x01, 0xE0, 0x00, + 0x40, 0x00, 0x00, 0x02, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x50, 0x00, 0x00, 0x00, 0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8B, 0x30, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xA9, 0x58, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/firmware/io_ctrl.v b/firmware/io_ctrl.v index 7fb3af2d..01c44dad 100644 --- a/firmware/io_ctrl.v +++ b/firmware/io_ctrl.v @@ -15,7 +15,7 @@ module io_ctrl input [3:0] i_config, output o_led0, output o_led1, - output [3:0] o_pmod, + //output [3:0] o_pmod, // Analog interfaces output o_mixer_fm, @@ -91,7 +91,7 @@ module io_ctrl //========================================================================= assign o_led0 = led0_state; assign o_led1 = led1_state; - assign o_pmod = pmod_state; + //assign o_pmod = pmod_state; // Analog interfaces assign o_mixer_fm = 1'b0; @@ -113,7 +113,7 @@ module io_ctrl if (i_rst_b == 1'b0) begin debug_mode <= debug_mode_none; rf_mode <= rf_mode_low_power; - led0_state <= 1'b0; + led0_state <= 1'b0; // a marker, to show it is my version of the firmware led1_state <= 1'b0; end else begin if (i_cs == 1'b1) begin @@ -307,4 +307,4 @@ module io_ctrl end end -endmodule // io_ctrl \ No newline at end of file +endmodule // io_ctrl diff --git a/firmware/lvds_tx.v b/firmware/lvds_tx.v index a5d95863..12fc1d70 100644 --- a/firmware/lvds_tx.v +++ b/firmware/lvds_tx.v @@ -1,129 +1,227 @@ module lvds_tx ( input i_rst_b, - input i_ddr_clk, - output reg[1:0] o_ddr_data, - + input i_ddr_clk, input i_fifo_empty, - output o_fifo_read_clk, - output o_fifo_pull, input [31:0] i_fifo_data, input [3:0] i_sample_gap, input i_tx_state, - input i_sync_input, - input i_debug_lb, - output o_tx_state_bit, - output o_sync_state_bit, + input i_debug_lb, + + output reg[1:0] o_ddr_data, + output [2:0] o_tx_fsm_state, + output o_fifo_read_clk, + output o_fifo_pull ); // STATES and PARAMS - localparam - tx_state_sync = 1'b0, - tx_state_tx = 1'b1; localparam sync_duration_frames = 4'd10; // at least 2.5usec localparam zero_frame = 32'b00000000_00000000_00000000_00000000; - localparam lb_frame = 32'b10000100_00000011_01110000_01001000; - + localparam sync_frame = 32'b10000000_00000000_01000000_00000000; + localparam lb_frame = 32'b10000100_00000011_01110000_01001000; + + localparam IDLE = 3'd0; + localparam TX_FRAME = 3'd1; + localparam TX_GAP = 3'd2; + localparam LOOPBACK = 3'd3; + // Internal Registers - reg [3:0] r_sync_count; - wire frame_pull_clock; - wire frame_assign_clock; - reg r_state; - reg [3:0] r_phase_count; - reg [31:0] r_fifo_data; - reg r_pulled; - reg r_schedule_zero_frame; - - // Initial conditions - initial begin - r_phase_count = 4'd15; - r_fifo_data <= zero_frame; - end + reg [3:0] r_sync_count; + reg [3:0] r_phase_count; + reg [2:0] r_state; + reg [31:0] r_fifo_data; + reg r_pulled; + reg [3:0] r_gap_frame_count; + reg pending_load; // set when we asserted rd_en at last boundary + reg sent_first_sync; // gate leaving IDLE until we’ve emitted one sync + reg [3:0] r_sample_gap; // sampled copy of i_sample_gap (CDC-lite) + reg r_tx_state_q; + reg [3:0] next_sync; + wire tx_rise = r_tx_state & ~r_tx_state_q; + wire tx_fall = ~r_tx_state & r_tx_state_q; + + wire frame_boundary = (r_phase_count == 4'd0); + assign o_fifo_read_clk = i_ddr_clk; - assign o_tx_state_bit = r_state; - assign o_sync_state_bit = 1'b0; assign o_fifo_pull = r_pulled; + assign o_tx_fsm_state = r_state; // output current state for debug - // SHIFT REGISTER - always @(posedge i_ddr_clk) begin - if (i_rst_b == 1'b0) begin - r_phase_count <= 4'd15; - end else begin - o_ddr_data[1:0] <= r_fifo_data[2*r_phase_count+1 : 2*r_phase_count]; - r_phase_count <= r_phase_count - 1; - end + reg tx_state_d1, tx_state_d2; + always @(posedge i_ddr_clk or negedge i_rst_b) begin + if (!i_rst_b) {tx_state_d2, tx_state_d1} <= 2'b00; + else {tx_state_d2, tx_state_d1} <= {tx_state_d1, i_tx_state}; + end + wire r_tx_state = tx_state_d2; + + reg debug_lb_d1, debug_lb_d2; + always @(posedge i_ddr_clk or negedge i_rst_b) begin + if (!i_rst_b) {debug_lb_d2, debug_lb_d1} <= 2'b00; + else {debug_lb_d2, debug_lb_d1} <= {debug_lb_d1, i_debug_lb}; end + wire r_debug_lb = debug_lb_d2; - // SYNC AND MANAGEMENT - always @(posedge i_ddr_clk) - begin + reg fifo_empty_d1, fifo_empty_d2; + always @(posedge i_ddr_clk or negedge i_rst_b) begin + if (!i_rst_b) {fifo_empty_d2, fifo_empty_d1} <= 2'b11; + else {fifo_empty_d2, fifo_empty_d1} <= {fifo_empty_d1, i_fifo_empty}; + end + wire r_fifo_empty = fifo_empty_d2; + + // SHIFT REGISTER and STATE MACHINE + always @(posedge i_ddr_clk or negedge i_rst_b) begin if (i_rst_b == 1'b0) begin - r_state <= tx_state_sync; - r_pulled <= 1'b0; - r_fifo_data <= zero_frame; - r_sync_count <= sync_duration_frames; - r_schedule_zero_frame <= 1'b0; + r_phase_count <= 4'd15; + r_sync_count <= sync_duration_frames; + r_fifo_data <= zero_frame; + r_state <= INIT; + r_pulled <= 1'b0; + r_gap_frame_count <= 4'd0; + pending_load <= 1'b0; + sent_first_sync <= 1'b0; + r_sample_gap <= 4'd0; + o_ddr_data <= 2'b00; + r_tx_state_q <= 1'b0; + end else begin - case (r_state) - //---------------------------------------------- - tx_state_sync: - begin - if (r_phase_count == 4'd0) begin - if (r_schedule_zero_frame) begin + + // SHIFT REGISTER + o_ddr_data[1:0] <= r_fifo_data[2*r_phase_count+1 : 2*r_phase_count]; + // case (r_phase_count) + // 15: o_ddr_data[1:0] <= r_fifo_data[31:30]; + // 14: o_ddr_data[1:0] <= r_fifo_data[29:28]; + // 13: o_ddr_data[1:0] <= r_fifo_data[27:26]; + // 12: o_ddr_data[1:0] <= r_fifo_data[25:24]; + // 11: o_ddr_data[1:0] <= r_fifo_data[23:22]; + // 10: o_ddr_data[1:0] <= r_fifo_data[21:20]; + // 9: o_ddr_data[1:0] <= r_fifo_data[19:18]; + // 8: o_ddr_data[1:0] <= r_fifo_data[17:16]; + // 7: o_ddr_data[1:0] <= r_fifo_data[15:14]; + // 6: o_ddr_data[1:0] <= r_fifo_data[13:12]; + // 5: o_ddr_data[1:0] <= r_fifo_data[11:10]; + // 4: o_ddr_data[1:0] <= r_fifo_data[ 9: 8]; + // 3: o_ddr_data[1:0] <= r_fifo_data[ 7: 6]; + // 2: o_ddr_data[1:0] <= r_fifo_data[ 5: 4]; + // 1: o_ddr_data[1:0] <= r_fifo_data[ 3: 2]; + // 0: o_ddr_data[1:0] <= r_fifo_data[ 1: 0]; + // default: o_ddr_data[1:0] <= o_ddr_data[1:0]; // keep the last value + // endcase + + // default: deassert pull unless we decide at boundary + r_pulled <= 1'b0; + r_tx_state_q <= r_tx_state; + + // --- handle everything at frame boundaries --- + if (frame_boundary) begin + // sample config (cheap CDC – OK for slow register writes) + r_sample_gap <= i_sample_gap; + + // handoff the FIFO data one boundary after we pulled it + if (pending_load) begin + r_fifo_data <= i_fifo_data; + pending_load <= 1'b0; + end + + // idle cadence counter rolls 9→...→0 then reloads to 10 + //r_sync_count <= (r_sync_count == 4'd0) ? sync_duration_frames : (r_sync_count - 1'b1); + + // If TX is off, require a new sync burst before leaving IDLE next time + //if (!r_tx_state) sent_first_sync <= 1'b0; + + // default next value for the idle cadence + next_sync = (r_sync_count == 4'd0) ? sync_duration_frames : (r_sync_count - 1'b1); + + // On TX disable: re-arm preamble and kill any pending load + if (tx_fall) begin + sent_first_sync <= 1'b0; // must see a fresh sync before leaving IDLE + pending_load <= 1'b0; // cancel staged FIFO handoff + next_sync <= 4'd1; // schedule: one zero frame then a sync soon + // optional: realign the shifter to a frame boundary + // r_phase_count <= 4'd15; + end + + // On TX enable: ensure a quick sync + if (tx_rise) begin + next_sync <= 4'd1; // zero frame, then sync + end + + r_sync_count <= next_sync; + + // STATE MACHINE + case (r_state) + //---------------------------// + IDLE: begin + // emit idle pattern + if (r_sync_count == 4'd0) begin + r_fifo_data <= sync_frame; + sent_first_sync <= 1'b1; + end else begin r_fifo_data <= zero_frame; - r_schedule_zero_frame <= 1'b0; end - end else if (r_phase_count == 4'd1) begin - if (r_sync_count == 4'd0) begin - if (i_debug_lb && !i_tx_state) begin - r_fifo_data <= lb_frame; - r_state <= tx_state_sync; - end else if (!i_debug_lb && i_tx_state) begin - r_pulled <= !i_fifo_empty; - r_state <= tx_state_tx; + + // only leave IDLE after first sync and with data ready + if (!r_debug_lb && r_tx_state && sent_first_sync && !r_fifo_empty) begin + r_pulled <= 1'b1; // request next word now + pending_load <= 1'b1; // latch it next boundary + if (r_sample_gap == 4'd0) begin + r_state <= TX_FRAME; end else begin - r_sync_count <= sync_duration_frames; - r_state <= tx_state_sync; - r_fifo_data <= zero_frame; + r_state <= TX_GAP; + r_gap_frame_count <= r_sample_gap - 1'b1; + end + end else if (r_debug_lb) begin + r_state <= LOOPBACK; + end + end + + //---------------------------// + TX_FRAME: begin + // currently outputting a data frame (loaded last boundary) + if (r_sample_gap == 4'd0) begin + if (r_tx_state && !r_debug_lb && !r_fifo_empty) begin + r_pulled <= 1'b1; + pending_load <= 1'b1; // pipeline next data frame + r_state <= TX_FRAME; + end else begin + r_fifo_data <= zero_frame; // ensure immediate return-to-idle zeros + r_state <= IDLE; // back to idle/sync end end else begin - r_sync_count <= r_sync_count - 1; - r_schedule_zero_frame <= 1'b1; - //r_fifo_data <= zero_frame; - r_state <= tx_state_sync; + r_state <= TX_GAP; // schedule gaps after this data frame + r_gap_frame_count <= r_sample_gap - 1'b1; end end - end - //---------------------------------------------- - tx_state_tx: - begin - if (i_debug_lb || !i_tx_state) begin - r_state <= tx_state_sync; - r_sync_count <= sync_duration_frames; - r_pulled <= 1'b0; - end else if (r_phase_count == 4'd1) begin - r_pulled <= !i_fifo_empty; - r_state <= tx_state_tx; - end else if (r_phase_count == 4'd0) begin - if (r_pulled == 1'b0) begin - r_sync_count <= sync_duration_frames; - r_fifo_data <= zero_frame; - r_state <= tx_state_sync; + //---------------------------// + TX_GAP: begin + // emit zero frames during the gap + r_fifo_data <= zero_frame; + if (r_gap_frame_count != 0) begin + r_gap_frame_count <= r_gap_frame_count - 1'b1; end else begin - r_fifo_data <= i_fifo_data; - if (i_sample_gap > 0) begin - r_sync_count <= i_sample_gap; - r_state <= tx_state_sync; + if (r_tx_state && !r_debug_lb && !r_fifo_empty) begin + r_pulled <= 1'b1; + pending_load <= 1'b1; + r_state <= TX_FRAME; end else begin - r_state <= tx_state_tx; + r_state <= IDLE; end end - - r_pulled <= 1'b0; end - end - endcase - end - end + //---------------------------// + LOOPBACK: begin + r_fifo_data <= lb_frame; + if (!r_debug_lb) r_state <= IDLE; + end + //---------------------------// + // other states go below + + // other states go above + default: r_state <= IDLE; + endcase + end + + // free-running phase counter (wrap 0→15) + r_phase_count <= r_phase_count - 1'b1; + end // phase loop + end // always blobk endmodule diff --git a/firmware/smi_ctrl.v b/firmware/smi_ctrl.v index b7d0052d..d4e0fc0b 100644 --- a/firmware/smi_ctrl.v +++ b/firmware/smi_ctrl.v @@ -3,8 +3,8 @@ module smi_ctrl input i_rst_b, input i_sys_clk, // FPGA Clock - input [4:0] i_ioc, - input [7:0] i_data_in, + input [4:0] i_ioc, + input [7:0] i_data_in, output reg [7:0] o_data_out, input i_cs, input i_fetch_cmd, @@ -12,7 +12,7 @@ module smi_ctrl // FIFO INTERFACE output o_rx_fifo_pull, - input [31:0] i_rx_fifo_pulled_data, + input [31:0] i_rx_fifo_pulled_data, input i_rx_fifo_empty, output o_tx_fifo_push, @@ -24,7 +24,7 @@ module smi_ctrl input i_smi_soe_se, input i_smi_swe_srw, output reg [7:0] o_smi_data_out, - input [7:0] i_smi_data_in, + input [7:0] i_smi_data_in, output o_smi_read_req, output o_smi_write_req, output o_channel, @@ -33,239 +33,229 @@ module smi_ctrl // TX CONDITIONAL output reg o_cond_tx, - output wire [1:0] o_state); + output wire [1:0] o_state +); // --------------------------------- - // MODULE SPECIFIC IOC LIST // --------------------------------- - localparam - ioc_module_version = 5'b00000, // read only - ioc_fifo_status = 5'b00001, // read-only - ioc_channel_select = 5'b00010, - ioc_dir_select = 5'b00011; + localparam ioc_module_version = 5'b00000; // read only + localparam ioc_fifo_status = 5'b00001; // read-only + localparam ioc_channel_select = 5'b00010; + localparam ioc_dir_select = 5'b00011; - // --------------------------------- - // MODULE SPECIFIC PARAMS - // --------------------------------- - localparam - module_version = 8'b00000001; + localparam [7:0] module_version = 8'b00000001; // --------------------------------------- - // MODULE CONTROL + // CONTROL REGISTERS // --------------------------------------- + reg r_channel, r_dir; + assign o_channel = r_channel; - assign o_dir = r_dir; - always @(posedge i_sys_clk or negedge i_rst_b) - begin - if (i_rst_b == 1'b0) begin - r_dir <= 1'b0; - r_channel <= 1'b0; - end else begin - if (i_cs == 1'b1) begin - //============================================= - // READ OPERATIONS - //============================================= - if (i_fetch_cmd == 1'b1) begin - case (i_ioc) - //---------------------------------------------- - ioc_module_version: o_data_out <= module_version; // Module Version + assign o_dir = r_dir; - //---------------------------------------------- - ioc_fifo_status: begin - o_data_out[0] <= i_rx_fifo_empty; - o_data_out[1] <= i_tx_fifo_full; - o_data_out[2] <= r_channel; - o_data_out[3] <= 1'b0; - o_data_out[4] <= r_dir; - o_data_out[7:4] <= 3'b000; - end - endcase - end - //============================================= - // WRITE OPERATIONS - //============================================= - else if (i_load_cmd == 1'b1) begin - case (i_ioc) - //---------------------------------------------- - ioc_channel_select: begin - r_channel <= i_data_in[0]; - end - //---------------------------------------------- - ioc_dir_select: begin - r_dir <= i_data_in[0]; - end - endcase - end + always @(posedge i_sys_clk or negedge i_rst_b) begin + if (!i_rst_b) begin + r_dir <= 1'b0; + r_channel <= 1'b0; + o_data_out <= 8'h00; + end else if (i_cs) begin + // READ + if (i_fetch_cmd) begin + case (i_ioc) + ioc_module_version: o_data_out <= module_version; + ioc_fifo_status: begin + o_data_out[0] <= i_rx_fifo_empty; + o_data_out[1] <= i_tx_fifo_full; + o_data_out[2] <= r_channel; + o_data_out[3] <= 1'b0; + o_data_out[4] <= r_dir; + o_data_out[7:5] <= 3'b000; + end + default: o_data_out <= 8'h00; + endcase + end + // WRITE + else if (i_load_cmd) begin + case (i_ioc) + ioc_channel_select: r_channel <= i_data_in[0]; + ioc_dir_select: r_dir <= i_data_in[0]; + default: ; // no-op + endcase end end end - // --------------------------------------- - // RX SIDE + // RX SIDE (FPGA -> Pi) -- original semantics kept // --------------------------------------- - reg [4:0] int_cnt_rx; - reg [7:0] r_smi_test_count; - reg r_fifo_pull; - reg r_fifo_pull_1; - wire w_fifo_pull_trigger; - reg r_channel; - reg r_dir; + reg [4:0] int_cnt_rx; // 0,8,16,24 wrap + reg r_fifo_pull, r_fifo_pull_1; + reg w_fifo_pull_trigger; // pulse on 2nd byte reg [31:0] r_fifo_pulled_data; - wire soe_and_reset; - assign soe_and_reset = i_rst_b & i_smi_soe_se; - assign o_smi_read_req = (!i_rx_fifo_empty); + wire soe_and_reset = i_rst_b & i_smi_soe_se; + + // Host can read whenever FIFO not empty (unchanged) + assign o_smi_read_req = !i_rx_fifo_empty; + + // Make a single-cycle rd_en in sys domain using the 2-FF edge detect assign o_rx_fifo_pull = !r_fifo_pull_1 && r_fifo_pull && !i_rx_fifo_empty; - always @(negedge soe_and_reset) - begin - if (i_rst_b == 1'b0) begin - int_cnt_rx <= 5'd0; - r_smi_test_count <= 8'h56; - r_fifo_pulled_data <= 32'h00000000; + // Byte emit on SOE falling edge; request next word while sending byte#1 + always @(negedge soe_and_reset or negedge i_rst_b) begin + if (!i_rst_b) begin + int_cnt_rx <= 5'd0; + r_fifo_pulled_data <= 32'h0000_0000; + o_smi_data_out <= 8'h00; + w_fifo_pull_trigger<= 1'b0; end else begin - // trigger the fifo pulling on the second byte + // trigger FIFO pull on the *second* byte (int_cnt_rx==8) w_fifo_pull_trigger <= (int_cnt_rx == 5'd8); - int_cnt_rx <= int_cnt_rx + 8; - o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx]; - - // update the internal register as soon as we reach the fourth byte - if (int_cnt_rx == 5'd24) begin + // drive current byte LSB->MSB order + o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx +: 8]; + + // latch next 32b word right after sending the 4th byte (24) + if (int_cnt_rx == 5'd24) r_fifo_pulled_data <= i_rx_fifo_pulled_data; - end + + // advance byte index: 0,8,16,24, wrap by 5b overflow + int_cnt_rx <= int_cnt_rx + 5'd8; end end - always @(posedge i_sys_clk) - begin - if (i_rst_b == 1'b0) begin - r_fifo_pull <= 1'b0; + // sync the pull trigger into sys clock and form a 1-cycle pulse + always @(posedge i_sys_clk or negedge i_rst_b) begin + if (!i_rst_b) begin + r_fifo_pull <= 1'b0; r_fifo_pull_1 <= 1'b0; end else begin - r_fifo_pull <= w_fifo_pull_trigger; + r_fifo_pull <= w_fifo_pull_trigger; r_fifo_pull_1 <= r_fifo_pull; end end - // ----------------------------------------- - // TX SIDE - // ----------------------------------------- - localparam - tx_state_first = 2'b00, - tx_state_second = 2'b01, - tx_state_third = 2'b10, - tx_state_fourth = 2'b11; +// ----------------------------------------- +// TX SIDE (Pi -> FPGA -> TX FIFO) — compact +// ----------------------------------------- +localparam [1:0] tx_b0 = 2'd0, tx_b1 = 2'd1, tx_b2 = 2'd2, tx_b3 = 2'd3; - reg [12:0] int_cnt_tx; - reg [31:0] r_fifo_pushed_data; - reg [1:0] tx_reg_state; - reg modem_tx_ctrl; - reg cond_tx_ctrl; - reg r_fifo_push; - reg r_fifo_push_1; - wire w_fifo_push_trigger; - wire swe_and_reset; - - assign o_smi_write_req = !i_tx_fifo_full; - assign o_tx_fifo_push = !r_fifo_push_1 && r_fifo_push && !i_tx_fifo_full; - assign swe_and_reset = i_rst_b & i_smi_swe_srw; - assign o_tx_fifo_clock = i_sys_clk; - assign o_state = tx_reg_state; +// Board uses active-low SWE on the pin. +// Normalize so that "asserted" = 1 regardless of pin polarity. +parameter SWE_ACTIVE_HIGH = 0; // 0 = active-low on the pin +wire swe_in_norm = SWE_ACTIVE_HIGH ? i_smi_swe_srw // active-high: use as-is + : ~i_smi_swe_srw; // active-low: invert → asserted=1 - always @(negedge swe_and_reset) - begin - if (i_rst_b == 1'b0) begin - tx_reg_state <= tx_state_first; - w_fifo_push_trigger <= 1'b0; - r_fifo_pushed_data <= 32'h00000000; - modem_tx_ctrl <= 1'b0; - cond_tx_ctrl <= 1'b0; - - // DEBUG - int_cnt_tx <= 0; - // END_DEBUG +assign o_smi_write_req = !i_tx_fifo_full; +assign o_tx_fifo_clock = i_sys_clk; - end else begin - case (tx_reg_state) - //---------------------------------------------- - tx_state_first: - begin - if (i_smi_data_in[7] == 1'b1) begin - r_fifo_pushed_data[31:30] <= 2'b10; - modem_tx_ctrl <= i_smi_data_in[6]; - cond_tx_ctrl <= i_smi_data_in[5]; - r_fifo_pushed_data[29:25] <= i_smi_data_in[4:0]; - tx_reg_state <= tx_state_second; - w_fifo_push_trigger <= 1'b0; - end else begin - // if from some reason we are in the first byte stage and we got - // a byte without '1' on its MSB, that means that we are not synced - // so push a "sync" word into the modem. - cond_tx_ctrl <= 1'b0; - modem_tx_ctrl <= 1'b0; - o_tx_fifo_pushed_data <= 32'h00000000; - w_fifo_push_trigger <= 1'b1; +// 2-FF synchronize the normalized SWE, then edge-detect. +// We want to sample on the end of assertion: +// - physical active-low: rising edge on the pin +// - normalized (asserted=1): falling edge (1→0) +reg swe_q1, swe_q2, swe_q2_d; +always @(posedge i_sys_clk or negedge i_rst_b) begin + if (!i_rst_b) begin + swe_q1 <= 1'b0; + swe_q2 <= 1'b0; + swe_q2_d <= 1'b0; + end else begin + swe_q1 <= swe_in_norm; + swe_q2 <= swe_q1; + swe_q2_d <= swe_q2; + end +end + +// Falling edge of normalized SWE = end-of-byte strobe +wire swe_edge = (swe_q2_d & ~swe_q2); // 1->0 on swe_in_norm + + +// Resync 8-bit bus (2FF) and snapshot once per byte at swe_edge +reg [7:0] d_q1, d_q2, d_q3, d_byte; +always @(posedge i_sys_clk) begin + d_q1 <= i_smi_data_in; + d_q2 <= d_q1; + d_q3 <= d_q2; + if (swe_edge) d_byte <= d_q3; +end + +// Compact collector: shift register + 2-bit byte counter +reg [31:0] frame_sr; // {b3,b2,b1,b0} after 4 edges +reg [1:0] byte_ix; // 0..3 +reg push_req; +reg push_pulse; + +assign o_tx_fifo_push = push_pulse; + +// pack & push when allowed +always @(posedge i_sys_clk or negedge i_rst_b) begin + if (!i_rst_b) begin + frame_sr <= 32'h0; + byte_ix <= 2'd0; + o_tx_fifo_pushed_data <= 32'h0; + o_cond_tx <= 1'b0; + push_req <= 1'b0; + push_pulse <= 1'b0; + end else begin + push_pulse <= 1'b0; + + if (push_req && !i_tx_fifo_full) begin + push_pulse <= 1'b1; + push_req <= 1'b0; + end + + if (swe_edge) begin + // place next byte into the shift register + case (byte_ix) + tx_b0: begin + frame_sr[7:0] <= d_byte; // b0 + // require SOF = 1 in b0[7]; else immediately push fallback + if (d_byte[7]) byte_ix <= tx_b1; + else begin + //o_tx_fifo_pushed_data <= 32'h8000_4000; // fallback "quiet" + push_req <= 1'b1; + byte_ix <= tx_b0; end end - //---------------------------------------------- - tx_state_second: - begin - if (i_smi_data_in[7] == 1'b0) begin - r_fifo_pushed_data[24:18] <= i_smi_data_in[6:0]; - tx_reg_state <= tx_state_third; - end else begin - tx_reg_state <= tx_state_first; - end - w_fifo_push_trigger <= 1'b0; + tx_b1: begin + frame_sr[15:8] <= d_byte; // b1 + if (!d_byte[7]) byte_ix <= tx_b2; + else byte_ix <= tx_b0; // resync end - //---------------------------------------------- - tx_state_third: - begin - if (i_smi_data_in[7] == 1'b0) begin - r_fifo_pushed_data[17] <= i_smi_data_in[6]; - r_fifo_pushed_data[16] <= modem_tx_ctrl; - r_fifo_pushed_data[15:14] <= 2'b01; - r_fifo_pushed_data[13:8] <= i_smi_data_in[5:0]; - tx_reg_state <= tx_state_fourth; - end else begin - tx_reg_state <= tx_state_first; - end - w_fifo_push_trigger <= 1'b0; + tx_b2: begin + frame_sr[23:16] <= d_byte; // b2 + if (!d_byte[7]) byte_ix <= tx_b3; + else byte_ix <= tx_b0; // resync end - //---------------------------------------------- - tx_state_fourth: - begin - if (i_smi_data_in[7] == 1'b0) begin - o_tx_fifo_pushed_data <= {r_fifo_pushed_data[31:8], i_smi_data_in[6:0], 1'b0}; - - //o_tx_fifo_pushed_data <= {i_smi_data_in[6:0], 1'b0, r_fifo_pushed_data[15:8], r_fifo_pushed_data[23:16], r_fifo_pushed_data[31:24]}; - o_tx_fifo_pushed_data <= {2'b10, int_cnt_tx, 1'b1, 2'b01, 13'h3F, 1'b0}; - int_cnt_tx <= int_cnt_tx + 512; - - w_fifo_push_trigger <= 1'b1; - o_cond_tx <= cond_tx_ctrl; + tx_b3: begin + frame_sr[31:24] <= d_byte; // b3 + // full frame captured: require b3[7]==0 + if (!d_byte[7] && frame_sr[7] && !frame_sr[15] && !frame_sr[23]) begin + // bytes now: b0=frame_sr[7:0], b1=frame_sr[15:8], + // b2=frame_sr[23:16], b3=frame_sr[31:24] + // I = {b0[4:0], b1[6:0], b2[6]} + // Q = {b2[5:0], b3[6:0]} + o_tx_fifo_pushed_data <= { + 2'b10, + frame_sr[4:0], frame_sr[14:8], frame_sr[22], // I[12:0] + 1'b1, // TX_EN held high + 2'b01, + frame_sr[21:16], d_byte[6:0], // Q[12:0] + 1'b0 + }; + //push_req <= 1'b1; end else begin - o_tx_fifo_pushed_data <= 32'h00000000; - w_fifo_push_trigger <= 1'b0; + //o_tx_fifo_pushed_data <= 32'h8000_4000; // fallback end - tx_reg_state <= tx_state_first; + push_req <= 1'b1; + byte_ix <= tx_b0; end endcase end end - - always @(posedge i_sys_clk) - begin - if (i_rst_b == 1'b0) begin - r_fifo_push <= 1'b0; - r_fifo_push_1 <= 1'b0; - end else begin - r_fifo_push <= w_fifo_push_trigger; - r_fifo_push_1 <= r_fifo_push; - end - end +end +// SMI write request mirrors FIFO backpressure +assign o_smi_write_req = !i_tx_fifo_full; -endmodule // smi_ctrl \ No newline at end of file +endmodule \ No newline at end of file diff --git a/firmware/sys_ctrl.v b/firmware/sys_ctrl.v index 10de7e65..618907ac 100644 --- a/firmware/sys_ctrl.v +++ b/firmware/sys_ctrl.v @@ -11,9 +11,9 @@ module sys_ctrl input i_load_cmd, // controls output - output o_debug_fifo_push, - output o_debug_fifo_pull, - output o_debug_smi_test, + //output o_debug_fifo_push, + //output o_debug_fifo_pull, + //output o_debug_smi_test, output o_debug_loopback_tx, output [3:0] o_tx_sample_gap, @@ -25,7 +25,7 @@ module sys_ctrl output o_rx_sync_09, output o_rx_sync_24, output o_tx_sync_09, - output o_tx_sync_24, + output o_tx_sync_24 ); // MODULE SPECIFIC IOC LIST @@ -64,9 +64,9 @@ module sys_ctrl reg tx_sync_09; reg tx_sync_24; - assign o_debug_fifo_push = debug_fifo_push; - assign o_debug_fifo_pull = debug_fifo_pull; - assign o_debug_smi_test = debug_smi_test; + //assign o_debug_fifo_push = debug_fifo_push; + //assign o_debug_fifo_pull = debug_fifo_pull; + //assign o_debug_smi_test = debug_smi_test; assign o_rx_sync_type09 = rx_sync_type09; assign o_tx_sync_type09 = tx_sync_type09; assign o_rx_sync_type24 = rx_sync_type24; @@ -151,4 +151,4 @@ module sys_ctrl end end -endmodule // sys_ctrl \ No newline at end of file +endmodule // sys_ctrl diff --git a/firmware/top.asc b/firmware/top.asc index f5d712b6..2d7a528d 100644 --- a/firmware/top.asc +++ b/firmware/top.asc @@ -40,7 +40,7 @@ 000000000000000000 000000000000000000 000000000000000000 -000000000000000000 +000000000001100000 000000000000000000 000000000000000000 000100000000000000 @@ -57,83 +57,83 @@ .io_tile 4 0 000000000000000010 000000000000000000 -000000000000000000 -000000000000000001 -000010000001010001 -000011110011010000 +000010000000000000 +000010110000000001 +000000000001110001 +000000000011110000 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lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 80 $PACKER_VCC_NET +.sym 82 $PACKER_VCC_NET +.sym 85 lvds_tx_inst.frame_boundary +.sym 123 smi_ctrl_ins.d_byte[5] +.sym 177 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[2] +.sym 178 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 179 lvds_tx_inst.r_fifo_data[31] +.sym 180 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 181 lvds_tx_inst.r_fifo_data[6] +.sym 182 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E +.sym 183 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 184 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] +.sym 186 rx_fifo.rd_addr[8] +.sym 204 w_smi_data_direction +.sym 209 i_rst_b_SB_LUT4_I3_O +.sym 243 i_rst_b_SB_LUT4_I3_O +.sym 256 w_rx_fifo_pull +.sym 291 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 292 lvds_tx_inst.r_fifo_data[15] +.sym 293 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[1] +.sym 294 lvds_tx_inst.r_fifo_data[16] +.sym 295 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 296 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 297 lvds_tx_inst.r_fifo_data[5] +.sym 298 lvds_tx_inst.r_fifo_data[7] +.sym 318 w_tx_fifo_pulled_data[13] +.sym 323 i_rst_b_SB_LUT4_I3_O +.sym 325 smi_ctrl_ins.frame_sr[16] +.sym 331 w_tx_fifo_pulled_data[8] +.sym 334 w_tx_fsm_state[0] +.sym 336 w_tx_fsm_state[0] +.sym 339 w_tx_fifo_pulled_data[6] +.sym 347 lvds_tx_inst.frame_boundary +.sym 370 w_tx_fifo_pulled_data[4] +.sym 406 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 407 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 408 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 409 lvds_tx_inst.tx_state_d1 +.sym 410 lvds_tx_inst.r_tx_state_q +.sym 411 w_tx_fifo_pull +.sym 412 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 416 r_counter +.sym 434 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 437 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 440 w_tx_fifo_pulled_data[7] +.sym 442 w_tx_fsm_state[0] +.sym 451 w_tx_fsm_state[1] +.sym 453 lvds_tx_inst.frame_boundary +.sym 460 w_tx_fifo_pulled_data[5] +.sym 480 smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E +.sym 481 smi_ctrl_ins.frame_sr[12] +.sym 484 lvds_tx_inst.r_fifo_data[14] +.sym 492 $PACKER_GND_NET +.sym 493 $PACKER_VCC_NET +.sym 497 $PACKER_VCC_NET +.sym 498 $PACKER_GND_NET .sym 500 $PACKER_VCC_NET -.sym 505 $PACKER_VCC_NET -.sym 514 iq_tx_n_OUTPUT_CLK -.sym 515 lvds_clock -.sym 519 rx_fifo.mem_q.0.1_WDATA_3 -.sym 520 rx_fifo.mem_q.0.2_WDATA_1 -.sym 521 w_rx_24_fifo_data[15] -.sym 522 w_rx_24_fifo_data[11] -.sym 523 rx_fifo.mem_q.0.2_WDATA -.sym 524 w_rx_24_fifo_data[6] -.sym 525 w_rx_24_fifo_data[13] -.sym 526 w_rx_24_fifo_data[9] -.sym 555 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 561 $PACKER_VCC_NET -.sym 633 w_rx_24_fifo_data[7] -.sym 634 w_rx_24_fifo_data[2] -.sym 636 iq_tx_n_OUTPUT_CLK -.sym 637 w_rx_24_fifo_data[5] -.sym 638 rx_fifo.mem_q.0.1_WDATA_1 -.sym 639 w_rx_24_fifo_data[3] -.sym 640 w_rx_24_fifo_data[4] -.sym 679 rx_fifo.mem_q.0.1_WDATA_3 -.sym 714 iq_tx_n_OUTPUT_CLK -.sym 746 w_rx_09_fifo_data[5] -.sym 747 w_rx_09_fifo_data[30] -.sym 748 w_rx_09_fifo_data[4] -.sym 749 rx_fifo.mem_q.0.0_WDATA -.sym 750 w_rx_09_fifo_data[2] -.sym 751 rx_fifo.mem_q.0.0_WDATA_2 -.sym 752 w_rx_09_fifo_data[3] -.sym 753 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 766 rx_fifo.mem_i.0.3_WDATA_2 -.sym 779 lvds_clock -.sym 781 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 787 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 790 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 798 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 816 iq_tx_n_OUTPUT_CLK -.sym 826 lvds_clock -.sym 829 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 830 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 851 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 863 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 864 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 865 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 866 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 867 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 895 rx_fifo.mem_q.0.0_WDATA -.sym 899 rx_fifo.mem_q.0.0_WDATA_2 -.sym 916 w_rx_09_fifo_data[0] +.sym 502 lvds_clock_buf +.sym 504 $PACKER_VCC_NET +.sym 507 $PACKER_GND_NET +.sym 516 $PACKER_VCC_NET +.sym 519 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 520 lvds_tx_inst.r_fifo_data[26] +.sym 521 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 522 lvds_tx_inst.r_fifo_data[11] +.sym 523 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 524 lvds_tx_inst.r_fifo_data[17] +.sym 525 lvds_tx_inst.r_fifo_data[25] +.sym 526 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 528 rx_fifo.wr_addr[8] +.sym 537 w_tx_fifo_pulled_data[17] +.sym 538 w_tx_fifo_pull +.sym 546 w_tx_fifo_pulled_data[29] +.sym 551 rx_fifo.wr_addr[3] +.sym 564 $PACKER_GND_NET +.sym 569 lvds_tx_inst.frame_boundary +.sym 578 w_tx_fifo_pull +.sym 594 $PACKER_VCC_NET +.sym 597 r_counter +.sym 598 $PACKER_VCC_NET +.sym 633 iq_tx_p_D_OUT_1 +.sym 634 lvds_rx_09_inst.r_sync_input +.sym 635 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[3] +.sym 636 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[2] +.sym 637 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[2] +.sym 638 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[0] +.sym 639 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] +.sym 640 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[2] +.sym 641 w_rx_24_fifo_data[15] +.sym 642 w_tx_fsm_state[0] +.sym 661 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 673 w_tx_fifo_pulled_data[11] +.sym 675 w_tx_fifo_pulled_data[0] +.sym 676 w_tx_fifo_pulled_data[25] +.sym 678 w_tx_fifo_pulled_data[20] +.sym 746 w_rx_fifo_full +.sym 748 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 749 w_lvds_tx_d1 +.sym 750 lvds_tx_inst.fifo_empty_d2 +.sym 751 lvds_tx_inst.fifo_empty_d1 +.sym 752 w_lvds_tx_d0 +.sym 756 w_smi_data_direction +.sym 771 w_rx_sync_09 +.sym 777 lvds_rx_09_inst.r_sync_input +.sym 778 w_tx_data_smi[1] +.sym 779 w_lvds_rx_09_d0 +.sym 781 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 787 w_rx_sync_type_09 +.sym 809 iq_tx_p_D_OUT_1 +.sym 821 i_rst_b_SB_LUT4_I3_O +.sym 824 i_rst_b_SB_LUT4_I3_O +.sym 826 w_lvds_rx_09_d0 +.sym 828 iq_tx_p_D_OUT_1 +.sym 860 w_lvds_tx_d1 +.sym 861 tx_fifo.rd_addr[5] +.sym 862 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 863 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 864 tx_fifo.rd_addr[4] +.sym 865 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 866 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 893 tx_wr_en +.sym 897 lvds_tx_inst.fifo_empty_d2 +.sym 915 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] .sym 917 $PACKER_VCC_NET +.sym 935 w_rx_fifo_full +.sym 936 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] .sym 940 lvds_clock .sym 941 $PACKER_VCC_NET -.sym 944 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 961 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] -.sym 975 w_rx_24_fifo_data[1] -.sym 976 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 977 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] -.sym 980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 982 i_sck$SB_IO_IN -.sym 994 rx_fifo.wr_addr[5] -.sym 1000 rx_fifo.wr_addr[7] -.sym 1053 rx_fifo.wr_addr[8] -.sym 1054 lvds_clock -.sym 1061 $PACKER_GND_NET -.sym 1062 $PACKER_GND_NET -.sym 1066 $PACKER_VCC_NET -.sym 1067 $PACKER_VCC_NET +.sym 944 lvds_clock +.sym 970 lvds_clock +.sym 974 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 975 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 976 channel +.sym 977 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[0] +.sym 978 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 979 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[1] +.sym 980 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 981 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 990 tx_fifo.wr_addr[8] +.sym 994 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 1007 w_lvds_rx_24_d0 +.sym 1009 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 1011 tx_fifo.rd_addr[4] +.sym 1015 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 1021 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 1051 tx_fifo.rd_addr[5] +.sym 1054 w_lvds_rx_24_d0 +.sym 1061 w_lvds_tx_d1 +.sym 1062 w_lvds_tx_d0 +.sym 1066 iq_tx_p_D_OUT_0 +.sym 1067 iq_tx_p_D_OUT_1 .sym 1069 $PACKER_VCC_NET -.sym 1071 iq_tx_n_OUTPUT_CLK -.sym 1073 iq_tx_n_OUTPUT_CLK +.sym 1071 lvds_clock_buf +.sym 1072 w_lvds_tx_d1 .sym 1074 $PACKER_VCC_NET -.sym 1076 $PACKER_GND_NET -.sym 1080 $PACKER_VCC_NET -.sym 1084 $PACKER_GND_NET -.sym 1088 w_rx_09_fifo_data[1] -.sym 1090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] -.sym 1091 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 1092 $PACKER_GND_NET -.sym 1096 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] -.sym 1120 $PACKER_VCC_NET -.sym 1122 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] +.sym 1078 iq_tx_p_D_OUT_1 +.sym 1084 w_lvds_tx_d0 +.sym 1086 iq_tx_p_D_OUT_0 +.sym 1088 tx_fifo.wr_addr_gray_rd_r[6] +.sym 1089 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 1090 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 1091 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 1092 tx_fifo.wr_addr_gray_rd_r[3] +.sym 1093 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 1094 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 1095 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[3] +.sym 1116 iq_tx_p_D_OUT_0 +.sym 1119 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 1121 w_lvds_rx_24_d0 +.sym 1124 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] .sym 1132 $PACKER_VCC_NET -.sym 1138 w_lvds_rx_24_d0 -.sym 1145 iq_tx_n_OUTPUT_CLK -.sym 1165 $PACKER_VCC_NET +.sym 1145 w_lvds_rx_24_d1 +.sym 1159 w_lvds_tx_d0 +.sym 1165 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 1167 channel .sym 1168 w_lvds_rx_24_d0 -.sym 1169 $PACKER_VCC_NET +.sym 1169 w_lvds_rx_24_d1 .sym 1173 w_lvds_rx_09_d0 .sym 1174 w_lvds_rx_09_d1 .sym 1183 $PACKER_VCC_NET -.sym 1184 lvds_clock_$glb_clk +.sym 1184 lvds_clock_buf .sym 1191 $PACKER_VCC_NET -.sym 1203 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -.sym 1204 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 1205 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 1208 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] -.sym 1209 w_lvds_rx_09_d1_SB_LUT4_I0_O[1] -.sym 1228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 1230 rx_fifo.rd_addr_gray_wr_r[1] -.sym 1247 i_rst_b$SB_IO_IN -.sym 1262 w_lvds_rx_09_d1 -.sym 1269 w_lvds_rx_09_d0 -.sym 1272 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 1282 lvds_clock +.sym 1202 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 1203 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] +.sym 1204 tx_fifo.rd_addr_gray_wr[3] +.sym 1206 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 1207 tx_fifo.rd_addr_gray_wr_r[3] +.sym 1208 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 1209 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 1246 w_lvds_rx_09_d1 +.sym 1257 tx_fifo.wr_addr_gray_rd[6] +.sym 1280 w_lvds_rx_09_d0 .sym 1287 lvds_clock .sym 1297 $PACKER_VCC_NET .sym 1305 $PACKER_VCC_NET -.sym 1316 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 1317 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.sym 1318 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 1320 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 1321 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 1322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] -.sym 1323 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 1379 $PACKER_VCC_NET +.sym 1316 tx_fifo.wr_addr_gray_rd[5] +.sym 1317 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 1318 tx_fifo.wr_addr_gray_rd[8] +.sym 1319 tx_fifo.wr_addr_gray_rd[7] +.sym 1320 tx_fifo.wr_addr_gray_rd[4] +.sym 1321 tx_fifo.wr_addr_gray_rd_r[8] +.sym 1322 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 1323 tx_fifo.wr_addr_gray_rd[3] +.sym 1361 r_counter +.sym 1370 $PACKER_VCC_NET .sym 1401 w_lvds_rx_24_d0 .sym 1402 w_lvds_rx_24_d1 .sym 1411 $PACKER_VCC_NET -.sym 1412 lvds_clock_$glb_clk -.sym 1427 $PACKER_VCC_NET -.sym 1431 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 -.sym 1432 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] -.sym 1433 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 1434 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] -.sym 1435 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 1436 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 1437 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] +.sym 1412 lvds_clock_buf +.sym 1424 $PACKER_VCC_NET +.sym 1432 tx_fifo.rd_addr_gray[7] +.sym 1433 tx_fifo.rd_addr_gray[6] +.sym 1437 tx_fifo.rd_addr_gray[4] +.sym 1457 tx_fifo.wr_addr[2] +.sym 1462 r_counter +.sym 1463 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 1464 $PACKER_VCC_NET .sym 1474 w_lvds_rx_24_d1 -.sym 1510 lvds_clock -.sym 1544 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 1545 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 1547 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 1549 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 1551 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 1569 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 1579 $PACKER_VCC_NET -.sym 1687 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 1706 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 1879 rx_fifo.mem_i.0.1_WDATA_3 -.sym 1880 w_rx_09_fifo_data[20] -.sym 1881 w_rx_09_fifo_data[24] -.sym 1883 rx_fifo.mem_i.0.1_WDATA_2 -.sym 1885 w_rx_09_fifo_data[22] -.sym 1886 w_rx_09_fifo_data[26] -.sym 1907 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2063 w_rx_24_fifo_data[22] -.sym 2064 rx_fifo.mem_i.0.2_WDATA_3 -.sym 2065 rx_fifo.mem_q.0.3_WDATA_2 -.sym 2066 w_rx_24_fifo_data[24] -.sym 2067 w_rx_24_fifo_data[14] -.sym 2068 w_rx_24_fifo_data[16] -.sym 2069 w_rx_24_fifo_data[20] -.sym 2070 rx_fifo.mem_q.0.3_WDATA_3 -.sym 2094 w_rx_09_fifo_data[18] -.sym 2106 w_rx_24_fifo_data[29] -.sym 2107 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2117 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2124 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2128 w_rx_09_fifo_data[14] -.sym 2129 rx_fifo.mem_i.0.2_WDATA_1 -.sym 2137 w_rx_09_fifo_data[10] -.sym 2162 w_rx_09_fifo_data[12] -.sym 2173 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2182 w_rx_09_fifo_data[10] -.sym 2191 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2193 w_rx_09_fifo_data[12] -.sym 2198 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2200 w_rx_09_fifo_data[10] -.sym 2231 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2232 lvds_clock_$glb_clk -.sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2234 w_rx_24_fifo_data[18] -.sym 2235 w_rx_24_fifo_data[29] -.sym 2236 w_rx_24_fifo_data[25] -.sym 2237 w_rx_24_fifo_data[26] -.sym 2238 w_rx_24_fifo_data[10] -.sym 2239 w_rx_24_fifo_data[27] -.sym 2240 w_rx_24_fifo_data[12] -.sym 2241 w_rx_24_fifo_data[28] -.sym 2260 rx_fifo.wr_addr[7] -.sym 2264 w_rx_24_fifo_data[16] -.sym 2265 w_rx_09_fifo_data[19] -.sym 2269 w_rx_24_fifo_data[29] -.sym 2272 rx_fifo.mem_q.0.1_WDATA -.sym 2288 w_rx_09_fifo_data[25] -.sym 2298 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2299 w_rx_09_fifo_data[21] -.sym 2300 w_rx_09_fifo_data[27] -.sym 2305 w_rx_24_fifo_data[25] -.sym 2308 w_rx_24_fifo_data[27] -.sym 2311 w_rx_09_fifo_data[23] -.sym 2313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2316 w_rx_24_fifo_data[23] -.sym 2321 w_rx_09_fifo_data[21] -.sym 2322 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2328 w_rx_09_fifo_data[23] -.sym 2329 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2338 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2339 w_rx_24_fifo_data[25] -.sym 2340 w_rx_09_fifo_data[25] -.sym 2345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2346 w_rx_09_fifo_data[27] -.sym 2347 w_rx_24_fifo_data[27] -.sym 2351 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2352 w_rx_09_fifo_data[25] -.sym 2357 w_rx_09_fifo_data[23] -.sym 2358 w_rx_24_fifo_data[23] -.sym 2359 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2366 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2367 lvds_clock_$glb_clk -.sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2369 w_rx_09_fifo_data[16] -.sym 2370 rx_fifo.mem_i.0.0_WDATA_3 -.sym 2371 rx_fifo.mem_i.0.1_WDATA_1 -.sym 2372 rx_fifo.mem_q.0.3_WDATA -.sym 2373 w_rx_09_fifo_data[28] -.sym 2374 rx_fifo.mem_q.0.2_WDATA_2 -.sym 2375 rx_fifo.mem_i.0.0_WDATA_2 -.sym 2376 w_rx_09_fifo_data[18] -.sym 2384 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2386 rx_fifo.wr_addr[3] -.sym 2396 w_rx_24_fifo_data[21] -.sym 2397 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2400 w_rx_09_fifo_data[18] -.sym 2402 w_rx_24_fifo_data[23] -.sym 2405 w_rx_24_fifo_data[13] -.sym 2406 w_rx_24_fifo_data[7] -.sym 2411 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2415 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2427 w_rx_09_fifo_data[8] -.sym 2431 w_rx_09_fifo_data[19] -.sym 2435 w_rx_09_fifo_data[27] -.sym 2436 w_rx_09_fifo_data[13] -.sym 2437 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2439 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2442 w_rx_24_fifo_data[13] -.sym 2444 w_rx_09_fifo_data[17] -.sym 2446 w_rx_09_fifo_data[15] -.sym 2456 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2458 w_rx_09_fifo_data[13] -.sym 2462 w_rx_09_fifo_data[17] -.sym 2463 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2467 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2469 w_rx_24_fifo_data[13] -.sym 2470 w_rx_09_fifo_data[13] -.sym 2479 w_rx_09_fifo_data[19] -.sym 2482 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2486 w_rx_09_fifo_data[27] -.sym 2487 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2492 w_rx_09_fifo_data[15] -.sym 2494 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2497 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2499 w_rx_09_fifo_data[8] -.sym 2501 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2502 lvds_clock_$glb_clk -.sym 2503 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2504 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 2507 rx_fifo.mem_q.0.2_WDATA_3 -.sym 2508 rx_fifo.mem_i.0.3_WDATA_1 -.sym 2509 rx_fifo.mem_i.0.0_WDATA_1 -.sym 2510 rx_fifo.mem_q.0.1_WDATA_2 -.sym 2511 rx_fifo.mem_i.0.0_WDATA -.sym 2513 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2514 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2521 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 2522 rx_fifo.mem_q.0.3_WDATA_1 -.sym 2529 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2531 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2532 w_rx_09_fifo_data[28] -.sym 2534 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2537 w_rx_24_fifo_data[15] -.sym 2539 w_rx_24_fifo_data[29] -.sym 2541 w_rx_09_fifo_data[5] -.sym 2545 w_rx_09_fifo_data[4] -.sym 2557 w_rx_09_fifo_data[6] -.sym 2559 w_rx_09_fifo_data[11] -.sym 2566 w_rx_09_fifo_data[9] -.sym 2570 w_rx_09_fifo_data[29] -.sym 2573 w_rx_24_fifo_data[7] -.sym 2574 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2577 w_rx_09_fifo_data[7] -.sym 2578 w_rx_09_fifo_data[5] -.sym 2582 w_rx_09_fifo_data[4] -.sym 2587 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2590 w_rx_09_fifo_data[4] -.sym 2591 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2596 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2599 w_rx_09_fifo_data[7] -.sym 2603 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2604 w_rx_09_fifo_data[9] -.sym 2608 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2609 w_rx_09_fifo_data[29] -.sym 2615 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2617 w_rx_09_fifo_data[5] -.sym 2621 w_rx_09_fifo_data[6] -.sym 2622 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2627 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2628 w_rx_09_fifo_data[11] -.sym 2633 w_rx_24_fifo_data[7] -.sym 2634 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2635 w_rx_09_fifo_data[7] -.sym 2636 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 2637 lvds_clock_$glb_clk -.sym 2638 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2639 w_rx_24_fifo_data[8] -.sym 2640 w_rx_24_fifo_data[21] -.sym 2641 w_rx_24_fifo_data[30] -.sym 2642 w_rx_24_fifo_data[19] -.sym 2643 w_rx_24_fifo_data[23] -.sym 2644 rx_fifo.mem_i.0.3_WDATA -.sym 2645 w_rx_24_fifo_data[31] -.sym 2646 w_rx_24_fifo_data[17] -.sym 2650 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 2652 rx_fifo.wr_addr[0] -.sym 2658 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 2663 rx_fifo.mem_q.0.2_WDATA -.sym 2666 w_rx_09_fifo_data[28] -.sym 2667 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2668 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 2669 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2673 rx_fifo.mem_q.0.2_WDATA_1 -.sym 2686 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2694 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2695 w_rx_24_fifo_data[11] -.sym 2700 w_rx_24_fifo_data[7] -.sym 2701 w_rx_09_fifo_data[9] -.sym 2702 w_rx_09_fifo_data[11] -.sym 2705 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2707 w_rx_24_fifo_data[4] -.sym 2713 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2714 w_rx_24_fifo_data[13] -.sym 2715 w_rx_24_fifo_data[9] -.sym 2720 w_rx_09_fifo_data[4] -.sym 2725 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2727 w_rx_24_fifo_data[4] -.sym 2728 w_rx_09_fifo_data[4] -.sym 2732 w_rx_09_fifo_data[9] -.sym 2733 w_rx_24_fifo_data[9] -.sym 2734 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2739 w_rx_24_fifo_data[13] -.sym 2740 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2743 w_rx_24_fifo_data[9] -.sym 2745 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2750 w_rx_09_fifo_data[11] -.sym 2752 w_rx_24_fifo_data[11] -.sym 2756 w_rx_24_fifo_data[4] -.sym 2757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2762 w_rx_24_fifo_data[11] -.sym 2764 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2767 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2769 w_rx_24_fifo_data[7] -.sym 2771 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2772 lvds_clock_$glb_clk -.sym 2773 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2775 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2776 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 2777 rx_fifo.mem_i.0.3_WDATA_3 -.sym 2778 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 2779 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 2780 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 2781 rx_fifo.mem_i.0.3_WDATA_2 -.sym 2791 rx_fifo.mem_q.0.1_WDATA -.sym 2798 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 2799 rx_fifo.wr_addr[7] -.sym 2805 rx_fifo.wr_addr[6] -.sym 2807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 2809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2813 w_rx_24_fifo_data[1] -.sym 2831 lvds_clock -.sym 2835 w_rx_09_fifo_data[5] -.sym 2836 w_rx_24_fifo_data[2] -.sym 2839 w_rx_24_fifo_data[5] -.sym 2841 w_rx_24_fifo_data[3] -.sym 2845 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2847 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2851 w_rx_24_fifo_data[0] -.sym 2857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2858 w_rx_24_fifo_data[1] -.sym 2861 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2863 w_rx_24_fifo_data[5] -.sym 2866 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2868 w_rx_24_fifo_data[0] -.sym 2881 lvds_clock -.sym 2885 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2887 w_rx_24_fifo_data[3] -.sym 2890 w_rx_24_fifo_data[5] -.sym 2891 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2892 w_rx_09_fifo_data[5] -.sym 2897 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2898 w_rx_24_fifo_data[1] -.sym 2903 w_rx_24_fifo_data[2] -.sym 2904 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2906 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2907 lvds_clock_$glb_clk -.sym 2908 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 2909 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 2911 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 2914 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 2915 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 2922 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 2926 rx_fifo.wr_addr[4] -.sym 2929 iq_tx_n_OUTPUT_CLK -.sym 2930 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 2936 iq_tx_n_OUTPUT_CLK -.sym 2937 w_rx_24_fifo_data[0] -.sym 2940 rx_fifo.mem_q.0.1_WDATA_1 -.sym 2946 w_rx_09_fifo_data[1] -.sym 2947 rx_fifo.wr_addr[4] -.sym 2954 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 2955 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 2968 w_rx_24_fifo_data[3] -.sym 2971 w_rx_24_fifo_data[2] -.sym 2972 w_rx_09_fifo_data[28] -.sym 2974 w_rx_09_fifo_data[2] -.sym 2976 w_rx_09_fifo_data[3] -.sym 2977 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 2981 w_rx_09_fifo_data[0] -.sym 2983 w_rx_09_fifo_data[1] -.sym 2987 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 2990 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 2996 w_rx_09_fifo_data[3] -.sym 2997 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3001 w_rx_09_fifo_data[28] -.sym 3002 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3007 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3010 w_rx_09_fifo_data[2] -.sym 3013 w_rx_09_fifo_data[3] -.sym 3014 w_rx_24_fifo_data[3] -.sym 3016 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 3020 w_rx_09_fifo_data[0] -.sym 3021 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3026 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 3027 w_rx_09_fifo_data[2] -.sym 3028 w_rx_24_fifo_data[2] -.sym 3032 w_rx_09_fifo_data[1] -.sym 3033 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3039 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3041 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 3042 lvds_clock_$glb_clk -.sym 3043 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 3044 rx_fifo.wr_addr[7] -.sym 3045 rx_fifo.mem_q.0.0_WDATA_3 -.sym 3046 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 3047 rx_fifo.wr_addr[6] -.sym 3048 rx_fifo.wr_addr[1] -.sym 3049 rx_fifo.wr_addr[2] -.sym 3050 rx_fifo.mem_q.0.0_WDATA_1 -.sym 3051 rx_fifo.wr_addr[5] -.sym 3057 $PACKER_VCC_NET -.sym 3061 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 3068 w_rx_09_fifo_data[1] -.sym 3073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 3074 rx_fifo.wr_addr[9] -.sym 3076 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3078 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 3086 $PACKER_VCC_NET -.sym 3101 rx_fifo.wr_addr[8] -.sym 3106 rx_fifo.wr_addr[3] -.sym 3113 rx_fifo.wr_addr[7] -.sym 3116 rx_fifo.wr_addr[6] -.sym 3117 rx_fifo.wr_addr[1] -.sym 3124 rx_fifo.wr_addr[4] -.sym 3126 rx_fifo.wr_addr[2] -.sym 3128 rx_fifo.wr_addr[5] -.sym 3129 $nextpnr_ICESTORM_LC_0$O -.sym 3132 rx_fifo.wr_addr[1] -.sym 3135 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 -.sym 3137 rx_fifo.wr_addr[2] -.sym 3139 rx_fifo.wr_addr[1] -.sym 3141 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 -.sym 3144 rx_fifo.wr_addr[3] -.sym 3145 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 -.sym 3147 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 3149 rx_fifo.wr_addr[4] -.sym 3151 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 -.sym 3153 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 3156 rx_fifo.wr_addr[5] -.sym 3157 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 3159 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 3162 rx_fifo.wr_addr[6] -.sym 3163 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 3165 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3168 rx_fifo.wr_addr[7] -.sym 3169 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 3171 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 -.sym 3173 rx_fifo.wr_addr[8] -.sym 3175 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 3179 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 3181 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 3182 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 3183 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 3184 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 3185 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 3186 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] -.sym 3191 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3192 rx_fifo.wr_addr[3] -.sym 3193 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 3194 rx_fifo.wr_addr[6] -.sym 3195 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 3196 rx_fifo.wr_addr[5] -.sym 3198 rx_fifo.wr_addr[7] -.sym 3200 rx_fifo.wr_addr[0] -.sym 3201 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 3208 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 3210 w_rx_09_fifo_data[0] -.sym 3211 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3212 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 3214 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 3224 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3227 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 -.sym 3232 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3233 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 3234 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 3235 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 3237 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 3238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 3242 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] -.sym 3245 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 3246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 3247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 3248 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 3250 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 3254 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 3255 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 3257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 3258 rx_fifo.wr_addr[9] -.sym 3260 w_lvds_rx_24_d0 -.sym 3261 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] -.sym 3266 rx_fifo.wr_addr[9] -.sym 3268 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 -.sym 3273 w_lvds_rx_24_d0 -.sym 3277 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 3278 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 3279 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 3280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] -.sym 3284 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 3285 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 3286 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 3289 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 3291 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 3292 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 3295 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 3296 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 3298 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 3301 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 3302 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 3303 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 3308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 3309 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 3310 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] -.sym 3311 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 3312 lvds_clock_$glb_clk -.sym 3314 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 3315 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 3317 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 3318 rx_fifo.rd_addr_gray_wr[0] -.sym 3319 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 3320 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 3321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 3326 rx_fifo.rd_addr_gray_wr_r[7] -.sym 3327 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 3330 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 3332 rx_fifo.rd_addr_gray_wr_r[4] -.sym 3337 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 3339 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3341 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 3342 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 3343 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3345 rx_fifo.rd_addr_gray[5] -.sym 3349 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 3375 w_lvds_rx_09_d0 -.sym 3382 w_lvds_rx_09_d1_SB_LUT4_I0_O[1] -.sym 3384 i_rst_b$SB_IO_IN -.sym 3392 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 3396 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 3401 w_lvds_rx_09_d0 -.sym 3412 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 3414 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 3419 w_lvds_rx_09_d1_SB_LUT4_I0_O[1] -.sym 3420 i_rst_b$SB_IO_IN -.sym 3446 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 3447 lvds_clock_$glb_clk -.sym 3449 rx_fifo.rd_addr_gray_wr[9] -.sym 3451 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 3453 rx_fifo.rd_addr_gray_wr[5] -.sym 3454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 3464 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 3465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 3466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 3467 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 3468 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 3469 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 3472 rx_fifo.rd_addr_gray[0] -.sym 3475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 3477 w_rx_fifo_full -.sym 3481 w_rx_24_fifo_data[0] -.sym 3484 rx_fifo.rd_addr[9] -.sym 3488 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3496 w_lvds_rx_09_d0 -.sym 3505 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3509 $PACKER_VCC_NET -.sym 3511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.sym 3516 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] -.sym 3517 $PACKER_VCC_NET -.sym 3519 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -.sym 3520 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3522 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3523 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3526 w_lvds_rx_09_d0 -.sym 3529 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3531 w_lvds_rx_09_d1 -.sym 3533 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3534 $nextpnr_ICESTORM_LC_1$O -.sym 3537 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.sym 3540 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3541 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3542 $PACKER_VCC_NET -.sym 3543 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] -.sym 3544 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.sym 3547 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3548 $PACKER_VCC_NET -.sym 3549 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3550 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3553 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -.sym 3556 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 3572 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -.sym 3577 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3578 w_lvds_rx_09_d1 -.sym 3579 w_lvds_rx_09_d0 -.sym 3580 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3581 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3582 lvds_clock_$glb_clk -.sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3585 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 3586 w_rx_24_fifo_data[0] -.sym 3590 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 3601 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3608 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3610 w_lvds_rx_09_d1 -.sym 3619 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3622 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3638 w_lvds_rx_24_d1 -.sym 3639 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3640 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 3641 w_lvds_rx_24_d0 -.sym 3648 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 3649 w_lvds_rx_24_d0 -.sym 3651 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] -.sym 3652 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3658 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 3659 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3667 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 3668 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3670 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3671 w_lvds_rx_24_d1 -.sym 3672 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3673 w_lvds_rx_24_d0 -.sym 3676 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 3682 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3683 w_lvds_rx_24_d1 -.sym 3684 w_lvds_rx_24_d0 -.sym 3695 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 3697 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] -.sym 3700 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 3701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3702 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 3703 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3706 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 3707 w_lvds_rx_24_d1 -.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3709 w_lvds_rx_24_d0 -.sym 3713 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3714 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 3715 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 3716 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3717 lvds_clock_$glb_clk -.sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3721 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3722 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 3725 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3726 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 3732 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 3735 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3745 w_rx_09_fifo_data[0] -.sym 3750 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3773 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3774 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 3775 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 3778 $PACKER_VCC_NET -.sym 3779 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3781 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3783 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 3787 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] -.sym 3794 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 3797 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 -.sym 3798 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] -.sym 3800 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] -.sym 3804 $nextpnr_ICESTORM_LC_6$O -.sym 3807 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] -.sym 3810 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 -.sym 3811 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3812 $PACKER_VCC_NET -.sym 3813 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] -.sym 3814 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] -.sym 3817 $PACKER_VCC_NET -.sym 3818 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] -.sym 3819 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3820 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 -.sym 3823 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3824 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 3825 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3826 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 3831 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 -.sym 3835 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 3836 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 3837 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3838 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3841 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 3842 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3843 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 -.sym 3844 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] -.sym 3850 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 3851 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 3852 lvds_clock_$glb_clk -.sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3859 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3861 w_rx_09_fifo_data[0] -.sym 3868 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E -.sym 3869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 3886 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 3917 w_lvds_rx_09_d0 -.sym 3918 w_lvds_rx_09_d1 -.sym 3924 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3925 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3928 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3934 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 3938 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3940 w_lvds_rx_09_d1 -.sym 3941 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3942 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3943 w_lvds_rx_09_d0 -.sym 3946 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3948 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3958 w_lvds_rx_09_d0 -.sym 3961 w_lvds_rx_09_d1 -.sym 3970 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 3971 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 3973 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3982 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 3986 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 3987 lvds_clock_$glb_clk -.sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4019 o_shdn_tx_lna$SB_IO_OUT -.sym 4024 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 4238 w_rx_fifo_pulled_data[20] -.sym 4242 w_rx_fifo_pulled_data[22] -.sym 4254 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4255 w_rx_09_fifo_data[0] -.sym 4279 w_rx_24_fifo_data[22] -.sym 4285 w_rx_24_fifo_data[20] -.sym 4286 w_rx_09_fifo_data[18] -.sym 4288 w_rx_09_fifo_data[20] -.sym 4289 w_rx_09_fifo_data[24] -.sym 4296 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4299 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4309 w_rx_09_fifo_data[22] -.sym 4312 w_rx_09_fifo_data[20] -.sym 4313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4314 w_rx_24_fifo_data[20] -.sym 4320 w_rx_09_fifo_data[18] -.sym 4321 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4324 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4325 w_rx_09_fifo_data[22] -.sym 4337 w_rx_09_fifo_data[22] -.sym 4338 w_rx_24_fifo_data[22] -.sym 4339 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4348 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4350 w_rx_09_fifo_data[20] -.sym 4355 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4356 w_rx_09_fifo_data[24] -.sym 4358 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 4359 lvds_clock_$glb_clk -.sym 4360 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4366 w_rx_fifo_pulled_data[21] -.sym 4370 w_rx_fifo_pulled_data[23] -.sym 4376 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] -.sym 4382 rx_fifo.wr_addr[7] -.sym 4390 rx_fifo.wr_addr[1] -.sym 4400 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 4406 rx_fifo.rd_addr[2] -.sym 4408 rx_fifo.mem_q.0.3_WDATA_3 -.sym 4411 rx_fifo.rd_addr[1] -.sym 4413 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4414 w_rx_09_fifo_data[26] -.sym 4416 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 4417 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 4418 rx_fifo.wr_addr[2] -.sym 4422 w_rx_24_fifo_data[28] -.sym 4424 rx_fifo.mem_i.0.1_WDATA_1 -.sym 4428 rx_fifo.wr_addr[5] -.sym 4429 $PACKER_VCC_NET -.sym 4431 w_rx_09_fifo_data[26] -.sym 4432 rx_fifo.wr_addr[2] -.sym 4442 w_rx_24_fifo_data[22] -.sym 4444 w_rx_09_fifo_data[12] -.sym 4448 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4450 w_rx_24_fifo_data[18] -.sym 4451 w_rx_09_fifo_data[14] -.sym 4452 w_rx_09_fifo_data[24] -.sym 4453 w_rx_24_fifo_data[24] -.sym 4454 w_rx_24_fifo_data[14] -.sym 4456 w_rx_24_fifo_data[12] -.sym 4464 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4469 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4472 w_rx_24_fifo_data[20] -.sym 4475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4476 w_rx_24_fifo_data[20] -.sym 4481 w_rx_09_fifo_data[24] -.sym 4482 w_rx_24_fifo_data[24] -.sym 4484 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4487 w_rx_09_fifo_data[14] -.sym 4488 w_rx_24_fifo_data[14] -.sym 4489 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4494 w_rx_24_fifo_data[22] -.sym 4496 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4499 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4502 w_rx_24_fifo_data[12] -.sym 4506 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4507 w_rx_24_fifo_data[14] -.sym 4511 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4514 w_rx_24_fifo_data[18] -.sym 4518 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4519 w_rx_24_fifo_data[12] -.sym 4520 w_rx_09_fifo_data[12] -.sym 4521 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4522 lvds_clock_$glb_clk -.sym 4523 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4525 w_rx_fifo_pulled_data[24] -.sym 4529 w_rx_fifo_pulled_data[26] -.sym 4541 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 4542 rx_fifo.mem_q.0.3_WDATA_2 -.sym 4544 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 4549 rx_fifo.mem_i.0.0_WDATA_2 -.sym 4550 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 4551 rx_fifo.wr_addr[2] -.sym 4552 rx_fifo.wr_addr[1] -.sym 4553 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4554 rx_fifo.wr_addr[6] -.sym 4555 rx_fifo.mem_i.0.0_WDATA_3 -.sym 4559 rx_fifo.wr_addr[6] -.sym 4567 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4568 w_rx_24_fifo_data[24] -.sym 4570 w_rx_24_fifo_data[16] -.sym 4578 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4583 w_rx_24_fifo_data[25] -.sym 4585 w_rx_24_fifo_data[8] -.sym 4586 w_rx_24_fifo_data[23] -.sym 4592 w_rx_24_fifo_data[26] -.sym 4593 w_rx_24_fifo_data[10] -.sym 4594 w_rx_24_fifo_data[27] -.sym 4598 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4599 w_rx_24_fifo_data[16] -.sym 4605 w_rx_24_fifo_data[27] -.sym 4607 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4612 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4613 w_rx_24_fifo_data[23] -.sym 4618 w_rx_24_fifo_data[24] -.sym 4619 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4622 w_rx_24_fifo_data[8] -.sym 4624 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4629 w_rx_24_fifo_data[25] -.sym 4631 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4634 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4637 w_rx_24_fifo_data[10] -.sym 4641 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4643 w_rx_24_fifo_data[26] -.sym 4644 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4645 lvds_clock_$glb_clk -.sym 4646 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4648 w_rx_fifo_pulled_data[25] -.sym 4652 w_rx_fifo_pulled_data[27] -.sym 4663 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4666 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4667 w_rx_24_fifo_data[26] -.sym 4671 w_rx_24_fifo_data[8] -.sym 4672 rx_fifo.wr_addr[7] -.sym 4674 rx_fifo.mem_i.0.0_WDATA -.sym 4676 $PACKER_VCC_NET -.sym 4678 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 4679 $PACKER_VCC_NET -.sym 4680 rx_fifo.mem_q.0.1_WDATA_3 -.sym 4682 w_rx_24_fifo_data[28] -.sym 4688 w_rx_24_fifo_data[18] -.sym 4690 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4692 w_rx_24_fifo_data[10] -.sym 4695 w_rx_09_fifo_data[10] -.sym 4696 w_rx_09_fifo_data[15] -.sym 4698 w_rx_24_fifo_data[16] -.sym 4699 w_rx_09_fifo_data[14] -.sym 4700 w_rx_09_fifo_data[21] -.sym 4706 w_rx_09_fifo_data[26] -.sym 4711 w_rx_09_fifo_data[18] -.sym 4712 w_rx_09_fifo_data[16] -.sym 4713 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4714 w_rx_24_fifo_data[21] -.sym 4717 w_rx_24_fifo_data[15] -.sym 4721 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4723 w_rx_09_fifo_data[14] -.sym 4727 w_rx_09_fifo_data[16] -.sym 4729 w_rx_24_fifo_data[16] -.sym 4730 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4733 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4734 w_rx_09_fifo_data[21] -.sym 4736 w_rx_24_fifo_data[21] -.sym 4740 w_rx_24_fifo_data[15] -.sym 4741 w_rx_09_fifo_data[15] -.sym 4742 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4745 w_rx_09_fifo_data[26] -.sym 4747 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4752 w_rx_24_fifo_data[10] -.sym 4753 w_rx_09_fifo_data[10] -.sym 4754 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4757 w_rx_24_fifo_data[18] -.sym 4759 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4760 w_rx_09_fifo_data[18] -.sym 4764 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 4765 w_rx_09_fifo_data[16] -.sym 4767 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 4768 lvds_clock_$glb_clk -.sym 4769 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 4771 w_rx_fifo_pulled_data[4] -.sym 4775 w_rx_fifo_pulled_data[6] -.sym 4784 rx_fifo.mem_i.0.2_WDATA_1 -.sym 4785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 4788 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 4789 rx_fifo.rd_addr[2] -.sym 4790 rx_fifo.mem_q.0.3_WDATA -.sym 4792 w_rx_09_fifo_data[28] -.sym 4794 rx_fifo.wr_addr[1] -.sym 4795 rx_fifo.mem_i.0.2_WDATA -.sym 4796 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4797 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 4798 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 4799 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4800 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 4801 rx_fifo.mem_q.0.2_WDATA_2 -.sym 4802 rx_fifo.rd_addr[1] -.sym 4803 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 4804 rx_fifo.wr_addr[2] -.sym 4805 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 4811 w_rx_24_fifo_data[8] -.sym 4816 w_rx_09_fifo_data[8] -.sym 4818 w_rx_24_fifo_data[17] -.sym 4819 w_rx_09_fifo_data[6] -.sym 4821 w_rx_24_fifo_data[29] -.sym 4822 w_rx_24_fifo_data[19] -.sym 4823 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4825 w_rx_09_fifo_data[19] -.sym 4828 w_rx_fifo_pulled_data[5] -.sym 4832 w_rx_09_fifo_data[29] -.sym 4833 w_rx_09_fifo_data[17] -.sym 4836 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4840 w_rx_24_fifo_data[6] -.sym 4845 w_rx_fifo_pulled_data[5] -.sym 4862 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4863 w_rx_24_fifo_data[8] -.sym 4864 w_rx_09_fifo_data[8] -.sym 4869 w_rx_24_fifo_data[29] -.sym 4870 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4871 w_rx_09_fifo_data[29] -.sym 4874 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4876 w_rx_24_fifo_data[17] -.sym 4877 w_rx_09_fifo_data[17] -.sym 4881 w_rx_09_fifo_data[6] -.sym 4882 w_rx_24_fifo_data[6] -.sym 4883 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4886 w_rx_09_fifo_data[19] -.sym 4887 w_rx_24_fifo_data[19] -.sym 4888 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4890 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 4891 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 4892 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4894 w_rx_fifo_pulled_data[5] -.sym 4898 w_rx_fifo_pulled_data[7] -.sym 4906 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 4907 rx_fifo.mem_i.0.0_WDATA_1 -.sym 4908 rx_fifo.wr_addr[6] -.sym 4910 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 4912 rx_fifo.wr_addr[7] -.sym 4915 rx_fifo.mem_i.0.3_WDATA_1 -.sym 4920 rx_fifo.mem_q.0.2_WDATA_3 -.sym 4924 rx_fifo.wr_addr[5] -.sym 4928 w_rx_24_fifo_data[28] -.sym 4936 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 4937 w_rx_24_fifo_data[19] -.sym 4939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4941 w_rx_24_fifo_data[17] -.sym 4943 w_rx_24_fifo_data[21] -.sym 4944 w_rx_24_fifo_data[15] -.sym 4947 w_rx_24_fifo_data[6] -.sym 4948 w_rx_24_fifo_data[31] -.sym 4949 w_rx_24_fifo_data[29] -.sym 4952 w_rx_24_fifo_data[28] -.sym 4961 w_rx_09_fifo_data[31] -.sym 4964 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4969 w_rx_24_fifo_data[6] -.sym 4970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4973 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4975 w_rx_24_fifo_data[19] -.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4981 w_rx_24_fifo_data[28] -.sym 4985 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4987 w_rx_24_fifo_data[17] -.sym 4991 w_rx_24_fifo_data[21] -.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 4997 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 4999 w_rx_24_fifo_data[31] -.sym 5000 w_rx_09_fifo_data[31] -.sym 5003 w_rx_24_fifo_data[29] -.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5009 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5011 w_rx_24_fifo_data[15] -.sym 5013 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 5014 lvds_clock_$glb_clk -.sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5017 w_rx_fifo_pulled_data[8] -.sym 5021 w_rx_fifo_pulled_data[10] -.sym 5030 rx_fifo.mem_i.0.3_WDATA -.sym 5036 rx_fifo.mem_q.0.1_WDATA_1 -.sym 5040 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 5041 $PACKER_VCC_NET -.sym 5046 rx_fifo.wr_addr[6] -.sym 5048 rx_fifo.wr_addr[1] -.sym 5050 rx_fifo.wr_addr[2] -.sym 5051 i_rst_b$SB_IO_IN -.sym 5066 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5067 w_rx_24_fifo_data[30] -.sym 5068 w_rx_fifo_pulled_data[18] -.sym 5069 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5070 w_rx_09_fifo_data[28] -.sym 5074 w_rx_fifo_pulled_data[9] -.sym 5075 i_rst_b$SB_IO_IN -.sym 5078 w_rx_fifo_pulled_data[10] -.sym 5081 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 5082 w_rx_09_fifo_data[30] -.sym 5086 w_rx_fifo_pulled_data[11] -.sym 5088 w_rx_24_fifo_data[28] -.sym 5096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 5097 i_rst_b$SB_IO_IN -.sym 5099 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5102 w_rx_fifo_pulled_data[11] -.sym 5109 w_rx_09_fifo_data[28] -.sym 5110 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5111 w_rx_24_fifo_data[28] -.sym 5115 w_rx_fifo_pulled_data[10] -.sym 5121 w_rx_fifo_pulled_data[18] -.sym 5127 w_rx_fifo_pulled_data[9] -.sym 5132 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5134 w_rx_24_fifo_data[30] -.sym 5135 w_rx_09_fifo_data[30] -.sym 5136 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 5137 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 5138 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5140 w_rx_fifo_pulled_data[9] -.sym 5144 w_rx_fifo_pulled_data[11] -.sym 5147 rx_fifo.wr_addr[8] -.sym 5154 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 5155 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 5156 w_rx_fifo_pulled_data[18] -.sym 5159 rx_fifo.mem_i.0.3_WDATA_3 -.sym 5162 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5163 rx_fifo.rd_addr[9] -.sym 5165 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5166 w_rx_fifo_pulled_data[1] -.sym 5168 rx_fifo.wr_addr[7] -.sym 5169 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 5171 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 5173 rx_fifo.rd_addr[0] -.sym 5174 w_rx_fifo_pulled_data[3] -.sym 5182 w_rx_fifo_pulled_data[1] -.sym 5198 w_rx_fifo_pulled_data[3] -.sym 5201 w_rx_fifo_pulled_data[2] -.sym 5205 w_rx_fifo_pulled_data[0] -.sym 5215 w_rx_fifo_pulled_data[0] -.sym 5227 w_rx_fifo_pulled_data[3] -.sym 5246 w_rx_fifo_pulled_data[1] -.sym 5252 w_rx_fifo_pulled_data[2] -.sym 5259 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 5260 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5263 w_rx_fifo_pulled_data[0] -.sym 5267 w_rx_fifo_pulled_data[2] -.sym 5275 rx_fifo.mem_q.0.2_WDATA -.sym 5276 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 5277 rx_fifo.mem_q.0.2_WDATA_1 -.sym 5278 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5280 rx_fifo.rd_addr[2] -.sym 5281 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 5282 rx_fifo.rd_addr[1] -.sym 5283 $PACKER_VCC_NET -.sym 5286 rx_fifo.wr_addr[1] -.sym 5287 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5288 rx_fifo.wr_addr[2] -.sym 5289 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 5292 rx_fifo.wr_addr[5] -.sym 5293 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5294 rx_fifo.rd_addr[1] -.sym 5295 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 5296 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 5303 w_rx_24_fifo_data[0] -.sym 5308 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5310 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 5312 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5313 rx_fifo.wr_addr[0] -.sym 5314 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 5316 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 5320 w_rx_24_fifo_data[1] -.sym 5321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 5323 rx_fifo.wr_addr[1] -.sym 5328 w_rx_09_fifo_data[1] -.sym 5329 w_rx_09_fifo_data[0] -.sym 5332 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5337 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 5342 w_rx_09_fifo_data[0] -.sym 5343 w_rx_24_fifo_data[0] -.sym 5345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5349 rx_fifo.wr_addr[0] -.sym 5350 rx_fifo.wr_addr[1] -.sym 5355 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 5366 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5372 w_rx_09_fifo_data[1] -.sym 5373 w_rx_24_fifo_data[1] -.sym 5374 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5382 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 5383 lvds_clock_$glb_clk -.sym 5384 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5386 w_rx_fifo_pulled_data[1] -.sym 5390 w_rx_fifo_pulled_data[3] -.sym 5394 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5397 rx_fifo.rd_addr_gray[5] -.sym 5399 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5405 rx_fifo.wr_addr[6] -.sym 5407 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5411 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5413 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5414 rx_fifo.wr_addr[1] -.sym 5415 rx_fifo.mem_q.0.0_WDATA_2 -.sym 5416 rx_fifo.wr_addr[2] -.sym 5417 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5418 $PACKER_VCC_NET -.sym 5420 rx_fifo.wr_addr[5] -.sym 5428 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 5429 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 5430 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] -.sym 5433 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 5434 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] -.sym 5435 rx_fifo.rd_addr_gray_wr_r[4] -.sym 5436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 5437 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 5438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 5439 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5441 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 5443 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 5447 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5449 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] -.sym 5451 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5452 i_rst_b$SB_IO_IN -.sym 5453 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 5454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 5455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 5457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 5459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 5461 rx_fifo.rd_addr_gray_wr_r[4] -.sym 5462 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 5465 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] -.sym 5467 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 5468 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] -.sym 5472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 5474 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5479 i_rst_b$SB_IO_IN -.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5483 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 5484 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 5485 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5486 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] -.sym 5490 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 5492 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 5495 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 5496 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 5497 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 5498 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 5501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] -.sym 5502 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5503 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 5504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 5518 w_rx_09_fifo_data[0] -.sym 5524 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5526 rx_fifo.rd_addr[9] -.sym 5527 w_rx_fifo_full -.sym 5528 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 5530 rx_fifo.rd_addr[2] -.sym 5536 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 5538 i_rst_b$SB_IO_IN -.sym 5542 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 5549 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 5550 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5551 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5553 rx_fifo.rd_addr_gray[0] -.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] -.sym 5557 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5558 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5559 rx_fifo.rd_addr_gray_wr_r[1] -.sym 5561 rx_fifo.rd_addr_gray_wr[0] -.sym 5562 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 5563 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 5564 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 5565 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 5568 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 5569 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5571 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5573 w_rx_fifo_full -.sym 5574 rx_fifo.wr_addr[1] -.sym 5575 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5576 rx_fifo.wr_addr[2] -.sym 5577 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5579 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 5582 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5583 w_rx_fifo_full -.sym 5584 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5585 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5588 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5589 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 5594 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 5595 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5597 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 5600 rx_fifo.rd_addr_gray_wr[0] -.sym 5606 rx_fifo.rd_addr_gray[0] -.sym 5613 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 5614 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 5615 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 5618 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 5619 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 5620 rx_fifo.wr_addr[1] -.sym 5621 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 5624 rx_fifo.rd_addr_gray_wr_r[1] -.sym 5625 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] -.sym 5627 rx_fifo.wr_addr[2] -.sym 5629 lvds_clock_$glb_clk -.sym 5645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 5646 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 5647 rx_fifo.wr_addr[9] -.sym 5649 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 5651 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 5656 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 5657 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 5661 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 5680 rx_fifo.rd_addr_gray_wr[9] -.sym 5683 rx_fifo.rd_addr_gray[5] -.sym 5684 rx_fifo.rd_addr_gray_wr[5] -.sym 5690 rx_fifo.rd_addr[9] -.sym 5707 rx_fifo.rd_addr[9] -.sym 5720 rx_fifo.rd_addr_gray_wr[9] -.sym 5731 rx_fifo.rd_addr_gray[5] -.sym 5735 rx_fifo.rd_addr_gray_wr[5] -.sym 5752 lvds_clock_$glb_clk -.sym 5782 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 5801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5802 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 5809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5810 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 5813 w_lvds_rx_24_d1 -.sym 5834 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 5837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5840 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 5841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 5842 w_lvds_rx_24_d1 -.sym 5865 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 5867 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5874 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 5875 lvds_clock_$glb_clk -.sym 5885 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] -.sym 5893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 5920 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 5924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 5941 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5942 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 5944 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 5964 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 5966 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 5969 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 5972 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5988 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 5989 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 5995 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 5997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O -.sym 5998 lvds_clock_$glb_clk -.sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 6013 o_shdn_tx_lna$SB_IO_OUT -.sym 6014 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 6017 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 6044 w_lvds_rx_09_d1 -.sym 6049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 6054 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 6056 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 6071 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 6104 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 6106 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 6116 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 6117 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 6118 w_lvds_rx_09_d1 -.sym 6119 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 6120 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce -.sym 6121 lvds_clock_$glb_clk -.sym 6262 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 1496 r_counter +.sym 1544 tx_fifo.rd_addr_gray_wr[2] +.sym 1545 tx_fifo.rd_addr_gray_wr_r[6] +.sym 1546 tx_fifo.rd_addr_gray_wr[6] +.sym 1547 tx_fifo.rd_addr_gray_wr[7] +.sym 1548 tx_fifo.rd_addr_gray_wr[4] +.sym 1550 tx_fifo.rd_addr_gray_wr_r[4] +.sym 1570 tx_fifo.wr_addr[6] +.sym 1576 r_counter +.sym 1663 tx_fifo.rd_addr_gray_wr[5] +.sym 1691 tx_fifo.rd_addr_gray_wr_r[4] +.sym 1880 smi_ctrl_ins.d_byte[1] +.sym 1881 smi_ctrl_ins.d_byte[4] +.sym 1882 smi_ctrl_ins.d_byte[0] +.sym 1886 smi_ctrl_ins.d_byte[5] +.sym 1893 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 1895 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 1900 w_tx_fifo_pull +.sym 1901 lvds_tx_inst.r_tx_state +.sym 1914 w_smi_data_output[6] +.sym 1931 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E +.sym 1947 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] +.sym 1954 lvds_tx_inst.r_tx_state +.sym 1972 lvds_tx_inst.r_sync_count[3] +.sym 1973 $PACKER_VCC_NET +.sym 1978 lvds_tx_inst.r_sync_count[1] +.sym 1980 lvds_tx_inst.r_sync_count[3] +.sym 1982 i_rst_b_SB_LUT4_I3_O +.sym 1983 $PACKER_VCC_NET +.sym 1984 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 1990 lvds_tx_inst.r_sync_count[0] +.sym 1995 lvds_tx_inst.r_sync_count[2] +.sym 1996 lvds_tx_inst.frame_boundary +.sym 2001 $nextpnr_ICESTORM_LC_11$O +.sym 2003 lvds_tx_inst.r_sync_count[0] +.sym 2007 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] +.sym 2009 lvds_tx_inst.r_sync_count[1] +.sym 2010 $PACKER_VCC_NET +.sym 2013 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] +.sym 2014 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 2015 lvds_tx_inst.r_sync_count[2] +.sym 2016 $PACKER_VCC_NET +.sym 2017 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] +.sym 2020 lvds_tx_inst.r_sync_count[3] +.sym 2021 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 2022 $PACKER_VCC_NET +.sym 2023 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] +.sym 2032 lvds_tx_inst.r_sync_count[0] +.sym 2033 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 2044 lvds_tx_inst.r_sync_count[0] +.sym 2045 lvds_tx_inst.r_sync_count[1] +.sym 2046 lvds_tx_inst.r_sync_count[2] +.sym 2047 lvds_tx_inst.r_sync_count[3] +.sym 2048 lvds_tx_inst.frame_boundary +.sym 2049 lvds_clock_buf +.sym 2050 i_rst_b_SB_LUT4_I3_O +.sym 2069 lvds_tx_inst.r_fifo_data[3] +.sym 2070 lvds_tx_inst.r_fifo_data[13] +.sym 2071 smi_ctrl_ins.d_q3[1] +.sym 2076 lvds_tx_inst.r_sync_count[1] +.sym 2077 lvds_tx_inst.r_sync_count[0] +.sym 2078 w_rx_fifo_data[10] +.sym 2081 rx_fifo.wr_addr[9] +.sym 2082 i_rst_b_SB_LUT4_I3_O +.sym 2084 smi_ctrl_ins.d_byte[1] +.sym 2085 rx_fifo.wr_addr[4] +.sym 2086 smi_ctrl_ins.d_byte[4] +.sym 2091 smi_ctrl_ins.d_q3[0] +.sym 2099 smi_ctrl_ins.d_byte[1] +.sym 2101 smi_ctrl_ins.d_q3[4] +.sym 2105 lvds_tx_inst.r_fifo_data[3] +.sym 2111 lvds_tx_inst.frame_boundary +.sym 2112 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 2117 smi_ctrl_ins.d_byte[4] +.sym 2119 smi_ctrl_ins.d_byte[0] +.sym 2125 $PACKER_VCC_NET +.sym 2126 lvds_tx_inst.fifo_empty_d2 +.sym 2128 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2144 i_rst_b_SB_LUT4_I3_O +.sym 2154 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E +.sym 2158 $PACKER_VCC_NET +.sym 2162 lvds_tx_inst.r_gap_frame_count[2] +.sym 2163 lvds_tx_inst.r_gap_frame_count[3] +.sym 2165 i_rst_b_SB_LUT4_I3_O +.sym 2166 $PACKER_VCC_NET +.sym 2167 lvds_tx_inst.r_gap_frame_count[0] +.sym 2175 lvds_tx_inst.r_gap_frame_count[0] +.sym 2177 lvds_tx_inst.r_gap_frame_count[1] +.sym 2184 $nextpnr_ICESTORM_LC_5$O +.sym 2186 lvds_tx_inst.r_gap_frame_count[0] +.sym 2190 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] +.sym 2192 lvds_tx_inst.r_gap_frame_count[1] +.sym 2193 $PACKER_VCC_NET +.sym 2194 lvds_tx_inst.r_gap_frame_count[0] +.sym 2196 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] +.sym 2198 lvds_tx_inst.r_gap_frame_count[2] +.sym 2199 $PACKER_VCC_NET +.sym 2200 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] +.sym 2203 $PACKER_VCC_NET +.sym 2204 lvds_tx_inst.r_gap_frame_count[3] +.sym 2206 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] +.sym 2215 lvds_tx_inst.r_gap_frame_count[0] +.sym 2216 lvds_tx_inst.r_gap_frame_count[3] +.sym 2217 lvds_tx_inst.r_gap_frame_count[2] +.sym 2218 lvds_tx_inst.r_gap_frame_count[1] +.sym 2227 lvds_tx_inst.r_gap_frame_count[0] +.sym 2231 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E +.sym 2232 lvds_clock_buf +.sym 2233 i_rst_b_SB_LUT4_I3_O +.sym 2234 tx_wr_data[8] +.sym 2235 tx_wr_data[11] +.sym 2236 tx_wr_data[5] +.sym 2237 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[2] +.sym 2238 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[2] +.sym 2239 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[1] +.sym 2240 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[2] +.sym 2241 tx_wr_data[6] +.sym 2242 w_rx_fifo_pull +.sym 2244 w_tx_fifo_pulled_data[15] +.sym 2248 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 2250 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 2253 w_smi_data_direction +.sym 2259 i_rst_b_SB_LUT4_I3_O +.sym 2262 smi_ctrl_ins.d_byte[1] +.sym 2263 w_tx_fifo_pulled_data[29] +.sym 2265 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 2267 lvds_tx_inst.frame_boundary +.sym 2268 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 2272 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2274 w_smi_data_direction +.sym 2276 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E +.sym 2281 w_tx_fsm_state[1] +.sym 2290 lvds_tx_inst.frame_boundary +.sym 2291 w_tx_fifo_pulled_data[4] +.sym 2292 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2293 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 2295 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 2298 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 2299 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 2300 i_rst_b_SB_LUT4_I3_O +.sym 2302 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 2304 w_tx_fsm_state[0] +.sym 2305 w_tx_fifo_pulled_data[6] +.sym 2306 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[2] +.sym 2307 lvds_tx_inst.r_fifo_data[6] +.sym 2308 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[1] +.sym 2309 w_tx_fsm_state[0] +.sym 2310 w_tx_fsm_state[1] +.sym 2311 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[2] +.sym 2312 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 2314 lvds_tx_inst.frame_boundary +.sym 2315 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2316 w_tx_fifo_pulled_data[8] +.sym 2317 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2318 w_tx_fsm_state[1] +.sym 2320 lvds_tx_inst.r_fifo_data[6] +.sym 2321 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2322 w_tx_fifo_pulled_data[6] +.sym 2323 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2326 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2327 w_tx_fifo_pulled_data[4] +.sym 2328 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2329 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 2332 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 2333 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[1] +.sym 2334 w_tx_fsm_state[1] +.sym 2335 w_tx_fsm_state[0] +.sym 2338 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[2] +.sym 2340 w_tx_fsm_state[1] +.sym 2341 w_tx_fsm_state[0] +.sym 2345 w_tx_fsm_state[1] +.sym 2346 w_tx_fsm_state[0] +.sym 2347 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[2] +.sym 2350 lvds_tx_inst.frame_boundary +.sym 2352 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 2356 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 2357 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2358 w_tx_fifo_pulled_data[8] +.sym 2359 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2362 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 2363 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 2364 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2365 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 2366 lvds_tx_inst.frame_boundary +.sym 2367 lvds_clock_buf +.sym 2368 i_rst_b_SB_LUT4_I3_O +.sym 2369 tx_wr_data[22] +.sym 2370 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[2] +.sym 2371 tx_wr_data[1] +.sym 2372 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 2373 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2374 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[0] +.sym 2375 tx_wr_data[2] +.sym 2376 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 2382 w_rx_fifo_data[20] +.sym 2384 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 2386 smi_ctrl_ins.frame_sr[19] +.sym 2387 w_tx_fifo_pulled_data[31] +.sym 2389 rx_fifo.wr_addr[0] +.sym 2390 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 2391 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 2394 w_tx_fifo_pull +.sym 2395 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2398 w_tx_fsm_state[0] +.sym 2401 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 2406 lvds_tx_inst.tx_state_d1 +.sym 2408 lvds_tx_inst.r_tx_state_q +.sym 2409 w_tx_fifo_pulled_data[10] +.sym 2411 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2415 w_tx_fifo_pulled_data[31] +.sym 2423 lvds_tx_inst.r_fifo_data[15] +.sym 2424 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2426 lvds_tx_inst.r_fifo_data[6] +.sym 2427 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2428 w_tx_fifo_pulled_data[7] +.sym 2429 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2430 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 2434 lvds_tx_inst.r_fifo_data[14] +.sym 2435 i_rst_b_SB_LUT4_I3_O +.sym 2436 w_tx_fifo_pulled_data[5] +.sym 2437 lvds_tx_inst.r_fifo_data[7] +.sym 2438 w_tx_fsm_state[1] +.sym 2439 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[2] +.sym 2440 lvds_tx_inst.frame_boundary +.sym 2442 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2443 w_tx_fifo_pulled_data[15] +.sym 2445 lvds_tx_inst.r_fifo_data[7] +.sym 2446 w_tx_fsm_state[0] +.sym 2447 w_tx_fifo_pulled_data[29] +.sym 2448 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 2451 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2452 lvds_tx_inst.r_fifo_data[5] +.sym 2455 w_tx_fifo_pulled_data[29] +.sym 2456 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 2457 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2458 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2461 lvds_tx_inst.r_fifo_data[15] +.sym 2462 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2463 w_tx_fifo_pulled_data[15] +.sym 2464 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2467 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2468 lvds_tx_inst.r_fifo_data[15] +.sym 2469 lvds_tx_inst.r_fifo_data[7] +.sym 2473 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[2] +.sym 2475 w_tx_fsm_state[0] +.sym 2476 w_tx_fsm_state[1] +.sym 2479 lvds_tx_inst.r_fifo_data[6] +.sym 2480 lvds_tx_inst.r_fifo_data[14] +.sym 2481 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2482 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2485 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 2491 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2492 w_tx_fifo_pulled_data[5] +.sym 2493 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2494 lvds_tx_inst.r_fifo_data[5] +.sym 2497 lvds_tx_inst.r_fifo_data[7] +.sym 2498 w_tx_fifo_pulled_data[7] +.sym 2499 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2500 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2501 lvds_tx_inst.frame_boundary +.sym 2502 lvds_clock_buf +.sym 2503 i_rst_b_SB_LUT4_I3_O +.sym 2504 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] +.sym 2505 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[2] +.sym 2506 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 2507 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[1] +.sym 2508 lvds_tx_inst.frame_boundary +.sym 2509 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[3] +.sym 2510 $PACKER_GND_NET +.sym 2511 io_ctrl_ins.mixer_en_state +.sym 2514 w_tx_fifo_pulled_data[31] +.sym 2518 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2520 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 2521 lvds_tx_inst.r_tx_state +.sym 2525 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 2526 w_rx_fifo_data[23] +.sym 2528 lvds_tx_inst.r_tx_state +.sym 2529 lvds_tx_inst.frame_boundary +.sym 2530 lvds_tx_inst.r_fifo_data[22] +.sym 2532 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2533 w_tx_fifo_pulled_data[28] +.sym 2534 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2536 lvds_tx_inst.r_fifo_data[3] +.sym 2538 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2547 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] +.sym 2548 w_tx_fifo_pull +.sym 2557 w_smi_data_direction +.sym 2560 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 2569 $PACKER_VCC_NET +.sym 2570 i_rst_b_SB_LUT4_I3_O +.sym 2572 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2575 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 2578 lvds_tx_inst.r_tx_state +.sym 2582 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2583 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2584 $PACKER_VCC_NET +.sym 2585 lvds_tx_inst.frame_boundary +.sym 2589 $nextpnr_ICESTORM_LC_4$O +.sym 2592 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2595 lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 2597 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2598 $PACKER_VCC_NET +.sym 2599 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2601 lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[3] +.sym 2603 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2604 $PACKER_VCC_NET +.sym 2605 lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 2608 $PACKER_VCC_NET +.sym 2610 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 2611 lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[3] +.sym 2614 w_smi_data_direction +.sym 2622 lvds_tx_inst.r_tx_state +.sym 2626 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 2627 lvds_tx_inst.frame_boundary +.sym 2633 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 2637 lvds_clock_buf +.sym 2638 i_rst_b_SB_LUT4_I3_O +.sym 2639 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 2640 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] +.sym 2641 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 2642 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] +.sym 2643 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[1] +.sym 2644 w_rx_09_fifo_push +.sym 2646 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[3] +.sym 2647 rx_fifo.wr_addr[6] +.sym 2652 i_rst_b_SB_LUT4_I3_O +.sym 2655 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2656 i_rst_b_SB_LUT4_I3_O +.sym 2658 i_rst_b_SB_LUT4_I3_O +.sym 2659 i_button_SB_LUT4_I2_I1[2] +.sym 2661 io_ctrl_ins.rf_pin_state[0] +.sym 2663 w_rx_fifo_full +.sym 2664 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2665 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 2669 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2670 $PACKER_VCC_NET +.sym 2671 lvds_tx_inst.fifo_empty_d2 +.sym 2672 w_tx_fifo_pull +.sym 2674 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] +.sym 2675 i_rst_b_SB_LUT4_I3_O +.sym 2678 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2679 i_rst_b_SB_LUT4_I3_O +.sym 2680 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 2692 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 2693 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[2] +.sym 2694 w_tx_fsm_state[0] +.sym 2695 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] +.sym 2696 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 2700 w_tx_fifo_pulled_data[10] +.sym 2701 w_tx_fsm_state[1] +.sym 2703 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2709 w_tx_fifo_pulled_data[20] +.sym 2711 lvds_tx_inst.r_fifo_data[11] +.sym 2712 i_rst_b_SB_LUT4_I3_O +.sym 2714 w_tx_fifo_pulled_data[25] +.sym 2715 w_tx_fifo_pulled_data[0] +.sym 2716 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2717 w_tx_fifo_pulled_data[28] +.sym 2718 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 2719 lvds_tx_inst.frame_boundary +.sym 2721 w_tx_fifo_pulled_data[11] +.sym 2722 lvds_tx_inst.r_fifo_data[25] +.sym 2723 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 2725 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2726 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2727 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 2728 w_tx_fifo_pulled_data[20] +.sym 2731 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] +.sym 2732 w_tx_fsm_state[0] +.sym 2734 w_tx_fsm_state[1] +.sym 2737 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2738 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 2739 w_tx_fifo_pulled_data[28] +.sym 2740 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2743 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2744 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2745 lvds_tx_inst.r_fifo_data[11] +.sym 2746 w_tx_fifo_pulled_data[11] +.sym 2749 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 2750 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2751 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2752 w_tx_fifo_pulled_data[0] +.sym 2755 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[2] +.sym 2756 w_tx_fsm_state[0] +.sym 2758 w_tx_fsm_state[1] +.sym 2761 w_tx_fifo_pulled_data[25] +.sym 2762 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2763 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2764 lvds_tx_inst.r_fifo_data[25] +.sym 2767 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 2768 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 2769 w_tx_fifo_pulled_data[10] +.sym 2770 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2771 lvds_tx_inst.frame_boundary +.sym 2772 lvds_clock_buf +.sym 2773 i_rst_b_SB_LUT4_I3_O +.sym 2774 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 2776 w_tx_data_smi[2] +.sym 2777 w_tx_data_smi[4] +.sym 2778 w_tx_data_smi[1] +.sym 2779 w_rx_fifo_data[11] +.sym 2780 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 2781 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 2787 w_tx_fsm_state[1] +.sym 2788 w_tx_fsm_state[1] +.sym 2790 lvds_tx_inst.r_fifo_data[26] +.sym 2791 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] +.sym 2792 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 2793 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 2796 lvds_tx_inst.r_fifo_data[30] +.sym 2797 io_pmod_in[3]$SB_IO_IN +.sym 2799 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] +.sym 2800 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] +.sym 2801 w_tx_fifo_pull +.sym 2803 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 2804 w_rx_09_fifo_push +.sym 2805 lvds_tx_inst.frame_boundary +.sym 2807 i_rst_b_SB_LUT4_I3_O +.sym 2808 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 2811 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 2812 io_pmod_in[3]$SB_IO_IN +.sym 2815 w_lvds_tx_d0 +.sym 2827 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 2829 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[3] +.sym 2831 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 2832 lvds_tx_inst.r_fifo_data[17] +.sym 2833 lvds_tx_inst.r_fifo_data[25] +.sym 2834 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[2] +.sym 2835 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 2836 lvds_tx_inst.r_fifo_data[26] +.sym 2838 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] +.sym 2839 w_rx_sync_09 +.sym 2840 i_rst_b_SB_LUT4_I3_O +.sym 2841 w_lvds_tx_d0 +.sym 2842 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 2843 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 2845 lvds_tx_inst.r_fifo_data[18] +.sym 2846 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2847 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 2848 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2849 io_pmod_in[3]$SB_IO_IN +.sym 2850 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 2853 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 2854 lvds_rx_09_inst.r_sync_input_SB_DFFER_Q_E +.sym 2855 w_rx_sync_type_09 +.sym 2856 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 2857 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] +.sym 2858 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 2861 w_lvds_tx_d0 +.sym 2866 w_rx_sync_type_09 +.sym 2868 w_rx_sync_09 +.sym 2869 io_pmod_in[3]$SB_IO_IN +.sym 2872 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 2873 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2874 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 2875 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 2878 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 2879 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 2880 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] +.sym 2881 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 2884 lvds_tx_inst.r_fifo_data[18] +.sym 2885 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2886 lvds_tx_inst.r_fifo_data[26] +.sym 2887 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 2890 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2891 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] +.sym 2892 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[2] +.sym 2893 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[3] +.sym 2896 lvds_tx_inst.r_fifo_data[25] +.sym 2897 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2898 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 2899 lvds_tx_inst.r_fifo_data[17] +.sym 2902 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 2903 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 2904 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 2905 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 2906 lvds_rx_09_inst.r_sync_input_SB_DFFER_Q_E +.sym 2907 lvds_clock_buf +.sym 2908 i_rst_b_SB_LUT4_I3_O +.sym 2909 lvds_tx_inst.r_fifo_data[19] +.sym 2910 lvds_tx_inst.r_fifo_data[27] +.sym 2911 lvds_tx_inst.r_fifo_data[18] +.sym 2912 lvds_rx_09_inst.r_sync_input_SB_DFFER_Q_E +.sym 2913 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 2914 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 2915 lvds_tx_inst.r_fifo_data[9] +.sym 2916 lvds_tx_inst.r_fifo_data[1] +.sym 2921 iq_tx_p_D_OUT_1 +.sym 2922 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2924 w_tx_data_smi[4] +.sym 2926 tx_fifo.wr_addr[4] +.sym 2928 w_rx_24_fifo_data[11] +.sym 2930 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 2931 lvds_tx_inst.r_tx_state_q +.sym 2932 w_tx_data_smi[2] +.sym 2934 w_tx_fifo_pull +.sym 2935 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 2936 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 2937 channel +.sym 2940 tx_fifo.rd_addr[5] +.sym 2941 w_rx_fifo_full +.sym 2944 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 2945 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 2946 lvds_tx_inst.tx_state_d1 +.sym 2948 w_tx_fifo_pulled_data[10] +.sym 2964 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 2965 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[2] +.sym 2966 i_rst_b_SB_LUT4_I3_O +.sym 2971 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 2972 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 2973 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 2975 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[0] +.sym 2976 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 2977 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 2978 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 2979 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 2980 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] +.sym 2982 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 2983 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] +.sym 2984 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] +.sym 2988 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 2991 lvds_tx_inst.fifo_empty_d1 +.sym 2992 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 2995 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 2996 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 2997 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 2998 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 3007 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 3008 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 3009 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 3010 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 3013 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 3014 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[0] +.sym 3016 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] +.sym 3021 lvds_tx_inst.fifo_empty_d1 +.sym 3026 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 3031 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 3032 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[2] +.sym 3033 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] +.sym 3034 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] +.sym 3042 lvds_clock_buf +.sym 3043 i_rst_b_SB_LUT4_I3_O +.sym 3044 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 3045 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 3046 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 3047 w_rx_fifo_push +.sym 3049 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 3050 tx_fifo.rd_addr[6] +.sym 3051 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 3052 channel +.sym 3055 channel +.sym 3059 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 3061 w_tx_fifo_pull +.sym 3063 tx_fifo.rd_addr[4] +.sym 3064 w_lvds_tx_d1 +.sym 3066 lvds_tx_inst.fifo_empty_d2 +.sym 3067 w_tx_fifo_pull +.sym 3068 tx_fifo.rd_addr[4] +.sym 3069 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 3072 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3074 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 3076 tx_fifo.wr_addr[8] +.sym 3077 channel +.sym 3078 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 3079 lvds_tx_inst.r_tx_state +.sym 3080 r_counter +.sym 3084 tx_fifo.rd_addr[4] +.sym 3103 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3107 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3108 w_lvds_tx_d1 +.sym 3110 i_rst_b_SB_LUT4_I3_O +.sym 3116 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 3118 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 3122 tx_fifo.rd_addr[5] +.sym 3124 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 3125 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 3127 tx_fifo.rd_addr[6] +.sym 3132 w_lvds_tx_d1 +.sym 3138 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 3143 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3144 tx_fifo.rd_addr[5] +.sym 3145 tx_fifo.rd_addr[6] +.sym 3150 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 3155 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 3160 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3161 tx_fifo.rd_addr[5] +.sym 3162 tx_fifo.rd_addr[6] +.sym 3168 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3176 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 3177 lvds_clock_buf +.sym 3178 i_rst_b_SB_LUT4_I3_O +.sym 3180 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 3181 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 3182 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 3183 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 3184 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 3185 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3186 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3187 $PACKER_VCC_NET +.sym 3192 w_rx_24_fifo_push +.sym 3194 w_rx_fifo_push +.sym 3195 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3197 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 3199 tx_fifo.wr_addr[2] +.sym 3200 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 3202 i_rst_b_SB_LUT4_I3_O +.sym 3203 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 3204 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 3205 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 3206 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 3208 tx_fifo.rd_addr[9] +.sym 3209 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 3210 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3211 tx_fifo.rd_addr[6] +.sym 3212 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3213 w_tx_fifo_pull +.sym 3214 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 3215 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 3218 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3222 tx_fifo.wr_addr_gray_rd[7] +.sym 3223 w_rx_data[0] +.sym 3224 i_rst_b_SB_LUT4_I3_O +.sym 3232 tx_fifo.wr_addr_gray_rd_r[6] +.sym 3234 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 3235 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3236 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 3237 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[1] +.sym 3238 tx_fifo.rd_addr[6] +.sym 3239 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 3240 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 3241 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 3242 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 3243 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 3244 tx_fifo.rd_addr[9] +.sym 3245 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 3246 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 3247 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[3] +.sym 3248 w_lvds_rx_09_d0 +.sym 3249 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 3251 w_tx_fifo_pull +.sym 3252 w_rx_data[0] +.sym 3253 w_lvds_rx_09_d1 +.sym 3254 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 3255 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3257 r_counter +.sym 3259 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[0] +.sym 3261 i_rst_b_SB_LUT4_I3_O +.sym 3262 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3263 tx_fifo.wr_addr_gray_rd_r[9] +.sym 3265 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[3] +.sym 3266 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[1] +.sym 3267 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 3268 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 3271 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3272 w_lvds_rx_09_d0 +.sym 3273 w_lvds_rx_09_d1 +.sym 3279 w_rx_data[0] +.sym 3284 tx_fifo.wr_addr_gray_rd_r[6] +.sym 3286 tx_fifo.rd_addr[6] +.sym 3289 tx_fifo.wr_addr_gray_rd_r[6] +.sym 3290 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3292 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3295 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 3296 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 3297 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 3298 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[0] +.sym 3301 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 3302 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 3303 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 3304 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 3307 w_tx_fifo_pull +.sym 3308 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 3309 tx_fifo.rd_addr[9] +.sym 3310 tx_fifo.wr_addr_gray_rd_r[9] +.sym 3311 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 3312 r_counter +.sym 3313 i_rst_b_SB_LUT4_I3_O +.sym 3314 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 3315 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 3316 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 3317 tx_fifo.wr_addr_gray_rd[9] +.sym 3318 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 3319 tx_fifo.wr_addr_gray_rd[2] +.sym 3320 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 3321 tx_fifo.wr_addr_gray_rd_r[9] +.sym 3326 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 3327 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3329 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3330 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 3331 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3332 channel +.sym 3337 tx_wr_data[3] +.sym 3340 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 3342 w_tx_fifo_pull +.sym 3343 i_rst_b_SB_LUT4_I3_O +.sym 3346 tx_fifo.wr_addr[5] +.sym 3350 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 3352 tx_fifo.wr_addr_gray_rd[3] +.sym 3356 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3358 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3368 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] +.sym 3370 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 3371 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 3372 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 3373 tx_fifo.wr_addr_gray_rd[6] +.sym 3374 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3378 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 3379 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 3381 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3382 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 3383 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 3387 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 3388 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 3389 tx_fifo.wr_addr_gray_rd[3] +.sym 3393 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 3395 tx_fifo.wr_addr_gray_rd_r[3] +.sym 3396 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3397 tx_fifo.wr_addr_gray_rd[7] +.sym 3402 tx_fifo.wr_addr_gray_rd[6] +.sym 3406 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3408 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 3412 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 3413 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3418 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 3419 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 3420 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 3421 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 3424 tx_fifo.wr_addr_gray_rd[3] +.sym 3430 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 3431 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 3432 tx_fifo.wr_addr_gray_rd_r[3] +.sym 3439 tx_fifo.wr_addr_gray_rd[7] +.sym 3442 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] +.sym 3443 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 3444 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 3445 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3447 lvds_clock_buf +.sym 3449 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 3451 tx_fifo.rd_addr_gray[3] +.sym 3453 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 3454 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 3458 lvds_tx_inst.r_tx_state +.sym 3461 tx_fifo.wr_addr[4] +.sym 3463 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 3465 w_tx_fifo_pulled_data[10] +.sym 3466 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 3469 lvds_tx_inst.tx_state_d1 +.sym 3470 tx_fifo.wr_addr[7] +.sym 3473 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 3474 w_tx_fifo_pull +.sym 3475 tx_fifo.rd_addr_gray_wr_r[3] +.sym 3476 tx_fifo.rd_addr[5] +.sym 3481 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 3482 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 3484 tx_fifo.wr_addr_gray[2] +.sym 3502 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 3503 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3504 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 3505 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 3506 tx_fifo.rd_addr_gray_wr[3] +.sym 3508 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 3510 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 3511 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3512 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 3513 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 3514 tx_fifo.wr_addr_gray_rd_r[3] +.sym 3515 tx_fifo.rd_addr[4] +.sym 3516 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 3518 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3520 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 3526 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 3527 r_counter +.sym 3528 tx_fifo.rd_addr_gray[3] +.sym 3530 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 3535 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 3538 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 3541 tx_fifo.wr_addr_gray_rd_r[3] +.sym 3542 tx_fifo.rd_addr[4] +.sym 3543 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 3548 tx_fifo.rd_addr_gray[3] +.sym 3559 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 3560 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 3561 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3562 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 3566 tx_fifo.rd_addr_gray_wr[3] +.sym 3571 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 3572 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 3573 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 3574 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 3577 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 3578 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 3580 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3582 r_counter +.sym 3584 tx_fifo.wr_addr_gray[7] +.sym 3586 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 3588 tx_fifo.wr_addr_gray[4] +.sym 3589 tx_fifo.wr_addr_gray[1] +.sym 3590 tx_fifo.wr_addr_gray[3] +.sym 3598 tx_fifo.rd_addr_gray_wr_r[3] +.sym 3601 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 3602 tx_fifo.rd_addr_gray_wr[3] +.sym 3603 tx_fifo.rd_addr[4] +.sym 3606 r_counter +.sym 3616 tx_fifo.wr_addr[8] +.sym 3625 r_counter +.sym 3637 tx_fifo.wr_addr_gray_rd[5] +.sym 3645 tx_fifo.wr_addr_gray[8] +.sym 3648 tx_fifo.wr_addr_gray[5] +.sym 3653 tx_fifo.wr_addr_gray[7] +.sym 3655 tx_fifo.wr_addr_gray_rd[8] +.sym 3657 tx_fifo.wr_addr_gray_rd[4] +.sym 3665 tx_fifo.wr_addr_gray[4] +.sym 3667 tx_fifo.wr_addr_gray[3] +.sym 3672 tx_fifo.wr_addr_gray[5] +.sym 3677 tx_fifo.wr_addr_gray_rd[5] +.sym 3683 tx_fifo.wr_addr_gray[8] +.sym 3689 tx_fifo.wr_addr_gray[7] +.sym 3695 tx_fifo.wr_addr_gray[4] +.sym 3701 tx_fifo.wr_addr_gray_rd[8] +.sym 3706 tx_fifo.wr_addr_gray_rd[4] +.sym 3712 tx_fifo.wr_addr_gray[3] +.sym 3717 lvds_clock_buf +.sym 3721 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 3723 i_rst_b_SB_LUT4_I3_O +.sym 3724 tx_fifo.wr_addr_gray[2] +.sym 3732 i_rst_b_SB_LUT4_I3_O +.sym 3734 tx_fifo.wr_addr[8] +.sym 3736 tx_fifo.wr_addr_gray[5] +.sym 3739 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 3740 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 3741 tx_fifo.wr_addr_gray[8] +.sym 3742 w_rx_data[0] +.sym 3743 tx_fifo.rd_addr[9] +.sym 3746 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 3749 w_tx_fifo_pull +.sym 3750 tx_fifo.rd_addr_gray_wr_r[6] +.sym 3751 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 3752 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 3754 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 3773 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 3774 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 3781 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3787 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3789 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 3792 i_rst_b_SB_LUT4_I3_O +.sym 3818 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 3824 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 3826 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 3849 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 3851 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 3852 lvds_clock_buf +.sym 3853 i_rst_b_SB_LUT4_I3_O +.sym 3855 tx_fifo.rd_addr_gray[2] +.sym 3856 tx_fifo.rd_addr_gray[1] +.sym 3857 tx_fifo.rd_addr_gray[0] +.sym 3858 tx_fifo.rd_addr_gray[5] +.sym 3859 tx_fifo.rd_addr_gray[8] +.sym 3860 tx_fifo.rd_addr[9] +.sym 3863 w_tx_fifo_pulled_data[15] +.sym 3871 tx_wr_data[21] +.sym 3878 tx_fifo.rd_addr_gray_wr_r[2] +.sym 3879 i_rst_b_SB_LUT4_I3_O +.sym 3909 tx_fifo.rd_addr_gray[7] +.sym 3910 tx_fifo.rd_addr_gray[6] +.sym 3914 tx_fifo.rd_addr_gray[4] +.sym 3916 r_counter +.sym 3917 tx_fifo.rd_addr_gray_wr[6] +.sym 3932 tx_fifo.rd_addr_gray[2] +.sym 3935 tx_fifo.rd_addr_gray_wr[4] +.sym 3940 tx_fifo.rd_addr_gray[2] +.sym 3946 tx_fifo.rd_addr_gray_wr[6] +.sym 3955 tx_fifo.rd_addr_gray[6] +.sym 3961 tx_fifo.rd_addr_gray[7] +.sym 3965 tx_fifo.rd_addr_gray[4] +.sym 3979 tx_fifo.rd_addr_gray_wr[4] +.sym 3987 r_counter +.sym 3989 tx_fifo.rd_addr_gray_wr[9] +.sym 3992 tx_fifo.rd_addr_gray_wr[1] +.sym 3993 tx_fifo.rd_addr_gray_wr[0] +.sym 3995 tx_fifo.rd_addr_gray_wr_r[2] +.sym 3996 tx_fifo.rd_addr_gray_wr[8] +.sym 4005 tx_fifo.rd_addr_gray_wr_r[6] +.sym 4009 tx_fifo.rd_addr_gray_wr[7] +.sym 4011 tx_wr_data[14] +.sym 4022 tx_fifo.rd_addr_gray_wr_r[4] +.sym 4042 r_counter +.sym 4046 tx_fifo.rd_addr_gray[5] +.sym 4108 tx_fifo.rd_addr_gray[5] +.sym 4122 r_counter +.sym 4141 w_tx_fifo_pulled_data[31] +.sym 4145 tx_fifo.rd_addr_gray_wr_r[2] +.sym 4146 tx_fifo.rd_addr_gray_wr[5] +.sym 4147 r_counter +.sym 4149 tx_fifo.rd_addr_gray_wr[8] +.sym 4150 r_counter +.sym 4151 tx_fifo.rd_addr_gray_wr[9] +.sym 4154 r_counter +.sym 4238 w_rx_fifo_pulled_data[8] +.sym 4242 w_rx_fifo_pulled_data[10] +.sym 4247 w_tx_fsm_state[1] +.sym 4252 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4253 lvds_tx_inst.frame_boundary +.sym 4258 tx_wr_data[8] +.sym 4267 i_rst_b_SB_LUT4_I3_O +.sym 4279 smi_ctrl_ins.d_q3[5] +.sym 4282 smi_ctrl_ins.d_q3[1] +.sym 4283 smi_ctrl_ins.d_q3[0] +.sym 4290 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 4292 smi_ctrl_ins.d_q3[4] +.sym 4304 r_counter +.sym 4320 smi_ctrl_ins.d_q3[1] +.sym 4324 smi_ctrl_ins.d_q3[4] +.sym 4333 smi_ctrl_ins.d_q3[0] +.sym 4355 smi_ctrl_ins.d_q3[5] +.sym 4358 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 4359 r_counter +.sym 4366 w_rx_fifo_pulled_data[9] +.sym 4370 w_rx_fifo_pulled_data[11] +.sym 4373 smi_ctrl_ins.d_q3[5] +.sym 4378 rx_fifo.wr_addr[8] +.sym 4380 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 4381 rx_fifo.wr_addr[3] +.sym 4382 rx_fifo.wr_addr[2] +.sym 4384 rx_fifo.wr_addr[6] +.sym 4385 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] +.sym 4386 w_rx_fifo_pulled_data[8] +.sym 4388 rx_fifo.wr_addr[0] +.sym 4396 smi_ctrl_ins.d_byte[5] +.sym 4400 smi_ctrl_ins.d_byte[1] +.sym 4405 smi_ctrl_ins.d_byte[0] +.sym 4408 w_rx_fifo_data[11] +.sym 4414 smi_ctrl_ins.d_byte[0] +.sym 4415 w_tx_fsm_state[0] +.sym 4418 smi_ctrl_ins.d_byte[1] +.sym 4419 w_rx_fifo_data[22] +.sym 4420 w_tx_fsm_state[0] +.sym 4422 tx_wr_data[6] +.sym 4425 r_counter +.sym 4426 lvds_tx_inst.r_fifo_data[13] +.sym 4427 tx_wr_data[11] +.sym 4429 tx_wr_data[5] +.sym 4431 smi_ctrl_ins.d_byte[5] +.sym 4434 smi_ctrl_ins.d_byte[0] +.sym 4446 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[2] +.sym 4453 lvds_tx_inst.frame_boundary +.sym 4456 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[2] +.sym 4459 w_tx_fsm_state[1] +.sym 4462 i_rst_b_SB_LUT4_I3_O +.sym 4471 w_tx_fsm_state[0] +.sym 4512 w_tx_fsm_state[1] +.sym 4513 w_tx_fsm_state[0] +.sym 4514 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[2] +.sym 4518 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[2] +.sym 4519 w_tx_fsm_state[1] +.sym 4520 w_tx_fsm_state[0] +.sym 4521 lvds_tx_inst.frame_boundary +.sym 4522 lvds_clock_buf +.sym 4523 i_rst_b_SB_LUT4_I3_O +.sym 4525 w_rx_fifo_pulled_data[20] +.sym 4529 w_rx_fifo_pulled_data[22] +.sym 4533 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 4537 smi_ctrl_ins.d_q3[0] +.sym 4540 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 4541 smi_ctrl_ins.d_q3[4] +.sym 4542 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 4547 w_rx_fifo_data[9] +.sym 4550 w_rx_fifo_push +.sym 4551 lvds_tx_inst.r_fifo_data[23] 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smi_ctrl_ins.frame_sr[19] +.sym 4611 smi_ctrl_ins.d_byte[4] +.sym 4616 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 4617 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4618 w_tx_fifo_pulled_data[12] +.sym 4619 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4622 w_tx_fifo_pulled_data[13] +.sym 4623 lvds_tx_inst.r_fifo_data[13] +.sym 4624 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4625 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4628 lvds_tx_inst.r_fifo_data[31] +.sym 4629 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4630 w_tx_fifo_pulled_data[31] +.sym 4631 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4634 w_tx_fifo_pulled_data[3] +.sym 4635 lvds_tx_inst.r_fifo_data[3] +.sym 4636 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4637 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4643 smi_ctrl_ins.d_byte[5] +.sym 4644 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 4645 r_counter +.sym 4646 i_rst_b_SB_LUT4_I3_O +.sym 4648 w_rx_fifo_pulled_data[21] +.sym 4652 w_rx_fifo_pulled_data[23] +.sym 4661 smi_ctrl_ins.frame_sr[20] +.sym 4662 rx_fifo.wr_addr[8] +.sym 4663 rx_fifo.wr_addr[2] +.sym 4665 rx_fifo.wr_addr[6] +.sym 4666 w_tx_fifo_pulled_data[12] +.sym 4667 smi_ctrl_ins.frame_sr[17] +.sym 4668 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 4671 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4673 rx_fifo.rd_addr[0] +.sym 4675 tx_wr_data[2] +.sym 4676 lvds_tx_inst.sent_first_sync +.sym 4677 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 4678 w_tx_fifo_pulled_data[3] +.sym 4679 tx_wr_data[22] +.sym 4680 rx_fifo.rd_addr[8] +.sym 4681 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 4682 lvds_tx_inst.r_fifo_data[24] +.sym 4688 smi_ctrl_ins.d_byte[1] +.sym 4689 lvds_tx_inst.fifo_empty_d2 +.sym 4690 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 4691 smi_ctrl_ins.d_byte[0] +.sym 4693 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4694 lvds_tx_inst.r_tx_state +.sym 4696 w_tx_fsm_state[0] +.sym 4697 r_counter +.sym 4698 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[1] +.sym 4699 lvds_tx_inst.r_fifo_data[16] +.sym 4700 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4701 i_rst_b_SB_LUT4_I3_O +.sym 4702 lvds_tx_inst.r_fifo_data[5] +.sym 4703 lvds_tx_inst.r_fifo_data[13] +.sym 4706 lvds_tx_inst.r_fifo_data[31] +.sym 4709 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[0] +.sym 4711 lvds_tx_inst.r_fifo_data[23] +.sym 4713 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 4714 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4715 w_tx_fifo_pulled_data[16] +.sym 4717 w_tx_fsm_state[1] +.sym 4718 smi_ctrl_ins.frame_sr[12] +.sym 4719 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4724 smi_ctrl_ins.frame_sr[12] +.sym 4727 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4728 lvds_tx_inst.r_fifo_data[16] +.sym 4729 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4730 w_tx_fifo_pulled_data[16] +.sym 4736 smi_ctrl_ins.d_byte[0] +.sym 4739 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[1] +.sym 4740 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 4741 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[0] +.sym 4742 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4745 lvds_tx_inst.r_tx_state +.sym 4746 lvds_tx_inst.fifo_empty_d2 +.sym 4747 w_tx_fsm_state[1] +.sym 4748 w_tx_fsm_state[0] +.sym 4751 lvds_tx_inst.r_fifo_data[5] +.sym 4752 lvds_tx_inst.r_fifo_data[13] +.sym 4753 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4759 smi_ctrl_ins.d_byte[1] +.sym 4763 lvds_tx_inst.r_fifo_data[23] +.sym 4764 lvds_tx_inst.r_fifo_data[31] +.sym 4765 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4766 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4767 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 4768 r_counter +.sym 4769 i_rst_b_SB_LUT4_I3_O +.sym 4771 w_rx_fifo_pulled_data[12] +.sym 4775 w_rx_fifo_pulled_data[14] +.sym 4782 rx_fifo.rd_addr[3] +.sym 4787 smi_ctrl_ins.d_byte[0] +.sym 4788 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 4790 rx_fifo.rd_addr[8] +.sym 4791 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 4793 r_counter +.sym 4794 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 4795 tx_wr_data[1] +.sym 4797 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 4798 w_tx_fifo_pulled_data[8] +.sym 4799 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4800 io_ctrl_ins.mixer_en_state +.sym 4801 w_tx_fifo_pulled_data[16] +.sym 4802 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 4804 w_rx_fifo_data[11] +.sym 4805 w_tx_fifo_pulled_data[6] +.sym 4812 w_tx_fsm_state[0] +.sym 4813 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 4814 i_button_SB_LUT4_I2_I1[2] +.sym 4815 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 4817 w_tx_fifo_pulled_data[17] +.sym 4818 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4820 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 4821 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4822 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 4823 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4824 io_ctrl_ins.rf_pin_state[0] +.sym 4825 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 4826 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 4827 r_counter +.sym 4828 lvds_tx_inst.r_tx_state +.sym 4829 w_tx_fsm_state[1] +.sym 4830 lvds_tx_inst.r_fifo_data[16] +.sym 4832 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4833 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 4836 lvds_tx_inst.sent_first_sync +.sym 4837 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 4838 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[1] +.sym 4839 lvds_tx_inst.fifo_empty_d2 +.sym 4840 lvds_tx_inst.r_fifo_data[17] +.sym 4841 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 4842 lvds_tx_inst.r_fifo_data[24] +.sym 4844 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 4845 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4846 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 4847 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 4850 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 4851 lvds_tx_inst.r_fifo_data[17] +.sym 4852 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 4853 w_tx_fifo_pulled_data[17] +.sym 4857 lvds_tx_inst.r_tx_state +.sym 4858 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[1] +.sym 4859 lvds_tx_inst.fifo_empty_d2 +.sym 4862 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 4863 w_tx_fsm_state[1] +.sym 4864 w_tx_fsm_state[0] +.sym 4865 lvds_tx_inst.sent_first_sync +.sym 4868 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 4870 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 4871 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4874 lvds_tx_inst.r_fifo_data[16] +.sym 4875 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 4876 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4877 lvds_tx_inst.r_fifo_data[24] +.sym 4886 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 4887 io_ctrl_ins.rf_pin_state[0] +.sym 4888 i_button_SB_LUT4_I2_I1[2] +.sym 4889 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 4890 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 4891 r_counter +.sym 4894 w_rx_fifo_pulled_data[13] +.sym 4898 w_rx_fifo_pulled_data[15] +.sym 4901 i_rst_b_SB_LUT4_I3_O +.sym 4902 rx_fifo.wr_addr[4] +.sym 4904 i_rst_b_SB_LUT4_I3_O +.sym 4905 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] +.sym 4907 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 4908 w_tx_fifo_full +.sym 4909 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 4911 w_tx_fifo_pulled_data[29] +.sym 4913 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 4914 w_rx_09_fifo_data[10] +.sym 4915 lvds_tx_inst.frame_boundary +.sym 4916 rx_fifo.wr_addr[0] +.sym 4917 r_counter +.sym 4918 w_tx_fifo_pulled_data[27] +.sym 4919 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 4920 tx_wr_data[6] +.sym 4921 r_counter +.sym 4922 lvds_tx_inst.frame_boundary +.sym 4923 w_tx_fifo_full +.sym 4924 tx_wr_data[11] +.sym 4925 w_tx_fifo_pulled_data[19] +.sym 4926 tx_wr_data[5] +.sym 4927 tx_wr_data[7] +.sym 4928 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 4934 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 4936 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 4938 i_rst_b_SB_LUT4_I3_O +.sym 4939 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[3] +.sym 4940 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 4941 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[3] +.sym 4942 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 4944 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 4945 lvds_tx_inst.r_fifo_data[11] +.sym 4946 lvds_tx_inst.r_fifo_data[3] +.sym 4947 lvds_tx_inst.r_fifo_data[30] +.sym 4948 lvds_tx_inst.r_fifo_data[22] +.sym 4950 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 4951 w_rx_fifo_full +.sym 4952 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 4954 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[2] +.sym 4957 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 4959 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 4960 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4961 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 4962 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[1] +.sym 4965 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4967 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 4969 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4973 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[3] +.sym 4974 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 4975 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[1] +.sym 4976 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[2] +.sym 4979 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 4980 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 4981 lvds_tx_inst.r_fifo_data[11] +.sym 4982 lvds_tx_inst.r_fifo_data[3] +.sym 4985 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 4986 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 4987 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 4988 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 4991 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 4992 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[3] +.sym 4993 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 4994 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 4997 w_rx_fifo_full +.sym 4998 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 5009 lvds_tx_inst.r_fifo_data[22] +.sym 5010 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 5011 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 5012 lvds_tx_inst.r_fifo_data[30] +.sym 5013 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 5014 lvds_clock_buf +.sym 5015 i_rst_b_SB_LUT4_I3_O +.sym 5017 w_tx_fifo_pulled_data[4] +.sym 5021 w_tx_fifo_pulled_data[6] +.sym 5025 w_tx_fsm_state[1] +.sym 5028 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 5030 channel +.sym 5031 w_tx_fsm_state[0] +.sym 5032 w_rx_fifo_full +.sym 5033 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5034 i_rst_b_SB_LUT4_I3_O +.sym 5035 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 5039 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 5040 r_counter +.sym 5041 lvds_tx_inst.frame_boundary +.sym 5042 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5044 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 5045 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 5046 w_rx_fifo_push +.sym 5049 rx_fifo.rd_addr[3] +.sym 5051 w_tx_fifo_pulled_data[9] +.sym 5057 w_rx_24_fifo_data[11] +.sym 5058 lvds_tx_inst.r_fifo_data[27] +.sym 5060 w_rx_09_fifo_data[11] +.sym 5062 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 5063 lvds_tx_inst.r_fifo_data[9] +.sym 5064 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 5065 lvds_tx_inst.r_fifo_data[19] +.sym 5066 r_counter +.sym 5068 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 5070 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 5071 w_smi_data_direction +.sym 5072 lvds_tx_inst.r_fifo_data[1] +.sym 5076 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 5080 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 5081 channel +.sym 5083 w_tx_fifo_full +.sym 5084 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 5086 i_rst_b_SB_LUT4_I3_O +.sym 5091 lvds_tx_inst.r_fifo_data[27] +.sym 5092 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 5093 lvds_tx_inst.r_fifo_data[19] +.sym 5103 channel +.sym 5105 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 5108 w_smi_data_direction +.sym 5110 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 5115 w_tx_fifo_full +.sym 5117 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 5120 w_rx_09_fifo_data[11] +.sym 5121 w_rx_24_fifo_data[11] +.sym 5122 channel +.sym 5126 lvds_tx_inst.r_fifo_data[9] +.sym 5127 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 5128 lvds_tx_inst.r_fifo_data[1] +.sym 5129 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 5134 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 5135 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 5136 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 5137 r_counter +.sym 5138 i_rst_b_SB_LUT4_I3_O +.sym 5140 w_tx_fifo_pulled_data[5] +.sym 5144 w_tx_fifo_pulled_data[7] +.sym 5147 w_rx_09_fifo_data[0] +.sym 5150 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 5151 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 5152 tx_fifo.rd_addr[4] +.sym 5153 lvds_tx_inst.r_fifo_data[22] +.sym 5154 w_tx_fifo_pulled_data[28] +.sym 5155 tx_fifo.wr_addr[5] +.sym 5156 w_rx_09_fifo_data[11] +.sym 5158 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 5159 lvds_tx_inst.frame_boundary +.sym 5161 channel +.sym 5162 tx_fifo.wr_addr[8] +.sym 5164 tx_fifo.rd_addr[6] +.sym 5165 w_tx_fifo_pulled_data[20] +.sym 5166 w_tx_fifo_pulled_data[1] +.sym 5167 w_tx_fifo_pulled_data[11] +.sym 5168 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5169 w_tx_fifo_pulled_data[0] +.sym 5171 tx_wr_data[22] +.sym 5172 tx_wr_data[2] +.sym 5174 w_tx_fifo_pulled_data[3] +.sym 5180 lvds_tx_inst.r_fifo_data[19] +.sym 5182 w_tx_fifo_pulled_data[1] +.sym 5185 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 5187 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5188 w_tx_fifo_pulled_data[27] +.sym 5189 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 5190 lvds_tx_inst.r_fifo_data[18] +.sym 5191 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 5193 i_rst_b_SB_LUT4_I3_O +.sym 5194 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 5196 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5197 w_tx_fifo_pulled_data[19] +.sym 5199 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 5200 w_tx_fifo_pulled_data[18] +.sym 5201 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 5203 lvds_tx_inst.r_fifo_data[1] +.sym 5204 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 5205 lvds_tx_inst.r_fifo_data[27] +.sym 5207 lvds_tx_inst.frame_boundary +.sym 5209 w_tx_fifo_pulled_data[2] +.sym 5210 lvds_tx_inst.r_fifo_data[9] +.sym 5211 w_tx_fifo_pulled_data[9] +.sym 5213 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5214 w_tx_fifo_pulled_data[19] +.sym 5215 lvds_tx_inst.r_fifo_data[19] +.sym 5216 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5219 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5220 lvds_tx_inst.r_fifo_data[27] +.sym 5221 w_tx_fifo_pulled_data[27] +.sym 5222 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5225 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5226 lvds_tx_inst.r_fifo_data[18] +.sym 5227 w_tx_fifo_pulled_data[18] +.sym 5228 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5231 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 5233 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 5237 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 5238 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 5239 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 5240 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 5243 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5244 w_tx_fifo_pulled_data[2] +.sym 5245 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 5246 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5249 w_tx_fifo_pulled_data[9] +.sym 5250 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5251 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5252 lvds_tx_inst.r_fifo_data[9] +.sym 5255 lvds_tx_inst.r_fifo_data[1] +.sym 5256 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 5257 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 5258 w_tx_fifo_pulled_data[1] +.sym 5259 lvds_tx_inst.frame_boundary +.sym 5260 lvds_clock_buf +.sym 5261 i_rst_b_SB_LUT4_I3_O +.sym 5263 w_tx_fifo_pulled_data[0] +.sym 5267 w_tx_fifo_pulled_data[2] +.sym 5272 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 5273 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 5274 w_rx_24_fifo_data[1] +.sym 5275 $PACKER_VCC_NET +.sym 5278 w_tx_fifo_pull +.sym 5280 $PACKER_VCC_NET +.sym 5283 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 5286 w_tx_fifo_pulled_data[18] +.sym 5288 tx_wr_data[1] +.sym 5289 w_tx_fifo_pulled_data[8] +.sym 5290 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 5291 w_rx_sync_type_09 +.sym 5292 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5293 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 5294 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 5295 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 5297 w_tx_fifo_pulled_data[16] +.sym 5304 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 5305 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 5307 i_rst_b_SB_LUT4_I3_O +.sym 5308 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 5310 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 5313 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 5314 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5315 w_rx_24_fifo_push +.sym 5317 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 5318 w_rx_09_fifo_push +.sym 5321 channel +.sym 5329 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5334 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5336 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 5337 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 5338 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5339 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5343 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5344 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5345 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 5349 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 5354 w_rx_24_fifo_push +.sym 5355 w_rx_09_fifo_push +.sym 5357 channel +.sym 5368 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 5375 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 5378 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 5382 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5383 lvds_clock_buf +.sym 5384 i_rst_b_SB_LUT4_I3_O +.sym 5386 w_tx_fifo_pulled_data[1] +.sym 5390 w_tx_fifo_pulled_data[3] +.sym 5395 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 5401 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 5402 tx_fifo.wr_addr[4] +.sym 5403 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5405 w_rx_fifo_push +.sym 5408 tx_fifo.wr_addr[5] +.sym 5409 w_tx_fifo_pulled_data[19] +.sym 5410 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5411 tx_fifo.rd_addr[9] +.sym 5413 r_counter +.sym 5414 $PACKER_VCC_NET +.sym 5416 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 5417 tx_wr_data[11] +.sym 5418 tx_fifo.rd_addr[6] +.sym 5420 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5431 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 5433 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5436 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5440 tx_fifo.rd_addr[6] +.sym 5445 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 5448 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 5451 tx_fifo.rd_addr[5] +.sym 5454 tx_fifo.rd_addr[4] +.sym 5458 $nextpnr_ICESTORM_LC_6$O +.sym 5461 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 5464 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 5467 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5468 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 5470 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 5472 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5474 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 5476 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 5479 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 5480 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 5482 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 5484 tx_fifo.rd_addr[4] +.sym 5486 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 5488 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 5490 tx_fifo.rd_addr[5] +.sym 5492 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 5494 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 5496 tx_fifo.rd_addr[6] +.sym 5498 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 5500 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 5503 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 5504 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 5509 w_tx_fifo_pulled_data[8] +.sym 5513 w_tx_fifo_pulled_data[10] +.sym 5516 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 5520 tx_fifo.rd_addr[5] +.sym 5522 w_lvds_rx_24_d1 +.sym 5526 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 5528 w_tx_fifo_pull +.sym 5530 tx_fifo.rd_addr_gray_wr_r[3] +.sym 5531 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 5532 i_rst_b_SB_LUT4_I3_O +.sym 5533 tx_fifo.rd_addr[4] +.sym 5535 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 5536 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5537 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 5538 w_tx_fifo_pulled_data[9] +.sym 5540 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 5542 i_rst_b$SB_IO_IN +.sym 5543 r_counter +.sym 5544 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 5550 tx_fifo.rd_addr[9] +.sym 5552 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 5553 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 5556 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 5559 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 5561 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5562 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 5568 tx_fifo.wr_addr_gray_rd[9] +.sym 5569 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 5578 tx_fifo.wr_addr_gray_rd[2] +.sym 5580 tx_fifo.wr_addr_gray[2] +.sym 5581 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 5583 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5585 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 5590 tx_fifo.rd_addr[9] +.sym 5591 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 5594 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 5595 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 5597 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 5602 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 5606 tx_fifo.wr_addr_gray_rd[2] +.sym 5613 tx_fifo.wr_addr_gray[2] +.sym 5618 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 5620 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 5626 tx_fifo.wr_addr_gray_rd[9] +.sym 5629 lvds_clock_buf +.sym 5632 w_tx_fifo_pulled_data[9] +.sym 5636 w_tx_fifo_pulled_data[11] +.sym 5639 tx_wr_data[8] +.sym 5640 tx_wr_data[24] +.sym 5644 tx_fifo.rd_addr[4] +.sym 5645 lvds_tx_inst.r_tx_state +.sym 5646 tx_fifo.wr_addr[5] +.sym 5647 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 5650 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 5653 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 5655 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5656 tx_wr_data[22] +.sym 5658 w_tx_fifo_pulled_data[11] +.sym 5659 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 5661 w_tx_fifo_pulled_data[20] +.sym 5664 tx_fifo.rd_addr[6] +.sym 5666 w_tx_fifo_pulled_data[23] +.sym 5673 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 5674 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5679 tx_fifo.wr_addr_gray_rd_r[9] +.sym 5680 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 5681 tx_fifo.rd_addr[9] +.sym 5684 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5687 tx_fifo.wr_addr_gray_rd_r[9] +.sym 5692 i_rst_b_SB_LUT4_I3_O +.sym 5695 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 5697 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 5701 tx_fifo.wr_addr_gray_rd_r[8] +.sym 5705 tx_fifo.wr_addr_gray_rd_r[8] +.sym 5706 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 5707 tx_fifo.wr_addr_gray_rd_r[9] +.sym 5708 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 5717 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 5718 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 5730 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 5735 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5736 tx_fifo.rd_addr[9] +.sym 5737 tx_fifo.wr_addr_gray_rd_r[9] +.sym 5738 tx_fifo.wr_addr_gray_rd_r[8] +.sym 5751 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5752 lvds_clock_buf +.sym 5753 i_rst_b_SB_LUT4_I3_O +.sym 5755 w_tx_fifo_pulled_data[20] +.sym 5759 w_tx_fifo_pulled_data[22] +.sym 5767 tx_fifo.rd_addr[9] +.sym 5768 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 5769 w_tx_fifo_pull +.sym 5770 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 5771 tx_fifo.rd_addr[6] +.sym 5774 tx_fifo.rd_addr_gray_wr_r[6] +.sym 5775 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 5776 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 5777 $PACKER_VCC_NET +.sym 5779 tx_wr_data[9] +.sym 5780 tx_fifo.wr_addr_gray[1] +.sym 5781 w_tx_fifo_pulled_data[16] +.sym 5784 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5789 w_tx_fifo_pulled_data[18] +.sym 5798 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 5799 i_rst_b_SB_LUT4_I3_O +.sym 5800 w_tx_fifo_pull +.sym 5802 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 5806 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5808 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5811 r_counter +.sym 5814 i_rst_b$SB_IO_IN +.sym 5819 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 5829 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 5841 w_tx_fifo_pull +.sym 5843 i_rst_b$SB_IO_IN +.sym 5855 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 5858 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 5864 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 5874 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5875 r_counter +.sym 5876 i_rst_b_SB_LUT4_I3_O +.sym 5878 w_tx_fifo_pulled_data[21] +.sym 5882 w_tx_fifo_pulled_data[23] +.sym 5885 w_cs[2] +.sym 5890 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 5891 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 5892 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 5895 tx_fifo.wr_addr[3] +.sym 5897 tx_fifo.rd_addr_gray_wr_r[2] +.sym 5898 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 5900 tx_fifo.wr_addr[5] +.sym 5902 tx_fifo.rd_addr[9] +.sym 5904 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 5906 $PACKER_VCC_NET +.sym 5908 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 5909 $PACKER_VCC_NET +.sym 5910 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 5911 tx_fifo.rd_addr[6] +.sym 5912 w_tx_fifo_pulled_data[19] +.sym 5920 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5926 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 5928 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5934 r_counter +.sym 5947 i_rst_b_SB_LUT4_I3_O +.sym 5949 i_rst_b_SB_LUT4_I3_O +.sym 5966 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 5975 i_rst_b_SB_LUT4_I3_O +.sym 5983 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 5997 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 5998 r_counter +.sym 5999 i_rst_b_SB_LUT4_I3_O +.sym 6001 w_tx_fifo_pulled_data[16] +.sym 6005 w_tx_fifo_pulled_data[18] +.sym 6009 spi_if_ins.spi.r3_rx_done +.sym 6012 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 6013 tx_fifo.rd_addr_gray_wr_r[4] +.sym 6014 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 6016 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 6017 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 6020 w_tx_fifo_pull +.sym 6021 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 6022 tx_fifo.rd_addr[5] +.sym 6024 r_counter +.sym 6028 tx_fifo.rd_addr[9] +.sym 6032 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 6033 tx_fifo.rd_addr[4] +.sym 6043 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 6053 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 6054 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 6056 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 6061 i_rst_b_SB_LUT4_I3_O +.sym 6062 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 6065 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 6067 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 6068 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 6080 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 6083 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 6086 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 6088 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 6093 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 6095 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 6099 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 6104 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 6106 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 6111 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 6120 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 6121 lvds_clock_buf +.sym 6122 i_rst_b_SB_LUT4_I3_O +.sym 6124 w_tx_fifo_pulled_data[17] +.sym 6128 w_tx_fifo_pulled_data[19] +.sym 6135 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6137 tx_fifo.wr_addr[5] +.sym 6139 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 6141 tx_fifo.wr_addr[8] +.sym 6152 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 6156 tx_fifo.rd_addr[9] +.sym 6166 tx_fifo.rd_addr_gray[1] +.sym 6170 tx_fifo.rd_addr[9] +.sym 6173 r_counter +.sym 6175 tx_fifo.rd_addr_gray[0] +.sym 6177 tx_fifo.rd_addr_gray[8] +.sym 6188 tx_fifo.rd_addr_gray_wr[2] +.sym 6197 tx_fifo.rd_addr[9] +.sym 6216 tx_fifo.rd_addr_gray[1] +.sym 6221 tx_fifo.rd_addr_gray[0] +.sym 6234 tx_fifo.rd_addr_gray_wr[2] +.sym 6242 tx_fifo.rd_addr_gray[8] +.sym 6244 r_counter +.sym 6250 tx_fifo.rd_addr_gray_wr[0] +.sym 6254 tx_fifo.rd_addr_gray_wr_r[8] +.sym 6255 $PACKER_VCC_NET +.sym 6258 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 6262 tx_fifo.rd_addr_gray_wr[1] +.sym 6263 w_tx_fifo_pull +.sym 6264 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 6265 o_shdn_tx_lna$SB_IO_OUT +.sym 6280 o_shdn_tx_lna$SB_IO_OUT .sym 6294 o_shdn_tx_lna$SB_IO_OUT -.sym 6310 o_shdn_tx_lna$SB_IO_OUT -.sym 6346 tx_fifo.rd_addr_gray_wr[3] -.sym 6347 tx_fifo.rd_addr_gray_wr[2] -.sym 6348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 6349 tx_fifo.rd_addr_gray_wr[5] -.sym 6350 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 6351 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 6352 tx_fifo.rd_addr_gray_wr[6] -.sym 6386 rx_fifo.mem_i.0.1_WDATA_3 -.sym 6390 rx_fifo.mem_i.0.1_WDATA_2 -.sym 6392 rx_fifo.wr_addr[4] -.sym 6395 rx_fifo.wr_addr[1] -.sym 6397 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 6398 rx_fifo.wr_addr[3] -.sym 6399 rx_fifo.wr_addr[2] -.sym 6400 rx_fifo.wr_addr[7] -.sym 6401 rx_fifo.wr_addr[6] -.sym 6403 rx_fifo.wr_addr[9] -.sym 6406 rx_fifo.wr_addr[8] -.sym 6414 rx_fifo.wr_addr[5] -.sym 6415 $PACKER_VCC_NET -.sym 6416 rx_fifo.wr_addr[0] -.sym 6422 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 6423 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 6424 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 6425 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 6426 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 6427 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 6428 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 6429 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 6314 o_shdn_tx_lna$SB_IO_OUT +.sym 6347 smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[1] +.sym 6348 w_rx_fifo_data[8] +.sym 6349 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 6350 smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E +.sym 6351 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 6352 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] +.sym 6353 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] +.sym 6376 rx_fifo.wr_addr[7] +.sym 6386 rx_fifo.wr_addr[6] +.sym 6388 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6389 rx_fifo.wr_addr[7] +.sym 6390 rx_fifo.wr_addr[8] +.sym 6391 rx_fifo.wr_addr[5] +.sym 6392 rx_fifo.wr_addr[2] +.sym 6393 rx_fifo.wr_addr[3] +.sym 6397 w_rx_fifo_push +.sym 6398 rx_fifo.wr_addr[0] +.sym 6399 $PACKER_VCC_NET +.sym 6402 rx_fifo.wr_addr[4] +.sym 6404 w_rx_fifo_data[8] +.sym 6413 w_rx_fifo_data[10] +.sym 6414 rx_fifo.wr_addr[9] +.sym 6418 w_smi_data_input[6] +.sym 6422 smi_ctrl_ins.frame_sr[11] +.sym 6423 smi_ctrl_ins.frame_sr[8] +.sym 6424 smi_ctrl_ins.frame_sr[9] +.sym 6425 smi_ctrl_ins.frame_sr[13] +.sym 6426 smi_ctrl_ins.frame_sr[15] +.sym 6427 smi_ctrl_ins.frame_sr[10] +.sym 6428 smi_ctrl_ins.frame_sr[14] +.sym 6429 smi_ctrl_ins.frame_sr[12] .sym 6438 rx_fifo.wr_addr[2] .sym 6439 rx_fifo.wr_addr[3] .sym 6441 rx_fifo.wr_addr[4] @@ -6020,93 +6700,122 @@ .sym 6444 rx_fifo.wr_addr[7] .sym 6445 rx_fifo.wr_addr[8] .sym 6446 rx_fifo.wr_addr[9] -.sym 6447 rx_fifo.wr_addr[1] +.sym 6447 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] .sym 6448 rx_fifo.wr_addr[0] -.sym 6449 lvds_clock_$glb_clk -.sym 6450 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 6452 rx_fifo.mem_i.0.1_WDATA_3 -.sym 6456 rx_fifo.mem_i.0.1_WDATA_2 +.sym 6449 lvds_clock_buf +.sym 6450 w_rx_fifo_push +.sym 6452 w_rx_fifo_data[8] +.sym 6456 w_rx_fifo_data[10] .sym 6459 $PACKER_VCC_NET -.sym 6473 rx_fifo.wr_addr[6] -.sym 6481 rx_fifo.rd_addr[0] -.sym 6487 rx_fifo.rd_addr[5] -.sym 6490 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6493 rx_fifo.rd_addr[9] -.sym 6494 rx_fifo.mem_i.0.1_WDATA -.sym 6495 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 6497 rx_fifo.wr_addr[3] -.sym 6498 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 6500 rx_fifo.wr_addr[4] -.sym 6502 tx_fifo.rd_addr_gray[5] +.sym 6460 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6463 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6465 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] +.sym 6466 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6467 rx_fifo.wr_addr[7] +.sym 6468 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6469 w_rx_fifo_push +.sym 6471 rx_fifo.wr_addr[5] +.sym 6472 w_rx_09_fifo_data[8] +.sym 6473 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 6474 rx_fifo.rd_addr[3] +.sym 6478 $PACKER_VCC_NET +.sym 6481 smi_ctrl_ins.byte_ix[3] +.sym 6482 w_rx_fifo_pull +.sym 6486 w_smi_data_direction +.sym 6487 rx_fifo.rd_addr[9] +.sym 6489 i_rst_b_SB_LUT4_I3_O +.sym 6490 r_counter +.sym 6491 channel +.sym 6502 smi_ctrl_ins.soe_and_reset .sym 6503 rx_fifo.wr_addr[9] -.sym 6504 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 6506 rx_fifo.wr_addr[8] -.sym 6513 w_smi_data_direction -.sym 6515 w_smi_data_output[6] +.sym 6506 smi_ctrl_ins.frame_sr[23] +.sym 6508 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 6509 smi_ctrl_ins.frame_sr[10] +.sym 6511 smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E +.sym 6512 r_counter +.sym 6514 smi_ctrl_ins.frame_sr[12] .sym 6516 $PACKER_VCC_NET -.sym 6517 rx_fifo.wr_addr[0] -.sym 6518 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 6528 rx_fifo.rd_addr[1] -.sym 6532 $PACKER_VCC_NET +.sym 6517 smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E +.sym 6518 w_rx_fifo_pulled_data[19] +.sym 6519 $PACKER_VCC_NET +.sym 6528 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 6530 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6532 w_rx_fifo_data[9] +.sym 6534 rx_fifo.rd_addr[8] +.sym 6535 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] .sym 6536 rx_fifo.rd_addr[0] -.sym 6539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 6540 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6541 rx_fifo.rd_addr[2] -.sym 6542 rx_fifo.rd_addr[5] -.sym 6543 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 6544 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6548 rx_fifo.mem_i.0.1_WDATA -.sym 6549 rx_fifo.rd_addr[9] -.sym 6557 rx_fifo.mem_i.0.1_WDATA_1 -.sym 6558 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6559 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 6563 tx_fifo.rd_addr_gray[6] -.sym 6564 tx_fifo.rd_addr_gray[5] -.sym 6565 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] -.sym 6566 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 6567 rx_fifo.mem_i.0.2_WDATA_2 -.sym 6576 rx_fifo.rd_addr[2] -.sym 6577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 6580 rx_fifo.rd_addr[5] -.sym 6581 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6582 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6583 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 6537 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6539 w_rx_fifo_pull +.sym 6542 rx_fifo.rd_addr[9] +.sym 6543 w_rx_fifo_data[11] +.sym 6544 r_counter +.sym 6545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6546 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 6548 $PACKER_VCC_NET +.sym 6549 rx_fifo.rd_addr[3] +.sym 6560 smi_ctrl_ins.frame_sr[21] +.sym 6561 smi_ctrl_ins.frame_sr[20] +.sym 6562 smi_ctrl_ins.frame_sr[18] +.sym 6563 smi_ctrl_ins.frame_sr[19] +.sym 6564 smi_ctrl_ins.frame_sr[22] +.sym 6565 smi_ctrl_ins.frame_sr[16] +.sym 6566 smi_ctrl_ins.frame_sr[23] +.sym 6567 smi_ctrl_ins.frame_sr[17] +.sym 6576 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6577 rx_fifo.rd_addr[3] +.sym 6579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 6580 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6581 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6582 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 6583 rx_fifo.rd_addr[8] .sym 6584 rx_fifo.rd_addr[9] -.sym 6585 rx_fifo.rd_addr[1] +.sym 6585 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] .sym 6586 rx_fifo.rd_addr[0] -.sym 6587 r_counter_$glb_clk -.sym 6588 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 6587 r_counter +.sym 6588 w_rx_fifo_pull .sym 6589 $PACKER_VCC_NET -.sym 6593 rx_fifo.mem_i.0.1_WDATA -.sym 6597 rx_fifo.mem_i.0.1_WDATA_1 -.sym 6603 w_rx_fifo_pulled_data[13] -.sym 6607 smi_ctrl_ins.int_cnt_rx[3] -.sym 6608 $PACKER_VCC_NET -.sym 6610 w_rx_fifo_pulled_data[15] -.sym 6621 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 6636 rx_fifo.wr_addr[1] -.sym 6641 rx_fifo.wr_addr[2] -.sym 6642 rx_fifo.wr_addr[5] -.sym 6643 $PACKER_VCC_NET +.sym 6593 w_rx_fifo_data[11] +.sym 6597 w_rx_fifo_data[9] +.sym 6598 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 6600 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 6602 rx_fifo.rd_addr[0] +.sym 6604 w_rx_fifo_pulled_data[11] +.sym 6606 rx_fifo.rd_addr[8] +.sym 6607 rx_fifo.rd_addr[0] +.sym 6608 smi_ctrl_ins.d_byte[0] +.sym 6610 smi_ctrl_ins.d_byte[1] +.sym 6612 smi_ctrl_ins.d_byte[5] +.sym 6614 $PACKER_VCC_NET +.sym 6615 rx_fifo.wr_addr[3] +.sym 6616 smi_ctrl_ins.frame_sr[13] +.sym 6617 rx_fifo.wr_addr[4] +.sym 6619 tx_wr_en +.sym 6620 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 6621 i_smi_swe_srw$SB_IO_IN +.sym 6624 smi_ctrl_ins.d_byte[5] +.sym 6625 w_rx_fifo_data[12] +.sym 6632 rx_fifo.wr_addr[4] +.sym 6634 w_rx_fifo_data[22] +.sym 6636 rx_fifo.wr_addr[8] +.sym 6638 rx_fifo.wr_addr[3] +.sym 6639 rx_fifo.wr_addr[6] +.sym 6645 rx_fifo.wr_addr[2] .sym 6647 rx_fifo.wr_addr[9] -.sym 6648 rx_fifo.wr_addr[6] -.sym 6649 rx_fifo.wr_addr[3] -.sym 6650 rx_fifo.wr_addr[8] -.sym 6651 rx_fifo.wr_addr[7] -.sym 6655 rx_fifo.mem_i.0.2_WDATA_3 -.sym 6657 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 6659 rx_fifo.wr_addr[4] +.sym 6648 w_rx_fifo_push +.sym 6649 rx_fifo.wr_addr[5] +.sym 6655 w_rx_fifo_data[20] +.sym 6657 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6658 rx_fifo.wr_addr[7] +.sym 6659 $PACKER_VCC_NET .sym 6660 rx_fifo.wr_addr[0] -.sym 6661 rx_fifo.mem_i.0.2_WDATA_2 -.sym 6662 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 6663 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 6664 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 6665 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 6666 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 6667 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 6668 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 6669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.sym 6662 tx_wr_data[23] +.sym 6663 tx_wr_data[18] +.sym 6664 tx_wr_data[4] +.sym 6665 tx_wr_data[7] +.sym 6666 tx_wr_data[10] +.sym 6667 tx_wr_data[19] +.sym 6668 tx_wr_data[20] +.sym 6669 tx_wr_data[17] .sym 6678 rx_fifo.wr_addr[2] .sym 6679 rx_fifo.wr_addr[3] .sym 6681 rx_fifo.wr_addr[4] @@ -6115,99 +6824,110 @@ .sym 6684 rx_fifo.wr_addr[7] .sym 6685 rx_fifo.wr_addr[8] .sym 6686 rx_fifo.wr_addr[9] -.sym 6687 rx_fifo.wr_addr[1] +.sym 6687 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] .sym 6688 rx_fifo.wr_addr[0] -.sym 6689 lvds_clock_$glb_clk -.sym 6690 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 6692 rx_fifo.mem_i.0.2_WDATA_3 -.sym 6696 rx_fifo.mem_i.0.2_WDATA_2 +.sym 6689 lvds_clock_buf +.sym 6690 w_rx_fifo_push +.sym 6692 w_rx_fifo_data[20] +.sym 6696 w_rx_fifo_data[22] .sym 6699 $PACKER_VCC_NET -.sym 6704 smi_ctrl_ins.int_cnt_rx[4] -.sym 6705 w_rx_09_fifo_data[26] -.sym 6706 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 6707 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 6708 rx_fifo.mem_q.0.3_WDATA_3 -.sym 6709 smi_ctrl_ins.int_cnt_rx[3] -.sym 6710 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 6712 rx_fifo.wr_addr[1] -.sym 6713 rx_fifo.rd_addr[2] -.sym 6715 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6717 rx_fifo.rd_addr[0] -.sym 6721 smi_ctrl_ins.int_cnt_rx[4] -.sym 6725 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6727 rx_fifo.rd_addr[5] -.sym 6732 rx_fifo.rd_addr[2] -.sym 6733 rx_fifo.rd_addr[5] -.sym 6740 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6745 $PACKER_VCC_NET -.sym 6746 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6747 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6748 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6750 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 6752 rx_fifo.rd_addr[1] -.sym 6756 rx_fifo.rd_addr[0] -.sym 6759 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 6760 rx_fifo.rd_addr[9] -.sym 6761 rx_fifo.mem_i.0.2_WDATA -.sym 6763 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 6764 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 6767 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 6768 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 6769 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 6771 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 6780 rx_fifo.rd_addr[2] -.sym 6781 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6783 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 6784 rx_fifo.rd_addr[5] -.sym 6785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6786 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6787 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 6700 smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E +.sym 6702 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 6705 smi_ctrl_ins.d_byte[0] +.sym 6706 w_rx_fifo_pulled_data[22] +.sym 6708 w_rx_fifo_pulled_data[20] +.sym 6709 w_tx_fsm_state[0] +.sym 6711 smi_ctrl_ins.d_byte[1] +.sym 6712 w_tx_fsm_state[0] +.sym 6717 smi_ctrl_ins.byte_ix[3] +.sym 6718 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 6719 w_rx_fifo_pull +.sym 6720 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6721 tx_wr_data[20] +.sym 6723 w_rx_fifo_pulled_data[12] +.sym 6724 rx_fifo.rd_addr[9] +.sym 6725 tx_wr_data[23] +.sym 6726 channel +.sym 6727 w_rx_fifo_pull +.sym 6732 r_counter +.sym 6734 w_rx_fifo_pull +.sym 6736 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 6737 rx_fifo.rd_addr[3] +.sym 6738 w_rx_fifo_data[21] +.sym 6741 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 6742 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6743 rx_fifo.rd_addr[8] +.sym 6745 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6748 w_rx_fifo_data[23] +.sym 6749 rx_fifo.rd_addr[9] +.sym 6750 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6751 rx_fifo.rd_addr[0] +.sym 6752 $PACKER_VCC_NET +.sym 6758 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 6764 smi_ctrl_ins.swe_q1 +.sym 6765 smi_ctrl_ins.push_req +.sym 6766 tx_wr_en +.sym 6767 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] +.sym 6768 smi_ctrl_ins.swe_q2_d +.sym 6769 w_rx_fifo_data[10] +.sym 6770 smi_ctrl_ins.swe_q2 +.sym 6771 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 6780 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6781 rx_fifo.rd_addr[3] +.sym 6783 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 6784 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6786 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 6787 rx_fifo.rd_addr[8] .sym 6788 rx_fifo.rd_addr[9] -.sym 6789 rx_fifo.rd_addr[1] +.sym 6789 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] .sym 6790 rx_fifo.rd_addr[0] -.sym 6791 r_counter_$glb_clk -.sym 6792 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 6791 r_counter +.sym 6792 w_rx_fifo_pull .sym 6793 $PACKER_VCC_NET -.sym 6797 rx_fifo.mem_i.0.2_WDATA -.sym 6801 rx_fifo.mem_i.0.2_WDATA_1 -.sym 6806 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6808 smi_ctrl_ins.int_cnt_rx[4] -.sym 6810 w_rx_fifo_pulled_data[12] -.sym 6813 $PACKER_VCC_NET -.sym 6816 $PACKER_VCC_NET -.sym 6818 rx_fifo.wr_addr[9] -.sym 6819 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 6820 w_rx_fifo_pulled_data[8] -.sym 6821 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 6822 rx_fifo.rd_addr[0] -.sym 6823 rx_fifo.rd_addr[1] -.sym 6824 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 6825 rx_fifo.wr_addr[4] -.sym 6826 rx_fifo.rd_addr[9] -.sym 6827 rx_fifo.wr_addr[3] -.sym 6828 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6829 w_rx_fifo_pulled_data[14] -.sym 6835 rx_fifo.wr_addr[9] -.sym 6836 rx_fifo.wr_addr[1] -.sym 6837 rx_fifo.wr_addr[3] -.sym 6838 $PACKER_VCC_NET -.sym 6840 rx_fifo.mem_q.0.1_WDATA_2 +.sym 6797 w_rx_fifo_data[23] +.sym 6801 w_rx_fifo_data[21] +.sym 6803 tx_wr_data[19] +.sym 6804 tx_wr_data[19] +.sym 6806 w_tx_fsm_state[0] +.sym 6807 w_tx_fifo_full +.sym 6808 w_rx_fifo_pulled_data[23] +.sym 6809 tx_wr_data[7] +.sym 6810 w_rx_fifo_pulled_data[21] +.sym 6811 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 6813 w_tx_fsm_state[1] +.sym 6814 w_rx_fifo_data[21] +.sym 6816 w_rx_fifo_data[22] +.sym 6818 tx_wr_data[4] +.sym 6820 w_tx_fifo_pulled_data[4] +.sym 6821 tx_fifo.wr_addr[7] +.sym 6822 tx_wr_data[10] +.sym 6825 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 6826 rx_fifo.wr_addr[9] +.sym 6827 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 6828 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 6829 smi_ctrl_ins.push_req +.sym 6834 w_rx_fifo_data[14] +.sym 6836 rx_fifo.wr_addr[4] +.sym 6838 rx_fifo.wr_addr[6] +.sym 6840 rx_fifo.wr_addr[8] .sym 6842 rx_fifo.wr_addr[7] -.sym 6845 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 6847 rx_fifo.mem_q.0.1_WDATA_3 -.sym 6849 rx_fifo.wr_addr[6] -.sym 6851 rx_fifo.wr_addr[0] -.sym 6853 rx_fifo.wr_addr[5] -.sym 6854 rx_fifo.wr_addr[8] -.sym 6861 rx_fifo.wr_addr[2] -.sym 6865 rx_fifo.wr_addr[4] -.sym 6866 rx_fifo.rd_addr[0] -.sym 6868 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 6869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 6870 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6871 rx_fifo.rd_addr[5] -.sym 6873 rx_fifo.wr_addr[4] +.sym 6843 rx_fifo.wr_addr[2] +.sym 6845 w_rx_fifo_push +.sym 6846 rx_fifo.wr_addr[0] +.sym 6848 rx_fifo.wr_addr[5] +.sym 6849 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 6851 rx_fifo.wr_addr[9] +.sym 6852 w_rx_fifo_data[12] +.sym 6854 $PACKER_VCC_NET +.sym 6855 rx_fifo.wr_addr[3] +.sym 6866 w_rx_24_fifo_data[15] +.sym 6868 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 6869 w_rx_24_fifo_data[27] +.sym 6870 w_rx_24_fifo_data[18] +.sym 6871 w_rx_24_fifo_data[13] +.sym 6872 w_rx_fifo_data[15] +.sym 6873 w_rx_24_fifo_data[26] .sym 6882 rx_fifo.wr_addr[2] .sym 6883 rx_fifo.wr_addr[3] .sym 6885 rx_fifo.wr_addr[4] @@ -6216,4287 +6936,5932 @@ .sym 6888 rx_fifo.wr_addr[7] .sym 6889 rx_fifo.wr_addr[8] .sym 6890 rx_fifo.wr_addr[9] -.sym 6891 rx_fifo.wr_addr[1] +.sym 6891 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] .sym 6892 rx_fifo.wr_addr[0] -.sym 6893 lvds_clock_$glb_clk -.sym 6894 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 6896 rx_fifo.mem_q.0.1_WDATA_3 -.sym 6900 rx_fifo.mem_q.0.1_WDATA_2 +.sym 6893 lvds_clock_buf +.sym 6894 w_rx_fifo_push +.sym 6896 w_rx_fifo_data[12] +.sym 6900 w_rx_fifo_data[14] .sym 6903 $PACKER_VCC_NET -.sym 6908 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6909 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 6910 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 6911 rx_fifo.wr_addr[2] -.sym 6912 rx_fifo.wr_addr[1] -.sym 6913 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6914 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 6916 rx_fifo.mem_i.0.0_WDATA_2 -.sym 6917 $PACKER_VCC_NET -.sym 6920 rx_fifo.wr_addr[8] -.sym 6921 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6922 rx_fifo.wr_addr[0] -.sym 6923 rx_fifo.rd_addr[5] -.sym 6925 w_smi_data_direction -.sym 6926 rx_fifo.wr_addr_gray_rd_r[5] +.sym 6904 rx_fifo.wr_addr[7] +.sym 6906 w_tx_fifo_pulled_data[17] +.sym 6907 w_tx_fifo_pull +.sym 6908 w_tx_fifo_pulled_data[26] +.sym 6909 rx_fifo.wr_addr[2] +.sym 6910 w_rx_fifo_pulled_data[14] +.sym 6912 lvds_tx_inst.r_fifo_data[23] +.sym 6915 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 6916 rx_fifo.wr_addr[5] +.sym 6917 w_rx_fifo_push +.sym 6918 w_rx_fifo_data[14] +.sym 6919 tx_wr_en +.sym 6920 tx_wr_en +.sym 6921 tx_fifo.wr_addr[0] +.sym 6922 w_tx_fifo_pulled_data[5] +.sym 6923 tx_wr_data[18] +.sym 6924 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 6925 r_counter +.sym 6926 w_rx_09_fifo_data[15] .sym 6929 $PACKER_VCC_NET -.sym 6938 rx_fifo.rd_addr[2] -.sym 6940 $PACKER_VCC_NET -.sym 6941 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6942 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 6947 rx_fifo.mem_q.0.1_WDATA_1 -.sym 6951 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 6954 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 6956 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6957 rx_fifo.rd_addr[5] -.sym 6960 rx_fifo.rd_addr[0] -.sym 6961 rx_fifo.rd_addr[1] -.sym 6963 rx_fifo.mem_q.0.1_WDATA -.sym 6964 rx_fifo.rd_addr[9] -.sym 6966 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6968 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 6970 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] -.sym 6971 rx_fifo.wr_addr[4] -.sym 6972 rx_fifo.wr_addr[3] -.sym 6974 rx_fifo.wr_addr[8] -.sym 6975 rx_fifo.wr_addr[0] -.sym 6984 rx_fifo.rd_addr[2] -.sym 6985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 6987 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 6988 rx_fifo.rd_addr[5] -.sym 6989 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 6990 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 6991 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 6930 w_tx_fifo_pulled_data[7] +.sym 6931 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 6936 rx_fifo.rd_addr[8] +.sym 6939 rx_fifo.rd_addr[0] +.sym 6941 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6945 w_rx_fifo_data[13] +.sym 6947 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 6948 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 6949 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6953 rx_fifo.rd_addr[9] +.sym 6954 w_rx_fifo_pull +.sym 6956 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 6957 rx_fifo.rd_addr[3] +.sym 6958 w_rx_fifo_data[15] +.sym 6961 r_counter +.sym 6965 $PACKER_VCC_NET +.sym 6967 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6968 smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] +.sym 6969 w_rx_09_fifo_data[1] +.sym 6970 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6971 w_rx_fifo_data[27] +.sym 6972 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 6973 w_rx_fifo_data[0] +.sym 6974 w_rx_09_fifo_data[0] +.sym 6975 w_rx_fifo_data[23] +.sym 6984 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 6985 rx_fifo.rd_addr[3] +.sym 6987 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 6988 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 6989 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 6990 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 6991 rx_fifo.rd_addr[8] .sym 6992 rx_fifo.rd_addr[9] -.sym 6993 rx_fifo.rd_addr[1] +.sym 6993 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] .sym 6994 rx_fifo.rd_addr[0] -.sym 6995 r_counter_$glb_clk -.sym 6996 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 6995 r_counter +.sym 6996 w_rx_fifo_pull .sym 6997 $PACKER_VCC_NET -.sym 7001 rx_fifo.mem_q.0.1_WDATA -.sym 7005 rx_fifo.mem_q.0.1_WDATA_1 -.sym 7013 i_rst_b$SB_IO_IN -.sym 7014 rx_fifo.rd_addr[2] -.sym 7016 $PACKER_VCC_NET -.sym 7017 rx_fifo.rd_addr[0] -.sym 7018 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7020 rx_fifo.mem_i.0.0_WDATA -.sym 7021 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 7023 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 7027 rx_fifo.wr_addr[8] -.sym 7029 rx_fifo.wr_addr[0] -.sym 7032 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 7033 rx_fifo.wr_addr[9] -.sym 7039 rx_fifo.wr_addr[9] -.sym 7040 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 7044 rx_fifo.mem_q.0.2_WDATA_2 -.sym 7046 rx_fifo.wr_addr[5] -.sym 7049 rx_fifo.wr_addr[4] -.sym 7053 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7055 rx_fifo.wr_addr[7] -.sym 7060 rx_fifo.wr_addr[8] -.sym 7061 rx_fifo.wr_addr[0] -.sym 7063 rx_fifo.wr_addr[1] -.sym 7065 rx_fifo.wr_addr[2] -.sym 7066 rx_fifo.wr_addr[3] +.sym 7001 w_rx_fifo_data[15] +.sym 7005 w_rx_fifo_data[13] +.sym 7010 w_rx_24_fifo_data[9] +.sym 7011 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 7012 w_rx_fifo_pulled_data[15] +.sym 7013 lvds_tx_inst.sent_first_sync +.sym 7014 w_rx_fifo_pulled_data[13] +.sym 7015 w_tx_fifo_pulled_data[25] +.sym 7017 lvds_tx_inst.r_fifo_data[24] +.sym 7018 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 7019 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 7021 w_rx_fifo_data[13] +.sym 7022 w_lvds_rx_24_d0 +.sym 7023 tx_wr_en +.sym 7024 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 7026 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 7028 tx_fifo.rd_addr[5] +.sym 7030 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7031 $PACKER_VCC_NET +.sym 7032 w_lvds_rx_24_d1 +.sym 7033 tx_wr_en +.sym 7038 r_counter +.sym 7040 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7042 tx_fifo.wr_addr[8] +.sym 7045 tx_fifo.wr_addr[5] +.sym 7047 tx_wr_data[4] +.sym 7048 tx_fifo.wr_addr[7] +.sym 7053 tx_wr_data[6] +.sym 7056 tx_wr_en +.sym 7059 tx_fifo.wr_addr[0] +.sym 7061 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7063 tx_fifo.wr_addr[6] +.sym 7065 tx_fifo.wr_addr[4] +.sym 7066 tx_fifo.wr_addr[3] .sym 7067 $PACKER_VCC_NET -.sym 7069 rx_fifo.wr_addr[6] -.sym 7072 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 7073 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 7074 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 7075 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 7076 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 7077 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 7086 rx_fifo.wr_addr[2] -.sym 7087 rx_fifo.wr_addr[3] -.sym 7089 rx_fifo.wr_addr[4] -.sym 7090 rx_fifo.wr_addr[5] -.sym 7091 rx_fifo.wr_addr[6] -.sym 7092 rx_fifo.wr_addr[7] -.sym 7093 rx_fifo.wr_addr[8] -.sym 7094 rx_fifo.wr_addr[9] -.sym 7095 rx_fifo.wr_addr[1] -.sym 7096 rx_fifo.wr_addr[0] -.sym 7097 lvds_clock_$glb_clk -.sym 7098 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 7100 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7104 rx_fifo.mem_q.0.2_WDATA_2 +.sym 7069 tx_fifo.wr_addr[2] +.sym 7070 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 7073 w_rx_24_fifo_data[0] +.sym 7074 w_rx_24_fifo_data[1] +.sym 7076 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 7077 tx_fifo.wr_addr[2] +.sym 7086 tx_fifo.wr_addr[2] +.sym 7087 tx_fifo.wr_addr[3] +.sym 7089 tx_fifo.wr_addr[4] +.sym 7090 tx_fifo.wr_addr[5] +.sym 7091 tx_fifo.wr_addr[6] +.sym 7092 tx_fifo.wr_addr[7] +.sym 7093 tx_fifo.wr_addr[8] +.sym 7094 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7095 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7096 tx_fifo.wr_addr[0] +.sym 7097 r_counter +.sym 7098 tx_wr_en +.sym 7100 tx_wr_data[4] +.sym 7104 tx_wr_data[6] .sym 7107 $PACKER_VCC_NET -.sym 7112 rx_fifo.wr_addr[5] -.sym 7113 rx_fifo.wr_addr[8] -.sym 7115 rx_fifo.wr_addr[4] -.sym 7117 rx_fifo.wr_addr[0] -.sym 7118 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 7119 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7120 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 7121 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7122 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 7123 rx_fifo.rd_addr[1] -.sym 7125 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 7126 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 7128 rx_fifo.wr_addr[3] -.sym 7129 rx_fifo.rd_addr[5] -.sym 7131 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 7133 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 7143 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 7144 rx_fifo.mem_q.0.2_WDATA -.sym 7146 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7148 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 7149 rx_fifo.rd_addr[2] -.sym 7150 rx_fifo.rd_addr[5] -.sym 7151 rx_fifo.rd_addr[1] -.sym 7153 $PACKER_VCC_NET -.sym 7156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 7157 rx_fifo.rd_addr[9] -.sym 7159 rx_fifo.rd_addr[0] -.sym 7162 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 7169 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7172 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 7173 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 7174 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 7175 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 7176 rx_fifo.rd_addr_gray[5] -.sym 7177 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] -.sym 7178 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 7179 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 7188 rx_fifo.rd_addr[2] -.sym 7189 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 7191 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7192 rx_fifo.rd_addr[5] -.sym 7193 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 7194 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 7195 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7196 rx_fifo.rd_addr[9] -.sym 7197 rx_fifo.rd_addr[1] -.sym 7198 rx_fifo.rd_addr[0] -.sym 7199 r_counter_$glb_clk -.sym 7200 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 7112 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 7113 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 7114 w_rx_09_fifo_data[17] +.sym 7115 w_rx_fifo_data[27] +.sym 7118 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 7119 w_rx_09_fifo_data[27] +.sym 7121 io_ctrl_ins.mixer_en_state +.sym 7123 w_rx_09_fifo_data[4] +.sym 7124 i_rst_b_SB_LUT4_I3_O +.sym 7125 tx_wr_data[20] +.sym 7126 channel +.sym 7127 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7129 tx_fifo.wr_addr[6] +.sym 7130 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 7131 w_tx_fifo_full +.sym 7132 tx_fifo.wr_addr[3] +.sym 7133 smi_ctrl_ins.byte_ix[3] +.sym 7134 tx_wr_data[23] +.sym 7135 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 7140 tx_wr_data[5] +.sym 7141 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7143 tx_fifo.rd_addr[9] +.sym 7144 $PACKER_VCC_NET +.sym 7150 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7151 tx_wr_data[7] +.sym 7158 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7160 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7161 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7162 tx_fifo.rd_addr[6] +.sym 7166 tx_fifo.rd_addr[5] +.sym 7167 w_tx_fifo_pull +.sym 7169 tx_fifo.rd_addr[4] +.sym 7171 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7174 lvds_rx_24_inst.r_phase_count[1] +.sym 7175 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 7177 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 7179 lvds_tx_inst.r_fifo_data[30] +.sym 7188 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7189 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7191 tx_fifo.rd_addr[4] +.sym 7192 tx_fifo.rd_addr[5] +.sym 7193 tx_fifo.rd_addr[6] +.sym 7194 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7195 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7196 tx_fifo.rd_addr[9] +.sym 7197 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7198 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7199 lvds_clock_buf +.sym 7200 w_tx_fifo_pull .sym 7201 $PACKER_VCC_NET -.sym 7205 rx_fifo.mem_q.0.2_WDATA -.sym 7209 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7217 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 7218 $PACKER_VCC_NET -.sym 7220 rx_fifo.wr_addr[1] -.sym 7222 rx_fifo.wr_addr[2] -.sym 7225 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 7226 rx_fifo.rd_addr[9] -.sym 7227 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 7228 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 7229 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 7231 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 7232 rx_fifo.rd_addr_gray_wr_r[1] -.sym 7233 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7234 rx_fifo.wr_addr[4] -.sym 7235 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7236 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 7237 rx_fifo.wr_addr[9] -.sym 7243 rx_fifo.wr_addr[9] -.sym 7244 rx_fifo.wr_addr[4] -.sym 7246 rx_fifo.wr_addr[1] -.sym 7249 rx_fifo.wr_addr[5] -.sym 7250 rx_fifo.wr_addr[7] -.sym 7251 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7253 rx_fifo.wr_addr[6] -.sym 7255 rx_fifo.wr_addr[2] -.sym 7256 rx_fifo.wr_addr[0] -.sym 7260 rx_fifo.mem_q.0.0_WDATA_2 -.sym 7262 rx_fifo.wr_addr[8] -.sym 7266 rx_fifo.wr_addr[3] -.sym 7269 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 7271 $PACKER_VCC_NET -.sym 7274 rx_fifo.rd_addr_gray[0] -.sym 7275 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 7276 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 7277 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 7279 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] -.sym 7280 rx_fifo.rd_addr[9] -.sym 7281 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 7290 rx_fifo.wr_addr[2] -.sym 7291 rx_fifo.wr_addr[3] -.sym 7293 rx_fifo.wr_addr[4] -.sym 7294 rx_fifo.wr_addr[5] -.sym 7295 rx_fifo.wr_addr[6] -.sym 7296 rx_fifo.wr_addr[7] -.sym 7297 rx_fifo.wr_addr[8] -.sym 7298 rx_fifo.wr_addr[9] -.sym 7299 rx_fifo.wr_addr[1] -.sym 7300 rx_fifo.wr_addr[0] -.sym 7301 lvds_clock_$glb_clk -.sym 7302 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 7304 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7308 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7205 tx_wr_data[7] +.sym 7209 tx_wr_data[5] +.sym 7214 lvds_tx_inst.fifo_empty_d2 +.sym 7215 w_rx_09_fifo_data[31] +.sym 7216 $PACKER_VCC_NET +.sym 7219 tx_fifo.rd_addr[9] +.sym 7220 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 7221 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 7223 w_tx_fifo_pulled_data[27] +.sym 7224 spi_if_ins.w_rx_data[6] +.sym 7226 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 7228 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 7229 tx_fifo.wr_addr[7] +.sym 7230 tx_wr_data[10] +.sym 7233 w_tx_fifo_pulled_data[22] +.sym 7234 i_rst_b_SB_LUT4_I3_O +.sym 7235 w_lvds_rx_09_d1 +.sym 7236 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 7237 tx_fifo.wr_addr[8] +.sym 7246 $PACKER_VCC_NET +.sym 7248 tx_fifo.wr_addr[4] +.sym 7252 tx_fifo.wr_addr[7] +.sym 7254 tx_fifo.wr_addr[5] +.sym 7255 tx_wr_data[2] +.sym 7257 tx_fifo.wr_addr[8] +.sym 7258 r_counter +.sym 7260 tx_wr_en +.sym 7262 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7263 tx_fifo.wr_addr[0] +.sym 7264 tx_fifo.wr_addr[2] +.sym 7265 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7267 tx_fifo.wr_addr[6] +.sym 7270 tx_fifo.wr_addr[3] +.sym 7275 tx_fifo.wr_addr[2] +.sym 7277 iq_tx_p_D_OUT_0 +.sym 7278 lvds_rx_24_inst.r_phase_count[0] +.sym 7280 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 7281 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 7290 tx_fifo.wr_addr[2] +.sym 7291 tx_fifo.wr_addr[3] +.sym 7293 tx_fifo.wr_addr[4] +.sym 7294 tx_fifo.wr_addr[5] +.sym 7295 tx_fifo.wr_addr[6] +.sym 7296 tx_fifo.wr_addr[7] +.sym 7297 tx_fifo.wr_addr[8] +.sym 7298 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7299 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7300 tx_fifo.wr_addr[0] +.sym 7301 r_counter +.sym 7302 tx_wr_en +.sym 7308 tx_wr_data[2] .sym 7311 $PACKER_VCC_NET -.sym 7316 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 7319 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 7322 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 7323 i_rst_b$SB_IO_IN -.sym 7324 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7325 $PACKER_VCC_NET -.sym 7333 rx_fifo.wr_addr_gray_rd_r[5] -.sym 7338 rx_fifo.mem_q.0.0_WDATA -.sym 7344 rx_fifo.mem_q.0.0_WDATA -.sym 7347 rx_fifo.rd_addr[0] -.sym 7348 rx_fifo.rd_addr[1] -.sym 7350 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7351 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 7355 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 7356 rx_fifo.rd_addr[5] -.sym 7357 rx_fifo.rd_addr[2] -.sym 7360 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 7366 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7367 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 7371 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7373 $PACKER_VCC_NET -.sym 7374 rx_fifo.rd_addr[9] -.sym 7376 rx_fifo.wr_addr_gray[1] -.sym 7377 w_smi_read_req_SB_LUT4_I1_I3[3] -.sym 7378 rx_fifo.wr_addr_gray[8] -.sym 7379 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 7380 rx_fifo.wr_addr_gray[5] -.sym 7381 rx_fifo.wr_addr[9] -.sym 7383 rx_fifo.wr_addr_gray[0] -.sym 7392 rx_fifo.rd_addr[2] -.sym 7393 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 7395 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 7396 rx_fifo.rd_addr[5] -.sym 7397 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 7398 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 7399 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7400 rx_fifo.rd_addr[9] -.sym 7401 rx_fifo.rd_addr[1] -.sym 7402 rx_fifo.rd_addr[0] -.sym 7403 r_counter_$glb_clk -.sym 7404 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 7316 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 7318 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 7319 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 7322 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7323 w_tx_fifo_pulled_data[30] +.sym 7324 lvds_tx_inst.frame_boundary +.sym 7325 i_rst_b_SB_LUT4_I3_O +.sym 7328 tx_wr_data[17] +.sym 7329 tx_fifo.wr_addr[0] +.sym 7330 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 7331 tx_wr_data[18] +.sym 7332 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 7334 tx_fifo.wr_addr_gray[0] +.sym 7335 tx_wr_en +.sym 7336 tx_fifo.wr_addr[3] +.sym 7337 $PACKER_VCC_NET +.sym 7345 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7348 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7349 tx_fifo.rd_addr[5] +.sym 7350 tx_wr_data[1] +.sym 7355 w_tx_fifo_pull +.sym 7362 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7363 tx_fifo.rd_addr[9] +.sym 7364 $PACKER_VCC_NET +.sym 7365 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7366 tx_fifo.rd_addr[6] +.sym 7369 tx_wr_data[3] +.sym 7372 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7373 tx_fifo.rd_addr[4] +.sym 7375 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7376 tx_fifo.wr_addr_gray_rd[6] +.sym 7377 tx_fifo.wr_addr_gray_rd[0] +.sym 7378 tx_fifo.wr_addr_gray_rd[1] +.sym 7379 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 7380 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 7381 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 7383 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 7392 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7393 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7395 tx_fifo.rd_addr[4] +.sym 7396 tx_fifo.rd_addr[5] +.sym 7397 tx_fifo.rd_addr[6] +.sym 7398 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7399 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7400 tx_fifo.rd_addr[9] +.sym 7401 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7402 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7403 lvds_clock_buf +.sym 7404 w_tx_fifo_pull .sym 7405 $PACKER_VCC_NET -.sym 7409 rx_fifo.mem_q.0.0_WDATA -.sym 7413 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7418 w_rx_fifo_full -.sym 7419 rx_fifo.rd_addr[9] -.sym 7423 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 7425 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 7426 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 7428 rx_fifo.rd_addr[1] -.sym 7433 rx_fifo.wr_addr[9] -.sym 7436 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 7479 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 7480 rx_fifo.wr_addr_gray_rd_r[5] -.sym 7481 rx_fifo.wr_addr_gray_rd_r[8] -.sym 7482 rx_fifo.wr_addr_gray_rd[5] -.sym 7484 rx_fifo.wr_addr_gray_rd[8] -.sym 7485 rx_fifo.wr_addr_gray_rd[1] -.sym 7521 rx_fifo.wr_addr[1] -.sym 7529 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 7530 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 7531 i_rst_b$SB_IO_IN -.sym 7533 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 7542 $PACKER_VCC_NET -.sym 7580 rx_fifo.wr_addr_gray_rd[4] -.sym 7582 rx_fifo.wr_addr_gray_rd[2] -.sym 7583 rx_fifo.wr_addr_gray_rd[6] -.sym 7584 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 7585 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 7587 rx_fifo.wr_addr_gray_rd[3] -.sym 7636 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 7682 rx_fifo.wr_addr_gray[2] -.sym 7683 rx_fifo.wr_addr_gray[3] -.sym 7684 rx_fifo.wr_addr_gray[7] -.sym 7685 rx_fifo.wr_addr_gray[6] -.sym 7689 rx_fifo.wr_addr_gray[4] -.sym 7728 i_rst_b$SB_IO_IN -.sym 7835 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 7929 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 7935 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] +.sym 7409 tx_wr_data[3] +.sym 7413 tx_wr_data[1] +.sym 7419 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 7420 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 7423 w_tx_fifo_pulled_data[23] +.sym 7429 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 7430 $PACKER_VCC_NET +.sym 7431 tx_fifo.rd_addr[5] +.sym 7432 tx_wr_en +.sym 7433 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 7435 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7436 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 7437 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 7438 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7439 w_lvds_rx_24_d1 +.sym 7440 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 7446 r_counter +.sym 7448 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7455 tx_fifo.wr_addr[2] +.sym 7457 tx_wr_data[8] +.sym 7459 tx_wr_data[10] +.sym 7460 tx_fifo.wr_addr[5] +.sym 7462 tx_fifo.wr_addr[4] +.sym 7464 tx_fifo.wr_addr[8] +.sym 7469 tx_fifo.wr_addr[7] +.sym 7470 tx_fifo.wr_addr[0] +.sym 7471 tx_fifo.wr_addr[6] +.sym 7472 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7473 tx_wr_en +.sym 7474 tx_fifo.wr_addr[3] +.sym 7475 $PACKER_VCC_NET +.sym 7478 tx_fifo.wr_addr[0] +.sym 7479 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7480 tx_fifo.wr_addr_gray[8] +.sym 7481 tx_fifo.wr_addr_gray[5] +.sym 7482 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7483 tx_fifo.wr_addr_gray[6] +.sym 7484 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 7485 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 7494 tx_fifo.wr_addr[2] +.sym 7495 tx_fifo.wr_addr[3] +.sym 7497 tx_fifo.wr_addr[4] +.sym 7498 tx_fifo.wr_addr[5] +.sym 7499 tx_fifo.wr_addr[6] +.sym 7500 tx_fifo.wr_addr[7] +.sym 7501 tx_fifo.wr_addr[8] +.sym 7502 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7503 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7504 tx_fifo.wr_addr[0] +.sym 7505 r_counter +.sym 7506 tx_wr_en +.sym 7508 tx_wr_data[8] +.sym 7512 tx_wr_data[10] +.sym 7515 $PACKER_VCC_NET +.sym 7520 tx_wr_data[9] +.sym 7522 tx_wr_data[12] +.sym 7524 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 7526 w_rx_sync_type_09 +.sym 7527 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 7528 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 7529 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7530 tx_fifo.wr_addr_gray[1] +.sym 7531 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 7532 tx_fifo.wr_addr[3] +.sym 7534 tx_wr_data[20] +.sym 7535 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 7536 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 7537 tx_fifo.wr_addr[6] +.sym 7538 tx_wr_data[23] +.sym 7539 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7540 w_load +.sym 7541 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 7542 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7548 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7550 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7551 tx_fifo.rd_addr[9] +.sym 7552 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7554 tx_fifo.rd_addr[6] +.sym 7555 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7557 tx_wr_data[11] +.sym 7560 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7561 tx_fifo.rd_addr[4] +.sym 7562 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7568 $PACKER_VCC_NET +.sym 7569 tx_fifo.rd_addr[5] +.sym 7575 w_tx_fifo_pull +.sym 7577 tx_wr_data[9] +.sym 7580 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 7581 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 7583 lvds_rx_09_inst.r_phase_count[0] +.sym 7584 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 7585 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 7586 tx_fifo.wr_addr[3] +.sym 7587 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 7596 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7597 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7599 tx_fifo.rd_addr[4] +.sym 7600 tx_fifo.rd_addr[5] +.sym 7601 tx_fifo.rd_addr[6] +.sym 7602 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7603 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7604 tx_fifo.rd_addr[9] +.sym 7605 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7606 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7607 lvds_clock_buf +.sym 7608 w_tx_fifo_pull +.sym 7609 $PACKER_VCC_NET +.sym 7613 tx_wr_data[11] +.sym 7617 tx_wr_data[9] +.sym 7622 r_counter +.sym 7623 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 7624 $PACKER_VCC_NET +.sym 7626 w_tx_fifo_full +.sym 7627 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 7628 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7629 tx_fifo.wr_addr[0] +.sym 7630 r_counter +.sym 7632 tx_fifo.rd_addr[6] +.sym 7633 $PACKER_VCC_NET +.sym 7634 tx_fifo.rd_addr_gray_wr_r[4] +.sym 7635 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 7636 w_tx_fifo_pulled_data[22] +.sym 7637 w_lvds_rx_09_d1 +.sym 7638 i_rst_b_SB_LUT4_I3_O +.sym 7639 w_ioc[0] +.sym 7640 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 7641 tx_fifo.wr_addr[7] +.sym 7642 i_rst_b_SB_LUT4_I3_O +.sym 7643 w_lvds_rx_09_d0 +.sym 7644 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 7645 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 7650 tx_fifo.wr_addr[4] +.sym 7652 tx_fifo.wr_addr[2] +.sym 7654 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7658 tx_fifo.wr_addr[0] +.sym 7659 r_counter +.sym 7661 tx_wr_en +.sym 7662 tx_fifo.wr_addr[5] +.sym 7663 tx_wr_data[22] +.sym 7664 tx_fifo.wr_addr[7] +.sym 7668 tx_fifo.wr_addr[6] +.sym 7669 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7670 $PACKER_VCC_NET +.sym 7672 tx_wr_data[20] +.sym 7677 tx_fifo.wr_addr[8] +.sym 7680 tx_fifo.wr_addr[3] +.sym 7682 tx_fifo.wr_addr[2] +.sym 7683 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 7684 tx_fifo.wr_addr[6] +.sym 7685 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7686 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 7687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 7688 tx_fifo.wr_addr_gray[0] +.sym 7689 tx_fifo.wr_addr[4] +.sym 7698 tx_fifo.wr_addr[2] +.sym 7699 tx_fifo.wr_addr[3] +.sym 7701 tx_fifo.wr_addr[4] +.sym 7702 tx_fifo.wr_addr[5] +.sym 7703 tx_fifo.wr_addr[6] +.sym 7704 tx_fifo.wr_addr[7] +.sym 7705 tx_fifo.wr_addr[8] +.sym 7706 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7707 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7708 tx_fifo.wr_addr[0] +.sym 7709 r_counter +.sym 7710 tx_wr_en +.sym 7712 tx_wr_data[20] +.sym 7716 tx_wr_data[22] +.sym 7719 $PACKER_VCC_NET +.sym 7721 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 7724 tx_fifo.wr_addr[4] +.sym 7725 r_counter +.sym 7726 tx_fifo.rd_addr[9] +.sym 7727 lvds_rx_09_inst.r_phase_count[0] +.sym 7729 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 7730 tx_fifo.wr_addr[5] +.sym 7731 r_counter +.sym 7732 i_rst_b$SB_IO_IN +.sym 7736 tx_wr_data[17] +.sym 7737 tx_fifo.wr_addr[0] +.sym 7738 lvds_rx_09_inst.r_phase_count[0] +.sym 7741 tx_fifo.wr_addr_gray[0] +.sym 7743 tx_wr_en +.sym 7744 tx_fifo.wr_addr[3] +.sym 7747 tx_wr_data[18] +.sym 7752 tx_fifo.rd_addr[6] +.sym 7754 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7757 tx_fifo.rd_addr[5] +.sym 7761 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7762 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7763 w_tx_fifo_pull +.sym 7767 tx_wr_data[23] +.sym 7768 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7772 $PACKER_VCC_NET +.sym 7778 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7779 tx_wr_data[21] +.sym 7780 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7781 tx_fifo.rd_addr[4] +.sym 7782 tx_fifo.rd_addr[9] +.sym 7784 lvds_rx_09_inst.r_phase_count[1] +.sym 7785 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 7786 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 7787 tx_fifo.wr_addr[7] +.sym 7788 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7789 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 7790 tx_fifo.wr_addr[8] +.sym 7791 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 7800 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7801 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7803 tx_fifo.rd_addr[4] +.sym 7804 tx_fifo.rd_addr[5] +.sym 7805 tx_fifo.rd_addr[6] +.sym 7806 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7807 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7808 tx_fifo.rd_addr[9] +.sym 7809 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7810 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7811 lvds_clock_buf +.sym 7812 w_tx_fifo_pull +.sym 7813 $PACKER_VCC_NET +.sym 7817 tx_wr_data[23] +.sym 7821 tx_wr_data[21] +.sym 7823 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 7827 tx_fifo.rd_addr[9] +.sym 7829 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7830 w_tx_fifo_pulled_data[21] +.sym 7833 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 7839 tx_fifo.rd_addr[5] +.sym 7840 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7845 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 7846 r_counter +.sym 7848 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 7854 tx_fifo.wr_addr[2] +.sym 7856 tx_fifo.wr_addr[6] +.sym 7857 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7858 $PACKER_VCC_NET +.sym 7861 tx_fifo.wr_addr[5] +.sym 7865 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7869 tx_fifo.wr_addr[4] +.sym 7870 tx_wr_data[14] +.sym 7873 tx_fifo.wr_addr[7] +.sym 7875 tx_fifo.wr_addr[0] +.sym 7876 tx_fifo.wr_addr[8] +.sym 7879 r_counter +.sym 7881 tx_wr_en +.sym 7882 tx_fifo.wr_addr[3] +.sym 7885 tx_wr_data[18] +.sym 7886 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 7887 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 7889 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 7890 tx_fifo.rd_addr_gray_wr_r[8] +.sym 7891 tx_fifo.rd_addr_gray_wr_r[1] +.sym 7892 tx_fifo.rd_addr_gray_wr_r[7] +.sym 7893 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 7902 tx_fifo.wr_addr[2] +.sym 7903 tx_fifo.wr_addr[3] +.sym 7905 tx_fifo.wr_addr[4] +.sym 7906 tx_fifo.wr_addr[5] +.sym 7907 tx_fifo.wr_addr[6] +.sym 7908 tx_fifo.wr_addr[7] +.sym 7909 tx_fifo.wr_addr[8] +.sym 7910 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 7911 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 7912 tx_fifo.wr_addr[0] +.sym 7913 r_counter +.sym 7914 tx_wr_en +.sym 7916 tx_wr_data[14] +.sym 7920 tx_wr_data[18] +.sym 7923 $PACKER_VCC_NET +.sym 7925 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 7929 w_ioc[1] +.sym 7930 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 7931 tx_fifo.wr_addr[7] +.sym 7932 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 7938 i_rst_b$SB_IO_IN +.sym 7950 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 7956 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 7958 w_tx_fifo_pull +.sym 7960 $PACKER_VCC_NET +.sym 7962 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 7963 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 7965 tx_wr_data[17] +.sym 7966 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 7967 tx_fifo.rd_addr[6] +.sym 7968 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 7969 tx_fifo.rd_addr[4] +.sym 7976 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 7977 tx_fifo.rd_addr[5] +.sym 7981 tx_wr_data[19] +.sym 7986 tx_fifo.rd_addr[9] +.sym 8000 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 8001 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 8003 tx_fifo.rd_addr[4] +.sym 8004 tx_fifo.rd_addr[5] +.sym 8005 tx_fifo.rd_addr[6] +.sym 8006 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 8007 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 8008 tx_fifo.rd_addr[9] +.sym 8009 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 8010 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 8011 lvds_clock_buf +.sym 8012 w_tx_fifo_pull +.sym 8013 $PACKER_VCC_NET +.sym 8017 tx_wr_data[19] +.sym 8021 tx_wr_data[17] +.sym 8027 tx_fifo.rd_addr_gray_wr_r[7] +.sym 8029 tx_fifo.rd_addr[6] +.sym 8033 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 8034 tx_fifo.rd_addr[9] +.sym 8036 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 8048 o_shdn_rx_lna$SB_IO_OUT .sym 8093 w_smi_data_output[6] .sym 8095 w_smi_data_direction .sym 8099 $PACKER_VCC_NET -.sym 8106 w_smi_data_output[6] +.sym 8104 $PACKER_VCC_NET .sym 8112 w_smi_data_direction -.sym 8115 $PACKER_VCC_NET -.sym 8118 tx_fifo.rd_addr[0] -.sym 8119 tx_fifo.rd_addr[2] -.sym 8120 tx_fifo.rd_addr[1] -.sym 8121 tx_fifo.rd_addr[4] -.sym 8122 tx_fifo.rd_addr_gray[2] -.sym 8123 tx_fifo.rd_addr[3] -.sym 8124 tx_fifo.rd_addr_gray[3] -.sym 8125 tx_fifo.rd_addr[7] -.sym 8137 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8140 rx_fifo.rd_addr[5] -.sym 8168 tx_fifo.rd_addr_gray_wr[3] -.sym 8171 tx_fifo.rd_addr_gray_wr[5] -.sym 8176 tx_fifo.rd_addr_gray[5] -.sym 8180 tx_fifo.rd_addr_gray[2] -.sym 8182 tx_fifo.rd_addr_gray[3] -.sym 8190 tx_fifo.rd_addr_gray_wr[6] -.sym 8191 tx_fifo.rd_addr_gray[6] -.sym 8193 tx_fifo.rd_addr_gray[3] -.sym 8202 tx_fifo.rd_addr_gray[2] -.sym 8205 tx_fifo.rd_addr_gray_wr[5] -.sym 8212 tx_fifo.rd_addr_gray[5] -.sym 8218 tx_fifo.rd_addr_gray_wr[6] -.sym 8225 tx_fifo.rd_addr_gray_wr[3] -.sym 8231 tx_fifo.rd_addr_gray[6] -.sym 8240 r_counter_$glb_clk -.sym 8246 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 8247 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] -.sym 8248 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 8249 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 8250 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 8251 w_tx_fifo_pull -.sym 8252 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 8253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] -.sym 8260 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8262 tx_fifo.rd_addr_gray_wr[2] -.sym 8264 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8268 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 8269 tx_fifo.rd_addr[1] -.sym 8287 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 8288 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 8294 tx_fifo.rd_addr[7] -.sym 8295 i_rst_b_SB_LUT4_I3_O -.sym 8298 tx_fifo.rd_addr[2] -.sym 8299 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 8300 tx_fifo.rd_addr[1] -.sym 8301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8307 tx_fifo.rd_addr[3] -.sym 8308 w_smi_data_direction -.sym 8309 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 8312 tx_fifo.rd_addr_gray[6] -.sym 8315 i_rst_b_SB_LUT4_I3_O -.sym 8323 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 8324 w_rx_fifo_pulled_data[21] -.sym 8326 w_rx_fifo_pulled_data[15] -.sym 8327 smi_ctrl_ins.int_cnt_rx[4] -.sym 8333 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 8335 w_rx_fifo_pulled_data[13] -.sym 8336 w_rx_fifo_pulled_data[23] -.sym 8337 smi_ctrl_ins.int_cnt_rx[3] -.sym 8344 w_rx_fifo_pulled_data[22] -.sym 8348 w_rx_fifo_pulled_data[20] -.sym 8352 w_rx_fifo_pulled_data[26] -.sym 8356 smi_ctrl_ins.int_cnt_rx[4] -.sym 8357 smi_ctrl_ins.int_cnt_rx[3] -.sym 8358 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 8359 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 8362 w_rx_fifo_pulled_data[13] -.sym 8368 w_rx_fifo_pulled_data[26] -.sym 8376 w_rx_fifo_pulled_data[15] -.sym 8380 w_rx_fifo_pulled_data[23] -.sym 8388 w_rx_fifo_pulled_data[21] -.sym 8394 w_rx_fifo_pulled_data[20] -.sym 8398 w_rx_fifo_pulled_data[22] -.sym 8402 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8403 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8405 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] -.sym 8406 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] -.sym 8407 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 8408 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] -.sym 8409 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 8410 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] -.sym 8411 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 8412 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 8423 smi_ctrl_ins.int_cnt_rx[4] -.sym 8435 i_rst_b$SB_IO_IN -.sym 8436 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 8439 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8440 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 8448 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 8449 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8452 smi_ctrl_ins.int_cnt_rx[3] -.sym 8455 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 8457 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 8458 w_rx_09_fifo_data[26] -.sym 8459 smi_ctrl_ins.int_cnt_rx[4] -.sym 8460 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 8464 tx_fifo.rd_addr[2] -.sym 8466 tx_fifo.rd_addr[1] -.sym 8468 w_rx_24_fifo_data[26] -.sym 8469 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 8476 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8498 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 8505 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 8510 tx_fifo.rd_addr[1] -.sym 8511 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 8512 tx_fifo.rd_addr[2] -.sym 8515 smi_ctrl_ins.int_cnt_rx[4] -.sym 8516 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 8517 smi_ctrl_ins.int_cnt_rx[3] -.sym 8518 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8521 w_rx_09_fifo_data[26] -.sym 8522 w_rx_24_fifo_data[26] -.sym 8523 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 8525 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 8526 lvds_clock_$glb_clk -.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8528 w_smi_data_output[2] -.sym 8529 w_smi_data_output[7] -.sym 8530 w_smi_data_output[6] -.sym 8531 smi_ctrl_ins.w_fifo_pull_trigger -.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 8533 w_smi_data_output[5] -.sym 8534 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 8542 w_rx_fifo_pulled_data[14] -.sym 8545 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 8548 rx_fifo.wr_addr[9] -.sym 8550 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8556 smi_ctrl_ins.int_cnt_rx[3] -.sym 8558 smi_ctrl_ins.int_cnt_rx[4] -.sym 8560 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8561 tx_fifo.rd_addr[6] -.sym 8562 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 8570 w_rx_fifo_pulled_data[25] -.sym 8571 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 8574 w_rx_fifo_pulled_data[27] -.sym 8576 smi_ctrl_ins.int_cnt_rx[4] -.sym 8582 smi_ctrl_ins.int_cnt_rx[3] -.sym 8584 w_rx_fifo_pulled_data[12] -.sym 8586 w_rx_fifo_pulled_data[24] -.sym 8589 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 8590 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 8592 w_rx_fifo_pulled_data[14] -.sym 8598 w_rx_fifo_pulled_data[6] -.sym 8599 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8605 w_rx_fifo_pulled_data[24] -.sym 8610 w_rx_fifo_pulled_data[25] -.sym 8617 w_rx_fifo_pulled_data[27] -.sym 8621 w_rx_fifo_pulled_data[12] -.sym 8628 w_rx_fifo_pulled_data[6] -.sym 8634 w_rx_fifo_pulled_data[14] -.sym 8638 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 8639 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 8640 smi_ctrl_ins.int_cnt_rx[3] -.sym 8641 smi_ctrl_ins.int_cnt_rx[4] -.sym 8644 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 8645 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 8646 smi_ctrl_ins.int_cnt_rx[4] -.sym 8647 smi_ctrl_ins.int_cnt_rx[3] -.sym 8648 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8650 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8651 smi_ctrl_ins.r_fifo_pull -.sym 8654 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 8657 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 8658 smi_ctrl_ins.r_fifo_pull_1 -.sym 8659 rx_fifo.rd_addr[9] -.sym 8661 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 8662 rx_fifo.rd_addr[9] -.sym 8663 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.sym 8117 w_smi_data_output[6] +.sym 8118 smi_ctrl_ins.d_q3[1] +.sym 8119 smi_ctrl_ins.d_q3[2] +.sym 8120 smi_ctrl_ins.d_q2[6] +.sym 8121 smi_ctrl_ins.d_q2[2] +.sym 8122 smi_ctrl_ins.d_q1[2] +.sym 8123 smi_ctrl_ins.d_q1[4] +.sym 8124 smi_ctrl_ins.d_q1[6] +.sym 8125 smi_ctrl_ins.d_q2[0] +.sym 8140 tx_wr_data[17] +.sym 8147 smi_ctrl_ins.frame_sr[9] +.sym 8150 w_smi_data_output[0] +.sym 8151 $PACKER_VCC_NET +.sym 8152 w_smi_data_input[7] +.sym 8162 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 8163 w_rx_09_fifo_data[8] +.sym 8164 i_rst_b_SB_LUT4_I3_O +.sym 8165 w_rx_fifo_pulled_data[10] +.sym 8166 channel +.sym 8168 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8169 smi_ctrl_ins.frame_sr[7] +.sym 8171 w_rx_24_fifo_data[8] +.sym 8172 smi_ctrl_ins.frame_sr[15] +.sym 8173 smi_ctrl_ins.byte_ix[3] +.sym 8176 smi_ctrl_ins.soe_and_reset +.sym 8177 w_rx_fifo_pulled_data[9] +.sym 8182 smi_ctrl_ins.byte_ix[2] +.sym 8183 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8185 smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[1] +.sym 8188 smi_ctrl_ins.frame_sr[23] +.sym 8191 w_rx_fifo_pulled_data[19] +.sym 8199 smi_ctrl_ins.frame_sr[15] +.sym 8200 smi_ctrl_ins.frame_sr[7] +.sym 8201 smi_ctrl_ins.frame_sr[23] +.sym 8202 smi_ctrl_ins.byte_ix[3] +.sym 8205 channel +.sym 8207 w_rx_24_fifo_data[8] +.sym 8208 w_rx_09_fifo_data[8] +.sym 8211 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8212 smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[1] +.sym 8213 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8218 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8219 smi_ctrl_ins.byte_ix[2] +.sym 8224 w_rx_fifo_pulled_data[19] +.sym 8230 w_rx_fifo_pulled_data[10] +.sym 8235 w_rx_fifo_pulled_data[9] +.sym 8239 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 8240 smi_ctrl_ins.soe_and_reset +.sym 8241 i_rst_b_SB_LUT4_I3_O +.sym 8242 w_smi_data_input[2] +.sym 8244 w_smi_data_input[1] +.sym 8246 smi_ctrl_ins.d_q2[1] +.sym 8247 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 8248 smi_ctrl_ins.d_q3[0] +.sym 8249 smi_ctrl_ins.d_q3[4] +.sym 8250 smi_ctrl_ins.d_q3[6] +.sym 8251 smi_ctrl_ins.d_q3[3] +.sym 8252 smi_ctrl_ins.d_q1[1] +.sym 8253 smi_ctrl_ins.d_q2[4] +.sym 8258 i_smi_swe_srw$SB_IO_IN +.sym 8260 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 8263 $PACKER_VCC_NET +.sym 8264 r_counter +.sym 8265 $PACKER_VCC_NET +.sym 8267 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 8271 smi_ctrl_ins.frame_sr[7] +.sym 8276 smi_ctrl_ins.byte_ix[2] +.sym 8277 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8280 w_smi_data_direction +.sym 8283 w_smi_data_input[1] +.sym 8286 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8287 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8290 w_rx_24_fifo_data[8] +.sym 8291 smi_ctrl_ins.frame_sr[11] +.sym 8292 w_smi_data_output[2] +.sym 8295 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8297 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 8299 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 8303 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8305 smi_ctrl_ins.frame_sr[14] +.sym 8306 r_counter +.sym 8308 w_smi_data_output[6] +.sym 8309 w_smi_data_output[1] +.sym 8311 smi_ctrl_ins.frame_sr[8] +.sym 8315 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8323 r_counter +.sym 8324 smi_ctrl_ins.d_byte[0] +.sym 8327 i_rst_b_SB_LUT4_I3_O +.sym 8334 smi_ctrl_ins.d_byte[1] +.sym 8336 smi_ctrl_ins.d_byte[5] +.sym 8343 smi_ctrl_ins.d_byte[6] +.sym 8346 smi_ctrl_ins.d_byte[4] +.sym 8347 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8348 smi_ctrl_ins.d_byte[3] +.sym 8350 smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E +.sym 8354 smi_ctrl_ins.d_byte[2] +.sym 8358 smi_ctrl_ins.d_byte[3] +.sym 8362 smi_ctrl_ins.d_byte[0] +.sym 8368 smi_ctrl_ins.d_byte[1] +.sym 8377 smi_ctrl_ins.d_byte[5] +.sym 8383 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8389 smi_ctrl_ins.d_byte[2] +.sym 8394 smi_ctrl_ins.d_byte[6] +.sym 8398 smi_ctrl_ins.d_byte[4] +.sym 8402 smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E +.sym 8403 r_counter +.sym 8404 i_rst_b_SB_LUT4_I3_O +.sym 8405 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8406 smi_ctrl_ins.d_byte[3] +.sym 8407 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 8408 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 8409 smi_ctrl_ins.d_byte[6] +.sym 8410 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[0] +.sym 8411 smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E +.sym 8412 smi_ctrl_ins.d_byte[2] +.sym 8417 smi_ctrl_ins.byte_ix[3] +.sym 8418 w_rx_fifo_pull +.sym 8419 w_rx_fifo_pull +.sym 8420 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 8422 rx_fifo.rd_addr[9] +.sym 8423 i_rst_b_SB_LUT4_I3_O +.sym 8424 r_counter +.sym 8425 rx_fifo.rd_addr[9] +.sym 8426 w_smi_data_direction +.sym 8427 r_counter +.sym 8428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 8429 smi_ctrl_ins.frame_sr[7] +.sym 8430 i_rst_b_SB_LUT4_I3_O +.sym 8432 smi_ctrl_ins.d_byte[4] +.sym 8433 i_rst_b_SB_LUT4_I3_O +.sym 8435 smi_ctrl_ins.d_byte[1] +.sym 8436 w_rx_fifo_data[0] +.sym 8437 smi_ctrl_ins.frame_sr[21] +.sym 8438 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8439 w_rx_fifo_data[10] +.sym 8446 smi_ctrl_ins.d_byte[1] +.sym 8455 r_counter +.sym 8456 smi_ctrl_ins.d_byte[4] +.sym 8457 smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E +.sym 8458 smi_ctrl_ins.d_byte[0] +.sym 8459 i_rst_b_SB_LUT4_I3_O +.sym 8462 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8463 smi_ctrl_ins.d_byte[3] +.sym 8465 smi_ctrl_ins.d_byte[5] +.sym 8466 smi_ctrl_ins.d_byte[6] +.sym 8477 smi_ctrl_ins.d_byte[2] +.sym 8480 smi_ctrl_ins.d_byte[5] +.sym 8485 smi_ctrl_ins.d_byte[4] +.sym 8491 smi_ctrl_ins.d_byte[2] +.sym 8499 smi_ctrl_ins.d_byte[3] +.sym 8503 smi_ctrl_ins.d_byte[6] +.sym 8509 smi_ctrl_ins.d_byte[0] +.sym 8517 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8522 smi_ctrl_ins.d_byte[1] +.sym 8525 smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E +.sym 8526 r_counter +.sym 8527 i_rst_b_SB_LUT4_I3_O +.sym 8528 w_rx_fifo_data[22] +.sym 8529 smi_ctrl_ins.frame_sr[4] +.sym 8530 w_rx_fifo_data[20] +.sym 8531 smi_ctrl_ins.frame_sr[3] +.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[3] +.sym 8533 smi_ctrl_ins.frame_sr[0] +.sym 8534 smi_ctrl_ins.frame_sr[7] +.sym 8535 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 8537 smi_ctrl_ins.soe_and_reset +.sym 8539 tx_wr_en +.sym 8540 smi_ctrl_ins.soe_and_reset +.sym 8542 smi_ctrl_ins.frame_sr[16] +.sym 8543 smi_ctrl_ins.soe_and_reset +.sym 8545 smi_ctrl_ins.soe_and_reset +.sym 8546 i_rst_b_SB_LUT4_I3_O +.sym 8547 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 8548 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8550 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 8551 rx_fifo.wr_addr[9] +.sym 8552 tx_wr_data[3] +.sym 8554 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 8555 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8556 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 8558 w_tx_fsm_state[1] +.sym 8559 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8560 smi_ctrl_ins.byte_ix[0] +.sym 8561 lvds_tx_inst.r_fifo_data[26] +.sym 8563 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] +.sym 8570 smi_ctrl_ins.d_byte[3] +.sym 8571 smi_ctrl_ins.frame_sr[18] +.sym 8573 smi_ctrl_ins.d_byte[6] +.sym 8575 smi_ctrl_ins.frame_sr[13] +.sym 8578 r_counter +.sym 8579 smi_ctrl_ins.frame_sr[10] +.sym 8580 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8581 smi_ctrl_ins.frame_sr[22] +.sym 8582 i_rst_b_SB_LUT4_I3_O +.sym 8585 smi_ctrl_ins.frame_sr[9] +.sym 8588 smi_ctrl_ins.frame_sr[8] +.sym 8604 smi_ctrl_ins.frame_sr[13] +.sym 8608 smi_ctrl_ins.frame_sr[8] +.sym 8615 smi_ctrl_ins.d_byte[3] +.sym 8623 smi_ctrl_ins.d_byte[6] +.sym 8626 smi_ctrl_ins.frame_sr[18] +.sym 8633 smi_ctrl_ins.frame_sr[9] +.sym 8639 smi_ctrl_ins.frame_sr[10] +.sym 8646 smi_ctrl_ins.frame_sr[22] +.sym 8648 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8649 r_counter +.sym 8650 i_rst_b_SB_LUT4_I3_O +.sym 8651 tx_wr_data[13] +.sym 8652 tx_wr_data[28] +.sym 8653 tx_wr_data[29] +.sym 8654 tx_wr_data[14] +.sym 8655 tx_wr_data[26] +.sym 8656 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 8657 tx_wr_data[3] +.sym 8658 tx_wr_data[27] +.sym 8659 i_rst_b_SB_LUT4_I3_O +.sym 8660 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 8662 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 8664 r_counter +.sym 8665 w_rx_fifo_pulled_data[19] +.sym 8666 w_rx_24_fifo_data[20] +.sym 8667 tx_wr_data[18] .sym 8668 $PACKER_VCC_NET -.sym 8669 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 8672 rx_fifo.rd_addr[5] -.sym 8674 w_smi_data_output[6] -.sym 8675 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 8683 rx_fifo.wr_addr[3] -.sym 8685 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 8692 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 8693 smi_ctrl_ins.int_cnt_rx[4] -.sym 8694 w_rx_fifo_pulled_data[16] -.sym 8696 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 8701 w_rx_fifo_pulled_data[4] -.sym 8710 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 8711 w_rx_fifo_pulled_data[8] -.sym 8713 w_rx_fifo_pulled_data[7] -.sym 8716 smi_ctrl_ins.int_cnt_rx[3] -.sym 8717 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 8728 w_rx_fifo_pulled_data[8] -.sym 8739 w_rx_fifo_pulled_data[16] -.sym 8743 w_rx_fifo_pulled_data[7] -.sym 8749 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 8750 smi_ctrl_ins.int_cnt_rx[4] -.sym 8751 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 8752 smi_ctrl_ins.int_cnt_rx[3] -.sym 8755 smi_ctrl_ins.int_cnt_rx[3] -.sym 8756 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 8757 smi_ctrl_ins.int_cnt_rx[4] -.sym 8758 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 8768 w_rx_fifo_pulled_data[4] -.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 8775 w_smi_data_output[1] -.sym 8776 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 8777 w_smi_data_output[0] -.sym 8780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 8788 w_rx_fifo_pulled_data[16] -.sym 8797 rx_fifo.wr_addr[8] -.sym 8798 rx_fifo.wr_addr_gray_rd_r[5] -.sym 8799 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8800 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 8805 w_smi_data_direction -.sym 8806 rx_fifo.rd_addr[0] -.sym 8815 rx_fifo.rd_addr[0] -.sym 8818 rx_fifo.wr_addr[4] -.sym 8819 smi_ctrl_ins.int_cnt_rx[4] -.sym 8823 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 8826 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 8827 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 8828 smi_ctrl_ins.int_cnt_rx[3] -.sym 8833 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 8844 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 8845 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8850 rx_fifo.rd_addr[0] -.sym 8862 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 8866 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 8867 smi_ctrl_ins.int_cnt_rx[4] -.sym 8868 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 8869 smi_ctrl_ins.int_cnt_rx[3] -.sym 8873 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8879 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 8892 rx_fifo.wr_addr[4] -.sym 8894 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 8895 r_counter_$glb_clk -.sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8898 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 8899 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 8900 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 8901 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 8902 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 8903 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 8904 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 8906 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 8908 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 8909 rx_fifo.rd_addr[0] -.sym 8911 rx_fifo.rd_addr[5] -.sym 8916 $PACKER_VCC_NET -.sym 8919 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8920 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 8921 rx_fifo.wr_addr[3] -.sym 8922 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8923 rx_fifo.wr_addr[5] -.sym 8924 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8925 rx_fifo.wr_addr[7] -.sym 8926 i_rst_b$SB_IO_IN -.sym 8927 rx_fifo.wr_addr[0] -.sym 8928 rx_fifo.wr_addr[9] -.sym 8930 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 8931 rx_fifo.wr_addr[6] -.sym 8932 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 8941 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 8942 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8943 rx_fifo.rd_addr[5] -.sym 8944 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8945 rx_fifo.wr_addr[0] -.sym 8948 rx_fifo.wr_addr_gray_rd_r[5] -.sym 8949 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8950 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 8953 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8954 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 8965 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 8971 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 8973 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 8974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 8984 rx_fifo.wr_addr_gray_rd_r[5] -.sym 8985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 8986 rx_fifo.rd_addr[5] -.sym 8991 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 8997 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9009 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9013 rx_fifo.wr_addr[0] -.sym 9017 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 9018 lvds_clock_$glb_clk -.sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9020 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9021 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 9022 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 9023 w_smi_data_direction -.sym 9024 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 9025 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 9026 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 9027 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 9028 rx_fifo.wr_addr[3] -.sym 9031 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9032 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 9034 rx_fifo.wr_addr[9] -.sym 9035 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 9036 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 9038 rx_fifo.rd_addr[1] -.sym 9040 rx_fifo.wr_addr[4] -.sym 9042 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 9044 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 9045 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 9046 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9047 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9049 rx_fifo.rd_addr_gray_wr_r[4] -.sym 9050 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 9051 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9052 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9053 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9055 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 9062 rx_fifo.wr_addr[1] -.sym 9064 rx_fifo.wr_addr[4] -.sym 9068 rx_fifo.wr_addr[0] -.sym 9072 rx_fifo.wr_addr[2] -.sym 9073 rx_fifo.wr_addr[3] -.sym 9083 rx_fifo.wr_addr[5] -.sym 9085 rx_fifo.wr_addr[7] -.sym 9091 rx_fifo.wr_addr[6] -.sym 9093 $nextpnr_ICESTORM_LC_8$O -.sym 9095 rx_fifo.wr_addr[0] -.sym 9099 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9102 rx_fifo.wr_addr[1] -.sym 9105 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9108 rx_fifo.wr_addr[2] -.sym 9109 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9111 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9114 rx_fifo.wr_addr[3] -.sym 9115 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9117 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9119 rx_fifo.wr_addr[4] -.sym 9121 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9123 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9125 rx_fifo.wr_addr[5] -.sym 9127 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9129 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 9131 rx_fifo.wr_addr[6] -.sym 9133 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 9135 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 9138 rx_fifo.wr_addr[7] -.sym 9139 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 9143 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9144 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] -.sym 9145 spi_if_ins.spi.SCKr[0] -.sym 9146 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 9147 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 9148 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 9150 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 9158 w_smi_data_direction +.sym 8669 r_counter +.sym 8670 i_rst_b_SB_LUT4_I3_O +.sym 8671 lvds_tx_inst.r_fifo_data[14] +.sym 8675 w_rx_fifo_data[20] +.sym 8676 smi_ctrl_ins.frame_sr[11] +.sym 8677 w_rx_24_fifo_data[16] +.sym 8678 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 8679 w_rx_24_fifo_data[11] +.sym 8680 w_rx_09_fifo_data[20] +.sym 8681 smi_ctrl_ins.frame_sr[0] +.sym 8682 w_rx_24_fifo_data[23] +.sym 8684 w_rx_24_fifo_data[19] +.sym 8685 w_rx_24_fifo_data[24] +.sym 8692 r_counter +.sym 8696 i_rst_b_SB_LUT4_I3_O +.sym 8697 w_tx_fifo_pulled_data[26] +.sym 8698 i_smi_swe_srw$SB_IO_IN +.sym 8699 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8700 smi_ctrl_ins.swe_q1 +.sym 8706 channel +.sym 8707 w_rx_24_fifo_data[10] +.sym 8708 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8709 smi_ctrl_ins.push_req +.sym 8711 w_tx_fifo_full +.sym 8712 smi_ctrl_ins.swe_q2_d +.sym 8714 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 8716 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 8717 smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] +.sym 8720 smi_ctrl_ins.byte_ix[0] +.sym 8721 lvds_tx_inst.r_fifo_data[26] +.sym 8722 smi_ctrl_ins.swe_q2 +.sym 8723 w_rx_09_fifo_data[10] +.sym 8727 i_smi_swe_srw$SB_IO_IN +.sym 8731 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8732 smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] +.sym 8733 smi_ctrl_ins.byte_ix[0] +.sym 8734 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 8738 w_tx_fifo_full +.sym 8740 smi_ctrl_ins.push_req +.sym 8743 w_tx_fifo_pulled_data[26] +.sym 8744 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 8745 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 8746 lvds_tx_inst.r_fifo_data[26] +.sym 8752 smi_ctrl_ins.swe_q2 +.sym 8756 w_rx_09_fifo_data[10] +.sym 8757 channel +.sym 8758 w_rx_24_fifo_data[10] +.sym 8762 smi_ctrl_ins.swe_q1 +.sym 8768 smi_ctrl_ins.swe_q2_d +.sym 8769 smi_ctrl_ins.swe_q2 +.sym 8772 r_counter +.sym 8773 i_rst_b_SB_LUT4_I3_O +.sym 8774 w_rx_24_fifo_data[11] +.sym 8775 w_rx_24_fifo_data[25] +.sym 8776 w_rx_24_fifo_data[28] +.sym 8777 w_rx_24_fifo_data[4] +.sym 8778 w_rx_24_fifo_data[21] +.sym 8779 w_rx_24_fifo_data[3] +.sym 8780 w_rx_24_fifo_data[29] +.sym 8781 w_rx_24_fifo_data[2] +.sym 8786 rx_fifo.wr_addr[3] +.sym 8787 $PACKER_VCC_NET +.sym 8788 w_rx_fifo_data[12] +.sym 8790 rx_fifo.wr_addr[4] +.sym 8792 tx_wr_en +.sym 8793 r_counter +.sym 8794 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 8795 w_rx_24_fifo_data[10] +.sym 8796 r_counter +.sym 8797 $PACKER_VCC_NET +.sym 8798 smi_ctrl_ins.frame_sr[14] +.sym 8799 tx_wr_en +.sym 8800 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 8801 w_rx_fifo_data[23] +.sym 8802 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 8803 smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] +.sym 8804 w_rx_24_fifo_data[26] +.sym 8806 w_rx_24_fifo_data[1] +.sym 8807 w_rx_09_fifo_data[9] +.sym 8808 w_rx_09_fifo_data[21] +.sym 8809 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 8821 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 8823 w_rx_24_fifo_data[15] +.sym 8826 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 8828 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 8831 w_rx_24_fifo_data[11] +.sym 8836 w_rx_24_fifo_data[13] +.sym 8837 w_rx_24_fifo_data[16] +.sym 8839 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8840 w_rx_24_fifo_data[25] +.sym 8841 channel +.sym 8844 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 8845 w_rx_24_fifo_data[24] +.sym 8846 w_rx_09_fifo_data[15] +.sym 8849 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8851 w_rx_24_fifo_data[13] +.sym 8860 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 8862 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 8868 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8869 w_rx_24_fifo_data[25] +.sym 8874 w_rx_24_fifo_data[16] +.sym 8875 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8878 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8879 w_rx_24_fifo_data[11] +.sym 8885 w_rx_24_fifo_data[15] +.sym 8886 w_rx_09_fifo_data[15] +.sym 8887 channel +.sym 8890 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8892 w_rx_24_fifo_data[24] +.sym 8894 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 8895 lvds_clock_buf +.sym 8896 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 8897 w_rx_09_fifo_data[3] +.sym 8898 w_rx_09_fifo_data[17] +.sym 8899 w_rx_09_fifo_data[20] +.sym 8900 w_rx_09_fifo_data[11] +.sym 8901 w_rx_09_fifo_data[13] +.sym 8903 w_rx_09_fifo_data[6] +.sym 8904 w_rx_09_fifo_data[23] +.sym 8906 w_rx_24_fifo_data[3] +.sym 8909 w_tx_fifo_full +.sym 8910 i_rst_b_SB_LUT4_I3_O +.sym 8911 w_rx_24_fifo_data[13] +.sym 8912 w_rx_24_fifo_data[4] +.sym 8914 w_rx_24_fifo_data[2] +.sym 8915 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 8917 w_rx_fifo_pulled_data[12] +.sym 8918 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 8919 w_rx_24_fifo_data[18] +.sym 8920 w_rx_24_fifo_data[28] +.sym 8921 i_sck$SB_IO_IN +.sym 8922 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 8923 w_rx_fifo_data[0] +.sym 8925 w_rx_fifo_push +.sym 8926 w_rx_09_fifo_data[6] +.sym 8928 tx_fifo.wr_addr[2] +.sym 8930 lvds_rx_24_inst.r_sync_input +.sym 8931 w_rx_09_fifo_data[1] +.sym 8932 w_rx_24_fifo_data[0] +.sym 8939 lvds_rx_09_inst.r_sync_input +.sym 8940 smi_ctrl_ins.push_req +.sym 8941 w_rx_24_fifo_data[0] +.sym 8942 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 8943 w_rx_fifo_push +.sym 8944 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 8945 w_rx_24_fifo_data[23] +.sym 8946 w_rx_09_fifo_data[27] +.sym 8947 w_lvds_rx_09_d1 +.sym 8949 w_rx_24_fifo_data[27] +.sym 8950 w_lvds_rx_09_d0 +.sym 8951 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 8952 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8954 channel +.sym 8956 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 8957 w_tx_fifo_full +.sym 8961 tx_fifo.rd_addr[5] +.sym 8962 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 8963 tx_fifo.rd_addr[4] +.sym 8965 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 8967 smi_ctrl_ins.byte_ix[3] +.sym 8968 w_rx_09_fifo_data[0] +.sym 8969 w_rx_09_fifo_data[23] +.sym 8971 smi_ctrl_ins.push_req +.sym 8972 w_tx_fifo_full +.sym 8973 smi_ctrl_ins.byte_ix[3] +.sym 8974 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 8977 w_lvds_rx_09_d0 +.sym 8983 tx_fifo.rd_addr[4] +.sym 8985 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 8986 tx_fifo.rd_addr[5] +.sym 8990 w_rx_24_fifo_data[27] +.sym 8991 w_rx_09_fifo_data[27] +.sym 8992 channel +.sym 8995 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 8996 w_rx_fifo_push +.sym 8997 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 8998 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 9001 w_rx_09_fifo_data[0] +.sym 9003 w_rx_24_fifo_data[0] +.sym 9004 channel +.sym 9007 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 9008 lvds_rx_09_inst.r_sync_input +.sym 9009 w_lvds_rx_09_d1 +.sym 9013 w_rx_24_fifo_data[23] +.sym 9014 channel +.sym 9016 w_rx_09_fifo_data[23] +.sym 9017 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 9018 lvds_clock_buf +.sym 9020 spi_if_ins.w_rx_data[6] +.sym 9021 spi_if_ins.w_rx_data[1] +.sym 9022 spi_if_ins.w_rx_data[5] +.sym 9023 spi_if_ins.w_rx_data[0] +.sym 9024 spi_if_ins.w_rx_data[4] +.sym 9025 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 9027 spi_if_ins.w_rx_data[2] +.sym 9032 i_rst_b_SB_LUT4_I3_O +.sym 9033 w_lvds_rx_09_d1 +.sym 9035 w_tx_fifo_pulled_data[22] +.sym 9036 w_rx_09_fifo_data[2] +.sym 9037 w_tx_data_smi[1] +.sym 9038 w_lvds_rx_09_d0 +.sym 9039 i_rst_b_SB_LUT4_I3_O +.sym 9040 w_rx_09_fifo_data[15] +.sym 9041 w_rx_24_fifo_data[23] +.sym 9042 w_rx_09_fifo_data[16] +.sym 9043 i_rst_b_SB_LUT4_I3_O +.sym 9045 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 9046 i_mosi$SB_IO_IN +.sym 9047 lvds_tx_inst.r_fifo_data[30] +.sym 9048 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 9049 tx_wr_data[3] +.sym 9050 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 9052 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 9054 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 9055 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 9063 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 9064 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 9065 w_lvds_rx_24_d0 +.sym 9067 w_lvds_rx_24_d1 +.sym 9070 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 9083 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9088 tx_fifo.wr_addr[2] +.sym 9089 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9090 lvds_rx_24_inst.r_sync_input +.sym 9096 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9097 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9112 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 9113 w_lvds_rx_24_d1 +.sym 9115 lvds_rx_24_inst.r_sync_input +.sym 9120 w_lvds_rx_24_d0 +.sym 9130 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9131 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9132 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 9137 tx_fifo.wr_addr[2] +.sym 9140 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 9141 lvds_clock_buf +.sym 9143 spi_if_ins.spi.r_rx_byte[5] +.sym 9144 spi_if_ins.spi.r_rx_byte[4] +.sym 9145 spi_if_ins.spi.r_rx_byte[3] +.sym 9146 spi_if_ins.spi.r_rx_byte[6] +.sym 9147 spi_if_ins.spi.r_rx_byte[1] +.sym 9148 spi_if_ins.spi.r_rx_byte[2] +.sym 9149 spi_if_ins.spi.r_rx_byte[7] +.sym 9150 spi_if_ins.spi.r_rx_byte[0] +.sym 9154 tx_fifo.wr_addr[0] +.sym 9155 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 9156 w_rx_fifo_full +.sym 9157 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 9159 $PACKER_VCC_NET .sym 9160 $PACKER_VCC_NET -.sym 9161 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 9163 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 9164 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 9165 rx_fifo.rd_addr[5] -.sym 9167 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 9168 rx_fifo.rd_addr[9] -.sym 9169 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 9170 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9171 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 9172 rx_fifo.rd_addr_gray[0] -.sym 9173 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 9174 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 9175 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9176 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9177 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9179 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 9188 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9189 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9190 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9193 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 9195 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9196 rx_fifo.wr_addr[8] -.sym 9198 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 9199 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 9202 rx_fifo.wr_addr[9] -.sym 9205 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] -.sym 9206 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9207 rx_fifo.rd_addr_gray_wr_r[1] -.sym 9210 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 9211 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9212 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9216 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 9218 rx_fifo.wr_addr[8] -.sym 9220 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 9224 rx_fifo.wr_addr[9] -.sym 9226 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 9229 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9231 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 9235 rx_fifo.rd_addr_gray_wr_r[1] -.sym 9236 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9237 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] -.sym 9238 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 9242 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9244 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 9247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 9248 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9250 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9255 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9256 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9261 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9262 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9264 r_counter_$glb_clk -.sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9266 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 9267 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] -.sym 9268 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 9269 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 9270 w_rx_fifo_full -.sym 9271 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 9272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 9273 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 9290 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9291 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 9292 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 9293 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 9294 rx_fifo.wr_addr_gray_rd_r[5] -.sym 9295 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 9296 rx_fifo.wr_addr_gray_rd_r[8] -.sym 9297 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 9301 rx_fifo.wr_addr_gray_rd[3] -.sym 9307 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 9308 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9309 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9310 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 9312 rx_fifo.rd_addr[1] -.sym 9313 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9314 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9315 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 9318 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9319 rx_fifo.rd_addr_gray_wr_r[4] -.sym 9320 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 9322 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 9325 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 9326 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 9327 rx_fifo.wr_addr_gray_rd_r[5] -.sym 9329 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 9331 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 9334 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 9338 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 9343 rx_fifo.rd_addr[1] -.sym 9346 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 9347 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 9348 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 9349 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 9352 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 9353 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9354 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 9355 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9358 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9359 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9360 rx_fifo.rd_addr_gray_wr_r[4] -.sym 9361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 9370 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 9371 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 9372 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 9373 rx_fifo.wr_addr_gray_rd_r[5] -.sym 9376 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 9382 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 9385 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9386 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 9387 r_counter_$glb_clk -.sym 9388 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9389 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 9390 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 9391 rx_fifo.rd_addr_gray[1] -.sym 9392 rx_fifo.rd_addr_gray[6] -.sym 9393 rx_fifo.rd_addr_gray[2] -.sym 9394 rx_fifo.rd_addr_gray[7] -.sym 9395 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] -.sym 9396 rx_fifo.rd_addr_gray[8] -.sym 9404 $PACKER_VCC_NET -.sym 9407 $PACKER_VCC_NET -.sym 9409 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 9413 i_rst_b$SB_IO_IN -.sym 9414 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9415 rx_fifo.wr_addr[9] -.sym 9418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 9420 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 9423 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 9424 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 9430 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 9431 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 9433 rx_fifo.wr_addr_gray_rd_r[8] -.sym 9434 rx_fifo.wr_addr[1] -.sym 9436 rx_fifo.rd_addr[9] -.sym 9442 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9443 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9444 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 9447 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9449 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9454 rx_fifo.wr_addr_gray_rd_r[9] -.sym 9455 rx_fifo.rd_addr[5] -.sym 9457 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 9463 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 9469 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 9471 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 9472 rx_fifo.rd_addr[5] -.sym 9476 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 9478 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9481 rx_fifo.wr_addr_gray_rd_r[9] -.sym 9482 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 9483 rx_fifo.wr_addr_gray_rd_r[8] -.sym 9484 rx_fifo.rd_addr[9] -.sym 9490 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 9495 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 9506 rx_fifo.wr_addr[1] -.sym 9509 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 9510 lvds_clock_$glb_clk -.sym 9511 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9512 rx_fifo.wr_addr_gray_rd_r[9] -.sym 9513 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 9514 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 9515 rx_fifo.wr_addr_gray_rd[9] -.sym 9516 w_smi_read_req_SB_LUT4_I1_O[3] -.sym 9517 rx_fifo.wr_addr_gray_rd[0] -.sym 9518 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 9519 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 9528 rx_fifo.rd_addr_gray_wr_r[1] -.sym 9532 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 9539 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 9541 rx_fifo.rd_addr_gray_wr_r[4] -.sym 9542 rx_fifo.rd_addr_gray[7] -.sym 9543 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9546 rx_fifo.rd_addr_gray[8] -.sym 9547 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9553 rx_fifo.wr_addr_gray[1] -.sym 9557 rx_fifo.wr_addr_gray[5] -.sym 9561 rx_fifo.wr_addr_gray_rd[4] -.sym 9563 rx_fifo.wr_addr_gray[8] -.sym 9565 rx_fifo.wr_addr_gray_rd[5] -.sym 9567 rx_fifo.wr_addr_gray_rd[8] -.sym 9592 rx_fifo.wr_addr_gray_rd[4] -.sym 9601 rx_fifo.wr_addr_gray_rd[5] -.sym 9604 rx_fifo.wr_addr_gray_rd[8] -.sym 9612 rx_fifo.wr_addr_gray[5] -.sym 9625 rx_fifo.wr_addr_gray[8] -.sym 9629 rx_fifo.wr_addr_gray[1] -.sym 9633 r_counter_$glb_clk -.sym 9636 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 9637 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 9639 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 9640 rx_fifo.rd_addr_gray[4] -.sym 9641 rx_fifo.rd_addr_gray[3] -.sym 9660 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 9661 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 9669 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9676 rx_fifo.wr_addr_gray[2] -.sym 9683 rx_fifo.wr_addr_gray[4] -.sym 9685 rx_fifo.wr_addr_gray[3] -.sym 9686 rx_fifo.wr_addr_gray_rd[2] -.sym 9687 rx_fifo.wr_addr_gray[6] -.sym 9689 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9691 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9710 rx_fifo.wr_addr_gray[4] -.sym 9723 rx_fifo.wr_addr_gray[2] -.sym 9730 rx_fifo.wr_addr_gray[6] -.sym 9733 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9735 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9739 rx_fifo.wr_addr_gray_rd[2] -.sym 9752 rx_fifo.wr_addr_gray[3] -.sym 9756 r_counter_$glb_clk -.sym 9758 rx_fifo.rd_addr_gray_wr[7] -.sym 9759 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 9760 rx_fifo.rd_addr_gray_wr_r[4] -.sym 9761 rx_fifo.rd_addr_gray_wr_r[7] -.sym 9762 rx_fifo.rd_addr_gray_wr[8] -.sym 9763 rx_fifo.rd_addr_gray_wr[4] -.sym 9764 rx_fifo.rd_addr_gray_wr[3] -.sym 9765 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 9778 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 9793 rx_fifo.wr_addr_gray_rd[3] -.sym 9801 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 9805 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9811 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9815 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9828 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9829 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9832 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 9834 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 9840 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 9845 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 9853 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 9875 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 9878 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.sym 9879 lvds_clock_$glb_clk -.sym 9880 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9881 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 9884 rx_fifo.wr_addr_gray_rd[7] -.sym 9905 i_rst_b$SB_IO_IN +.sym 9161 r_counter +.sym 9162 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 9164 w_rx_09_fifo_data[15] +.sym 9165 w_rx_09_fifo_data[12] +.sym 9166 spi_if_ins.w_rx_data[5] +.sym 9167 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 9168 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9169 tx_fifo.wr_addr[4] +.sym 9171 spi_if_ins.w_rx_data[4] +.sym 9173 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 9176 smi_ctrl_ins.frame_sr[11] +.sym 9178 smi_ctrl_ins.frame_sr[0] +.sym 9184 w_tx_fifo_pulled_data[30] +.sym 9185 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 9188 i_rst_b_SB_LUT4_I3_O +.sym 9189 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 9191 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 9193 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 9194 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9195 lvds_tx_inst.frame_boundary +.sym 9197 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 9199 lvds_tx_inst.r_fifo_data[30] +.sym 9208 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 9212 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 9213 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 9215 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 9232 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 9235 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 9236 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 9238 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 9247 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 9248 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 9249 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9250 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 9259 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 9260 w_tx_fifo_pulled_data[30] +.sym 9261 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 9262 lvds_tx_inst.r_fifo_data[30] +.sym 9263 lvds_tx_inst.frame_boundary +.sym 9264 lvds_clock_buf +.sym 9265 i_rst_b_SB_LUT4_I3_O +.sym 9267 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 9268 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 9269 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 9270 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 9271 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 9272 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 9273 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9277 tx_fifo.wr_addr[8] +.sym 9279 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 9282 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9283 $PACKER_VCC_NET +.sym 9284 w_lvds_rx_24_d0 +.sym 9285 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 9286 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 9287 $PACKER_VCC_NET +.sym 9288 w_lvds_rx_24_d1 +.sym 9290 smi_ctrl_ins.frame_sr[14] +.sym 9291 tx_wr_en +.sym 9292 tx_fifo.rd_addr_gray_wr_r[2] +.sym 9293 w_tx_fifo_pull +.sym 9294 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9295 r_counter +.sym 9296 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9297 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 9298 tx_fifo.rd_addr_gray_wr_r[8] +.sym 9300 w_lvds_tx_d1 +.sym 9301 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 9309 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 9311 i_rst_b_SB_LUT4_I3_O +.sym 9314 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9321 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9325 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 9326 w_lvds_tx_d1 +.sym 9334 tx_fifo.wr_addr[2] +.sym 9338 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9347 tx_fifo.wr_addr[2] +.sym 9360 w_lvds_tx_d1 +.sym 9364 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9376 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 9377 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9379 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9382 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 9383 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 9384 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9386 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 9387 lvds_clock_buf +.sym 9388 i_rst_b_SB_LUT4_I3_O +.sym 9389 tx_wr_data[25] +.sym 9390 tx_wr_data[12] +.sym 9391 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 9392 tx_wr_data[21] +.sym 9393 tx_wr_data[9] +.sym 9396 tx_wr_data[24] +.sym 9401 i_rst_b_SB_LUT4_I3_O +.sym 9403 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 9404 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 9405 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 9406 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9407 w_lvds_rx_24_d0 +.sym 9408 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 9409 $PACKER_VCC_NET +.sym 9410 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 9413 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 9414 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 9415 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9416 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 9417 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 9418 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9420 tx_fifo.wr_addr[2] +.sym 9421 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 9422 tx_fifo.wr_addr_gray[8] +.sym 9423 w_rx_fifo_push +.sym 9424 tx_fifo.wr_addr_gray[5] +.sym 9432 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 9435 tx_fifo.wr_addr_gray[1] +.sym 9440 tx_fifo.wr_addr_gray[0] +.sym 9441 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9442 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 9443 tx_fifo.wr_addr_gray[6] +.sym 9445 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9447 tx_fifo.wr_addr_gray_rd[0] +.sym 9450 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 9453 w_tx_fifo_pull +.sym 9454 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 9456 tx_fifo.wr_addr_gray_rd[1] +.sym 9458 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 9463 tx_fifo.wr_addr_gray[6] +.sym 9471 tx_fifo.wr_addr_gray[0] +.sym 9478 tx_fifo.wr_addr_gray[1] +.sym 9483 tx_fifo.wr_addr_gray_rd[0] +.sym 9490 tx_fifo.wr_addr_gray_rd[1] +.sym 9493 w_tx_fifo_pull +.sym 9494 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9495 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 9496 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9505 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 9506 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 9507 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 9508 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 9510 lvds_clock_buf +.sym 9513 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 9514 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 9515 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 9516 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 9517 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 9518 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9519 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 9520 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 9522 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 9524 tx_fifo.wr_addr_gray_rd[6] +.sym 9525 tx_fifo.rd_addr_gray_wr_r[4] +.sym 9527 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 9529 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 9532 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 9533 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 9534 w_rx_09_fifo_data[26] +.sym 9535 i_rst_b_SB_LUT4_I3_O +.sym 9538 tx_wr_data[21] +.sym 9539 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 9540 tx_fifo.wr_addr[6] +.sym 9541 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 9543 tx_fifo.rd_addr_gray_wr_r[1] +.sym 9546 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 9547 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9553 tx_fifo.wr_addr[0] +.sym 9556 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 9557 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 9559 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 9560 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 9561 tx_wr_en +.sym 9562 r_counter +.sym 9564 tx_fifo.rd_addr_gray_wr_r[2] +.sym 9565 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 9566 i_rst_b_SB_LUT4_I3_O +.sym 9568 w_tx_fifo_full +.sym 9569 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 9570 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9571 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9572 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 9576 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 9577 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 9578 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9580 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9583 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 9584 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 9586 tx_fifo.wr_addr[0] +.sym 9592 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 9593 tx_fifo.rd_addr_gray_wr_r[2] +.sym 9594 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 9599 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 9605 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 9610 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9611 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 9612 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9613 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 9618 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 9622 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 9623 tx_wr_en +.sym 9624 w_tx_fifo_full +.sym 9625 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9628 tx_wr_en +.sym 9629 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 9630 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 9631 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 9632 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9633 r_counter +.sym 9634 i_rst_b_SB_LUT4_I3_O +.sym 9635 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 9636 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9637 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9638 tx_fifo.wr_addr[2] +.sym 9639 tx_fifo.wr_addr[4] +.sym 9640 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 9641 tx_fifo.wr_addr[5] +.sym 9642 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 9647 tx_fifo.wr_addr[0] +.sym 9648 r_counter +.sym 9649 i_ss_SB_LUT4_I3_O +.sym 9652 lvds_rx_09_inst.r_phase_count[0] +.sym 9654 i_rst_b_SB_LUT4_I3_O +.sym 9656 r_counter +.sym 9657 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9659 spi_if_ins.w_rx_data[4] +.sym 9660 tx_fifo.wr_addr[4] +.sym 9661 tx_wr_data[14] +.sym 9662 w_ioc[1] +.sym 9663 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 9664 spi_if_ins.spi.r2_rx_done +.sym 9665 tx_fifo.wr_addr[7] +.sym 9666 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9667 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9668 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 9669 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 9670 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 9676 r_counter +.sym 9677 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 9678 w_ioc[1] +.sym 9679 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 9680 w_cs[2] +.sym 9681 w_fetch +.sym 9684 tx_fifo.wr_addr[0] +.sym 9687 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9688 w_load +.sym 9689 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 9690 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9691 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 9695 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 9696 i_rst_b_SB_LUT4_I3_O +.sym 9703 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9704 w_ioc[0] +.sym 9705 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 9709 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 9710 w_load +.sym 9711 w_cs[2] +.sym 9712 w_fetch +.sym 9715 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 9717 tx_fifo.wr_addr[0] +.sym 9728 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9733 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 9736 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9739 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 9741 w_ioc[0] +.sym 9742 w_ioc[1] +.sym 9748 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 9752 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 9753 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9755 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9756 r_counter +.sym 9757 i_rst_b_SB_LUT4_I3_O +.sym 9760 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 9761 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 9762 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 9763 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 9764 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 9765 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 9772 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 9773 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 9776 r_counter +.sym 9777 w_fetch +.sym 9778 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 9779 $PACKER_VCC_NET +.sym 9781 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9782 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9783 tx_fifo.wr_addr[8] +.sym 9784 tx_fifo.wr_addr[2] +.sym 9785 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 9786 r_counter +.sym 9787 lvds_rx_09_inst.r_phase_count[1] +.sym 9788 tx_fifo.rd_addr_gray_wr_r[2] +.sym 9789 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 9790 tx_fifo.rd_addr_gray_wr_r[8] +.sym 9791 r_counter +.sym 9793 tx_fifo.rd_addr_gray_wr_r[3] +.sym 9800 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9802 tx_fifo.wr_addr[2] +.sym 9803 i_rst_b_SB_LUT4_I3_O +.sym 9804 w_lvds_rx_09_d0 +.sym 9806 w_lvds_rx_09_d1 +.sym 9808 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9811 tx_fifo.wr_addr[4] +.sym 9812 spi_if_ins.spi.r3_rx_done +.sym 9815 r_counter +.sym 9817 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9819 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 9820 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 9824 spi_if_ins.spi.r2_rx_done +.sym 9827 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9835 tx_fifo.wr_addr[2] +.sym 9838 w_lvds_rx_09_d0 +.sym 9840 w_lvds_rx_09_d1 +.sym 9845 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 9851 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9856 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 9857 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 9863 spi_if_ins.spi.r3_rx_done +.sym 9865 spi_if_ins.spi.r2_rx_done +.sym 9869 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9876 tx_fifo.wr_addr[4] +.sym 9878 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9879 r_counter +.sym 9880 i_rst_b_SB_LUT4_I3_O +.sym 9881 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9882 w_ioc[2] +.sym 9883 w_ioc[3] +.sym 9884 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9885 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9887 w_ioc[4] +.sym 9895 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 9896 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 9899 w_load +.sym 9900 i_rst_b_SB_LUT4_I3_O +.sym 9901 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 9904 r_counter +.sym 9906 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9907 w_rx_data[0] +.sym 9908 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 9909 tx_fifo.wr_addr[8] +.sym 9915 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 9922 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 9924 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 9926 w_ioc[1] +.sym 9928 tx_fifo.rd_addr_gray_wr_r[7] +.sym 9929 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 9930 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 9931 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 9934 w_ioc[0] +.sym 9935 i_rst_b_SB_LUT4_I3_O +.sym 9936 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 9937 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 9938 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 9940 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 9941 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 9942 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9944 tx_fifo.wr_addr[2] +.sym 9947 r_counter +.sym 9949 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 9957 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 9961 w_ioc[0] +.sym 9962 w_ioc[1] +.sym 9963 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 9964 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 9967 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 9968 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 9969 tx_fifo.rd_addr_gray_wr_r[7] +.sym 9973 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 9979 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 9981 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9982 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 9986 tx_fifo.wr_addr[2] +.sym 9988 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 9993 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 9998 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 10000 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 10001 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 10002 r_counter +.sym 10003 i_rst_b_SB_LUT4_I3_O +.sym 10005 w_rx_data[2] +.sym 10007 w_rx_data[3] +.sym 10009 w_rx_data[4] +.sym 10011 w_rx_data[0] +.sym 10012 tx_wr_en +.sym 10016 w_cs[0] +.sym 10017 w_ioc[4] +.sym 10020 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 10021 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 10022 w_ioc[0] +.sym 10023 o_shdn_rx_lna$SB_IO_OUT +.sym 10024 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 10026 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 10027 w_ioc[3] +.sym 10030 tx_fifo.rd_addr_gray_wr_r[1] +.sym 10032 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 10035 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 10053 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 10057 tx_fifo.rd_addr_gray_wr[0] +.sym 10061 tx_fifo.wr_addr[0] +.sym 10067 tx_fifo.rd_addr_gray_wr[1] +.sym 10069 tx_fifo.rd_addr_gray_wr[9] +.sym 10070 r_counter +.sym 10072 tx_fifo.rd_addr_gray_wr[7] +.sym 10075 tx_fifo.rd_addr_gray_wr[8] +.sym 10076 tx_fifo.rd_addr_gray_wr[5] +.sym 10079 tx_fifo.rd_addr_gray_wr[0] +.sym 10084 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 10087 tx_fifo.wr_addr[0] +.sym 10096 tx_fifo.rd_addr_gray_wr[9] +.sym 10103 tx_fifo.rd_addr_gray_wr[8] +.sym 10109 tx_fifo.rd_addr_gray_wr[1] +.sym 10114 tx_fifo.rd_addr_gray_wr[7] +.sym 10123 tx_fifo.rd_addr_gray_wr[5] +.sym 10125 r_counter +.sym 10140 w_rx_data[0] +.sym 10141 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 10144 w_rx_data[2] +.sym 10154 tx_fifo.rd_addr_gray_wr[7] .sym 10172 o_shdn_rx_lna$SB_IO_OUT -.sym 10190 o_shdn_rx_lna$SB_IO_OUT -.sym 10197 lvds_clock -.sym 10198 o_shdn_rx_lna$SB_IO_OUT +.sym 10192 o_shdn_rx_lna$SB_IO_OUT .sym 10201 w_smi_data_output[2] .sym 10203 w_smi_data_direction .sym 10204 w_smi_data_output[1] .sym 10206 w_smi_data_direction .sym 10207 $PACKER_VCC_NET -.sym 10212 $PACKER_VCC_NET -.sym 10213 w_smi_data_direction -.sym 10215 w_smi_data_output[1] -.sym 10221 w_smi_data_direction -.sym 10225 w_smi_data_output[2] -.sym 10227 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 10228 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10229 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 10231 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 10232 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10233 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10239 w_smi_data_output[1] -.sym 10254 tx_fifo.rd_addr[4] -.sym 10255 w_smi_data_output[2] -.sym 10260 $PACKER_VCC_NET -.sym 10261 w_smi_data_direction -.sym 10279 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 10280 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 10284 tx_fifo.rd_addr[0] -.sym 10291 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10293 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 10294 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10295 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 10301 tx_fifo.rd_addr[0] -.sym 10307 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10313 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 10319 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 10327 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10328 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10332 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10338 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 10343 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10347 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 10348 lvds_clock_$glb_clk -.sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10212 w_smi_data_direction +.sym 10215 $PACKER_VCC_NET +.sym 10220 w_smi_data_direction +.sym 10222 w_smi_data_output[1] +.sym 10223 w_smi_data_output[2] +.sym 10226 smi_ctrl_ins.d_q3[5] +.sym 10227 smi_ctrl_ins.d_q2[5] +.sym 10228 smi_ctrl_ins.d_q2[3] +.sym 10229 smi_ctrl_ins.d_q1[0] +.sym 10230 smi_ctrl_ins.d_q2[7] +.sym 10231 smi_ctrl_ins.d_q1[3] +.sym 10232 smi_ctrl_ins.d_q1[5] +.sym 10233 smi_ctrl_ins.d_q3[7] +.sym 10250 spi_if_ins.w_rx_data[4] +.sym 10259 $PACKER_VCC_NET +.sym 10268 smi_ctrl_ins.d_q2[1] +.sym 10271 smi_ctrl_ins.d_q2[2] +.sym 10272 smi_ctrl_ins.d_q1[2] +.sym 10273 w_smi_data_input[4] +.sym 10277 r_counter +.sym 10280 w_smi_data_input[2] +.sym 10290 smi_ctrl_ins.d_q1[6] +.sym 10295 smi_ctrl_ins.d_q1[0] +.sym 10296 w_smi_data_input[6] +.sym 10301 smi_ctrl_ins.d_q2[1] +.sym 10307 smi_ctrl_ins.d_q2[2] +.sym 10313 smi_ctrl_ins.d_q1[6] +.sym 10320 smi_ctrl_ins.d_q1[2] +.sym 10328 w_smi_data_input[2] +.sym 10333 w_smi_data_input[4] +.sym 10340 w_smi_data_input[6] +.sym 10346 smi_ctrl_ins.d_q1[0] +.sym 10348 r_counter +.sym 10350 w_smi_data_input[0] .sym 10352 w_smi_data_input[7] -.sym 10354 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10355 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10356 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] -.sym 10357 smi_ctrl_ins.int_cnt_rx[3] -.sym 10358 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 10359 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] -.sym 10360 smi_ctrl_ins.int_cnt_rx[4] -.sym 10361 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] -.sym 10366 tx_fifo.rd_addr[0] -.sym 10370 i_rst_b_SB_LUT4_I3_O -.sym 10394 w_smi_data_output[0] -.sym 10403 tx_fifo.rd_addr[7] -.sym 10405 tx_fifo.wr_addr_gray_rd[1] -.sym 10406 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 10407 tx_fifo.rd_addr[2] -.sym 10409 $PACKER_VCC_NET -.sym 10410 w_smi_data_output[7] -.sym 10415 w_smi_data_direction -.sym 10418 tx_fifo.rd_addr[8] -.sym 10420 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 10432 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] -.sym 10433 i_rst_b_SB_LUT4_I3_O -.sym 10434 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10435 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 10437 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10438 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10441 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10442 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10450 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 10454 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] -.sym 10456 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 10457 i_rst_b$SB_IO_IN -.sym 10458 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10459 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 10460 w_tx_fifo_pull -.sym 10464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 10465 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] -.sym 10466 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 10467 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10471 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10472 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10473 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10478 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 10479 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 10483 w_tx_fifo_pull -.sym 10484 i_rst_b$SB_IO_IN -.sym 10488 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10490 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 10496 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 10501 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 10502 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 10503 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] -.sym 10507 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10508 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 10509 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10510 i_rst_b_SB_LUT4_I3_O -.sym 10511 lvds_clock_$glb_clk -.sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10513 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 10514 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 10515 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 10516 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 10517 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 10518 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 10519 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] -.sym 10520 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 10526 smi_ctrl_ins.int_cnt_rx[4] -.sym 10528 smi_ctrl_ins.int_cnt_rx[3] -.sym 10529 tx_fifo.rd_addr[6] -.sym 10539 smi_ctrl_ins.int_cnt_rx[3] -.sym 10542 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 10544 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10545 smi_ctrl_ins.int_cnt_rx[4] -.sym 10548 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10554 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] -.sym 10555 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10556 tx_fifo.rd_addr[3] -.sym 10557 smi_ctrl_ins.int_cnt_rx[3] -.sym 10559 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] -.sym 10560 smi_ctrl_ins.int_cnt_rx[4] -.sym 10561 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] -.sym 10562 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 10564 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 10565 smi_ctrl_ins.int_cnt_rx[3] -.sym 10567 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] -.sym 10568 tx_fifo.rd_addr[7] -.sym 10569 tx_fifo.rd_addr[7] -.sym 10571 tx_fifo.wr_addr_gray_rd[1] -.sym 10572 tx_fifo.rd_addr[4] -.sym 10573 tx_fifo.rd_addr[2] -.sym 10575 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] -.sym 10577 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] -.sym 10578 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] -.sym 10579 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 10580 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 10582 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10583 tx_fifo.rd_addr[6] -.sym 10584 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10585 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 10587 tx_fifo.rd_addr[3] -.sym 10588 tx_fifo.rd_addr[2] -.sym 10590 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10593 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] -.sym 10594 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] -.sym 10595 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] -.sym 10596 tx_fifo.rd_addr[4] -.sym 10599 smi_ctrl_ins.int_cnt_rx[4] -.sym 10600 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 10601 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 10602 smi_ctrl_ins.int_cnt_rx[3] -.sym 10605 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] -.sym 10606 tx_fifo.rd_addr[7] -.sym 10607 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] -.sym 10608 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] -.sym 10611 smi_ctrl_ins.int_cnt_rx[4] -.sym 10612 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10613 smi_ctrl_ins.int_cnt_rx[3] -.sym 10614 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 10617 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] -.sym 10618 tx_fifo.rd_addr[6] -.sym 10619 tx_fifo.rd_addr[7] -.sym 10620 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 10623 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 10624 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 10626 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 10629 tx_fifo.wr_addr_gray_rd[1] -.sym 10634 lvds_clock_$glb_clk -.sym 10636 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] -.sym 10638 tx_fifo.rd_addr_gray[8] -.sym 10640 tx_fifo.rd_addr[8] -.sym 10641 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] -.sym 10642 tx_fifo.rd_addr_gray[4] -.sym 10643 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] -.sym 10647 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 10648 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 10649 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 10651 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 10652 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] -.sym 10653 rx_fifo.wr_addr[3] -.sym 10654 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 10659 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 10661 w_smi_read_req -.sym 10662 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 10665 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 10666 w_smi_data_output[0] -.sym 10669 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 10670 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10671 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 10679 i_rst_b$SB_IO_IN -.sym 10681 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 10683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 10684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 10685 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10686 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 10688 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 10689 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10691 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 10692 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 10699 smi_ctrl_ins.int_cnt_rx[3] -.sym 10700 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 10705 smi_ctrl_ins.int_cnt_rx[4] -.sym 10706 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 10707 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 10710 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 10712 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 10716 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 10718 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 10724 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 10725 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 10729 smi_ctrl_ins.int_cnt_rx[3] -.sym 10730 smi_ctrl_ins.int_cnt_rx[4] -.sym 10734 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 10735 smi_ctrl_ins.int_cnt_rx[4] +.sym 10355 smi_ctrl_ins.r_fifo_pull_1 +.sym 10356 smi_ctrl_ins.byte_ix[0] +.sym 10357 w_smi_read_req +.sym 10358 smi_ctrl_ins.byte_ix[3] +.sym 10359 smi_ctrl_ins.r_fifo_pull +.sym 10360 smi_ctrl_ins.byte_ix[1] +.sym 10361 smi_ctrl_ins.byte_ix[2] +.sym 10364 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 10366 rx_fifo.wr_addr[4] +.sym 10367 lvds_tx_inst.r_sync_count[0] +.sym 10368 lvds_tx_inst.r_sync_count[1] +.sym 10372 rx_fifo.wr_addr[9] +.sym 10373 w_smi_data_input[4] +.sym 10374 w_rx_fifo_data[0] +.sym 10377 i_rst_b_SB_LUT4_I3_O +.sym 10391 smi_ctrl_ins.d_q2[3] +.sym 10407 smi_ctrl_ins.d_q3[2] +.sym 10411 w_rx_09_fifo_data[22] +.sym 10415 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 10419 smi_ctrl_ins.d_q3[7] +.sym 10431 r_counter +.sym 10433 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] +.sym 10436 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 10437 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 10440 w_smi_data_input[1] +.sym 10441 smi_ctrl_ins.d_q2[6] +.sym 10443 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 10444 smi_ctrl_ins.d_q1[4] +.sym 10446 smi_ctrl_ins.d_q2[0] +.sym 10448 smi_ctrl_ins.d_q2[3] +.sym 10453 smi_ctrl_ins.d_q1[1] +.sym 10462 smi_ctrl_ins.d_q2[4] +.sym 10464 smi_ctrl_ins.d_q1[1] +.sym 10470 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 10471 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 10472 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 10473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] +.sym 10476 smi_ctrl_ins.d_q2[0] +.sym 10483 smi_ctrl_ins.d_q2[4] +.sym 10491 smi_ctrl_ins.d_q2[6] +.sym 10494 smi_ctrl_ins.d_q2[3] +.sym 10502 w_smi_data_input[1] +.sym 10507 smi_ctrl_ins.d_q1[4] +.sym 10511 r_counter +.sym 10513 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[0] +.sym 10514 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 10515 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[1] +.sym 10516 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 10517 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[0] +.sym 10518 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[1] +.sym 10519 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 10520 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10521 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 10527 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] +.sym 10528 w_smi_read_req +.sym 10529 w_smi_data_direction +.sym 10530 smi_ctrl_ins.byte_ix[2] +.sym 10532 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 10533 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 10534 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10536 smi_ctrl_ins.byte_ix[0] +.sym 10537 smi_ctrl_ins.byte_ix[0] +.sym 10538 w_rx_fifo_pulled_data[8] +.sym 10540 lvds_tx_inst.frame_boundary +.sym 10542 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 10543 smi_ctrl_ins.d_byte[2] +.sym 10544 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 10545 rx_fifo.wr_addr[0] +.sym 10547 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] +.sym 10559 smi_ctrl_ins.d_q3[3] +.sym 10560 smi_ctrl_ins.byte_ix[1] +.sym 10561 smi_ctrl_ins.byte_ix[2] +.sym 10563 r_counter +.sym 10564 smi_ctrl_ins.byte_ix[0] +.sym 10565 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10566 smi_ctrl_ins.d_q3[6] +.sym 10569 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 10570 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 10573 smi_ctrl_ins.d_q3[2] +.sym 10575 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[0] +.sym 10584 smi_ctrl_ins.d_q3[7] +.sym 10585 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10590 smi_ctrl_ins.d_q3[7] +.sym 10595 smi_ctrl_ins.d_q3[3] +.sym 10599 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 10600 smi_ctrl_ins.byte_ix[0] +.sym 10601 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10602 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[0] +.sym 10606 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 10612 smi_ctrl_ins.d_q3[6] +.sym 10618 smi_ctrl_ins.byte_ix[1] +.sym 10619 smi_ctrl_ins.byte_ix[2] +.sym 10623 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10625 smi_ctrl_ins.byte_ix[1] +.sym 10631 smi_ctrl_ins.d_q3[2] +.sym 10633 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10634 r_counter +.sym 10636 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.sym 10637 w_smi_data_output[4] +.sym 10638 w_smi_data_output[1] +.sym 10639 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 10640 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10641 smi_ctrl_ins.int_cnt_rx[3] +.sym 10642 w_smi_data_output[6] +.sym 10643 smi_ctrl_ins.int_cnt_rx[4] +.sym 10646 spi_if_ins.w_rx_data[2] +.sym 10647 tx_wr_data[29] +.sym 10648 w_smi_data_output[2] +.sym 10650 rx_fifo.wr_addr[0] +.sym 10651 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 10653 w_rx_24_fifo_data[8] +.sym 10654 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 10655 w_rx_24_fifo_data[24] +.sym 10656 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 10658 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 10659 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 10661 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10662 w_rx_fifo_data[9] +.sym 10665 channel +.sym 10666 w_rx_24_fifo_data[4] +.sym 10668 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 10669 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.sym 10670 w_tx_fsm_state[0] +.sym 10671 w_rx_data[0] +.sym 10678 smi_ctrl_ins.d_byte[3] +.sym 10679 w_rx_24_fifo_data[22] +.sym 10681 channel +.sym 10684 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10685 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 10686 r_counter +.sym 10687 w_rx_09_fifo_data[22] +.sym 10688 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 10689 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 10690 i_rst_b_SB_LUT4_I3_O +.sym 10691 w_rx_24_fifo_data[20] +.sym 10692 smi_ctrl_ins.d_byte[4] +.sym 10697 smi_ctrl_ins.byte_ix[0] +.sym 10699 smi_ctrl_ins.d_byte[0] +.sym 10700 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10702 w_rx_09_fifo_data[20] +.sym 10706 smi_ctrl_ins.int_cnt_rx[3] +.sym 10708 smi_ctrl_ins.int_cnt_rx[4] +.sym 10710 channel +.sym 10711 w_rx_09_fifo_data[22] +.sym 10712 w_rx_24_fifo_data[22] +.sym 10719 smi_ctrl_ins.d_byte[4] +.sym 10722 w_rx_09_fifo_data[20] +.sym 10723 w_rx_24_fifo_data[20] +.sym 10724 channel +.sym 10730 smi_ctrl_ins.d_byte[3] +.sym 10734 smi_ctrl_ins.int_cnt_rx[4] +.sym 10735 smi_ctrl_ins.r_fifo_pulled_data[28] .sym 10736 smi_ctrl_ins.int_cnt_rx[3] -.sym 10737 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10740 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 10741 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 10746 smi_ctrl_ins.int_cnt_rx[3] -.sym 10747 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 10748 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 10749 smi_ctrl_ins.int_cnt_rx[4] -.sym 10756 i_rst_b$SB_IO_IN -.sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 10759 tx_fifo.wr_addr_gray_rd[6] -.sym 10760 tx_fifo.wr_addr_gray_rd[8] -.sym 10761 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 10762 tx_fifo.wr_addr_gray_rd_r[2] -.sym 10763 tx_fifo.wr_addr_gray_rd[4] -.sym 10764 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 10765 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 10766 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 10770 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 10771 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 10772 tx_fifo.rd_addr_gray[4] -.sym 10775 rx_fifo.rd_addr[0] -.sym 10779 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 10780 rx_fifo.mem_q.0.3_WDATA_1 -.sym 10783 tx_fifo.wr_addr_gray_rd[1] -.sym 10790 w_smi_data_output[5] -.sym 10803 smi_ctrl_ins.w_fifo_pull_trigger -.sym 10811 smi_ctrl_ins.int_cnt_rx[3] -.sym 10814 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 10815 smi_ctrl_ins.r_fifo_pull_1 -.sym 10816 smi_ctrl_ins.r_fifo_pull -.sym 10817 smi_ctrl_ins.int_cnt_rx[4] -.sym 10821 w_smi_read_req -.sym 10829 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 10834 smi_ctrl_ins.w_fifo_pull_trigger -.sym 10851 w_smi_read_req -.sym 10852 smi_ctrl_ins.r_fifo_pull_1 -.sym 10854 smi_ctrl_ins.r_fifo_pull -.sym 10869 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 10870 smi_ctrl_ins.int_cnt_rx[4] -.sym 10871 smi_ctrl_ins.int_cnt_rx[3] -.sym 10872 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 10878 smi_ctrl_ins.r_fifo_pull -.sym 10880 r_counter_$glb_clk -.sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10884 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 10886 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 10888 tx_fifo.wr_addr_gray_rd[1] -.sym 10894 rx_fifo.wr_addr[0] -.sym 10895 rx_fifo.wr_addr[3] -.sym 10897 rx_fifo.wr_addr[9] -.sym 10904 rx_fifo.wr_addr[5] -.sym 10906 rx_fifo.rd_addr[1] -.sym 10907 $PACKER_VCC_NET -.sym 10909 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 10910 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 10911 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 10912 w_smi_data_direction -.sym 10916 rx_fifo.rd_addr[2] -.sym 10926 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 10927 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 10928 smi_ctrl_ins.int_cnt_rx[3] -.sym 10933 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 10934 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 10935 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 10938 smi_ctrl_ins.int_cnt_rx[4] -.sym 10941 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 10942 i_rst_b$SB_IO_IN -.sym 10945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 10947 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 10950 i_rst_b$SB_IO_IN -.sym 10951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 10956 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 10957 smi_ctrl_ins.int_cnt_rx[3] -.sym 10958 smi_ctrl_ins.int_cnt_rx[4] -.sym 10959 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 10962 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 10965 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 10968 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 10969 i_rst_b$SB_IO_IN -.sym 10974 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 10976 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 10992 smi_ctrl_ins.int_cnt_rx[4] -.sym 10993 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 10994 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 10995 smi_ctrl_ins.int_cnt_rx[3] -.sym 11002 i_rst_b$SB_IO_IN -.sym 11003 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 11005 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11006 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11008 rx_fifo.rd_addr[2] -.sym 11009 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11010 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11011 rx_fifo.rd_addr[1] -.sym 11018 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 11030 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 11032 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11035 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11038 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11039 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11040 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11062 rx_fifo.rd_addr[0] -.sym 11063 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11066 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11068 rx_fifo.rd_addr[1] -.sym 11070 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11073 rx_fifo.rd_addr[2] -.sym 11074 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 11075 rx_fifo.rd_addr[5] -.sym 11078 $nextpnr_ICESTORM_LC_3$O -.sym 11081 rx_fifo.rd_addr[0] -.sym 11084 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 11086 rx_fifo.rd_addr[1] -.sym 11088 rx_fifo.rd_addr[0] -.sym 11090 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 11093 rx_fifo.rd_addr[2] -.sym 11094 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 11096 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 -.sym 11099 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11100 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 11102 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 11105 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11106 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 -.sym 11108 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11110 rx_fifo.rd_addr[5] -.sym 11112 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 11114 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11116 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 11118 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11120 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11123 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11124 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11129 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11130 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 11131 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11132 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 11133 spi_if_ins.r_tx_data_valid -.sym 11134 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 11135 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11143 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 11149 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11152 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 11153 w_smi_read_req -.sym 11154 rx_fifo.rd_addr[2] -.sym 11156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 11158 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 11159 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11160 rx_fifo.rd_addr[1] -.sym 11164 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11170 rx_fifo.wr_addr_gray_rd_r[5] -.sym 11171 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 11172 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11173 w_rx_data[0] -.sym 11174 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 11175 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11176 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11177 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11179 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 11180 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 11181 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11182 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11185 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11187 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] -.sym 11190 rx_fifo.rd_addr[9] -.sym 11198 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 11201 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11204 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11210 rx_fifo.rd_addr[9] -.sym 11211 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 11214 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11217 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11223 w_rx_data[0] -.sym 11227 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 11228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 11229 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 11233 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11238 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 11239 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11240 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] -.sym 11241 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11244 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 11245 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11246 rx_fifo.wr_addr_gray_rd_r[5] -.sym 11248 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 11249 r_counter_$glb_clk -.sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11251 spi_if_ins.state_if[0] -.sym 11252 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 11253 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 11254 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 11255 spi_if_ins.state_if[1] -.sym 11256 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 11257 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 11258 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 11263 spi_if_ins.spi.r_tx_bit_count[0] -.sym 11264 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 11265 $PACKER_VCC_NET -.sym 11267 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11269 w_rx_data[0] -.sym 11271 w_smi_data_direction -.sym 11272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11274 rx_fifo.rd_addr[0] -.sym 11276 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11277 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11279 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 11282 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 11284 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 11286 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 11292 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 11293 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] -.sym 11294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11295 i_sck$SB_IO_IN -.sym 11296 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 11299 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 11303 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 11305 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 11308 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11315 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 11318 spi_if_ins.spi.SCKr[0] -.sym 11320 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 11322 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11323 rx_fifo.wr_addr_gray_rd[3] -.sym 11325 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 11326 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 11331 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] -.sym 11332 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 11333 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 11334 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 11340 i_sck$SB_IO_IN -.sym 11346 rx_fifo.wr_addr_gray_rd[3] -.sym 11351 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 11357 spi_if_ins.spi.SCKr[0] -.sym 11361 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11362 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 11364 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 11370 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 11372 r_counter_$glb_clk -.sym 11374 w_smi_read_req -.sym 11375 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 11376 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 11377 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 11378 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11379 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 11380 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 11381 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 11386 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 11390 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 11396 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 11398 rx_fifo.wr_addr_gray_rd_r[9] -.sym 11406 rx_fifo.rd_addr[1] -.sym 11407 w_smi_read_req -.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 11417 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11419 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11420 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] -.sym 11421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 11423 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 11424 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] -.sym 11425 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 11426 rx_fifo.rd_addr[2] -.sym 11427 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 11428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 11430 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 11432 rx_fifo.rd_addr[1] -.sym 11434 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 11436 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 11437 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11438 rx_fifo.wr_addr_gray_rd_r[8] -.sym 11439 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 11440 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 11442 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 11443 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 11444 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 11445 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 11446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 11448 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11449 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 11450 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] -.sym 11451 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 11454 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 11457 rx_fifo.rd_addr[2] -.sym 11460 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 11461 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] -.sym 11462 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 11463 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 11466 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 11467 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 11468 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 11469 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 11473 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 11474 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 11475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 11478 rx_fifo.rd_addr[1] -.sym 11479 rx_fifo.rd_addr[2] -.sym 11480 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 11484 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11486 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11487 rx_fifo.wr_addr_gray_rd_r[8] -.sym 11490 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 11491 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 11492 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 11493 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 11495 lvds_clock_$glb_clk -.sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11497 rx_fifo.rd_addr_gray_wr[2] -.sym 11498 rx_fifo.rd_addr_gray_wr[6] -.sym 11501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 11502 rx_fifo.rd_addr_gray_wr_r[1] -.sym 11504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 11514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 11515 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 11522 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 11523 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 11524 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11526 w_rx_fifo_full -.sym 11528 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11531 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11532 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11538 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 11539 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 11541 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 11543 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11544 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 11545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11548 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 11550 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11551 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 11552 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 11553 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11558 rx_fifo.wr_addr_gray_rd_r[9] -.sym 11560 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] -.sym 11565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 11566 rx_fifo.rd_addr[1] -.sym 11568 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] -.sym 11571 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 11572 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] -.sym 11573 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] -.sym 11574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 11577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 11578 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 11579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 11584 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 11589 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 11595 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 11601 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 11607 rx_fifo.wr_addr_gray_rd_r[9] -.sym 11608 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 11609 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11610 rx_fifo.rd_addr[1] -.sym 11613 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 11616 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 11618 r_counter_$glb_clk -.sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11620 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 11622 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 11624 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 11626 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] -.sym 11628 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 11637 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 11645 rx_fifo.rd_addr_gray[1] -.sym 11651 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11653 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 11654 rx_fifo.rd_addr_gray_wr[1] -.sym 11655 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11664 rx_fifo.wr_addr_gray_rd[9] -.sym 11666 rx_fifo.wr_addr_gray_rd[0] -.sym 11668 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 11670 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 11673 w_smi_read_req_SB_LUT4_I1_O[3] -.sym 11676 rx_fifo.wr_addr_gray_rd[1] -.sym 11677 w_smi_read_req -.sym 11678 w_smi_read_req_SB_LUT4_I1_I3[3] -.sym 11680 rx_fifo.wr_addr_gray_rd[6] -.sym 11682 rx_fifo.wr_addr[9] -.sym 11684 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11688 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11690 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 11692 rx_fifo.wr_addr_gray[0] -.sym 11697 rx_fifo.wr_addr_gray_rd[9] -.sym 11702 rx_fifo.wr_addr_gray_rd[0] -.sym 11707 rx_fifo.wr_addr_gray_rd[6] -.sym 11712 rx_fifo.wr_addr[9] -.sym 11718 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 11719 w_smi_read_req_SB_LUT4_I1_I3[3] -.sym 11720 w_smi_read_req -.sym 11721 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 11727 rx_fifo.wr_addr_gray[0] -.sym 11732 rx_fifo.wr_addr_gray_rd[1] -.sym 11736 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 11737 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 11738 w_smi_read_req_SB_LUT4_I1_O[3] -.sym 11739 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 11741 r_counter_$glb_clk -.sym 11746 rx_fifo.rd_addr_gray_wr[1] -.sym 11756 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 11761 w_rx_data[0] -.sym 11774 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 11786 rx_fifo.rd_addr_gray_wr_r[4] -.sym 11787 rx_fifo.rd_addr_gray_wr_r[7] -.sym 11788 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11791 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 11792 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 11795 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 11799 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 11803 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11804 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 11809 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 11811 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11823 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 11826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11829 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 11830 rx_fifo.rd_addr_gray_wr_r[7] -.sym 11831 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 11832 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 11841 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 11843 rx_fifo.rd_addr_gray_wr_r[4] -.sym 11849 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 11855 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 11863 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 11864 r_counter_$glb_clk -.sym 11865 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11867 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 11871 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 11884 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 11912 rx_fifo.rd_addr_gray_wr[4] -.sym 11915 rx_fifo.rd_addr_gray_wr[7] -.sym 11918 rx_fifo.rd_addr_gray[8] -.sym 11920 rx_fifo.rd_addr_gray[4] -.sym 11921 rx_fifo.rd_addr_gray[3] -.sym 11922 rx_fifo.rd_addr_gray[7] -.sym 11929 rx_fifo.rd_addr_gray_wr[3] -.sym 11935 rx_fifo.rd_addr_gray_wr[8] -.sym 11940 rx_fifo.rd_addr_gray[7] -.sym 11946 rx_fifo.rd_addr_gray_wr[8] -.sym 11955 rx_fifo.rd_addr_gray_wr[4] -.sym 11960 rx_fifo.rd_addr_gray_wr[7] -.sym 11966 rx_fifo.rd_addr_gray[8] -.sym 11971 rx_fifo.rd_addr_gray[4] -.sym 11977 rx_fifo.rd_addr_gray[3] -.sym 11983 rx_fifo.rd_addr_gray_wr[3] -.sym 11987 lvds_clock_$glb_clk -.sym 11993 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 12010 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 12048 rx_fifo.wr_addr_gray[7] -.sym 12049 rx_fifo.wr_addr_gray_rd[7] -.sym 12066 rx_fifo.wr_addr_gray_rd[7] -.sym 12084 rx_fifo.wr_addr_gray[7] -.sym 12110 r_counter_$glb_clk -.sym 12113 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 12305 i_rst_b$SB_IO_IN -.sym 12309 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 10737 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 10741 smi_ctrl_ins.d_byte[0] +.sym 10747 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 10752 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 10755 smi_ctrl_ins.byte_ix[0] +.sym 10756 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 10757 r_counter +.sym 10758 i_rst_b_SB_LUT4_I3_O +.sym 10759 smi_ctrl_ins.frame_sr[2] +.sym 10760 w_rx_fifo_data[1] +.sym 10761 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[3] +.sym 10762 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[3] +.sym 10763 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 10764 smi_ctrl_ins.frame_sr[1] +.sym 10765 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 10766 w_rx_fifo_data[9] +.sym 10769 tx_wr_data[14] +.sym 10771 w_rx_24_fifo_data[26] +.sym 10772 w_smi_data_output[6] +.sym 10773 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 10774 r_counter +.sym 10775 w_rx_24_fifo_data[22] +.sym 10776 smi_ctrl_ins.int_cnt_rx[4] +.sym 10777 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 10779 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 10780 w_smi_data_output[4] +.sym 10782 w_smi_data_output[1] +.sym 10784 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 10785 smi_ctrl_ins.frame_sr[20] +.sym 10786 w_rx_09_fifo_data[25] +.sym 10787 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10789 smi_ctrl_ins.int_cnt_rx[3] +.sym 10790 smi_ctrl_ins.frame_sr[17] +.sym 10791 tx_wr_data[13] +.sym 10792 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 10793 tx_wr_data[28] +.sym 10794 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 10800 r_counter +.sym 10801 smi_ctrl_ins.frame_sr[4] +.sym 10802 w_tx_fsm_state[1] +.sym 10803 smi_ctrl_ins.frame_sr[3] +.sym 10806 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 10809 smi_ctrl_ins.frame_sr[21] +.sym 10811 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 10812 $PACKER_VCC_NET +.sym 10813 i_rst_b_SB_LUT4_I3_O +.sym 10815 smi_ctrl_ins.d_byte[2] +.sym 10821 smi_ctrl_ins.frame_sr[1] +.sym 10824 smi_ctrl_ins.frame_sr[2] +.sym 10830 w_tx_fsm_state[0] +.sym 10833 smi_ctrl_ins.frame_sr[21] +.sym 10841 smi_ctrl_ins.frame_sr[3] +.sym 10846 smi_ctrl_ins.frame_sr[4] +.sym 10853 $PACKER_VCC_NET +.sym 10860 smi_ctrl_ins.frame_sr[1] +.sym 10864 w_tx_fsm_state[1] +.sym 10865 w_tx_fsm_state[0] +.sym 10866 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 10871 smi_ctrl_ins.d_byte[2] +.sym 10875 smi_ctrl_ins.frame_sr[2] +.sym 10879 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 10880 r_counter +.sym 10881 i_rst_b_SB_LUT4_I3_O +.sym 10882 w_rx_fifo_data[3] +.sym 10883 lvds_tx_inst.r_state_SB_DFFER_Q_E +.sym 10885 w_rx_fifo_data[25] +.sym 10886 w_tx_fifo_full +.sym 10887 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] +.sym 10888 w_rx_fifo_data[13] +.sym 10889 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[1] +.sym 10894 i_rst_b_SB_LUT4_I3_O +.sym 10895 i_sck$SB_IO_IN +.sym 10896 w_rx_fifo_push +.sym 10897 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 10899 i_button_SB_LUT4_I2_I1[2] +.sym 10900 w_rx_09_fifo_data[1] +.sym 10901 i_rst_b_SB_LUT4_I3_O +.sym 10902 tx_wr_data[14] +.sym 10903 smi_ctrl_ins.d_byte[1] +.sym 10904 io_ctrl_ins.rf_pin_state[0] +.sym 10905 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 10906 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 10907 w_rx_09_fifo_data[6] +.sym 10908 spi_if_ins.w_rx_data[1] +.sym 10909 w_rx_09_fifo_data[22] +.sym 10910 w_rx_24_fifo_data[29] +.sym 10911 tx_wr_data[26] +.sym 10913 w_rx_24_fifo_data[1] +.sym 10914 w_rx_09_fifo_data[19] +.sym 10916 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 10917 tx_wr_data[27] +.sym 10925 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 10926 w_rx_24_fifo_data[23] +.sym 10928 w_rx_24_fifo_data[19] +.sym 10934 w_rx_24_fifo_data[27] +.sym 10938 w_rx_24_fifo_data[26] +.sym 10939 w_rx_24_fifo_data[9] +.sym 10940 w_rx_24_fifo_data[1] +.sym 10944 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10946 w_rx_24_fifo_data[0] +.sym 10952 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 10954 w_rx_24_fifo_data[2] +.sym 10956 w_rx_24_fifo_data[9] +.sym 10959 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10962 w_rx_24_fifo_data[23] +.sym 10964 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10968 w_rx_24_fifo_data[26] +.sym 10969 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10976 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10977 w_rx_24_fifo_data[2] +.sym 10981 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10983 w_rx_24_fifo_data[19] +.sym 10986 w_rx_24_fifo_data[1] +.sym 10988 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10994 w_rx_24_fifo_data[27] +.sym 10995 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 10998 w_rx_24_fifo_data[0] +.sym 11000 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11002 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 11003 lvds_clock_buf +.sym 11004 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 11005 w_rx_09_fifo_data[16] +.sym 11006 w_rx_09_fifo_data[25] +.sym 11007 w_rx_09_fifo_data[19] +.sym 11008 w_rx_09_fifo_data[29] +.sym 11009 w_rx_09_fifo_data[27] +.sym 11010 w_rx_09_fifo_data[2] +.sym 11011 w_rx_09_fifo_data[14] +.sym 11012 w_rx_09_fifo_data[18] +.sym 11013 w_rx_24_fifo_data[21] +.sym 11018 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 11019 w_tx_fsm_state[1] +.sym 11020 w_rx_fifo_data[25] +.sym 11021 w_tx_fsm_state[1] +.sym 11022 i_mosi$SB_IO_IN +.sym 11023 w_rx_24_fifo_data[28] +.sym 11026 lvds_tx_inst.r_state_SB_DFFER_Q_E +.sym 11027 w_rx_24_fifo_data[21] +.sym 11028 io_pmod_in[3]$SB_IO_IN +.sym 11029 w_rx_09_fifo_data[10] +.sym 11031 w_tx_fifo_pulled_data[14] +.sym 11032 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 11033 w_tx_fifo_full +.sym 11036 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 11038 lvds_tx_inst.frame_boundary +.sym 11039 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 11049 w_rx_09_fifo_data[15] +.sym 11051 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11052 w_rx_09_fifo_data[21] +.sym 11055 w_rx_09_fifo_data[1] +.sym 11059 w_rx_09_fifo_data[9] +.sym 11064 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 11065 w_rx_09_fifo_data[11] +.sym 11066 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 11071 w_rx_09_fifo_data[4] +.sym 11077 w_rx_09_fifo_data[18] +.sym 11079 w_rx_09_fifo_data[1] +.sym 11080 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11085 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11087 w_rx_09_fifo_data[15] +.sym 11091 w_rx_09_fifo_data[18] +.sym 11094 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11097 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11100 w_rx_09_fifo_data[9] +.sym 11104 w_rx_09_fifo_data[11] +.sym 11106 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11115 w_rx_09_fifo_data[4] +.sym 11116 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11123 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11124 w_rx_09_fifo_data[21] +.sym 11125 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 11126 lvds_clock_buf +.sym 11127 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 11128 w_rx_09_fifo_data[12] +.sym 11129 w_rx_09_fifo_data[22] +.sym 11130 w_rx_09_fifo_data[31] +.sym 11131 w_rx_09_fifo_data[5] +.sym 11132 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 11133 w_rx_09_fifo_data[24] +.sym 11134 w_rx_09_fifo_data[7] +.sym 11135 w_rx_09_fifo_data[13] +.sym 11138 spi_if_ins.w_rx_data[0] +.sym 11140 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11142 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 11143 w_rx_09_fifo_data[29] +.sym 11145 w_rx_24_fifo_data[16] +.sym 11146 lvds_tx_inst.r_tx_state_q +.sym 11147 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11148 w_rx_24_fifo_data[23] +.sym 11149 w_tx_data_smi[4] +.sym 11150 w_rx_24_fifo_data[19] +.sym 11151 w_tx_data_smi[2] +.sym 11154 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 11155 w_rx_09_fifo_data[24] +.sym 11158 w_rx_24_fifo_data[4] +.sym 11160 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 11161 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 11162 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.sym 11163 w_rx_data[0] +.sym 11170 spi_if_ins.spi.r_rx_byte[4] +.sym 11174 spi_if_ins.spi.r_rx_byte[2] +.sym 11176 spi_if_ins.spi.r_rx_byte[0] +.sym 11177 spi_if_ins.spi.r_rx_byte[5] +.sym 11178 r_counter +.sym 11180 spi_if_ins.spi.r_rx_byte[6] +.sym 11181 spi_if_ins.spi.r_rx_byte[1] +.sym 11183 spi_if_ins.spi.r_rx_byte[7] +.sym 11196 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 11202 spi_if_ins.spi.r_rx_byte[6] +.sym 11208 spi_if_ins.spi.r_rx_byte[1] +.sym 11215 spi_if_ins.spi.r_rx_byte[5] +.sym 11222 spi_if_ins.spi.r_rx_byte[0] +.sym 11227 spi_if_ins.spi.r_rx_byte[4] +.sym 11232 spi_if_ins.spi.r_rx_byte[7] +.sym 11244 spi_if_ins.spi.r_rx_byte[2] +.sym 11248 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 11249 r_counter +.sym 11251 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 11252 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 11253 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 11254 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 11256 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 11257 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 11258 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 11263 spi_if_ins.w_rx_data[6] +.sym 11264 w_rx_09_fifo_data[7] +.sym 11265 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11266 w_rx_09_fifo_data[5] +.sym 11267 spi_if_ins.w_rx_data[1] +.sym 11269 lvds_tx_inst.fifo_empty_d2 +.sym 11270 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 11271 w_rx_09_fifo_data[21] +.sym 11273 w_rx_09_fifo_data[9] +.sym 11274 tx_fifo.rd_addr_gray_wr_r[8] +.sym 11275 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.sym 11276 tx_wr_data[13] +.sym 11278 spi_if_ins.w_rx_data[0] +.sym 11279 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 11281 w_rx_09_fifo_data[24] +.sym 11282 smi_ctrl_ins.frame_sr[20] +.sym 11283 smi_ctrl_ins.frame_sr[17] +.sym 11284 tx_fifo.wr_addr[5] +.sym 11285 tx_wr_data[28] +.sym 11301 i_sck$SB_IO_IN +.sym 11306 i_mosi$SB_IO_IN +.sym 11308 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 11310 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 11311 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 11313 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 11317 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 11319 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 11320 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 11321 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 11328 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 11332 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 11338 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 11346 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 11352 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 11356 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 11361 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 11367 i_mosi$SB_IO_IN +.sym 11371 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 11372 i_sck$SB_IO_IN +.sym 11374 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 11375 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 11376 spi_if_ins.w_rx_data[3] +.sym 11377 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 11378 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 11380 w_rx_fifo_data[4] +.sym 11381 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 11386 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11387 w_rx_24_fifo_push +.sym 11388 w_rx_09_fifo_data[6] +.sym 11390 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 11391 lvds_rx_24_inst.r_sync_input +.sym 11392 i_sck$SB_IO_IN +.sym 11397 i_rst_b_SB_LUT4_I3_O +.sym 11398 $PACKER_VCC_NET +.sym 11399 tx_fifo.rd_addr_gray_wr_r[6] +.sym 11400 spi_if_ins.w_rx_data[1] +.sym 11403 tx_wr_data[25] +.sym 11404 $PACKER_VCC_NET +.sym 11406 i_sck$SB_IO_IN +.sym 11407 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 11409 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 11415 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 11416 w_lvds_rx_24_d0 +.sym 11417 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 11418 $PACKER_VCC_NET +.sym 11419 lvds_rx_24_inst.r_phase_count[0] +.sym 11424 $PACKER_VCC_NET +.sym 11425 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.sym 11427 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 11428 i_rst_b_SB_LUT4_I3_O +.sym 11430 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 11432 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 11433 lvds_rx_24_inst.r_phase_count[1] +.sym 11434 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.sym 11435 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.sym 11436 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11437 w_rx_fifo_push +.sym 11439 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 11440 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 11441 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 11442 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 11443 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11444 tx_fifo.rd_addr_gray_wr_r[3] +.sym 11446 w_lvds_rx_24_d1 +.sym 11447 $nextpnr_ICESTORM_LC_7$O +.sym 11450 lvds_rx_24_inst.r_phase_count[0] +.sym 11453 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 11455 lvds_rx_24_inst.r_phase_count[1] +.sym 11456 $PACKER_VCC_NET +.sym 11457 lvds_rx_24_inst.r_phase_count[0] +.sym 11460 $PACKER_VCC_NET +.sym 11461 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 11463 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 11466 w_lvds_rx_24_d0 +.sym 11469 w_lvds_rx_24_d1 +.sym 11472 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 11473 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 11474 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 11475 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11478 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 11479 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 11480 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 11481 tx_fifo.rd_addr_gray_wr_r[3] +.sym 11484 w_rx_fifo_push +.sym 11485 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.sym 11486 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.sym 11487 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.sym 11490 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 11491 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 11492 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11493 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 11494 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 11495 lvds_clock_buf +.sym 11496 i_rst_b_SB_LUT4_I3_O +.sym 11497 w_rx_09_fifo_data[26] +.sym 11498 w_rx_09_fifo_data[10] +.sym 11499 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 11500 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 11501 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 11502 w_rx_09_fifo_data[28] +.sym 11504 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 11509 channel +.sym 11511 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.sym 11513 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 11514 i_ss$SB_IO_IN +.sym 11515 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 11516 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 11517 tx_fifo.rd_addr_gray_wr_r[1] +.sym 11518 channel +.sym 11519 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 11521 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 11522 tx_fifo.rd_addr_gray_wr_r[2] +.sym 11523 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 11524 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 11525 w_rx_data[0] +.sym 11527 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 11528 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 11529 tx_fifo.wr_addr[4] +.sym 11531 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 11532 w_rx_09_fifo_data[10] +.sym 11542 i_rst_b_SB_LUT4_I3_O +.sym 11546 smi_ctrl_ins.frame_sr[11] +.sym 11547 r_counter +.sym 11548 smi_ctrl_ins.frame_sr[0] +.sym 11549 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 11550 smi_ctrl_ins.frame_sr[14] +.sym 11552 smi_ctrl_ins.frame_sr[20] +.sym 11555 smi_ctrl_ins.frame_sr[17] +.sym 11560 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11561 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 11567 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 11572 smi_ctrl_ins.frame_sr[0] +.sym 11579 smi_ctrl_ins.frame_sr[20] +.sym 11583 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11585 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 11586 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 11589 smi_ctrl_ins.frame_sr[11] +.sym 11596 smi_ctrl_ins.frame_sr[17] +.sym 11613 smi_ctrl_ins.frame_sr[14] +.sym 11617 smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.sym 11618 r_counter +.sym 11619 i_rst_b_SB_LUT4_I3_O +.sym 11621 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 11622 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 11623 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 11624 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 11625 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 11627 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 11632 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11633 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 11636 lvds_tx_inst.tx_state_d1 +.sym 11637 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 11639 tx_fifo.wr_addr[4] +.sym 11641 tx_fifo.wr_addr[7] +.sym 11646 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 11647 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 11650 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 11651 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 11653 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 11654 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 11655 w_rx_data[0] +.sym 11661 tx_fifo.wr_addr[0] +.sym 11665 tx_fifo.wr_addr[4] +.sym 11671 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 11672 tx_fifo.wr_addr[2] +.sym 11674 tx_fifo.wr_addr[0] +.sym 11675 tx_fifo.wr_addr[5] +.sym 11679 tx_fifo.wr_addr[7] +.sym 11682 tx_fifo.wr_addr[6] +.sym 11683 tx_fifo.wr_addr[3] +.sym 11693 $nextpnr_ICESTORM_LC_0$O +.sym 11696 tx_fifo.wr_addr[0] +.sym 11699 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 11702 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 11703 tx_fifo.wr_addr[0] +.sym 11705 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 11708 tx_fifo.wr_addr[2] +.sym 11709 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 11711 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 11713 tx_fifo.wr_addr[3] +.sym 11715 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 11717 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 11720 tx_fifo.wr_addr[4] +.sym 11721 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 11723 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 11726 tx_fifo.wr_addr[5] +.sym 11727 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 11729 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 11731 tx_fifo.wr_addr[6] +.sym 11733 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 11735 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 11737 tx_fifo.wr_addr[7] +.sym 11739 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 11743 w_tx_data_sys[2] +.sym 11744 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 11745 w_tx_data_sys[5] +.sym 11746 w_tx_data_sys[3] +.sym 11747 w_tx_data_sys[4] +.sym 11748 w_tx_data_sys[1] +.sym 11750 w_tx_data_sys[0] +.sym 11754 spi_if_ins.w_rx_data[4] +.sym 11755 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 11758 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 11762 tx_fifo.rd_addr[4] +.sym 11764 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 11765 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 11766 lvds_rx_09_inst.r_phase_count[1] +.sym 11767 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 11768 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 11769 w_ioc[2] +.sym 11770 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 11771 tx_fifo.wr_addr[5] +.sym 11772 tx_fifo.wr_addr[8] +.sym 11775 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 11776 w_tx_data_sys[2] +.sym 11778 spi_if_ins.w_rx_data[0] +.sym 11779 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 11785 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 11786 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 11787 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 11789 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 11793 r_counter +.sym 11794 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 11795 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 11796 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 11797 i_rst_b_SB_LUT4_I3_O +.sym 11811 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 11813 tx_fifo.wr_addr[8] +.sym 11815 tx_fifo.rd_addr_gray_wr_r[3] +.sym 11816 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] +.sym 11819 tx_fifo.wr_addr[8] +.sym 11820 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 11824 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 11826 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] +.sym 11830 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 11838 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 11842 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 11847 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 11848 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 11854 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 11859 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 11860 tx_fifo.rd_addr_gray_wr_r[3] +.sym 11861 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 11863 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 11864 r_counter +.sym 11865 i_rst_b_SB_LUT4_I3_O +.sym 11866 w_rx_sync_type_09 +.sym 11867 w_rx_sync_type_24 +.sym 11868 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 11869 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 11870 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 11872 sys_ctrl_ins.tx_sample_gap[0] +.sym 11873 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 11875 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 11878 i_rst_b_SB_LUT4_I3_O +.sym 11880 tx_fifo.wr_addr[8] +.sym 11881 w_tx_data_sys[3] +.sym 11882 w_rx_data[1] +.sym 11885 i_rst_b_SB_LUT4_I3_O +.sym 11886 tx_fifo.wr_addr[2] +.sym 11887 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 11888 tx_fifo.wr_addr[4] +.sym 11889 w_tx_data_sys[5] +.sym 11890 $PACKER_VCC_NET +.sym 11891 w_ioc[4] +.sym 11892 spi_if_ins.w_rx_data[1] +.sym 11893 tx_fifo.wr_addr[2] +.sym 11894 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 11895 spi_if_ins.w_rx_data[3] +.sym 11897 tx_fifo.rd_addr_gray_wr_r[8] +.sym 11898 i_sck$SB_IO_IN +.sym 11899 w_ioc[3] +.sym 11900 w_rx_data[4] +.sym 11909 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 11911 tx_fifo.wr_addr[4] +.sym 11917 tx_fifo.wr_addr[6] +.sym 11918 tx_fifo.wr_addr[2] +.sym 11921 tx_fifo.wr_addr[5] +.sym 11929 tx_fifo.wr_addr[8] +.sym 11934 tx_fifo.wr_addr[7] +.sym 11937 tx_fifo.wr_addr[3] +.sym 11939 $nextpnr_ICESTORM_LC_10$O +.sym 11942 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 11945 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 11947 tx_fifo.wr_addr[2] +.sym 11951 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 11953 tx_fifo.wr_addr[3] +.sym 11955 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 11957 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 11959 tx_fifo.wr_addr[4] +.sym 11961 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 11963 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 11965 tx_fifo.wr_addr[5] +.sym 11967 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 11969 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 11972 tx_fifo.wr_addr[6] +.sym 11973 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 11975 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 11978 tx_fifo.wr_addr[7] +.sym 11979 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 11981 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 11983 tx_fifo.wr_addr[8] +.sym 11985 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 11989 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 11990 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 11991 w_ioc[1] +.sym 11993 w_cs[0] +.sym 11994 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 11995 w_ioc[0] +.sym 11996 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 12001 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 12003 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 12007 w_rx_data[5] +.sym 12009 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 12010 w_rx_sync_type_24 +.sym 12011 tx_fifo.rd_addr_gray_wr_r[1] +.sym 12016 w_rx_data[0] +.sym 12020 w_rx_data[2] +.sym 12024 w_rx_data[3] +.sym 12025 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 12030 r_counter +.sym 12035 tx_fifo.rd_addr_gray_wr_r[6] +.sym 12036 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 12039 spi_if_ins.w_rx_data[4] +.sym 12041 tx_wr_en +.sym 12043 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 12046 i_rst_b$SB_IO_IN +.sym 12047 spi_if_ins.w_rx_data[2] +.sym 12048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 12049 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 12055 spi_if_ins.w_rx_data[3] +.sym 12057 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 12059 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 12063 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 12064 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 12065 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 12066 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 12069 spi_if_ins.w_rx_data[2] +.sym 12075 spi_if_ins.w_rx_data[3] +.sym 12081 tx_fifo.rd_addr_gray_wr_r[6] +.sym 12082 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 12084 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 12087 tx_wr_en +.sym 12089 i_rst_b$SB_IO_IN +.sym 12101 spi_if_ins.w_rx_data[4] +.sym 12109 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 12110 r_counter +.sym 12114 spi_if_ins.spi.r_rx_bit_count[2] +.sym 12115 spi_if_ins.spi.r_rx_bit_count[0] +.sym 12117 spi_if_ins.spi.r_rx_bit_count[1] +.sym 12118 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 12120 tx_wr_data[29] +.sym 12122 spi_if_ins.w_rx_data[2] +.sym 12124 tx_fifo.wr_addr[4] +.sym 12125 w_ioc[0] +.sym 12126 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 12128 w_ioc[2] +.sym 12130 spi_if_ins.spi.r2_rx_done +.sym 12131 tx_fifo.rd_addr_gray_wr_r[6] +.sym 12133 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 12135 w_ioc[1] +.sym 12141 tx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 12142 w_rx_data[0] +.sym 12153 r_counter +.sym 12155 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 12165 spi_if_ins.w_rx_data[3] +.sym 12169 spi_if_ins.w_rx_data[4] +.sym 12175 spi_if_ins.w_rx_data[2] +.sym 12183 spi_if_ins.w_rx_data[0] +.sym 12195 spi_if_ins.w_rx_data[2] +.sym 12204 spi_if_ins.w_rx_data[3] +.sym 12217 spi_if_ins.w_rx_data[4] +.sym 12228 spi_if_ins.w_rx_data[0] +.sym 12232 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 12233 r_counter +.sym 12240 tx_wr_data[14] +.sym 12243 i_ss$SB_IO_IN +.sym 12245 w_rx_data[4] +.sym 12247 w_rx_data[2] +.sym 12248 i_ss$SB_IO_IN +.sym 12251 w_rx_data[3] +.sym 12253 r_counter .sym 12310 w_smi_data_output[0] .sym 12312 w_smi_data_direction .sym 12313 w_smi_data_output[7] .sym 12315 w_smi_data_direction .sym 12316 $PACKER_VCC_NET +.sym 12319 w_smi_data_output[0] .sym 12321 w_smi_data_direction -.sym 12324 $PACKER_VCC_NET -.sym 12326 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 12324 w_smi_data_output[7] .sym 12329 w_smi_data_direction -.sym 12333 w_smi_data_output[7] -.sym 12334 w_smi_data_output[0] -.sym 12335 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 12336 tx_fifo.wr_addr_gray_rd[9] -.sym 12337 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12338 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12339 tx_fifo.wr_addr_gray_rd[3] -.sym 12340 i_rst_b_SB_LUT4_I3_O -.sym 12341 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 12342 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E -.sym 12369 w_smi_data_input[7] -.sym 12379 tx_fifo.rd_addr[1] -.sym 12382 tx_fifo.rd_addr[3] -.sym 12385 tx_fifo.rd_addr[0] -.sym 12386 tx_fifo.rd_addr[2] -.sym 12388 tx_fifo.rd_addr[4] -.sym 12390 tx_fifo.rd_addr[0] -.sym 12392 tx_fifo.rd_addr[7] -.sym 12399 tx_fifo.rd_addr[5] -.sym 12406 tx_fifo.rd_addr[6] -.sym 12409 $nextpnr_ICESTORM_LC_7$O -.sym 12411 tx_fifo.rd_addr[0] -.sym 12415 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 -.sym 12417 tx_fifo.rd_addr[1] -.sym 12419 tx_fifo.rd_addr[0] -.sym 12421 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 12424 tx_fifo.rd_addr[2] -.sym 12425 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 -.sym 12427 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 12430 tx_fifo.rd_addr[3] -.sym 12431 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 12433 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 12436 tx_fifo.rd_addr[4] -.sym 12437 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 12439 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 12441 tx_fifo.rd_addr[5] -.sym 12443 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 12445 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12448 tx_fifo.rd_addr[6] -.sym 12449 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 12451 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12453 tx_fifo.rd_addr[7] -.sym 12455 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12463 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] -.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12465 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 12466 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12467 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 12468 tx_fifo.rd_addr[6] -.sym 12469 tx_fifo.rd_addr[5] -.sym 12470 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] -.sym 12477 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 12489 $PACKER_VCC_NET -.sym 12502 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12504 smi_ctrl_ins.int_cnt_rx[4] -.sym 12511 w_smi_data_output[3] -.sym 12513 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 12515 smi_ctrl_ins.int_cnt_rx[3] -.sym 12516 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12517 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12518 i_ss$SB_IO_IN -.sym 12519 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12522 smi_ctrl_ins.int_cnt_rx[4] -.sym 12526 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12529 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12535 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12540 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12543 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 12550 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12551 smi_ctrl_ins.int_cnt_rx[3] -.sym 12553 w_tx_fifo_pull -.sym 12555 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12557 tx_fifo.rd_addr[2] -.sym 12559 tx_fifo.wr_addr_gray_rd_r[2] -.sym 12561 tx_fifo.rd_addr[3] -.sym 12562 smi_ctrl_ins.int_cnt_rx[4] -.sym 12564 tx_fifo.rd_addr[8] -.sym 12565 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 12567 tx_fifo.rd_addr[4] -.sym 12569 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 12572 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12574 tx_fifo.rd_addr[8] -.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12580 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 12582 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 12585 w_tx_fifo_pull -.sym 12586 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 12587 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 12588 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12592 smi_ctrl_ins.int_cnt_rx[3] -.sym 12597 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12599 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12603 tx_fifo.wr_addr_gray_rd_r[2] -.sym 12604 tx_fifo.rd_addr[4] -.sym 12605 tx_fifo.rd_addr[2] -.sym 12606 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 12609 smi_ctrl_ins.int_cnt_rx[3] -.sym 12611 smi_ctrl_ins.int_cnt_rx[4] -.sym 12615 tx_fifo.rd_addr[3] -.sym 12616 tx_fifo.rd_addr[4] -.sym 12618 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 12620 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12622 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 12623 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 12624 tx_fifo.rd_addr_gray[1] -.sym 12625 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12626 tx_fifo.rd_addr_gray[7] -.sym 12627 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 12629 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 12639 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 12643 rx_fifo.mem_q.0.3_WDATA_2 -.sym 12647 tx_fifo.wr_addr[1] -.sym 12648 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 12649 smi_ctrl_ins.int_cnt_rx[3] -.sym 12650 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 12654 tx_fifo.rd_addr[5] -.sym 12655 tx_fifo.wr_addr_gray_rd[3] -.sym 12657 $PACKER_VCC_NET -.sym 12664 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12665 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] -.sym 12667 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 12668 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12669 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12670 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 12671 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12672 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12673 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] -.sym 12675 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12676 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] -.sym 12677 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] -.sym 12678 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] -.sym 12679 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12682 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] -.sym 12683 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12684 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 12686 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12688 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12689 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12690 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12691 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 12692 w_tx_fifo_pull -.sym 12693 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 12696 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] -.sym 12697 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] -.sym 12698 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] -.sym 12699 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] -.sym 12702 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12705 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12708 w_tx_fifo_pull -.sym 12709 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12710 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12714 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 12715 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 12716 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 12717 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 12721 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12723 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12726 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 12727 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 12728 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12729 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 12732 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] -.sym 12733 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 12734 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] -.sym 12735 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 12738 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 12739 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 12740 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 12743 lvds_clock_$glb_clk -.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12745 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 12746 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 12747 tx_fifo.wr_addr_gray[6] -.sym 12748 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] -.sym 12750 tx_fifo.wr_addr_gray[4] -.sym 12759 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 12760 w_smi_data_output[5] -.sym 12769 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 12770 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 12772 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12777 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 12779 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 12780 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 12790 tx_fifo.rd_addr[8] -.sym 12791 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 12793 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12795 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12798 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 12799 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 12803 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12804 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12813 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 12814 tx_fifo.rd_addr[5] -.sym 12820 tx_fifo.rd_addr[5] -.sym 12822 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 12834 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 12844 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 12849 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 12850 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 12851 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 12852 tx_fifo.rd_addr[8] -.sym 12857 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 12862 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 12864 tx_fifo.rd_addr[8] -.sym 12865 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 12866 lvds_clock_$glb_clk -.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12868 tx_fifo.wr_addr_gray[1] -.sym 12869 tx_fifo.wr_addr_gray[0] -.sym 12870 tx_fifo.wr_addr_gray[8] -.sym 12871 tx_fifo.wr_addr_gray[2] -.sym 12872 tx_fifo.wr_addr_gray[5] -.sym 12875 tx_fifo.wr_addr_gray[7] -.sym 12884 rx_fifo.mem_q.0.3_WDATA -.sym 12886 tx_fifo.rd_addr_gray[8] -.sym 12889 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 12892 rx_fifo.wr_addr[8] -.sym 12894 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 12895 i_rst_b$SB_IO_IN -.sym 12898 rx_fifo.rd_addr[2] -.sym 12900 rx_fifo.wr_addr[0] -.sym 12911 tx_fifo.wr_addr_gray[6] -.sym 12913 tx_fifo.wr_addr_gray_rd[4] -.sym 12922 tx_fifo.wr_addr_gray[4] -.sym 12925 tx_fifo.wr_addr_gray_rd[3] -.sym 12926 tx_fifo.wr_addr_gray_rd[8] -.sym 12927 tx_fifo.wr_addr_gray[8] -.sym 12939 tx_fifo.wr_addr_gray_rd[7] -.sym 12940 tx_fifo.wr_addr_gray_rd[2] -.sym 12944 tx_fifo.wr_addr_gray[6] -.sym 12949 tx_fifo.wr_addr_gray[8] -.sym 12956 tx_fifo.wr_addr_gray_rd[3] -.sym 12963 tx_fifo.wr_addr_gray_rd[2] -.sym 12966 tx_fifo.wr_addr_gray[4] -.sym 12972 tx_fifo.wr_addr_gray_rd[7] -.sym 12981 tx_fifo.wr_addr_gray_rd[8] -.sym 12987 tx_fifo.wr_addr_gray_rd[4] -.sym 12989 lvds_clock_$glb_clk -.sym 12991 tx_fifo.wr_addr_gray_rd[0] -.sym 12993 tx_fifo.wr_addr_gray_rd[5] -.sym 12996 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 12997 tx_fifo.wr_addr_gray_rd[7] -.sym 12998 tx_fifo.wr_addr_gray_rd[2] -.sym 13005 rx_fifo.mem_i.0.0_WDATA_1 -.sym 13007 rx_fifo.wr_addr[6] -.sym 13011 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 13012 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 13013 rx_fifo.mem_i.0.3_WDATA_1 -.sym 13016 rx_fifo.rd_addr[1] -.sym 13018 $PACKER_VCC_NET -.sym 13019 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 13020 rx_fifo.wr_addr[1] -.sym 13022 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 13024 i_ss$SB_IO_IN -.sym 13026 rx_fifo.rd_addr[2] -.sym 13032 tx_fifo.wr_addr_gray_rd[6] -.sym 13040 tx_fifo.wr_addr_gray[1] -.sym 13048 tx_fifo.wr_addr_gray_rd[0] -.sym 13079 tx_fifo.wr_addr_gray_rd[6] -.sym 13089 tx_fifo.wr_addr_gray_rd[0] -.sym 13102 tx_fifo.wr_addr_gray[1] -.sym 13112 lvds_clock_$glb_clk -.sym 13116 tx_fifo.rd_addr_gray[0] -.sym 13122 io_pmod_in[3]$SB_IO_IN -.sym 13125 io_pmod_in[3]$SB_IO_IN -.sym 13128 rx_fifo.mem_i.0.3_WDATA -.sym 13131 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 13132 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 13133 w_smi_read_req -.sym 13138 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 13140 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 13142 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 13144 $PACKER_VCC_NET -.sym 13146 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 13147 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13159 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 13164 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 13165 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 13166 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 13170 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 13173 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 13179 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 13190 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 13197 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 13206 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 13214 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 13218 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 13226 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 13234 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O -.sym 13235 r_counter_$glb_clk -.sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13238 $PACKER_VCC_NET -.sym 13239 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 13240 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 13241 spi_if_ins.spi.r_tx_bit_count[0] -.sym 13242 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 13244 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 13245 io_pmod_in[2]$SB_IO_IN -.sym 13248 io_pmod_in[2]$SB_IO_IN -.sym 13249 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 13251 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 13253 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 13257 rx_fifo.rd_addr[2] -.sym 13258 w_rx_fifo_pulled_data[18] -.sym 13259 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 13260 rx_fifo.mem_i.0.3_WDATA_3 -.sym 13264 rx_fifo.rd_addr[2] -.sym 13265 i_rst_b$SB_IO_IN -.sym 13267 rx_fifo.rd_addr[9] -.sym 13268 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 13270 rx_fifo.rd_addr[1] -.sym 13272 $PACKER_VCC_NET -.sym 13280 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 13288 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 13289 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13291 spi_if_ins.r_tx_data_valid -.sym 13294 i_ss$SB_IO_IN -.sym 13298 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13299 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 13301 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 13303 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 13306 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 13307 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 13320 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 13323 spi_if_ins.r_tx_data_valid -.sym 13325 i_ss$SB_IO_IN -.sym 13329 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 13331 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 13335 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 13336 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 13342 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 13347 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 13348 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 13350 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 13355 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 13356 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 13357 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13358 r_counter_$glb_clk -.sym 13359 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 13361 w_smi_read_req -.sym 13363 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 13364 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13366 w_fetch -.sym 13367 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 13378 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 13379 o_led0_SB_LUT4_I1_O[1] -.sym 13381 $PACKER_VCC_NET -.sym 13382 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 13388 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 13389 w_cs[2] -.sym 13390 w_rx_data[2] -.sym 13391 i_rst_b$SB_IO_IN -.sym 13392 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13403 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13404 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 13405 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13407 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 13408 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 13409 spi_if_ins.state_if[0] -.sym 13411 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13413 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13416 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13417 i_rst_b$SB_IO_IN -.sym 13420 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13421 spi_if_ins.state_if[1] -.sym 13424 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13425 i_rst_b$SB_IO_IN -.sym 13427 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 13431 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13437 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13440 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 13442 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 13446 spi_if_ins.state_if[1] -.sym 13448 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13449 spi_if_ins.state_if[0] -.sym 13452 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13453 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13454 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13455 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13459 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13461 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13464 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 13465 i_rst_b$SB_IO_IN -.sym 13466 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13467 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 13470 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13471 i_rst_b$SB_IO_IN -.sym 13476 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 13480 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13481 r_counter_$glb_clk -.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13483 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 13484 w_rx_data[2] -.sym 13485 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 13486 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 13488 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 13489 w_rx_data[6] -.sym 13490 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] -.sym 13496 w_fetch -.sym 13497 spi_if_ins.state_if_SB_DFFESR_Q_E -.sym 13499 rx_fifo.wr_addr[6] -.sym 13507 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 13509 spi_if_ins.r_tx_byte[7] -.sym 13510 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 13518 w_rx_data[2] -.sym 13524 spi_if_ins.state_if[0] -.sym 13526 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 13528 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13531 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 13532 spi_if_ins.state_if[0] -.sym 13535 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 13536 spi_if_ins.state_if[1] -.sym 13537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13538 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 13539 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13541 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13548 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 13549 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 13557 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 13558 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 13559 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 13560 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 13563 spi_if_ins.state_if[0] -.sym 13564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13565 spi_if_ins.state_if[1] -.sym 13569 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13571 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 13576 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13581 spi_if_ins.state_if[0] -.sym 13584 spi_if_ins.state_if[1] -.sym 13587 spi_if_ins.state_if[1] -.sym 13588 spi_if_ins.state_if[0] -.sym 13590 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13593 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13594 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 13595 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13599 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 13600 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 13602 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 13604 r_counter_$glb_clk -.sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13606 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 13607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] -.sym 13608 w_cs[0] -.sym 13611 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 13612 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 13613 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 13618 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 13619 w_rx_data[6] -.sym 13620 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 13621 spi_if_ins.w_rx_data[6] -.sym 13627 rx_fifo.rd_addr[9] -.sym 13628 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13629 spi_if_ins.w_rx_data[2] -.sym 13633 spi_if_ins.r_tx_byte[7] -.sym 13634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 13637 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 13640 i_rst_b$SB_IO_IN -.sym 13647 rx_fifo.rd_addr_gray_wr[2] -.sym 13651 rx_fifo.rd_addr_gray[2] -.sym 13658 rx_fifo.rd_addr_gray[6] -.sym 13664 rx_fifo.rd_addr_gray_wr[6] -.sym 13677 rx_fifo.rd_addr_gray_wr[1] -.sym 13680 rx_fifo.rd_addr_gray[2] -.sym 13689 rx_fifo.rd_addr_gray[6] -.sym 13704 rx_fifo.rd_addr_gray_wr[2] -.sym 13712 rx_fifo.rd_addr_gray_wr[1] -.sym 13724 rx_fifo.rd_addr_gray_wr[6] -.sym 13727 lvds_clock_$glb_clk -.sym 13729 w_tx_data_io[7] -.sym 13730 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 13731 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 13732 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 13733 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 13735 i_button_SB_LUT4_I0_I3[3] -.sym 13736 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 13748 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 13751 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 13752 w_cs[0] -.sym 13757 i_rst_b$SB_IO_IN -.sym 13760 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 13761 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 13772 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 13776 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 13777 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 13779 w_rx_data[0] -.sym 13783 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 13788 w_rx_data[2] -.sym 13805 w_rx_data[2] -.sym 13817 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 13827 w_rx_data[0] -.sym 13840 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 13841 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 13849 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 13850 r_counter_$glb_clk -.sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13852 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 13853 w_tx_data_io[5] -.sym 13854 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 13856 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 13857 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 13858 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 13859 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 13871 w_cs[2] -.sym 13872 w_cs[1] -.sym 13878 i_rst_b$SB_IO_IN -.sym 13880 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 13881 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 13882 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 13883 w_cs[3] -.sym 13885 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 13887 w_rx_data[2] -.sym 13898 rx_fifo.rd_addr_gray[1] -.sym 13944 rx_fifo.rd_addr_gray[1] -.sym 13973 lvds_clock_$glb_clk -.sym 13975 r_tx_data[2] -.sym 13980 r_tx_data[0] -.sym 13982 r_tx_data[7] -.sym 13988 i_button_SB_LUT4_I0_I3[1] -.sym 13991 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 13993 w_rx_fifo_full -.sym 13994 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 13995 w_tx_data_io[2] -.sym 13999 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14001 spi_if_ins.r_tx_byte[7] -.sym 14003 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 14006 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] -.sym 14008 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 14018 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 14024 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14025 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 14035 io_pmod_in[2]$SB_IO_IN -.sym 14042 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 14043 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 14057 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 14058 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 14079 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14080 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 14081 io_pmod_in[2]$SB_IO_IN -.sym 14095 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 14096 lvds_clock_$glb_clk -.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14098 spi_if_ins.r_tx_byte[2] -.sym 14101 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 14102 spi_if_ins.r_tx_byte[0] -.sym 14105 spi_if_ins.r_tx_byte[7] -.sym 14107 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 14111 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 14112 o_shdn_tx_lna$SB_IO_OUT -.sym 14114 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 14118 o_tr_vc1$SB_IO_OUT -.sym 14119 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 14129 spi_if_ins.r_tx_byte[7] -.sym 14131 i_rst_b$SB_IO_IN -.sym 14150 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 14151 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 14159 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14162 io_pmod_in[3]$SB_IO_IN -.sym 14197 io_pmod_in[3]$SB_IO_IN -.sym 14198 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 14199 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 14218 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 14219 lvds_clock_$glb_clk -.sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14222 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 14223 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 14224 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] -.sym 14225 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 14226 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 14227 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] +.sym 12332 $PACKER_VCC_NET +.sym 12336 lvds_tx_inst.r_sync_count[1] +.sym 12337 w_smi_data_direction +.sym 12362 w_smi_data_output[7] +.sym 12377 w_smi_data_input[3] +.sym 12381 w_smi_data_input[0] +.sym 12382 smi_ctrl_ins.d_q1[3] +.sym 12385 smi_ctrl_ins.d_q1[7] +.sym 12386 smi_ctrl_ins.d_q2[5] +.sym 12397 smi_ctrl_ins.d_q2[7] +.sym 12398 w_smi_data_input[5] +.sym 12399 smi_ctrl_ins.d_q1[5] +.sym 12402 r_counter +.sym 12412 smi_ctrl_ins.d_q2[5] +.sym 12419 smi_ctrl_ins.d_q1[5] +.sym 12423 smi_ctrl_ins.d_q1[3] +.sym 12431 w_smi_data_input[0] +.sym 12435 smi_ctrl_ins.d_q1[7] +.sym 12441 w_smi_data_input[3] +.sym 12447 w_smi_data_input[5] +.sym 12453 smi_ctrl_ins.d_q2[7] +.sym 12457 r_counter +.sym 12459 w_smi_data_input[3] +.sym 12463 w_smi_read_req_SB_LUT4_I1_I2[2] +.sym 12464 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] +.sym 12465 w_rx_fifo_pull +.sym 12466 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12467 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[3] +.sym 12468 w_smi_data_direction +.sym 12469 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 12470 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 12478 rx_fifo.wr_addr[3] +.sym 12480 rx_fifo.wr_addr[2] +.sym 12482 rx_fifo.wr_addr[8] +.sym 12484 lvds_tx_inst.frame_boundary +.sym 12485 smi_ctrl_ins.d_q1[7] +.sym 12486 rx_fifo.wr_addr[6] +.sym 12492 w_smi_data_input[5] +.sym 12503 w_smi_data_direction +.sym 12506 w_smi_data_output[3] +.sym 12514 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[0] +.sym 12517 smi_ctrl_ins.soe_and_reset +.sym 12520 w_rx_fifo_pulled_data[21] +.sym 12523 r_counter +.sym 12527 r_counter +.sym 12528 smi_ctrl_ins.int_cnt_rx[3] +.sym 12542 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 12544 smi_ctrl_ins.byte_ix[3] +.sym 12548 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12549 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12550 smi_ctrl_ins.byte_ix[0] +.sym 12551 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12552 smi_ctrl_ins.byte_ix[3] +.sym 12553 smi_ctrl_ins.r_fifo_pull +.sym 12554 smi_ctrl_ins.byte_ix[1] +.sym 12555 smi_ctrl_ins.byte_ix[2] +.sym 12556 r_counter +.sym 12558 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 12559 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12560 i_rst_b_SB_LUT4_I3_O +.sym 12564 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 12571 smi_ctrl_ins.w_fifo_pull_trigger +.sym 12580 smi_ctrl_ins.r_fifo_pull +.sym 12585 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 12587 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 12588 smi_ctrl_ins.byte_ix[3] +.sym 12591 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 12592 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 12593 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12594 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 12597 smi_ctrl_ins.byte_ix[3] +.sym 12598 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 12599 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 12600 smi_ctrl_ins.byte_ix[1] +.sym 12606 smi_ctrl_ins.w_fifo_pull_trigger +.sym 12609 smi_ctrl_ins.byte_ix[2] +.sym 12610 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 12611 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 12612 smi_ctrl_ins.byte_ix[1] +.sym 12615 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 12616 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 12617 smi_ctrl_ins.byte_ix[0] +.sym 12618 smi_ctrl_ins.byte_ix[2] +.sym 12620 r_counter +.sym 12621 i_rst_b_SB_LUT4_I3_O +.sym 12622 w_smi_data_output[0] +.sym 12623 w_smi_data_output[3] +.sym 12624 w_smi_data_output[5] +.sym 12625 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[3] +.sym 12626 w_smi_data_output[2] +.sym 12627 w_smi_data_output[7] +.sym 12628 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 12629 smi_ctrl_ins.w_fifo_pull_trigger +.sym 12635 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 12636 w_rx_data[0] +.sym 12637 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 12639 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 12641 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 12644 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 12645 w_rx_fifo_pull +.sym 12646 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 12647 w_rx_09_fifo_data[8] +.sym 12648 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] +.sym 12649 smi_ctrl_ins.int_cnt_rx[4] +.sym 12651 w_rx_fifo_pulled_data[14] +.sym 12652 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 12653 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] +.sym 12654 i_rst_b_SB_LUT4_I3_O +.sym 12655 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 12656 rx_fifo.wr_addr[5] +.sym 12657 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 12663 w_rx_fifo_pulled_data[1] +.sym 12665 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 12671 w_rx_fifo_pulled_data[26] +.sym 12677 w_rx_fifo_pulled_data[18] +.sym 12678 w_rx_fifo_pulled_data[2] +.sym 12679 smi_ctrl_ins.soe_and_reset +.sym 12683 i_rst_b_SB_LUT4_I3_O +.sym 12685 w_rx_fifo_pulled_data[11] +.sym 12686 w_rx_fifo_pulled_data[21] +.sym 12687 w_rx_fifo_pulled_data[8] +.sym 12694 w_rx_fifo_pulled_data[20] +.sym 12696 w_rx_fifo_pulled_data[1] +.sym 12704 w_rx_fifo_pulled_data[26] +.sym 12710 w_rx_fifo_pulled_data[11] +.sym 12716 w_rx_fifo_pulled_data[21] +.sym 12720 w_rx_fifo_pulled_data[2] +.sym 12726 w_rx_fifo_pulled_data[8] +.sym 12733 w_rx_fifo_pulled_data[18] +.sym 12741 w_rx_fifo_pulled_data[20] +.sym 12742 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 12743 smi_ctrl_ins.soe_and_reset +.sym 12744 i_rst_b_SB_LUT4_I3_O +.sym 12745 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[1] +.sym 12746 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 12747 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[0] +.sym 12748 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[1] +.sym 12749 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 12750 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 12751 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 12752 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[3] +.sym 12754 w_smi_data_output[7] +.sym 12757 w_rx_fifo_pulled_data[1] +.sym 12758 rx_fifo.wr_addr[6] +.sym 12759 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[1] +.sym 12760 rx_fifo.wr_addr[2] +.sym 12761 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 12762 rx_fifo.wr_addr[8] +.sym 12764 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 12765 w_rx_fifo_pulled_data[18] +.sym 12766 w_rx_fifo_pulled_data[2] +.sym 12767 w_rx_fifo_pulled_data[26] +.sym 12768 w_tx_fifo_pulled_data[12] +.sym 12769 w_rx_fifo_data[3] +.sym 12770 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 12771 w_rx_fifo_pulled_data[11] +.sym 12772 w_rx_fifo_pulled_data[13] +.sym 12773 w_rx_24_fifo_data[9] +.sym 12774 w_rx_fifo_pulled_data[15] +.sym 12775 w_rx_fifo_pulled_data[3] +.sym 12776 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 12778 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 12779 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] +.sym 12780 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 12786 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[0] +.sym 12787 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 12788 smi_ctrl_ins.int_cnt_rx[3] +.sym 12789 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[3] +.sym 12790 i_rst_b_SB_LUT4_I3_O +.sym 12791 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 12792 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 12794 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 12795 smi_ctrl_ins.soe_and_reset +.sym 12796 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[3] +.sym 12797 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 12798 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[3] +.sym 12799 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 12800 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] +.sym 12801 smi_ctrl_ins.int_cnt_rx[4] +.sym 12802 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[1] +.sym 12806 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 12807 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 12808 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] +.sym 12809 smi_ctrl_ins.int_cnt_rx[4] +.sym 12814 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 12815 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 12817 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 12819 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 12820 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 12821 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 12822 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 12825 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[3] +.sym 12826 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 12827 smi_ctrl_ins.int_cnt_rx[4] +.sym 12828 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] +.sym 12831 smi_ctrl_ins.int_cnt_rx[4] +.sym 12832 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] +.sym 12833 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[0] +.sym 12834 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[3] +.sym 12837 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 12838 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 12839 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 12840 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 12844 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 12850 smi_ctrl_ins.int_cnt_rx[3] +.sym 12855 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 12856 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[3] +.sym 12857 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[1] +.sym 12858 smi_ctrl_ins.int_cnt_rx[4] +.sym 12861 smi_ctrl_ins.int_cnt_rx[4] +.sym 12862 smi_ctrl_ins.int_cnt_rx[3] +.sym 12866 smi_ctrl_ins.soe_and_reset +.sym 12867 i_rst_b_SB_LUT4_I3_O +.sym 12868 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 12869 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 12870 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[1] +.sym 12871 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 12872 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 12873 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 12874 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[0] +.sym 12875 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 12880 w_rx_fifo_pulled_data[16] +.sym 12881 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 12882 smi_ctrl_ins.int_cnt_rx[3] +.sym 12883 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 12885 rx_fifo.rd_addr[8] +.sym 12886 rx_fifo.rd_addr[3] +.sym 12887 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 12889 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 12891 w_rx_09_fifo_data[19] +.sym 12892 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 12893 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 12894 w_rx_fifo_pulled_data[22] +.sym 12895 rx_fifo.rd_addr_gray_wr_r[0] +.sym 12896 smi_ctrl_ins.soe_and_reset +.sym 12897 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 12898 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 12899 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 12900 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 12903 smi_ctrl_ins.int_cnt_rx[4] +.sym 12910 w_rx_09_fifo_data[1] +.sym 12911 rx_fifo.rd_addr_gray_wr_r[7] +.sym 12913 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 12914 smi_ctrl_ins.int_cnt_rx[3] +.sym 12915 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 12916 smi_ctrl_ins.int_cnt_rx[4] +.sym 12918 channel +.sym 12919 smi_ctrl_ins.d_byte[1] +.sym 12920 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 12921 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 12922 i_rst_b_SB_LUT4_I3_O +.sym 12923 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 12924 smi_ctrl_ins.d_byte[2] +.sym 12925 r_counter +.sym 12927 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 12928 w_rx_24_fifo_data[1] +.sym 12929 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 12930 w_rx_09_fifo_data[9] +.sym 12931 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 12932 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 12933 w_rx_24_fifo_data[9] +.sym 12937 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 12938 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 12944 smi_ctrl_ins.d_byte[2] +.sym 12948 w_rx_24_fifo_data[1] +.sym 12949 channel +.sym 12950 w_rx_09_fifo_data[1] +.sym 12954 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 12955 smi_ctrl_ins.int_cnt_rx[4] +.sym 12956 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 12957 smi_ctrl_ins.int_cnt_rx[3] +.sym 12960 smi_ctrl_ins.int_cnt_rx[3] +.sym 12961 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 12962 smi_ctrl_ins.int_cnt_rx[4] +.sym 12963 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 12966 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 12967 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 12968 rx_fifo.rd_addr_gray_wr_r[7] +.sym 12969 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 12972 smi_ctrl_ins.d_byte[1] +.sym 12978 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 12979 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 12981 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 12984 w_rx_24_fifo_data[9] +.sym 12986 w_rx_09_fifo_data[9] +.sym 12987 channel +.sym 12988 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 12989 r_counter +.sym 12990 i_rst_b_SB_LUT4_I3_O +.sym 12991 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 12992 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 12993 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 12994 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 12995 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 12996 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] +.sym 12997 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 12998 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 12999 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 13003 w_rx_fifo_pulled_data[17] +.sym 13004 w_rx_fifo_pulled_data[29] +.sym 13005 rx_fifo.rd_addr_gray_wr_r[7] +.sym 13006 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 13007 w_rx_fifo_data[1] +.sym 13009 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 13011 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 13012 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 13014 rx_fifo.wr_addr[0] +.sym 13015 w_tx_fifo_full +.sym 13016 w_rx_09_fifo_data[9] +.sym 13017 w_rx_fifo_pulled_data[23] +.sym 13018 w_rx_09_fifo_data[18] +.sym 13020 i_rst_b$SB_IO_IN +.sym 13021 w_tx_fsm_state[1] +.sym 13022 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 13023 i_mosi$SB_IO_IN +.sym 13024 r_counter +.sym 13025 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 13026 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 13033 w_rx_24_fifo_data[25] +.sym 13034 channel +.sym 13035 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 13036 i_rst_b_SB_LUT4_I3_O +.sym 13037 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 13038 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 13040 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 13041 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 13042 smi_ctrl_ins.int_cnt_rx[3] +.sym 13045 w_rx_24_fifo_data[3] +.sym 13047 w_rx_09_fifo_data[25] +.sym 13048 r_counter +.sym 13050 w_rx_24_fifo_data[13] +.sym 13052 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 13053 lvds_tx_inst.frame_boundary +.sym 13054 w_tx_fifo_pulled_data[14] +.sym 13055 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 13056 w_rx_09_fifo_data[3] +.sym 13057 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 13059 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 13060 w_rx_09_fifo_data[13] +.sym 13061 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 13062 lvds_tx_inst.r_fifo_data[14] +.sym 13063 smi_ctrl_ins.int_cnt_rx[4] +.sym 13065 channel +.sym 13067 w_rx_24_fifo_data[3] +.sym 13068 w_rx_09_fifo_data[3] +.sym 13071 lvds_tx_inst.frame_boundary +.sym 13072 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 13074 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 13083 w_rx_24_fifo_data[25] +.sym 13084 channel +.sym 13086 w_rx_09_fifo_data[25] +.sym 13089 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 13090 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 13091 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 13092 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 13095 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 13096 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 13097 smi_ctrl_ins.int_cnt_rx[3] +.sym 13098 smi_ctrl_ins.int_cnt_rx[4] +.sym 13101 w_rx_24_fifo_data[13] +.sym 13103 channel +.sym 13104 w_rx_09_fifo_data[13] +.sym 13107 lvds_tx_inst.r_fifo_data[14] +.sym 13108 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 13109 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 13110 w_tx_fifo_pulled_data[14] +.sym 13112 r_counter +.sym 13113 i_rst_b_SB_LUT4_I3_O +.sym 13114 w_rx_fifo_data[14] +.sym 13115 lvds_tx_inst.r_fifo_data[22] +.sym 13116 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 13117 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 13118 lvds_tx_inst.r_fifo_data[24] +.sym 13119 lvds_tx_inst.r_fifo_data[23] +.sym 13120 lvds_tx_inst.r_fifo_data[14] +.sym 13121 lvds_tx_inst.sent_first_sync +.sym 13126 rx_fifo.wr_addr[0] +.sym 13128 channel +.sym 13129 w_tx_fsm_state[0] +.sym 13130 w_rx_fifo_full +.sym 13131 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 13132 i_rst_b_SB_LUT4_I3_O +.sym 13134 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 13135 w_rx_09_fifo_data[24] +.sym 13136 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 13138 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 13141 lvds_tx_inst.r_fifo_data[23] +.sym 13142 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 13143 i_rst_b_SB_LUT4_I3_O +.sym 13144 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] +.sym 13146 w_rx_09_fifo_data[8] +.sym 13147 w_rx_fifo_data[14] +.sym 13149 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13155 w_rx_09_fifo_data[12] +.sym 13159 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 13160 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13162 w_rx_09_fifo_data[23] +.sym 13163 w_rx_09_fifo_data[0] +.sym 13164 w_rx_09_fifo_data[17] +.sym 13167 w_rx_09_fifo_data[27] +.sym 13169 w_rx_09_fifo_data[14] +.sym 13171 w_rx_09_fifo_data[16] +.sym 13172 w_rx_09_fifo_data[25] +.sym 13173 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13189 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13191 w_rx_09_fifo_data[14] +.sym 13194 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13196 w_rx_09_fifo_data[23] +.sym 13202 w_rx_09_fifo_data[17] +.sym 13203 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13206 w_rx_09_fifo_data[27] +.sym 13208 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13213 w_rx_09_fifo_data[25] +.sym 13215 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13218 w_rx_09_fifo_data[0] +.sym 13220 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13224 w_rx_09_fifo_data[12] +.sym 13227 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13230 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13233 w_rx_09_fifo_data[16] +.sym 13234 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13235 lvds_clock_buf +.sym 13236 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 13237 w_rx_09_fifo_data[9] +.sym 13238 tx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 13239 w_rx_09_fifo_data[8] +.sym 13240 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 13241 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13242 w_rx_09_fifo_data[15] +.sym 13243 w_rx_09_fifo_data[4] +.sym 13244 w_rx_09_fifo_data[21] +.sym 13249 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 13250 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.sym 13252 w_tx_fifo_pulled_data[28] +.sym 13255 w_rx_24_fifo_data[14] +.sym 13256 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 13257 lvds_tx_inst.frame_boundary +.sym 13258 lvds_tx_inst.r_fifo_data[22] +.sym 13259 channel +.sym 13261 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 13262 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13263 w_tx_fifo_pulled_data[23] +.sym 13264 w_tx_fifo_pulled_data[21] +.sym 13265 lvds_tx_inst.r_fifo_data[24] +.sym 13266 w_ioc[0] +.sym 13267 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13268 w_rx_09_fifo_data[21] +.sym 13269 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 13271 lvds_tx_inst.sent_first_sync +.sym 13272 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13281 w_rx_09_fifo_data[29] +.sym 13282 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 13293 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13296 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13297 w_rx_09_fifo_data[5] +.sym 13298 w_rx_09_fifo_data[13] +.sym 13300 w_rx_09_fifo_data[10] +.sym 13302 w_rx_09_fifo_data[3] +.sym 13303 w_rx_09_fifo_data[22] +.sym 13304 w_rx_09_fifo_data[20] +.sym 13311 w_rx_09_fifo_data[10] +.sym 13313 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13319 w_rx_09_fifo_data[20] +.sym 13320 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13323 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13326 w_rx_09_fifo_data[29] +.sym 13329 w_rx_09_fifo_data[3] +.sym 13332 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13337 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13342 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13344 w_rx_09_fifo_data[22] +.sym 13347 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13348 w_rx_09_fifo_data[5] +.sym 13354 w_rx_09_fifo_data[13] +.sym 13357 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13358 lvds_clock_buf +.sym 13359 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 13362 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 13364 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 13365 lvds_rx_24_inst.r_sync_input_SB_DFFER_Q_E +.sym 13371 spi_if_ins.w_rx_data[3] +.sym 13372 tx_fifo.rd_addr_gray_wr_r[6] +.sym 13373 $PACKER_VCC_NET +.sym 13374 tx_wr_data[26] +.sym 13375 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 13376 w_tx_fifo_pull +.sym 13378 tx_wr_data[27] +.sym 13379 w_rx_24_fifo_data[29] +.sym 13380 w_rx_09_fifo_data[6] +.sym 13383 i_sck$SB_IO_IN +.sym 13384 w_rx_09_fifo_data[8] +.sym 13385 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 13386 w_rx_09_fifo_data[10] +.sym 13387 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 13388 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13389 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 13390 io_ctrl_ins.mixer_en_state +.sym 13392 w_rx_09_fifo_data[4] +.sym 13404 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 13406 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 13410 i_sck$SB_IO_IN +.sym 13412 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 13415 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 13417 w_lvds_rx_24_d1 +.sym 13418 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 13419 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 13425 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 13428 i_ss_SB_LUT4_I3_O +.sym 13429 w_lvds_rx_24_d0 +.sym 13430 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 13437 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 13440 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 13449 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 13454 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 13465 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 13470 w_lvds_rx_24_d1 +.sym 13472 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 13473 w_lvds_rx_24_d0 +.sym 13478 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 13479 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 13480 i_ss_SB_LUT4_I3_O +.sym 13481 i_sck$SB_IO_IN +.sym 13485 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13487 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 13488 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13489 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 13495 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 13496 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 13497 w_tx_fifo_pulled_data[14] +.sym 13498 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 13499 w_rx_fifo_push +.sym 13500 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 13502 w_rx_data[0] +.sym 13503 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 13504 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 13506 w_rx_fifo_push +.sym 13507 i_rst_b$SB_IO_IN +.sym 13508 r_counter +.sym 13509 tx_fifo.rd_addr_gray_wr_r[7] +.sym 13511 i_mosi$SB_IO_IN +.sym 13512 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13513 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 13514 i_ss_SB_LUT4_I3_O +.sym 13515 w_tx_fifo_full +.sym 13516 spi_if_ins.w_rx_data[6] +.sym 13517 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 13518 $PACKER_VCC_NET +.sym 13524 r_counter +.sym 13526 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 13527 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 13528 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 13529 channel +.sym 13530 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 13533 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 13534 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 13535 tx_fifo.rd_addr_gray_wr_r[1] +.sym 13536 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 13538 i_ss$SB_IO_IN +.sym 13539 w_rx_24_fifo_data[4] +.sym 13542 spi_if_ins.spi.r_rx_byte[3] +.sym 13544 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 13545 tx_fifo.rd_addr_gray_wr_r[2] +.sym 13546 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 13549 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 13550 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 13552 w_rx_09_fifo_data[4] +.sym 13557 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 13558 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 13559 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 13560 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 13564 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 13565 i_ss$SB_IO_IN +.sym 13571 spi_if_ins.spi.r_rx_byte[3] +.sym 13576 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 13581 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 13582 tx_fifo.rd_addr_gray_wr_r[2] +.sym 13583 tx_fifo.rd_addr_gray_wr_r[1] +.sym 13584 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 13594 channel +.sym 13595 w_rx_24_fifo_data[4] +.sym 13596 w_rx_09_fifo_data[4] +.sym 13599 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 13600 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 13602 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 13603 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 13604 r_counter +.sym 13606 w_tx_data_sys[6] +.sym 13608 w_tx_data_sys[7] +.sym 13609 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 13610 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 13611 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] +.sym 13613 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 13622 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 13623 tx_fifo.rd_addr[5] +.sym 13630 i_rst_b_SB_LUT4_I3_O +.sym 13631 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 13632 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 13633 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 13634 r_counter +.sym 13635 i_button_SB_LUT4_I2_I1[0] +.sym 13636 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13638 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 13639 w_rx_fifo_data[4] +.sym 13640 lvds_rx_09_inst.r_phase_count[0] +.sym 13649 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13650 w_ioc[2] +.sym 13652 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13654 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 13656 w_rx_09_fifo_data[8] +.sym 13660 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 13662 w_rx_09_fifo_data[24] +.sym 13666 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 13667 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 13668 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 13671 w_rx_09_fifo_data[26] +.sym 13674 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 13676 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13678 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 13681 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13682 w_rx_09_fifo_data[24] +.sym 13686 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13687 w_rx_09_fifo_data[8] +.sym 13692 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 13695 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 13699 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 13701 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 13704 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 13705 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 13706 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13707 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13710 w_rx_09_fifo_data[26] +.sym 13712 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13722 w_ioc[2] +.sym 13724 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 13726 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 13727 lvds_clock_buf +.sym 13728 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 13729 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 13730 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 13731 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O +.sym 13732 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 13733 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 13734 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 13736 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 13741 tx_wr_data[13] +.sym 13742 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 13743 w_rx_09_fifo_data[28] +.sym 13744 tx_wr_data[28] +.sym 13745 lvds_tx_inst.r_tx_state +.sym 13746 w_ioc[2] +.sym 13747 tx_fifo.rd_addr[4] +.sym 13748 w_tx_data_sys[6] +.sym 13750 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 13751 w_tx_data_sys[2] +.sym 13752 tx_fifo.wr_addr[8] +.sym 13753 i_rst_b$SB_IO_IN +.sym 13754 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 13756 w_tx_fifo_pulled_data[21] +.sym 13758 w_ioc[0] +.sym 13759 w_tx_sync_type_24 +.sym 13760 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 13761 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13764 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 13771 $PACKER_VCC_NET +.sym 13774 lvds_rx_09_inst.r_phase_count[1] +.sym 13775 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 13777 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 13779 i_sck$SB_IO_IN +.sym 13783 i_mosi$SB_IO_IN +.sym 13785 $PACKER_VCC_NET +.sym 13786 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 13788 i_ss_SB_LUT4_I3_O +.sym 13792 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 13793 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 13794 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 13797 lvds_rx_09_inst.r_phase_count[0] +.sym 13798 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 13799 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 13800 lvds_rx_09_inst.r_phase_count[0] +.sym 13802 $nextpnr_ICESTORM_LC_12$O +.sym 13804 lvds_rx_09_inst.r_phase_count[0] +.sym 13808 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 13810 lvds_rx_09_inst.r_phase_count[1] +.sym 13811 $PACKER_VCC_NET +.sym 13812 lvds_rx_09_inst.r_phase_count[0] +.sym 13815 $PACKER_VCC_NET +.sym 13816 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 13818 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 13822 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 13823 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 13830 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 13833 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 13834 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 13835 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 13836 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 13848 i_mosi$SB_IO_IN +.sym 13849 i_ss_SB_LUT4_I3_O +.sym 13850 i_sck$SB_IO_IN +.sym 13852 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 13853 w_tx_sync_type_24 +.sym 13854 sys_ctrl_ins.tx_sample_gap[3] +.sym 13856 w_tx_sync_type_09 +.sym 13857 sys_ctrl_ins.tx_sample_gap[1] +.sym 13858 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 13859 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13860 w_fetch +.sym 13863 w_fetch +.sym 13864 w_ioc[4] +.sym 13865 w_ioc[3] +.sym 13866 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 13867 w_tx_fifo_pull +.sym 13868 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 13869 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 13870 tx_wr_data[25] +.sym 13871 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 13873 tx_fifo.wr_addr[2] +.sym 13874 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 13875 $PACKER_VCC_NET +.sym 13876 w_tx_data_sys[4] +.sym 13877 i_rst_b$SB_IO_IN +.sym 13878 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 13880 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 13881 w_rx_sync_type_09 +.sym 13882 w_tx_data_sys[0] +.sym 13884 w_cs[0] +.sym 13885 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 13886 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 13887 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 13893 w_rx_sync_type_09 +.sym 13894 w_rx_sync_type_24 +.sym 13895 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O +.sym 13899 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13906 i_rst_b_SB_LUT4_I3_O +.sym 13907 sys_ctrl_ins.tx_sample_gap[0] +.sym 13909 r_counter +.sym 13911 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 13912 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 13916 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13919 sys_ctrl_ins.tx_sample_gap[3] +.sym 13922 sys_ctrl_ins.tx_sample_gap[1] +.sym 13926 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13929 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 13932 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 13935 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 13939 w_rx_sync_type_24 +.sym 13940 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13944 sys_ctrl_ins.tx_sample_gap[3] +.sym 13945 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13950 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13952 w_rx_sync_type_09 +.sym 13957 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13959 sys_ctrl_ins.tx_sample_gap[1] +.sym 13970 sys_ctrl_ins.tx_sample_gap[0] +.sym 13971 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 13972 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O +.sym 13973 r_counter +.sym 13974 i_rst_b_SB_LUT4_I3_O +.sym 13975 i_button_SB_LUT4_I2_I1[1] +.sym 13976 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 13977 w_cs[1] +.sym 13978 w_rx_data[6] +.sym 13979 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 13980 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 13981 w_rx_data[5] +.sym 13982 w_rx_data[7] +.sym 13987 tx_fifo.wr_addr[3] +.sym 13988 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 13989 w_tx_data_sys[1] +.sym 13990 w_rx_data[2] +.sym 13991 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 13992 w_rx_data[3] +.sym 13993 tx_fifo.wr_addr[3] +.sym 13994 tx_fifo.wr_addr[5] +.sym 13995 w_rx_data[2] +.sym 13996 w_rx_data[0] +.sym 13998 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 13999 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 14000 r_counter +.sym 14003 i_rst_b$SB_IO_IN +.sym 14004 spi_if_ins.w_rx_data[6] +.sym 14005 tx_fifo.rd_addr_gray_wr_r[7] +.sym 14007 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 14008 w_ioc[1] +.sym 14009 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 14016 r_counter +.sym 14017 tx_fifo.rd_addr_gray_wr_r[4] +.sym 14019 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 14020 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 14025 i_rst_b$SB_IO_IN +.sym 14027 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 14029 tx_fifo.rd_addr_gray_wr_r[1] +.sym 14034 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 14035 w_rx_data[4] +.sym 14036 w_fetch +.sym 14037 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 14038 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 14039 w_rx_data[0] +.sym 14042 w_cs[1] +.sym 14043 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 14045 i_rst_b_SB_LUT4_I3_O +.sym 14046 w_rx_data[5] +.sym 14050 w_rx_data[4] +.sym 14055 w_rx_data[5] +.sym 14061 w_fetch +.sym 14063 i_rst_b$SB_IO_IN +.sym 14064 w_cs[1] +.sym 14068 tx_fifo.rd_addr_gray_wr_r[1] +.sym 14069 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 14073 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 14074 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 14075 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 14086 w_rx_data[0] +.sym 14091 tx_fifo.rd_addr_gray_wr_r[4] +.sym 14092 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 14094 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 14095 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 14096 r_counter +.sym 14097 i_rst_b_SB_LUT4_I3_O +.sym 14099 spi_if_ins.spi.SCKr[0] +.sym 14102 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 14103 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 14105 spi_if_ins.spi.SCKr[1] +.sym 14110 i_button_SB_LUT4_I2_I1[0] +.sym 14111 tx_fifo.rd_addr_gray_wr_r[4] +.sym 14113 w_rx_data[6] +.sym 14115 w_rx_data[7] +.sym 14116 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 14117 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 14120 w_load +.sym 14123 i_rst_b$SB_IO_IN +.sym 14126 r_counter +.sym 14132 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 14140 w_ioc[2] +.sym 14141 w_ioc[3] +.sym 14142 tx_fifo.rd_addr_gray_wr_r[8] +.sym 14145 spi_if_ins.w_rx_data[1] +.sym 14148 w_ioc[2] +.sym 14149 spi_if_ins.w_rx_data[0] +.sym 14152 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 14153 w_ioc[4] +.sym 14155 r_counter +.sym 14157 w_ioc[1] +.sym 14166 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 14169 w_ioc[0] +.sym 14170 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 14172 w_ioc[2] +.sym 14173 w_ioc[4] +.sym 14174 w_ioc[3] +.sym 14178 w_ioc[4] +.sym 14179 w_ioc[1] +.sym 14180 w_ioc[0] +.sym 14181 w_ioc[3] +.sym 14184 spi_if_ins.w_rx_data[1] +.sym 14198 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 14204 tx_fifo.rd_addr_gray_wr_r[8] +.sym 14205 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 14211 spi_if_ins.w_rx_data[0] +.sym 14214 w_ioc[4] +.sym 14216 w_ioc[2] +.sym 14217 w_ioc[3] +.sym 14218 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 14219 r_counter +.sym 14221 r_counter +.sym 14239 tx_fifo.wr_addr[8] +.sym 14240 tx_fifo.wr_addr[5] +.sym 14243 w_cs[0] .sym 14249 i_rst_b$SB_IO_IN -.sym 14276 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 14301 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 14254 w_ioc[0] +.sym 14268 i_ss$SB_IO_IN +.sym 14271 i_sck$SB_IO_IN +.sym 14272 spi_if_ins.spi.r_rx_bit_count[2] +.sym 14273 spi_if_ins.spi.r_rx_bit_count[0] +.sym 14275 i_ss$SB_IO_IN +.sym 14283 spi_if_ins.spi.r_rx_bit_count[1] +.sym 14294 $nextpnr_ICESTORM_LC_9$O +.sym 14297 spi_if_ins.spi.r_rx_bit_count[0] +.sym 14300 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 14303 spi_if_ins.spi.r_rx_bit_count[1] +.sym 14308 spi_if_ins.spi.r_rx_bit_count[2] +.sym 14310 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 14316 spi_if_ins.spi.r_rx_bit_count[0] +.sym 14325 spi_if_ins.spi.r_rx_bit_count[1] +.sym 14328 spi_if_ins.spi.r_rx_bit_count[0] +.sym 14331 spi_if_ins.spi.r_rx_bit_count[0] +.sym 14332 spi_if_ins.spi.r_rx_bit_count[1] +.sym 14333 i_ss$SB_IO_IN +.sym 14334 spi_if_ins.spi.r_rx_bit_count[2] +.sym 14342 i_sck$SB_IO_IN +.sym 14343 i_ss$SB_IO_IN .sym 14344 i_rst_b$SB_IO_IN -.sym 14360 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 14355 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 14359 r_counter +.sym 14360 o_shdn_tx_lna$SB_IO_OUT .sym 14365 i_rst_b$SB_IO_IN -.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14399 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14418 i_rst_b_SB_LUT4_I3_O +.sym 14373 i_rst_b$SB_IO_IN .sym 14419 w_smi_data_output[3] .sym 14421 w_smi_data_direction .sym 14425 $PACKER_VCC_NET -.sym 14430 $PACKER_VCC_NET -.sym 14431 w_smi_data_direction -.sym 14433 i_rst_b_SB_LUT4_I3_O -.sym 14434 w_smi_data_output[3] -.sym 14445 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 14446 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 14447 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14448 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 14449 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14450 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14451 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14456 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14460 i_rst_b$SB_IO_IN -.sym 14478 i_ss$SB_IO_IN -.sym 14487 tx_fifo.wr_addr_gray_rd[9] -.sym 14489 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14504 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 14505 tx_fifo.wr_addr_gray[3] -.sym 14506 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 14508 smi_ctrl_ins.int_cnt_rx[4] -.sym 14510 i_rst_b$SB_IO_IN -.sym 14511 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 14512 tx_fifo.wr_addr[9] -.sym 14513 smi_ctrl_ins.int_cnt_rx[3] -.sym 14515 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14516 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14519 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 14520 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14527 tx_fifo.wr_addr[9] -.sym 14532 tx_fifo.wr_addr_gray_rd[9] -.sym 14538 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14539 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14546 tx_fifo.wr_addr_gray[3] -.sym 14551 i_rst_b$SB_IO_IN -.sym 14555 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 14557 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 14562 smi_ctrl_ins.int_cnt_rx[3] -.sym 14563 i_rst_b$SB_IO_IN -.sym 14564 smi_ctrl_ins.int_cnt_rx[4] -.sym 14566 lvds_clock_$glb_clk -.sym 14568 o_smi_write_req$SB_IO_OUT -.sym 14572 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 14573 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14574 tx_fifo.wr_addr[9] -.sym 14575 tx_fifo.wr_addr_gray[3] -.sym 14576 tx_fifo.wr_addr[5] -.sym 14577 tx_fifo.wr_addr[3] -.sym 14578 tx_fifo.wr_addr[8] -.sym 14579 tx_fifo.wr_addr[7] -.sym 14587 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14589 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14592 tx_fifo.wr_addr[1] -.sym 14594 tx_fifo.wr_addr_gray_rd[3] -.sym 14623 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 14626 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 14631 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 14632 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14633 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14635 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14636 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14637 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14651 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14659 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 14660 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14661 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14663 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14664 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14669 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 14670 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14671 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 14674 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 14675 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 14677 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14683 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 14684 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14688 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 14690 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14694 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 14697 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 14700 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14703 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 14715 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 14719 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 14724 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14725 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 14727 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14728 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14729 lvds_clock_$glb_clk -.sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14731 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] -.sym 14732 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 14733 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14734 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 14735 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14736 w_smi_data_output[4] -.sym 14737 w_smi_data_output[3] -.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 14748 w_rx_fifo_pulled_data[15] -.sym 14750 w_rx_fifo_pulled_data[13] -.sym 14752 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14755 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 14757 tx_fifo.wr_addr[1] -.sym 14758 tx_fifo.rd_addr_gray_wr[2] -.sym 14760 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14762 tx_fifo.rd_addr[6] -.sym 14763 tx_fifo.rd_addr[1] -.sym 14764 i_sck$SB_IO_IN -.sym 14766 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14772 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 14773 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14774 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 14776 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14780 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 14781 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 14782 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14783 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14784 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 14787 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 14788 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 14789 tx_fifo.rd_addr[1] -.sym 14791 smi_ctrl_ins.int_cnt_rx[3] -.sym 14792 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 14794 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 14795 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14797 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14798 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14799 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 14802 smi_ctrl_ins.int_cnt_rx[4] -.sym 14805 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14806 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14807 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 14808 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14811 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 14812 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14813 tx_fifo.rd_addr[1] -.sym 14814 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 14818 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14823 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 14824 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 14826 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 14830 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 14838 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 14842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14843 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 14844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14847 smi_ctrl_ins.int_cnt_rx[4] -.sym 14848 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 14849 smi_ctrl_ins.int_cnt_rx[3] -.sym 14850 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 14851 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 14852 lvds_clock_$glb_clk -.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14855 tx_fifo.rd_addr_gray_wr[9] -.sym 14856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 14857 tx_fifo.rd_addr_gray_wr[7] -.sym 14858 tx_fifo.rd_addr_gray_wr[4] -.sym 14859 tx_fifo.rd_addr_gray_wr[1] -.sym 14860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 14861 tx_fifo.rd_addr_gray_wr_r[1] -.sym 14865 w_fetch -.sym 14867 w_smi_data_output[3] -.sym 14868 rx_fifo.mem_q.0.3_WDATA_3 -.sym 14870 rx_fifo.wr_addr[0] -.sym 14874 rx_fifo.wr_addr[8] -.sym 14875 i_rst_b$SB_IO_IN -.sym 14876 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 14881 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 14885 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 14886 i_ss$SB_IO_IN -.sym 14889 tx_fifo.rd_addr_gray_wr[9] -.sym 14897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 14900 smi_ctrl_ins.int_cnt_rx[4] -.sym 14902 smi_ctrl_ins.int_cnt_rx[3] -.sym 14906 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14907 tx_fifo.rd_addr[5] -.sym 14908 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 14910 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14911 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14912 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14914 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14918 tx_fifo.rd_addr_gray_wr_r[1] -.sym 14920 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 14921 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14922 tx_fifo.rd_addr[6] -.sym 14925 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14926 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 14928 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 14929 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14930 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 14931 tx_fifo.rd_addr_gray_wr_r[1] -.sym 14934 smi_ctrl_ins.int_cnt_rx[3] -.sym 14935 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 14430 w_smi_data_output[3] +.sym 14433 $PACKER_VCC_NET +.sym 14435 w_smi_data_direction +.sym 14444 smi_ctrl_ins.d_q1[7] +.sym 14445 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 14446 rx_fifo.wr_addr_gray_rd[4] +.sym 14447 w_smi_read_req_SB_LUT4_I1_I2[1] +.sym 14448 rx_fifo.wr_addr_gray_rd[9] +.sym 14449 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 14450 rx_fifo.wr_addr_gray_rd[6] +.sym 14451 rx_fifo.wr_addr_gray_rd_r[2] +.sym 14457 w_smi_data_direction +.sym 14460 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 14478 w_smi_data_input[5] +.sym 14488 lvds_tx_inst.frame_boundary +.sym 14495 lvds_tx_inst.r_sync_count[1] +.sym 14496 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 14499 w_smi_data_direction +.sym 14503 $PACKER_VCC_NET +.sym 14506 i_rst_b_SB_LUT4_I3_O +.sym 14511 lvds_tx_inst.r_sync_count[0] +.sym 14525 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 14526 lvds_tx_inst.r_sync_count[0] +.sym 14527 $PACKER_VCC_NET +.sym 14528 lvds_tx_inst.r_sync_count[1] +.sym 14531 w_smi_data_direction +.sym 14565 lvds_tx_inst.frame_boundary +.sym 14566 lvds_clock_buf +.sym 14567 i_rst_b_SB_LUT4_I3_O +.sym 14568 i_smi_swe_srw$SB_IO_IN +.sym 14573 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 14574 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 14575 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 14576 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 14577 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 14578 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 14579 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 14584 rx_fifo.rd_addr[3] +.sym 14587 rx_fifo.wr_addr_gray_rd[2] +.sym 14588 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 14592 w_rx_fifo_push +.sym 14594 rx_fifo.wr_addr[7] +.sym 14596 i_smi_swe_srw$SB_IO_IN +.sym 14600 i_rst_b_SB_LUT4_I3_O +.sym 14601 w_smi_data_input[7] +.sym 14604 w_rx_fifo_pull +.sym 14610 rx_fifo.rd_addr[9] +.sym 14612 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 14614 w_smi_data_output[0] +.sym 14617 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 14622 smi_ctrl_ins.soe_and_reset +.sym 14626 r_counter +.sym 14627 rx_fifo.wr_addr_gray[6] +.sym 14628 w_smi_data_direction +.sym 14632 w_rx_24_fifo_data[6] +.sym 14633 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 14634 rx_fifo.wr_addr[9] +.sym 14636 rx_fifo.wr_addr_gray[4] +.sym 14643 $PACKER_VCC_NET +.sym 14650 smi_ctrl_ins.r_fifo_pull_1 +.sym 14651 w_rx_fifo_pull +.sym 14652 w_smi_read_req_SB_LUT4_I1_I2[1] +.sym 14653 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 14654 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 14655 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 14656 w_rx_data[0] +.sym 14657 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 14658 r_counter +.sym 14659 rx_fifo.rd_addr[8] +.sym 14660 w_smi_read_req +.sym 14662 smi_ctrl_ins.r_fifo_pull +.sym 14664 rx_fifo.wr_addr_gray_rd_r[2] +.sym 14665 rx_fifo.rd_addr[9] +.sym 14666 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 14667 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 14668 smi_ctrl_ins.int_cnt_rx[3] +.sym 14669 i_rst_b_SB_LUT4_I3_O +.sym 14671 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 14672 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 14673 w_smi_read_req_SB_LUT4_I1_I2[2] +.sym 14674 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 14675 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 14676 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 14679 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 14680 smi_ctrl_ins.int_cnt_rx[4] +.sym 14682 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 14683 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 14684 rx_fifo.rd_addr[9] +.sym 14685 rx_fifo.rd_addr[8] +.sym 14688 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 14689 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 14690 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 14691 w_rx_fifo_pull +.sym 14694 smi_ctrl_ins.r_fifo_pull +.sym 14695 smi_ctrl_ins.r_fifo_pull_1 +.sym 14696 w_smi_read_req +.sym 14700 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 14702 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 14703 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 14706 smi_ctrl_ins.int_cnt_rx[4] +.sym 14707 smi_ctrl_ins.int_cnt_rx[3] +.sym 14708 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 14709 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 14712 w_rx_data[0] +.sym 14718 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 14720 rx_fifo.wr_addr_gray_rd_r[2] +.sym 14721 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 14724 w_smi_read_req_SB_LUT4_I1_I2[2] +.sym 14726 w_smi_read_req_SB_LUT4_I1_I2[1] +.sym 14727 w_smi_read_req +.sym 14728 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 14729 r_counter +.sym 14730 i_rst_b_SB_LUT4_I3_O +.sym 14731 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 14732 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 14733 w_rx_24_fifo_data[12] +.sym 14734 w_rx_24_fifo_data[8] +.sym 14735 w_rx_24_fifo_data[24] +.sym 14736 w_rx_24_fifo_data[10] +.sym 14737 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 14738 w_rx_24_fifo_data[22] +.sym 14743 rx_fifo.rd_addr[0] +.sym 14744 w_rx_fifo_data[3] +.sym 14747 rx_fifo.rd_addr[8] +.sym 14749 w_rx_fifo_pull +.sym 14752 w_rx_fifo_pulled_data[3] +.sym 14756 r_counter +.sym 14757 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 14758 w_rx_24_fifo_data[10] +.sym 14759 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[1] +.sym 14760 w_rx_fifo_pulled_data[0] +.sym 14762 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 14763 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 14764 r_counter +.sym 14765 rx_fifo.rd_addr_gray_wr_r[2] +.sym 14766 w_rx_fifo_pulled_data[24] +.sym 14774 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[1] +.sym 14775 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[1] +.sym 14776 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 14777 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 14779 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[1] +.sym 14781 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[0] +.sym 14782 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[0] +.sym 14783 w_tx_fsm_state[0] +.sym 14784 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[3] +.sym 14785 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[1] +.sym 14787 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[3] +.sym 14788 smi_ctrl_ins.soe_and_reset +.sym 14791 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 14792 i_rst_b_SB_LUT4_I3_O +.sym 14793 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[0] +.sym 14794 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] +.sym 14795 smi_ctrl_ins.int_cnt_rx[4] +.sym 14797 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[3] +.sym 14798 w_tx_fsm_state[1] +.sym 14799 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[3] +.sym 14800 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 14801 smi_ctrl_ins.int_cnt_rx[3] +.sym 14802 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] +.sym 14803 smi_ctrl_ins.int_cnt_rx[4] +.sym 14805 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[3] +.sym 14806 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[0] +.sym 14807 smi_ctrl_ins.int_cnt_rx[4] +.sym 14808 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[1] +.sym 14811 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[0] +.sym 14812 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[1] +.sym 14813 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[3] +.sym 14814 smi_ctrl_ins.int_cnt_rx[4] +.sym 14817 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[3] +.sym 14818 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[1] +.sym 14819 smi_ctrl_ins.int_cnt_rx[4] +.sym 14820 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 14823 smi_ctrl_ins.int_cnt_rx[4] +.sym 14824 smi_ctrl_ins.int_cnt_rx[3] +.sym 14825 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 14826 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 14829 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[0] +.sym 14830 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] +.sym 14831 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] +.sym 14832 smi_ctrl_ins.int_cnt_rx[4] +.sym 14835 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 14836 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[3] +.sym 14837 smi_ctrl_ins.int_cnt_rx[4] +.sym 14838 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[1] +.sym 14841 w_tx_fsm_state[0] +.sym 14842 w_tx_fsm_state[1] +.sym 14848 smi_ctrl_ins.int_cnt_rx[3] +.sym 14850 smi_ctrl_ins.int_cnt_rx[4] +.sym 14852 smi_ctrl_ins.soe_and_reset +.sym 14853 i_rst_b_SB_LUT4_I3_O +.sym 14854 rx_fifo.wr_addr_gray[6] +.sym 14855 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[3] +.sym 14857 rx_fifo.wr_addr[9] +.sym 14858 rx_fifo.wr_addr_gray[4] +.sym 14859 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 14860 w_rx_fifo_data[26] +.sym 14861 o_smi_read_req$SB_IO_OUT +.sym 14866 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 14867 rx_fifo.rd_addr_gray[5] +.sym 14868 w_rx_24_fifo_data[20] +.sym 14869 smi_ctrl_ins.soe_and_reset +.sym 14871 w_tx_fsm_state[0] +.sym 14872 w_smi_data_output[5] +.sym 14875 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 14876 rx_fifo.rd_addr_gray_wr_r[0] +.sym 14877 w_rx_24_fifo_data[12] +.sym 14878 i_rst_b_SB_LUT4_I3_O +.sym 14879 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[0] +.sym 14881 w_rx_fifo_pulled_data[27] +.sym 14882 r_counter +.sym 14884 w_tx_fsm_state[1] +.sym 14885 w_tx_fifo_full +.sym 14887 r_counter +.sym 14889 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 14895 smi_ctrl_ins.soe_and_reset +.sym 14899 i_rst_b_SB_LUT4_I3_O +.sym 14900 w_rx_fifo_pulled_data[16] +.sym 14902 smi_ctrl_ins.int_cnt_rx[4] +.sym 14903 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 14904 w_rx_fifo_pulled_data[14] +.sym 14908 smi_ctrl_ins.int_cnt_rx[3] +.sym 14910 smi_ctrl_ins.int_cnt_rx[4] +.sym 14914 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 14917 w_rx_fifo_pulled_data[22] +.sym 14920 w_rx_fifo_pulled_data[0] +.sym 14921 w_rx_fifo_pulled_data[13] +.sym 14922 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 14926 w_rx_fifo_pulled_data[24] +.sym 14930 w_rx_fifo_pulled_data[14] +.sym 14935 smi_ctrl_ins.int_cnt_rx[3] .sym 14936 smi_ctrl_ins.int_cnt_rx[4] -.sym 14937 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 14941 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 14943 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 14946 tx_fifo.rd_addr[5] -.sym 14947 tx_fifo.rd_addr[6] -.sym 14948 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 14959 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 14961 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 14974 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 14975 r_counter_$glb_clk -.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14977 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 14979 spi_if_ins.spi.r_rx_done -.sym 14980 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 14981 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 14982 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 14983 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 14984 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 14992 w_rx_fifo_pulled_data[12] -.sym 14993 $PACKER_VCC_NET -.sym 14994 rx_fifo.rd_addr[2] -.sym 14995 rx_fifo.wr_addr[1] -.sym 14996 rx_fifo.rd_addr[1] -.sym 14997 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 15008 rx_fifo.wr_addr[4] -.sym 15020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 15021 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 15022 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15023 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 15024 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 15026 tx_fifo.wr_addr[1] -.sym 15038 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 15045 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 15053 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 15057 tx_fifo.wr_addr[1] -.sym 15063 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 15065 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 15071 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 15075 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 15093 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 15096 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 15098 r_counter_$glb_clk -.sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15100 spi_if_ins.spi.r3_rx_done -.sym 15102 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 15104 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 15105 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 15106 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 15107 spi_if_ins.spi.r2_rx_done -.sym 15111 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 15112 rx_fifo.mem_i.0.0_WDATA_3 -.sym 15113 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 15114 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 15115 rx_fifo.wr_addr[2] -.sym 15116 rx_fifo.wr_addr[1] -.sym 15118 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 15120 rx_fifo.mem_i.0.0_WDATA_2 -.sym 15126 $PACKER_VCC_NET -.sym 15132 w_tx_fifo_full -.sym 15133 i_ss$SB_IO_IN -.sym 15135 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15144 tx_fifo.wr_addr_gray[2] -.sym 15145 tx_fifo.wr_addr_gray[5] -.sym 15148 tx_fifo.wr_addr_gray[7] -.sym 15150 tx_fifo.wr_addr_gray[0] -.sym 15151 tx_fifo.wr_addr_gray_rd[5] -.sym 15174 tx_fifo.wr_addr_gray[0] -.sym 15186 tx_fifo.wr_addr_gray[5] -.sym 15204 tx_fifo.wr_addr_gray_rd[5] -.sym 15213 tx_fifo.wr_addr_gray[7] -.sym 15218 tx_fifo.wr_addr_gray[2] -.sym 15221 lvds_clock_$glb_clk -.sym 15225 tx_fifo.rd_addr_gray_wr[0] -.sym 15226 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 15235 rx_fifo.rd_addr[9] -.sym 15236 rx_fifo.rd_addr[1] -.sym 15238 rx_fifo.mem_i.0.0_WDATA -.sym 15244 rx_fifo.rd_addr[2] -.sym 15250 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15251 tx_fifo.rd_addr[1] -.sym 15255 w_tx_data_smi[2] -.sym 15258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15277 tx_fifo.rd_addr[1] -.sym 15291 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 15311 tx_fifo.rd_addr[1] -.sym 15343 lvds_tx_inst.r_pulled_SB_LUT4_I3_O -.sym 15344 lvds_clock_$glb_clk -.sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 15346 w_tx_data_smi[1] -.sym 15347 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] -.sym 15348 w_tx_data_smi[2] -.sym 15349 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 15350 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 15351 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15353 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 15358 rx_fifo.wr_addr[5] -.sym 15361 rx_fifo.wr_addr[4] -.sym 15363 rx_fifo.wr_addr[0] -.sym 15366 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 15368 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 15371 w_fetch -.sym 15379 w_tx_data_smi[1] -.sym 15380 $PACKER_VCC_NET -.sym 15381 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15391 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15392 spi_if_ins.r_tx_data_valid -.sym 15396 $PACKER_VCC_NET -.sym 15400 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15403 i_ss$SB_IO_IN -.sym 15404 $PACKER_VCC_NET -.sym 15405 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15413 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15414 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15419 $nextpnr_ICESTORM_LC_9$O -.sym 15422 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15425 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 15427 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15428 $PACKER_VCC_NET -.sym 15433 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15434 $PACKER_VCC_NET -.sym 15435 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 15439 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15440 $PACKER_VCC_NET -.sym 15441 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15444 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15451 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 15452 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 15453 spi_if_ins.spi.r_tx_bit_count[0] -.sym 15462 spi_if_ins.r_tx_data_valid -.sym 15463 i_ss$SB_IO_IN -.sym 15466 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 15467 r_counter_$glb_clk -.sym 15468 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 15469 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 15470 spi_if_ins.spi.r_tx_byte[4] -.sym 15471 spi_if_ins.spi.r_tx_byte[2] -.sym 15472 spi_if_ins.spi.r_tx_byte[3] -.sym 15473 spi_if_ins.spi.r_tx_byte[6] -.sym 15474 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 15475 spi_if_ins.spi.r_tx_byte[1] -.sym 15476 spi_if_ins.spi.r_tx_byte[0] -.sym 15485 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15486 spi_if_ins.r_tx_byte[7] -.sym 15489 rx_fifo.rd_addr[1] -.sym 15490 rx_fifo.wr_addr[1] -.sym 15491 $PACKER_VCC_NET -.sym 15492 rx_fifo.wr_addr[2] -.sym 15493 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15494 spi_if_ins.r_tx_byte[0] -.sym 15497 w_fetch -.sym 15498 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 15500 spi_if_ins.r_tx_byte[3] -.sym 15502 spi_if_ins.r_tx_byte[1] -.sym 15503 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15512 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15517 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 15521 i_rst_b$SB_IO_IN -.sym 15523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 15526 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15533 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15534 w_smi_read_req -.sym 15537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15543 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15551 w_smi_read_req -.sym 15562 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 15564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15567 i_rst_b$SB_IO_IN -.sym 15568 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 15569 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15570 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 15581 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15586 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 15587 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 15588 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15589 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15590 r_counter_$glb_clk -.sym 15591 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15592 w_ioc[2] -.sym 15593 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15595 i_button_SB_LUT4_I0_O[1] -.sym 15596 w_ioc[4] -.sym 15597 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 15598 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15599 w_ioc[3] -.sym 15603 i_rst_b$SB_IO_IN -.sym 15604 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15607 i_rst_b$SB_IO_IN -.sym 15608 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15613 spi_if_ins.r_tx_byte[7] -.sym 15615 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 15617 spi_if_ins.r_tx_byte[2] -.sym 15618 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 15619 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 15620 w_rx_data[6] -.sym 15622 smi_ctrl_ins.r_dir_SB_DFFER_Q_E -.sym 15624 spi_if_ins.r_tx_byte[4] -.sym 15625 w_fetch -.sym 15626 w_rx_data[2] -.sym 15627 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15635 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15636 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15637 spi_if_ins.w_rx_data[2] -.sym 15639 spi_if_ins.w_rx_data[6] -.sym 15642 w_cs[2] -.sym 15643 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 15644 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15645 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15646 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15647 w_fetch -.sym 15649 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15656 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 15659 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 15663 i_rst_b$SB_IO_IN -.sym 15664 i_rst_b$SB_IO_IN -.sym 15667 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 15668 i_rst_b$SB_IO_IN -.sym 15669 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 15673 spi_if_ins.w_rx_data[2] -.sym 15678 i_rst_b$SB_IO_IN -.sym 15679 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 15680 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15681 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15684 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15686 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15687 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15697 i_rst_b$SB_IO_IN -.sym 15698 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15699 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15704 spi_if_ins.w_rx_data[6] -.sym 15708 w_fetch -.sym 15709 w_cs[2] -.sym 15710 i_rst_b$SB_IO_IN -.sym 15711 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15712 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15713 r_counter_$glb_clk -.sym 15715 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 15716 spi_if_ins.r_tx_byte[5] -.sym 15717 spi_if_ins.r_tx_byte[4] -.sym 15718 spi_if_ins.r_tx_byte[3] -.sym 15719 spi_if_ins.r_tx_byte[1] -.sym 15721 i_button_SB_LUT4_I0_I3[2] -.sym 15722 spi_if_ins.r_tx_byte[6] -.sym 15727 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 15728 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15729 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15733 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15737 w_rx_fifo_full -.sym 15740 i_button_SB_LUT4_I0_I3[3] -.sym 15741 i_button_SB_LUT4_I0_O[1] -.sym 15742 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15743 w_tx_data_smi[2] -.sym 15744 i_button_SB_LUT4_I0_I3[2] -.sym 15745 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15746 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 15747 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15748 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 15749 io_pmod_out[1]$SB_IO_OUT -.sym 15757 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15758 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15762 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15765 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15766 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 15770 w_load -.sym 15773 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] -.sym 15774 w_cs[0] -.sym 15775 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15780 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 15783 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 15784 i_rst_b$SB_IO_IN -.sym 15785 w_fetch -.sym 15789 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15790 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15791 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15792 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 15795 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 15796 w_fetch -.sym 15797 w_load -.sym 15798 w_cs[0] -.sym 15801 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 15819 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] -.sym 15820 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15821 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15826 i_rst_b$SB_IO_IN -.sym 15828 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 15831 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15832 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15833 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] -.sym 15835 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15836 r_counter_$glb_clk -.sym 15838 r_tx_data[5] -.sym 15839 r_tx_data[1] -.sym 15840 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 15841 r_tx_data[6] -.sym 15842 i_button_SB_LUT4_I0_O[2] -.sym 15843 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 15844 r_tx_data[4] -.sym 15845 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15846 o_led1_SB_DFFER_Q_E -.sym 15850 w_cs[3] -.sym 15851 i_button_SB_LUT4_I0_I3[2] -.sym 15854 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 15855 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 15856 w_cs[2] -.sym 15858 w_load -.sym 15859 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 15862 o_led0_SB_LUT4_I1_O[1] -.sym 15863 w_cs[0] -.sym 15865 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15866 i_button_SB_LUT4_I0_I3[0] -.sym 15867 o_rx_h_tx_l$SB_IO_OUT -.sym 15869 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 15870 i_button$SB_IO_IN -.sym 15871 w_fetch -.sym 15872 w_tx_data_smi[1] -.sym 15873 o_led0_SB_LUT4_I1_O[3] -.sym 15879 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 15880 w_tx_data_io[5] -.sym 15881 w_cs[0] -.sym 15882 w_cs[1] -.sym 15883 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15887 w_cs[2] -.sym 15888 w_load -.sym 15890 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 15891 o_rx_h_tx_l$SB_IO_OUT -.sym 15893 i_button_SB_LUT4_I0_I3[2] -.sym 15895 w_fetch -.sym 15897 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15898 i_rst_b$SB_IO_IN -.sym 15899 i_button_SB_LUT4_I0_O[2] -.sym 15900 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 15901 i_button_SB_LUT4_I0_O[1] -.sym 15902 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15906 w_cs[3] -.sym 15907 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15908 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 15910 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15912 i_button_SB_LUT4_I0_O[1] -.sym 15913 o_rx_h_tx_l$SB_IO_OUT -.sym 15914 i_button_SB_LUT4_I0_O[2] -.sym 15919 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 15921 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 15924 w_cs[0] -.sym 15925 w_cs[1] -.sym 15926 w_cs[3] -.sym 15927 w_cs[2] -.sym 15930 w_cs[2] -.sym 15931 w_fetch -.sym 15932 i_button_SB_LUT4_I0_I3[2] -.sym 15933 w_load -.sym 15936 w_fetch -.sym 15937 w_cs[1] -.sym 15939 i_rst_b$SB_IO_IN -.sym 15948 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 15949 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 15950 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 15951 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 15954 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 15956 w_tx_data_io[5] -.sym 15957 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15958 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 15959 r_counter_$glb_clk -.sym 15961 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] -.sym 15962 w_tx_data_io[0] -.sym 15963 o_led1_SB_LUT4_I1_O[2] -.sym 15964 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 15965 o_led0_SB_LUT4_I1_O[2] -.sym 15966 w_tx_data_io[1] -.sym 15967 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] -.sym 15968 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 15978 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 15980 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 15982 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 15984 w_load -.sym 15985 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 15991 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 15993 spi_if_ins.r_tx_byte[0] -.sym 15995 o_tr_vc1_b$SB_IO_OUT -.sym 16002 w_tx_data_io[7] -.sym 16004 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 16005 w_tx_data_io[2] -.sym 16006 i_button_SB_LUT4_I0_I3[1] -.sym 16007 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 16008 i_button_SB_LUT4_I0_I3[3] -.sym 16009 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16012 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 16013 i_button_SB_LUT4_I0_O[1] -.sym 16014 i_button_SB_LUT4_I0_I3[2] -.sym 16015 w_tx_data_smi[2] -.sym 16017 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 16018 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 16019 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 16020 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 16022 w_fetch -.sym 16023 w_cs[0] -.sym 16025 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 16026 i_button_SB_LUT4_I0_I3[0] -.sym 16029 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 16030 o_rx_h_tx_l_b$SB_IO_OUT -.sym 16031 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 16033 o_tr_vc1$SB_IO_OUT -.sym 16035 w_tx_data_io[7] -.sym 16036 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 16038 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16041 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 16042 o_tr_vc1$SB_IO_OUT -.sym 16044 i_button_SB_LUT4_I0_O[1] -.sym 16047 i_button_SB_LUT4_I0_I3[3] -.sym 16048 i_button_SB_LUT4_I0_I3[0] -.sym 16049 i_button_SB_LUT4_I0_I3[1] -.sym 16050 i_button_SB_LUT4_I0_I3[2] -.sym 16059 w_fetch -.sym 16061 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 16062 w_cs[0] -.sym 16065 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 16066 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 16067 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 16068 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 16071 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 16072 w_tx_data_io[2] -.sym 16073 w_tx_data_smi[2] -.sym 16074 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 16078 i_button_SB_LUT4_I0_O[1] -.sym 16079 o_rx_h_tx_l_b$SB_IO_OUT -.sym 16080 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 16081 io_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 16082 r_counter_$glb_clk -.sym 16084 o_tr_vc2$SB_IO_OUT -.sym 16085 o_shdn_tx_lna$SB_IO_OUT -.sym 16086 o_rx_h_tx_l$SB_IO_OUT -.sym 16087 o_tr_vc1_b$SB_IO_OUT -.sym 16088 o_rx_h_tx_l_b$SB_IO_OUT -.sym 16089 o_shdn_rx_lna$SB_IO_OUT -.sym 16090 io_ctrl_ins.mixer_en_state -.sym 16091 o_tr_vc1$SB_IO_OUT -.sym 16096 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 16098 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 16102 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 16106 i_rst_b$SB_IO_IN -.sym 16110 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 16112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 16113 spi_if_ins.r_tx_byte[2] +.sym 14940 w_rx_fifo_pulled_data[0] +.sym 14948 w_rx_fifo_pulled_data[13] +.sym 14955 w_rx_fifo_pulled_data[16] +.sym 14959 w_rx_fifo_pulled_data[24] +.sym 14966 w_rx_fifo_pulled_data[22] +.sym 14970 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 14971 smi_ctrl_ins.int_cnt_rx[3] +.sym 14972 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 14973 smi_ctrl_ins.int_cnt_rx[4] +.sym 14974 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 14975 smi_ctrl_ins.soe_and_reset +.sym 14976 i_rst_b_SB_LUT4_I3_O +.sym 14978 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 14979 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 14980 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 14981 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 14982 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 14983 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 14984 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 14985 r_counter +.sym 14988 r_counter +.sym 14989 w_tx_fsm_state[0] +.sym 14990 r_counter +.sym 14991 w_rx_fifo_data[21] +.sym 14992 rx_fifo.wr_addr[9] +.sym 14993 w_tx_fsm_state[1] +.sym 14994 o_smi_read_req$SB_IO_OUT +.sym 14995 i_rst_b$SB_IO_IN +.sym 14999 smi_ctrl_ins.soe_and_reset +.sym 15000 i_mosi$SB_IO_IN +.sym 15002 w_rx_fifo_data[16] +.sym 15003 rx_fifo.wr_addr[9] +.sym 15004 w_rx_09_fifo_data[26] +.sym 15007 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 15008 w_rx_fifo_data[18] +.sym 15010 w_rx_09_fifo_data[2] +.sym 15011 smi_ctrl_ins.soe_and_reset +.sym 15018 smi_ctrl_ins.soe_and_reset +.sym 15022 w_rx_fifo_pulled_data[29] +.sym 15023 w_rx_fifo_pulled_data[17] +.sym 15024 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 15027 w_rx_fifo_pulled_data[15] +.sym 15028 w_rx_fifo_pulled_data[3] +.sym 15037 rx_fifo.rd_addr_gray_wr_r[2] +.sym 15038 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 15039 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 15040 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 15041 w_rx_fifo_pulled_data[27] +.sym 15044 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15045 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 15047 i_rst_b_SB_LUT4_I3_O +.sym 15048 w_rx_fifo_pulled_data[23] +.sym 15051 w_rx_fifo_pulled_data[29] +.sym 15057 rx_fifo.rd_addr_gray_wr_r[2] +.sym 15058 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 15059 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15063 w_rx_fifo_pulled_data[15] +.sym 15071 w_rx_fifo_pulled_data[23] +.sym 15078 w_rx_fifo_pulled_data[17] +.sym 15083 w_rx_fifo_pulled_data[27] +.sym 15088 w_rx_fifo_pulled_data[3] +.sym 15094 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 15095 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 15096 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 15097 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 15098 smi_ctrl_ins.soe_and_reset +.sym 15099 i_rst_b_SB_LUT4_I3_O +.sym 15100 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 15101 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 15102 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15104 w_tx_data_smi[0] +.sym 15105 w_rx_fifo_data[24] +.sym 15106 w_rx_fifo_data[2] +.sym 15107 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 15108 i_rst_b$SB_IO_IN +.sym 15109 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 15111 i_rst_b$SB_IO_IN +.sym 15114 rx_fifo.wr_addr[2] +.sym 15116 rx_fifo.wr_addr[8] +.sym 15117 w_rx_fifo_push +.sym 15118 i_rst_b_SB_LUT4_I3_O +.sym 15119 tx_wr_en +.sym 15120 rx_fifo.wr_addr[5] +.sym 15121 w_rx_fifo_push +.sym 15122 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 15123 w_tx_fifo_pulled_data[26] +.sym 15124 r_counter +.sym 15125 lvds_tx_inst.r_fifo_data[14] +.sym 15126 rx_fifo.rd_addr_gray_wr_r[5] +.sym 15127 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 15128 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 15129 r_counter +.sym 15131 rx_fifo.rd_addr_gray[6] +.sym 15132 lvds_tx_inst.r_tx_state +.sym 15133 w_rx_09_fifo_data[12] +.sym 15134 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15135 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 15141 smi_ctrl_ins.soe_and_reset +.sym 15143 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 15144 rx_fifo.rd_addr_gray_wr_r[5] +.sym 15146 rx_fifo.wr_addr[0] +.sym 15148 rx_fifo.rd_addr_gray_wr_r[0] +.sym 15150 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 15151 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 15152 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 15153 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 15154 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 15155 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 15156 w_rx_fifo_full +.sym 15157 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 15158 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 15159 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 15161 i_rst_b_SB_LUT4_I3_O +.sym 15166 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 15167 rx_fifo.rd_addr_gray_wr_r[9] +.sym 15168 w_rx_fifo_pulled_data[12] +.sym 15174 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 15175 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 15176 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 15181 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 15182 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 15186 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 15187 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 15189 rx_fifo.rd_addr_gray_wr_r[5] +.sym 15192 rx_fifo.wr_addr[0] +.sym 15194 rx_fifo.rd_addr_gray_wr_r[0] +.sym 15195 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 15199 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 15200 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 15205 w_rx_fifo_pulled_data[12] +.sym 15211 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 15212 w_rx_fifo_full +.sym 15213 rx_fifo.rd_addr_gray_wr_r[9] +.sym 15217 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 15220 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 15221 smi_ctrl_ins.soe_and_reset +.sym 15222 i_rst_b_SB_LUT4_I3_O +.sym 15223 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 15224 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 15225 rx_fifo.rd_addr_gray_wr[6] +.sym 15226 rx_fifo.rd_addr_gray_wr[3] +.sym 15227 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[2] +.sym 15229 w_rx_fifo_data[12] +.sym 15230 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.sym 15235 w_rx_24_fifo_data[9] +.sym 15236 w_rx_fifo_data[2] +.sym 15238 w_rx_09_fifo_data[21] +.sym 15239 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 15240 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 15241 w_ioc[0] +.sym 15244 w_tx_fifo_pulled_data[25] +.sym 15245 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 15246 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15247 rx_fifo.rd_addr[9] +.sym 15248 r_counter +.sym 15249 rx_fifo.rd_addr_gray_wr_r[2] +.sym 15250 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 15251 lvds_tx_inst.r_tx_state +.sym 15252 w_rx_fifo_data[12] +.sym 15253 rx_fifo.rd_addr_gray_wr_r[9] +.sym 15254 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 15255 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15256 r_counter +.sym 15257 lvds_rx_24_inst.r_sync_input_SB_DFFER_Q_E +.sym 15264 w_tx_fsm_state[0] +.sym 15265 tx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 15266 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 15267 w_tx_fifo_pulled_data[24] +.sym 15268 lvds_tx_inst.r_fifo_data[24] +.sym 15269 channel +.sym 15270 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 15271 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 15272 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 15273 w_rx_24_fifo_data[14] +.sym 15274 w_tx_fsm_state[1] +.sym 15275 lvds_tx_inst.frame_boundary +.sym 15277 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 15278 w_rx_09_fifo_data[14] +.sym 15282 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 15284 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 15285 lvds_tx_inst.r_fifo_data[23] +.sym 15286 w_tx_fifo_pulled_data[23] +.sym 15287 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[1] +.sym 15289 lvds_tx_inst.r_fifo_data[22] +.sym 15290 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 15292 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[2] +.sym 15293 i_rst_b_SB_LUT4_I3_O +.sym 15294 w_tx_fifo_pulled_data[22] +.sym 15295 w_tx_fifo_pulled_data[21] +.sym 15298 w_rx_09_fifo_data[14] +.sym 15299 w_rx_24_fifo_data[14] +.sym 15300 channel +.sym 15303 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 15304 lvds_tx_inst.r_fifo_data[22] +.sym 15305 w_tx_fifo_pulled_data[22] +.sym 15306 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 15309 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 15310 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 15311 w_tx_fifo_pulled_data[21] +.sym 15312 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 15315 tx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 15316 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 15317 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 15318 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 15321 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 15322 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 15323 lvds_tx_inst.r_fifo_data[24] +.sym 15324 w_tx_fifo_pulled_data[24] +.sym 15327 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 15328 w_tx_fifo_pulled_data[23] +.sym 15329 lvds_tx_inst.r_fifo_data[23] +.sym 15330 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 15333 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 15334 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[1] +.sym 15335 w_tx_fsm_state[0] +.sym 15336 w_tx_fsm_state[1] +.sym 15340 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 15341 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[2] +.sym 15342 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 15343 lvds_tx_inst.frame_boundary +.sym 15344 lvds_clock_buf +.sym 15345 i_rst_b_SB_LUT4_I3_O +.sym 15347 rx_fifo.rd_addr_gray_wr_r[9] +.sym 15348 rx_fifo.rd_addr_gray_wr[2] +.sym 15349 w_rx_fifo_data[18] +.sym 15350 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 15351 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 15352 rx_fifo.rd_addr_gray_wr[9] +.sym 15353 rx_fifo.rd_addr_gray_wr_r[2] +.sym 15358 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 15360 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15361 rx_fifo.rd_addr_gray[3] +.sym 15362 w_rx_fifo_data[27] +.sym 15363 w_tx_fifo_pulled_data[24] +.sym 15364 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 15365 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15366 w_rx_09_fifo_data[17] +.sym 15368 w_tx_fsm_state[0] +.sym 15370 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15371 r_counter +.sym 15374 r_counter +.sym 15376 i_rst_b_SB_LUT4_I3_O +.sym 15379 w_rx_24_fifo_data[18] +.sym 15381 smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.sym 15391 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 15393 w_rx_09_fifo_data[7] +.sym 15394 w_rx_09_fifo_data[13] +.sym 15395 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 15398 w_rx_09_fifo_data[6] +.sym 15399 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15400 tx_fifo.rd_addr_gray_wr_r[6] +.sym 15402 lvds_tx_inst.sent_first_sync +.sym 15404 tx_fifo.rd_addr_gray_wr_r[8] +.sym 15405 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15406 i_rst_b$SB_IO_IN +.sym 15408 w_rx_09_fifo_data[2] +.sym 15409 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 15410 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15411 lvds_tx_inst.r_tx_state +.sym 15413 w_rx_09_fifo_data[19] +.sym 15414 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 15415 lvds_tx_inst.fifo_empty_d2 +.sym 15418 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 15420 w_rx_09_fifo_data[7] +.sym 15421 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15426 tx_fifo.rd_addr_gray_wr_r[8] +.sym 15427 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 15428 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 15429 tx_fifo.rd_addr_gray_wr_r[6] +.sym 15434 w_rx_09_fifo_data[6] +.sym 15435 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15438 lvds_tx_inst.fifo_empty_d2 +.sym 15439 lvds_tx_inst.sent_first_sync +.sym 15440 lvds_tx_inst.r_tx_state +.sym 15441 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 15445 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15446 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 15447 i_rst_b$SB_IO_IN +.sym 15450 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15452 w_rx_09_fifo_data[13] +.sym 15457 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15459 w_rx_09_fifo_data[2] +.sym 15462 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15464 w_rx_09_fifo_data[19] +.sym 15466 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15467 lvds_clock_buf +.sym 15468 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 15470 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 15472 lvds_rx_24_inst.r_sync_input +.sym 15475 w_rx_fifo_data[16] +.sym 15479 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 15481 smi_ctrl_ins.soe_and_reset +.sym 15482 w_rx_09_fifo_data[31] +.sym 15483 $PACKER_VCC_NET +.sym 15484 w_tx_fifo_pulled_data[27] +.sym 15485 w_rx_09_fifo_data[18] +.sym 15486 lvds_tx_inst.fifo_empty_d2 +.sym 15489 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 15490 w_tx_fsm_state[1] +.sym 15491 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15493 w_rx_09_fifo_data[16] +.sym 15494 w_fetch +.sym 15495 w_rx_fifo_data[18] +.sym 15496 w_rx_09_fifo_data[26] +.sym 15497 i_rst_b_SB_LUT4_I3_O +.sym 15498 w_rx_fifo_data[16] +.sym 15500 w_rx_09_fifo_data[15] +.sym 15501 rx_fifo.rd_addr_gray_wr[8] +.sym 15502 w_tx_data_smi[1] +.sym 15512 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 15514 i_rst_b_SB_LUT4_I3_O +.sym 15520 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 15524 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 15528 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 15530 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15555 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 15557 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15558 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 15567 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 15569 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15570 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 15574 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15575 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 15589 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 15590 lvds_clock_buf +.sym 15591 i_rst_b_SB_LUT4_I3_O +.sym 15592 spi_if_ins.r_tx_byte[5] +.sym 15593 spi_if_ins.r_tx_byte[4] +.sym 15594 spi_if_ins.r_tx_byte[0] +.sym 15595 spi_if_ins.r_tx_byte[1] +.sym 15596 spi_if_ins.r_tx_byte[6] +.sym 15597 spi_if_ins.r_tx_byte[7] +.sym 15598 spi_if_ins.r_tx_byte[3] +.sym 15599 spi_if_ins.r_tx_byte[2] +.sym 15604 w_rx_24_fifo_data[16] +.sym 15605 w_rx_fifo_data[4] +.sym 15606 r_counter +.sym 15608 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 15610 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 15611 w_tx_fifo_pulled_data[30] +.sym 15613 i_rst_b_SB_LUT4_I3_O +.sym 15614 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 15616 r_counter +.sym 15617 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 15618 w_tx_data_io[5] +.sym 15619 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 15620 spi_if_ins.spi.SCKr[1] +.sym 15621 r_counter +.sym 15624 spi_if_ins.w_rx_data[5] +.sym 15634 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15635 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 15637 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 15639 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 15643 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 15644 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 15645 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15647 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 15654 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15655 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 15656 i_rst_b$SB_IO_IN +.sym 15657 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 15662 i_rst_b_SB_LUT4_I3_O +.sym 15679 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15691 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 15692 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 15693 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 15696 i_rst_b$SB_IO_IN +.sym 15698 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15699 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 15702 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 15703 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 15704 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 15705 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 15712 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E +.sym 15713 lvds_clock_buf +.sym 15714 i_rst_b_SB_LUT4_I3_O +.sym 15715 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 15716 w_rx_09_fifo_data[30] +.sym 15717 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 15718 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[3] +.sym 15719 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[2] +.sym 15720 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 15722 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 15728 spi_if_ins.r_tx_byte[3] +.sym 15729 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 15732 spi_if_ins.r_tx_byte[2] +.sym 15736 spi_if_ins.r_tx_byte[4] +.sym 15738 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15739 io_ctrl_ins.pmod_state[0] +.sym 15740 r_counter +.sym 15741 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] +.sym 15742 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 15744 w_cs[2] +.sym 15745 $PACKER_VCC_NET +.sym 15746 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 15747 w_tx_sync_type_09 +.sym 15748 w_cs[1] +.sym 15750 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 15756 r_counter +.sym 15757 io_ctrl_ins.pmod_state[0] +.sym 15758 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O +.sym 15760 w_cs[2] +.sym 15762 tx_fifo.rd_addr_gray_wr_r[7] +.sym 15763 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 15764 w_fetch +.sym 15766 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 15768 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 15769 i_rst_b_SB_LUT4_I3_O +.sym 15771 io_ctrl_ins.mixer_en_state +.sym 15773 w_tx_sync_type_09 +.sym 15774 w_tx_sync_type_24 +.sym 15781 w_ioc[0] +.sym 15782 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 15783 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 15784 tx_fifo.rd_addr_gray_wr_r[4] +.sym 15790 w_tx_sync_type_09 +.sym 15792 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 15801 w_tx_sync_type_24 +.sym 15802 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 15807 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 15813 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 15814 tx_fifo.rd_addr_gray_wr_r[4] +.sym 15815 tx_fifo.rd_addr_gray_wr_r[7] +.sym 15816 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 15819 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 15820 io_ctrl_ins.mixer_en_state +.sym 15821 io_ctrl_ins.pmod_state[0] +.sym 15822 w_ioc[0] +.sym 15833 w_fetch +.sym 15834 w_cs[2] +.sym 15835 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O +.sym 15836 r_counter +.sym 15837 i_rst_b_SB_LUT4_I3_O +.sym 15839 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 15840 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 15841 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 15842 spi_if_ins.o_cs_SB_LUT4_I2_1_O[0] +.sym 15843 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 15844 w_tx_data_io[2] +.sym 15845 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 15850 i_rst_b$SB_IO_IN +.sym 15851 tx_wr_data[12] +.sym 15852 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 15854 w_cs[0] +.sym 15856 w_tx_data_sys[7] +.sym 15857 i_rst_b$SB_IO_IN +.sym 15858 w_tx_data_sys[4] +.sym 15859 w_tx_data_sys[0] +.sym 15862 i_button_SB_LUT4_I2_I1[1] +.sym 15863 r_counter +.sym 15864 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 15866 r_counter +.sym 15868 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 15870 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 15872 smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.sym 15873 w_tx_data_io[4] +.sym 15879 spi_if_ins.w_rx_data[6] +.sym 15880 i_button_SB_LUT4_I2_I1[0] +.sym 15882 w_fetch +.sym 15883 i_rst_b_SB_LUT4_I3_O +.sym 15885 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 15886 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 15888 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 15889 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 15890 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 15894 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 15896 spi_if_ins.w_rx_data[5] +.sym 15898 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15899 w_cs[0] +.sym 15900 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 15901 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15902 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 15904 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 15906 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 15909 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 15910 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 15912 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 15913 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 15914 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15915 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 15918 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15919 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 15920 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 15921 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 15924 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 15925 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 15926 w_cs[0] +.sym 15927 w_fetch +.sym 15930 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 15931 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 15932 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 15933 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 15937 spi_if_ins.w_rx_data[5] +.sym 15938 spi_if_ins.w_rx_data[6] +.sym 15942 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 15944 i_button_SB_LUT4_I2_I1[0] +.sym 15945 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 15955 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 15956 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 15958 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 15959 lvds_clock_buf +.sym 15960 i_rst_b_SB_LUT4_I3_O +.sym 15963 w_cs[2] +.sym 15965 w_cs[1] +.sym 15966 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 15967 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] +.sym 15968 w_cs[3] +.sym 15973 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 15974 i_ss_SB_LUT4_I3_O +.sym 15975 i_rst_b$SB_IO_IN +.sym 15977 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 15979 tx_fifo.rd_addr[6] +.sym 15980 tx_fifo.wr_addr[0] +.sym 15981 $PACKER_VCC_NET +.sym 15983 w_ioc[1] +.sym 15984 r_counter +.sym 15985 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 15986 w_cs[0] +.sym 15988 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 15989 i_rst_b_SB_LUT4_I3_O +.sym 15990 w_ioc[0] +.sym 15991 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 15992 w_fetch +.sym 15994 i_sck$SB_IO_IN +.sym 15995 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 15996 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 16002 i_button_SB_LUT4_I2_I1[1] +.sym 16005 w_rx_data[2] +.sym 16008 w_rx_data[3] +.sym 16009 w_rx_data[7] +.sym 16013 w_rx_data[6] +.sym 16014 i_button_SB_LUT4_I2_I1[0] +.sym 16020 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 16027 r_counter +.sym 16028 w_rx_data[1] +.sym 16029 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 16031 i_rst_b_SB_LUT4_I3_O +.sym 16037 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 16043 w_rx_data[7] +.sym 16049 w_rx_data[3] +.sym 16059 w_rx_data[6] +.sym 16065 w_rx_data[1] +.sym 16071 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 16073 i_button_SB_LUT4_I2_I1[1] +.sym 16074 i_button_SB_LUT4_I2_I1[0] +.sym 16077 w_rx_data[2] +.sym 16081 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.sym 16082 r_counter +.sym 16083 i_rst_b_SB_LUT4_I3_O +.sym 16084 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 16085 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 16086 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 16087 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 16089 w_tx_data_io[4] +.sym 16090 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 16091 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 16096 tx_fifo.wr_addr[5] +.sym 16097 tx_fifo.rd_addr[9] +.sym 16098 r_counter +.sym 16102 i_button_SB_LUT4_I2_I1[0] +.sym 16103 i_rst_b$SB_IO_IN +.sym 16104 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 16108 r_counter +.sym 16109 spi_if_ins.w_rx_data[5] +.sym 16111 spi_if_ins.spi.SCKr[1] +.sym 16112 i_rst_b_SB_LUT4_I3_O +.sym 16113 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] .sym 16114 w_rx_data[2] -.sym 16117 w_rx_data[6] -.sym 16118 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16119 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 16125 i_glob_clock$SB_IO_IN -.sym 16127 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16131 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] -.sym 16133 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 16135 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 16136 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16139 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 16141 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 16151 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 16155 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] -.sym 16158 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16159 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 16160 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 16161 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 16189 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] -.sym 16190 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] -.sym 16191 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16200 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 16202 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 16203 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 16204 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16205 i_glob_clock$SB_IO_IN -.sym 16207 io_ctrl_ins.rf_pin_state[4] -.sym 16208 io_ctrl_ins.rf_pin_state[2] -.sym 16209 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 16210 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 16211 io_ctrl_ins.rf_pin_state[1] -.sym 16212 io_ctrl_ins.rf_pin_state[0] -.sym 16213 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 16214 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 16224 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 16228 o_shdn_tx_lna$SB_IO_OUT -.sym 16229 i_glob_clock$SB_IO_IN -.sym 16232 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 16237 o_shdn_rx_lna$SB_IO_OUT -.sym 16256 r_tx_data[2] -.sym 16259 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 16261 r_tx_data[0] -.sym 16263 r_tx_data[7] -.sym 16272 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 16284 r_tx_data[2] -.sym 16301 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 16307 r_tx_data[0] -.sym 16326 r_tx_data[7] -.sym 16327 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 16328 r_counter_$glb_clk -.sym 16330 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 16331 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 16332 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] -.sym 16334 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] -.sym 16336 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 16337 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 16344 w_rx_data[2] -.sym 16345 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 16349 i_rst_b$SB_IO_IN -.sym 16354 i_button$SB_IO_IN -.sym 16356 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 16358 i_button_SB_LUT4_I0_I3[0] -.sym 16362 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 16388 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 16390 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16391 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] -.sym 16394 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 16395 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 16397 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] -.sym 16398 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 16401 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 16410 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 16412 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16417 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16419 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 16422 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] -.sym 16424 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16429 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 16431 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16434 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 16436 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16440 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] -.sym 16443 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 16450 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 16451 r_counter_$glb_clk -.sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16453 i_button_SB_LUT4_I0_I3[0] +.sym 16115 io_ctrl_ins.pmod_state[3] +.sym 16116 w_rx_data[0] +.sym 16117 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 16118 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 16125 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 16127 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 16129 w_cs[1] +.sym 16130 i_button_SB_LUT4_I2_I1[0] +.sym 16133 spi_if_ins.w_rx_data[5] +.sym 16135 w_cs[2] +.sym 16138 w_load +.sym 16140 w_cs[3] +.sym 16141 r_counter +.sym 16145 spi_if_ins.w_rx_data[6] +.sym 16147 w_ioc[0] +.sym 16149 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 16151 w_ioc[1] +.sym 16152 w_fetch +.sym 16153 w_cs[0] +.sym 16156 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 16158 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 16159 w_ioc[1] +.sym 16160 w_ioc[0] +.sym 16161 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 16164 w_cs[2] +.sym 16165 w_cs[1] +.sym 16166 w_cs[0] +.sym 16167 w_cs[3] +.sym 16170 w_cs[1] +.sym 16179 spi_if_ins.w_rx_data[6] +.sym 16182 w_cs[1] +.sym 16183 w_cs[2] +.sym 16184 w_cs[3] +.sym 16185 w_cs[0] +.sym 16188 w_cs[2] +.sym 16189 w_fetch +.sym 16190 i_button_SB_LUT4_I2_I1[0] +.sym 16191 w_load +.sym 16197 spi_if_ins.w_rx_data[5] +.sym 16201 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 16204 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 16205 r_counter +.sym 16207 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 16208 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16209 io_ctrl_ins.debug_mode[1] +.sym 16210 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16211 io_ctrl_ins.debug_mode[0] +.sym 16212 i_button_SB_LUT4_I2_I1[2] +.sym 16213 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 16214 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16215 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 16219 i_button_SB_LUT4_I2_I1[1] +.sym 16221 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 16226 i_rst_b$SB_IO_IN +.sym 16227 w_rx_data[6] +.sym 16228 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 16230 tx_fifo.rd_addr[9] +.sym 16231 io_ctrl_ins.pmod_state[0] +.sym 16236 r_counter +.sym 16238 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16240 w_rx_data[5] +.sym 16242 w_rx_data[7] +.sym 16248 r_counter +.sym 16249 spi_if_ins.spi.SCKr[0] +.sym 16258 w_ioc[1] +.sym 16264 i_sck$SB_IO_IN +.sym 16266 w_ioc[2] +.sym 16268 w_ioc[4] +.sym 16269 spi_if_ins.spi.r_rx_bit_count[1] +.sym 16274 spi_if_ins.spi.r_rx_bit_count[2] +.sym 16275 spi_if_ins.spi.r_rx_bit_count[0] +.sym 16276 w_ioc[3] +.sym 16288 i_sck$SB_IO_IN +.sym 16305 spi_if_ins.spi.r_rx_bit_count[0] +.sym 16306 spi_if_ins.spi.r_rx_bit_count[2] +.sym 16308 spi_if_ins.spi.r_rx_bit_count[1] +.sym 16311 w_ioc[3] +.sym 16312 w_ioc[2] +.sym 16313 w_ioc[1] +.sym 16314 w_ioc[4] +.sym 16325 spi_if_ins.spi.SCKr[0] +.sym 16328 r_counter +.sym 16330 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] +.sym 16331 r_counter +.sym 16332 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] +.sym 16333 io_ctrl_ins.pmod_state[3] +.sym 16334 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 16335 io_ctrl_ins.pmod_state[1] +.sym 16336 io_ctrl_ins.pmod_state[0] +.sym 16337 io_ctrl_ins.pmod_state[2] +.sym 16345 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16346 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 16348 o_tr_vc1$SB_IO_OUT +.sym 16350 o_tr_vc2$SB_IO_OUT +.sym 16351 tx_fifo.wr_addr[7] +.sym 16352 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 16362 r_counter +.sym 16379 r_counter +.sym 16380 i_glob_clock$SB_IO_IN +.sym 16384 i_rst_b_SB_LUT4_I3_O +.sym 16405 r_counter +.sym 16451 i_glob_clock$SB_IO_IN +.sym 16452 i_rst_b_SB_LUT4_I3_O +.sym 16453 i_config[3]$SB_IO_IN .sym 16455 i_button$SB_IO_IN -.sym 16462 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 16497 lvds_clock -.sym 16519 lvds_clock -.sym 16554 tx_fifo.wr_addr[0] -.sym 16555 tx_fifo.wr_addr[2] -.sym 16556 tx_fifo.wr_addr[6] -.sym 16560 tx_fifo.wr_addr[1] -.sym 16585 o_smi_write_req$SB_IO_OUT -.sym 16599 tx_fifo.wr_addr[5] -.sym 16602 tx_fifo.wr_addr[7] -.sym 16608 tx_fifo.wr_addr[3] -.sym 16613 tx_fifo.wr_addr[2] -.sym 16615 tx_fifo.wr_addr[4] -.sym 16618 tx_fifo.wr_addr[1] -.sym 16620 tx_fifo.wr_addr[0] -.sym 16622 tx_fifo.wr_addr[6] -.sym 16627 $nextpnr_ICESTORM_LC_5$O -.sym 16630 tx_fifo.wr_addr[0] -.sym 16633 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 16636 tx_fifo.wr_addr[1] -.sym 16637 tx_fifo.wr_addr[0] -.sym 16639 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 16642 tx_fifo.wr_addr[2] -.sym 16643 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 16645 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 -.sym 16647 tx_fifo.wr_addr[3] -.sym 16649 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 16651 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16654 tx_fifo.wr_addr[4] -.sym 16655 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 -.sym 16657 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16659 tx_fifo.wr_addr[5] -.sym 16661 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16663 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 -.sym 16666 tx_fifo.wr_addr[6] -.sym 16667 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 16669 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16672 tx_fifo.wr_addr[7] -.sym 16673 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 -.sym 16682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 16683 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16684 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16686 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 16688 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16698 tx_fifo.wr_addr[1] -.sym 16703 i_sck$SB_IO_IN -.sym 16723 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 16725 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16730 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 16734 w_smi_data_output[4] -.sym 16735 tx_fifo.wr_addr[4] -.sym 16736 $PACKER_VCC_NET -.sym 16737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16743 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16747 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 16753 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16758 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 16759 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 16760 tx_fifo.wr_addr[9] -.sym 16761 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16773 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 16782 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 16788 tx_fifo.wr_addr[8] -.sym 16790 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 16792 tx_fifo.wr_addr[8] -.sym 16794 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 16798 tx_fifo.wr_addr[9] -.sym 16800 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 16811 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 16818 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 16827 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 16834 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 16837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16838 r_counter_$glb_clk -.sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 16841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 16845 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 16846 tx_fifo.wr_addr[4] -.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16852 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 16856 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 16863 i_ss$SB_IO_IN -.sym 16871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16882 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 16883 i_rst_b$SB_IO_IN -.sym 16884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 16885 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16886 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16887 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 16888 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 16890 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 16891 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 16892 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16893 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 16895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 16896 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 16897 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] -.sym 16898 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 16899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 16902 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 16904 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] -.sym 16905 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 16906 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 16908 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16912 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 16914 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16915 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 16916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 16920 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 16922 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 16926 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] -.sym 16927 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 16928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16929 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] -.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 16933 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 16934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16939 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 16940 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 16941 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 16945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 16946 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 16950 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 16951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 16956 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 16959 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16960 i_rst_b$SB_IO_IN -.sym 16961 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 16963 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] -.sym 16964 smi_ctrl_ins.r_fifo_push_1 -.sym 16965 w_tx_fifo_full -.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] -.sym 16967 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 16968 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] -.sym 16969 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 16970 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 16978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 16979 w_rx_fifo_pulled_data[14] -.sym 16980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16983 rx_fifo.wr_addr[4] -.sym 16984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16986 rx_fifo.wr_addr[9] +.sym 16461 r_counter +.sym 16465 tx_fifo.rd_addr[9] +.sym 16470 tx_fifo.rd_addr[6] +.sym 16471 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 16472 i_glob_clock$SB_IO_IN +.sym 16489 i_rst_b$SB_IO_IN +.sym 16523 i_rst_b$SB_IO_IN +.sym 16525 i_config[2]$SB_IO_IN +.sym 16553 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[1] +.sym 16554 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 16555 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 16556 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 16557 rx_fifo.rd_addr[3] +.sym 16558 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16559 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 16560 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 16586 $PACKER_VCC_NET +.sym 16595 r_counter +.sym 16599 rx_fifo.wr_addr_gray_rd[9] +.sym 16600 w_smi_data_input[7] +.sym 16602 rx_fifo.wr_addr_gray_rd_r[2] +.sym 16609 rx_fifo.wr_addr_gray_rd[2] +.sym 16614 rx_fifo.wr_addr[9] +.sym 16616 rx_fifo.wr_addr_gray[6] +.sym 16617 rx_fifo.wr_addr_gray_rd[6] +.sym 16622 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 16623 rx_fifo.rd_addr[3] +.sym 16624 rx_fifo.wr_addr_gray[4] +.sym 16629 w_smi_data_input[7] +.sym 16635 rx_fifo.wr_addr_gray_rd[6] +.sym 16642 rx_fifo.wr_addr_gray[4] +.sym 16646 rx_fifo.rd_addr[3] +.sym 16647 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 16648 rx_fifo.wr_addr_gray_rd_r[2] +.sym 16653 rx_fifo.wr_addr[9] +.sym 16661 rx_fifo.wr_addr_gray_rd[9] +.sym 16665 rx_fifo.wr_addr_gray[6] +.sym 16670 rx_fifo.wr_addr_gray_rd[2] +.sym 16675 r_counter +.sym 16677 w_smi_data_input[4] +.sym 16681 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 16682 rx_fifo.rd_addr_gray[7] +.sym 16683 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 16684 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 16685 rx_fifo.rd_addr[0] +.sym 16686 rx_fifo.rd_addr[8] +.sym 16687 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[2] +.sym 16688 rx_fifo.rd_addr_gray[2] +.sym 16692 w_rx_24_fifo_data[12] +.sym 16693 r_counter +.sym 16694 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 16695 w_rx_fifo_pulled_data[0] +.sym 16698 $PACKER_VCC_NET +.sym 16699 rx_fifo.wr_addr_gray_rd[4] +.sym 16700 r_counter +.sym 16702 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 16703 r_counter +.sym 16704 $PACKER_VCC_NET +.sym 16705 w_smi_data_input[4] +.sym 16706 i_sck$SB_IO_IN +.sym 16709 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 16710 i_ss$SB_IO_IN +.sym 16712 w_smi_data_direction +.sym 16715 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 16716 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 16717 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 16722 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 16723 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 16735 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 16736 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 16738 w_rx_24_fifo_data[22] +.sym 16742 w_smi_data_output[4] +.sym 16743 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 16746 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 16747 rx_fifo.wr_addr_gray_rd_r[2] +.sym 16748 i_rst_b_SB_LUT4_I3_O +.sym 16762 rx_fifo.rd_addr[3] +.sym 16763 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16764 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 16767 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 16768 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 16776 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 16778 rx_fifo.rd_addr[0] +.sym 16785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 16786 rx_fifo.rd_addr[0] +.sym 16790 $nextpnr_ICESTORM_LC_1$O +.sym 16792 rx_fifo.rd_addr[0] +.sym 16796 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 16798 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 16800 rx_fifo.rd_addr[0] +.sym 16802 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 16805 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 16806 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 16808 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 16810 rx_fifo.rd_addr[3] +.sym 16812 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 16814 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 16817 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 16818 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 16820 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 16823 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16824 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 16826 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 16828 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 16830 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 16832 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 16834 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 16836 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 16840 rx_fifo.rd_addr_gray_wr[7] +.sym 16842 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[0] +.sym 16843 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 16844 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 16845 rx_fifo.rd_addr_gray_wr[5] +.sym 16846 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 16847 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 16853 i_rst_b_SB_LUT4_I3_O +.sym 16854 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 16855 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 16856 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 16857 rx_fifo.rd_addr[9] +.sym 16858 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 16859 r_counter +.sym 16860 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 16862 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 16863 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 16864 i_sck$SB_IO_IN +.sym 16865 w_rx_fifo_data[26] +.sym 16867 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 16869 w_rx_fifo_push +.sym 16871 rx_fifo.wr_addr[4] +.sym 16872 i_rst_b_SB_LUT4_I3_O +.sym 16873 rx_fifo.rd_addr_gray_wr_r[0] +.sym 16874 rx_fifo.rd_addr_gray[2] +.sym 16875 rx_fifo.wr_addr[9] +.sym 16876 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 16883 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 16886 rx_fifo.rd_addr[8] +.sym 16888 w_rx_24_fifo_data[20] +.sym 16890 w_rx_24_fifo_data[6] +.sym 16891 rx_fifo.rd_addr[9] +.sym 16894 w_rx_24_fifo_data[10] +.sym 16896 w_rx_24_fifo_data[22] +.sym 16901 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 16906 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 16908 w_rx_24_fifo_data[8] +.sym 16910 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 16913 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 16915 rx_fifo.rd_addr[8] +.sym 16917 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 16922 rx_fifo.rd_addr[9] +.sym 16923 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 16926 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 16928 w_rx_24_fifo_data[10] +.sym 16933 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 16935 w_rx_24_fifo_data[6] +.sym 16938 w_rx_24_fifo_data[22] +.sym 16940 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 16945 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 16947 w_rx_24_fifo_data[8] +.sym 16952 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 16957 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 16958 w_rx_24_fifo_data[20] +.sym 16960 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 16961 lvds_clock_buf +.sym 16962 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 16964 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 16965 rx_fifo.rd_addr_gray_wr_r[5] +.sym 16966 rx_fifo.rd_addr_gray_wr_r[7] +.sym 16967 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 16968 w_rx_fifo_data[19] +.sym 16975 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 16976 rx_fifo.rd_addr_gray_wr[4] +.sym 16977 rx_fifo.rd_addr[9] +.sym 16978 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 16979 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 16980 smi_ctrl_ins.soe_and_reset +.sym 16981 i_rst_b_SB_LUT4_I3_O +.sym 16982 w_rx_fifo_data[16] +.sym 16983 w_rx_fifo_data[18] +.sym 16985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 16986 rx_fifo.wr_addr_gray_rd_r[7] +.sym 16987 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] .sym 16988 i_ss$SB_IO_IN -.sym 16991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 16997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 17008 tx_fifo.rd_addr_gray_wr[4] -.sym 17011 tx_fifo.rd_addr_gray_wr[2] -.sym 17015 tx_fifo.rd_addr_gray_wr[7] -.sym 17024 tx_fifo.rd_addr_gray[4] -.sym 17025 tx_fifo.rd_addr_gray_wr[1] -.sym 17030 tx_fifo.rd_addr_gray[1] -.sym 17032 tx_fifo.rd_addr_gray[7] -.sym 17033 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 17037 tx_fifo.rd_addr_gray_wr[7] -.sym 17046 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 17052 tx_fifo.rd_addr_gray_wr[2] -.sym 17057 tx_fifo.rd_addr_gray[7] -.sym 17061 tx_fifo.rd_addr_gray[4] -.sym 17067 tx_fifo.rd_addr_gray[1] -.sym 17075 tx_fifo.rd_addr_gray_wr[4] -.sym 17081 tx_fifo.rd_addr_gray_wr[1] -.sym 17084 r_counter_$glb_clk -.sym 17087 spi_if_ins.spi.r_rx_bit_count[1] -.sym 17088 spi_if_ins.spi.r_rx_bit_count[2] -.sym 17089 spi_if_ins.spi.r_rx_bit_count[0] -.sym 17093 o_smi_read_req$SB_IO_OUT -.sym 17100 rx_fifo.rd_addr[5] -.sym 17102 i_ss$SB_IO_IN -.sym 17103 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 17108 smi_ctrl_ins.r_fifo_push -.sym 17109 w_tx_fifo_full -.sym 17111 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 17112 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 17118 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17127 i_sck$SB_IO_IN -.sym 17129 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17130 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 17131 i_ss$SB_IO_IN -.sym 17133 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17134 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 17137 w_tx_fifo_full -.sym 17138 tx_fifo.wr_addr[1] -.sym 17139 i_ss$SB_IO_IN -.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 17141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 17143 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 17144 spi_if_ins.spi.r_rx_bit_count[1] -.sym 17145 spi_if_ins.spi.r_rx_bit_count[2] -.sym 17147 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 17148 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 17154 spi_if_ins.spi.r_rx_bit_count[0] -.sym 17160 spi_if_ins.spi.r_rx_bit_count[0] -.sym 17161 spi_if_ins.spi.r_rx_bit_count[1] -.sym 17162 spi_if_ins.spi.r_rx_bit_count[2] -.sym 17163 i_ss$SB_IO_IN -.sym 17174 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17178 w_tx_fifo_full -.sym 17180 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 17181 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 17185 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 17186 tx_fifo.wr_addr[1] -.sym 17187 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 17190 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 17191 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 17193 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 17196 spi_if_ins.spi.r_rx_bit_count[0] -.sym 17198 spi_if_ins.spi.r_rx_bit_count[2] -.sym 17199 spi_if_ins.spi.r_rx_bit_count[1] -.sym 17204 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 17206 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17207 i_sck$SB_IO_IN -.sym 17208 i_ss$SB_IO_IN -.sym 17209 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 17210 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 17212 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 17213 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 17214 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 17216 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 17219 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] -.sym 17223 w_rx_fifo_pulled_data[16] -.sym 17227 i_sck$SB_IO_IN -.sym 17232 rx_fifo.wr_addr[8] -.sym 17234 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 17236 spi_if_ins.w_rx_data[6] -.sym 17238 $PACKER_VCC_NET -.sym 17240 w_smi_data_direction -.sym 17243 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17250 spi_if_ins.spi.r3_rx_done -.sym 17252 spi_if_ins.spi.r_rx_done -.sym 17254 tx_fifo.rd_addr_gray_wr[9] -.sym 17259 i_ss$SB_IO_IN -.sym 17260 tx_fifo.rd_addr_gray_wr[0] -.sym 17264 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17273 spi_if_ins.spi.r2_rx_done -.sym 17284 spi_if_ins.spi.r2_rx_done -.sym 17297 spi_if_ins.spi.r3_rx_done -.sym 17298 spi_if_ins.spi.r2_rx_done -.sym 17307 i_ss$SB_IO_IN -.sym 17308 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17316 tx_fifo.rd_addr_gray_wr[9] -.sym 17320 tx_fifo.rd_addr_gray_wr[0] -.sym 17328 spi_if_ins.spi.r_rx_done -.sym 17330 r_counter_$glb_clk -.sym 17332 spi_if_ins.spi.r_rx_byte[0] -.sym 17333 spi_if_ins.spi.r_rx_byte[7] -.sym 17334 spi_if_ins.spi.r_rx_byte[2] -.sym 17335 spi_if_ins.spi.r_rx_byte[4] -.sym 17336 spi_if_ins.spi.r_rx_byte[5] -.sym 17337 spi_if_ins.spi.r_rx_byte[3] -.sym 17338 spi_if_ins.spi.r_rx_byte[1] -.sym 17339 spi_if_ins.spi.r_rx_byte[6] -.sym 17344 rx_fifo.rd_addr[0] -.sym 17346 rx_fifo.rd_addr[5] -.sym 17347 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 17350 tx_fifo.rd_addr_gray_wr[9] -.sym 17351 $PACKER_VCC_NET -.sym 17357 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17362 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 17363 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17377 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 17383 tx_fifo.rd_addr_gray[0] -.sym 17421 tx_fifo.rd_addr_gray[0] -.sym 17427 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 17453 r_counter_$glb_clk -.sym 17455 spi_if_ins.w_rx_data[2] -.sym 17456 spi_if_ins.w_rx_data[6] -.sym 17457 spi_if_ins.w_rx_data[0] -.sym 17458 spi_if_ins.w_rx_data[4] -.sym 17459 spi_if_ins.w_rx_data[5] -.sym 17460 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 17461 spi_if_ins.w_rx_data[1] -.sym 17462 spi_if_ins.w_rx_data[3] -.sym 17468 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 17469 rx_fifo.wr_addr[9] -.sym 17470 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 17471 rx_fifo.wr_addr[4] -.sym 17472 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 17473 i_sck$SB_IO_IN -.sym 17476 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 17478 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 17486 spi_if_ins.w_rx_data[3] -.sym 17488 spi_if_ins.w_rx_data[2] -.sym 17489 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 17490 spi_if_ins.w_rx_data[6] -.sym 17496 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 17498 spi_if_ins.spi.r_tx_byte[2] -.sym 17499 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 17501 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 17503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 17505 w_tx_fifo_full -.sym 17506 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 17507 spi_if_ins.spi.r_tx_byte[3] -.sym 17508 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17509 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 17514 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 17516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17517 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 17521 w_smi_read_req -.sym 17522 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 17523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 17524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17525 o_led0_SB_LUT4_I1_O[1] -.sym 17531 w_tx_fifo_full -.sym 17536 w_smi_read_req -.sym 17544 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 17547 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 17548 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 17549 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 17553 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 17554 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 17555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 17556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 17559 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 17560 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17571 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17572 spi_if_ins.spi.r_tx_byte[3] -.sym 17574 spi_if_ins.spi.r_tx_byte[2] -.sym 17575 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 17576 r_counter_$glb_clk -.sym 17577 o_led0_SB_LUT4_I1_O[1] -.sym 17580 spi_if_ins.spi.r_tx_byte[7] -.sym 17581 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17582 spi_if_ins.spi.r_tx_byte[5] -.sym 17583 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 17593 rx_fifo.rd_addr[5] -.sym 17599 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 17600 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 17601 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 17602 spi_if_ins.w_rx_data[0] -.sym 17604 spi_if_ins.w_rx_data[4] -.sym 17606 spi_if_ins.w_rx_data[5] -.sym 17608 o_led0_SB_LUT4_I1_O[1] -.sym 17610 w_rx_data[4] -.sym 17613 i_button_SB_LUT4_I0_O[1] -.sym 17623 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17631 spi_if_ins.spi.r_tx_byte[6] -.sym 17635 spi_if_ins.r_tx_byte[1] -.sym 17638 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 17639 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17640 spi_if_ins.r_tx_byte[2] -.sym 17641 spi_if_ins.r_tx_byte[3] -.sym 17642 spi_if_ins.r_tx_byte[6] -.sym 17643 spi_if_ins.r_tx_byte[0] -.sym 17644 spi_if_ins.spi.r_tx_byte[4] -.sym 17646 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17647 spi_if_ins.r_tx_byte[4] -.sym 17649 spi_if_ins.spi.r_tx_byte[1] -.sym 17650 spi_if_ins.spi.r_tx_byte[0] -.sym 17652 spi_if_ins.spi.r_tx_byte[4] -.sym 17653 spi_if_ins.spi.r_tx_byte[6] -.sym 17654 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 17658 spi_if_ins.r_tx_byte[4] -.sym 17667 spi_if_ins.r_tx_byte[2] -.sym 17673 spi_if_ins.r_tx_byte[3] -.sym 17677 spi_if_ins.r_tx_byte[6] -.sym 17682 spi_if_ins.spi.r_tx_byte[1] -.sym 17683 spi_if_ins.spi.r_tx_byte[0] -.sym 17685 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17690 spi_if_ins.r_tx_byte[1] -.sym 17694 spi_if_ins.r_tx_byte[0] -.sym 17698 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17699 r_counter_$glb_clk -.sym 17700 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17701 w_rx_data[1] -.sym 17702 o_led0_SB_LUT4_I1_O[1] -.sym 17703 w_rx_data[4] -.sym 17704 w_rx_data[7] -.sym 17705 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 17706 w_rx_data[3] -.sym 17707 w_rx_data[0] -.sym 17708 w_rx_data[5] -.sym 17715 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 17720 io_pmod_out[1]$SB_IO_OUT -.sym 17723 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 17725 i_glob_clock$SB_IO_IN -.sym 17726 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 17728 spi_if_ins.r_tx_byte[6] -.sym 17729 spi_if_ins.spi.r_tx_bit_count[0] -.sym 17730 w_rx_data[0] -.sym 17731 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17732 spi_if_ins.r_tx_byte[5] -.sym 17734 w_rx_data[1] -.sym 17735 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 17736 spi_if_ins.w_rx_data[6] -.sym 17742 w_ioc[2] -.sym 17744 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 17748 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 17749 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] -.sym 17751 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 17754 w_ioc[4] -.sym 17756 spi_if_ins.w_rx_data[3] -.sym 17758 spi_if_ins.w_rx_data[2] -.sym 17761 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 17762 spi_if_ins.w_rx_data[0] -.sym 17764 spi_if_ins.w_rx_data[4] -.sym 17773 w_ioc[3] -.sym 17777 spi_if_ins.w_rx_data[2] -.sym 17782 w_ioc[2] -.sym 17783 w_ioc[4] -.sym 17784 w_ioc[3] -.sym 17793 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 17796 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 17801 spi_if_ins.w_rx_data[4] -.sym 17806 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 17807 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] -.sym 17813 spi_if_ins.w_rx_data[0] -.sym 17819 spi_if_ins.w_rx_data[3] -.sym 17821 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 17822 r_counter_$glb_clk -.sym 17824 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 17825 w_cs[1] -.sym 17827 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 17828 w_cs[3] -.sym 17829 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 17830 w_cs[2] -.sym 17831 o_led1_SB_LUT4_I1_I3[3] -.sym 17836 w_fetch -.sym 17837 w_rx_data[0] -.sym 17839 w_rx_data[7] -.sym 17840 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 17843 w_rx_data[1] -.sym 17844 i_button_SB_LUT4_I0_O[1] -.sym 17845 o_led0_SB_LUT4_I1_O[1] -.sym 17848 w_rx_data[4] -.sym 17850 io_ctrl_ins.pmod_dir_state[7] -.sym 17851 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 17852 i_button_SB_LUT4_I0_I3[2] -.sym 17854 w_rx_data[3] -.sym 17856 w_rx_data[0] -.sym 17857 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 17858 w_rx_data[5] -.sym 17859 w_cs[1] -.sym 17866 r_tx_data[1] -.sym 17867 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 17868 r_tx_data[6] -.sym 17871 r_tx_data[4] -.sym 17872 r_tx_data[3] -.sym 17873 r_tx_data[5] -.sym 17874 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 17875 w_cs[0] -.sym 17879 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 17882 w_cs[1] -.sym 17885 w_cs[3] -.sym 17887 w_cs[2] -.sym 17893 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 17898 w_cs[2] -.sym 17899 w_cs[1] -.sym 17900 w_cs[3] -.sym 17901 w_cs[0] -.sym 17906 r_tx_data[5] -.sym 17912 r_tx_data[4] -.sym 17918 r_tx_data[3] -.sym 17923 r_tx_data[1] -.sym 17935 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 17936 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 17937 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 17940 r_tx_data[6] -.sym 17944 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 17945 r_counter_$glb_clk -.sym 17947 o_led1_SB_LUT4_I1_O[3] -.sym 17948 o_led1_SB_LUT4_I1_I3[0] -.sym 17949 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0] -.sym 17950 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] -.sym 17951 io_ctrl_ins.pmod_dir_state[1] -.sym 17952 io_ctrl_ins.pmod_dir_state[5] -.sym 17953 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 17954 io_ctrl_ins.pmod_dir_state[7] -.sym 17960 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 17961 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 17964 o_led1_SB_LUT4_I1_I3[3] -.sym 17966 w_fetch -.sym 17967 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 17968 r_tx_data[3] -.sym 17972 w_rx_data[7] -.sym 17973 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 17974 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 17976 w_load -.sym 17979 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 17980 i_button_SB_LUT4_I0_I3[2] -.sym 17982 w_load -.sym 17988 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 17989 w_cs[1] -.sym 17990 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 17991 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 17992 w_cs[3] -.sym 17993 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 17994 i_button_SB_LUT4_I0_I3[3] -.sym 17995 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 17996 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 17997 i_glob_clock$SB_IO_IN -.sym 17999 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 18000 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18001 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 18002 w_cs[2] -.sym 18003 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18005 i_button$SB_IO_IN -.sym 18006 w_cs[0] -.sym 18007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 18010 io_ctrl_ins.pmod_dir_state[7] -.sym 18011 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 18012 i_button_SB_LUT4_I0_I3[2] -.sym 18018 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 18019 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18021 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 18022 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 18023 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 18028 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 18029 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 18030 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 18034 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 18035 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18036 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18039 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 18040 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 18041 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 18042 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18045 i_button_SB_LUT4_I0_I3[3] -.sym 18046 i_button$SB_IO_IN -.sym 18047 io_ctrl_ins.pmod_dir_state[7] -.sym 18048 i_button_SB_LUT4_I0_I3[2] -.sym 18051 w_cs[2] -.sym 18052 w_cs[3] -.sym 18053 w_cs[1] -.sym 18054 w_cs[0] -.sym 18057 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 18058 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 18059 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18060 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 18063 w_cs[1] -.sym 18064 w_cs[3] -.sym 18065 w_cs[2] -.sym 18066 w_cs[0] -.sym 18067 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 18068 i_glob_clock$SB_IO_IN -.sym 18070 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18071 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 18072 i_button_SB_LUT4_I0_I3[1] -.sym 18073 io_ctrl_ins.pmod_dir_state[3] -.sym 18074 o_led1_SB_LUT4_I1_I2[1] -.sym 18075 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 18076 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 18077 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 18085 w_rx_data[2] -.sym 18088 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 18089 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 18092 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 18093 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 18094 o_led1$SB_IO_OUT -.sym 18095 w_rx_data[4] -.sym 18096 o_led0_SB_LUT4_I1_O[1] -.sym 18097 w_cs[1] -.sym 18099 o_led1_SB_LUT4_I1_O[0] -.sym 18101 i_button_SB_LUT4_I0_O[1] -.sym 18105 o_led0_SB_LUT4_I1_O[0] -.sym 18112 o_led0_SB_LUT4_I1_O[0] -.sym 18113 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 18114 io_pmod_out[1]$SB_IO_OUT -.sym 18115 o_led0_SB_LUT4_I1_O[1] -.sym 18116 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 18117 w_tx_data_smi[1] -.sym 18118 o_led0_SB_LUT4_I1_O[3] -.sym 18119 o_led1_SB_LUT4_I1_O[3] -.sym 18120 io_pmod_out[0]$SB_IO_OUT -.sym 18121 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 18123 o_led1_SB_LUT4_I1_O[0] -.sym 18124 o_shdn_rx_lna$SB_IO_OUT -.sym 18125 io_ctrl_ins.mixer_en_state -.sym 18126 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18127 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 18128 w_tx_data_io[0] -.sym 18129 o_led1_SB_LUT4_I1_O[2] -.sym 18131 o_led0_SB_LUT4_I1_O[2] -.sym 18132 w_tx_data_io[1] -.sym 18134 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18135 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] -.sym 18136 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] -.sym 18137 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 18139 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 18140 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 18145 w_tx_data_io[0] -.sym 18146 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18147 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 18150 o_led0_SB_LUT4_I1_O[0] -.sym 18151 o_led0_SB_LUT4_I1_O[2] -.sym 18152 o_led0_SB_LUT4_I1_O[3] -.sym 18153 o_led0_SB_LUT4_I1_O[1] -.sym 18156 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 18157 io_pmod_out[1]$SB_IO_OUT -.sym 18158 o_shdn_rx_lna$SB_IO_OUT -.sym 18159 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18162 w_tx_data_io[1] -.sym 18163 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 18164 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 18165 w_tx_data_smi[1] -.sym 18168 io_pmod_out[0]$SB_IO_OUT -.sym 18169 io_ctrl_ins.mixer_en_state -.sym 18170 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 18171 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18174 o_led1_SB_LUT4_I1_O[0] -.sym 18175 o_led1_SB_LUT4_I1_O[2] -.sym 18176 o_led1_SB_LUT4_I1_O[3] -.sym 18177 o_led0_SB_LUT4_I1_O[1] -.sym 18180 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] -.sym 18181 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 18183 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] -.sym 18186 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 18187 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 18188 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 18190 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 18191 r_counter_$glb_clk -.sym 18192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 18193 io_ctrl_ins.rf_pin_state[3] -.sym 18194 io_ctrl_ins.rf_pin_state[5] -.sym 18195 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E -.sym 18196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 18197 io_ctrl_ins.rf_pin_state[6] -.sym 18198 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 18199 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 18200 io_ctrl_ins.rf_pin_state[7] -.sym 18206 io_pmod_out[0]$SB_IO_OUT -.sym 18208 io_pmod_out[3]$SB_IO_OUT -.sym 18209 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 18210 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 18213 i_button_SB_LUT4_I0_I3[3] -.sym 18216 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 18217 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18218 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 18219 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 18223 w_rx_data[0] -.sym 18226 w_rx_data[1] -.sym 18234 io_ctrl_ins.rf_pin_state[4] -.sym 18236 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 18238 io_ctrl_ins.rf_pin_state[1] -.sym 18243 io_ctrl_ins.rf_pin_state[2] -.sym 18247 io_ctrl_ins.rf_pin_state[0] -.sym 18249 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18250 io_ctrl_ins.rf_pin_state[3] -.sym 18251 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18254 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18256 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 18257 io_ctrl_ins.rf_pin_state[7] -.sym 18258 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18259 io_ctrl_ins.rf_pin_state[5] -.sym 18262 io_ctrl_ins.rf_pin_state[6] -.sym 18267 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18268 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18269 io_ctrl_ins.rf_pin_state[3] -.sym 18270 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18273 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18274 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18275 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18276 io_ctrl_ins.rf_pin_state[2] -.sym 18280 io_ctrl_ins.rf_pin_state[7] -.sym 18281 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18282 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18285 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18286 io_ctrl_ins.rf_pin_state[4] -.sym 18287 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18288 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 18291 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18292 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18294 io_ctrl_ins.rf_pin_state[6] -.sym 18297 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18299 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18300 io_ctrl_ins.rf_pin_state[1] -.sym 18303 io_ctrl_ins.rf_pin_state[0] -.sym 18304 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18305 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18306 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18309 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18310 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 18311 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18312 io_ctrl_ins.rf_pin_state[5] -.sym 18313 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 18314 r_counter_$glb_clk -.sym 18316 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18317 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18318 o_led1_SB_LUT4_I1_O[0] -.sym 18319 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] -.sym 18320 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18321 o_led0_SB_LUT4_I1_O[0] -.sym 18323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 18328 o_tr_vc2$SB_IO_OUT -.sym 18332 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 18334 o_rx_h_tx_l$SB_IO_OUT -.sym 18335 o_led0_SB_LUT4_I1_O[3] -.sym 18338 w_fetch -.sym 18340 w_rx_data[4] -.sym 18344 w_rx_data[0] -.sym 18345 i_config[2]$SB_IO_IN -.sym 18346 w_rx_data[5] -.sym 18357 i_rst_b$SB_IO_IN -.sym 18359 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 18365 w_rx_data[4] -.sym 18367 w_rx_data[2] -.sym 18370 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 18374 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18375 o_led1_SB_LUT4_I1_O[0] -.sym 18377 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18378 o_led0_SB_LUT4_I1_O[0] -.sym 18381 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18383 w_rx_data[0] -.sym 18384 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 18386 w_rx_data[1] -.sym 18388 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 18393 w_rx_data[4] -.sym 18398 w_rx_data[2] -.sym 18402 i_rst_b$SB_IO_IN -.sym 18403 o_led0_SB_LUT4_I1_O[0] -.sym 18404 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18405 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18409 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 18414 w_rx_data[1] -.sym 18420 w_rx_data[0] -.sym 18426 o_led1_SB_LUT4_I1_O[0] -.sym 18428 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 18432 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 18433 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 18434 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 18435 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 18436 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 18437 r_counter_$glb_clk -.sym 18439 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 18454 o_tr_vc1_b$SB_IO_OUT -.sym 18460 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 18482 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 18487 w_rx_data[2] -.sym 18488 w_rx_data[6] -.sym 18496 w_rx_data[1] -.sym 18500 w_rx_data[4] -.sym 18504 w_rx_data[0] -.sym 18506 w_rx_data[5] -.sym 18514 w_rx_data[5] -.sym 18521 w_rx_data[2] -.sym 18528 w_rx_data[0] -.sym 18537 w_rx_data[1] -.sym 18551 w_rx_data[4] -.sym 18555 w_rx_data[6] -.sym 18559 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 18560 r_counter_$glb_clk -.sym 18561 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16989 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 16991 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 16992 w_rx_24_fifo_data[24] +.sym 16995 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 16996 channel +.sym 16997 w_smi_read_req +.sym 17005 i_rst_b$SB_IO_IN +.sym 17006 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 17007 channel +.sym 17009 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 17011 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 17012 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 17015 w_smi_data_direction +.sym 17016 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 17017 i_rst_b_SB_LUT4_I3_O +.sym 17018 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 17022 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 17023 w_smi_read_req +.sym 17026 smi_ctrl_ins.int_cnt_rx[4] +.sym 17029 w_rx_fifo_push +.sym 17030 smi_ctrl_ins.int_cnt_rx[3] +.sym 17031 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 17033 w_rx_24_fifo_data[26] +.sym 17034 w_tx_fifo_full +.sym 17035 w_rx_09_fifo_data[26] +.sym 17038 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 17040 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 17043 smi_ctrl_ins.int_cnt_rx[3] +.sym 17044 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 17045 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 17046 smi_ctrl_ins.int_cnt_rx[4] +.sym 17056 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 17062 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 17064 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 17068 w_rx_fifo_push +.sym 17069 i_rst_b$SB_IO_IN +.sym 17073 w_rx_09_fifo_data[26] +.sym 17074 channel +.sym 17075 w_rx_24_fifo_data[26] +.sym 17079 w_tx_fifo_full +.sym 17080 w_smi_data_direction +.sym 17081 w_smi_read_req +.sym 17083 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 17084 lvds_clock_buf +.sym 17085 i_rst_b_SB_LUT4_I3_O +.sym 17086 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 17087 rx_fifo.wr_addr[2] +.sym 17088 rx_fifo.wr_addr[3] +.sym 17089 rx_fifo.wr_addr[4] +.sym 17090 rx_fifo.wr_addr[6] +.sym 17091 rx_fifo.wr_addr[8] +.sym 17092 rx_fifo.wr_addr[0] +.sym 17093 rx_fifo.wr_addr[5] +.sym 17099 r_counter +.sym 17100 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 17101 w_rx_24_fifo_data[6] +.sym 17102 w_rx_fifo_pulled_data[19] +.sym 17103 $PACKER_VCC_NET +.sym 17104 r_counter +.sym 17105 i_rst_b_SB_LUT4_I3_O +.sym 17106 rx_fifo.rd_addr_gray[6] +.sym 17107 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] +.sym 17108 w_rx_24_fifo_data[20] +.sym 17109 rx_fifo.rd_addr_gray_wr_r[5] +.sym 17110 w_rx_24_fifo_data[19] +.sym 17112 rx_fifo.rd_addr_gray_wr_r[7] +.sym 17113 rx_fifo.wr_addr[9] +.sym 17114 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 17115 rx_fifo.wr_addr[0] +.sym 17119 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 17121 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 17132 rx_fifo.wr_addr[7] +.sym 17145 rx_fifo.wr_addr[3] +.sym 17149 rx_fifo.wr_addr[0] +.sym 17150 rx_fifo.wr_addr[5] +.sym 17151 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 17152 rx_fifo.wr_addr[2] +.sym 17154 rx_fifo.wr_addr[4] +.sym 17155 rx_fifo.wr_addr[6] +.sym 17157 rx_fifo.wr_addr[0] +.sym 17159 $nextpnr_ICESTORM_LC_2$O +.sym 17161 rx_fifo.wr_addr[0] +.sym 17165 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 17168 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 17169 rx_fifo.wr_addr[0] +.sym 17171 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 17174 rx_fifo.wr_addr[2] +.sym 17175 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 17177 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 17179 rx_fifo.wr_addr[3] +.sym 17181 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 17183 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 17186 rx_fifo.wr_addr[4] +.sym 17187 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 17189 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 17192 rx_fifo.wr_addr[5] +.sym 17193 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 17195 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 17197 rx_fifo.wr_addr[6] +.sym 17199 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 17201 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 17204 rx_fifo.wr_addr[7] +.sym 17205 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 17210 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 17211 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 17212 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 17213 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.sym 17214 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] +.sym 17215 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 17216 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 17222 $PACKER_VCC_NET +.sym 17223 w_rx_fifo_pulled_data[24] +.sym 17224 rx_fifo.wr_addr[4] +.sym 17225 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 17228 rx_fifo.wr_addr[7] +.sym 17229 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 17230 rx_fifo.rd_addr[9] +.sym 17231 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 17232 rx_fifo.wr_addr[3] +.sym 17233 w_tx_data_smi[0] +.sym 17234 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 17235 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 17237 r_counter +.sym 17239 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 17241 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 17242 spi_if_ins.w_rx_data[1] +.sym 17244 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 17245 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 17254 i_rst_b_SB_LUT4_I3_O +.sym 17255 rx_fifo.wr_addr[8] +.sym 17256 w_rx_24_fifo_data[2] +.sym 17258 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 17259 w_ioc[0] +.sym 17260 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 17261 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 17262 w_rx_24_fifo_data[24] +.sym 17263 w_rx_09_fifo_data[2] +.sym 17264 rx_fifo.wr_addr[9] +.sym 17265 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 17267 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 17268 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 17269 w_smi_read_req +.sym 17275 r_counter +.sym 17276 channel +.sym 17281 w_rx_09_fifo_data[24] +.sym 17282 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 17284 rx_fifo.wr_addr[8] +.sym 17286 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 17289 rx_fifo.wr_addr[9] +.sym 17292 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 17297 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 17298 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 17308 w_smi_read_req +.sym 17309 w_ioc[0] +.sym 17310 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 17313 channel +.sym 17314 w_rx_09_fifo_data[24] +.sym 17315 w_rx_24_fifo_data[24] +.sym 17319 w_rx_24_fifo_data[2] +.sym 17321 w_rx_09_fifo_data[2] +.sym 17322 channel +.sym 17325 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 17328 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 17329 smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 17330 r_counter +.sym 17331 i_rst_b_SB_LUT4_I3_O +.sym 17332 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8] +.sym 17334 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.sym 17335 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 17336 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 17337 w_rx_data[1] +.sym 17338 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] +.sym 17339 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 17344 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 17345 i_rst_b_SB_LUT4_I3_O +.sym 17347 w_rx_24_fifo_data[4] +.sym 17348 w_rx_fifo_pulled_data[27] +.sym 17350 i_rst_b_SB_LUT4_I3_O +.sym 17352 w_rx_24_fifo_data[2] +.sym 17353 w_tx_fsm_state[1] +.sym 17354 w_rx_24_fifo_data[18] +.sym 17355 w_rx_24_fifo_data[28] +.sym 17356 rx_fifo.wr_addr[9] +.sym 17357 rx_fifo.wr_addr[7] +.sym 17358 i_button_SB_LUT4_I2_I1[2] +.sym 17359 w_rx_data[1] +.sym 17360 i_rst_b_SB_LUT4_I3_O +.sym 17361 i_sck$SB_IO_IN +.sym 17362 rx_fifo.rd_addr_gray[2] +.sym 17363 w_rx_fifo_data[24] +.sym 17364 i_rst_b_SB_LUT4_I3_O +.sym 17365 io_ctrl_ins.rf_pin_state[0] +.sym 17366 tx_wr_data[14] +.sym 17367 w_rx_09_fifo_data[6] +.sym 17374 rx_fifo.rd_addr_gray_wr_r[9] +.sym 17376 rx_fifo.rd_addr_gray[6] +.sym 17377 lvds_tx_inst.r_tx_state +.sym 17378 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] +.sym 17379 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 17380 lvds_tx_inst.sent_first_sync +.sym 17382 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 17385 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 17386 w_rx_09_fifo_data[12] +.sym 17387 rx_fifo.rd_addr_gray[3] +.sym 17388 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 17389 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8] +.sym 17394 channel +.sym 17398 lvds_tx_inst.r_tx_state_q +.sym 17399 rx_fifo.rd_addr_gray_wr[6] +.sym 17401 w_rx_24_fifo_data[12] +.sym 17403 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] +.sym 17406 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8] +.sym 17407 rx_fifo.rd_addr_gray_wr_r[9] +.sym 17408 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 17409 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 17414 rx_fifo.rd_addr_gray_wr[6] +.sym 17421 rx_fifo.rd_addr_gray[6] +.sym 17426 rx_fifo.rd_addr_gray[3] +.sym 17430 lvds_tx_inst.r_tx_state +.sym 17431 lvds_tx_inst.sent_first_sync +.sym 17432 lvds_tx_inst.r_tx_state_q +.sym 17442 w_rx_09_fifo_data[12] +.sym 17443 channel +.sym 17445 w_rx_24_fifo_data[12] +.sym 17448 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] +.sym 17449 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 17450 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] +.sym 17451 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 17453 lvds_clock_buf +.sym 17455 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 17456 w_rx_fifo_data[28] +.sym 17457 w_rx_fifo_data[30] +.sym 17458 w_rx_fifo_data[6] +.sym 17459 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 17460 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 17461 w_rx_fifo_data[29] +.sym 17462 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 17470 w_rx_24_fifo_data[23] +.sym 17472 rx_fifo.rd_addr_gray_wr[8] +.sym 17478 i_rst_b_SB_LUT4_I3_O +.sym 17479 w_rx_fifo_pulled_data[25] +.sym 17480 channel +.sym 17481 i_ss$SB_IO_IN +.sym 17483 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 17484 w_rx_24_fifo_data[28] +.sym 17485 channel +.sym 17486 channel +.sym 17487 w_rx_sync_type_24 +.sym 17490 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.sym 17498 rx_fifo.rd_addr_gray_wr[2] +.sym 17499 rx_fifo.rd_addr_gray_wr[3] +.sym 17502 rx_fifo.rd_addr_gray_wr[9] +.sym 17504 channel +.sym 17508 rx_fifo.rd_addr[9] +.sym 17511 w_rx_09_fifo_data[18] +.sym 17512 w_rx_24_fifo_data[18] +.sym 17522 rx_fifo.rd_addr_gray[2] +.sym 17524 rx_fifo.rd_addr_gray_wr[8] +.sym 17538 rx_fifo.rd_addr_gray_wr[9] +.sym 17542 rx_fifo.rd_addr_gray[2] +.sym 17547 channel +.sym 17548 w_rx_09_fifo_data[18] +.sym 17550 w_rx_24_fifo_data[18] +.sym 17554 rx_fifo.rd_addr_gray_wr[8] +.sym 17561 rx_fifo.rd_addr_gray_wr[3] +.sym 17566 rx_fifo.rd_addr[9] +.sym 17574 rx_fifo.rd_addr_gray_wr[2] +.sym 17576 lvds_clock_buf +.sym 17578 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 17580 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 17581 w_rx_fifo_data[7] +.sym 17583 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 17585 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 17589 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 17590 i_rst_b_SB_LUT4_I3_O +.sym 17591 w_rx_24_fifo_data[6] +.sym 17594 $PACKER_VCC_NET +.sym 17596 w_rx_fifo_full +.sym 17597 spi_if_ins.spi.SCKr[1] +.sym 17599 $PACKER_VCC_NET +.sym 17601 lvds_tx_inst.r_tx_state +.sym 17603 w_tx_data_smi[4] +.sym 17604 w_rx_09_fifo_data[30] +.sym 17605 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 17606 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 17607 w_rx_09_fifo_data[29] +.sym 17608 io_pmod_in[2]$SB_IO_IN +.sym 17610 w_tx_data_smi[2] +.sym 17613 w_rx_data[1] +.sym 17621 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 17624 w_rx_sync_24 +.sym 17630 lvds_rx_24_inst.r_sync_input_SB_DFFER_Q_E +.sym 17631 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 17632 w_rx_24_fifo_data[16] +.sym 17634 io_pmod_in[2]$SB_IO_IN +.sym 17636 w_rx_09_fifo_data[16] +.sym 17639 i_rst_b_SB_LUT4_I3_O +.sym 17640 channel +.sym 17647 w_rx_sync_type_24 +.sym 17658 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 17659 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 17670 w_rx_sync_24 +.sym 17671 io_pmod_in[2]$SB_IO_IN +.sym 17672 w_rx_sync_type_24 +.sym 17689 channel +.sym 17690 w_rx_24_fifo_data[16] +.sym 17691 w_rx_09_fifo_data[16] +.sym 17698 lvds_rx_24_inst.r_sync_input_SB_DFFER_Q_E +.sym 17699 lvds_clock_buf +.sym 17700 i_rst_b_SB_LUT4_I3_O +.sym 17702 r_tx_data[3] +.sym 17704 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 17713 lvds_tx_inst.r_tx_state +.sym 17717 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 17719 w_rx_24_fifo_data[7] +.sym 17720 w_rx_sync_24 +.sym 17721 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 17722 $PACKER_VCC_NET +.sym 17723 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 17725 w_rx_09_fifo_data[7] +.sym 17726 spi_if_ins.w_rx_data[6] +.sym 17727 w_tx_data_io[7] +.sym 17729 r_counter +.sym 17730 w_tx_data_smi[0] +.sym 17732 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 17742 r_counter +.sym 17744 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 17759 r_tx_data[0] +.sym 17760 r_tx_data[1] +.sym 17763 r_tx_data[6] +.sym 17767 r_tx_data[3] +.sym 17769 r_tx_data[5] +.sym 17770 r_tx_data[4] +.sym 17772 r_tx_data[2] +.sym 17773 r_tx_data[7] +.sym 17777 r_tx_data[5] +.sym 17781 r_tx_data[4] +.sym 17788 r_tx_data[0] +.sym 17796 r_tx_data[1] +.sym 17800 r_tx_data[6] +.sym 17806 r_tx_data[7] +.sym 17811 r_tx_data[3] +.sym 17819 r_tx_data[2] +.sym 17821 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 17822 r_counter +.sym 17824 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +.sym 17825 r_tx_data[0] +.sym 17826 r_tx_data[1] +.sym 17827 r_tx_data[5] +.sym 17828 r_tx_data[4] +.sym 17829 r_tx_data[6] +.sym 17830 r_tx_data[2] +.sym 17831 r_tx_data[7] +.sym 17832 spi_if_ins.r_tx_byte[6] +.sym 17836 spi_if_ins.r_tx_byte[5] +.sym 17838 spi_if_ins.r_tx_byte[7] +.sym 17840 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 17841 $PACKER_VCC_NET +.sym 17842 spi_if_ins.r_tx_byte[0] +.sym 17844 spi_if_ins.r_tx_byte[1] +.sym 17847 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17849 i_rst_b_SB_LUT4_I3_O +.sym 17850 i_button_SB_LUT4_I2_I1[2] +.sym 17851 w_rx_data[1] +.sym 17853 w_tx_data_io[1] +.sym 17854 tx_wr_data[14] +.sym 17856 w_tx_data_sys[5] +.sym 17857 io_ctrl_ins.rf_pin_state[0] +.sym 17858 w_tx_data_sys[3] +.sym 17865 w_tx_data_smi[1] +.sym 17866 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 17869 spi_if_ins.o_cs_SB_LUT4_I2_1_O[0] +.sym 17870 i_rst_b$SB_IO_IN +.sym 17871 w_tx_data_io[2] +.sym 17873 w_tx_data_smi[4] +.sym 17877 w_tx_data_io[1] +.sym 17878 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 17879 w_tx_data_io[5] +.sym 17880 w_cs[0] +.sym 17881 w_cs[1] +.sym 17882 w_tx_data_smi[2] +.sym 17883 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 17885 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17886 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 17888 w_cs[3] +.sym 17891 w_rx_09_fifo_data[28] +.sym 17893 w_cs[2] +.sym 17895 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 17896 w_tx_data_io[4] +.sym 17899 i_rst_b$SB_IO_IN +.sym 17900 spi_if_ins.o_cs_SB_LUT4_I2_1_O[0] +.sym 17904 w_rx_09_fifo_data[28] +.sym 17906 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 17910 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17911 w_tx_data_smi[4] +.sym 17912 w_tx_data_io[4] +.sym 17913 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 17916 w_tx_data_smi[2] +.sym 17917 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17918 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 17919 w_tx_data_io[2] +.sym 17922 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17923 w_tx_data_io[1] +.sym 17924 w_tx_data_smi[1] +.sym 17925 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 17928 w_tx_data_io[5] +.sym 17929 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17930 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 17940 w_cs[2] +.sym 17941 w_cs[1] +.sym 17942 w_cs[3] +.sym 17943 w_cs[0] +.sym 17944 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 17945 lvds_clock_buf +.sym 17946 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 17947 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 17948 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 17949 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[2] +.sym 17950 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 17951 o_led1$SB_IO_OUT +.sym 17952 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 17954 o_led0$SB_IO_OUT +.sym 17966 i_rst_b_SB_LUT4_I3_O +.sym 17968 w_fetch +.sym 17969 i_sck$SB_IO_IN +.sym 17970 i_rst_b_SB_LUT4_I3_O +.sym 17971 w_rx_sync_type_24 +.sym 17972 o_led1$SB_IO_OUT +.sym 17973 w_tx_data_io[3] +.sym 17974 w_cs[3] +.sym 17978 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 17989 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] +.sym 17990 w_cs[2] +.sym 17993 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 17995 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 17997 r_counter +.sym 17999 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 18000 w_cs[1] +.sym 18001 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18003 w_cs[3] +.sym 18005 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] +.sym 18009 w_cs[0] +.sym 18010 i_button_SB_LUT4_I2_I1[0] +.sym 18012 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 18013 i_button_SB_LUT4_I2_I1[1] +.sym 18015 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18017 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 18018 i_button_SB_LUT4_I2_I1[2] +.sym 18027 w_cs[1] +.sym 18028 w_cs[3] +.sym 18029 w_cs[0] +.sym 18030 w_cs[2] +.sym 18033 i_button_SB_LUT4_I2_I1[1] +.sym 18034 i_button_SB_LUT4_I2_I1[2] +.sym 18035 i_button_SB_LUT4_I2_I1[0] +.sym 18039 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 18040 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18041 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 18045 w_cs[3] +.sym 18046 w_cs[1] +.sym 18047 w_cs[2] +.sym 18048 w_cs[0] +.sym 18052 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18058 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] +.sym 18060 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] +.sym 18063 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 18065 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 18067 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 18068 r_counter +.sym 18069 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 18070 w_tx_data_io[0] +.sym 18071 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] +.sym 18072 w_tx_data_io[1] +.sym 18073 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 18074 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3] +.sym 18076 i_button_SB_LUT4_I2_I1[0] +.sym 18077 w_tx_data_io[3] +.sym 18083 r_counter +.sym 18084 r_counter +.sym 18086 spi_if_ins.spi.SCKr[1] +.sym 18087 w_tx_data_io[5] +.sym 18088 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 18089 i_rst_b_SB_LUT4_I3_O +.sym 18091 i_ss_SB_LUT4_I3_O +.sym 18093 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] +.sym 18094 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 18096 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18097 w_ioc[2] +.sym 18098 io_ctrl_ins.debug_mode[1] +.sym 18100 w_ioc[0] +.sym 18101 w_rx_data[1] +.sym 18102 io_ctrl_ins.debug_mode[0] +.sym 18103 w_ioc[2] +.sym 18104 i_button_SB_LUT4_I2_I1[2] +.sym 18105 o_tr_vc1_b$SB_IO_OUT +.sym 18111 r_counter +.sym 18112 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 18114 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18118 w_ioc[0] +.sym 18122 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 18127 w_tx_data_io[0] +.sym 18131 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 18132 spi_if_ins.w_rx_data[5] +.sym 18133 spi_if_ins.w_rx_data[6] +.sym 18139 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 18157 spi_if_ins.w_rx_data[5] +.sym 18158 spi_if_ins.w_rx_data[6] +.sym 18169 spi_if_ins.w_rx_data[5] +.sym 18170 spi_if_ins.w_rx_data[6] +.sym 18174 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18176 w_ioc[0] +.sym 18180 w_tx_data_io[0] +.sym 18181 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 18183 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 18186 spi_if_ins.w_rx_data[5] +.sym 18187 spi_if_ins.w_rx_data[6] +.sym 18190 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 18191 r_counter +.sym 18192 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 18193 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3] +.sym 18195 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 18196 io_ctrl_ins.pmod_dir_state[4] +.sym 18197 io_ctrl_ins.pmod_dir_state[3] +.sym 18198 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 18199 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 18200 io_ctrl_ins.pmod_dir_state[1] +.sym 18206 w_rx_data[5] +.sym 18207 w_rx_data[7] +.sym 18208 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 18209 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 18210 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] +.sym 18211 r_counter +.sym 18212 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 18213 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 18214 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 18216 w_fetch +.sym 18217 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] +.sym 18218 w_rx_data[3] +.sym 18219 spi_if_ins.w_rx_data[6] +.sym 18220 r_counter +.sym 18221 tx_fifo.rd_addr[4] +.sym 18222 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 18223 w_fetch +.sym 18224 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18228 w_rx_data[4] +.sym 18234 w_load +.sym 18235 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18236 io_ctrl_ins.debug_mode[1] +.sym 18237 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18238 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 18239 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 18241 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 18242 i_rst_b$SB_IO_IN +.sym 18243 w_ioc[0] +.sym 18245 w_fetch +.sym 18246 w_cs[1] +.sym 18247 i_button_SB_LUT4_I2_I1[2] +.sym 18248 i_button_SB_LUT4_I2_I1[0] +.sym 18249 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 18252 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 18255 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 18256 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18257 o_tr_vc2$SB_IO_OUT +.sym 18258 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18259 r_counter +.sym 18260 w_ioc[0] +.sym 18262 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 18263 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18264 io_ctrl_ins.pmod_state[3] +.sym 18265 o_tr_vc1_b$SB_IO_OUT +.sym 18267 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18270 w_ioc[0] +.sym 18273 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 18275 i_rst_b$SB_IO_IN +.sym 18276 io_ctrl_ins.debug_mode[1] +.sym 18279 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 18280 i_button_SB_LUT4_I2_I1[0] +.sym 18281 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 18282 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 18285 io_ctrl_ins.pmod_state[3] +.sym 18286 w_ioc[0] +.sym 18287 o_tr_vc2$SB_IO_OUT +.sym 18288 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18297 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 18298 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 18299 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18300 o_tr_vc1_b$SB_IO_OUT +.sym 18303 w_fetch +.sym 18304 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 18305 w_load +.sym 18306 w_cs[1] +.sym 18309 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18310 i_button_SB_LUT4_I2_I1[2] +.sym 18311 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18313 io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 18314 r_counter +.sym 18316 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18317 o_shdn_tx_lna$SB_IO_OUT +.sym 18318 o_shdn_rx_lna$SB_IO_OUT +.sym 18319 o_rx_h_tx_l$SB_IO_OUT +.sym 18320 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O +.sym 18321 o_tr_vc1_b$SB_IO_OUT +.sym 18322 o_tr_vc1$SB_IO_OUT +.sym 18323 o_tr_vc2$SB_IO_OUT +.sym 18324 w_load +.sym 18328 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 18329 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 18330 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 18332 i_rst_b_SB_LUT4_I3_O +.sym 18335 r_counter +.sym 18337 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 18338 w_load +.sym 18339 r_counter +.sym 18340 io_ctrl_ins.rf_pin_state[2] +.sym 18341 i_config[1]$SB_IO_IN +.sym 18342 i_button_SB_LUT4_I2_I1[2] +.sym 18344 io_ctrl_ins.rf_pin_state[0] +.sym 18346 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 18349 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18351 w_rx_data[1] +.sym 18359 w_rx_data[2] +.sym 18361 w_rx_data[0] +.sym 18364 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 18370 i_rst_b_SB_LUT4_I3_O +.sym 18371 w_rx_data[1] +.sym 18373 r_counter +.sym 18376 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18377 io_ctrl_ins.debug_mode[0] +.sym 18378 w_rx_data[3] +.sym 18382 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18383 io_ctrl_ins.debug_mode[1] +.sym 18384 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 18386 i_button_SB_LUT4_I2_I1[2] +.sym 18388 w_rx_data[4] +.sym 18390 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18391 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 18392 i_button_SB_LUT4_I2_I1[2] +.sym 18393 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18396 w_rx_data[3] +.sym 18403 w_rx_data[1] +.sym 18408 io_ctrl_ins.debug_mode[1] +.sym 18411 io_ctrl_ins.debug_mode[0] +.sym 18414 w_rx_data[0] +.sym 18423 w_rx_data[4] +.sym 18426 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18427 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18428 i_button_SB_LUT4_I2_I1[2] +.sym 18429 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 18433 w_rx_data[2] +.sym 18436 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 18437 r_counter +.sym 18438 i_rst_b_SB_LUT4_I3_O +.sym 18439 io_ctrl_ins.rf_pin_state[0] +.sym 18440 io_ctrl_ins.rf_pin_state[5] +.sym 18441 io_ctrl_ins.rf_pin_state[3] +.sym 18442 io_ctrl_ins.rf_pin_state[6] +.sym 18443 io_ctrl_ins.rf_pin_state[1] +.sym 18444 io_ctrl_ins.rf_pin_state[4] +.sym 18445 io_ctrl_ins.rf_pin_state[2] +.sym 18446 io_ctrl_ins.rf_pin_state[7] +.sym 18452 w_fetch +.sym 18454 o_rx_h_tx_l$SB_IO_OUT +.sym 18456 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 18460 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 18462 o_shdn_rx_lna$SB_IO_OUT +.sym 18467 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O +.sym 18471 w_rx_data[5] +.sym 18474 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O +.sym 18480 r_counter +.sym 18481 o_shdn_tx_lna$SB_IO_OUT +.sym 18482 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 18483 w_rx_data[0] +.sym 18487 io_ctrl_ins.pmod_state[2] +.sym 18490 o_shdn_rx_lna$SB_IO_OUT +.sym 18492 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 18500 w_ioc[0] +.sym 18501 io_ctrl_ins.pmod_state[1] +.sym 18503 w_rx_data[2] +.sym 18507 w_rx_data[3] +.sym 18509 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18511 w_rx_data[1] +.sym 18513 w_ioc[0] +.sym 18514 o_shdn_rx_lna$SB_IO_OUT +.sym 18515 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18516 io_ctrl_ins.pmod_state[1] +.sym 18520 r_counter +.sym 18525 w_ioc[0] +.sym 18526 o_shdn_tx_lna$SB_IO_OUT +.sym 18527 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18528 io_ctrl_ins.pmod_state[2] +.sym 18532 w_rx_data[3] +.sym 18537 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 18539 w_ioc[0] +.sym 18540 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 18546 w_rx_data[1] +.sym 18550 w_rx_data[0] +.sym 18555 w_rx_data[2] +.sym 18559 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 18560 r_counter .sym 18562 i_config[1]$SB_IO_IN .sym 18564 i_config[2]$SB_IO_IN +.sym 18570 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 18574 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 18575 w_rx_data[0] +.sym 18582 w_ioc[0] +.sym 18631 i_config[3]$SB_IO_IN +.sym 18633 i_button$SB_IO_IN .sym 18636 w_smi_data_output[4] .sym 18638 w_smi_data_direction -.sym 18639 o_smi_write_req$SB_IO_OUT .sym 18642 $PACKER_VCC_NET -.sym 18648 w_smi_data_direction -.sym 18656 w_smi_data_output[4] -.sym 18657 o_smi_write_req$SB_IO_OUT -.sym 18658 $PACKER_VCC_NET +.sym 18647 w_smi_data_output[4] +.sym 18650 $PACKER_VCC_NET +.sym 18652 w_smi_data_direction +.sym 18662 w_rx_fifo_pulled_data[0] +.sym 18666 w_rx_fifo_pulled_data[2] +.sym 18671 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 18673 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 18679 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 18684 w_rx_data[1] +.sym 18690 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 18693 i_sck$SB_IO_IN .sym 18694 $PACKER_VCC_NET -.sym 18696 w_smi_data_direction -.sym 18704 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 18705 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 18709 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 18714 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18728 tx_fifo.wr_addr[0] -.sym 18743 tx_fifo.wr_addr[0] -.sym 18750 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 18757 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 18780 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 18782 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18783 r_counter_$glb_clk -.sym 18784 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 18695 i_ss$SB_IO_IN +.sym 18696 o_smi_read_req$SB_IO_OUT +.sym 18703 r_counter +.sym 18705 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 18710 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 18712 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 18714 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 18716 i_rst_b_SB_LUT4_I3_O +.sym 18720 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 18722 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 18723 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 18724 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 18725 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 18726 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 18736 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 18737 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 18738 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 18739 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 18742 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 18748 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 18756 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 18757 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 18763 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 18766 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 18772 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 18779 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 18780 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 18782 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 18783 r_counter +.sym 18784 i_rst_b_SB_LUT4_I3_O .sym 18785 i_smi_soe_se$SB_IO_IN -.sym 18800 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 18804 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18818 w_smi_data_input[7] -.sym 18842 w_smi_data_output[5] +.sym 18787 w_smi_data_input[5] +.sym 18790 w_rx_fifo_pulled_data[1] +.sym 18794 w_rx_fifo_pulled_data[3] +.sym 18797 rx_fifo.rd_addr[3] +.sym 18803 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 18804 rx_fifo.wr_addr[4] +.sym 18805 w_rx_fifo_data[0] +.sym 18806 rx_fifo.wr_addr[9] +.sym 18811 rx_fifo.rd_addr_gray_wr_r[0] +.sym 18818 rx_fifo.wr_addr[0] +.sym 18820 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 18823 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 18824 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 18825 rx_fifo.wr_addr[8] +.sym 18826 rx_fifo.rd_addr[0] +.sym 18827 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 18828 rx_fifo.rd_addr[8] +.sym 18829 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 18831 rx_fifo.rd_addr[3] +.sym 18832 w_rx_fifo_pulled_data[2] +.sym 18833 rx_fifo.wr_addr[5] +.sym 18836 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 18838 w_rx_fifo_pulled_data[1] +.sym 18839 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 18840 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 18841 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] .sym 18843 $PACKER_VCC_NET -.sym 18844 tx_fifo.wr_addr[2] -.sym 18845 tx_fifo.rd_addr_gray_wr_r[8] -.sym 18846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18848 i_smi_soe_se$SB_IO_IN -.sym 18868 tx_fifo.wr_addr[2] -.sym 18869 tx_fifo.wr_addr[6] -.sym 18871 tx_fifo.wr_addr[3] -.sym 18872 tx_fifo.wr_addr[4] -.sym 18873 tx_fifo.wr_addr[7] -.sym 18878 tx_fifo.wr_addr[5] -.sym 18880 tx_fifo.wr_addr[8] -.sym 18881 tx_fifo.wr_addr[1] -.sym 18898 $nextpnr_ICESTORM_LC_2$O -.sym 18901 tx_fifo.wr_addr[1] -.sym 18904 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18906 tx_fifo.wr_addr[2] -.sym 18908 tx_fifo.wr_addr[1] -.sym 18910 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18912 tx_fifo.wr_addr[3] -.sym 18914 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18918 tx_fifo.wr_addr[4] -.sym 18920 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18924 tx_fifo.wr_addr[5] -.sym 18926 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18931 tx_fifo.wr_addr[6] -.sym 18932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18936 tx_fifo.wr_addr[7] -.sym 18938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 18940 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 18943 tx_fifo.wr_addr[8] -.sym 18944 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 18949 w_rx_fifo_pulled_data[12] -.sym 18953 w_rx_fifo_pulled_data[14] -.sym 18960 i_ss$SB_IO_IN -.sym 18978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18979 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 18981 rx_fifo.wr_addr[6] -.sym 18983 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 18984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 18990 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 18994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 18995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 18996 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 18998 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19000 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19003 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19005 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 19006 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 19009 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 19011 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 19015 tx_fifo.wr_addr[9] -.sym 19019 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 19020 i_rst_b$SB_IO_IN -.sym 19023 tx_fifo.wr_addr[9] -.sym 19025 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 19030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 19034 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 19042 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 19047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 19048 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19049 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 19053 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 19054 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 19055 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19060 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 19065 i_rst_b$SB_IO_IN -.sym 19067 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 19068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 19069 r_counter_$glb_clk -.sym 19070 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19072 w_rx_fifo_pulled_data[13] -.sym 19076 w_rx_fifo_pulled_data[15] -.sym 19081 w_rx_data[3] -.sym 19086 rx_fifo.wr_addr[3] -.sym 19096 rx_fifo.mem_q.0.3_WDATA_2 -.sym 19099 w_smi_read_req -.sym 19101 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 19106 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 19112 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 19113 smi_ctrl_ins.r_fifo_push_1 -.sym 19114 w_tx_fifo_full -.sym 19115 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] -.sym 19117 smi_ctrl_ins.r_fifo_push -.sym 19118 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19119 tx_fifo.rd_addr_gray_wr_r[1] -.sym 19120 tx_fifo.wr_addr[2] -.sym 19122 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 19125 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] -.sym 19126 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] -.sym 19131 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19132 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 19133 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 19135 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 19136 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] -.sym 19137 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 19141 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 19142 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 19143 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 19145 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 19146 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19147 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 19148 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 19151 smi_ctrl_ins.r_fifo_push -.sym 19157 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 19158 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 19159 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 19160 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 19163 tx_fifo.wr_addr[2] -.sym 19164 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 19165 tx_fifo.rd_addr_gray_wr_r[1] -.sym 19169 w_tx_fifo_full -.sym 19170 smi_ctrl_ins.r_fifo_push_1 -.sym 19172 smi_ctrl_ins.r_fifo_push -.sym 19175 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 19176 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 19178 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19181 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] -.sym 19182 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] -.sym 19183 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] -.sym 19184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] -.sym 19187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 19190 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 19192 r_counter_$glb_clk -.sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19195 w_rx_fifo_pulled_data[16] -.sym 19199 w_rx_fifo_pulled_data[18] -.sym 19205 w_rx_data[0] -.sym 19213 rx_fifo.rd_addr[0] -.sym 19214 tx_fifo.rd_addr_gray_wr_r[8] -.sym 19215 rx_fifo.mem_q.0.3_WDATA_1 -.sym 19217 $PACKER_VCC_NET -.sym 19219 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 19220 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 19221 w_rx_fifo_pulled_data[18] -.sym 19223 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 19224 o_smi_read_req$SB_IO_OUT -.sym 19225 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 19227 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 19229 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 19237 w_tx_fifo_full -.sym 19244 i_sck$SB_IO_IN -.sym 19245 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19246 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19248 i_ss$SB_IO_IN -.sym 19254 w_smi_data_direction -.sym 19259 w_smi_read_req -.sym 19260 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19267 $nextpnr_ICESTORM_LC_4$O -.sym 19270 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19273 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 19275 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19277 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19281 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19283 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 19289 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19310 w_smi_read_req -.sym 19312 w_smi_data_direction -.sym 19313 w_tx_fifo_full -.sym 19315 i_sck$SB_IO_IN -.sym 19316 i_ss$SB_IO_IN -.sym 19318 w_rx_fifo_pulled_data[17] -.sym 19322 w_rx_fifo_pulled_data[19] -.sym 19327 w_rx_data[5] -.sym 19335 rx_fifo.wr_addr[5] -.sym 19338 rx_fifo.wr_addr[9] -.sym 19339 rx_fifo.wr_addr[0] -.sym 19340 rx_fifo.wr_addr[3] -.sym 19341 $PACKER_VCC_NET -.sym 19344 w_rx_fifo_pulled_data[29] -.sym 19347 $PACKER_VCC_NET -.sym 19350 i_smi_soe_se$SB_IO_IN -.sym 19352 w_rx_fifo_pulled_data[31] -.sym 19359 w_rx_fifo_pulled_data[31] -.sym 19368 w_rx_fifo_pulled_data[29] -.sym 19375 w_rx_fifo_pulled_data[28] -.sym 19379 w_rx_fifo_pulled_data[19] -.sym 19383 w_rx_fifo_pulled_data[17] -.sym 19387 w_rx_fifo_pulled_data[30] -.sym 19394 w_rx_fifo_pulled_data[28] -.sym 19398 w_rx_fifo_pulled_data[17] -.sym 19409 w_rx_fifo_pulled_data[29] -.sym 19415 w_rx_fifo_pulled_data[30] -.sym 19421 w_rx_fifo_pulled_data[19] -.sym 19435 w_rx_fifo_pulled_data[31] -.sym 19437 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce -.sym 19438 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 19439 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 18844 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 18845 rx_fifo.rd_addr[8] +.sym 18847 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 18849 rx_fifo.rd_addr[3] +.sym 18850 w_rx_fifo_pulled_data[16] +.sym 18851 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 18852 r_counter +.sym 18853 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 18855 $PACKER_VCC_NET +.sym 18866 r_counter +.sym 18868 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[0] +.sym 18869 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 18870 rx_fifo.rd_addr[0] +.sym 18873 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 18874 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[1] +.sym 18875 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 18876 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 18877 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 18879 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 18880 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 18881 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 18886 i_rst_b_SB_LUT4_I3_O +.sym 18890 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 18896 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[2] +.sym 18899 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[0] +.sym 18900 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[2] +.sym 18902 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[1] +.sym 18905 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 18907 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 18913 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 18917 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 18923 rx_fifo.rd_addr[0] +.sym 18929 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 18935 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 18936 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 18938 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 18942 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 18943 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 18945 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 18946 r_counter +.sym 18947 i_rst_b_SB_LUT4_I3_O +.sym 18949 w_rx_fifo_pulled_data[16] +.sym 18953 w_rx_fifo_pulled_data[18] +.sym 18965 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 18970 rx_fifo.rd_addr[0] +.sym 18972 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 18973 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 18974 rx_fifo.wr_addr[2] +.sym 18975 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 18976 rx_fifo.wr_addr[3] +.sym 18977 rx_fifo.rd_addr[0] +.sym 18978 w_rx_fifo_pulled_data[17] +.sym 18979 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 18980 rx_fifo.wr_addr[6] +.sym 18981 w_rx_fifo_data[1] +.sym 18982 rx_fifo.wr_addr[8] +.sym 18983 rx_fifo.rd_addr_gray_wr_r[7] +.sym 18989 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 18993 rx_fifo.rd_addr_gray_wr[4] +.sym 18996 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 18998 rx_fifo.rd_addr_gray[7] +.sym 19001 rx_fifo.wr_addr_gray_rd_r[7] +.sym 19002 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 19004 rx_fifo.wr_addr_gray_rd_r[2] +.sym 19006 rx_fifo.rd_addr_gray[5] +.sym 19008 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 19009 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 19010 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 19012 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 19015 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 19017 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 19024 rx_fifo.rd_addr_gray[7] +.sym 19034 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 19035 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 19036 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 19037 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 19040 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 19042 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 19046 rx_fifo.rd_addr_gray_wr[4] +.sym 19054 rx_fifo.rd_addr_gray[5] +.sym 19059 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 19060 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 19061 rx_fifo.wr_addr_gray_rd_r[7] +.sym 19064 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 19066 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 19067 rx_fifo.wr_addr_gray_rd_r[2] +.sym 19069 lvds_clock_buf +.sym 19072 w_rx_fifo_pulled_data[17] +.sym 19076 w_rx_fifo_pulled_data[19] +.sym 19083 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 19088 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 19091 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 19093 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 19094 rx_fifo.wr_addr[0] +.sym 19096 rx_fifo.wr_addr[0] +.sym 19098 w_rx_fifo_pull +.sym 19099 rx_fifo.rd_addr[0] +.sym 19100 channel +.sym 19101 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 19102 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 19103 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 19104 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 19105 rx_fifo.rd_addr[8] +.sym 19106 rx_fifo.wr_addr[4] +.sym 19114 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 19116 channel +.sym 19117 rx_fifo.rd_addr_gray_wr[5] +.sym 19118 rx_fifo.wr_addr[0] +.sym 19120 rx_fifo.rd_addr_gray_wr[7] +.sym 19122 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] +.sym 19125 rx_fifo.rd_addr_gray_wr_r[0] +.sym 19126 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 19127 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 19132 w_rx_09_fifo_data[19] +.sym 19140 w_rx_24_fifo_data[19] +.sym 19152 rx_fifo.wr_addr[0] +.sym 19154 rx_fifo.rd_addr_gray_wr_r[0] +.sym 19158 rx_fifo.rd_addr_gray_wr[5] +.sym 19165 rx_fifo.rd_addr_gray_wr[7] +.sym 19169 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 19170 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 19171 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 19172 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] +.sym 19176 channel +.sym 19177 w_rx_24_fifo_data[19] +.sym 19178 w_rx_09_fifo_data[19] +.sym 19192 lvds_clock_buf +.sym 19195 w_rx_fifo_pulled_data[24] +.sym 19199 w_rx_fifo_pulled_data[26] +.sym 19215 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 19218 rx_fifo.wr_addr[6] +.sym 19219 rx_fifo.rd_addr_gray_wr_r[5] +.sym 19220 rx_fifo.wr_addr[8] +.sym 19221 w_rx_fifo_pulled_data[26] +.sym 19222 smi_ctrl_ins.soe_and_reset +.sym 19223 rx_fifo.rd_addr[3] +.sym 19224 rx_fifo.wr_addr[5] +.sym 19226 w_tx_fifo_pulled_data[12] +.sym 19227 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 19228 rx_fifo.wr_addr[2] +.sym 19229 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 19237 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 19238 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 19239 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 19240 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 19241 rx_fifo.wr_addr[0] +.sym 19244 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 19249 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 19251 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 19253 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 19255 i_rst_b_SB_LUT4_I3_O +.sym 19270 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 19275 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 19281 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 19289 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 19293 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 19299 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 19304 rx_fifo.wr_addr[0] +.sym 19310 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 19314 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 19315 lvds_clock_buf +.sym 19316 i_rst_b_SB_LUT4_I3_O +.sym 19318 w_rx_fifo_pulled_data[25] +.sym 19322 w_rx_fifo_pulled_data[27] +.sym 19329 rx_fifo.wr_addr[7] +.sym 19332 w_rx_fifo_data[24] +.sym 19335 rx_fifo.wr_addr[9] +.sym 19337 w_rx_fifo_data[26] +.sym 19338 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 19340 i_rst_b_SB_LUT4_I3_O +.sym 19341 r_counter +.sym 19342 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 19343 rx_fifo.rd_addr[8] +.sym 19344 rx_fifo.wr_addr[4] +.sym 19346 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 19347 rx_fifo.rd_addr[3] +.sym 19348 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 19349 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 19350 rx_fifo.wr_addr[0] +.sym 19351 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 19352 $PACKER_VCC_NET +.sym 19358 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 19360 rx_fifo.wr_addr[3] +.sym 19361 rx_fifo.wr_addr[4] +.sym 19362 rx_fifo.wr_addr[6] +.sym 19363 rx_fifo.wr_addr[8] +.sym 19367 rx_fifo.wr_addr[2] +.sym 19371 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 19373 rx_fifo.wr_addr[5] +.sym 19379 rx_fifo.wr_addr[7] +.sym 19390 $nextpnr_ICESTORM_LC_3$O +.sym 19393 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 19396 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 19398 rx_fifo.wr_addr[2] +.sym 19400 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 19402 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 19405 rx_fifo.wr_addr[3] +.sym 19406 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 19408 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 19411 rx_fifo.wr_addr[4] +.sym 19412 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 19414 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 19417 rx_fifo.wr_addr[5] +.sym 19418 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 19420 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 19422 rx_fifo.wr_addr[6] +.sym 19424 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 19426 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 19428 rx_fifo.wr_addr[7] +.sym 19430 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 19432 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 19435 rx_fifo.wr_addr[8] +.sym 19436 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] .sym 19441 w_rx_fifo_pulled_data[28] .sym 19445 w_rx_fifo_pulled_data[30] -.sym 19450 o_led1_SB_LUT4_I1_I3[3] -.sym 19464 rx_fifo.mem_i.0.3_WDATA_1 -.sym 19473 rx_fifo.wr_addr[6] -.sym 19475 rx_fifo.mem_i.0.0_WDATA_1 -.sym 19481 i_mosi$SB_IO_IN -.sym 19483 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 19485 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 19487 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 19489 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 19490 i_sck$SB_IO_IN -.sym 19491 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 19492 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 19493 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 19495 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 19516 i_mosi$SB_IO_IN -.sym 19520 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 19527 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 19533 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 19540 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 19546 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 19551 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 19557 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 19560 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 19561 i_sck$SB_IO_IN +.sym 19452 i_mosi$SB_IO_IN +.sym 19453 io_pmod_in[3]$SB_IO_IN +.sym 19454 lvds_tx_inst.r_state_SB_DFFER_Q_E +.sym 19455 w_rx_fifo_data[25] +.sym 19456 w_tx_fsm_state[1] +.sym 19461 w_rx_fifo_pulled_data[25] +.sym 19462 w_rx_24_fifo_data[21] +.sym 19464 rx_fifo.wr_addr[3] +.sym 19465 rx_fifo.rd_addr[0] +.sym 19466 w_rx_fifo_push +.sym 19470 w_rx_fifo_pulled_data[29] +.sym 19471 rx_fifo.wr_addr[2] +.sym 19472 rx_fifo.wr_addr[6] +.sym 19473 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 19474 rx_fifo.wr_addr[8] +.sym 19475 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 19476 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 19481 r_counter +.sym 19483 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 19484 rx_fifo.rd_addr_gray_wr_r[7] +.sym 19487 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 19488 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 19489 rx_fifo.rd_addr_gray_wr_r[5] +.sym 19490 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 19491 rx_fifo.wr_addr[9] +.sym 19492 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 19493 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.sym 19494 spi_if_ins.w_rx_data[1] +.sym 19496 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 19497 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 19500 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 19502 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 19504 rx_fifo.rd_addr_gray_wr_r[2] +.sym 19508 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 19515 rx_fifo.wr_addr[9] +.sym 19517 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 19526 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 19527 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 19528 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 19529 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.sym 19533 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 19534 rx_fifo.rd_addr_gray_wr_r[2] +.sym 19535 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 19538 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 19539 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 19540 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 19541 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 19547 spi_if_ins.w_rx_data[1] +.sym 19551 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.sym 19553 rx_fifo.rd_addr_gray_wr_r[5] +.sym 19556 rx_fifo.rd_addr_gray_wr_r[7] +.sym 19557 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 19559 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 19560 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 19561 r_counter .sym 19564 w_rx_fifo_pulled_data[29] .sym 19568 w_rx_fifo_pulled_data[31] -.sym 19575 i_mosi$SB_IO_IN -.sym 19577 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 19585 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 19587 rx_fifo.rd_addr[9] -.sym 19589 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 19591 spi_if_ins.w_rx_data[1] -.sym 19592 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 19593 spi_if_ins.w_rx_data[3] -.sym 19595 spi_if_ins.w_rx_data[2] -.sym 19597 spi_if_ins.w_rx_data[6] -.sym 19598 rx_fifo.mem_i.0.3_WDATA -.sym 19604 spi_if_ins.spi.r_rx_byte[0] -.sym 19607 spi_if_ins.spi.r_rx_byte[4] -.sym 19608 spi_if_ins.spi.r_rx_byte[5] -.sym 19610 spi_if_ins.spi.r_rx_byte[1] -.sym 19613 spi_if_ins.spi.r_rx_byte[7] -.sym 19614 spi_if_ins.spi.r_rx_byte[2] -.sym 19615 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19617 spi_if_ins.spi.r_rx_byte[3] -.sym 19619 spi_if_ins.spi.r_rx_byte[6] -.sym 19640 spi_if_ins.spi.r_rx_byte[2] -.sym 19646 spi_if_ins.spi.r_rx_byte[6] -.sym 19649 spi_if_ins.spi.r_rx_byte[0] -.sym 19655 spi_if_ins.spi.r_rx_byte[4] -.sym 19663 spi_if_ins.spi.r_rx_byte[5] -.sym 19668 spi_if_ins.spi.r_rx_byte[7] -.sym 19673 spi_if_ins.spi.r_rx_byte[1] -.sym 19682 spi_if_ins.spi.r_rx_byte[3] -.sym 19683 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19684 r_counter_$glb_clk -.sym 19697 w_rx_data[4] -.sym 19699 i_glob_clock$SB_IO_IN -.sym 19709 rx_fifo.rd_addr[0] -.sym 19710 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 19711 w_rx_data[0] -.sym 19713 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 19714 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 19717 o_led0_SB_LUT4_I1_O[1] -.sym 19720 rx_fifo.rd_addr[2] -.sym 19721 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 19740 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 19742 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 19745 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 19746 spi_if_ins.r_tx_byte[5] -.sym 19747 spi_if_ins.spi.r_tx_byte[5] -.sym 19748 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 19751 spi_if_ins.spi.r_tx_bit_count[0] -.sym 19753 spi_if_ins.spi.r_tx_byte[7] -.sym 19758 spi_if_ins.r_tx_byte[7] -.sym 19774 spi_if_ins.r_tx_byte[7] -.sym 19780 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 19787 spi_if_ins.r_tx_byte[5] -.sym 19790 spi_if_ins.spi.r_tx_byte[7] -.sym 19791 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 19792 spi_if_ins.spi.r_tx_bit_count[0] -.sym 19793 spi_if_ins.spi.r_tx_byte[5] -.sym 19806 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 19807 r_counter_$glb_clk -.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O -.sym 19825 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 19829 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19834 w_cs[2] -.sym 19835 w_rx_data[3] -.sym 19837 w_rx_data[0] -.sym 19840 w_cs[1] -.sym 19843 o_led0_SB_LUT4_I1_O[1] -.sym 19850 spi_if_ins.w_rx_data[5] -.sym 19851 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 19854 spi_if_ins.w_rx_data[0] -.sym 19856 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 19859 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 19860 spi_if_ins.w_rx_data[6] -.sym 19861 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 19863 spi_if_ins.w_rx_data[1] -.sym 19864 spi_if_ins.w_rx_data[4] -.sym 19865 spi_if_ins.w_rx_data[3] -.sym 19868 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 19885 spi_if_ins.w_rx_data[1] -.sym 19889 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 19890 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 19892 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 19898 spi_if_ins.w_rx_data[4] -.sym 19902 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 19909 spi_if_ins.w_rx_data[5] -.sym 19910 spi_if_ins.w_rx_data[6] -.sym 19916 spi_if_ins.w_rx_data[3] -.sym 19919 spi_if_ins.w_rx_data[0] -.sym 19926 spi_if_ins.w_rx_data[5] -.sym 19929 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 19930 r_counter_$glb_clk -.sym 19949 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 19950 w_load -.sym 19952 w_rx_data[7] -.sym 19955 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 19957 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 19959 w_rx_data[7] -.sym 19963 w_fetch -.sym 19964 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 19977 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 19982 w_cs[1] -.sym 19984 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 19985 w_cs[3] -.sym 19986 spi_if_ins.w_rx_data[5] -.sym 19987 w_cs[2] -.sym 19988 spi_if_ins.w_rx_data[6] -.sym 19989 w_ioc[2] -.sym 19993 w_cs[0] -.sym 19995 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 19998 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 20000 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 20001 w_ioc[4] -.sym 20003 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 20004 w_ioc[3] -.sym 20006 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 20007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 20008 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 20013 spi_if_ins.w_rx_data[5] -.sym 20015 spi_if_ins.w_rx_data[6] -.sym 20024 w_cs[3] -.sym 20025 w_cs[1] -.sym 20026 w_cs[2] -.sym 20027 w_cs[0] -.sym 20030 spi_if_ins.w_rx_data[5] -.sym 20032 spi_if_ins.w_rx_data[6] -.sym 20037 w_ioc[3] -.sym 20038 w_ioc[4] -.sym 20039 w_ioc[2] -.sym 20042 spi_if_ins.w_rx_data[6] -.sym 20044 spi_if_ins.w_rx_data[5] -.sym 20049 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 20050 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 20051 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 20052 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 20053 r_counter_$glb_clk -.sym 20054 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 20071 w_cs[1] -.sym 20075 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 20076 o_led1$SB_IO_OUT -.sym 20079 w_rx_data[6] -.sym 20082 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 20086 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 20089 o_led1_SB_LUT4_I1_I3[0] -.sym 20090 o_led1_SB_LUT4_I1_I3[3] -.sym 20096 w_rx_data[1] -.sym 20099 io_ctrl_ins.pmod_dir_state[3] -.sym 20100 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 20102 w_rx_data[5] -.sym 20104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 20107 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 20108 w_rx_data[0] -.sym 20109 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 20110 w_rx_data[2] -.sym 20111 o_led1_SB_LUT4_I1_I3[3] -.sym 20116 io_ctrl_ins.pmod_dir_state[1] -.sym 20119 w_rx_data[7] -.sym 20121 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 20123 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20124 o_led1$SB_IO_OUT -.sym 20126 i_button_SB_LUT4_I0_I3[2] -.sym 20129 o_led1_SB_LUT4_I1_I3[3] -.sym 20130 o_led1$SB_IO_OUT -.sym 20131 io_ctrl_ins.pmod_dir_state[1] -.sym 20132 i_button_SB_LUT4_I0_I3[2] -.sym 20135 w_rx_data[0] -.sym 20142 w_rx_data[2] -.sym 20147 i_button_SB_LUT4_I0_I3[2] -.sym 20148 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 20149 io_ctrl_ins.pmod_dir_state[3] -.sym 20150 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 20155 w_rx_data[1] -.sym 20160 w_rx_data[5] -.sym 20165 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 20166 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 20167 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 20173 w_rx_data[7] -.sym 20175 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20176 r_counter_$glb_clk -.sym 20196 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0] -.sym 20198 o_rx_h_tx_l_b$SB_IO_OUT -.sym 20201 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 20205 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] -.sym 20206 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20209 o_led0_SB_LUT4_I1_O[1] -.sym 20210 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20211 o_led1$SB_IO_OUT -.sym 20220 w_rx_data[4] -.sym 20221 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20222 i_button_SB_LUT4_I0_I3[3] -.sym 20223 i_config[2]$SB_IO_IN -.sym 20224 io_ctrl_ins.pmod_dir_state[5] -.sym 20225 io_pmod_out[3]$SB_IO_OUT -.sym 20227 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 20228 w_load -.sym 20229 w_cs[1] -.sym 20231 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 20232 i_button_SB_LUT4_I0_I3[2] -.sym 20233 w_fetch -.sym 20234 w_rx_data[3] -.sym 20235 i_rst_b$SB_IO_IN -.sym 20239 w_rx_data[6] -.sym 20241 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20246 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 20250 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 20252 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20254 i_button_SB_LUT4_I0_I3[2] -.sym 20258 i_button_SB_LUT4_I0_I3[3] -.sym 20259 i_config[2]$SB_IO_IN -.sym 20260 io_ctrl_ins.pmod_dir_state[5] -.sym 20261 i_button_SB_LUT4_I0_I3[2] -.sym 20266 w_rx_data[6] -.sym 20273 w_rx_data[3] -.sym 20277 w_rx_data[4] -.sym 20283 io_pmod_out[3]$SB_IO_OUT -.sym 20284 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 20285 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 20288 w_load -.sym 20289 w_cs[1] -.sym 20290 i_rst_b$SB_IO_IN -.sym 20291 w_fetch -.sym 20296 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 20297 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 20298 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O -.sym 20299 r_counter_$glb_clk -.sym 20319 i_config[2]$SB_IO_IN -.sym 20322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 20342 w_rx_data[7] -.sym 20344 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 20345 o_tr_vc1_b$SB_IO_OUT -.sym 20346 o_led1_SB_LUT4_I1_I2[1] -.sym 20348 o_led0_SB_LUT4_I1_O[1] -.sym 20349 w_cs[1] -.sym 20350 i_button_SB_LUT4_I0_I3[2] -.sym 20351 w_rx_data[6] -.sym 20352 w_load -.sym 20353 i_button_SB_LUT4_I0_O[1] -.sym 20354 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 20355 w_fetch -.sym 20356 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20357 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 20368 w_rx_data[3] -.sym 20372 w_rx_data[5] -.sym 20378 w_rx_data[3] -.sym 20383 w_rx_data[5] -.sym 20387 w_fetch -.sym 20388 w_cs[1] -.sym 20389 o_led0_SB_LUT4_I1_O[1] -.sym 20390 w_load -.sym 20393 i_button_SB_LUT4_I0_I3[2] -.sym 20394 i_button_SB_LUT4_I0_O[1] -.sym 20395 o_tr_vc1_b$SB_IO_OUT -.sym 20396 o_led1_SB_LUT4_I1_I2[1] -.sym 20399 w_rx_data[6] -.sym 20406 i_button_SB_LUT4_I0_O[1] -.sym 20407 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 20413 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 20414 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 20418 w_rx_data[7] -.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 20422 r_counter_$glb_clk -.sym 20438 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 20440 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 20454 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 20467 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E -.sym 20470 w_rx_data[1] -.sym 20476 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 20477 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 20478 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20482 w_rx_data[3] -.sym 20483 o_led1_SB_LUT4_I1_O[0] -.sym 20484 w_rx_data[0] -.sym 20491 w_rx_data[2] -.sym 20492 w_rx_data[4] -.sym 20494 o_led0_SB_LUT4_I1_O[0] -.sym 20498 o_led1_SB_LUT4_I1_O[0] -.sym 20500 o_led0_SB_LUT4_I1_O[0] -.sym 20506 w_rx_data[3] -.sym 20513 w_rx_data[1] -.sym 20517 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 20518 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 20519 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 20522 w_rx_data[4] -.sym 20530 w_rx_data[0] -.sym 20540 w_rx_data[2] -.sym 20544 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E -.sym 20545 r_counter_$glb_clk -.sym 20546 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 20563 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 20579 i_config[0]$SB_IO_IN -.sym 20591 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] -.sym 20592 i_config[1]$SB_IO_IN -.sym 20599 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 20609 o_led1_SB_LUT4_I1_I3[3] -.sym 20621 i_config[1]$SB_IO_IN -.sym 20622 o_led1_SB_LUT4_I1_I3[3] -.sym 20624 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] -.sym 20667 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 20668 r_counter_$glb_clk +.sym 19575 w_rx_24_fifo_data[16] +.sym 19576 io_pmod_in[2]$SB_IO_IN +.sym 19577 w_rx_data[1] +.sym 19583 w_rx_24_fifo_data[23] +.sym 19585 w_rx_24_fifo_data[19] +.sym 19587 rx_fifo.wr_addr[4] +.sym 19590 w_rx_fifo_pull +.sym 19591 rx_fifo.rd_addr[0] +.sym 19592 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 19593 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 19594 w_rx_data[1] +.sym 19595 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 19596 rx_fifo.wr_addr[0] +.sym 19598 w_rx_fifo_pulled_data[7] +.sym 19605 w_rx_fifo_pulled_data[28] +.sym 19608 w_rx_24_fifo_data[30] +.sym 19609 w_rx_fifo_pulled_data[30] +.sym 19615 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 19616 w_rx_24_fifo_data[6] +.sym 19617 i_rst_b_SB_LUT4_I3_O +.sym 19619 w_rx_09_fifo_data[6] +.sym 19620 smi_ctrl_ins.soe_and_reset +.sym 19622 w_rx_fifo_pulled_data[7] +.sym 19626 channel +.sym 19628 w_rx_24_fifo_data[29] +.sym 19629 w_rx_09_fifo_data[29] +.sym 19632 w_rx_24_fifo_data[28] +.sym 19633 w_rx_fifo_pulled_data[31] +.sym 19634 w_rx_09_fifo_data[30] +.sym 19635 w_rx_09_fifo_data[28] +.sym 19637 w_rx_fifo_pulled_data[31] +.sym 19644 w_rx_09_fifo_data[28] +.sym 19645 w_rx_24_fifo_data[28] +.sym 19646 channel +.sym 19649 w_rx_24_fifo_data[30] +.sym 19650 w_rx_09_fifo_data[30] +.sym 19651 channel +.sym 19655 w_rx_24_fifo_data[6] +.sym 19656 channel +.sym 19658 w_rx_09_fifo_data[6] +.sym 19661 w_rx_fifo_pulled_data[7] +.sym 19667 w_rx_fifo_pulled_data[28] +.sym 19673 channel +.sym 19675 w_rx_09_fifo_data[29] +.sym 19676 w_rx_24_fifo_data[29] +.sym 19679 w_rx_fifo_pulled_data[30] +.sym 19683 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 19684 smi_ctrl_ins.soe_and_reset +.sym 19685 i_rst_b_SB_LUT4_I3_O +.sym 19687 w_rx_fifo_pulled_data[4] +.sym 19691 w_rx_fifo_pulled_data[6] +.sym 19702 w_rx_09_fifo_data[5] +.sym 19704 w_rx_24_fifo_data[30] +.sym 19710 smi_ctrl_ins.soe_and_reset +.sym 19714 w_tx_fifo_pulled_data[28] +.sym 19715 rx_fifo.rd_addr[3] +.sym 19720 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 19721 w_rx_09_fifo_data[28] +.sym 19728 w_rx_24_fifo_data[7] +.sym 19729 channel +.sym 19731 w_rx_fifo_pulled_data[25] +.sym 19736 smi_ctrl_ins.soe_and_reset +.sym 19738 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 19740 i_rst_b_SB_LUT4_I3_O +.sym 19744 w_rx_fifo_pulled_data[5] +.sym 19748 w_rx_fifo_pulled_data[6] +.sym 19752 w_rx_fifo_pulled_data[4] +.sym 19755 w_rx_09_fifo_data[7] +.sym 19762 w_rx_fifo_pulled_data[4] +.sym 19775 w_rx_fifo_pulled_data[6] +.sym 19778 w_rx_24_fifo_data[7] +.sym 19780 w_rx_09_fifo_data[7] +.sym 19781 channel +.sym 19790 w_rx_fifo_pulled_data[5] +.sym 19805 w_rx_fifo_pulled_data[25] +.sym 19806 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E +.sym 19807 smi_ctrl_ins.soe_and_reset +.sym 19808 i_rst_b_SB_LUT4_I3_O +.sym 19810 w_rx_fifo_pulled_data[5] +.sym 19814 w_rx_fifo_pulled_data[7] +.sym 19822 w_rx_24_fifo_push +.sym 19823 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 19830 rx_fifo.wr_addr[9] +.sym 19833 r_counter +.sym 19834 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 19835 tx_wr_data[26] +.sym 19836 w_tx_fifo_pull +.sym 19837 r_counter +.sym 19838 $PACKER_VCC_NET +.sym 19839 tx_fifo.wr_addr[2] +.sym 19841 tx_wr_data[27] +.sym 19842 w_tx_data_io[6] +.sym 19844 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 19850 i_glob_clock$SB_IO_IN +.sym 19854 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 19858 w_tx_data_io[3] +.sym 19866 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 19877 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 19880 w_tx_data_sys[3] +.sym 19881 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 19889 w_tx_data_sys[3] +.sym 19890 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 19891 w_tx_data_io[3] +.sym 19892 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 19902 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 19929 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 19930 i_glob_clock$SB_IO_IN +.sym 19933 w_tx_fifo_pulled_data[24] +.sym 19937 w_tx_fifo_pulled_data[26] +.sym 19941 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 19944 i_glob_clock$SB_IO_IN +.sym 19951 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 19954 w_tx_data_io[3] +.sym 19957 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 19958 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 19960 tx_fifo.wr_addr[5] +.sym 19961 w_tx_data_sys[1] +.sym 19962 w_rx_data[0] +.sym 19963 tx_fifo.wr_addr[3] +.sym 19966 w_rx_data[2] +.sym 19967 w_tx_fifo_pulled_data[14] +.sym 19973 i_glob_clock$SB_IO_IN +.sym 19975 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 19976 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[3] +.sym 19977 w_tx_data_sys[1] +.sym 19978 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 19980 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 19981 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +.sym 19983 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[2] +.sym 19984 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 19985 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[2] +.sym 19987 w_tx_data_io[7] +.sym 19988 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 19990 w_tx_data_sys[5] +.sym 19994 w_tx_data_sys[2] +.sym 19996 w_tx_data_sys[0] +.sym 19997 w_tx_data_sys[6] +.sym 19998 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 20000 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 20001 w_tx_data_sys[7] +.sym 20002 w_tx_data_io[6] +.sym 20003 w_tx_data_sys[4] +.sym 20006 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 20007 w_tx_data_io[7] +.sym 20008 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 20012 w_tx_data_sys[0] +.sym 20013 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20014 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[2] +.sym 20018 w_tx_data_sys[1] +.sym 20020 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20021 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[2] +.sym 20024 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 20026 w_tx_data_sys[5] +.sym 20027 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20031 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20032 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 20033 w_tx_data_sys[4] +.sym 20036 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20037 w_tx_data_io[6] +.sym 20038 w_tx_data_sys[6] +.sym 20039 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 20042 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20043 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[3] +.sym 20044 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 20045 w_tx_data_sys[2] +.sym 20048 w_tx_data_sys[7] +.sym 20050 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +.sym 20051 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 20052 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 20053 i_glob_clock$SB_IO_IN +.sym 20056 w_tx_fifo_pulled_data[25] +.sym 20060 w_tx_fifo_pulled_data[27] +.sym 20067 i_glob_clock$SB_IO_IN +.sym 20068 tx_fifo.wr_addr[4] +.sym 20069 lvds_tx_inst.tx_state_d1 +.sym 20072 tx_fifo.wr_addr[7] +.sym 20075 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 20078 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 20079 o_led1$SB_IO_OUT +.sym 20080 i_button_SB_LUT4_I2_I1[0] +.sym 20081 tx_fifo.rd_addr[5] +.sym 20084 i_config[0]$SB_IO_IN +.sym 20085 o_led0$SB_IO_OUT +.sym 20086 w_rx_data[1] +.sym 20088 w_load +.sym 20090 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 20097 w_fetch +.sym 20098 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 20099 w_load +.sym 20102 i_button_SB_LUT4_I2_I1[0] +.sym 20103 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20105 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 20108 w_tx_data_smi[0] +.sym 20109 i_rst_b_SB_LUT4_I3_O +.sym 20112 w_ioc[1] +.sym 20113 w_rx_data[1] +.sym 20116 w_cs[1] +.sym 20117 w_ioc[4] +.sym 20121 r_counter +.sym 20122 w_rx_data[0] +.sym 20124 w_ioc[3] +.sym 20125 w_cs[0] +.sym 20126 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] +.sym 20127 w_ioc[2] +.sym 20130 w_fetch +.sym 20131 w_cs[0] +.sym 20132 w_load +.sym 20135 w_load +.sym 20136 i_button_SB_LUT4_I2_I1[0] +.sym 20137 w_fetch +.sym 20138 w_cs[1] +.sym 20142 w_tx_data_smi[0] +.sym 20143 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 20144 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] +.sym 20147 w_ioc[3] +.sym 20148 w_ioc[1] +.sym 20149 w_ioc[4] +.sym 20150 w_ioc[2] +.sym 20154 w_rx_data[1] +.sym 20159 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 20171 w_rx_data[0] +.sym 20175 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 20176 r_counter +.sym 20177 i_rst_b_SB_LUT4_I3_O +.sym 20179 w_tx_fifo_pulled_data[12] +.sym 20183 w_tx_fifo_pulled_data[14] +.sym 20188 w_rx_data[1] +.sym 20190 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 20191 w_fetch +.sym 20192 w_tx_data_io[7] +.sym 20194 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 20197 tx_fifo.rd_addr[4] +.sym 20200 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 20202 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 20205 w_tx_fifo_pulled_data[28] +.sym 20206 tx_wr_data[13] +.sym 20207 tx_fifo.rd_addr[4] +.sym 20211 w_cs[0] +.sym 20212 tx_wr_data[28] +.sym 20219 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3] +.sym 20221 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 20222 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 20223 io_ctrl_ins.pmod_dir_state[2] +.sym 20224 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20225 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] +.sym 20226 o_led0$SB_IO_OUT +.sym 20228 r_counter +.sym 20229 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 20230 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 20231 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3] +.sym 20232 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 20233 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 20234 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 20236 io_ctrl_ins.debug_mode[0] +.sym 20238 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20240 io_ctrl_ins.debug_mode[1] +.sym 20241 i_button_SB_LUT4_I2_I1[0] +.sym 20243 w_ioc[2] +.sym 20244 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 20246 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 20247 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] +.sym 20248 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 20249 i_button_SB_LUT4_I2_I1[0] +.sym 20250 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 20252 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 20253 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3] +.sym 20254 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] +.sym 20255 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20258 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20259 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 20260 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 20261 io_ctrl_ins.pmod_dir_state[2] +.sym 20264 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 20265 io_ctrl_ins.debug_mode[1] +.sym 20266 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3] +.sym 20267 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] +.sym 20270 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 20271 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 20272 i_button_SB_LUT4_I2_I1[0] +.sym 20273 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 20276 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 20277 io_ctrl_ins.debug_mode[0] +.sym 20278 i_button_SB_LUT4_I2_I1[0] +.sym 20279 o_led0$SB_IO_OUT +.sym 20288 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 20291 w_ioc[2] +.sym 20294 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20295 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 20296 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 20297 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 20298 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 20299 r_counter +.sym 20300 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 20302 w_tx_fifo_pulled_data[13] +.sym 20306 w_tx_fifo_pulled_data[15] +.sym 20314 tx_wr_data[14] +.sym 20315 tx_fifo.wr_addr[8] +.sym 20316 tx_fifo.wr_addr[4] +.sym 20319 io_ctrl_ins.pmod_dir_state[2] +.sym 20321 tx_fifo.wr_addr[2] +.sym 20323 o_rx_h_tx_l_b$SB_IO_OUT +.sym 20326 tx_fifo.wr_addr[2] +.sym 20327 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 20328 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 20329 r_counter +.sym 20330 $PACKER_VCC_NET +.sym 20332 o_shdn_tx_lna$SB_IO_OUT +.sym 20334 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 20335 w_tx_fifo_pull +.sym 20336 w_tx_fifo_pull +.sym 20342 r_counter +.sym 20344 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 20345 w_load +.sym 20346 io_ctrl_ins.pmod_dir_state[3] +.sym 20348 i_button_SB_LUT4_I2_I1[0] +.sym 20350 o_led1$SB_IO_OUT +.sym 20354 i_config[0]$SB_IO_IN +.sym 20356 w_rx_data[1] +.sym 20357 io_ctrl_ins.pmod_dir_state[1] +.sym 20358 w_rx_data[3] +.sym 20360 w_rx_data[4] +.sym 20362 w_cs[1] +.sym 20363 i_config[1]$SB_IO_IN +.sym 20365 w_fetch +.sym 20368 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20369 io_ctrl_ins.pmod_dir_state[4] +.sym 20371 i_rst_b$SB_IO_IN +.sym 20375 io_ctrl_ins.pmod_dir_state[1] +.sym 20376 o_led1$SB_IO_OUT +.sym 20377 i_button_SB_LUT4_I2_I1[0] +.sym 20378 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20387 i_button_SB_LUT4_I2_I1[0] +.sym 20388 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20389 io_ctrl_ins.pmod_dir_state[3] +.sym 20390 i_config[0]$SB_IO_IN +.sym 20396 w_rx_data[4] +.sym 20399 w_rx_data[3] +.sym 20405 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 20406 io_ctrl_ins.pmod_dir_state[4] +.sym 20407 i_config[1]$SB_IO_IN +.sym 20408 i_button_SB_LUT4_I2_I1[0] +.sym 20411 w_cs[1] +.sym 20412 w_fetch +.sym 20413 i_rst_b$SB_IO_IN +.sym 20414 w_load +.sym 20417 w_rx_data[1] +.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 20422 r_counter +.sym 20425 w_tx_fifo_pulled_data[28] +.sym 20429 w_tx_fifo_pulled_data[30] +.sym 20438 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O +.sym 20452 o_tr_vc1$SB_IO_OUT +.sym 20453 tx_fifo.wr_addr[3] +.sym 20455 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 20457 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 20466 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20467 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 20468 io_ctrl_ins.rf_pin_state[6] +.sym 20470 io_ctrl_ins.rf_pin_state[4] +.sym 20471 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20472 io_ctrl_ins.rf_pin_state[7] +.sym 20473 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20474 io_ctrl_ins.rf_pin_state[5] +.sym 20475 io_ctrl_ins.rf_pin_state[3] +.sym 20476 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20477 io_ctrl_ins.rf_pin_state[1] +.sym 20478 i_button_SB_LUT4_I2_I1[2] +.sym 20479 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20482 io_ctrl_ins.rf_pin_state[2] +.sym 20489 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20490 r_counter +.sym 20499 io_ctrl_ins.rf_pin_state[6] +.sym 20500 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20501 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20504 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20505 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20506 io_ctrl_ins.rf_pin_state[2] +.sym 20507 i_button_SB_LUT4_I2_I1[2] +.sym 20511 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20512 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20513 io_ctrl_ins.rf_pin_state[1] +.sym 20516 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20518 io_ctrl_ins.rf_pin_state[7] +.sym 20519 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20523 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 20524 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 20528 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20530 io_ctrl_ins.rf_pin_state[4] +.sym 20531 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20534 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20536 io_ctrl_ins.rf_pin_state[5] +.sym 20537 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20540 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20541 i_button_SB_LUT4_I2_I1[2] +.sym 20542 io_ctrl_ins.rf_pin_state[3] +.sym 20543 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20544 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.sym 20545 r_counter +.sym 20548 w_tx_fifo_pulled_data[29] +.sym 20552 w_tx_fifo_pulled_data[31] +.sym 20559 o_rx_h_tx_l_b$SB_IO_OUT +.sym 20560 spi_if_ins.spi.r2_rx_done +.sym 20561 o_tr_vc1_b$SB_IO_OUT +.sym 20564 tx_fifo.wr_addr[4] +.sym 20567 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 20568 tx_wr_en +.sym 20571 i_config[0]$SB_IO_IN +.sym 20573 tx_fifo.rd_addr[5] +.sym 20576 o_led1$SB_IO_OUT +.sym 20580 w_rx_data[7] +.sym 20581 w_rx_data[6] +.sym 20589 w_rx_data[4] +.sym 20591 w_rx_data[7] +.sym 20594 w_rx_data[0] +.sym 20598 w_rx_data[2] +.sym 20602 w_rx_data[3] +.sym 20604 r_counter +.sym 20605 w_rx_data[5] +.sym 20606 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O +.sym 20607 w_rx_data[6] +.sym 20613 w_rx_data[1] +.sym 20623 w_rx_data[0] +.sym 20629 w_rx_data[5] +.sym 20636 w_rx_data[3] +.sym 20641 w_rx_data[6] +.sym 20645 w_rx_data[1] +.sym 20653 w_rx_data[4] +.sym 20660 w_rx_data[2] +.sym 20663 w_rx_data[7] +.sym 20667 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O +.sym 20668 r_counter .sym 20672 i_config[0]$SB_IO_IN -.sym 20700 o_led1$SB_IO_OUT +.sym 20678 i_ss$SB_IO_IN +.sym 20679 w_rx_data[4] +.sym 20681 tx_fifo.rd_addr[4] +.sym 20682 w_rx_data[2] +.sym 20686 w_rx_data[3] +.sym 20690 tx_wr_data[29] .sym 20748 w_smi_data_output[5] .sym 20750 w_smi_data_direction .sym 20751 $PACKER_VCC_NET -.sym 20757 w_smi_data_output[5] +.sym 20756 w_smi_data_direction .sym 20759 $PACKER_VCC_NET -.sym 20769 w_smi_data_direction -.sym 20770 smi_ctrl_ins.swe_and_reset -.sym 20786 rx_fifo.wr_addr[7] -.sym 20804 i_mosi$SB_IO_IN +.sym 20764 w_smi_data_output[5] +.sym 20770 rx_fifo.rd_addr_gray_wr_r[0] +.sym 20772 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 20773 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] +.sym 20774 rx_fifo.rd_addr_gray_wr[4] +.sym 20775 rx_fifo.rd_addr_gray_wr[0] +.sym 20777 w_smi_read_req_SB_LUT4_I1_O[2] +.sym 20790 w_smi_data_direction +.sym 20802 i_smi_soe_se$SB_IO_IN +.sym 20804 w_smi_data_output[5] +.sym 20812 rx_fifo.wr_addr[8] +.sym 20814 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 20815 rx_fifo.wr_addr[0] +.sym 20816 rx_fifo.wr_addr[4] +.sym 20819 rx_fifo.wr_addr[6] +.sym 20820 rx_fifo.wr_addr[3] +.sym 20821 rx_fifo.wr_addr[2] +.sym 20822 rx_fifo.wr_addr[7] +.sym 20824 rx_fifo.wr_addr[9] +.sym 20825 w_rx_fifo_data[0] +.sym 20829 rx_fifo.wr_addr[5] +.sym 20830 $PACKER_VCC_NET +.sym 20835 w_rx_fifo_data[2] +.sym 20837 w_rx_fifo_push .sym 20844 i_mosi$SB_IO_IN -.sym 20846 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 20847 smi_ctrl_ins.tx_reg_state[1] -.sym 20848 smi_ctrl_ins.tx_reg_state[2] -.sym 20849 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 20850 smi_ctrl_ins.tx_reg_state[3] -.sym 20851 smi_ctrl_ins.tx_reg_state[0] -.sym 20852 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 20900 o_miso_$_TBUF__Y_E -.sym 20925 i_rst_b$SB_IO_IN -.sym 20936 rx_fifo.wr_addr[1] -.sym 20937 rx_fifo.wr_addr[5] -.sym 20938 w_rx_fifo_pulled_data[12] -.sym 20947 int_miso -.sym 20986 smi_ctrl_ins.r_fifo_push -.sym 21034 w_smi_data_input[7] -.sym 21038 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21039 o_miso_$_TBUF__Y_E +.sym 20846 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 20847 rx_fifo.rd_addr_gray[0] +.sym 20848 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 20849 rx_fifo.rd_addr[9] +.sym 20850 rx_fifo.rd_addr_gray[6] +.sym 20851 rx_fifo.rd_addr_gray[4] +.sym 20852 rx_fifo.rd_addr_gray[5] +.sym 20853 rx_fifo.rd_addr_gray[3] +.sym 20862 rx_fifo.wr_addr[2] +.sym 20863 rx_fifo.wr_addr[3] +.sym 20865 rx_fifo.wr_addr[4] +.sym 20866 rx_fifo.wr_addr[5] +.sym 20867 rx_fifo.wr_addr[6] +.sym 20868 rx_fifo.wr_addr[7] +.sym 20869 rx_fifo.wr_addr[8] +.sym 20870 rx_fifo.wr_addr[9] +.sym 20871 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 20872 rx_fifo.wr_addr[0] +.sym 20873 lvds_clock_buf +.sym 20874 w_rx_fifo_push +.sym 20876 w_rx_fifo_data[0] +.sym 20880 w_rx_fifo_data[2] +.sym 20883 $PACKER_VCC_NET +.sym 20890 rx_fifo.wr_addr[3] +.sym 20893 rx_fifo.wr_addr[2] +.sym 20899 rx_fifo.wr_addr[6] +.sym 20907 rx_fifo.rd_addr[8] +.sym 20909 w_rx_fifo_data[2] +.sym 20918 rx_fifo.rd_addr_gray[5] +.sym 20920 rx_fifo.rd_addr_gray[3] +.sym 20924 smi_ctrl_ins.soe_and_reset +.sym 20925 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 20926 rx_fifo.rd_addr_gray_wr_r[0] +.sym 20927 int_miso +.sym 20929 rx_fifo.rd_addr[9] +.sym 20930 rx_fifo.wr_addr_gray_rd_r[7] +.sym 20934 rx_fifo.wr_addr[7] +.sym 20935 rx_fifo.wr_addr[9] +.sym 20936 $PACKER_VCC_NET +.sym 20939 i_mosi$SB_IO_IN +.sym 20941 smi_ctrl_ins.soe_and_reset +.sym 20954 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 20956 $PACKER_VCC_NET +.sym 20963 w_rx_fifo_pull +.sym 20964 rx_fifo.rd_addr[0] +.sym 20965 rx_fifo.rd_addr[8] +.sym 20967 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 20969 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 20970 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 20971 rx_fifo.rd_addr[9] +.sym 20972 w_rx_fifo_data[3] +.sym 20973 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 20974 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 20977 r_counter +.sym 20980 rx_fifo.rd_addr[3] +.sym 20981 w_rx_fifo_data[1] +.sym 20984 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 20985 w_smi_read_req_SB_LUT4_I1_O[1] +.sym 20986 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 20987 smi_ctrl_ins.soe_and_reset +.sym 20988 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 20989 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[2] +.sym 20990 rx_fifo.wr_addr_gray_rd_r[7] +.sym 20991 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 21000 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21001 rx_fifo.rd_addr[3] +.sym 21003 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21004 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21005 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21006 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21007 rx_fifo.rd_addr[8] +.sym 21008 rx_fifo.rd_addr[9] +.sym 21009 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21010 rx_fifo.rd_addr[0] +.sym 21011 r_counter +.sym 21012 w_rx_fifo_pull +.sym 21013 $PACKER_VCC_NET +.sym 21017 w_rx_fifo_data[3] +.sym 21021 w_rx_fifo_data[1] +.sym 21024 w_tx_fifo_pulled_data[12] +.sym 21025 tx_fifo.wr_addr[6] +.sym 21029 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 21032 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 21033 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 21036 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 21037 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 21040 rx_fifo.rd_addr[9] .sym 21042 i_rst_b$SB_IO_IN -.sym 21046 int_miso -.sym 21048 rx_fifo.wr_addr[2] -.sym 21054 rx_fifo.wr_addr[2] +.sym 21044 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21046 w_rx_fifo_push +.sym 21047 rx_fifo.wr_addr[7] +.sym 21048 rx_fifo.wr_addr_gray_rd[2] +.sym 21056 w_rx_fifo_push +.sym 21057 rx_fifo.wr_addr[7] .sym 21058 $PACKER_VCC_NET -.sym 21068 rx_fifo.wr_addr[3] -.sym 21070 rx_fifo.wr_addr[6] -.sym 21071 rx_fifo.wr_addr[9] -.sym 21072 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 21076 rx_fifo.wr_addr[4] -.sym 21077 rx_fifo.wr_addr[0] -.sym 21079 rx_fifo.wr_addr[1] -.sym 21080 rx_fifo.wr_addr[5] -.sym 21081 rx_fifo.wr_addr[8] -.sym 21082 rx_fifo.wr_addr[7] -.sym 21083 rx_fifo.mem_q.0.3_WDATA_2 -.sym 21085 rx_fifo.mem_q.0.3_WDATA_3 -.sym 21088 tx_fifo.rd_addr_gray_wr[8] -.sym 21093 tx_fifo.rd_addr_gray_wr_r[8] +.sym 21060 rx_fifo.wr_addr[6] +.sym 21062 rx_fifo.wr_addr[5] +.sym 21065 rx_fifo.wr_addr[8] +.sym 21066 rx_fifo.wr_addr[0] +.sym 21075 rx_fifo.wr_addr[3] +.sym 21076 w_rx_fifo_data[18] +.sym 21078 rx_fifo.wr_addr[9] +.sym 21079 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21081 rx_fifo.wr_addr[2] +.sym 21083 w_rx_fifo_data[16] +.sym 21085 rx_fifo.wr_addr[4] +.sym 21086 rx_fifo.wr_addr_gray_rd[5] +.sym 21087 rx_fifo.wr_addr_gray_rd[8] +.sym 21088 rx_fifo.wr_addr_gray_rd[0] +.sym 21089 rx_fifo.wr_addr_gray_rd[2] +.sym 21091 rx_fifo.wr_addr_gray_rd_r[0] +.sym 21092 rx_fifo.wr_addr_gray_rd[3] +.sym 21093 rx_fifo.wr_addr_gray_rd[7] .sym 21102 rx_fifo.wr_addr[2] .sym 21103 rx_fifo.wr_addr[3] .sym 21105 rx_fifo.wr_addr[4] @@ -10505,66 +12870,100 @@ .sym 21108 rx_fifo.wr_addr[7] .sym 21109 rx_fifo.wr_addr[8] .sym 21110 rx_fifo.wr_addr[9] -.sym 21111 rx_fifo.wr_addr[1] +.sym 21111 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] .sym 21112 rx_fifo.wr_addr[0] -.sym 21113 lvds_clock_$glb_clk -.sym 21114 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 21116 rx_fifo.mem_q.0.3_WDATA_3 -.sym 21120 rx_fifo.mem_q.0.3_WDATA_2 +.sym 21113 lvds_clock_buf +.sym 21114 w_rx_fifo_push +.sym 21116 w_rx_fifo_data[16] +.sym 21120 w_rx_fifo_data[18] .sym 21123 $PACKER_VCC_NET -.sym 21137 o_smi_read_req$SB_IO_OUT -.sym 21142 w_rx_fifo_pulled_data[15] -.sym 21150 w_rx_fifo_pulled_data[13] -.sym 21158 rx_fifo.mem_q.0.3_WDATA_1 +.sym 21126 w_tx_fifo_pulled_data[13] +.sym 21128 rx_fifo.wr_addr[5] +.sym 21129 i_smi_soe_se$SB_IO_IN +.sym 21130 w_rx_fifo_pulled_data[18] +.sym 21131 smi_ctrl_ins.soe_and_reset +.sym 21132 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21133 rx_fifo.wr_addr[8] +.sym 21134 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21136 rx_fifo.wr_addr[6] +.sym 21139 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 21140 w_rx_fifo_data[2] +.sym 21141 rx_fifo.rd_addr[9] +.sym 21142 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 21143 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 21144 rx_fifo.rd_addr[0] +.sym 21145 w_rx_fifo_pull +.sym 21146 rx_fifo.rd_addr[8] +.sym 21148 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 21149 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 21156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21157 rx_fifo.rd_addr[0] +.sym 21158 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21159 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] .sym 21160 $PACKER_VCC_NET -.sym 21164 rx_fifo.rd_addr[0] -.sym 21167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 21168 rx_fifo.rd_addr[9] -.sym 21169 rx_fifo.mem_q.0.3_WDATA -.sym 21172 rx_fifo.rd_addr[1] -.sym 21175 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21176 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21177 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 21178 rx_fifo.rd_addr[2] -.sym 21182 rx_fifo.rd_addr[5] -.sym 21183 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 21187 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 21188 o_miso_$_TBUF__Y_E -.sym 21204 rx_fifo.rd_addr[2] -.sym 21205 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 21207 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21208 rx_fifo.rd_addr[5] -.sym 21209 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 21210 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21211 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 21164 rx_fifo.rd_addr[9] +.sym 21167 rx_fifo.rd_addr[8] +.sym 21168 rx_fifo.rd_addr[3] +.sym 21169 w_rx_fifo_data[19] +.sym 21170 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21171 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21174 w_rx_fifo_pull +.sym 21176 w_rx_fifo_data[17] +.sym 21181 r_counter +.sym 21185 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21188 rx_fifo.wr_addr_gray[8] +.sym 21189 rx_fifo.wr_addr_gray[0] +.sym 21190 rx_fifo.wr_addr_gray[1] +.sym 21191 rx_fifo.wr_addr_gray[3] +.sym 21192 rx_fifo.wr_addr[7] +.sym 21193 rx_fifo.wr_addr_gray[7] +.sym 21194 rx_fifo.wr_addr_gray[2] +.sym 21195 rx_fifo.wr_addr_gray[5] +.sym 21204 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21205 rx_fifo.rd_addr[3] +.sym 21207 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21208 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21209 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21210 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21211 rx_fifo.rd_addr[8] .sym 21212 rx_fifo.rd_addr[9] -.sym 21213 rx_fifo.rd_addr[1] +.sym 21213 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] .sym 21214 rx_fifo.rd_addr[0] -.sym 21215 r_counter_$glb_clk -.sym 21216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 21215 r_counter +.sym 21216 w_rx_fifo_pull .sym 21217 $PACKER_VCC_NET -.sym 21221 rx_fifo.mem_q.0.3_WDATA -.sym 21225 rx_fifo.mem_q.0.3_WDATA_1 -.sym 21235 tx_fifo.rd_addr_gray_wr_r[8] -.sym 21236 tx_fifo.rd_addr_gray[8] -.sym 21237 rx_fifo.mem_q.0.3_WDATA -.sym 21239 $PACKER_VCC_NET -.sym 21245 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 21252 rx_fifo.wr_addr[4] -.sym 21258 rx_fifo.wr_addr[4] -.sym 21259 rx_fifo.wr_addr[5] -.sym 21260 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 21263 rx_fifo.wr_addr[0] -.sym 21268 rx_fifo.wr_addr[9] -.sym 21270 rx_fifo.wr_addr[3] -.sym 21271 rx_fifo.wr_addr[6] +.sym 21221 w_rx_fifo_data[19] +.sym 21225 w_rx_fifo_data[17] +.sym 21236 $PACKER_VCC_NET +.sym 21242 w_rx_fifo_data[17] +.sym 21243 w_rx_09_fifo_data[17] +.sym 21244 w_tx_fsm_state[0] +.sym 21245 rx_fifo.rd_addr[9] +.sym 21247 w_rx_24_fifo_data[20] +.sym 21249 int_miso +.sym 21250 w_rx_24_fifo_data[12] +.sym 21251 w_rx_fifo_data[27] +.sym 21252 rx_fifo.rd_addr_gray[3] +.sym 21258 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21259 rx_fifo.wr_addr[9] +.sym 21262 rx_fifo.wr_addr[6] +.sym 21264 w_rx_fifo_data[24] +.sym 21265 rx_fifo.wr_addr[5] +.sym 21267 rx_fifo.wr_addr[2] +.sym 21268 rx_fifo.wr_addr[3] +.sym 21269 w_rx_fifo_data[26] +.sym 21271 rx_fifo.wr_addr[8] +.sym 21272 rx_fifo.wr_addr[0] +.sym 21273 rx_fifo.wr_addr[4] +.sym 21276 w_rx_fifo_push .sym 21278 $PACKER_VCC_NET -.sym 21280 rx_fifo.wr_addr[2] -.sym 21282 rx_fifo.wr_addr[7] -.sym 21283 rx_fifo.wr_addr[8] -.sym 21285 rx_fifo.mem_i.0.0_WDATA_2 -.sym 21287 rx_fifo.mem_i.0.0_WDATA_3 -.sym 21289 rx_fifo.wr_addr[1] +.sym 21286 rx_fifo.wr_addr[7] +.sym 21290 w_rx_24_fifo_data[15] +.sym 21291 w_rx_fifo_data[21] +.sym 21294 $PACKER_VCC_NET +.sym 21295 w_tx_fsm_state[1] +.sym 21296 w_rx_fifo_data[17] +.sym 21297 w_tx_fsm_state[0] .sym 21306 rx_fifo.wr_addr[2] .sym 21307 rx_fifo.wr_addr[3] .sym 21309 rx_fifo.wr_addr[4] @@ -10573,72 +12972,99 @@ .sym 21312 rx_fifo.wr_addr[7] .sym 21313 rx_fifo.wr_addr[8] .sym 21314 rx_fifo.wr_addr[9] -.sym 21315 rx_fifo.wr_addr[1] +.sym 21315 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] .sym 21316 rx_fifo.wr_addr[0] -.sym 21317 lvds_clock_$glb_clk -.sym 21318 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 21320 rx_fifo.mem_i.0.0_WDATA_3 -.sym 21324 rx_fifo.mem_i.0.0_WDATA_2 +.sym 21317 lvds_clock_buf +.sym 21318 w_rx_fifo_push +.sym 21320 w_rx_fifo_data[24] +.sym 21324 w_rx_fifo_data[26] .sym 21327 $PACKER_VCC_NET -.sym 21339 rx_fifo.wr_addr[6] -.sym 21344 rx_fifo.wr_addr[1] -.sym 21346 rx_fifo.wr_addr[2] -.sym 21362 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 21363 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 21373 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21374 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21375 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 21378 rx_fifo.rd_addr[2] -.sym 21380 rx_fifo.rd_addr[1] -.sym 21381 rx_fifo.rd_addr[9] -.sym 21382 rx_fifo.mem_i.0.0_WDATA -.sym 21384 rx_fifo.rd_addr[0] -.sym 21386 rx_fifo.rd_addr[5] -.sym 21387 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 21389 $PACKER_VCC_NET -.sym 21391 rx_fifo.mem_i.0.0_WDATA_1 -.sym 21392 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 21393 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 21394 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 21395 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 21397 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 21398 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 21399 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 21408 rx_fifo.rd_addr[2] -.sym 21409 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 21411 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21412 rx_fifo.rd_addr[5] -.sym 21413 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 21414 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21415 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 21330 w_tx_fifo_pulled_data[29] +.sym 21342 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 21343 rx_fifo.wr_addr[0] +.sym 21344 w_rx_09_fifo_data[31] +.sym 21345 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 21346 lvds_tx_inst.fifo_empty_d2 +.sym 21347 w_tx_fsm_state[1] +.sym 21348 rx_fifo.wr_addr[7] +.sym 21349 $PACKER_VCC_NET +.sym 21350 smi_ctrl_ins.soe_and_reset +.sym 21351 w_tx_fsm_state[0] +.sym 21353 r_counter +.sym 21354 rx_fifo.wr_addr[9] +.sym 21355 w_rx_fifo_data[21] +.sym 21360 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21361 rx_fifo.rd_addr[3] +.sym 21362 w_rx_fifo_pull +.sym 21364 $PACKER_VCC_NET +.sym 21365 rx_fifo.rd_addr[0] +.sym 21366 w_rx_fifo_data[25] +.sym 21371 rx_fifo.rd_addr[8] +.sym 21373 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21374 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21375 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21376 r_counter +.sym 21377 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21380 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21383 rx_fifo.rd_addr[9] +.sym 21389 w_rx_fifo_data[27] +.sym 21392 w_rx_24_fifo_data[19] +.sym 21393 w_rx_24_fifo_data[17] +.sym 21394 w_rx_24_fifo_data[20] +.sym 21395 w_rx_fifo_data[31] +.sym 21396 w_rx_24_fifo_data[16] +.sym 21397 w_rx_24_fifo_data[5] +.sym 21398 w_rx_24_fifo_data[14] +.sym 21399 w_rx_24_fifo_data[23] +.sym 21408 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21409 rx_fifo.rd_addr[3] +.sym 21411 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21412 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21413 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21414 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21415 rx_fifo.rd_addr[8] .sym 21416 rx_fifo.rd_addr[9] -.sym 21417 rx_fifo.rd_addr[1] +.sym 21417 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] .sym 21418 rx_fifo.rd_addr[0] -.sym 21419 r_counter_$glb_clk -.sym 21420 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 21419 r_counter +.sym 21420 w_rx_fifo_pull .sym 21421 $PACKER_VCC_NET -.sym 21425 rx_fifo.mem_i.0.0_WDATA -.sym 21429 rx_fifo.mem_i.0.0_WDATA_1 -.sym 21446 int_miso -.sym 21448 o_miso_$_TBUF__Y_E -.sym 21450 i_rst_b$SB_IO_IN -.sym 21457 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 21462 rx_fifo.wr_addr[8] -.sym 21466 $PACKER_VCC_NET -.sym 21468 rx_fifo.mem_i.0.3_WDATA_2 -.sym 21471 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21474 rx_fifo.wr_addr[3] -.sym 21478 rx_fifo.wr_addr[6] -.sym 21480 rx_fifo.wr_addr[4] -.sym 21482 rx_fifo.wr_addr[1] -.sym 21483 rx_fifo.wr_addr[5] -.sym 21484 rx_fifo.wr_addr[2] -.sym 21488 rx_fifo.wr_addr[9] -.sym 21489 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 21490 rx_fifo.wr_addr[7] -.sym 21492 rx_fifo.wr_addr[0] -.sym 21498 smi_ctrl_ins.soe_and_reset -.sym 21500 int_miso +.sym 21425 w_rx_fifo_data[27] +.sym 21429 w_rx_fifo_data[25] +.sym 21435 i_rst_b_SB_LUT4_I3_O +.sym 21436 channel +.sym 21439 w_tx_fsm_state[0] +.sym 21447 w_rx_24_fifo_data[16] +.sym 21448 w_tx_fifo_pulled_data[26] +.sym 21449 rx_fifo.wr_addr[8] +.sym 21451 rx_fifo.wr_addr[7] +.sym 21452 i_rst_b_SB_LUT4_I3_O +.sym 21453 rx_fifo.wr_addr[5] +.sym 21454 i_rst_b$SB_IO_IN +.sym 21455 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21456 rx_fifo.rd_addr[9] +.sym 21457 tx_wr_en +.sym 21464 rx_fifo.wr_addr[8] +.sym 21467 rx_fifo.wr_addr[0] +.sym 21469 rx_fifo.wr_addr[5] +.sym 21471 rx_fifo.wr_addr[6] +.sym 21473 rx_fifo.wr_addr[2] +.sym 21477 rx_fifo.wr_addr[4] +.sym 21478 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21479 rx_fifo.wr_addr[3] +.sym 21480 w_rx_fifo_data[30] +.sym 21486 rx_fifo.wr_addr[7] +.sym 21487 w_rx_fifo_data[28] +.sym 21489 w_rx_fifo_push +.sym 21491 $PACKER_VCC_NET +.sym 21492 rx_fifo.wr_addr[9] +.sym 21494 w_rx_24_fifo_data[7] +.sym 21496 w_rx_24_fifo_data[6] +.sym 21497 w_rx_24_fifo_data[31] +.sym 21498 w_rx_fifo_data[5] +.sym 21499 $PACKER_VCC_NET +.sym 21500 w_rx_24_fifo_data[30] +.sym 21501 w_rx_24_fifo_data[9] .sym 21510 rx_fifo.wr_addr[2] .sym 21511 rx_fifo.wr_addr[3] .sym 21513 rx_fifo.wr_addr[4] @@ -10647,2191 +13073,3421 @@ .sym 21516 rx_fifo.wr_addr[7] .sym 21517 rx_fifo.wr_addr[8] .sym 21518 rx_fifo.wr_addr[9] -.sym 21519 rx_fifo.wr_addr[1] +.sym 21519 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] .sym 21520 rx_fifo.wr_addr[0] -.sym 21521 lvds_clock_$glb_clk -.sym 21522 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 21524 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21528 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21521 lvds_clock_buf +.sym 21522 w_rx_fifo_push +.sym 21524 w_rx_fifo_data[28] +.sym 21528 w_rx_fifo_data[30] .sym 21531 $PACKER_VCC_NET -.sym 21538 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21547 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21554 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 21568 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21575 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 21576 rx_fifo.rd_addr[0] -.sym 21581 rx_fifo.rd_addr[9] -.sym 21582 rx_fifo.mem_i.0.3_WDATA -.sym 21583 rx_fifo.rd_addr[5] -.sym 21584 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21586 rx_fifo.rd_addr[2] -.sym 21587 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21588 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 21589 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 21591 rx_fifo.rd_addr[1] +.sym 21537 w_rx_24_fifo_data[14] +.sym 21546 channel +.sym 21549 rx_fifo.rd_addr[9] +.sym 21550 rx_fifo.rd_addr[8] +.sym 21554 w_tx_fifo_pulled_data[25] +.sym 21555 w_rx_24_fifo_data[9] +.sym 21564 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21565 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21568 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21569 rx_fifo.rd_addr[0] +.sym 21570 w_rx_fifo_data[29] +.sym 21571 rx_fifo.rd_addr[3] +.sym 21573 rx_fifo.rd_addr[8] +.sym 21575 w_rx_fifo_data[31] +.sym 21577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21580 r_counter +.sym 21581 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21582 w_rx_fifo_pull .sym 21593 $PACKER_VCC_NET -.sym 21595 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 21601 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 21612 rx_fifo.rd_addr[2] -.sym 21613 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 21615 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 21616 rx_fifo.rd_addr[5] -.sym 21617 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 21618 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 21619 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 21594 rx_fifo.rd_addr[9] +.sym 21597 w_rx_fifo_data[5] +.sym 21598 w_rx_sync_09 +.sym 21600 w_rx_sync_24 +.sym 21601 $PACKER_VCC_NET +.sym 21602 $PACKER_VCC_NET +.sym 21612 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21613 rx_fifo.rd_addr[3] +.sym 21615 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21616 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21617 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21618 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21619 rx_fifo.rd_addr[8] .sym 21620 rx_fifo.rd_addr[9] -.sym 21621 rx_fifo.rd_addr[1] +.sym 21621 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] .sym 21622 rx_fifo.rd_addr[0] -.sym 21623 r_counter_$glb_clk -.sym 21624 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.sym 21623 r_counter +.sym 21624 w_rx_fifo_pull .sym 21625 $PACKER_VCC_NET -.sym 21629 rx_fifo.mem_i.0.3_WDATA -.sym 21633 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21641 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 21642 i_smi_soe_se$SB_IO_IN -.sym 21644 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 21650 w_load -.sym 21653 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 21661 w_cs[2] -.sym 21699 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 21704 w_load -.sym 21754 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 21757 w_load -.sym 21760 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 21800 o_led1_SB_DFFER_Q_E -.sym 21805 r_tx_data[3] -.sym 21848 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 21849 spi_if_ins.w_rx_data[1] -.sym 21852 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 21855 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 21861 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 21865 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 21903 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 21904 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] -.sym 21905 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 21908 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] -.sym 21909 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 21948 o_led1$SB_IO_OUT -.sym 21952 w_rx_data[0] -.sym 21953 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 21956 o_shdn_tx_lna$SB_IO_OUT -.sym 21957 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 21963 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 21965 w_rx_fifo_full -.sym 21967 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 22009 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 22011 w_tx_data_io[2] -.sym 22049 w_rx_data[0] -.sym 22051 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 22057 w_rx_data[3] -.sym 22065 i_button_SB_LUT4_I0_I3[2] -.sym 22066 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] -.sym 22068 o_led0$SB_IO_OUT -.sym 22106 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 22107 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 22110 o_led0_SB_LUT4_I1_O[3] -.sym 22111 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 22148 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 22150 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 22153 w_tx_data_io[2] -.sym 22154 w_rx_fifo_full -.sym 22159 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 22160 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 22171 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 22214 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 22251 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 22252 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 22254 i_config[0]$SB_IO_IN -.sym 22256 o_led1_SB_LUT4_I1_I3[3] -.sym 22257 o_led1_SB_LUT4_I1_I3[0] -.sym 22258 o_tr_vc1$SB_IO_OUT -.sym 22356 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] -.sym 22360 o_led0_SB_LUT4_I1_O[1] -.sym 22465 o_led0$SB_IO_OUT +.sym 21629 w_rx_fifo_data[31] +.sym 21633 w_rx_fifo_data[29] +.sym 21639 i_sck$SB_IO_IN +.sym 21640 $PACKER_VCC_NET +.sym 21645 w_rx_24_fifo_data[29] +.sym 21649 rx_fifo.rd_addr[8] +.sym 21652 w_tx_fifo_pulled_data[24] +.sym 21658 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 21667 rx_fifo.wr_addr[3] +.sym 21668 w_rx_fifo_push +.sym 21670 rx_fifo.wr_addr[4] +.sym 21671 rx_fifo.wr_addr[0] +.sym 21672 rx_fifo.wr_addr[2] +.sym 21675 rx_fifo.wr_addr[6] +.sym 21676 rx_fifo.wr_addr[9] +.sym 21677 rx_fifo.wr_addr[8] +.sym 21678 rx_fifo.wr_addr[7] +.sym 21680 rx_fifo.wr_addr[5] +.sym 21682 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21686 w_rx_fifo_data[4] +.sym 21693 w_rx_fifo_data[6] +.sym 21695 $PACKER_VCC_NET +.sym 21698 spi_if_ins.spi.r_tx_byte[5] +.sym 21699 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 21700 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 21701 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21702 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 21703 spi_if_ins.spi.r_tx_byte[1] +.sym 21704 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 21705 spi_if_ins.spi.r_tx_byte[6] +.sym 21714 rx_fifo.wr_addr[2] +.sym 21715 rx_fifo.wr_addr[3] +.sym 21717 rx_fifo.wr_addr[4] +.sym 21718 rx_fifo.wr_addr[5] +.sym 21719 rx_fifo.wr_addr[6] +.sym 21720 rx_fifo.wr_addr[7] +.sym 21721 rx_fifo.wr_addr[8] +.sym 21722 rx_fifo.wr_addr[9] +.sym 21723 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 21724 rx_fifo.wr_addr[0] +.sym 21725 lvds_clock_buf +.sym 21726 w_rx_fifo_push +.sym 21728 w_rx_fifo_data[4] +.sym 21732 w_rx_fifo_data[6] +.sym 21735 $PACKER_VCC_NET +.sym 21742 w_rx_fifo_push +.sym 21743 w_rx_data[2] +.sym 21750 w_rx_data[0] +.sym 21752 $PACKER_VCC_NET +.sym 21756 tx_fifo.wr_addr[0] +.sym 21760 i_glob_clock$SB_IO_IN +.sym 21761 r_counter +.sym 21762 w_tx_fifo_pulled_data[27] +.sym 21768 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21769 rx_fifo.rd_addr[3] +.sym 21770 w_rx_fifo_pull +.sym 21772 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21773 rx_fifo.rd_addr[0] +.sym 21774 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21776 rx_fifo.rd_addr[9] +.sym 21777 w_rx_fifo_data[5] +.sym 21778 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21779 rx_fifo.rd_addr[8] +.sym 21781 $PACKER_VCC_NET +.sym 21783 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21792 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21793 r_counter +.sym 21795 w_rx_fifo_data[7] +.sym 21801 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 21803 spi_if_ins.r_tx_data_valid +.sym 21804 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 21806 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 21816 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 21817 rx_fifo.rd_addr[3] +.sym 21819 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 21820 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 21821 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 21822 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 21823 rx_fifo.rd_addr[8] +.sym 21824 rx_fifo.rd_addr[9] +.sym 21825 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 21826 rx_fifo.rd_addr[0] +.sym 21827 r_counter +.sym 21828 w_rx_fifo_pull +.sym 21829 $PACKER_VCC_NET +.sym 21833 w_rx_fifo_data[7] +.sym 21837 w_rx_fifo_data[5] +.sym 21854 i_rst_b$SB_IO_IN +.sym 21855 i_button$SB_IO_IN +.sym 21856 w_tx_fifo_pulled_data[26] +.sym 21858 i_rst_b$SB_IO_IN +.sym 21860 tx_fifo.rd_addr[9] +.sym 21862 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 21864 w_tx_fifo_pulled_data[30] +.sym 21865 tx_wr_en +.sym 21870 r_counter +.sym 21872 tx_fifo.wr_addr[2] +.sym 21873 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 21874 tx_fifo.wr_addr[4] +.sym 21876 tx_wr_data[26] +.sym 21879 tx_wr_data[24] +.sym 21883 tx_fifo.wr_addr[8] +.sym 21884 tx_fifo.wr_addr[7] +.sym 21888 tx_wr_en +.sym 21890 $PACKER_VCC_NET +.sym 21891 tx_fifo.wr_addr[5] +.sym 21894 tx_fifo.wr_addr[0] +.sym 21897 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 21900 tx_fifo.wr_addr[3] +.sym 21901 tx_fifo.wr_addr[6] +.sym 21902 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 21903 w_tx_data_io[7] +.sym 21904 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 21905 w_tx_data_io[5] +.sym 21907 i_ss_SB_LUT4_I3_O +.sym 21909 w_tx_data_io[6] +.sym 21918 tx_fifo.wr_addr[2] +.sym 21919 tx_fifo.wr_addr[3] +.sym 21921 tx_fifo.wr_addr[4] +.sym 21922 tx_fifo.wr_addr[5] +.sym 21923 tx_fifo.wr_addr[6] +.sym 21924 tx_fifo.wr_addr[7] +.sym 21925 tx_fifo.wr_addr[8] +.sym 21926 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 21927 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 21928 tx_fifo.wr_addr[0] +.sym 21929 r_counter +.sym 21930 tx_wr_en +.sym 21932 tx_wr_data[24] +.sym 21936 tx_wr_data[26] +.sym 21939 $PACKER_VCC_NET +.sym 21951 tx_fifo.wr_addr[8] +.sym 21952 lvds_tx_inst.r_tx_state +.sym 21957 i_button_SB_LUT4_I2_I1[1] +.sym 21958 i_config[2]$SB_IO_IN +.sym 21962 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 21963 w_rx_data[6] +.sym 21965 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 21966 w_tx_fifo_pulled_data[25] +.sym 21972 tx_fifo.rd_addr[4] +.sym 21973 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 21974 w_tx_fifo_pull +.sym 21976 $PACKER_VCC_NET +.sym 21981 tx_wr_data[27] +.sym 21982 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 21983 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 21985 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 21987 tx_wr_data[25] +.sym 21991 tx_fifo.rd_addr[5] +.sym 21997 tx_fifo.rd_addr[6] +.sym 21998 tx_fifo.rd_addr[9] +.sym 22000 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 22001 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22004 io_ctrl_ins.pmod_dir_state[7] +.sym 22005 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 22006 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 22007 io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[2] +.sym 22008 io_ctrl_ins.pmod_dir_state[6] +.sym 22009 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 22010 io_ctrl_ins.pmod_dir_state[2] +.sym 22011 io_ctrl_ins.pmod_dir_state[5] +.sym 22020 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22021 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 22023 tx_fifo.rd_addr[4] +.sym 22024 tx_fifo.rd_addr[5] +.sym 22025 tx_fifo.rd_addr[6] +.sym 22026 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 22027 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 22028 tx_fifo.rd_addr[9] +.sym 22029 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 22030 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 22031 lvds_clock_buf +.sym 22032 w_tx_fifo_pull +.sym 22033 $PACKER_VCC_NET +.sym 22037 tx_wr_data[27] +.sym 22041 tx_wr_data[25] +.sym 22047 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 22048 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 22049 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 22051 w_tx_data_io[6] +.sym 22053 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 22055 tx_wr_data[25] +.sym 22058 tx_wr_data[12] +.sym 22060 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22061 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 22064 tx_fifo.wr_addr[7] +.sym 22068 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 22077 tx_fifo.wr_addr[3] +.sym 22078 tx_wr_data[14] +.sym 22080 tx_fifo.wr_addr[4] +.sym 22081 tx_fifo.wr_addr[7] +.sym 22083 tx_wr_data[12] +.sym 22085 tx_fifo.wr_addr[2] +.sym 22089 tx_fifo.wr_addr[8] +.sym 22090 r_counter +.sym 22092 tx_wr_en +.sym 22094 $PACKER_VCC_NET +.sym 22095 tx_fifo.wr_addr[5] +.sym 22098 tx_fifo.wr_addr[0] +.sym 22100 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 22101 tx_fifo.wr_addr[6] +.sym 22103 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 22108 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 22109 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 22111 spi_if_ins.spi.r3_rx_done +.sym 22122 tx_fifo.wr_addr[2] +.sym 22123 tx_fifo.wr_addr[3] +.sym 22125 tx_fifo.wr_addr[4] +.sym 22126 tx_fifo.wr_addr[5] +.sym 22127 tx_fifo.wr_addr[6] +.sym 22128 tx_fifo.wr_addr[7] +.sym 22129 tx_fifo.wr_addr[8] +.sym 22130 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 22131 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 22132 tx_fifo.wr_addr[0] +.sym 22133 r_counter +.sym 22134 tx_wr_en +.sym 22136 tx_wr_data[12] +.sym 22140 tx_wr_data[14] +.sym 22143 $PACKER_VCC_NET +.sym 22153 tx_fifo.wr_addr[3] +.sym 22155 o_tr_vc1$SB_IO_OUT +.sym 22159 w_rx_data[2] +.sym 22160 $PACKER_VCC_NET +.sym 22161 r_counter +.sym 22164 tx_fifo.wr_addr[0] +.sym 22165 tx_fifo.rd_addr[6] +.sym 22166 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22168 i_glob_clock$SB_IO_IN +.sym 22176 tx_wr_data[13] +.sym 22179 tx_fifo.rd_addr[5] +.sym 22180 tx_fifo.rd_addr[6] +.sym 22185 tx_fifo.rd_addr[4] +.sym 22188 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 22192 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 22194 w_tx_fifo_pull +.sym 22195 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 22196 $PACKER_VCC_NET +.sym 22198 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22202 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 22204 tx_fifo.rd_addr[9] +.sym 22205 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 22208 spi_if_ins.spi.r_rx_done +.sym 22224 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22225 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 22227 tx_fifo.rd_addr[4] +.sym 22228 tx_fifo.rd_addr[5] +.sym 22229 tx_fifo.rd_addr[6] +.sym 22230 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 22231 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 22232 tx_fifo.rd_addr[9] +.sym 22233 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 22234 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 22235 lvds_clock_buf +.sym 22236 w_tx_fifo_pull +.sym 22237 $PACKER_VCC_NET +.sym 22245 tx_wr_data[13] +.sym 22249 tx_fifo.wr_addr[6] +.sym 22251 o_led0$SB_IO_OUT +.sym 22260 w_load +.sym 22262 i_rst_b$SB_IO_IN +.sym 22264 w_tx_fifo_pulled_data[30] +.sym 22278 r_counter +.sym 22279 tx_fifo.wr_addr[5] +.sym 22280 tx_wr_en +.sym 22281 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 22282 tx_fifo.wr_addr[8] +.sym 22284 tx_fifo.wr_addr[4] +.sym 22289 tx_wr_data[28] +.sym 22291 tx_fifo.wr_addr[2] +.sym 22298 $PACKER_VCC_NET +.sym 22300 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 22302 tx_fifo.wr_addr[0] +.sym 22304 tx_fifo.wr_addr[7] +.sym 22306 tx_fifo.wr_addr[3] +.sym 22309 tx_fifo.wr_addr[6] +.sym 22317 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 22326 tx_fifo.wr_addr[2] +.sym 22327 tx_fifo.wr_addr[3] +.sym 22329 tx_fifo.wr_addr[4] +.sym 22330 tx_fifo.wr_addr[5] +.sym 22331 tx_fifo.wr_addr[6] +.sym 22332 tx_fifo.wr_addr[7] +.sym 22333 tx_fifo.wr_addr[8] +.sym 22334 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 22335 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 22336 tx_fifo.wr_addr[0] +.sym 22337 r_counter +.sym 22338 tx_wr_en +.sym 22340 tx_wr_data[28] +.sym 22347 $PACKER_VCC_NET +.sym 22353 tx_fifo.wr_addr[5] +.sym 22358 tx_fifo.wr_addr[8] +.sym 22361 tx_wr_data[29] +.sym 22365 i_config[2]$SB_IO_IN +.sym 22375 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 22380 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 22382 tx_wr_data[14] +.sym 22383 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 22384 $PACKER_VCC_NET +.sym 22386 tx_fifo.rd_addr[4] +.sym 22390 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 22391 w_tx_fifo_pull +.sym 22393 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 22395 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22398 tx_fifo.rd_addr[6] +.sym 22399 tx_fifo.rd_addr[5] +.sym 22400 tx_wr_data[29] +.sym 22401 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 22403 tx_fifo.rd_addr[9] +.sym 22424 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 22425 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 22427 tx_fifo.rd_addr[4] +.sym 22428 tx_fifo.rd_addr[5] +.sym 22429 tx_fifo.rd_addr[6] +.sym 22430 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 22431 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 22432 tx_fifo.rd_addr[9] +.sym 22433 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 22434 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 22435 lvds_clock_buf +.sym 22436 w_tx_fifo_pull +.sym 22437 $PACKER_VCC_NET +.sym 22441 tx_wr_data[14] +.sym 22445 tx_wr_data[29] +.sym 22453 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] .sym 22487 o_led1$SB_IO_OUT -.sym 22507 o_led1$SB_IO_OUT +.sym 22505 o_led1$SB_IO_OUT .sym 22517 int_miso -.sym 22519 o_miso_$_TBUF__Y_E -.sym 22534 o_miso_$_TBUF__Y_E +.sym 22519 i_ss_SB_LUT4_I3_O +.sym 22527 i_ss_SB_LUT4_I3_O .sym 22535 int_miso -.sym 22554 i_mosi$SB_IO_IN -.sym 22559 rx_fifo.wr_addr[5] -.sym 22576 i_ss$SB_IO_IN -.sym 22589 i_rst_b$SB_IO_IN -.sym 22593 o_smi_write_req$SB_IO_OUT -.sym 22617 o_smi_write_req$SB_IO_OUT -.sym 22620 i_rst_b$SB_IO_IN +.sym 22542 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 22565 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 22573 i_ss_SB_LUT4_I3_O +.sym 22576 i_mosi$SB_IO_IN +.sym 22585 rx_fifo.rd_addr_gray[0] +.sym 22588 rx_fifo.rd_addr[3] +.sym 22589 rx_fifo.rd_addr_gray[4] +.sym 22594 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 22597 rx_fifo.rd_addr_gray_wr[0] +.sym 22599 rx_fifo.rd_addr[8] +.sym 22600 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 22601 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 22604 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 22610 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 22612 rx_fifo.wr_addr_gray_rd_r[7] +.sym 22617 rx_fifo.rd_addr_gray_wr[0] +.sym 22629 rx_fifo.rd_addr[3] +.sym 22630 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 22635 rx_fifo.wr_addr_gray_rd_r[7] +.sym 22636 rx_fifo.rd_addr[8] +.sym 22644 rx_fifo.rd_addr_gray[4] +.sym 22647 rx_fifo.rd_addr_gray[0] +.sym 22659 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 22660 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 22661 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 22662 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 22664 lvds_clock_buf .sym 22666 i_sck$SB_IO_IN .sym 22668 i_ss$SB_IO_IN -.sym 22677 smi_ctrl_ins.w_fifo_push_trigger -.sym 22689 i_rst_b$SB_IO_IN -.sym 22695 o_smi_write_req$SB_IO_OUT -.sym 22707 i_ss$SB_IO_IN -.sym 22711 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 22720 i_sck$SB_IO_IN +.sym 22674 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 22675 rx_fifo.rd_addr[0] +.sym 22702 r_counter +.sym 22711 i_sck$SB_IO_IN +.sym 22712 rx_fifo.rd_addr_gray_wr[4] +.sym 22720 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 22721 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 22722 rx_fifo.rd_addr[9] +.sym 22724 rx_fifo.rd_addr_gray[6] +.sym 22727 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] +.sym 22730 r_counter .sym 22733 i_ss$SB_IO_IN -.sym 22734 smi_ctrl_ins.r_fifo_push -.sym 22740 i_sck$SB_IO_IN -.sym 22747 smi_ctrl_ins.swe_and_reset -.sym 22748 smi_ctrl_ins.tx_reg_state[1] -.sym 22749 i_rst_b$SB_IO_IN -.sym 22750 w_smi_data_input[7] -.sym 22759 smi_ctrl_ins.tx_reg_state[3] -.sym 22763 i_rst_b$SB_IO_IN -.sym 22765 smi_ctrl_ins.tx_reg_state[2] -.sym 22771 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 22774 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 22776 smi_ctrl_ins.tx_reg_state[0] -.sym 22781 smi_ctrl_ins.tx_reg_state[1] -.sym 22782 smi_ctrl_ins.tx_reg_state[2] -.sym 22783 w_smi_data_input[7] -.sym 22786 w_smi_data_input[7] -.sym 22787 smi_ctrl_ins.tx_reg_state[2] -.sym 22789 i_rst_b$SB_IO_IN -.sym 22792 smi_ctrl_ins.tx_reg_state[0] -.sym 22793 w_smi_data_input[7] -.sym 22794 i_rst_b$SB_IO_IN -.sym 22798 w_smi_data_input[7] -.sym 22799 i_rst_b$SB_IO_IN -.sym 22800 smi_ctrl_ins.tx_reg_state[3] -.sym 22801 smi_ctrl_ins.tx_reg_state[0] -.sym 22804 i_rst_b$SB_IO_IN -.sym 22805 smi_ctrl_ins.tx_reg_state[1] -.sym 22807 w_smi_data_input[7] -.sym 22811 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 22812 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 22816 i_rst_b$SB_IO_IN -.sym 22817 smi_ctrl_ins.tx_reg_state[3] -.sym 22818 smi_ctrl_ins.tx_reg_state[0] -.sym 22827 smi_ctrl_ins.swe_and_reset -.sym 22858 i_sck$SB_IO_IN -.sym 22885 smi_ctrl_ins.w_fifo_push_trigger -.sym 22917 smi_ctrl_ins.w_fifo_push_trigger -.sym 22950 r_counter_$glb_clk -.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 22977 i_ss$SB_IO_IN -.sym 23002 tx_fifo.rd_addr_gray[8] -.sym 23019 tx_fifo.rd_addr_gray_wr[8] -.sym 23038 tx_fifo.rd_addr_gray[8] -.sym 23070 tx_fifo.rd_addr_gray_wr[8] -.sym 23073 r_counter_$glb_clk -.sym 23104 i_sck$SB_IO_IN -.sym 23108 i_sck$SB_IO_IN -.sym 23137 i_ss$SB_IO_IN -.sym 23150 i_ss$SB_IO_IN -.sym 23362 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23364 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23368 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23373 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23377 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23378 i_sck$SB_IO_IN -.sym 23386 i_mosi$SB_IO_IN -.sym 23387 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23389 o_miso_$_TBUF__Y_E -.sym 23395 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23402 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23409 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23414 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23428 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23432 i_mosi$SB_IO_IN -.sym 23440 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23441 o_miso_$_TBUF__Y_E -.sym 23442 i_sck$SB_IO_IN -.sym 23474 w_rx_data[0] -.sym 23486 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23493 i_rst_b$SB_IO_IN -.sym 23496 spi_if_ins.r_tx_byte[7] -.sym 23500 i_smi_soe_se$SB_IO_IN -.sym 23503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 23514 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 23542 i_smi_soe_se$SB_IO_IN -.sym 23543 i_rst_b$SB_IO_IN -.sym 23554 spi_if_ins.r_tx_byte[7] -.sym 23555 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 23564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 23565 r_counter_$glb_clk -.sym 23568 r_counter -.sym 23582 spi_if_ins.r_tx_byte[7] -.sym 23589 smi_ctrl_ins.soe_and_reset -.sym 23591 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 23593 o_led1_SB_LUT4_I1_I3[3] -.sym 23601 io_pmod_out[3]$SB_IO_OUT -.sym 23610 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 23634 w_rx_data[0] -.sym 23671 w_rx_data[0] -.sym 23687 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 23688 r_counter_$glb_clk -.sym 23689 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 23696 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 23719 i_glob_clock$SB_IO_IN -.sym 23736 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23737 w_load -.sym 23738 w_cs[2] -.sym 23752 w_fetch -.sym 23753 o_led1_SB_LUT4_I1_I3[3] -.sym 23758 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 23760 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 23770 w_fetch -.sym 23771 w_load -.sym 23772 w_cs[2] -.sym 23773 o_led1_SB_LUT4_I1_I3[3] -.sym 23801 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23810 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 23811 r_counter_$glb_clk -.sym 23812 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 23816 o_led0$SB_IO_OUT -.sym 23818 o_led1$SB_IO_OUT -.sym 23829 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E -.sym 23834 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 23837 io_pmod_out[0]$SB_IO_OUT -.sym 23839 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 23841 io_pmod_out[1]$SB_IO_OUT -.sym 23845 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 23847 io_pmod_out[3]$SB_IO_OUT -.sym 23856 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 23858 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 23860 w_load -.sym 23868 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 23872 w_cs[1] -.sym 23875 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 23876 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 23878 w_fetch -.sym 23879 i_glob_clock$SB_IO_IN -.sym 23884 o_led1_SB_LUT4_I1_I3[3] -.sym 23887 w_load -.sym 23888 o_led1_SB_LUT4_I1_I3[3] -.sym 23889 w_cs[1] -.sym 23890 w_fetch -.sym 23917 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 23918 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 23919 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 23920 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 23933 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O -.sym 23934 i_glob_clock$SB_IO_IN -.sym 23936 io_pmod_out[1]$SB_IO_OUT -.sym 23939 io_pmod_out[3]$SB_IO_OUT -.sym 23941 io_pmod_out[2]$SB_IO_OUT -.sym 23942 io_pmod_out[0]$SB_IO_OUT -.sym 23951 o_led0$SB_IO_OUT -.sym 23961 o_led0_SB_LUT4_I1_O[1] -.sym 23962 o_led0$SB_IO_OUT -.sym 23964 w_rx_data[1] -.sym 23967 i_button_SB_LUT4_I0_O[1] -.sym 23970 w_rx_data[7] -.sym 23977 w_rx_data[7] -.sym 23981 w_rx_data[3] -.sym 23984 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 23988 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 23994 o_shdn_tx_lna$SB_IO_OUT -.sym 23995 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] -.sym 23996 i_button_SB_LUT4_I0_I3[2] -.sym 23999 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 24005 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0] -.sym 24006 io_pmod_out[2]$SB_IO_OUT -.sym 24007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 24017 w_rx_data[7] -.sym 24022 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 24023 o_shdn_tx_lna$SB_IO_OUT -.sym 24024 io_pmod_out[2]$SB_IO_OUT -.sym 24025 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 24028 i_button_SB_LUT4_I0_I3[2] -.sym 24030 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0] -.sym 24031 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] -.sym 24048 w_rx_data[3] -.sym 24052 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 24054 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 24055 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 24056 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O -.sym 24057 r_counter_$glb_clk -.sym 24058 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24065 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] -.sym 24085 io_pmod_out[3]$SB_IO_OUT -.sym 24102 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 24103 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 24104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 24105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 24111 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 24117 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 24121 o_led0_SB_LUT4_I1_O[1] -.sym 24125 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 24163 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 24164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 24165 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 24175 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 24177 o_led0_SB_LUT4_I1_O[1] -.sym 24178 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 24179 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 24180 r_counter_$glb_clk -.sym 24181 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 24182 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] -.sym 24196 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E -.sym 24206 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 24208 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 24211 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 24225 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 24226 i_button_SB_LUT4_I0_I3[2] -.sym 24227 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] -.sym 24231 o_led1_SB_LUT4_I1_I3[0] -.sym 24232 o_led1_SB_LUT4_I1_I3[3] -.sym 24234 o_led0$SB_IO_OUT -.sym 24237 i_button_SB_LUT4_I0_O[1] -.sym 24238 i_config[0]$SB_IO_IN -.sym 24241 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 24244 o_tr_vc2$SB_IO_OUT -.sym 24249 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 24258 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] -.sym 24259 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 24263 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 24264 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 24280 o_led0$SB_IO_OUT -.sym 24281 o_led1_SB_LUT4_I1_I3[0] -.sym 24282 o_led1_SB_LUT4_I1_I3[3] -.sym 24283 i_button_SB_LUT4_I0_I3[2] -.sym 24286 i_button_SB_LUT4_I0_O[1] -.sym 24287 i_config[0]$SB_IO_IN -.sym 24288 o_tr_vc2$SB_IO_OUT -.sym 24289 o_led1_SB_LUT4_I1_I3[3] -.sym 24302 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E -.sym 24303 r_counter_$glb_clk -.sym 24304 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 24313 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 24317 i_glob_clock$SB_IO_IN -.sym 24321 w_rx_fifo_full -.sym 24349 o_led0_SB_LUT4_I1_O[1] -.sym 24361 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] -.sym 24364 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 24366 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 24372 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 24415 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] -.sym 24416 o_led0_SB_LUT4_I1_O[1] -.sym 24418 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 24425 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 24426 r_counter_$glb_clk -.sym 24427 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 22739 $PACKER_VCC_NET +.sym 22747 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 22748 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 22749 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 22752 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 22753 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 22754 w_smi_read_req_SB_LUT4_I1_O[2] +.sym 22756 w_smi_read_req_SB_LUT4_I1_O[1] +.sym 22757 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 22763 r_counter +.sym 22765 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 22766 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 22767 i_rst_b_SB_LUT4_I3_O +.sym 22768 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 22770 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 22771 rx_fifo.rd_addr[0] +.sym 22778 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 22780 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 22781 w_smi_read_req_SB_LUT4_I1_O[2] +.sym 22782 w_smi_read_req_SB_LUT4_I1_O[1] +.sym 22786 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 22788 rx_fifo.rd_addr[0] +.sym 22792 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 22794 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 22798 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 22805 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 22811 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 22812 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 22817 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 22824 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 22826 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 22827 r_counter +.sym 22828 i_rst_b_SB_LUT4_I3_O +.sym 22829 rx_fifo.rd_addr_gray[1] +.sym 22832 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 22833 rx_fifo.rd_addr_gray[8] +.sym 22836 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 22849 rx_fifo.rd_addr[9] +.sym 22855 $PACKER_VCC_NET +.sym 22856 rx_fifo.rd_addr[9] +.sym 22859 $PACKER_VCC_NET +.sym 22862 rx_fifo.rd_addr_gray[1] +.sym 22871 rx_fifo.wr_addr_gray_rd[8] +.sym 22874 i_smi_soe_se$SB_IO_IN +.sym 22875 rx_fifo.wr_addr_gray_rd_r[0] +.sym 22876 rx_fifo.wr_addr_gray_rd[3] +.sym 22877 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 22878 rx_fifo.wr_addr_gray_rd[5] +.sym 22879 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 22883 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[2] +.sym 22885 rx_fifo.wr_addr_gray_rd[7] +.sym 22886 rx_fifo.rd_addr[0] +.sym 22887 w_rx_fifo_pull +.sym 22891 i_rst_b$SB_IO_IN +.sym 22893 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 22895 r_counter +.sym 22904 rx_fifo.wr_addr_gray_rd[5] +.sym 22909 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 22910 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 22911 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 22912 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[2] +.sym 22916 i_rst_b$SB_IO_IN +.sym 22918 w_rx_fifo_pull +.sym 22923 i_rst_b$SB_IO_IN +.sym 22924 i_smi_soe_se$SB_IO_IN +.sym 22927 rx_fifo.wr_addr_gray_rd[3] +.sym 22934 rx_fifo.rd_addr[0] +.sym 22935 rx_fifo.wr_addr_gray_rd_r[0] +.sym 22939 rx_fifo.wr_addr_gray_rd[7] +.sym 22945 rx_fifo.wr_addr_gray_rd[8] +.sym 22950 r_counter +.sym 22956 i_rst_b_SB_LUT4_I3_O +.sym 22958 rx_fifo.wr_addr_gray_rd[1] +.sym 22959 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 22964 w_smi_data_output[5] +.sym 22976 i_rst_b_SB_LUT4_I3_O +.sym 22977 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 22979 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 22980 rx_fifo.rd_addr_gray[8] +.sym 22983 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 22993 r_counter +.sym 22998 rx_fifo.wr_addr_gray[7] +.sym 23000 rx_fifo.wr_addr_gray[5] +.sym 23001 rx_fifo.wr_addr_gray[8] +.sym 23002 rx_fifo.wr_addr_gray[0] +.sym 23004 rx_fifo.wr_addr_gray[3] +.sym 23007 rx_fifo.wr_addr_gray[2] +.sym 23019 rx_fifo.wr_addr_gray_rd[0] +.sym 23027 rx_fifo.wr_addr_gray[5] +.sym 23032 rx_fifo.wr_addr_gray[8] +.sym 23038 rx_fifo.wr_addr_gray[0] +.sym 23044 rx_fifo.wr_addr_gray[2] +.sym 23058 rx_fifo.wr_addr_gray_rd[0] +.sym 23064 rx_fifo.wr_addr_gray[3] +.sym 23068 rx_fifo.wr_addr_gray[7] +.sym 23073 r_counter +.sym 23075 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 23076 rx_fifo.rd_addr_gray_wr[8] +.sym 23078 rx_fifo.rd_addr_gray_wr[1] +.sym 23081 i_rst_b_SB_LUT4_I3_O +.sym 23093 r_counter +.sym 23094 smi_ctrl_ins.soe_and_reset +.sym 23095 o_smi_read_req$SB_IO_OUT +.sym 23100 i_sck$SB_IO_IN +.sym 23104 i_rst_b_SB_LUT4_I3_O +.sym 23108 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 23110 rx_fifo.rd_addr_gray_wr[8] +.sym 23120 rx_fifo.wr_addr[0] +.sym 23122 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 23125 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 23127 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 23128 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 23129 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 23131 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 23135 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 23136 i_rst_b_SB_LUT4_I3_O +.sym 23139 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 23143 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 23145 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 23147 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 23149 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 23157 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 23158 rx_fifo.wr_addr[0] +.sym 23161 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 23168 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 23169 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 23173 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 23181 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 23187 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 23192 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 23194 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 23195 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 23196 lvds_clock_buf +.sym 23197 i_rst_b_SB_LUT4_I3_O +.sym 23201 w_rx_24_fifo_data[3] +.sym 23204 w_rx_24_fifo_data[21] +.sym 23205 spi_if_ins.spi.SCKr[2] +.sym 23208 i_ss_SB_LUT4_I3_O +.sym 23211 i_rst_b_SB_LUT4_I3_O +.sym 23222 r_counter +.sym 23223 i_ss$SB_IO_IN +.sym 23224 lvds_tx_inst.r_tx_state +.sym 23225 $PACKER_VCC_NET +.sym 23226 w_rx_24_fifo_data[6] +.sym 23227 r_counter +.sym 23229 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 23230 i_rst_b_SB_LUT4_I3_O +.sym 23231 w_rx_24_fifo_data[20] +.sym 23232 spi_if_ins.spi.SCKr[1] +.sym 23241 $PACKER_VCC_NET +.sym 23242 lvds_tx_inst.r_tx_state +.sym 23244 w_rx_09_fifo_data[17] +.sym 23246 w_rx_24_fifo_data[15] +.sym 23248 w_rx_24_fifo_data[17] +.sym 23250 w_rx_09_fifo_data[21] +.sym 23254 channel +.sym 23255 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 23257 lvds_tx_inst.r_state_SB_DFFER_Q_E +.sym 23259 i_rst_b_SB_LUT4_I3_O +.sym 23262 w_tx_fsm_state[0] +.sym 23263 w_rx_24_fifo_data[21] +.sym 23266 lvds_tx_inst.fifo_empty_d2 +.sym 23268 w_tx_fsm_state[1] +.sym 23275 w_rx_24_fifo_data[15] +.sym 23279 channel +.sym 23280 w_rx_24_fifo_data[21] +.sym 23281 w_rx_09_fifo_data[21] +.sym 23296 $PACKER_VCC_NET +.sym 23303 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 23308 w_rx_24_fifo_data[17] +.sym 23310 channel +.sym 23311 w_rx_09_fifo_data[17] +.sym 23314 lvds_tx_inst.r_tx_state +.sym 23315 lvds_tx_inst.fifo_empty_d2 +.sym 23316 w_tx_fsm_state[0] +.sym 23317 w_tx_fsm_state[1] +.sym 23318 lvds_tx_inst.r_state_SB_DFFER_Q_E +.sym 23319 lvds_clock_buf +.sym 23320 i_rst_b_SB_LUT4_I3_O +.sym 23324 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 23325 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 23327 int_miso +.sym 23336 w_rx_09_fifo_data[21] +.sym 23350 w_rx_24_fifo_data[7] +.sym 23351 $PACKER_VCC_NET +.sym 23352 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 23354 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23355 spi_if_ins.spi.SCKr[2] +.sym 23362 w_rx_24_fifo_data[15] +.sym 23363 w_rx_24_fifo_data[12] +.sym 23364 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 23365 w_rx_24_fifo_data[3] +.sym 23366 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 23367 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23368 w_rx_24_fifo_data[21] +.sym 23373 w_rx_24_fifo_data[31] +.sym 23374 w_rx_09_fifo_data[31] +.sym 23375 channel +.sym 23376 w_rx_24_fifo_data[14] +.sym 23387 w_rx_24_fifo_data[17] +.sym 23391 w_rx_24_fifo_data[18] +.sym 23396 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23397 w_rx_24_fifo_data[17] +.sym 23401 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23402 w_rx_24_fifo_data[15] +.sym 23407 w_rx_24_fifo_data[18] +.sym 23408 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23414 w_rx_24_fifo_data[31] +.sym 23415 w_rx_09_fifo_data[31] +.sym 23416 channel +.sym 23420 w_rx_24_fifo_data[14] +.sym 23422 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23425 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23427 w_rx_24_fifo_data[3] +.sym 23432 w_rx_24_fifo_data[12] +.sym 23434 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23437 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23438 w_rx_24_fifo_data[21] +.sym 23441 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 23442 lvds_clock_buf +.sym 23443 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 23445 $PACKER_VCC_NET +.sym 23446 spi_if_ins.spi.r_tx_bit_count[2] +.sym 23447 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 23448 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 23451 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 23455 w_rx_sync_09 +.sym 23457 int_miso +.sym 23458 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 23462 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 23463 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23468 i_rst_b_SB_LUT4_I3_O +.sym 23471 w_rx_24_fifo_data[28] +.sym 23473 spi_if_ins.r_tx_byte[7] +.sym 23476 i_rst_b_SB_LUT4_I3_O +.sym 23477 w_rx_24_fifo_data[18] +.sym 23478 w_rx_24_fifo_data[4] +.sym 23479 $PACKER_VCC_NET +.sym 23485 w_rx_24_fifo_data[29] +.sym 23487 w_rx_24_fifo_data[28] +.sym 23490 w_rx_24_fifo_data[5] +.sym 23493 w_rx_24_fifo_data[7] +.sym 23496 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 23497 channel +.sym 23502 $PACKER_VCC_NET +.sym 23503 w_rx_09_fifo_data[5] +.sym 23504 w_rx_24_fifo_data[4] +.sym 23505 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 23514 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23520 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23521 w_rx_24_fifo_data[5] +.sym 23532 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23533 w_rx_24_fifo_data[4] +.sym 23537 w_rx_24_fifo_data[29] +.sym 23539 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23543 w_rx_24_fifo_data[5] +.sym 23544 w_rx_09_fifo_data[5] +.sym 23545 channel +.sym 23550 $PACKER_VCC_NET +.sym 23554 w_rx_24_fifo_data[28] +.sym 23556 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23560 w_rx_24_fifo_data[7] +.sym 23561 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 23564 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 23565 lvds_clock_buf +.sym 23566 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 23568 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 23569 w_rx_24_fifo_push +.sym 23570 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 23571 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 23572 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 23582 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 23588 $PACKER_VCC_NET +.sym 23590 i_glob_clock$SB_IO_IN +.sym 23591 spi_if_ins.spi.r_tx_bit_count[2] +.sym 23592 i_rst_b_SB_LUT4_I3_O +.sym 23593 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23595 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 23596 i_rst_b_SB_LUT4_I3_O +.sym 23600 i_sck$SB_IO_IN +.sym 23609 $PACKER_VCC_NET +.sym 23612 w_rx_fifo_data[5] +.sym 23614 w_rx_data[2] +.sym 23617 r_counter +.sym 23621 w_rx_data[0] +.sym 23626 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 23628 i_rst_b_SB_LUT4_I3_O +.sym 23650 w_rx_fifo_data[5] +.sym 23653 w_rx_data[0] +.sym 23665 w_rx_data[2] +.sym 23671 $PACKER_VCC_NET +.sym 23678 $PACKER_VCC_NET +.sym 23687 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E +.sym 23688 r_counter +.sym 23689 i_rst_b_SB_LUT4_I3_O +.sym 23692 spi_if_ins.spi.r_tx_byte[3] +.sym 23693 spi_if_ins.spi.r_tx_byte[2] +.sym 23694 spi_if_ins.spi.r_tx_byte[7] +.sym 23695 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 23696 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 23700 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 23703 r_counter +.sym 23706 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 23714 r_counter +.sym 23715 i_rst_b_SB_LUT4_I3_O +.sym 23716 lvds_tx_inst.r_tx_state +.sym 23717 spi_if_ins.spi.SCKr[1] +.sym 23719 r_counter +.sym 23722 w_rx_fifo_full +.sym 23723 i_ss$SB_IO_IN +.sym 23733 spi_if_ins.r_tx_byte[4] +.sym 23735 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 23736 spi_if_ins.spi.r_tx_byte[1] +.sym 23738 spi_if_ins.r_tx_byte[6] +.sym 23740 r_counter +.sym 23742 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 23744 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 23747 spi_if_ins.spi.r_tx_byte[5] +.sym 23748 spi_if_ins.r_tx_byte[0] +.sym 23749 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 23751 spi_if_ins.spi.r_tx_bit_count[2] +.sym 23752 spi_if_ins.r_tx_byte[5] +.sym 23755 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 23758 spi_if_ins.r_tx_byte[1] +.sym 23760 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23761 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 23765 spi_if_ins.r_tx_byte[5] +.sym 23770 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 23771 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 23772 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 23773 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 23776 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 23782 spi_if_ins.r_tx_byte[0] +.sym 23788 spi_if_ins.spi.r_tx_byte[5] +.sym 23789 spi_if_ins.spi.r_tx_byte[1] +.sym 23790 spi_if_ins.spi.r_tx_bit_count[2] +.sym 23791 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 23797 spi_if_ins.r_tx_byte[1] +.sym 23802 spi_if_ins.r_tx_byte[4] +.sym 23808 spi_if_ins.r_tx_byte[6] +.sym 23810 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 23811 r_counter +.sym 23812 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23813 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 23814 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 23816 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 23817 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 23818 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 23820 lvds_tx_inst.r_tx_state +.sym 23827 spi_if_ins.r_tx_byte[4] +.sym 23831 spi_if_ins.r_tx_byte[3] +.sym 23833 spi_if_ins.r_tx_byte[2] +.sym 23841 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 23842 i_config[3]$SB_IO_IN +.sym 23844 lvds_tx_inst.r_tx_state +.sym 23845 w_fetch +.sym 23848 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 23858 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23865 spi_if_ins.r_tx_data_valid +.sym 23871 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23874 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 23875 i_rst_b$SB_IO_IN +.sym 23879 r_counter +.sym 23881 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 23882 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 23883 i_ss$SB_IO_IN +.sym 23894 spi_if_ins.r_tx_data_valid +.sym 23896 i_ss$SB_IO_IN +.sym 23907 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 23912 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 23924 i_rst_b$SB_IO_IN +.sym 23925 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 23926 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 23933 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 23934 r_counter +.sym 23935 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23936 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 23937 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 23938 w_fetch +.sym 23939 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 23940 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 23941 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 23942 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23943 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 23954 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23955 i_rst_b$SB_IO_IN +.sym 23960 i_rst_b_SB_LUT4_I3_O +.sym 23961 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 23964 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 23965 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 23966 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23968 i_rst_b_SB_LUT4_I3_O +.sym 23969 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 23970 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 23971 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 23977 r_counter +.sym 23978 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 23979 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 23980 io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[2] +.sym 23986 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 23987 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 23989 i_rst_b$SB_IO_IN +.sym 23990 i_button$SB_IO_IN +.sym 23992 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23993 i_ss$SB_IO_IN +.sym 23996 i_config[2]$SB_IO_IN +.sym 23999 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 24001 i_button_SB_LUT4_I2_I1[1] +.sym 24002 i_config[3]$SB_IO_IN +.sym 24010 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 24011 i_rst_b$SB_IO_IN +.sym 24012 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 24016 i_button_SB_LUT4_I2_I1[1] +.sym 24017 i_button$SB_IO_IN +.sym 24018 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 24023 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 24028 i_config[2]$SB_IO_IN +.sym 24030 i_button_SB_LUT4_I2_I1[1] +.sym 24031 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 24041 i_ss$SB_IO_IN +.sym 24052 i_button_SB_LUT4_I2_I1[1] +.sym 24053 i_config[3]$SB_IO_IN +.sym 24054 io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[2] +.sym 24056 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 24057 r_counter +.sym 24059 spi_if_ins.state_if[0] +.sym 24061 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] +.sym 24062 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 24064 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 24065 spi_if_ins.state_if[1] +.sym 24071 r_counter +.sym 24073 i_ss_SB_LUT4_I3_O +.sym 24075 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E +.sym 24079 i_rst_b$SB_IO_IN +.sym 24083 w_fetch +.sym 24085 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 24087 o_rx_h_tx_l$SB_IO_OUT +.sym 24092 i_sck$SB_IO_IN +.sym 24100 o_tr_vc1$SB_IO_OUT +.sym 24102 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 24103 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 24104 w_rx_data[2] +.sym 24107 io_ctrl_ins.pmod_dir_state[5] +.sym 24108 io_ctrl_ins.pmod_dir_state[7] +.sym 24109 i_rst_b$SB_IO_IN +.sym 24111 w_rx_data[6] +.sym 24113 o_rx_h_tx_l$SB_IO_OUT +.sym 24119 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 24120 io_ctrl_ins.pmod_dir_state[6] +.sym 24121 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24123 w_rx_data[7] +.sym 24124 o_rx_h_tx_l_b$SB_IO_OUT +.sym 24125 r_counter +.sym 24127 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24128 w_rx_data[5] +.sym 24129 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 24136 w_rx_data[7] +.sym 24139 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24140 o_tr_vc1$SB_IO_OUT +.sym 24141 io_ctrl_ins.pmod_dir_state[5] +.sym 24142 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24145 o_rx_h_tx_l$SB_IO_OUT +.sym 24146 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24147 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24148 io_ctrl_ins.pmod_dir_state[7] +.sym 24151 o_rx_h_tx_l_b$SB_IO_OUT +.sym 24152 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24153 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 24154 io_ctrl_ins.pmod_dir_state[6] +.sym 24159 w_rx_data[6] +.sym 24163 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 24164 i_rst_b$SB_IO_IN +.sym 24165 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 24166 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 24169 w_rx_data[2] +.sym 24177 w_rx_data[5] +.sym 24179 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 24180 r_counter +.sym 24182 w_load +.sym 24184 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 24194 i_button$SB_IO_IN +.sym 24195 i_rst_b$SB_IO_IN +.sym 24196 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O +.sym 24213 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 24215 i_ss$SB_IO_IN +.sym 24223 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 24239 r_counter +.sym 24241 spi_if_ins.spi.r2_rx_done +.sym 24246 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 24250 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24268 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24270 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 24274 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 24289 spi_if_ins.spi.r2_rx_done +.sym 24303 r_counter +.sym 24307 spi_if_ins.spi.r2_rx_done +.sym 24321 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O +.sym 24323 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 24328 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 24329 i_config[3]$SB_IO_IN +.sym 24332 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 24336 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 24337 r_counter +.sym 24350 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 24362 i_sck$SB_IO_IN +.sym 24373 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 24375 i_ss$SB_IO_IN +.sym 24379 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 24425 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 24426 i_sck$SB_IO_IN +.sym 24427 i_ss$SB_IO_IN +.sym 24440 o_tr_vc1$SB_IO_OUT +.sym 24446 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 24448 o_tr_vc2$SB_IO_OUT +.sym 24469 r_counter +.sym 24487 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 24491 w_rx_data[0] +.sym 24545 w_rx_data[0] +.sym 24548 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 24549 r_counter +.sym 24559 r_counter .sym 24596 o_led0$SB_IO_OUT -.sym 24607 o_led0$SB_IO_OUT -.sym 24659 i_sck$SB_IO_IN -.sym 24865 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 24868 smi_ctrl_ins.swe_and_reset -.sym 24882 w_smi_data_input[7] -.sym 24927 w_smi_data_input[7] -.sym 24932 smi_ctrl_ins.swe_and_reset -.sym 24933 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R -.sym 25100 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 24605 o_led0$SB_IO_OUT +.sym 24621 o_led0$SB_IO_OUT +.sym 24664 i_rst_b_SB_LUT4_I3_O +.sym 24685 r_counter +.sym 24700 rx_fifo.wr_addr_gray_rd[4] +.sym 24718 rx_fifo.wr_addr_gray_rd[4] +.sym 24765 r_counter +.sym 24796 rx_fifo.wr_addr_gray_rd[4] +.sym 24854 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 24860 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 24873 rx_fifo.rd_addr[0] +.sym 24911 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 24912 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 24915 rx_fifo.rd_addr[0] +.sym 24942 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 24946 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 25009 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 25012 rx_fifo.rd_addr[0] +.sym 25016 r_counter +.sym 25019 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 25022 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 25026 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 25027 i_rst_b_SB_LUT4_I3_O +.sym 25028 rx_fifo.wr_addr_gray_rd_r[0] +.sym 25030 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 25038 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 25041 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 25058 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 25060 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 25061 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 25065 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 25082 rx_fifo.wr_addr_gray_rd_r[0] +.sym 25084 rx_fifo.rd_addr[0] +.sym 25085 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 25086 rx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 25087 r_counter +.sym 25088 i_rst_b_SB_LUT4_I3_O +.sym 25168 i_rst_b_SB_LUT4_I3_O +.sym 25171 r_counter +.sym 25176 rx_fifo.wr_addr_gray_rd[1] +.sym 25180 rx_fifo.wr_addr_gray[1] +.sym 25219 i_rst_b_SB_LUT4_I3_O +.sym 25231 rx_fifo.wr_addr_gray[1] +.sym 25237 rx_fifo.wr_addr_gray_rd[1] +.sym 25242 r_counter +.sym 25256 i_rst_b_SB_LUT4_I3_O +.sym 25260 rx_fifo.wr_addr_SB_DFFESR_Q_E +.sym 25261 $PACKER_VCC_NET +.sym 25317 rx_fifo.rd_addr_gray[1] +.sym 25320 i_rst_b$SB_IO_IN +.sym 25325 rx_fifo.rd_addr_gray[8] +.sym 25344 rx_fifo.rd_addr_gray_wr[1] +.sym 25352 rx_fifo.rd_addr_gray_wr[1] +.sym 25358 rx_fifo.rd_addr_gray[8] +.sym 25369 rx_fifo.rd_addr_gray[1] +.sym 25387 i_rst_b$SB_IO_IN +.sym 25397 lvds_clock_buf .sym 25401 io_pmod_in[3]$SB_IO_IN +.sym 25473 w_rx_24_fifo_data[3] +.sym 25487 w_rx_24_fifo_data[21] +.sym 25491 spi_if_ins.spi.SCKr[1] +.sym 25497 r_counter +.sym 25525 w_rx_24_fifo_data[3] +.sym 25543 w_rx_24_fifo_data[21] +.sym 25547 spi_if_ins.spi.SCKr[1] +.sym 25552 r_counter .sym 25556 io_pmod_in[2]$SB_IO_IN +.sym 25563 i_rst_b_SB_LUT4_I3_O +.sym 25629 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25633 spi_if_ins.spi.SCKr[1] +.sym 25634 spi_if_ins.spi.SCKr[2] +.sym 25636 r_counter +.sym 25638 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25639 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25652 spi_if_ins.r_tx_byte[7] +.sym 25657 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 25678 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25684 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25685 spi_if_ins.spi.SCKr[2] +.sym 25686 spi_if_ins.spi.SCKr[1] +.sym 25696 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25698 spi_if_ins.r_tx_byte[7] +.sym 25699 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 25706 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25707 r_counter .sym 25711 i_glob_clock$SB_IO_IN -.sym 25720 io_pmod_out[3]$SB_IO_OUT -.sym 25878 i_glob_clock$SB_IO_IN -.sym 25954 r_counter -.sym 25962 i_glob_clock$SB_IO_IN -.sym 25978 r_counter -.sym 26017 i_glob_clock$SB_IO_IN -.sym 26018 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 26094 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 26113 spi_if_ins.w_rx_data[1] -.sym 26164 spi_if_ins.w_rx_data[1] -.sym 26171 spi_if_ins.o_ioc_SB_DFFE_Q_E -.sym 26172 r_counter_$glb_clk -.sym 26181 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] -.sym 26258 o_led1_SB_DFFER_Q_E -.sym 26263 w_rx_data[1] -.sym 26269 w_rx_data[0] -.sym 26301 w_rx_data[0] -.sym 26313 w_rx_data[1] -.sym 26326 o_led1_SB_DFFER_Q_E -.sym 26327 r_counter_$glb_clk -.sym 26328 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 26405 w_rx_data[2] -.sym 26419 w_rx_data[3] -.sym 26421 w_rx_data[0] -.sym 26429 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 26431 w_rx_data[1] -.sym 26435 w_rx_data[1] -.sym 26453 w_rx_data[3] -.sym 26467 w_rx_data[2] -.sym 26474 w_rx_data[0] -.sym 26481 io_ctrl_ins.pmod_state_SB_DFFE_Q_E -.sym 26482 r_counter_$glb_clk -.sym 26495 w_rx_data[2] -.sym 26575 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 26577 w_rx_fifo_full -.sym 26583 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 26626 w_rx_fifo_full -.sym 26627 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 26636 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 26637 lvds_clock_$glb_clk -.sym 26638 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 26719 w_rx_fifo_full -.sym 26723 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 26729 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 26730 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 26745 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 26746 w_rx_fifo_full -.sym 26748 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 26791 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E -.sym 26792 lvds_clock_$glb_clk -.sym 26793 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 26807 o_tr_vc2$SB_IO_OUT -.sym 26811 o_rx_h_tx_l$SB_IO_OUT -.sym 26960 o_tr_vc1_b$SB_IO_OUT +.sym 25721 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25722 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25786 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 25789 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 25791 r_counter +.sym 25793 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25800 spi_if_ins.spi.r_tx_bit_count[2] +.sym 25802 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 25804 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25807 $PACKER_VCC_NET +.sym 25814 $nextpnr_ICESTORM_LC_8$O +.sym 25817 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 25820 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 25822 $PACKER_VCC_NET +.sym 25823 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 25827 spi_if_ins.spi.r_tx_bit_count[2] +.sym 25829 $PACKER_VCC_NET +.sym 25830 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 25834 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25841 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 25857 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 25858 $PACKER_VCC_NET +.sym 25860 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 25861 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 25862 r_counter +.sym 25863 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 25873 r_counter +.sym 25876 $PACKER_VCC_NET +.sym 25883 i_rst_b_SB_LUT4_I3_O +.sym 25938 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 25939 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 25940 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 25941 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 25942 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 25943 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 25944 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 25947 spi_if_ins.spi.r_tx_bit_count[2] +.sym 25948 spi_if_ins.spi.SCKr[2] +.sym 25952 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 25954 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 25957 i_rst_b_SB_LUT4_I3_O +.sym 25960 spi_if_ins.spi.SCKr[1] +.sym 25964 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 25965 w_rx_fifo_full +.sym 25976 spi_if_ins.spi.SCKr[1] +.sym 25977 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 25978 spi_if_ins.spi.r_tx_bit_count[2] +.sym 25979 spi_if_ins.spi.SCKr[2] +.sym 25983 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 25985 w_rx_fifo_full +.sym 25988 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 25989 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 25990 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 25991 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 25995 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 26001 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 26002 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 26003 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 26016 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 26017 lvds_clock_buf +.sym 26018 i_rst_b_SB_LUT4_I3_O +.sym 26031 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 26092 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 26093 spi_if_ins.r_tx_byte[3] +.sym 26094 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 26096 spi_if_ins.spi.r_tx_bit_count[2] +.sym 26099 spi_if_ins.spi.r_tx_byte[6] +.sym 26101 spi_if_ins.r_tx_byte[7] +.sym 26102 spi_if_ins.spi.r_tx_byte[3] +.sym 26103 spi_if_ins.r_tx_byte[2] +.sym 26111 spi_if_ins.spi.r_tx_byte[2] +.sym 26112 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 26117 r_counter +.sym 26120 spi_if_ins.spi.r_tx_byte[7] +.sym 26138 spi_if_ins.r_tx_byte[3] +.sym 26146 spi_if_ins.r_tx_byte[2] +.sym 26149 spi_if_ins.r_tx_byte[7] +.sym 26155 spi_if_ins.spi.r_tx_byte[6] +.sym 26156 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 26157 spi_if_ins.spi.r_tx_byte[2] +.sym 26158 spi_if_ins.spi.r_tx_bit_count[2] +.sym 26161 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 26162 spi_if_ins.spi.r_tx_byte[7] +.sym 26163 spi_if_ins.spi.r_tx_bit_count[2] +.sym 26164 spi_if_ins.spi.r_tx_byte[3] +.sym 26171 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 26172 r_counter +.sym 26173 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 26183 spi_if_ins.r_tx_byte[7] +.sym 26247 i_rst_b$SB_IO_IN +.sym 26250 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 26251 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 26260 i_rst_b_SB_LUT4_I3_O +.sym 26263 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 26265 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26268 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 26270 lvds_tx_inst.tx_state_d1 +.sym 26273 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26275 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 26277 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26280 i_rst_b$SB_IO_IN +.sym 26281 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 26286 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26287 i_rst_b$SB_IO_IN +.sym 26288 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 26289 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 26298 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26299 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26300 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26301 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 26305 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26307 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 26310 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 26312 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26313 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26324 lvds_tx_inst.tx_state_d1 +.sym 26327 lvds_clock_buf +.sym 26328 i_rst_b_SB_LUT4_I3_O +.sym 26402 spi_if_ins.state_if[0] +.sym 26404 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 26405 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26406 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 26407 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26408 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 26410 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 26411 r_counter +.sym 26412 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] +.sym 26413 i_rst_b$SB_IO_IN +.sym 26414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 26416 spi_if_ins.state_if[1] +.sym 26422 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 26425 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26431 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 26435 i_rst_b$SB_IO_IN +.sym 26436 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] +.sym 26437 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 26438 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 26441 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] +.sym 26442 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 26443 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 26447 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 26453 spi_if_ins.state_if[1] +.sym 26454 spi_if_ins.state_if[0] +.sym 26455 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26459 spi_if_ins.state_if[0] +.sym 26460 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26462 spi_if_ins.state_if[1] +.sym 26465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26467 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26473 spi_if_ins.state_if[0] +.sym 26474 spi_if_ins.state_if[1] +.sym 26477 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26478 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 26480 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 26481 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 26482 r_counter +.sym 26483 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 26493 r_counter +.sym 26557 r_counter +.sym 26560 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 26561 i_rst_b_SB_LUT4_I3_O +.sym 26563 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 26564 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 26565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 26568 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 26576 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26579 spi_if_ins.state_if[1] +.sym 26581 spi_if_ins.state_if[0] +.sym 26584 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26591 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 26602 spi_if_ins.state_if[1] +.sym 26603 spi_if_ins.state_if[0] +.sym 26604 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26605 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26608 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 26620 spi_if_ins.state_if[0] +.sym 26623 spi_if_ins.state_if[1] +.sym 26626 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 26627 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 26629 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 26636 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 26637 r_counter +.sym 26638 i_rst_b_SB_LUT4_I3_O +.sym 26647 r_counter +.sym 26650 spi_if_ins.state_if_SB_DFFESR_Q_E +.sym 26656 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 26714 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 26716 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 26721 r_counter +.sym 26723 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26725 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26745 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 26759 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 26791 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 26792 r_counter +.sym 26793 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 26802 w_load +.sym 26808 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O +.sym 26813 r_counter +.sym 26867 spi_if_ins.spi.r_rx_done +.sym 26892 r_counter +.sym 26914 spi_if_ins.spi.r_rx_done +.sym 26947 r_counter +.sym 26966 o_rx_h_tx_l$SB_IO_OUT +.sym 27216 i_button$SB_IO_IN +.sym 27277 i_mosi$SB_IO_IN .sym 27283 o_smi_read_req$SB_IO_OUT .sym 27296 o_smi_read_req$SB_IO_OUT -.sym 27307 i_mosi$SB_IO_IN +.sym 27335 i_sck$SB_IO_IN +.sym 27337 i_ss$SB_IO_IN .sym 27397 i_glob_clock$SB_IO_IN -.sym 27400 io_pmod_out[3]$SB_IO_OUT -.sym 27420 io_pmod_out[3]$SB_IO_OUT -.sym 27429 smi_ctrl_ins.soe_and_reset -.sym 27444 smi_ctrl_ins.soe_and_reset -.sym 27459 r_counter -.sym 27470 r_counter -.sym 27515 o_rx_h_tx_l$SB_IO_OUT -.sym 27516 i_glob_clock$SB_IO_IN -.sym 27519 io_pmod_out[2]$SB_IO_OUT -.sym 27522 io_pmod_out[1]$SB_IO_OUT -.sym 27536 io_pmod_out[1]$SB_IO_OUT -.sym 27541 io_pmod_out[2]$SB_IO_OUT -.sym 27549 io_pmod_out[0]$SB_IO_OUT -.sym 27564 io_pmod_out[0]$SB_IO_OUT -.sym 27577 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27427 i_glob_clock$SB_IO_IN +.sym 27457 i_ss$SB_IO_IN +.sym 27545 o_rx_h_tx_l$SB_IO_OUT +.sym 27546 o_tr_vc1$SB_IO_OUT +.sym 27547 o_tr_vc2$SB_IO_OUT +.sym 27576 i_ss$SB_IO_IN .sym 27582 o_rx_h_tx_l$SB_IO_OUT -.sym 27593 o_rx_h_tx_l$SB_IO_OUT +.sym 27589 o_rx_h_tx_l$SB_IO_OUT .sym 27605 o_tr_vc1$SB_IO_OUT .sym 27608 o_tr_vc2$SB_IO_OUT -.sym 27617 o_tr_vc2$SB_IO_OUT .sym 27620 o_tr_vc1$SB_IO_OUT +.sym 27621 o_tr_vc2$SB_IO_OUT .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT .sym 27634 o_tr_vc1_b$SB_IO_OUT -.sym 27643 o_tr_vc1_b$SB_IO_OUT -.sym 27655 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27720 w_rx_09_fifo_data[12] -.sym 27721 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27724 w_rx_09_fifo_data[10] -.sym 27725 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27748 w_rx_09_fifo_data[21] -.sym 27749 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27752 w_rx_09_fifo_data[23] -.sym 27753 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27759 w_rx_24_fifo_data[25] -.sym 27760 w_rx_09_fifo_data[25] -.sym 27761 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27763 w_rx_24_fifo_data[27] -.sym 27764 w_rx_09_fifo_data[27] -.sym 27765 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27768 w_rx_09_fifo_data[25] -.sym 27769 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27771 w_rx_09_fifo_data[23] -.sym 27772 w_rx_24_fifo_data[23] -.sym 27773 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27780 w_rx_09_fifo_data[13] -.sym 27781 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27784 w_rx_09_fifo_data[17] -.sym 27785 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27787 w_rx_24_fifo_data[13] -.sym 27788 w_rx_09_fifo_data[13] -.sym 27789 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27796 w_rx_09_fifo_data[19] -.sym 27797 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27800 w_rx_09_fifo_data[27] -.sym 27801 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27804 w_rx_09_fifo_data[15] -.sym 27805 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27808 w_rx_09_fifo_data[8] -.sym 27809 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27812 w_rx_09_fifo_data[4] -.sym 27813 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27816 w_rx_09_fifo_data[7] -.sym 27817 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27820 w_rx_09_fifo_data[9] -.sym 27821 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27824 w_rx_09_fifo_data[29] -.sym 27825 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27828 w_rx_09_fifo_data[5] -.sym 27829 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27832 w_rx_09_fifo_data[6] -.sym 27833 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27836 w_rx_09_fifo_data[11] -.sym 27837 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27839 w_rx_24_fifo_data[7] -.sym 27840 w_rx_09_fifo_data[7] -.sym 27841 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27843 w_rx_09_fifo_data[4] -.sym 27844 w_rx_24_fifo_data[4] -.sym 27845 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27847 w_rx_09_fifo_data[9] -.sym 27848 w_rx_24_fifo_data[9] -.sym 27849 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27852 w_rx_24_fifo_data[13] -.sym 27853 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27856 w_rx_24_fifo_data[9] -.sym 27857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27859 w_rx_24_fifo_data[11] -.sym 27860 w_rx_09_fifo_data[11] -.sym 27861 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27864 w_rx_24_fifo_data[4] -.sym 27865 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27868 w_rx_24_fifo_data[11] -.sym 27869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27872 w_rx_24_fifo_data[7] -.sym 27873 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27876 w_rx_24_fifo_data[5] -.sym 27877 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27880 w_rx_24_fifo_data[0] -.sym 27881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27889 lvds_clock -.sym 27892 w_rx_24_fifo_data[3] -.sym 27893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27895 w_rx_24_fifo_data[5] -.sym 27896 w_rx_09_fifo_data[5] -.sym 27897 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27900 w_rx_24_fifo_data[1] -.sym 27901 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27904 w_rx_24_fifo_data[2] -.sym 27905 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27908 w_rx_09_fifo_data[3] -.sym 27909 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27912 w_rx_09_fifo_data[28] -.sym 27913 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27916 w_rx_09_fifo_data[2] -.sym 27917 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27919 w_rx_09_fifo_data[3] -.sym 27920 w_rx_24_fifo_data[3] -.sym 27921 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27924 w_rx_09_fifo_data[0] -.sym 27925 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27927 w_rx_24_fifo_data[2] -.sym 27928 w_rx_09_fifo_data[2] -.sym 27929 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 27932 w_rx_09_fifo_data[1] -.sym 27933 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 27937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 27939 rx_fifo.wr_addr[1] -.sym 27944 rx_fifo.wr_addr[2] -.sym 27945 rx_fifo.wr_addr[1] -.sym 27948 rx_fifo.wr_addr[3] -.sym 27949 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 -.sym 27952 rx_fifo.wr_addr[4] -.sym 27953 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 -.sym 27956 rx_fifo.wr_addr[5] -.sym 27957 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 27960 rx_fifo.wr_addr[6] -.sym 27961 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 27964 rx_fifo.wr_addr[7] -.sym 27965 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 27968 rx_fifo.wr_addr[8] -.sym 27969 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 27972 rx_fifo.wr_addr[9] -.sym 27973 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 -.sym 27977 w_lvds_rx_24_d0 -.sym 27978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 27979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 27980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 27981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] -.sym 27983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] -.sym 27984 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] -.sym 27985 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] -.sym 27987 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 27988 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] -.sym 27989 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 27991 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 27992 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] -.sym 27993 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 27995 rx_fifo.rd_addr_gray_wr_r[7] -.sym 27996 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.sym 27997 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 27998 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 27999 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] -.sym 28000 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 28001 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] -.sym 28002 w_lvds_rx_09_d0 -.sym 28012 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 28013 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 28016 i_rst_b$SB_IO_IN -.sym 28017 w_lvds_rx_09_d1_SB_LUT4_I0_O[1] -.sym 28035 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.sym 28038 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28039 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] -.sym 28040 $PACKER_VCC_NET -.sym 28041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 -.sym 28042 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28043 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28044 $PACKER_VCC_NET -.sym 28045 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28048 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -.sym 28049 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] -.sym 28061 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] -.sym 28062 w_lvds_rx_09_d1 -.sym 28063 w_lvds_rx_09_d0 -.sym 28064 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28065 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28066 w_lvds_rx_24_d1 -.sym 28067 w_lvds_rx_24_d0 -.sym 28068 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28069 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28073 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 28075 w_lvds_rx_24_d1 -.sym 28076 w_lvds_rx_24_d0 -.sym 28077 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28084 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] -.sym 28085 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] -.sym 28086 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 28087 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28088 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28089 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 28090 w_lvds_rx_24_d1 -.sym 28091 w_lvds_rx_24_d0 -.sym 28092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28095 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] -.sym 28096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28097 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] -.sym 28099 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] -.sym 28102 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28103 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] -.sym 28104 $PACKER_VCC_NET -.sym 28105 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] -.sym 28106 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28107 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] -.sym 28108 $PACKER_VCC_NET -.sym 28109 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 -.sym 28110 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 28111 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28112 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28113 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 28117 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 -.sym 28118 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28119 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28120 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 28121 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 28122 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 -.sym 28123 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 28124 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] -.sym 28125 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28129 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 -.sym 28130 w_lvds_rx_09_d1 -.sym 28131 w_lvds_rx_09_d0 -.sym 28132 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28133 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28136 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28137 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28144 w_lvds_rx_09_d1 -.sym 28145 w_lvds_rx_09_d0 -.sym 28151 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28152 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28153 w_lvds_rx_09_d1_SB_LUT4_I2_O[2] -.sym 28158 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28195 w_rx_24_fifo_data[20] -.sym 28196 w_rx_09_fifo_data[20] -.sym 28197 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28200 w_rx_09_fifo_data[18] -.sym 28201 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28204 w_rx_09_fifo_data[22] -.sym 28205 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28211 w_rx_24_fifo_data[22] -.sym 28212 w_rx_09_fifo_data[22] -.sym 28213 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28220 w_rx_09_fifo_data[20] -.sym 28221 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28224 w_rx_09_fifo_data[24] -.sym 28225 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28228 w_rx_24_fifo_data[20] -.sym 28229 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28231 w_rx_24_fifo_data[24] -.sym 28232 w_rx_09_fifo_data[24] -.sym 28233 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28235 w_rx_24_fifo_data[14] -.sym 28236 w_rx_09_fifo_data[14] -.sym 28237 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28240 w_rx_24_fifo_data[22] -.sym 28241 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28244 w_rx_24_fifo_data[12] -.sym 28245 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28248 w_rx_24_fifo_data[14] -.sym 28249 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28252 w_rx_24_fifo_data[18] -.sym 28253 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28255 w_rx_09_fifo_data[12] -.sym 28256 w_rx_24_fifo_data[12] -.sym 28257 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28260 w_rx_24_fifo_data[16] -.sym 28261 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28264 w_rx_24_fifo_data[27] -.sym 28265 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28268 w_rx_24_fifo_data[23] -.sym 28269 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28272 w_rx_24_fifo_data[24] -.sym 28273 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28276 w_rx_24_fifo_data[8] -.sym 28277 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28280 w_rx_24_fifo_data[25] -.sym 28281 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28284 w_rx_24_fifo_data[10] -.sym 28285 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28288 w_rx_24_fifo_data[26] -.sym 28289 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28292 w_rx_09_fifo_data[14] -.sym 28293 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28295 w_rx_09_fifo_data[16] -.sym 28296 w_rx_24_fifo_data[16] -.sym 28297 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28299 w_rx_24_fifo_data[21] -.sym 28300 w_rx_09_fifo_data[21] -.sym 28301 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28303 w_rx_24_fifo_data[15] -.sym 28304 w_rx_09_fifo_data[15] -.sym 28305 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28308 w_rx_09_fifo_data[26] -.sym 28309 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28311 w_rx_24_fifo_data[10] -.sym 28312 w_rx_09_fifo_data[10] -.sym 28313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28315 w_rx_09_fifo_data[18] -.sym 28316 w_rx_24_fifo_data[18] -.sym 28317 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28320 w_rx_09_fifo_data[16] -.sym 28321 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 28322 w_rx_fifo_pulled_data[5] -.sym 28335 w_rx_24_fifo_data[8] -.sym 28336 w_rx_09_fifo_data[8] -.sym 28337 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28339 w_rx_24_fifo_data[29] -.sym 28340 w_rx_09_fifo_data[29] -.sym 28341 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28343 w_rx_09_fifo_data[17] -.sym 28344 w_rx_24_fifo_data[17] -.sym 28345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28347 w_rx_09_fifo_data[6] -.sym 28348 w_rx_24_fifo_data[6] -.sym 28349 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28351 w_rx_24_fifo_data[19] -.sym 28352 w_rx_09_fifo_data[19] -.sym 28353 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28356 w_rx_24_fifo_data[6] -.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28360 w_rx_24_fifo_data[19] -.sym 28361 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28364 w_rx_24_fifo_data[28] -.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28368 w_rx_24_fifo_data[17] -.sym 28369 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28372 w_rx_24_fifo_data[21] -.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28375 w_rx_09_fifo_data[31] -.sym 28376 w_rx_24_fifo_data[31] -.sym 28377 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28380 w_rx_24_fifo_data[29] -.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28384 w_rx_24_fifo_data[15] -.sym 28385 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28391 i_rst_b$SB_IO_IN -.sym 28392 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28393 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 28394 w_rx_fifo_pulled_data[11] -.sym 28399 w_rx_09_fifo_data[28] -.sym 28400 w_rx_24_fifo_data[28] -.sym 28401 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28402 w_rx_fifo_pulled_data[10] -.sym 28406 w_rx_fifo_pulled_data[18] -.sym 28410 w_rx_fifo_pulled_data[9] -.sym 28415 w_rx_09_fifo_data[30] -.sym 28416 w_rx_24_fifo_data[30] -.sym 28417 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28418 w_rx_fifo_pulled_data[0] -.sym 28426 w_rx_fifo_pulled_data[3] -.sym 28438 w_rx_fifo_pulled_data[1] -.sym 28442 w_rx_fifo_pulled_data[2] -.sym 28450 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28455 w_rx_24_fifo_data[0] -.sym 28456 w_rx_09_fifo_data[0] -.sym 28457 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28460 rx_fifo.wr_addr[1] -.sym 28461 rx_fifo.wr_addr[0] -.sym 28462 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 28470 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28475 w_rx_24_fifo_data[1] -.sym 28476 w_rx_09_fifo_data[1] -.sym 28477 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28478 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28483 rx_fifo.rd_addr_gray_wr_r[4] -.sym 28484 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] -.sym 28485 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] -.sym 28487 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28488 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] -.sym 28489 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] -.sym 28492 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28496 i_rst_b$SB_IO_IN -.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 28498 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 28499 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] -.sym 28500 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] -.sym 28501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] -.sym 28504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 28505 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] -.sym 28506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] -.sym 28507 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] -.sym 28508 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] -.sym 28509 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] -.sym 28510 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 28511 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 28512 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] -.sym 28513 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] -.sym 28514 w_rx_fifo_full -.sym 28515 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 28516 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28519 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 28520 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28522 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 28523 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] -.sym 28524 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28525 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28526 rx_fifo.rd_addr_gray_wr[0] -.sym 28530 rx_fifo.rd_addr_gray[0] -.sym 28535 rx_fifo.full_o_SB_LUT4_I0_O[0] -.sym 28536 rx_fifo.full_o_SB_LUT4_I0_O[1] -.sym 28537 rx_fifo.full_o_SB_LUT4_I0_O[2] -.sym 28538 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] -.sym 28539 rx_fifo.wr_addr[1] -.sym 28540 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] -.sym 28541 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 28542 rx_fifo.wr_addr[2] -.sym 28543 rx_fifo.rd_addr_gray_wr_r[1] -.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] -.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] -.sym 28546 rx_fifo.rd_addr[9] -.sym 28554 rx_fifo.rd_addr_gray_wr[9] -.sym 28562 rx_fifo.rd_addr_gray[5] -.sym 28566 rx_fifo.rd_addr_gray_wr[5] -.sym 28584 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28585 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28587 w_lvds_rx_24_d1 -.sym 28588 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 28589 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 28604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] -.sym 28605 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28620 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 28621 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] -.sym 28624 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28625 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] -.sym 28636 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] -.sym 28637 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28638 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] -.sym 28664 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] -.sym 28665 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 28670 w_lvds_rx_09_d1 -.sym 28671 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] -.sym 28672 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28673 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] -.sym 28706 tx_fifo.rd_addr_gray[3] -.sym 28710 tx_fifo.rd_addr_gray[2] -.sym 28714 tx_fifo.rd_addr_gray_wr[5] -.sym 28718 tx_fifo.rd_addr_gray[5] -.sym 28722 tx_fifo.rd_addr_gray_wr[6] -.sym 28726 tx_fifo.rd_addr_gray_wr[3] -.sym 28730 tx_fifo.rd_addr_gray[6] -.sym 28738 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 28739 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 28740 smi_ctrl_ins.int_cnt_rx[4] -.sym 28741 smi_ctrl_ins.int_cnt_rx[3] -.sym 28742 w_rx_fifo_pulled_data[13] -.sym 28746 w_rx_fifo_pulled_data[26] -.sym 28750 w_rx_fifo_pulled_data[15] -.sym 28754 w_rx_fifo_pulled_data[23] -.sym 28758 w_rx_fifo_pulled_data[21] -.sym 28762 w_rx_fifo_pulled_data[20] -.sym 28766 w_rx_fifo_pulled_data[22] -.sym 28782 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 28786 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 28791 tx_fifo.rd_addr[2] -.sym 28792 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 28793 tx_fifo.rd_addr[1] -.sym 28794 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 28795 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 28796 smi_ctrl_ins.int_cnt_rx[4] -.sym 28797 smi_ctrl_ins.int_cnt_rx[3] -.sym 28799 w_rx_09_fifo_data[26] -.sym 28800 w_rx_24_fifo_data[26] -.sym 28801 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 28802 w_rx_fifo_pulled_data[24] -.sym 28806 w_rx_fifo_pulled_data[25] -.sym 28810 w_rx_fifo_pulled_data[27] -.sym 28814 w_rx_fifo_pulled_data[12] -.sym 28818 w_rx_fifo_pulled_data[6] -.sym 28822 w_rx_fifo_pulled_data[14] -.sym 28826 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 28827 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 28828 smi_ctrl_ins.int_cnt_rx[4] -.sym 28829 smi_ctrl_ins.int_cnt_rx[3] -.sym 28830 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 28831 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 28832 smi_ctrl_ins.int_cnt_rx[4] -.sym 28833 smi_ctrl_ins.int_cnt_rx[3] -.sym 28834 w_rx_fifo_pulled_data[8] -.sym 28842 w_rx_fifo_pulled_data[16] -.sym 28846 w_rx_fifo_pulled_data[7] -.sym 28850 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 28851 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 28852 smi_ctrl_ins.int_cnt_rx[4] -.sym 28853 smi_ctrl_ins.int_cnt_rx[3] -.sym 28854 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 28855 smi_ctrl_ins.int_cnt_rx[4] -.sym 28856 smi_ctrl_ins.int_cnt_rx[3] -.sym 28857 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 28862 w_rx_fifo_pulled_data[4] -.sym 28869 rx_fifo.rd_addr[0] -.sym 28877 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 28878 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 28879 smi_ctrl_ins.int_cnt_rx[4] -.sym 28880 smi_ctrl_ins.int_cnt_rx[3] -.sym 28881 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 28882 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28886 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 28897 rx_fifo.wr_addr[4] -.sym 28899 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 28900 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28901 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28907 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 28908 rx_fifo.wr_addr_gray_rd_r[5] -.sym 28909 rx_fifo.rd_addr[5] -.sym 28910 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28914 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28922 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 28929 rx_fifo.wr_addr[0] -.sym 28931 rx_fifo.wr_addr[0] -.sym 28936 rx_fifo.wr_addr[1] -.sym 28940 rx_fifo.wr_addr[2] -.sym 28941 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28944 rx_fifo.wr_addr[3] -.sym 28945 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28948 rx_fifo.wr_addr[4] -.sym 28949 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28952 rx_fifo.wr_addr[5] -.sym 28953 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28956 rx_fifo.wr_addr[6] -.sym 28957 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 28960 rx_fifo.wr_addr[7] -.sym 28961 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 28964 rx_fifo.wr_addr[8] -.sym 28965 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 -.sym 28968 rx_fifo.wr_addr[9] -.sym 28969 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 28972 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28973 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 28974 rx_fifo.rd_addr_gray_wr_r[1] -.sym 28975 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 28976 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] -.sym 28977 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] -.sym 28980 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 28981 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 28983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 28984 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28985 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28988 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28989 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 28992 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28993 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 28997 rx_fifo.rd_addr[1] -.sym 28998 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.sym 28999 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] -.sym 29000 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] -.sym 29001 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] -.sym 29002 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] -.sym 29003 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29004 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29005 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.sym 29006 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] -.sym 29007 rx_fifo.rd_addr_gray_wr_r[4] -.sym 29008 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 29009 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 29014 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 29015 rx_fifo.wr_addr_gray_rd_r[5] -.sym 29016 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 29017 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 29018 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] -.sym 29025 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29026 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 29031 rx_fifo.rd_addr[5] -.sym 29032 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 29033 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29038 rx_fifo.wr_addr_gray_rd_r[9] -.sym 29039 rx_fifo.rd_addr[9] -.sym 29040 rx_fifo.wr_addr_gray_rd_r[8] -.sym 29041 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 29042 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] -.sym 29046 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] -.sym 29057 rx_fifo.wr_addr[1] -.sym 29062 rx_fifo.wr_addr_gray_rd[4] -.sym 29066 rx_fifo.wr_addr_gray_rd[5] -.sym 29070 rx_fifo.wr_addr_gray_rd[8] -.sym 29074 rx_fifo.wr_addr_gray[5] -.sym 29082 rx_fifo.wr_addr_gray[8] -.sym 29086 rx_fifo.wr_addr_gray[1] -.sym 29090 rx_fifo.wr_addr_gray[4] -.sym 29098 rx_fifo.wr_addr_gray[2] -.sym 29102 rx_fifo.wr_addr_gray[6] -.sym 29108 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29109 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29110 rx_fifo.wr_addr_gray_rd[2] -.sym 29118 rx_fifo.wr_addr_gray[3] -.sym 29124 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29125 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29126 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29130 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 29134 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 29150 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 29221 tx_fifo.rd_addr[0] -.sym 29222 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 29226 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 29230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 29236 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 29237 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29238 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29242 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 29246 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29250 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 29251 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29252 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 29253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] -.sym 29255 tx_fifo.wr_addr_gray_rd_r[2] -.sym 29256 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 29257 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29260 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29261 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29264 i_rst_b$SB_IO_IN -.sym 29265 w_tx_fifo_pull -.sym 29268 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29269 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 29270 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 29275 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 29276 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] -.sym 29277 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] -.sym 29279 tx_fifo.wr_addr_gray_rd_r[2] -.sym 29280 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 29281 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29283 tx_fifo.rd_addr[3] -.sym 29284 tx_fifo.rd_addr[2] -.sym 29285 tx_fifo.wr_addr_gray_rd_r[2] -.sym 29286 tx_fifo.rd_addr[4] -.sym 29287 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] -.sym 29288 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] -.sym 29289 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] -.sym 29290 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 29291 smi_ctrl_ins.int_cnt_rx[4] -.sym 29292 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 29293 smi_ctrl_ins.int_cnt_rx[3] -.sym 29294 tx_fifo.rd_addr[7] -.sym 29295 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] -.sym 29296 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] -.sym 29297 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] -.sym 29298 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 29299 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 29300 smi_ctrl_ins.int_cnt_rx[4] -.sym 29301 smi_ctrl_ins.int_cnt_rx[3] -.sym 29302 tx_fifo.rd_addr[7] -.sym 29303 tx_fifo.rd_addr[6] -.sym 29304 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 29305 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] -.sym 29307 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] -.sym 29308 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] -.sym 29309 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] -.sym 29310 tx_fifo.wr_addr_gray_rd[1] -.sym 29316 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] -.sym 29317 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] -.sym 29320 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] -.sym 29321 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] -.sym 29324 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] -.sym 29325 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] -.sym 29328 smi_ctrl_ins.int_cnt_rx[4] -.sym 29329 smi_ctrl_ins.int_cnt_rx[3] -.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 27647 o_tr_vc1_b$SB_IO_OUT +.sym 27653 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27683 lvds_tx_inst.r_sync_count[0] +.sym 27687 lvds_tx_inst.r_sync_count[1] +.sym 27688 $PACKER_VCC_NET +.sym 27690 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 27691 lvds_tx_inst.r_sync_count[2] +.sym 27692 $PACKER_VCC_NET +.sym 27693 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] +.sym 27694 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 27695 lvds_tx_inst.r_sync_count[3] +.sym 27696 $PACKER_VCC_NET +.sym 27697 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] +.sym 27704 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 27705 lvds_tx_inst.r_sync_count[0] +.sym 27710 lvds_tx_inst.r_sync_count[0] +.sym 27711 lvds_tx_inst.r_sync_count[1] +.sym 27712 lvds_tx_inst.r_sync_count[2] +.sym 27713 lvds_tx_inst.r_sync_count[3] +.sym 27715 lvds_tx_inst.r_gap_frame_count[0] +.sym 27719 lvds_tx_inst.r_gap_frame_count[1] +.sym 27720 $PACKER_VCC_NET +.sym 27721 lvds_tx_inst.r_gap_frame_count[0] +.sym 27723 lvds_tx_inst.r_gap_frame_count[2] +.sym 27724 $PACKER_VCC_NET +.sym 27725 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] +.sym 27727 lvds_tx_inst.r_gap_frame_count[3] +.sym 27728 $PACKER_VCC_NET +.sym 27729 lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] +.sym 27734 lvds_tx_inst.r_gap_frame_count[0] +.sym 27735 lvds_tx_inst.r_gap_frame_count[1] +.sym 27736 lvds_tx_inst.r_gap_frame_count[2] +.sym 27737 lvds_tx_inst.r_gap_frame_count[3] +.sym 27745 lvds_tx_inst.r_gap_frame_count[0] +.sym 27746 lvds_tx_inst.r_fifo_data[6] +.sym 27747 w_tx_fifo_pulled_data[6] +.sym 27748 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27749 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27750 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 27751 w_tx_fifo_pulled_data[4] +.sym 27752 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27753 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27754 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 27755 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[1] +.sym 27756 w_tx_fsm_state[0] +.sym 27757 w_tx_fsm_state[1] +.sym 27759 w_tx_fsm_state[0] +.sym 27760 w_tx_fsm_state[1] +.sym 27761 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[2] +.sym 27763 w_tx_fsm_state[0] +.sym 27764 w_tx_fsm_state[1] +.sym 27765 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[2] +.sym 27768 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 27769 lvds_tx_inst.frame_boundary +.sym 27770 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 27771 w_tx_fifo_pulled_data[8] +.sym 27772 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27773 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27774 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 27775 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 27776 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 27777 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 27778 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 27779 w_tx_fifo_pulled_data[29] +.sym 27780 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27781 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27782 lvds_tx_inst.r_fifo_data[15] +.sym 27783 w_tx_fifo_pulled_data[15] +.sym 27784 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27785 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27787 lvds_tx_inst.r_fifo_data[7] +.sym 27788 lvds_tx_inst.r_fifo_data[15] +.sym 27789 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27791 w_tx_fsm_state[0] +.sym 27792 w_tx_fsm_state[1] +.sym 27793 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[2] +.sym 27794 lvds_tx_inst.r_fifo_data[6] +.sym 27795 lvds_tx_inst.r_fifo_data[14] +.sym 27796 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 27797 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27798 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 27802 lvds_tx_inst.r_fifo_data[5] +.sym 27803 w_tx_fifo_pulled_data[5] +.sym 27804 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27805 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27806 lvds_tx_inst.r_fifo_data[7] +.sym 27807 w_tx_fifo_pulled_data[7] +.sym 27808 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27809 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27811 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 27815 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 27816 $PACKER_VCC_NET +.sym 27817 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 27819 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27820 $PACKER_VCC_NET +.sym 27821 lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 27823 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 27824 $PACKER_VCC_NET +.sym 27825 lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[3] +.sym 27829 w_smi_data_direction +.sym 27830 lvds_tx_inst.r_tx_state +.sym 27836 lvds_tx_inst.pending_load_SB_DFFER_Q_D +.sym 27837 lvds_tx_inst.frame_boundary +.sym 27841 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 27842 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 27843 w_tx_fifo_pulled_data[20] +.sym 27844 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27845 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27847 w_tx_fsm_state[0] +.sym 27848 w_tx_fsm_state[1] +.sym 27849 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] +.sym 27850 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 27851 w_tx_fifo_pulled_data[28] +.sym 27852 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27853 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27854 lvds_tx_inst.r_fifo_data[11] +.sym 27855 w_tx_fifo_pulled_data[11] +.sym 27856 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27857 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27858 w_tx_fifo_pulled_data[0] +.sym 27859 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 27860 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27861 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27863 w_tx_fsm_state[0] +.sym 27864 w_tx_fsm_state[1] +.sym 27865 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[2] +.sym 27866 lvds_tx_inst.r_fifo_data[25] +.sym 27867 w_tx_fifo_pulled_data[25] +.sym 27868 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27869 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27870 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 27871 w_tx_fifo_pulled_data[10] +.sym 27872 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 27873 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 27877 w_lvds_tx_d0 +.sym 27879 io_pmod_in[3]$SB_IO_IN +.sym 27880 w_rx_sync_09 +.sym 27881 w_rx_sync_type_09 +.sym 27882 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] +.sym 27883 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] +.sym 27884 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27885 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 27886 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 27887 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 27888 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] +.sym 27889 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 27890 lvds_tx_inst.r_fifo_data[18] +.sym 27891 lvds_tx_inst.r_fifo_data[26] +.sym 27892 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27893 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 27894 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 27895 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] +.sym 27896 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[2] +.sym 27897 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[3] +.sym 27898 lvds_tx_inst.r_fifo_data[17] +.sym 27899 lvds_tx_inst.r_fifo_data[25] +.sym 27900 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27901 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 27902 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 27903 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] +.sym 27904 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 27905 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 27906 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 27907 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 27908 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 27909 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 27914 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 27915 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 27916 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 27917 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 27919 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[0] +.sym 27920 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] +.sym 27921 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 27922 lvds_tx_inst.fifo_empty_d1 +.sym 27929 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 27930 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 27931 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] +.sym 27932 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[2] +.sym 27933 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] +.sym 27941 w_lvds_tx_d1 +.sym 27942 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 27947 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 27948 tx_fifo.rd_addr[5] +.sym 27949 tx_fifo.rd_addr[6] +.sym 27950 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 27954 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 27959 tx_fifo.rd_addr[5] +.sym 27960 tx_fifo.rd_addr[6] +.sym 27961 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 27965 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 27970 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 27971 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[1] +.sym 27972 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 27973 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[3] +.sym 27975 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27976 w_lvds_rx_09_d1 +.sym 27977 w_lvds_rx_09_d0 +.sym 27978 w_rx_data[0] +.sym 27984 tx_fifo.wr_addr_gray_rd_r[6] +.sym 27985 tx_fifo.rd_addr[6] +.sym 27987 tx_fifo.wr_addr_gray_rd_r[6] +.sym 27988 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 27989 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 27990 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[0] +.sym 27991 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 27992 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 27993 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 27994 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.sym 27995 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.sym 27996 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.sym 27997 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.sym 27998 tx_fifo.wr_addr_gray_rd_r[9] +.sym 27999 tx_fifo.rd_addr[9] +.sym 28000 w_tx_fifo_pull +.sym 28001 tx_fifo.empty_o_SB_LUT4_O_I3 +.sym 28002 tx_fifo.wr_addr_gray_rd[6] +.sym 28008 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 28009 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 28012 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 28013 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 28014 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 28015 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 28016 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 28017 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 28018 tx_fifo.wr_addr_gray_rd[3] +.sym 28023 tx_fifo.wr_addr_gray_rd_r[3] +.sym 28024 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 28025 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 28026 tx_fifo.wr_addr_gray_rd[7] +.sym 28030 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 28031 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 28032 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 28033 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] +.sym 28036 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 28037 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] +.sym 28039 tx_fifo.wr_addr_gray_rd_r[3] +.sym 28040 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 28041 tx_fifo.rd_addr[4] +.sym 28042 tx_fifo.rd_addr_gray[3] +.sym 28050 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 28051 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 28052 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 28053 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 28054 tx_fifo.rd_addr_gray_wr[3] +.sym 28058 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.sym 28059 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.sym 28060 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.sym 28061 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.sym 28063 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 28064 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] +.sym 28065 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28066 tx_fifo.wr_addr_gray[5] +.sym 28070 tx_fifo.wr_addr_gray_rd[5] +.sym 28074 tx_fifo.wr_addr_gray[8] +.sym 28078 tx_fifo.wr_addr_gray[7] +.sym 28082 tx_fifo.wr_addr_gray[4] +.sym 28086 tx_fifo.wr_addr_gray_rd[8] +.sym 28090 tx_fifo.wr_addr_gray_rd[4] +.sym 28094 tx_fifo.wr_addr_gray[3] +.sym 28106 tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 28112 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 28113 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 28126 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 28130 tx_fifo.rd_addr_gray[2] +.sym 28134 tx_fifo.rd_addr_gray_wr[6] +.sym 28138 tx_fifo.rd_addr_gray[6] +.sym 28142 tx_fifo.rd_addr_gray[7] +.sym 28146 tx_fifo.rd_addr_gray[4] +.sym 28154 tx_fifo.rd_addr_gray_wr[4] +.sym 28182 tx_fifo.rd_addr_gray[5] +.sym 28198 smi_ctrl_ins.d_q3[1] +.sym 28202 smi_ctrl_ins.d_q3[4] +.sym 28206 smi_ctrl_ins.d_q3[0] +.sym 28222 smi_ctrl_ins.d_q3[5] +.sym 28251 w_tx_fsm_state[0] +.sym 28252 w_tx_fsm_state[1] +.sym 28253 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[2] +.sym 28255 w_tx_fsm_state[0] +.sym 28256 w_tx_fsm_state[1] +.sym 28257 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[2] +.sym 28258 smi_ctrl_ins.frame_sr[16] +.sym 28262 smi_ctrl_ins.frame_sr[19] +.sym 28266 smi_ctrl_ins.d_byte[4] +.sym 28270 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 28271 w_tx_fifo_pulled_data[12] +.sym 28272 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28273 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28274 lvds_tx_inst.r_fifo_data[13] +.sym 28275 w_tx_fifo_pulled_data[13] +.sym 28276 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28277 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28278 lvds_tx_inst.r_fifo_data[31] +.sym 28279 w_tx_fifo_pulled_data[31] +.sym 28280 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28281 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28282 lvds_tx_inst.r_fifo_data[3] +.sym 28283 w_tx_fifo_pulled_data[3] +.sym 28284 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28285 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28286 smi_ctrl_ins.d_byte[5] +.sym 28290 smi_ctrl_ins.frame_sr[12] +.sym 28294 lvds_tx_inst.r_fifo_data[16] +.sym 28295 w_tx_fifo_pulled_data[16] +.sym 28296 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28297 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28298 smi_ctrl_ins.d_byte[0] +.sym 28302 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[0] +.sym 28303 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[1] +.sym 28304 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28305 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 28306 w_tx_fsm_state[1] +.sym 28307 lvds_tx_inst.fifo_empty_d2 +.sym 28308 w_tx_fsm_state[0] +.sym 28309 lvds_tx_inst.r_tx_state +.sym 28311 lvds_tx_inst.r_fifo_data[5] +.sym 28312 lvds_tx_inst.r_fifo_data[13] +.sym 28313 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28314 smi_ctrl_ins.d_byte[1] +.sym 28318 lvds_tx_inst.r_fifo_data[23] +.sym 28319 lvds_tx_inst.r_fifo_data[31] +.sym 28320 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28321 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28322 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 28323 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.sym 28324 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28325 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3] +.sym 28326 lvds_tx_inst.r_fifo_data[17] +.sym 28327 w_tx_fifo_pulled_data[17] +.sym 28328 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28329 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28331 lvds_tx_inst.fifo_empty_d2 +.sym 28332 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[1] +.sym 28333 lvds_tx_inst.r_tx_state +.sym 28334 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 28335 lvds_tx_inst.sent_first_sync +.sym 28336 w_tx_fsm_state[0] +.sym 28337 w_tx_fsm_state[1] +.sym 28339 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28340 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 28341 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 28342 lvds_tx_inst.r_fifo_data[16] +.sym 28343 lvds_tx_inst.r_fifo_data[24] +.sym 28344 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28345 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 28350 io_ctrl_ins.rf_pin_state[0] +.sym 28351 i_button_SB_LUT4_I2_I1[2] +.sym 28352 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 28353 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 28356 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 28357 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28358 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 28359 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[1] +.sym 28360 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[2] +.sym 28361 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[3] +.sym 28362 lvds_tx_inst.r_fifo_data[3] +.sym 28363 lvds_tx_inst.r_fifo_data[11] +.sym 28364 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28365 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 28366 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 28367 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 28368 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 28369 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] +.sym 28370 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] +.sym 28371 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] +.sym 28372 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28373 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[3] +.sym 28376 w_rx_fifo_full +.sym 28377 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 28382 lvds_tx_inst.r_fifo_data[22] +.sym 28383 lvds_tx_inst.r_fifo_data[30] +.sym 28384 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28385 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28387 lvds_tx_inst.r_fifo_data[19] +.sym 28388 lvds_tx_inst.r_fifo_data[27] +.sym 28389 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28396 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 28397 channel +.sym 28400 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 28401 w_smi_data_direction +.sym 28404 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 28405 w_tx_fifo_full +.sym 28407 w_rx_09_fifo_data[11] +.sym 28408 w_rx_24_fifo_data[11] +.sym 28409 channel +.sym 28410 lvds_tx_inst.r_fifo_data[1] +.sym 28411 lvds_tx_inst.r_fifo_data[9] +.sym 28412 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] +.sym 28413 lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] +.sym 28416 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] +.sym 28417 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] +.sym 28418 lvds_tx_inst.r_fifo_data[19] +.sym 28419 w_tx_fifo_pulled_data[19] +.sym 28420 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28421 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28422 lvds_tx_inst.r_fifo_data[27] +.sym 28423 w_tx_fifo_pulled_data[27] +.sym 28424 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28425 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28426 lvds_tx_inst.r_fifo_data[18] +.sym 28427 w_tx_fifo_pulled_data[18] +.sym 28428 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28429 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28432 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 28433 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 28434 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.sym 28435 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.sym 28436 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.sym 28437 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.sym 28438 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] +.sym 28439 w_tx_fifo_pulled_data[2] +.sym 28440 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28441 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28442 lvds_tx_inst.r_fifo_data[9] +.sym 28443 w_tx_fifo_pulled_data[9] +.sym 28444 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28445 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28446 lvds_tx_inst.r_fifo_data[1] +.sym 28447 w_tx_fifo_pulled_data[1] +.sym 28448 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28449 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28450 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 28451 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 28452 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 28453 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.sym 28455 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 28456 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 28457 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 28458 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28463 w_rx_24_fifo_push +.sym 28464 w_rx_09_fifo_push +.sym 28465 channel +.sym 28470 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 28474 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 28478 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28483 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 28488 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] +.sym 28489 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 28492 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 28493 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 28496 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 28497 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 28500 tx_fifo.rd_addr[4] +.sym 28501 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 28504 tx_fifo.rd_addr[5] +.sym 28505 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 28508 tx_fifo.rd_addr[6] +.sym 28509 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 28512 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] +.sym 28513 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 28516 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 28517 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 28520 tx_fifo.rd_addr[9] +.sym 28521 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 28523 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 28524 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28525 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 28526 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 28530 tx_fifo.wr_addr_gray_rd[2] +.sym 28534 tx_fifo.wr_addr_gray[2] +.sym 28540 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 28541 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 28542 tx_fifo.wr_addr_gray_rd[9] +.sym 28546 tx_fifo.wr_addr_gray_rd_r[8] +.sym 28547 tx_fifo.wr_addr_gray_rd_r[9] +.sym 28548 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 28549 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 28556 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 28557 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] +.sym 28562 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 28566 tx_fifo.rd_addr[9] +.sym 28567 tx_fifo.wr_addr_gray_rd_r[9] +.sym 28568 tx_fifo.wr_addr_gray_rd_r[8] +.sym 28569 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] +.sym 28578 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 28588 w_tx_fifo_pull +.sym 28589 i_rst_b$SB_IO_IN +.sym 28594 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 28598 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 28602 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 28621 tx_fifo.rd_addr_SB_DFFESR_Q_E +.sym 28629 i_rst_b_SB_LUT4_I3_O +.sym 28630 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 28648 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28649 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 28652 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28653 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28656 tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] +.sym 28657 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28658 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 28664 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 28665 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 28666 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 28674 tx_fifo.rd_addr[9] +.sym 28686 tx_fifo.rd_addr_gray[1] +.sym 28690 tx_fifo.rd_addr_gray[0] +.sym 28698 tx_fifo.rd_addr_gray_wr[2] +.sym 28702 tx_fifo.rd_addr_gray[8] +.sym 28710 smi_ctrl_ins.frame_sr[23] +.sym 28711 smi_ctrl_ins.frame_sr[15] +.sym 28712 smi_ctrl_ins.byte_ix[3] +.sym 28713 smi_ctrl_ins.frame_sr[7] +.sym 28715 w_rx_09_fifo_data[8] +.sym 28716 w_rx_24_fifo_data[8] +.sym 28717 channel +.sym 28719 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 28720 smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[1] +.sym 28721 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 28724 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 28725 smi_ctrl_ins.byte_ix[2] +.sym 28726 w_rx_fifo_pulled_data[19] +.sym 28730 w_rx_fifo_pulled_data[10] +.sym 28734 w_rx_fifo_pulled_data[9] +.sym 28738 smi_ctrl_ins.d_byte[3] +.sym 28742 smi_ctrl_ins.d_byte[0] +.sym 28746 smi_ctrl_ins.d_byte[1] +.sym 28750 smi_ctrl_ins.d_byte[5] +.sym 28754 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 28758 smi_ctrl_ins.d_byte[2] +.sym 28762 smi_ctrl_ins.d_byte[6] +.sym 28766 smi_ctrl_ins.d_byte[4] +.sym 28770 smi_ctrl_ins.d_byte[5] +.sym 28774 smi_ctrl_ins.d_byte[4] +.sym 28778 smi_ctrl_ins.d_byte[2] +.sym 28782 smi_ctrl_ins.d_byte[3] +.sym 28786 smi_ctrl_ins.d_byte[6] +.sym 28790 smi_ctrl_ins.d_byte[0] +.sym 28794 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 28798 smi_ctrl_ins.d_byte[1] +.sym 28802 smi_ctrl_ins.frame_sr[13] +.sym 28806 smi_ctrl_ins.frame_sr[8] +.sym 28810 smi_ctrl_ins.d_byte[3] +.sym 28814 smi_ctrl_ins.d_byte[6] +.sym 28818 smi_ctrl_ins.frame_sr[18] +.sym 28822 smi_ctrl_ins.frame_sr[9] +.sym 28826 smi_ctrl_ins.frame_sr[10] +.sym 28830 smi_ctrl_ins.frame_sr[22] +.sym 28837 i_smi_swe_srw$SB_IO_IN +.sym 28838 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 28839 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 28840 smi_ctrl_ins.byte_ix[0] +.sym 28841 smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] +.sym 28844 w_tx_fifo_full +.sym 28845 smi_ctrl_ins.push_req +.sym 28846 lvds_tx_inst.r_fifo_data[26] +.sym 28847 w_tx_fifo_pulled_data[26] +.sym 28848 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28849 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 28850 smi_ctrl_ins.swe_q2 +.sym 28855 w_rx_09_fifo_data[10] +.sym 28856 w_rx_24_fifo_data[10] +.sym 28857 channel +.sym 28858 smi_ctrl_ins.swe_q1 +.sym 28864 smi_ctrl_ins.swe_q2 +.sym 28865 smi_ctrl_ins.swe_q2_d +.sym 28868 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 28869 w_rx_24_fifo_data[13] +.sym 28876 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 28877 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 28880 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 28881 w_rx_24_fifo_data[25] +.sym 28884 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 28885 w_rx_24_fifo_data[16] +.sym 28888 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 28889 w_rx_24_fifo_data[11] +.sym 28891 w_rx_09_fifo_data[15] +.sym 28892 w_rx_24_fifo_data[15] +.sym 28893 channel +.sym 28896 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 28897 w_rx_24_fifo_data[24] +.sym 28898 w_tx_fifo_full +.sym 28899 smi_ctrl_ins.push_req +.sym 28900 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 28901 smi_ctrl_ins.byte_ix[3] +.sym 28902 w_lvds_rx_09_d0 +.sym 28907 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 28908 tx_fifo.rd_addr[4] +.sym 28909 tx_fifo.rd_addr[5] +.sym 28911 w_rx_09_fifo_data[27] +.sym 28912 w_rx_24_fifo_data[27] +.sym 28913 channel +.sym 28914 w_rx_fifo_push +.sym 28915 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 28916 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 28917 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 28919 w_rx_09_fifo_data[0] +.sym 28920 w_rx_24_fifo_data[0] +.sym 28921 channel +.sym 28923 w_lvds_rx_09_d1 +.sym 28924 lvds_rx_09_inst.r_sync_input +.sym 28925 lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] +.sym 28927 w_rx_09_fifo_data[23] +.sym 28928 w_rx_24_fifo_data[23] +.sym 28929 channel +.sym 28932 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 28933 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28943 w_lvds_rx_24_d1 +.sym 28944 lvds_rx_24_inst.r_sync_input +.sym 28945 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 28949 w_lvds_rx_24_d0 +.sym 28955 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 28956 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 28957 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28961 tx_fifo.wr_addr[2] +.sym 28973 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 28975 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 28976 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 28977 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 28982 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 28983 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 28984 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 28985 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 28990 lvds_tx_inst.r_fifo_data[30] +.sym 28991 w_tx_fifo_pulled_data[30] +.sym 28992 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 28993 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 29001 tx_fifo.wr_addr[2] +.sym 29009 w_lvds_tx_d1 +.sym 29013 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 29019 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 29020 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 29021 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29023 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 29024 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29025 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 29026 tx_fifo.wr_addr_gray[6] +.sym 29030 tx_fifo.wr_addr_gray[0] +.sym 29034 tx_fifo.wr_addr_gray[1] +.sym 29038 tx_fifo.wr_addr_gray_rd[0] +.sym 29042 tx_fifo.wr_addr_gray_rd[1] +.sym 29046 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] +.sym 29047 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 29048 tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 29049 w_tx_fifo_pull +.sym 29054 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 29055 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 29056 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 29057 tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 29061 tx_fifo.wr_addr[0] +.sym 29063 tx_fifo.rd_addr_gray_wr_r[2] +.sym 29064 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 29065 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 29066 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 29070 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 29074 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 29075 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 29076 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 29077 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 29078 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 29082 tx_wr_en +.sym 29083 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 29084 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 29085 w_tx_fifo_full +.sym 29086 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 29087 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 29088 tx_wr_en +.sym 29089 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 29090 w_fetch +.sym 29091 w_cs[2] +.sym 29092 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 29093 w_load +.sym 29096 tx_fifo.wr_addr[0] +.sym 29097 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 29105 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 29108 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 29109 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 29111 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 29112 w_ioc[0] +.sym 29113 w_ioc[1] +.sym 29114 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 29120 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 29121 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 29125 tx_fifo.wr_addr[2] +.sym 29128 w_lvds_rx_09_d0 +.sym 29129 w_lvds_rx_09_d1 +.sym 29130 tx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 29134 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 29140 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 29141 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 29144 spi_if_ins.spi.r3_rx_done +.sym 29145 spi_if_ins.spi.r2_rx_done +.sym 29146 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 29153 tx_fifo.wr_addr[4] +.sym 29157 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 29158 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 29159 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 29160 w_ioc[0] +.sym 29161 w_ioc[1] +.sym 29163 tx_fifo.rd_addr_gray_wr_r[7] +.sym 29164 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 29165 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 29166 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 29171 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 29172 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 29173 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 29176 tx_fifo.wr_addr[2] +.sym 29177 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 29178 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 29184 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 29185 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 29186 tx_fifo.rd_addr_gray_wr[0] +.sym 29192 tx_fifo.wr_addr[0] +.sym 29193 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 29198 tx_fifo.rd_addr_gray_wr[9] +.sym 29202 tx_fifo.rd_addr_gray_wr[8] +.sym 29206 tx_fifo.rd_addr_gray_wr[1] +.sym 29210 tx_fifo.rd_addr_gray_wr[7] +.sym 29214 tx_fifo.rd_addr_gray_wr[5] +.sym 29218 smi_ctrl_ins.d_q2[1] +.sym 29222 smi_ctrl_ins.d_q2[2] +.sym 29226 smi_ctrl_ins.d_q1[6] +.sym 29230 smi_ctrl_ins.d_q1[2] +.sym 29234 w_smi_data_input[2] +.sym 29238 w_smi_data_input[4] +.sym 29242 w_smi_data_input[6] +.sym 29246 smi_ctrl_ins.d_q1[0] +.sym 29250 smi_ctrl_ins.d_q1[1] +.sym 29254 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 29255 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 29256 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] +.sym 29257 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] +.sym 29258 smi_ctrl_ins.d_q2[0] +.sym 29262 smi_ctrl_ins.d_q2[4] +.sym 29266 smi_ctrl_ins.d_q2[6] +.sym 29270 smi_ctrl_ins.d_q2[3] +.sym 29274 w_smi_data_input[1] +.sym 29278 smi_ctrl_ins.d_q1[4] +.sym 29282 smi_ctrl_ins.d_q3[7] +.sym 29286 smi_ctrl_ins.d_q3[3] +.sym 29290 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[0] +.sym 29291 smi_ctrl_ins.byte_ix[0] +.sym 29292 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29293 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 29297 smi_ctrl_ins.frame_sr_SB_DFFER_Q_E +.sym 29298 smi_ctrl_ins.d_q3[6] +.sym 29304 smi_ctrl_ins.byte_ix[1] +.sym 29305 smi_ctrl_ins.byte_ix[2] +.sym 29308 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29309 smi_ctrl_ins.byte_ix[1] +.sym 29310 smi_ctrl_ins.d_q3[2] +.sym 29315 w_rx_09_fifo_data[22] +.sym 29316 w_rx_24_fifo_data[22] +.sym 29317 channel +.sym 29318 smi_ctrl_ins.d_byte[4] +.sym 29323 w_rx_09_fifo_data[20] +.sym 29324 w_rx_24_fifo_data[20] +.sym 29325 channel +.sym 29326 smi_ctrl_ins.d_byte[3] +.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[28] .sym 29332 smi_ctrl_ins.int_cnt_rx[4] .sym 29333 smi_ctrl_ins.int_cnt_rx[3] -.sym 29336 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] -.sym 29337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] -.sym 29338 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 29339 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 29340 smi_ctrl_ins.int_cnt_rx[4] -.sym 29341 smi_ctrl_ins.int_cnt_rx[3] -.sym 29346 smi_ctrl_ins.w_fifo_pull_trigger -.sym 29359 smi_ctrl_ins.r_fifo_pull_1 -.sym 29360 w_smi_read_req -.sym 29361 smi_ctrl_ins.r_fifo_pull -.sym 29370 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 29371 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 29372 smi_ctrl_ins.int_cnt_rx[4] -.sym 29373 smi_ctrl_ins.int_cnt_rx[3] -.sym 29374 smi_ctrl_ins.r_fifo_pull -.sym 29378 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 29379 smi_ctrl_ins.int_cnt_rx[4] -.sym 29380 smi_ctrl_ins.int_cnt_rx[3] -.sym 29381 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 29384 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] -.sym 29385 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] -.sym 29388 i_rst_b$SB_IO_IN -.sym 29389 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 29392 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] -.sym 29393 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] -.sym 29402 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 29403 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 29404 smi_ctrl_ins.int_cnt_rx[4] -.sym 29405 smi_ctrl_ins.int_cnt_rx[3] -.sym 29411 rx_fifo.rd_addr[0] -.sym 29416 rx_fifo.rd_addr[1] -.sym 29417 rx_fifo.rd_addr[0] -.sym 29420 rx_fifo.rd_addr[2] -.sym 29421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 29424 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 29428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 29429 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 -.sym 29432 rx_fifo.rd_addr[5] -.sym 29433 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 29436 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 29437 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29440 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 29441 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29444 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 29445 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29448 rx_fifo.rd_addr[9] -.sym 29449 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29453 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29454 w_rx_data[0] -.sym 29459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] -.sym 29460 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 29461 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29466 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 29467 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 29468 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 29469 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] -.sym 29471 rx_fifo.wr_addr_gray_rd_r[5] -.sym 29472 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 29473 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29476 rx_fifo.wr_addr_SB_DFFESR_Q_D[0] -.sym 29477 rx_fifo.wr_addr_SB_DFFESR_Q_D[1] -.sym 29478 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] -.sym 29479 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 29480 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] -.sym 29481 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] -.sym 29482 i_sck$SB_IO_IN -.sym 29486 rx_fifo.wr_addr_gray_rd[3] -.sym 29490 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 29494 spi_if_ins.spi.SCKr[0] -.sym 29499 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 29500 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.sym 29501 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 29502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 29506 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 29507 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 29508 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] -.sym 29509 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] -.sym 29512 rx_fifo.rd_addr[2] -.sym 29513 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29514 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] -.sym 29515 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] -.sym 29516 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] -.sym 29517 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] -.sym 29518 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] -.sym 29519 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] -.sym 29520 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 29521 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 29522 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] -.sym 29523 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] -.sym 29524 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] -.sym 29525 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] -.sym 29527 rx_fifo.rd_addr[2] -.sym 29528 rx_fifo.rd_addr[1] -.sym 29529 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 29531 rx_fifo.wr_addr_gray_rd_r[8] -.sym 29532 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29533 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29535 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 29536 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29537 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] -.sym 29539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] -.sym 29540 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] -.sym 29541 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] -.sym 29543 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 29544 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] -.sym 29545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 29546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 29550 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] -.sym 29554 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 29558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] -.sym 29562 rx_fifo.wr_addr_gray_rd_r[9] -.sym 29563 rx_fifo.rd_addr[1] -.sym 29564 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 29565 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29568 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29569 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29570 rx_fifo.wr_addr_gray_rd[9] -.sym 29574 rx_fifo.wr_addr_gray_rd[0] -.sym 29578 rx_fifo.wr_addr_gray_rd[6] -.sym 29582 rx_fifo.wr_addr[9] -.sym 29586 w_smi_read_req_SB_LUT4_I1_I3[0] -.sym 29587 w_smi_read_req -.sym 29588 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 29589 w_smi_read_req_SB_LUT4_I1_I3[3] -.sym 29590 rx_fifo.wr_addr_gray[0] -.sym 29594 rx_fifo.wr_addr_gray_rd[1] -.sym 29598 w_smi_read_req_SB_LUT4_I1_O[0] -.sym 29599 w_smi_read_req_SB_LUT4_I1_O[1] -.sym 29600 w_smi_read_req_SB_LUT4_I1_O[2] -.sym 29601 w_smi_read_req_SB_LUT4_I1_O[3] -.sym 29608 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] -.sym 29609 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29610 rx_fifo.rd_addr_gray_wr_r[7] -.sym 29611 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] -.sym 29612 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] -.sym 29613 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] -.sym 29620 rx_fifo.rd_addr_gray_wr_r[4] -.sym 29621 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 29622 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] -.sym 29626 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29634 rx_fifo.rd_addr_gray[7] -.sym 29638 rx_fifo.rd_addr_gray_wr[8] -.sym 29642 rx_fifo.rd_addr_gray_wr[4] -.sym 29646 rx_fifo.rd_addr_gray_wr[7] -.sym 29650 rx_fifo.rd_addr_gray[8] -.sym 29654 rx_fifo.rd_addr_gray[4] -.sym 29658 rx_fifo.rd_addr_gray[3] -.sym 29662 rx_fifo.rd_addr_gray_wr[3] -.sym 29666 rx_fifo.wr_addr_gray_rd[7] -.sym 29678 rx_fifo.wr_addr_gray[7] -.sym 29731 tx_fifo.rd_addr[0] -.sym 29736 tx_fifo.rd_addr[1] -.sym 29737 tx_fifo.rd_addr[0] -.sym 29740 tx_fifo.rd_addr[2] -.sym 29741 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 -.sym 29744 tx_fifo.rd_addr[3] -.sym 29745 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 29748 tx_fifo.rd_addr[4] -.sym 29749 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 29752 tx_fifo.rd_addr[5] -.sym 29753 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 -.sym 29756 tx_fifo.rd_addr[6] -.sym 29757 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 29760 tx_fifo.rd_addr[7] -.sym 29761 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29764 tx_fifo.rd_addr[8] -.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29768 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 29769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 29770 w_tx_fifo_pull -.sym 29771 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 29772 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 29773 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] -.sym 29777 smi_ctrl_ins.int_cnt_rx[3] -.sym 29780 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29781 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29782 tx_fifo.rd_addr[4] -.sym 29783 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 29784 tx_fifo.rd_addr[2] -.sym 29785 tx_fifo.wr_addr_gray_rd_r[2] -.sym 29788 smi_ctrl_ins.int_cnt_rx[4] -.sym 29789 smi_ctrl_ins.int_cnt_rx[3] -.sym 29791 tx_fifo.rd_addr[4] -.sym 29792 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] -.sym 29793 tx_fifo.rd_addr[3] -.sym 29794 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] -.sym 29795 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] -.sym 29796 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] -.sym 29797 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] -.sym 29800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 29801 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 29803 w_tx_fifo_pull -.sym 29804 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 29805 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29806 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 29807 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 29808 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 29809 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 29812 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29813 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29814 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29815 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 29816 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] -.sym 29817 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] -.sym 29818 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 29819 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 29820 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] -.sym 29821 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] -.sym 29823 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 29824 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] -.sym 29825 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 29828 tx_fifo.rd_addr[5] -.sym 29829 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] -.sym 29834 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] -.sym 29842 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29846 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 29847 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 29848 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] -.sym 29849 tx_fifo.rd_addr[8] -.sym 29850 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] -.sym 29856 tx_fifo.rd_addr[8] -.sym 29857 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] -.sym 29858 tx_fifo.wr_addr_gray[6] -.sym 29862 tx_fifo.wr_addr_gray[8] -.sym 29866 tx_fifo.wr_addr_gray_rd[3] -.sym 29870 tx_fifo.wr_addr_gray_rd[2] -.sym 29874 tx_fifo.wr_addr_gray[4] -.sym 29878 tx_fifo.wr_addr_gray_rd[7] -.sym 29882 tx_fifo.wr_addr_gray_rd[8] -.sym 29886 tx_fifo.wr_addr_gray_rd[4] -.sym 29898 tx_fifo.wr_addr_gray_rd[6] -.sym 29906 tx_fifo.wr_addr_gray_rd[0] -.sym 29914 tx_fifo.wr_addr_gray[1] -.sym 29922 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 29926 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 29934 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 29938 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 29942 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 29946 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 29960 w_smi_read_req_SB_LUT4_I1_I3[2] -.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 29964 i_ss$SB_IO_IN -.sym 29965 spi_if_ins.r_tx_data_valid -.sym 29968 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 29969 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] -.sym 29972 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] -.sym 29973 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 29974 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 29979 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 29980 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 29981 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] -.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] -.sym 29986 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 29992 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] -.sym 29993 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] -.sym 29995 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 29996 spi_if_ins.state_if[1] -.sym 29997 spi_if_ins.state_if[0] -.sym 29998 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 29999 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30000 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30001 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 30003 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 30004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30005 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] -.sym 30006 i_rst_b$SB_IO_IN -.sym 30007 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 30008 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30009 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 30012 i_rst_b$SB_IO_IN -.sym 30013 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30014 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30018 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] -.sym 30019 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] -.sym 30020 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] -.sym 30021 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] -.sym 30023 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30024 spi_if_ins.state_if[1] -.sym 30025 spi_if_ins.state_if[0] -.sym 30028 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30029 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30033 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30036 spi_if_ins.state_if[1] -.sym 30037 spi_if_ins.state_if[0] -.sym 30039 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30040 spi_if_ins.state_if[1] -.sym 30041 spi_if_ins.state_if[0] -.sym 30043 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30047 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 30048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] -.sym 30049 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] -.sym 30050 rx_fifo.rd_addr_gray[2] -.sym 30054 rx_fifo.rd_addr_gray[6] -.sym 30066 rx_fifo.rd_addr_gray_wr[2] -.sym 30070 rx_fifo.rd_addr_gray_wr[1] -.sym 30078 rx_fifo.rd_addr_gray_wr[6] -.sym 30082 w_rx_data[2] -.sym 30093 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E -.sym 30098 w_rx_data[0] -.sym 30108 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] -.sym 30109 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] -.sym 30126 rx_fifo.rd_addr_gray[1] -.sym 30152 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 30153 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 30167 io_pmod_in[2]$SB_IO_IN -.sym 30168 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30169 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30195 io_pmod_in[3]$SB_IO_IN -.sym 30196 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30197 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30217 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] -.sym 30244 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 30245 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 30246 tx_fifo.wr_addr[9] -.sym 30250 tx_fifo.wr_addr_gray_rd[9] -.sym 30256 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30257 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 30258 tx_fifo.wr_addr_gray[3] -.sym 30265 i_rst_b$SB_IO_IN -.sym 30268 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 30269 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 30271 i_rst_b$SB_IO_IN -.sym 30272 smi_ctrl_ins.int_cnt_rx[4] -.sym 30273 smi_ctrl_ins.int_cnt_rx[3] -.sym 30275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 30276 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 30277 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 30280 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] -.sym 30281 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30284 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] -.sym 30285 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] -.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 30294 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 30298 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] -.sym 30303 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 30304 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 30305 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 30306 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 30307 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 30308 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30309 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30310 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] -.sym 30311 tx_fifo.rd_addr[1] -.sym 30312 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] -.sym 30313 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30314 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30319 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] -.sym 30320 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] -.sym 30321 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] -.sym 30322 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] -.sym 30326 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30330 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30331 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 30332 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 30334 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 30335 smi_ctrl_ins.r_fifo_pulled_data[20] +.sym 29334 smi_ctrl_ins.d_byte[0] +.sym 29338 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 29344 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29345 smi_ctrl_ins.byte_ix[0] +.sym 29346 smi_ctrl_ins.frame_sr[21] +.sym 29350 smi_ctrl_ins.frame_sr[3] +.sym 29354 smi_ctrl_ins.frame_sr[4] +.sym 29358 $PACKER_VCC_NET +.sym 29362 smi_ctrl_ins.frame_sr[1] +.sym 29367 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.sym 29368 w_tx_fsm_state[0] +.sym 29369 w_tx_fsm_state[1] +.sym 29370 smi_ctrl_ins.d_byte[2] +.sym 29374 smi_ctrl_ins.frame_sr[2] +.sym 29380 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29381 w_rx_24_fifo_data[9] +.sym 29384 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29385 w_rx_24_fifo_data[23] +.sym 29388 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29389 w_rx_24_fifo_data[26] +.sym 29392 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29393 w_rx_24_fifo_data[2] +.sym 29396 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29397 w_rx_24_fifo_data[19] +.sym 29400 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29401 w_rx_24_fifo_data[1] +.sym 29404 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29405 w_rx_24_fifo_data[27] +.sym 29408 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29409 w_rx_24_fifo_data[0] +.sym 29412 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29413 w_rx_09_fifo_data[1] +.sym 29416 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29417 w_rx_09_fifo_data[15] +.sym 29420 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29421 w_rx_09_fifo_data[18] +.sym 29424 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29425 w_rx_09_fifo_data[9] +.sym 29428 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29429 w_rx_09_fifo_data[11] +.sym 29436 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29437 w_rx_09_fifo_data[4] +.sym 29440 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29441 w_rx_09_fifo_data[21] +.sym 29442 spi_if_ins.spi.r_rx_byte[6] +.sym 29446 spi_if_ins.spi.r_rx_byte[1] +.sym 29450 spi_if_ins.spi.r_rx_byte[5] +.sym 29454 spi_if_ins.spi.r_rx_byte[0] +.sym 29458 spi_if_ins.spi.r_rx_byte[4] +.sym 29462 spi_if_ins.spi.r_rx_byte[7] +.sym 29470 spi_if_ins.spi.r_rx_byte[2] +.sym 29474 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 29478 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 29482 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 29486 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 29490 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 29494 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 29498 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 29502 i_mosi$SB_IO_IN +.sym 29507 lvds_rx_24_inst.r_phase_count[0] +.sym 29511 lvds_rx_24_inst.r_phase_count[1] +.sym 29512 $PACKER_VCC_NET +.sym 29513 lvds_rx_24_inst.r_phase_count[0] +.sym 29514 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 29516 $PACKER_VCC_NET +.sym 29517 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 29520 w_lvds_rx_24_d1 +.sym 29521 w_lvds_rx_24_d0 +.sym 29522 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 29523 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 29524 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 29525 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29526 tx_fifo.rd_addr_gray_wr_r[3] +.sym 29527 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 29528 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 29529 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.sym 29530 w_rx_fifo_push +.sym 29531 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.sym 29532 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.sym 29533 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.sym 29534 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 29535 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 29536 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 29537 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29538 smi_ctrl_ins.frame_sr[0] +.sym 29542 smi_ctrl_ins.frame_sr[20] +.sym 29547 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 29548 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 29549 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29550 smi_ctrl_ins.frame_sr[11] +.sym 29554 smi_ctrl_ins.frame_sr[17] +.sym 29566 smi_ctrl_ins.frame_sr[14] +.sym 29571 tx_fifo.wr_addr[0] +.sym 29576 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 29577 tx_fifo.wr_addr[0] +.sym 29580 tx_fifo.wr_addr[2] +.sym 29581 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 29584 tx_fifo.wr_addr[3] +.sym 29585 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 29588 tx_fifo.wr_addr[4] +.sym 29589 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 29592 tx_fifo.wr_addr[5] +.sym 29593 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 29596 tx_fifo.wr_addr[6] +.sym 29597 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 29600 tx_fifo.wr_addr[7] +.sym 29601 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 29604 tx_fifo.wr_addr[8] +.sym 29605 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 29608 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 29609 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] +.sym 29610 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 29614 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 29618 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 29624 tx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 29625 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 29626 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 29631 tx_fifo.rd_addr_gray_wr_r[3] +.sym 29632 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 29633 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 29635 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 29640 tx_fifo.wr_addr[2] +.sym 29644 tx_fifo.wr_addr[3] +.sym 29645 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 29648 tx_fifo.wr_addr[4] +.sym 29649 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 29652 tx_fifo.wr_addr[5] +.sym 29653 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 29656 tx_fifo.wr_addr[6] +.sym 29657 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 29660 tx_fifo.wr_addr[7] +.sym 29661 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 29664 tx_fifo.wr_addr[8] +.sym 29665 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 29666 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 29667 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 29668 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +.sym 29669 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 29670 spi_if_ins.w_rx_data[2] +.sym 29674 spi_if_ins.w_rx_data[3] +.sym 29679 tx_fifo.rd_addr_gray_wr_r[6] +.sym 29680 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] +.sym 29681 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] +.sym 29684 tx_wr_en +.sym 29685 i_rst_b$SB_IO_IN +.sym 29690 spi_if_ins.w_rx_data[4] +.sym 29702 spi_if_ins.w_rx_data[2] +.sym 29710 spi_if_ins.w_rx_data[3] +.sym 29718 spi_if_ins.w_rx_data[4] +.sym 29726 spi_if_ins.w_rx_data[0] +.sym 29730 smi_ctrl_ins.d_q2[5] +.sym 29734 smi_ctrl_ins.d_q1[5] +.sym 29738 smi_ctrl_ins.d_q1[3] +.sym 29742 w_smi_data_input[0] +.sym 29746 smi_ctrl_ins.d_q1[7] +.sym 29750 w_smi_data_input[3] +.sym 29754 w_smi_data_input[5] +.sym 29758 smi_ctrl_ins.d_q2[7] +.sym 29766 smi_ctrl_ins.r_fifo_pull +.sym 29771 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29772 smi_ctrl_ins.byte_ix[3] +.sym 29773 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[2] +.sym 29774 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.sym 29775 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.sym 29776 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 29777 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.sym 29778 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 29779 smi_ctrl_ins.byte_ix[1] +.sym 29780 smi_ctrl_ins.byte_ix[3] +.sym 29781 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29782 smi_ctrl_ins.w_fifo_pull_trigger +.sym 29786 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 29787 smi_ctrl_ins.byte_ix[2] +.sym 29788 smi_ctrl_ins.byte_ix[1] +.sym 29789 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29790 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] +.sym 29791 smi_ctrl_ins.byte_ix[0] +.sym 29792 smi_ctrl_ins.byte_ix[2] +.sym 29793 smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +.sym 29794 w_rx_fifo_pulled_data[1] +.sym 29798 w_rx_fifo_pulled_data[26] +.sym 29802 w_rx_fifo_pulled_data[11] +.sym 29806 w_rx_fifo_pulled_data[21] +.sym 29810 w_rx_fifo_pulled_data[2] +.sym 29814 w_rx_fifo_pulled_data[8] +.sym 29818 w_rx_fifo_pulled_data[18] +.sym 29822 w_rx_fifo_pulled_data[20] +.sym 29826 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 29827 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 29828 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 29829 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 29830 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] +.sym 29831 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] +.sym 29832 smi_ctrl_ins.int_cnt_rx[4] +.sym 29833 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[3] +.sym 29834 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[0] +.sym 29835 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] +.sym 29836 smi_ctrl_ins.int_cnt_rx[4] +.sym 29837 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[3] +.sym 29838 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 29839 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 29840 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 29841 rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 29845 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 29849 smi_ctrl_ins.int_cnt_rx[3] +.sym 29850 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] +.sym 29851 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[1] +.sym 29852 smi_ctrl_ins.int_cnt_rx[4] +.sym 29853 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[3] +.sym 29856 smi_ctrl_ins.int_cnt_rx[4] +.sym 29857 smi_ctrl_ins.int_cnt_rx[3] +.sym 29858 smi_ctrl_ins.d_byte[2] +.sym 29863 w_rx_09_fifo_data[1] +.sym 29864 w_rx_24_fifo_data[1] +.sym 29865 channel +.sym 29866 smi_ctrl_ins.r_fifo_pulled_data[22] +.sym 29867 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 29868 smi_ctrl_ins.int_cnt_rx[4] +.sym 29869 smi_ctrl_ins.int_cnt_rx[3] +.sym 29870 smi_ctrl_ins.r_fifo_pulled_data[17] +.sym 29871 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 29872 smi_ctrl_ins.int_cnt_rx[4] +.sym 29873 smi_ctrl_ins.int_cnt_rx[3] +.sym 29874 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 29875 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 29876 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 29877 rx_fifo.rd_addr_gray_wr_r[7] +.sym 29878 smi_ctrl_ins.d_byte[1] +.sym 29883 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 29884 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 29885 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 29887 w_rx_09_fifo_data[9] +.sym 29888 w_rx_24_fifo_data[9] +.sym 29889 channel +.sym 29891 w_rx_09_fifo_data[3] +.sym 29892 w_rx_24_fifo_data[3] +.sym 29893 channel +.sym 29895 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +.sym 29896 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 29897 lvds_tx_inst.frame_boundary +.sym 29903 w_rx_09_fifo_data[25] +.sym 29904 w_rx_24_fifo_data[25] +.sym 29905 channel +.sym 29906 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] +.sym 29907 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[1] +.sym 29908 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] +.sym 29909 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] +.sym 29910 smi_ctrl_ins.r_fifo_pulled_data[18] +.sym 29911 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 29912 smi_ctrl_ins.int_cnt_rx[4] +.sym 29913 smi_ctrl_ins.int_cnt_rx[3] +.sym 29915 w_rx_09_fifo_data[13] +.sym 29916 w_rx_24_fifo_data[13] +.sym 29917 channel +.sym 29918 lvds_tx_inst.r_fifo_data[14] +.sym 29919 w_tx_fifo_pulled_data[14] +.sym 29920 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 29921 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 29924 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29925 w_rx_09_fifo_data[14] +.sym 29928 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29929 w_rx_09_fifo_data[23] +.sym 29932 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29933 w_rx_09_fifo_data[17] +.sym 29936 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29937 w_rx_09_fifo_data[27] +.sym 29940 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29941 w_rx_09_fifo_data[25] +.sym 29944 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29945 w_rx_09_fifo_data[0] +.sym 29948 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29949 w_rx_09_fifo_data[12] +.sym 29952 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29953 w_rx_09_fifo_data[16] +.sym 29956 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29957 w_rx_09_fifo_data[10] +.sym 29960 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29961 w_rx_09_fifo_data[20] +.sym 29964 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29965 w_rx_09_fifo_data[29] +.sym 29968 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29969 w_rx_09_fifo_data[3] +.sym 29973 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29976 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29977 w_rx_09_fifo_data[22] +.sym 29980 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 29981 w_rx_09_fifo_data[5] +.sym 29985 w_rx_09_fifo_data[13] +.sym 29986 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 29990 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 29994 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 29998 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 30006 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 30011 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 30012 w_lvds_rx_24_d0 +.sym 30013 w_lvds_rx_24_d1 +.sym 30016 tx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 30017 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 30018 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 30019 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 30020 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30021 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 30024 i_ss$SB_IO_IN +.sym 30025 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 30026 spi_if_ins.spi.r_rx_byte[3] +.sym 30033 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 30034 tx_fifo.rd_addr_gray_wr_r[1] +.sym 30035 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.sym 30036 tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 30037 tx_fifo.rd_addr_gray_wr_r[2] +.sym 30043 w_rx_09_fifo_data[4] +.sym 30044 w_rx_24_fifo_data[4] +.sym 30045 channel +.sym 30047 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 30048 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 30049 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30052 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30053 w_rx_09_fifo_data[24] +.sym 30056 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30057 w_rx_09_fifo_data[8] +.sym 30060 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 30061 tx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 30064 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 30065 tx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 30066 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 30067 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 30068 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30069 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 30072 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30073 w_rx_09_fifo_data[26] +.sym 30080 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 30081 w_ioc[2] +.sym 30083 lvds_rx_09_inst.r_phase_count[0] +.sym 30087 lvds_rx_09_inst.r_phase_count[1] +.sym 30088 $PACKER_VCC_NET +.sym 30089 lvds_rx_09_inst.r_phase_count[0] +.sym 30090 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 30092 $PACKER_VCC_NET +.sym 30093 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 30096 tx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 30097 tx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 30098 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 30102 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 30103 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 30104 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 30105 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 30110 i_mosi$SB_IO_IN +.sym 30116 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30117 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 30120 tx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 30121 tx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 30124 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30125 w_rx_sync_type_24 +.sym 30128 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30129 sys_ctrl_ins.tx_sample_gap[3] +.sym 30132 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30133 w_rx_sync_type_09 +.sym 30136 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30137 sys_ctrl_ins.tx_sample_gap[1] +.sym 30144 sys_ctrl_ins.tx_sample_gap[0] +.sym 30145 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30146 w_rx_data[4] +.sym 30150 w_rx_data[5] +.sym 30155 i_rst_b$SB_IO_IN +.sym 30156 w_cs[1] +.sym 30157 w_fetch +.sym 30160 tx_fifo.rd_addr_gray_wr_r[1] +.sym 30161 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 30163 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 30164 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 30165 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 30170 w_rx_data[0] +.sym 30175 tx_fifo.rd_addr_gray_wr_r[4] +.sym 30176 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 30177 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] +.sym 30179 w_ioc[4] +.sym 30180 w_ioc[3] +.sym 30181 w_ioc[2] +.sym 30182 w_ioc[0] +.sym 30183 w_ioc[4] +.sym 30184 w_ioc[3] +.sym 30185 w_ioc[1] +.sym 30186 spi_if_ins.w_rx_data[1] +.sym 30194 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 30200 tx_fifo.rd_addr_gray_wr_r[8] +.sym 30201 tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 30202 spi_if_ins.w_rx_data[0] +.sym 30207 w_ioc[2] +.sym 30208 w_ioc[4] +.sym 30209 w_ioc[3] +.sym 30211 spi_if_ins.spi.r_rx_bit_count[0] +.sym 30216 spi_if_ins.spi.r_rx_bit_count[1] +.sym 30220 spi_if_ins.spi.r_rx_bit_count[2] +.sym 30221 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 30225 spi_if_ins.spi.r_rx_bit_count[0] +.sym 30232 spi_if_ins.spi.r_rx_bit_count[1] +.sym 30233 spi_if_ins.spi.r_rx_bit_count[0] +.sym 30234 i_ss$SB_IO_IN +.sym 30235 spi_if_ins.spi.r_rx_bit_count[0] +.sym 30236 spi_if_ins.spi.r_rx_bit_count[2] +.sym 30237 spi_if_ins.spi.r_rx_bit_count[1] +.sym 30246 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 30247 lvds_tx_inst.r_sync_count[1] +.sym 30248 $PACKER_VCC_NET +.sym 30249 lvds_tx_inst.r_sync_count[0] +.sym 30253 w_smi_data_direction +.sym 30274 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] +.sym 30275 rx_fifo.rd_addr[9] +.sym 30276 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 30277 rx_fifo.rd_addr[8] +.sym 30278 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 30279 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 30280 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 30281 w_rx_fifo_pull +.sym 30283 smi_ctrl_ins.r_fifo_pull_1 +.sym 30284 w_smi_read_req +.sym 30285 smi_ctrl_ins.r_fifo_pull +.sym 30287 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 30288 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 30289 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 30290 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 30291 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 30292 smi_ctrl_ins.int_cnt_rx[4] +.sym 30293 smi_ctrl_ins.int_cnt_rx[3] +.sym 30294 w_rx_data[0] +.sym 30299 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 30300 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 30301 rx_fifo.wr_addr_gray_rd_r[2] +.sym 30303 w_smi_read_req +.sym 30304 w_smi_read_req_SB_LUT4_I1_I2[1] +.sym 30305 w_smi_read_req_SB_LUT4_I1_I2[2] +.sym 30306 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[0] +.sym 30307 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[1] +.sym 30308 smi_ctrl_ins.int_cnt_rx[4] +.sym 30309 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[3] +.sym 30310 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[0] +.sym 30311 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[1] +.sym 30312 smi_ctrl_ins.int_cnt_rx[4] +.sym 30313 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[3] +.sym 30314 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +.sym 30315 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[1] +.sym 30316 smi_ctrl_ins.int_cnt_rx[4] +.sym 30317 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[3] +.sym 30318 smi_ctrl_ins.r_fifo_pulled_data[16] +.sym 30319 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 30320 smi_ctrl_ins.int_cnt_rx[4] +.sym 30321 smi_ctrl_ins.int_cnt_rx[3] +.sym 30322 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[0] +.sym 30323 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] +.sym 30324 smi_ctrl_ins.int_cnt_rx[4] +.sym 30325 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] +.sym 30326 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] +.sym 30327 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[1] +.sym 30328 smi_ctrl_ins.int_cnt_rx[4] +.sym 30329 smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[3] +.sym 30332 w_tx_fsm_state[0] +.sym 30333 w_tx_fsm_state[1] .sym 30336 smi_ctrl_ins.int_cnt_rx[4] .sym 30337 smi_ctrl_ins.int_cnt_rx[3] -.sym 30338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30339 tx_fifo.rd_addr_gray_wr_r[1] -.sym 30340 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30341 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30342 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 30343 smi_ctrl_ins.r_fifo_pulled_data[19] +.sym 30338 w_rx_fifo_pulled_data[14] .sym 30344 smi_ctrl_ins.int_cnt_rx[4] .sym 30345 smi_ctrl_ins.int_cnt_rx[3] -.sym 30348 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 30349 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 30351 tx_fifo.rd_addr[6] -.sym 30352 tx_fifo.rd_addr[5] -.sym 30353 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 30360 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 30361 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30370 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30377 tx_fifo.wr_addr[1] -.sym 30380 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 30381 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30382 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] -.sym 30386 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30400 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 30401 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 30402 tx_fifo.wr_addr_gray[0] -.sym 30410 tx_fifo.wr_addr_gray[5] -.sym 30422 tx_fifo.wr_addr_gray_rd[5] -.sym 30426 tx_fifo.wr_addr_gray[7] -.sym 30430 tx_fifo.wr_addr_gray[2] -.sym 30445 tx_fifo.rd_addr[1] -.sym 30467 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30471 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30472 $PACKER_VCC_NET -.sym 30475 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 30476 $PACKER_VCC_NET -.sym 30477 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 -.sym 30479 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30480 $PACKER_VCC_NET -.sym 30481 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30485 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30487 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 30488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30489 spi_if_ins.spi.r_tx_bit_count[0] -.sym 30496 i_ss$SB_IO_IN -.sym 30497 spi_if_ins.r_tx_data_valid -.sym 30501 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30505 w_smi_read_req -.sym 30512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30513 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30514 i_rst_b$SB_IO_IN -.sym 30515 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30516 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] -.sym 30517 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 30522 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 30527 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 30528 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30531 i_rst_b$SB_IO_IN -.sym 30532 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] -.sym 30533 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] -.sym 30534 spi_if_ins.w_rx_data[2] -.sym 30538 i_rst_b$SB_IO_IN -.sym 30539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30540 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30541 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30543 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 30551 i_rst_b$SB_IO_IN -.sym 30552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30554 spi_if_ins.w_rx_data[6] -.sym 30558 i_rst_b$SB_IO_IN -.sym 30559 w_cs[2] -.sym 30560 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 30561 w_fetch -.sym 30562 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 30563 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 30564 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 30565 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 30566 w_load -.sym 30567 w_fetch -.sym 30568 w_cs[0] -.sym 30569 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 30570 sys_ctrl_ins.i_cs_SB_DFFE_Q_D -.sym 30583 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 30584 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 30585 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] -.sym 30588 i_rst_b$SB_IO_IN -.sym 30589 spi_if_ins.o_cs_SB_LUT4_I0_O[1] -.sym 30591 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 30592 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 30593 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] -.sym 30595 o_rx_h_tx_l$SB_IO_OUT -.sym 30596 i_button_SB_LUT4_I0_O[1] -.sym 30597 i_button_SB_LUT4_I0_O[2] -.sym 30600 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 30601 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 30602 w_cs[3] -.sym 30603 w_cs[2] -.sym 30604 w_cs[1] -.sym 30605 w_cs[0] -.sym 30606 w_cs[2] -.sym 30607 w_load -.sym 30608 w_fetch -.sym 30609 i_button_SB_LUT4_I0_I3[2] -.sym 30611 i_rst_b$SB_IO_IN -.sym 30612 w_cs[1] -.sym 30613 w_fetch -.sym 30618 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 30619 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 30620 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 30621 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 30623 w_tx_data_io[5] -.sym 30624 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 30625 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30627 w_tx_data_io[7] -.sym 30628 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 30629 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30631 o_tr_vc1$SB_IO_OUT -.sym 30632 i_button_SB_LUT4_I0_O[1] -.sym 30633 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] -.sym 30634 i_button_SB_LUT4_I0_I3[0] -.sym 30635 i_button_SB_LUT4_I0_I3[1] -.sym 30636 i_button_SB_LUT4_I0_I3[2] -.sym 30637 i_button_SB_LUT4_I0_I3[3] -.sym 30643 w_fetch -.sym 30644 w_cs[0] -.sym 30645 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] -.sym 30646 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 30647 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 30648 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 30649 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 30650 w_tx_data_io[2] -.sym 30651 w_tx_data_smi[2] -.sym 30652 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 30653 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 30655 o_rx_h_tx_l_b$SB_IO_OUT -.sym 30656 i_button_SB_LUT4_I0_O[1] -.sym 30657 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] -.sym 30658 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] -.sym 30659 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 30660 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30661 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] -.sym 30679 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] -.sym 30680 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30681 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] -.sym 30687 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] -.sym 30688 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 30689 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] -.sym 30690 r_tx_data[2] -.sym 30705 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30706 r_tx_data[0] -.sym 30718 r_tx_data[7] -.sym 30728 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] -.sym 30729 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30732 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 30733 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30736 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] -.sym 30737 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30740 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] -.sym 30741 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30744 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] -.sym 30745 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30748 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] -.sym 30749 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 30755 tx_fifo.wr_addr[0] -.sym 30760 tx_fifo.wr_addr[1] -.sym 30761 tx_fifo.wr_addr[0] -.sym 30764 tx_fifo.wr_addr[2] -.sym 30765 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 -.sym 30768 tx_fifo.wr_addr[3] -.sym 30769 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 -.sym 30772 tx_fifo.wr_addr[4] -.sym 30773 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 -.sym 30776 tx_fifo.wr_addr[5] -.sym 30777 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 30780 tx_fifo.wr_addr[6] -.sym 30781 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 30784 tx_fifo.wr_addr[7] -.sym 30785 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 -.sym 30788 tx_fifo.wr_addr[8] -.sym 30789 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO -.sym 30792 tx_fifo.wr_addr[9] -.sym 30793 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO -.sym 30794 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30798 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 30802 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30806 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] -.sym 30810 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 30814 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 30818 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 30820 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 30821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] -.sym 30822 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] -.sym 30823 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] -.sym 30824 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] -.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] -.sym 30826 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30827 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] -.sym 30828 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] -.sym 30829 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] -.sym 30831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30832 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 30833 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 30834 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30835 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] -.sym 30836 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 30837 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] -.sym 30840 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] -.sym 30841 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] -.sym 30844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] -.sym 30845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] -.sym 30847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 30849 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 30850 tx_fifo.rd_addr_gray_wr[7] -.sym 30854 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] -.sym 30858 tx_fifo.rd_addr_gray_wr[2] -.sym 30862 tx_fifo.rd_addr_gray[7] -.sym 30866 tx_fifo.rd_addr_gray[4] -.sym 30870 tx_fifo.rd_addr_gray[1] -.sym 30874 tx_fifo.rd_addr_gray_wr[4] -.sym 30878 tx_fifo.rd_addr_gray_wr[1] -.sym 30882 i_ss$SB_IO_IN -.sym 30883 spi_if_ins.spi.r_rx_bit_count[2] -.sym 30884 spi_if_ins.spi.r_rx_bit_count[1] -.sym 30885 spi_if_ins.spi.r_rx_bit_count[0] -.sym 30890 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 30895 w_tx_fifo_full -.sym 30896 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 30897 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30898 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 30899 tx_fifo.wr_addr[1] -.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 30901 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 30903 tx_fifo.full_o_SB_LUT4_I1_O[0] -.sym 30904 tx_fifo.full_o_SB_LUT4_I1_O[1] -.sym 30905 tx_fifo.full_o_SB_LUT4_I1_O[2] -.sym 30907 spi_if_ins.spi.r_rx_bit_count[2] -.sym 30908 spi_if_ins.spi.r_rx_bit_count[1] -.sym 30909 spi_if_ins.spi.r_rx_bit_count[0] -.sym 30913 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 30914 spi_if_ins.spi.r2_rx_done -.sym 30924 spi_if_ins.spi.r3_rx_done -.sym 30925 spi_if_ins.spi.r2_rx_done -.sym 30932 i_ss$SB_IO_IN -.sym 30933 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 30934 tx_fifo.rd_addr_gray_wr[9] -.sym 30938 tx_fifo.rd_addr_gray_wr[0] -.sym 30942 spi_if_ins.spi.r_rx_done -.sym 30954 tx_fifo.rd_addr_gray[0] -.sym 30961 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 30978 w_tx_fifo_full -.sym 30985 w_smi_read_req -.sym 30986 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] -.sym 30991 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 30992 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] -.sym 30993 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] -.sym 30994 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] -.sym 30995 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] -.sym 30996 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] -.sym 30997 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] -.sym 30999 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] -.sym 31001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.sym 31007 spi_if_ins.spi.r_tx_byte[3] -.sym 31008 spi_if_ins.spi.r_tx_byte[2] -.sym 31009 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31010 spi_if_ins.spi.r_tx_byte[6] -.sym 31011 spi_if_ins.spi.r_tx_byte[4] -.sym 31012 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 31013 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31014 spi_if_ins.r_tx_byte[4] -.sym 31018 spi_if_ins.r_tx_byte[2] -.sym 31022 spi_if_ins.r_tx_byte[3] -.sym 31026 spi_if_ins.r_tx_byte[6] -.sym 31031 spi_if_ins.spi.r_tx_byte[1] -.sym 31032 spi_if_ins.spi.r_tx_byte[0] -.sym 31033 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31034 spi_if_ins.r_tx_byte[1] -.sym 31038 spi_if_ins.r_tx_byte[0] -.sym 31042 spi_if_ins.w_rx_data[2] -.sym 31047 w_ioc[4] -.sym 31048 w_ioc[3] -.sym 31049 w_ioc[2] -.sym 31056 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31057 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 31058 spi_if_ins.w_rx_data[4] -.sym 31064 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31065 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] -.sym 31066 spi_if_ins.w_rx_data[0] -.sym 31070 spi_if_ins.w_rx_data[3] -.sym 31074 w_cs[3] -.sym 31075 w_cs[2] -.sym 31076 w_cs[1] -.sym 31077 w_cs[0] -.sym 31078 r_tx_data[5] -.sym 31082 r_tx_data[4] -.sym 31086 r_tx_data[3] -.sym 31090 r_tx_data[1] -.sym 31099 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 31100 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31101 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31102 r_tx_data[6] -.sym 31107 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] -.sym 31108 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 31109 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] -.sym 31111 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] -.sym 31112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 31113 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] -.sym 31115 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31116 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31117 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 31118 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] -.sym 31119 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] -.sym 31120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 31121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 31122 i_button$SB_IO_IN -.sym 31123 io_ctrl_ins.pmod_dir_state[7] -.sym 31124 i_button_SB_LUT4_I0_I3[2] -.sym 31125 i_button_SB_LUT4_I0_I3[3] -.sym 31126 w_cs[3] -.sym 31127 w_cs[2] -.sym 31128 w_cs[1] -.sym 31129 w_cs[0] -.sym 31130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] -.sym 31131 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] -.sym 31132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 31133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 31134 w_cs[3] -.sym 31135 w_cs[2] -.sym 31136 w_cs[1] -.sym 31137 w_cs[0] -.sym 31139 w_tx_data_io[0] -.sym 31140 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] -.sym 31141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 31142 o_led0_SB_LUT4_I1_O[0] -.sym 31143 o_led0_SB_LUT4_I1_O[1] -.sym 31144 o_led0_SB_LUT4_I1_O[2] -.sym 31145 o_led0_SB_LUT4_I1_O[3] -.sym 31146 io_pmod_out[1]$SB_IO_OUT -.sym 31147 o_shdn_rx_lna$SB_IO_OUT -.sym 31148 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31149 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 31150 w_tx_data_smi[1] -.sym 31151 w_tx_data_io[1] -.sym 31152 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 31153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 31154 io_pmod_out[0]$SB_IO_OUT -.sym 31155 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31156 io_ctrl_ins.mixer_en_state -.sym 31157 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 31158 o_led1_SB_LUT4_I1_O[0] -.sym 31159 o_led0_SB_LUT4_I1_O[1] -.sym 31160 o_led1_SB_LUT4_I1_O[2] -.sym 31161 o_led1_SB_LUT4_I1_O[3] -.sym 31163 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] -.sym 31164 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] -.sym 31165 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] -.sym 31167 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 31168 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31169 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 31170 io_ctrl_ins.rf_pin_state[3] -.sym 31171 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31172 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31173 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31174 io_ctrl_ins.rf_pin_state[2] -.sym 31175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31176 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31179 io_ctrl_ins.rf_pin_state[7] -.sym 31180 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31181 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31182 io_ctrl_ins.rf_pin_state[4] -.sym 31183 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31184 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 31185 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31187 io_ctrl_ins.rf_pin_state[6] -.sym 31188 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31189 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31191 io_ctrl_ins.rf_pin_state[1] -.sym 31192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31193 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31194 io_ctrl_ins.rf_pin_state[0] -.sym 31195 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31197 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31198 io_ctrl_ins.rf_pin_state[5] -.sym 31199 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31200 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] -.sym 31201 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31202 w_rx_data[4] -.sym 31206 w_rx_data[2] -.sym 31210 i_rst_b$SB_IO_IN -.sym 31211 o_led0_SB_LUT4_I1_O[0] -.sym 31212 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31213 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31217 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O -.sym 31218 w_rx_data[1] -.sym 31222 w_rx_data[0] -.sym 31228 o_led1_SB_LUT4_I1_O[0] -.sym 31229 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] -.sym 31230 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 31231 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 31232 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31233 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] -.sym 31234 w_rx_data[5] -.sym 31238 w_rx_data[2] -.sym 31242 w_rx_data[0] -.sym 31250 w_rx_data[1] -.sym 31258 w_rx_data[4] -.sym 31262 w_rx_data[6] -.sym 31273 tx_fifo.wr_addr[0] -.sym 31274 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] -.sym 31278 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] -.sym 31294 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31299 tx_fifo.wr_addr[1] -.sym 31304 tx_fifo.wr_addr[2] -.sym 31305 tx_fifo.wr_addr[1] -.sym 31308 tx_fifo.wr_addr[3] -.sym 31309 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31312 tx_fifo.wr_addr[4] -.sym 31313 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31316 tx_fifo.wr_addr[5] -.sym 31317 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31320 tx_fifo.wr_addr[6] -.sym 31321 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31324 tx_fifo.wr_addr[7] -.sym 31325 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI -.sym 31328 tx_fifo.wr_addr[8] -.sym 31329 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI -.sym 31332 tx_fifo.wr_addr[9] -.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 -.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] -.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] -.sym 31337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] -.sym 31339 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31340 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] -.sym 31342 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] -.sym 31343 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31344 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] -.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] -.sym 31347 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.sym 31348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.sym 31349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31351 tx_fifo.rd_addr_gray_wr_r[8] -.sym 31352 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.sym 31353 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.sym 31354 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] -.sym 31360 i_rst_b$SB_IO_IN -.sym 31361 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 31362 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31363 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] -.sym 31364 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] -.sym 31365 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 31366 smi_ctrl_ins.r_fifo_push -.sym 31370 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] -.sym 31371 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] -.sym 31372 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] -.sym 31373 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] -.sym 31375 tx_fifo.wr_addr[2] -.sym 31376 tx_fifo.rd_addr_gray_wr_r[1] -.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] -.sym 31379 w_tx_fifo_full -.sym 31380 smi_ctrl_ins.r_fifo_push -.sym 31381 smi_ctrl_ins.r_fifo_push_1 -.sym 31382 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] -.sym 31383 tx_fifo.rd_addr_gray_wr_r[8] -.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.sym 31385 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] -.sym 31386 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] -.sym 31387 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] -.sym 31388 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] -.sym 31389 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] -.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] -.sym 31393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] -.sym 31395 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31400 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31401 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31404 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31405 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 -.sym 31409 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31423 w_tx_fifo_full -.sym 31424 w_smi_read_req -.sym 31425 w_smi_data_direction -.sym 31426 w_rx_fifo_pulled_data[28] -.sym 31430 w_rx_fifo_pulled_data[17] -.sym 31438 w_rx_fifo_pulled_data[29] -.sym 31442 w_rx_fifo_pulled_data[30] -.sym 31446 w_rx_fifo_pulled_data[19] -.sym 31454 w_rx_fifo_pulled_data[31] -.sym 31458 i_mosi$SB_IO_IN -.sym 31462 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 31466 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 31470 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 31474 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 31478 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 31482 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 31486 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 31490 spi_if_ins.spi.r_rx_byte[2] -.sym 31494 spi_if_ins.spi.r_rx_byte[6] -.sym 31498 spi_if_ins.spi.r_rx_byte[0] -.sym 31502 spi_if_ins.spi.r_rx_byte[4] -.sym 31506 spi_if_ins.spi.r_rx_byte[5] -.sym 31510 spi_if_ins.spi.r_rx_byte[7] -.sym 31514 spi_if_ins.spi.r_rx_byte[1] -.sym 31518 spi_if_ins.spi.r_rx_byte[3] -.sym 31530 spi_if_ins.r_tx_byte[7] -.sym 31537 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 31538 spi_if_ins.r_tx_byte[5] -.sym 31542 spi_if_ins.spi.r_tx_byte[7] -.sym 31543 spi_if_ins.spi.r_tx_byte[5] -.sym 31544 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] -.sym 31545 spi_if_ins.spi.r_tx_bit_count[0] -.sym 31554 spi_if_ins.w_rx_data[1] -.sym 31559 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 31560 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31561 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31562 spi_if_ins.w_rx_data[4] -.sym 31566 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] -.sym 31572 spi_if_ins.w_rx_data[6] -.sym 31573 spi_if_ins.w_rx_data[5] -.sym 31574 spi_if_ins.w_rx_data[3] -.sym 31578 spi_if_ins.w_rx_data[0] -.sym 31582 spi_if_ins.w_rx_data[5] -.sym 31587 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31588 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31589 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 31592 spi_if_ins.w_rx_data[6] -.sym 31593 spi_if_ins.w_rx_data[5] -.sym 31598 w_cs[3] -.sym 31599 w_cs[2] -.sym 31600 w_cs[1] -.sym 31601 w_cs[0] -.sym 31604 spi_if_ins.w_rx_data[6] -.sym 31605 spi_if_ins.w_rx_data[5] -.sym 31607 w_ioc[4] -.sym 31608 w_ioc[3] -.sym 31609 w_ioc[2] -.sym 31612 spi_if_ins.w_rx_data[6] -.sym 31613 spi_if_ins.w_rx_data[5] -.sym 31615 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 31616 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31617 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31618 io_ctrl_ins.pmod_dir_state[1] -.sym 31619 o_led1$SB_IO_OUT -.sym 31620 i_button_SB_LUT4_I0_I3[2] -.sym 31621 o_led1_SB_LUT4_I1_I3[3] -.sym 31622 w_rx_data[0] -.sym 31626 w_rx_data[2] -.sym 31630 io_ctrl_ins.pmod_dir_state[3] -.sym 31631 i_button_SB_LUT4_I0_I3[2] -.sym 31632 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 31633 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 30346 w_rx_fifo_pulled_data[0] +.sym 30350 w_rx_fifo_pulled_data[13] +.sym 30354 w_rx_fifo_pulled_data[16] +.sym 30358 w_rx_fifo_pulled_data[24] +.sym 30362 w_rx_fifo_pulled_data[22] +.sym 30366 smi_ctrl_ins.r_fifo_pulled_data[21] +.sym 30367 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 30368 smi_ctrl_ins.int_cnt_rx[4] +.sym 30369 smi_ctrl_ins.int_cnt_rx[3] +.sym 30370 w_rx_fifo_pulled_data[29] +.sym 30375 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 30376 rx_fifo.rd_addr_gray_wr_r[2] +.sym 30377 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30378 w_rx_fifo_pulled_data[15] +.sym 30382 w_rx_fifo_pulled_data[23] +.sym 30386 w_rx_fifo_pulled_data[17] +.sym 30390 w_rx_fifo_pulled_data[27] +.sym 30394 w_rx_fifo_pulled_data[3] +.sym 30399 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 30400 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 30401 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 30403 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 30404 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 30405 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 30408 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 30409 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 30411 rx_fifo.rd_addr_gray_wr_r[5] +.sym 30412 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 30413 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 30415 rx_fifo.wr_addr[0] +.sym 30416 rx_fifo.rd_addr_gray_wr_r[0] +.sym 30417 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 30420 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 30421 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 30422 w_rx_fifo_pulled_data[12] +.sym 30427 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 30428 rx_fifo.rd_addr_gray_wr_r[9] +.sym 30429 w_rx_fifo_full +.sym 30433 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 30435 w_rx_09_fifo_data[14] +.sym 30436 w_rx_24_fifo_data[14] +.sym 30437 channel +.sym 30438 lvds_tx_inst.r_fifo_data[22] +.sym 30439 w_tx_fifo_pulled_data[22] +.sym 30440 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 30441 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 30442 w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.sym 30443 w_tx_fifo_pulled_data[21] +.sym 30444 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 30445 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 30446 tx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 30447 tx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 30448 tx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 30449 tx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 30450 lvds_tx_inst.r_fifo_data[24] +.sym 30451 w_tx_fifo_pulled_data[24] +.sym 30452 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 30453 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 30454 lvds_tx_inst.r_fifo_data[23] +.sym 30455 w_tx_fifo_pulled_data[23] +.sym 30456 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] +.sym 30457 lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] +.sym 30458 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 30459 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[1] +.sym 30460 w_tx_fsm_state[0] +.sym 30461 w_tx_fsm_state[1] +.sym 30463 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 30464 lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] +.sym 30465 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[2] +.sym 30468 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30469 w_rx_09_fifo_data[7] +.sym 30470 tx_fifo.rd_addr_gray_wr_r[6] +.sym 30471 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 30472 tx_fifo.rd_addr_gray_wr_r[8] +.sym 30473 tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 30476 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30477 w_rx_09_fifo_data[6] +.sym 30478 lvds_tx_inst.fifo_empty_d2 +.sym 30479 lvds_tx_inst.r_tx_state +.sym 30480 lvds_tx_inst.sent_first_sync +.sym 30481 lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] +.sym 30483 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30484 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 30485 i_rst_b$SB_IO_IN +.sym 30488 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30489 w_rx_09_fifo_data[13] +.sym 30492 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30493 w_rx_09_fifo_data[2] +.sym 30496 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30497 w_rx_09_fifo_data[19] +.sym 30507 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 30508 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30509 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 30515 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 30516 w_lvds_rx_24_d1_SB_LUT4_I2_O[2] +.sym 30517 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30520 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30521 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 30541 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O +.sym 30547 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 +.sym 30548 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] +.sym 30549 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 30551 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30552 w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.sym 30553 i_rst_b$SB_IO_IN +.sym 30554 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 30555 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] +.sym 30556 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 30557 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30564 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30565 w_tx_sync_type_09 +.sym 30572 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 30573 w_tx_sync_type_24 +.sym 30577 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 30578 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 30579 tx_fifo.rd_addr_gray_wr_r[7] +.sym 30580 tx_fifo.rd_addr_gray_wr_r[4] +.sym 30581 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 30582 io_ctrl_ins.pmod_state[0] +.sym 30583 io_ctrl_ins.mixer_en_state +.sym 30584 w_ioc[0] +.sym 30585 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 30592 w_cs[2] +.sym 30593 w_fetch +.sym 30594 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 30595 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 30596 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] +.sym 30597 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30598 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 30599 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 30600 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] +.sym 30601 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30602 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 30603 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 30604 w_cs[0] +.sym 30605 w_fetch +.sym 30606 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 30607 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] +.sym 30608 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] +.sym 30609 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 30612 spi_if_ins.w_rx_data[6] +.sym 30613 spi_if_ins.w_rx_data[5] +.sym 30615 i_button_SB_LUT4_I2_I1[0] +.sym 30616 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 30617 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 30624 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 30625 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 30629 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 30630 w_rx_data[7] +.sym 30634 w_rx_data[3] +.sym 30642 w_rx_data[6] +.sym 30646 w_rx_data[1] +.sym 30651 i_button_SB_LUT4_I2_I1[1] +.sym 30652 i_button_SB_LUT4_I2_I1[0] +.sym 30653 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 30654 w_rx_data[2] +.sym 30658 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.sym 30659 w_ioc[0] +.sym 30660 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] +.sym 30661 w_ioc[1] +.sym 30662 w_cs[1] +.sym 30663 w_cs[3] +.sym 30664 w_cs[0] +.sym 30665 w_cs[2] +.sym 30669 w_cs[1] +.sym 30670 spi_if_ins.w_rx_data[6] +.sym 30674 w_cs[2] +.sym 30675 w_cs[3] +.sym 30676 w_cs[0] +.sym 30677 w_cs[1] +.sym 30678 w_fetch +.sym 30679 w_cs[2] +.sym 30680 i_button_SB_LUT4_I2_I1[0] +.sym 30681 w_load +.sym 30682 spi_if_ins.w_rx_data[5] +.sym 30686 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 30694 i_sck$SB_IO_IN +.sym 30707 spi_if_ins.spi.r_rx_bit_count[1] +.sym 30708 spi_if_ins.spi.r_rx_bit_count[0] +.sym 30709 spi_if_ins.spi.r_rx_bit_count[2] +.sym 30710 w_ioc[1] +.sym 30711 w_ioc[4] +.sym 30712 w_ioc[3] +.sym 30713 w_ioc[2] +.sym 30718 spi_if_ins.spi.SCKr[0] +.sym 30725 r_counter +.sym 30754 w_smi_data_input[7] +.sym 30758 rx_fifo.wr_addr_gray_rd[6] +.sym 30762 rx_fifo.wr_addr_gray[4] +.sym 30767 rx_fifo.wr_addr_gray_rd_r[2] +.sym 30768 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 30769 rx_fifo.rd_addr[3] +.sym 30770 rx_fifo.wr_addr[9] +.sym 30774 rx_fifo.wr_addr_gray_rd[9] +.sym 30778 rx_fifo.wr_addr_gray[6] +.sym 30782 rx_fifo.wr_addr_gray_rd[2] +.sym 30787 rx_fifo.rd_addr[0] +.sym 30792 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 30793 rx_fifo.rd_addr[0] +.sym 30796 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 30797 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 30800 rx_fifo.rd_addr[3] +.sym 30801 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 30804 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 30805 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 30808 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 30809 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 30812 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 30813 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 30816 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 30817 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 30820 rx_fifo.rd_addr[8] +.sym 30821 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 30824 rx_fifo.rd_addr[9] +.sym 30825 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 30828 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30829 w_rx_24_fifo_data[10] +.sym 30832 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30833 w_rx_24_fifo_data[6] +.sym 30836 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30837 w_rx_24_fifo_data[22] +.sym 30840 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30841 w_rx_24_fifo_data[8] +.sym 30845 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.sym 30848 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 30849 w_rx_24_fifo_data[20] +.sym 30852 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 30853 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 30854 smi_ctrl_ins.r_fifo_pulled_data[23] +.sym 30855 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 30856 smi_ctrl_ins.int_cnt_rx[4] +.sym 30857 smi_ctrl_ins.int_cnt_rx[3] +.sym 30862 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 30868 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 30869 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 30872 w_rx_fifo_push +.sym 30873 i_rst_b$SB_IO_IN +.sym 30875 w_rx_09_fifo_data[26] +.sym 30876 w_rx_24_fifo_data[26] +.sym 30877 channel +.sym 30879 w_tx_fifo_full +.sym 30880 w_smi_read_req +.sym 30881 w_smi_data_direction +.sym 30883 rx_fifo.wr_addr[0] +.sym 30888 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 30889 rx_fifo.wr_addr[0] +.sym 30892 rx_fifo.wr_addr[2] +.sym 30893 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 30896 rx_fifo.wr_addr[3] +.sym 30897 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 30900 rx_fifo.wr_addr[4] +.sym 30901 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 30904 rx_fifo.wr_addr[5] +.sym 30905 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 30908 rx_fifo.wr_addr[6] +.sym 30909 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 30912 rx_fifo.wr_addr[7] +.sym 30913 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 30916 rx_fifo.wr_addr[8] +.sym 30917 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 30920 rx_fifo.wr_addr[9] +.sym 30921 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 30924 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 30925 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 30931 w_ioc[0] +.sym 30932 w_smi_read_req +.sym 30933 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 30935 w_rx_09_fifo_data[24] +.sym 30936 w_rx_24_fifo_data[24] +.sym 30937 channel +.sym 30939 w_rx_09_fifo_data[2] +.sym 30940 w_rx_24_fifo_data[2] +.sym 30941 channel +.sym 30944 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 30945 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 30946 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 30947 rx_fifo.rd_addr_gray_wr_r[9] +.sym 30948 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8] +.sym 30949 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 30950 rx_fifo.rd_addr_gray_wr[6] +.sym 30954 rx_fifo.rd_addr_gray[6] +.sym 30958 rx_fifo.rd_addr_gray[3] +.sym 30963 lvds_tx_inst.r_tx_state_q +.sym 30964 lvds_tx_inst.r_tx_state +.sym 30965 lvds_tx_inst.sent_first_sync +.sym 30971 w_rx_09_fifo_data[12] +.sym 30972 w_rx_24_fifo_data[12] +.sym 30973 channel +.sym 30974 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] +.sym 30975 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] +.sym 30976 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] +.sym 30977 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 30982 rx_fifo.rd_addr_gray_wr[9] +.sym 30986 rx_fifo.rd_addr_gray[2] +.sym 30991 w_rx_09_fifo_data[18] +.sym 30992 w_rx_24_fifo_data[18] +.sym 30993 channel +.sym 30994 rx_fifo.rd_addr_gray_wr[8] +.sym 30998 rx_fifo.rd_addr_gray_wr[3] +.sym 31002 rx_fifo.rd_addr[9] +.sym 31006 rx_fifo.rd_addr_gray_wr[2] +.sym 31016 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31017 w_lvds_rx_24_d1_SB_LUT4_I2_O[0] +.sym 31023 io_pmod_in[2]$SB_IO_IN +.sym 31024 w_rx_sync_24 +.sym 31025 w_rx_sync_type_24 +.sym 31035 w_rx_09_fifo_data[16] +.sym 31036 w_rx_24_fifo_data[16] +.sym 31037 channel +.sym 31042 r_tx_data[5] +.sym 31046 r_tx_data[4] +.sym 31050 r_tx_data[0] +.sym 31054 r_tx_data[1] +.sym 31058 r_tx_data[6] +.sym 31062 r_tx_data[7] +.sym 31066 r_tx_data[3] +.sym 31070 r_tx_data[2] +.sym 31076 spi_if_ins.o_cs_SB_LUT4_I2_1_O[0] +.sym 31077 i_rst_b$SB_IO_IN +.sym 31080 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 31081 w_rx_09_fifo_data[28] +.sym 31082 w_tx_data_smi[4] +.sym 31083 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 31084 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31085 w_tx_data_io[4] +.sym 31086 w_tx_data_smi[2] +.sym 31087 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 31088 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31089 w_tx_data_io[2] +.sym 31090 w_tx_data_smi[1] +.sym 31091 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 31092 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31093 w_tx_data_io[1] +.sym 31095 w_tx_data_io[5] +.sym 31096 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31097 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 31102 w_cs[2] +.sym 31103 w_cs[1] +.sym 31104 w_cs[3] +.sym 31105 w_cs[0] +.sym 31110 w_cs[2] +.sym 31111 w_cs[1] +.sym 31112 w_cs[0] +.sym 31113 w_cs[3] +.sym 31115 i_button_SB_LUT4_I2_I1[0] +.sym 31116 i_button_SB_LUT4_I2_I1[1] +.sym 31117 i_button_SB_LUT4_I2_I1[2] +.sym 31119 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 31120 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 31121 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 31122 w_cs[2] +.sym 31123 w_cs[1] +.sym 31124 w_cs[3] +.sym 31125 w_cs[0] +.sym 31129 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 31132 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] +.sym 31133 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] +.sym 31136 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 31137 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 31148 spi_if_ins.w_rx_data[5] +.sym 31149 spi_if_ins.w_rx_data[6] +.sym 31156 spi_if_ins.w_rx_data[6] +.sym 31157 spi_if_ins.w_rx_data[5] +.sym 31160 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 31161 w_ioc[0] +.sym 31163 w_tx_data_io[0] +.sym 31164 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31165 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 31168 spi_if_ins.w_rx_data[6] +.sym 31169 spi_if_ins.w_rx_data[5] +.sym 31172 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 31173 w_ioc[0] +.sym 31175 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 31176 io_ctrl_ins.debug_mode[1] +.sym 31177 i_rst_b$SB_IO_IN +.sym 31178 i_button_SB_LUT4_I2_I1[0] +.sym 31179 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 31180 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 31181 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 31182 io_ctrl_ins.pmod_state[3] +.sym 31183 o_tr_vc2$SB_IO_OUT +.sym 31184 w_ioc[0] +.sym 31185 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 31190 o_tr_vc1_b$SB_IO_OUT +.sym 31191 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31192 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 31193 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 31194 w_fetch +.sym 31195 w_cs[1] +.sym 31196 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 31197 w_load +.sym 31199 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31200 i_button_SB_LUT4_I2_I1[2] +.sym 31201 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31202 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 31203 i_button_SB_LUT4_I2_I1[2] +.sym 31204 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31205 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31206 w_rx_data[3] +.sym 31210 w_rx_data[1] +.sym 31216 io_ctrl_ins.debug_mode[0] +.sym 31217 io_ctrl_ins.debug_mode[1] +.sym 31218 w_rx_data[0] +.sym 31222 w_rx_data[4] +.sym 31226 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31227 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 31228 i_button_SB_LUT4_I2_I1[2] +.sym 31229 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31230 w_rx_data[2] +.sym 31234 io_ctrl_ins.pmod_state[1] +.sym 31235 o_shdn_rx_lna$SB_IO_OUT +.sym 31236 w_ioc[0] +.sym 31237 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 31241 r_counter +.sym 31242 io_ctrl_ins.pmod_state[2] +.sym 31243 o_shdn_tx_lna$SB_IO_OUT +.sym 31244 w_ioc[0] +.sym 31245 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 31246 w_rx_data[3] +.sym 31251 w_ioc[0] +.sym 31252 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 31253 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] +.sym 31254 w_rx_data[1] +.sym 31258 w_rx_data[0] +.sym 31262 w_rx_data[2] +.sym 31266 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 31267 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 31268 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 31269 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 31270 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 31274 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 31280 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 31281 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 31282 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 31286 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 31290 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 31296 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 31297 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 31299 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[0] +.sym 31300 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[1] +.sym 31301 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[2] +.sym 31304 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 31305 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 31306 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 31310 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 31317 rx_fifo.rd_addr[0] +.sym 31318 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 31323 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 31324 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 31325 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 31328 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 31329 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 31330 rx_fifo.rd_addr_gray[7] +.sym 31338 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 31339 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 31340 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 31341 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 31344 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 31345 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 31346 rx_fifo.rd_addr_gray_wr[4] +.sym 31350 rx_fifo.rd_addr_gray[5] +.sym 31355 rx_fifo.wr_addr_gray_rd_r[7] +.sym 31356 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 31357 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 31359 rx_fifo.wr_addr_gray_rd_r[2] +.sym 31360 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 31361 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] +.sym 31368 rx_fifo.wr_addr[0] +.sym 31369 rx_fifo.rd_addr_gray_wr_r[0] +.sym 31370 rx_fifo.rd_addr_gray_wr[5] +.sym 31374 rx_fifo.rd_addr_gray_wr[7] +.sym 31378 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] +.sym 31379 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] +.sym 31380 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] +.sym 31381 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] +.sym 31383 w_rx_09_fifo_data[19] +.sym 31384 w_rx_24_fifo_data[19] +.sym 31385 channel +.sym 31394 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 31398 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] +.sym 31402 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 31406 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 31410 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 31414 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 31421 rx_fifo.wr_addr[0] +.sym 31422 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 31427 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 31432 rx_fifo.wr_addr[2] +.sym 31433 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] +.sym 31436 rx_fifo.wr_addr[3] +.sym 31437 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 31440 rx_fifo.wr_addr[4] +.sym 31441 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 31444 rx_fifo.wr_addr[5] +.sym 31445 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 31448 rx_fifo.wr_addr[6] +.sym 31449 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 31452 rx_fifo.wr_addr[7] +.sym 31453 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 31456 rx_fifo.wr_addr[8] +.sym 31457 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 31460 rx_fifo.wr_addr[9] +.sym 31461 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 31466 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.sym 31467 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] +.sym 31468 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 31469 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.sym 31471 rx_fifo.rd_addr_gray_wr_r[2] +.sym 31472 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 31473 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 31474 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] +.sym 31475 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 31476 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.sym 31477 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 31478 spi_if_ins.w_rx_data[1] +.sym 31484 rx_fifo.rd_addr_gray_wr_r[5] +.sym 31485 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.sym 31487 rx_fifo.rd_addr_gray_wr_r[7] +.sym 31488 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.sym 31489 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.sym 31490 w_rx_fifo_pulled_data[31] +.sym 31495 w_rx_09_fifo_data[28] +.sym 31496 w_rx_24_fifo_data[28] +.sym 31497 channel +.sym 31499 w_rx_09_fifo_data[30] +.sym 31500 w_rx_24_fifo_data[30] +.sym 31501 channel +.sym 31503 w_rx_09_fifo_data[6] +.sym 31504 w_rx_24_fifo_data[6] +.sym 31505 channel +.sym 31506 w_rx_fifo_pulled_data[7] +.sym 31510 w_rx_fifo_pulled_data[28] +.sym 31515 w_rx_09_fifo_data[29] +.sym 31516 w_rx_24_fifo_data[29] +.sym 31517 channel +.sym 31518 w_rx_fifo_pulled_data[30] +.sym 31522 w_rx_fifo_pulled_data[4] +.sym 31530 w_rx_fifo_pulled_data[6] +.sym 31535 w_rx_09_fifo_data[7] +.sym 31536 w_rx_24_fifo_data[7] +.sym 31537 channel +.sym 31542 w_rx_fifo_pulled_data[5] +.sym 31550 w_rx_fifo_pulled_data[25] +.sym 31558 w_tx_data_sys[3] +.sym 31559 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31560 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31561 w_tx_data_io[3] +.sym 31569 spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O +.sym 31587 w_tx_data_io[7] +.sym 31588 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31589 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 31591 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31592 w_tx_data_sys[0] +.sym 31593 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[2] +.sym 31595 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31596 w_tx_data_sys[1] +.sym 31597 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[2] +.sym 31599 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31600 w_tx_data_sys[5] +.sym 31601 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31603 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31604 w_tx_data_sys[4] +.sym 31605 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.sym 31606 w_tx_data_sys[6] +.sym 31607 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31608 spi_if_ins.o_cs_SB_LUT4_I1_O[2] +.sym 31609 w_tx_data_io[6] +.sym 31610 w_tx_data_sys[2] +.sym 31611 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31612 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] +.sym 31613 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[3] +.sym 31615 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] +.sym 31616 w_tx_data_sys[7] +.sym 31617 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +.sym 31619 w_fetch +.sym 31620 w_cs[0] +.sym 31621 w_load +.sym 31622 w_fetch +.sym 31623 w_cs[1] +.sym 31624 i_button_SB_LUT4_I2_I1[0] +.sym 31625 w_load +.sym 31627 w_tx_data_smi[0] +.sym 31628 spi_if_ins.o_cs_SB_LUT4_I1_O[1] +.sym 31629 spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] +.sym 31630 w_ioc[2] +.sym 31631 w_ioc[1] +.sym 31632 w_ioc[4] +.sym 31633 w_ioc[3] .sym 31634 w_rx_data[1] -.sym 31638 w_rx_data[5] -.sym 31643 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 31644 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] -.sym 31645 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] -.sym 31646 w_rx_data[7] -.sym 31652 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31653 i_button_SB_LUT4_I0_I3[2] -.sym 31654 i_config[2]$SB_IO_IN -.sym 31655 io_ctrl_ins.pmod_dir_state[5] -.sym 31656 i_button_SB_LUT4_I0_I3[2] -.sym 31657 i_button_SB_LUT4_I0_I3[3] -.sym 31658 w_rx_data[6] -.sym 31662 w_rx_data[3] -.sym 31666 w_rx_data[4] -.sym 31671 io_pmod_out[3]$SB_IO_OUT -.sym 31672 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 31673 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 31674 i_rst_b$SB_IO_IN -.sym 31675 w_cs[1] -.sym 31676 w_load -.sym 31677 w_fetch -.sym 31680 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 31681 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] -.sym 31682 w_rx_data[3] -.sym 31686 w_rx_data[5] -.sym 31690 w_cs[1] -.sym 31691 w_load -.sym 31692 w_fetch -.sym 31693 o_led0_SB_LUT4_I1_O[1] -.sym 31694 o_tr_vc1_b$SB_IO_OUT -.sym 31695 o_led1_SB_LUT4_I1_I2[1] -.sym 31696 i_button_SB_LUT4_I0_I3[2] -.sym 31697 i_button_SB_LUT4_I0_O[1] -.sym 31698 w_rx_data[6] -.sym 31704 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 31705 i_button_SB_LUT4_I0_O[1] -.sym 31708 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 31709 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31710 w_rx_data[7] -.sym 31716 o_led1_SB_LUT4_I1_O[0] -.sym 31717 o_led0_SB_LUT4_I1_O[0] -.sym 31718 w_rx_data[3] -.sym 31722 w_rx_data[1] -.sym 31727 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] -.sym 31728 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] -.sym 31729 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] -.sym 31730 w_rx_data[4] -.sym 31734 w_rx_data[0] -.sym 31742 w_rx_data[2] -.sym 31747 i_config[1]$SB_IO_IN -.sym 31748 o_led1_SB_LUT4_I1_I3[3] -.sym 31749 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] -.sym 31780 o_smi_write_req$SB_IO_OUT -.sym 31781 i_rst_b$SB_IO_IN -.sym 31811 w_smi_data_input[7] -.sym 31812 smi_ctrl_ins.tx_reg_state[2] -.sym 31813 smi_ctrl_ins.tx_reg_state[1] -.sym 31815 i_rst_b$SB_IO_IN -.sym 31816 w_smi_data_input[7] -.sym 31817 smi_ctrl_ins.tx_reg_state[2] -.sym 31819 i_rst_b$SB_IO_IN -.sym 31820 w_smi_data_input[7] -.sym 31821 smi_ctrl_ins.tx_reg_state[0] -.sym 31822 i_rst_b$SB_IO_IN -.sym 31823 w_smi_data_input[7] -.sym 31824 smi_ctrl_ins.tx_reg_state[3] -.sym 31825 smi_ctrl_ins.tx_reg_state[0] -.sym 31827 i_rst_b$SB_IO_IN -.sym 31828 w_smi_data_input[7] -.sym 31829 smi_ctrl_ins.tx_reg_state[1] -.sym 31832 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] -.sym 31833 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] -.sym 31835 i_rst_b$SB_IO_IN -.sym 31836 smi_ctrl_ins.tx_reg_state[3] -.sym 31837 smi_ctrl_ins.tx_reg_state[0] -.sym 31850 smi_ctrl_ins.w_fifo_push_trigger -.sym 31882 tx_fifo.rd_addr_gray[8] -.sym 31902 tx_fifo.rd_addr_gray_wr[8] -.sym 31909 i_ss$SB_IO_IN -.sym 31970 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 31974 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 31978 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 31982 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 31990 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 31994 i_mosi$SB_IO_IN -.sym 31998 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 32020 i_smi_soe_se$SB_IO_IN -.sym 32021 i_rst_b$SB_IO_IN -.sym 32027 spi_if_ins.r_tx_byte[7] -.sym 32028 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 32029 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 32054 w_rx_data[0] -.sym 32070 w_cs[2] -.sym 32071 w_load -.sym 32072 w_fetch -.sym 32073 o_led1_SB_LUT4_I1_I3[3] -.sym 32090 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 32098 w_cs[1] -.sym 32099 w_load -.sym 32100 w_fetch -.sym 32101 o_led1_SB_LUT4_I1_I3[3] -.sym 32118 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] -.sym 32119 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] -.sym 32120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] -.sym 32121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] -.sym 32134 w_rx_data[7] -.sym 32138 io_pmod_out[2]$SB_IO_OUT -.sym 32139 o_shdn_tx_lna$SB_IO_OUT -.sym 32140 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 32141 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 32143 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0] -.sym 32144 i_button_SB_LUT4_I0_I3[2] -.sym 32145 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] -.sym 32154 w_rx_data[3] -.sym 32159 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 32160 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.sym 32161 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] -.sym 32183 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] -.sym 32184 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] -.sym 32185 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] -.sym 32191 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] -.sym 32192 o_led0_SB_LUT4_I1_O[1] -.sym 32193 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] -.sym 32196 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] -.sym 32197 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 32200 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] -.sym 32201 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] -.sym 32210 o_led1_SB_LUT4_I1_I3[0] -.sym 32211 o_led0$SB_IO_OUT -.sym 32212 i_button_SB_LUT4_I0_I3[2] -.sym 32213 o_led1_SB_LUT4_I1_I3[3] -.sym 32214 i_config[0]$SB_IO_IN -.sym 32215 o_tr_vc2$SB_IO_OUT -.sym 32216 o_led1_SB_LUT4_I1_I3[3] -.sym 32217 i_button_SB_LUT4_I0_O[1] -.sym 32251 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] -.sym 32252 o_led0_SB_LUT4_I1_O[1] -.sym 32253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] -.sym 32353 w_smi_data_input[7] -.sym 32553 r_counter -.sym 32602 spi_if_ins.w_rx_data[1] -.sym 32622 w_rx_data[0] -.sym 32630 w_rx_data[1] -.sym 32642 w_rx_data[1] -.sym 32654 w_rx_data[3] -.sym 32662 w_rx_data[2] -.sym 32666 w_rx_data[0] -.sym 32700 w_rx_fifo_full -.sym 32701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] -.sym 32707 w_rx_fifo_full -.sym 32708 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 32709 w_lvds_rx_09_d1_SB_LUT4_I2_O[3] +.sym 31641 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 31646 w_rx_data[0] +.sym 31650 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] +.sym 31651 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 31652 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] +.sym 31653 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3] +.sym 31654 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 31655 io_ctrl_ins.pmod_dir_state[2] +.sym 31656 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 31657 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 31658 io_ctrl_ins.debug_mode[1] +.sym 31659 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 31660 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] +.sym 31661 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3] +.sym 31662 i_button_SB_LUT4_I2_I1[0] +.sym 31663 io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] +.sym 31664 io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] +.sym 31665 io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] +.sym 31666 io_ctrl_ins.debug_mode[0] +.sym 31667 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 31668 i_button_SB_LUT4_I2_I1[0] +.sym 31669 o_led0$SB_IO_OUT +.sym 31676 w_ioc[2] +.sym 31677 sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.sym 31678 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31679 io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] +.sym 31680 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 31681 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 31682 io_ctrl_ins.pmod_dir_state[1] +.sym 31683 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 31684 i_button_SB_LUT4_I2_I1[0] +.sym 31685 o_led1$SB_IO_OUT +.sym 31690 io_ctrl_ins.pmod_dir_state[3] +.sym 31691 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 31692 i_button_SB_LUT4_I2_I1[0] +.sym 31693 i_config[0]$SB_IO_IN +.sym 31694 w_rx_data[4] +.sym 31698 w_rx_data[3] +.sym 31702 io_ctrl_ins.pmod_dir_state[4] +.sym 31703 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 31704 i_button_SB_LUT4_I2_I1[0] +.sym 31705 i_config[1]$SB_IO_IN +.sym 31706 w_fetch +.sym 31707 w_cs[1] +.sym 31708 i_rst_b$SB_IO_IN +.sym 31709 w_load +.sym 31710 w_rx_data[1] +.sym 31715 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31716 io_ctrl_ins.rf_pin_state[6] +.sym 31717 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31718 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31719 i_button_SB_LUT4_I2_I1[2] +.sym 31720 io_ctrl_ins.rf_pin_state[2] +.sym 31721 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31723 io_ctrl_ins.rf_pin_state[1] +.sym 31724 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31725 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31727 io_ctrl_ins.rf_pin_state[7] +.sym 31728 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31729 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31732 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 31733 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 31735 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31736 io_ctrl_ins.rf_pin_state[4] +.sym 31737 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31739 io_ctrl_ins.rf_pin_state[5] +.sym 31740 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31741 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31742 io_ctrl_ins.rf_pin_state[3] +.sym 31743 i_button_SB_LUT4_I2_I1[2] +.sym 31744 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31745 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31746 w_rx_data[0] +.sym 31750 w_rx_data[5] +.sym 31754 w_rx_data[3] +.sym 31758 w_rx_data[6] +.sym 31762 w_rx_data[1] +.sym 31766 w_rx_data[4] +.sym 31770 w_rx_data[2] +.sym 31774 w_rx_data[7] +.sym 31778 rx_fifo.rd_addr_gray_wr[0] +.sym 31788 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.sym 31789 rx_fifo.rd_addr[3] +.sym 31792 rx_fifo.wr_addr_gray_rd_r[7] +.sym 31793 rx_fifo.rd_addr[8] +.sym 31794 rx_fifo.rd_addr_gray[4] +.sym 31798 rx_fifo.rd_addr_gray[0] +.sym 31806 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 31807 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] +.sym 31808 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 31809 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 31811 w_smi_read_req_SB_LUT4_I1_O[0] +.sym 31812 w_smi_read_req_SB_LUT4_I1_O[1] +.sym 31813 w_smi_read_req_SB_LUT4_I1_O[2] +.sym 31816 rx_fifo.rd_addr[0] +.sym 31817 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 31820 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 31821 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 31822 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 31826 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] +.sym 31832 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 31833 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 31834 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 31838 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 31842 rx_fifo.wr_addr_gray_rd[5] +.sym 31846 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 31847 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] +.sym 31848 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[2] +.sym 31849 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] +.sym 31852 w_rx_fifo_pull +.sym 31853 i_rst_b$SB_IO_IN +.sym 31856 i_rst_b$SB_IO_IN +.sym 31857 i_smi_soe_se$SB_IO_IN +.sym 31858 rx_fifo.wr_addr_gray_rd[3] +.sym 31864 rx_fifo.rd_addr[0] +.sym 31865 rx_fifo.wr_addr_gray_rd_r[0] +.sym 31866 rx_fifo.wr_addr_gray_rd[7] +.sym 31870 rx_fifo.wr_addr_gray_rd[8] +.sym 31874 rx_fifo.wr_addr_gray[5] +.sym 31878 rx_fifo.wr_addr_gray[8] +.sym 31882 rx_fifo.wr_addr_gray[0] +.sym 31886 rx_fifo.wr_addr_gray[2] +.sym 31894 rx_fifo.wr_addr_gray_rd[0] +.sym 31898 rx_fifo.wr_addr_gray[3] +.sym 31902 rx_fifo.wr_addr_gray[7] +.sym 31906 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 31912 rx_fifo.wr_addr[0] +.sym 31913 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] +.sym 31914 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 31920 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 31921 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 31922 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] +.sym 31926 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 31930 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 31936 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 31937 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] +.sym 31941 w_rx_24_fifo_data[15] +.sym 31943 w_rx_09_fifo_data[21] +.sym 31944 w_rx_24_fifo_data[21] +.sym 31945 channel +.sym 31957 $PACKER_VCC_NET +.sym 31958 lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.sym 31963 w_rx_09_fifo_data[17] +.sym 31964 w_rx_24_fifo_data[17] +.sym 31965 channel +.sym 31966 w_tx_fsm_state[0] +.sym 31967 w_tx_fsm_state[1] +.sym 31968 lvds_tx_inst.fifo_empty_d2 +.sym 31969 lvds_tx_inst.r_tx_state +.sym 31972 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31973 w_rx_24_fifo_data[17] +.sym 31976 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31977 w_rx_24_fifo_data[15] +.sym 31980 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31981 w_rx_24_fifo_data[18] +.sym 31983 w_rx_09_fifo_data[31] +.sym 31984 w_rx_24_fifo_data[31] +.sym 31985 channel +.sym 31988 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31989 w_rx_24_fifo_data[14] +.sym 31992 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31993 w_rx_24_fifo_data[3] +.sym 31996 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 31997 w_rx_24_fifo_data[12] +.sym 32000 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 32001 w_rx_24_fifo_data[21] +.sym 32004 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 32005 w_rx_24_fifo_data[5] +.sym 32012 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 32013 w_rx_24_fifo_data[4] +.sym 32016 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 32017 w_rx_24_fifo_data[29] +.sym 32019 w_rx_09_fifo_data[5] +.sym 32020 w_rx_24_fifo_data[5] +.sym 32021 channel +.sym 32025 $PACKER_VCC_NET +.sym 32028 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 32029 w_rx_24_fifo_data[28] +.sym 32032 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 32033 w_rx_24_fifo_data[7] +.sym 32041 w_rx_fifo_data[5] +.sym 32042 w_rx_data[0] +.sym 32050 w_rx_data[2] +.sym 32057 $PACKER_VCC_NET +.sym 32061 $PACKER_VCC_NET +.sym 32066 spi_if_ins.r_tx_byte[5] +.sym 32070 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 32071 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 32072 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32073 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 32077 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 32078 spi_if_ins.r_tx_byte[0] +.sym 32082 spi_if_ins.spi.r_tx_byte[1] +.sym 32083 spi_if_ins.spi.r_tx_byte[5] +.sym 32084 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32085 spi_if_ins.spi.r_tx_bit_count[2] +.sym 32086 spi_if_ins.r_tx_byte[1] +.sym 32090 spi_if_ins.r_tx_byte[4] +.sym 32094 spi_if_ins.r_tx_byte[6] +.sym 32104 i_ss$SB_IO_IN +.sym 32105 spi_if_ins.r_tx_data_valid +.sym 32110 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 32117 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32123 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 32124 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 32125 i_rst_b$SB_IO_IN +.sym 32131 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 32132 i_rst_b$SB_IO_IN +.sym 32133 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32135 i_button_SB_LUT4_I2_I1[1] +.sym 32136 i_button$SB_IO_IN +.sym 32137 io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] +.sym 32141 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 32143 i_button_SB_LUT4_I2_I1[1] +.sym 32144 i_config[2]$SB_IO_IN +.sym 32145 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] +.sym 32153 i_ss$SB_IO_IN +.sym 32159 i_button_SB_LUT4_I2_I1[1] +.sym 32160 i_config[3]$SB_IO_IN +.sym 32161 io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[2] +.sym 32162 w_rx_data[7] +.sym 32166 o_tr_vc1$SB_IO_OUT +.sym 32167 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 32168 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 32169 io_ctrl_ins.pmod_dir_state[5] +.sym 32170 o_rx_h_tx_l$SB_IO_OUT +.sym 32171 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 32172 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 32173 io_ctrl_ins.pmod_dir_state[7] +.sym 32174 o_rx_h_tx_l_b$SB_IO_OUT +.sym 32175 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.sym 32176 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 32177 io_ctrl_ins.pmod_dir_state[6] +.sym 32178 w_rx_data[6] +.sym 32182 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 32183 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32184 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32185 i_rst_b$SB_IO_IN +.sym 32186 w_rx_data[2] +.sym 32190 w_rx_data[5] +.sym 32204 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] +.sym 32205 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.sym 32206 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 32214 spi_if_ins.spi.r2_rx_done +.sym 32226 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 32286 w_rx_data[0] +.sym 32290 rx_fifo.wr_addr_gray_rd[4] +.sym 32340 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 32341 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 32345 rx_fifo.rd_addr[0] +.sym 32354 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 32367 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 32368 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] +.sym 32369 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[2] +.sym 32370 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] +.sym 32383 rx_fifo.rd_addr[0] +.sym 32384 rx_fifo.wr_addr_gray_rd_r[0] +.sym 32385 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 32405 i_rst_b_SB_LUT4_I3_O +.sym 32410 rx_fifo.wr_addr_gray[1] +.sym 32414 rx_fifo.wr_addr_gray_rd[1] +.sym 32418 rx_fifo.rd_addr_gray_wr[1] +.sym 32422 rx_fifo.rd_addr_gray[8] +.sym 32430 rx_fifo.rd_addr_gray[1] +.sym 32445 i_rst_b$SB_IO_IN +.sym 32465 w_rx_24_fifo_data[3] +.sym 32477 w_rx_24_fifo_data[21] +.sym 32478 spi_if_ins.spi.SCKr[1] +.sym 32497 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 32499 spi_if_ins.spi.SCKr[2] +.sym 32500 spi_if_ins.spi.SCKr[1] +.sym 32501 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32507 spi_if_ins.r_tx_byte[7] +.sym 32508 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 32509 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32515 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32519 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 32520 $PACKER_VCC_NET +.sym 32523 spi_if_ins.spi.r_tx_bit_count[2] +.sym 32524 $PACKER_VCC_NET +.sym 32525 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 32529 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32533 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 32544 $PACKER_VCC_NET +.sym 32545 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32550 spi_if_ins.spi.SCKr[2] +.sym 32551 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32552 spi_if_ins.spi.r_tx_bit_count[2] +.sym 32553 spi_if_ins.spi.SCKr[1] +.sym 32556 w_rx_fifo_full +.sym 32557 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] +.sym 32558 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 32559 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 32560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 32561 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 32565 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 32567 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 32568 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 32569 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 32586 spi_if_ins.r_tx_byte[3] +.sym 32590 spi_if_ins.r_tx_byte[2] +.sym 32594 spi_if_ins.r_tx_byte[7] +.sym 32598 spi_if_ins.spi.r_tx_byte[2] +.sym 32599 spi_if_ins.spi.r_tx_byte[6] +.sym 32600 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32601 spi_if_ins.spi.r_tx_bit_count[2] +.sym 32602 spi_if_ins.spi.r_tx_byte[3] +.sym 32603 spi_if_ins.spi.r_tx_byte[7] +.sym 32604 spi_if_ins.spi.r_tx_bit_count[2] +.sym 32605 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 32612 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 32613 i_rst_b$SB_IO_IN +.sym 32614 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32615 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 32616 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 32617 i_rst_b$SB_IO_IN +.sym 32622 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 32623 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32624 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32625 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 32628 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 32629 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32631 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 32632 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32633 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 32638 lvds_tx_inst.tx_state_d1 +.sym 32642 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 32643 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 32644 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] +.sym 32645 i_rst_b$SB_IO_IN +.sym 32647 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] +.sym 32648 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] +.sym 32649 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.sym 32650 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 32655 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32656 spi_if_ins.state_if[1] +.sym 32657 spi_if_ins.state_if[0] +.sym 32659 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32660 spi_if_ins.state_if[0] +.sym 32661 spi_if_ins.state_if[1] +.sym 32664 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 32665 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32667 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32668 spi_if_ins.state_if[0] +.sym 32669 spi_if_ins.state_if[1] +.sym 32671 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 32672 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 32673 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32674 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 32682 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32683 spi_if_ins.state_if[0] +.sym 32684 spi_if_ins.state_if[1] +.sym 32685 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32686 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 32696 spi_if_ins.state_if[0] +.sym 32697 spi_if_ins.state_if[1] +.sym 32699 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] +.sym 32700 spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.sym 32701 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.sym 32706 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 32717 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32746 spi_if_ins.spi.r_rx_done diff --git a/firmware/top.bin b/firmware/top.bin index 48191cd6..457e8ae5 100644 Binary files a/firmware/top.bin and b/firmware/top.bin differ diff --git a/firmware/top.blif b/firmware/top.blif index 361df8a1..bc97b40f 100644 --- a/firmware/top.blif +++ b/firmware/top.blif @@ -1,4 +1,4 @@ -# Generated by Yosys 0.39+0 (git sha1 18cec2d9a, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) +# Generated by Yosys 0.23 (git sha1 7ce5011c24b) .model top .inputs i_glob_clock i_rst_b i_iq_rx_09_p i_iq_rx_24_n i_iq_rx_clk_p i_config[0] i_config[1] i_config[2] i_config[3] i_button io_pmod_in[0] io_pmod_in[1] io_pmod_in[2] io_pmod_in[3] i_smi_a2 i_smi_a3 i_smi_soe_se i_smi_swe_srw io_smi_data[0] io_smi_data[1] io_smi_data[2] io_smi_data[3] io_smi_data[4] io_smi_data[5] io_smi_data[6] io_smi_data[7] i_mosi i_sck i_ss @@ -7,341 +7,366 @@ .names $true 1 .names $undef -.gate SB_LUT4 I0=i_button I1=io_ctrl_ins.pmod_dir_state[7] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_button_SB_LUT4_I0_I3[3] O=i_button_SB_LUT4_I0_O[2] +.gate SB_GB GLOBAL_BUFFER_OUTPUT=lvds_rx_09_inst.i_ddr_clk USER_SIGNAL_TO_GLOBAL_BUFFER=lvds_clock .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=i_button_SB_LUT4_I0_I3[3] +.attr src "top.v:264.9-267.4" +.gate SB_LUT4 I0=$false I1=i_button_SB_LUT4_I2_I1[1] I2=i_button I3=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010011010101111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[4] I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=i_config[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_rst_b O=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_ss O=i_ss_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.debug_mode[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.debug_mode[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.debug_mode[0] I3=io_ctrl_ins.debug_mode[1] O=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] I2=io_ctrl_ins.debug_mode[1] I3=i_rst_b O=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000001100000000 -.gate SB_LUT4 I0=i_config[2] I1=io_ctrl_ins.pmod_dir_state[5] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_button_SB_LUT4_I0_I3[3] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] I2=io_ctrl_ins.rf_mode[2] I3=io_ctrl_ins.rf_mode[1] O=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=i_config[3] I1=io_ctrl_ins.pmod_dir_state[6] I2=o_led1_SB_LUT4_I1_I2[2] I3=i_button_SB_LUT4_I0_I3[3] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D[9] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=io_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111001100110011 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_rst_b O=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] I3=spi_if_ins.o_ioc[0] O=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_ss O=o_miso_$_TBUF__Y_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[2] I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[4] I3=spi_if_ins.o_ioc[3] O=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=io_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000001 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.led1_state_SB_DFFER_Q_E Q=io_ctrl_ins.led0_state R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=io_ctrl_ins.i_cs_SB_DFFESR_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=io_ctrl_ins.debug_mode[0] I1=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=io_ctrl_ins.led0_state O=io_ctrl_ins.led0_state_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_rx_shutdown_state +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.led1_state_SB_DFFER_Q_E Q=io_ctrl_ins.led1_state R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=io_ctrl_ins.i_cs I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=spi_if_ins.o_load_cmd O=io_ctrl_ins.led1_state_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000111111001100 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000000000000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=io_ctrl_ins.led1_state O=io_ctrl_ins.led1_state_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[2] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[1] I1=io_ctrl_ins.lna_rx_shutdown_state I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] O=io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111110101010 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010111111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.lna_rx_shutdown_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100101000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_dir_state[2] I2=o_led1_SB_LUT4_I1_I2[2] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] O=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[1] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] O=io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000111111001100 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.lna_tx_shutdown_state +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_mode[1] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_pin_state[2] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] O=io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.mixer_en_state +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1011101111110000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[2] I1=io_ctrl_ins.lna_tx_shutdown_state I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010111111111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.mixer_en_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[0] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] O=io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[0] I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.mixer_en_state I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=o_led0_SB_LUT4_I1_O[2] +.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[0] I1=io_ctrl_ins.mixer_en_state I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] O=io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110001000000000 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010111111111 +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=io_ctrl_ins.o_data_out[1] R=io_ctrl_ins.o_data_out_SB_DFFESS_Q_S .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=o_led0_SB_LUT4_I1_O[1] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=io_ctrl_ins.debug_mode[1] I1=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I2=io_ctrl_ins.led1_state_SB_LUT4_I3_O[2] I3=io_ctrl_ins.led1_state_SB_LUT4_I3_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 -.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E Q=io_ctrl_ins.o_data_out[2] R=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000111111111111 +.gate SB_DFFESR C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=io_ctrl_ins.o_data_out[3] R=io_ctrl_ins.o_data_out_SB_DFFESS_Q_S .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I2=o_led0_SB_LUT4_I1_O[1] I3=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=io_ctrl_ins.rf_mode[1] I1=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000111111111111 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111001100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111111111 +.gate SB_LUT4 I0=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I1=io_ctrl_ins.pmod_dir_state[2] I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=io_ctrl_ins.rf_mode[0] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111111 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I1=o_led0_SB_LUT4_I1_O[1] I2=o_led1_SB_LUT4_I1_O[2] I3=o_led1_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] I2=io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001011111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011111100000000 -.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_DFFESS C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=io_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=io_ctrl_ins.o_data_out[0] S=io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I2=io_ctrl_ins.led0_state_SB_LUT4_I3_O[2] I3=io_ctrl_ins.led0_state_SB_LUT4_I3_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I1=o_led0_SB_LUT4_I1_O[1] I2=o_led0_SB_LUT4_I1_O[2] I3=o_led0_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000111111111111 +.gate SB_LUT4 I0=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I1=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] I2=io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111001011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[7] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110111100000000 +.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] O=io_ctrl_ins.o_data_out_SB_DFFESS_Q_S .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[6] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E Q=io_ctrl_ins.o_data_out[5] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] Q=io_ctrl_ins.o_data_out[4] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=i_config[1] I2=o_led1_SB_LUT4_I1_I3[3] I3=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=i_button_SB_LUT4_I2_I1[1] I2=i_config[3] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000011111111 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2] +.gate SB_DFFE C=r_counter D=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D E=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E Q=io_ctrl_ins.o_data_out[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=i_button_SB_LUT4_I2_I1[1] I2=i_config[2] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=$false I1=i_button_SB_LUT4_I2_I1[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011000000 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=io_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111001100000000 +.gate SB_LUT4 I0=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I1=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] I2=io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[7] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110111100000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[6] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[5] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[4] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[3] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[2] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[1] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O Q=io_ctrl_ins.pmod_dir_state[0] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O Q=io_ctrl_ins.pmod_dir_state[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E Q=io_ctrl_ins.pmod_state[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_I2[2] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I3=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] I3=o_led1_SB_LUT4_I1_I2[3] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] I3=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_load_cmd I3=spi_if_ins.o_fetch_cmd O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000010000000 -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[7] +.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=io_ctrl_ins.i_cs I2=i_rst_b I3=spi_if_ins.o_load_cmd O=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[6] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[5] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[4] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.rf_mode[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[3] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.rf_mode[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[2] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.rf_mode_SB_DFFER_Q_E Q=io_ctrl_ins.rf_mode[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[1] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=io_ctrl_ins.i_cs I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=spi_if_ins.o_load_cmd O=io_ctrl_ins.rf_mode_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O Q=io_ctrl_ins.rf_pin_state[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000000000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[7] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_b_state +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[6] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[6] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[5] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011111100 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_b_state I2=o_led1_SB_LUT4_I1_I2[3] I3=io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_1_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.rx_h_state +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[2] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111111100001100 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I1=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100001000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rx_h_state I2=o_led1_SB_LUT4_I1_I2[3] I3=i_button_SB_LUT4_I0_O[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_1_O Q=io_ctrl_ins.rf_pin_state[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_b_state +.attr src "top.v:188.11-215.4|io_ctrl.v:111.5-207.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.rx_h_b_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[4] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] I2=io_ctrl_ins.rf_pin_state[6] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111110010101010 -.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=io_ctrl_ins.pmod_dir_state[4] I2=o_led1_SB_LUT4_I1_I2[2] I3=o_led1_SB_LUT4_I1_I2[3] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111100110000 +.gate SB_LUT4 I0=io_ctrl_ins.rx_h_b_state I1=io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I3=io_ctrl_ins.pmod_dir_state[6] O=io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.rx_h_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[7] I2=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] I3=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011111100 +.gate SB_LUT4 I0=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] I1=io_ctrl_ins.rf_mode[0] I2=io_ctrl_ins.rf_mode[2] I3=io_ctrl_ins.rf_mode[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E Q=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010100000101010 +.gate SB_LUT4 I0=io_ctrl_ins.rx_h_state I1=io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I3=io_ctrl_ins.pmod_dir_state[7] O=io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] I3=spi_if_ins.o_ioc[0] O=io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=i_rst_b I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.tr_vc_1_b_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000101010101010 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1] O=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] I2=io_ctrl_ins.rf_pin_state[4] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led0_SB_LUT4_I1_O[1] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111100110000 +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_b_state I1=io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111100011111111 +.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I2=i_button_SB_LUT4_I2_I1[1] I3=io_ctrl_ins.rf_mode[2] O=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000010010101111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_1_state +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.tr_vc_1_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[5] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.rf_pin_state[5] I2=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] I3=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000001110101010 -.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000011111100 +.gate SB_LUT4 I0=io_ctrl_ins.rf_mode[0] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] O=io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.tr_vc_1_state I2=o_led1_SB_LUT4_I1_I2[3] I3=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2] O=io_ctrl_ins.o_data_out_SB_DFFE_Q_2_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111000100000000 +.gate SB_LUT4 I0=io_ctrl_ins.tr_vc_1_state I1=io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I3=io_ctrl_ins.pmod_dir_state[5] O=io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011111111 -.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.rx_h_state_SB_DFFE_Q_E Q=io_ctrl_ins.tr_vc_2_state +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_DFFE C=r_counter D=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D E=io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O Q=io_ctrl_ins.tr_vc_2_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:210.5-308.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] I2=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] I3=io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D +.attr src "top.v:188.11-215.4|io_ctrl.v:210.5-308.8|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=io_ctrl_ins.rf_pin_state[3] I1=io_ctrl_ins.rf_mode[2] I2=io_ctrl_ins.rf_mode[1] I3=io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] O=io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0011110010101010 -.gate SB_LUT4 I0=i_config[0] I1=io_ctrl_ins.tr_vc_2_state I2=o_led1_SB_LUT4_I1_I3[3] I3=o_led1_SB_LUT4_I1_I2[3] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[3] I1=io_ctrl_ins.tr_vc_2_state I2=spi_if_ins.o_ioc[0] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010111111111 +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] O=io_ctrl_ins.i_cs_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001101011111 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[3] I1=o_led1_SB_LUT4_I1_I2[2] I2=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] I3=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] O=io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000011100000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.pmod_state[3] I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000100000000 +.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[3] I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=i_config[0] O=io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_09_p +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_09_d0 D_IN_1=w_lvds_rx_09_d1 INPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=i_iq_rx_09_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:289.7-294.4" +.attr src "top.v:295.7-300.4" .param IO_STANDARD "SB_LVDS_INPUT" .param NEG_TRIGGER 0 .param PIN_TYPE 000000 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_clock PACKAGE_PIN=i_iq_rx_24_n +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_lvds_rx_24_d0 D_IN_1=w_lvds_rx_24_d1 INPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=i_iq_rx_24_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:274.7-280.4" +.attr src "top.v:280.7-286.4" .param IO_STANDARD "SB_LVDS_INPUT" .param NEG_TRIGGER 0 .param PIN_TYPE 000000 @@ -350,1022 +375,1262 @@ .attr src "top.v:256.7-259.4" .param IO_STANDARD "SB_LVDS_INPUT" .param PIN_TYPE 000001 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=iq_tx_n_OUTPUT_CLK PACKAGE_PIN=o_iq_tx_clk_n +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$true OUTPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=o_iq_tx_clk_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:335.5-338.4" +.attr src "top.v:351.5-356.4" .param IO_STANDARD "SB_LVCMOS" -.param PIN_TYPE 011001 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=lvds_clock PACKAGE_PIN=o_iq_tx_clk_p +.param PIN_TYPE 010000 +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$false OUTPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=o_iq_tx_clk_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:326.5-329.4" +.attr src "top.v:340.5-345.4" .param IO_STANDARD "SB_LVCMOS" -.param PIN_TYPE 011001 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$false D_OUT_1=$false OUTPUT_CLK=iq_tx_n_OUTPUT_CLK PACKAGE_PIN=o_iq_tx_n +.param PIN_TYPE 010000 +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=w_lvds_tx_d1 D_OUT_1=w_lvds_tx_d0 OUTPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=o_iq_tx_n .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:315.5-320.4" +.attr src "top.v:329.5-334.4" .param IO_STANDARD "SB_LVCMOS" .param PIN_TYPE 010000 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_clock O=iq_tx_n_OUTPUT_CLK -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=$true D_OUT_1=$true OUTPUT_CLK=iq_tx_n_OUTPUT_CLK PACKAGE_PIN=o_iq_tx_p +.gate SB_IO CLOCK_ENABLE=$true D_OUT_0=iq_tx_p_D_OUT_0 D_OUT_1=iq_tx_p_D_OUT_1 OUTPUT_CLK=lvds_rx_09_inst.i_ddr_clk PACKAGE_PIN=o_iq_tx_p .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:304.5-309.4" +.attr src "top.v:318.5-323.4" .param IO_STANDARD "SB_LVCMOS" .param PIN_TYPE 010000 -.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_tx_d1 O=iq_tx_p_D_OUT_0 .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_tx_d0 O=iq_tx_p_D_OUT_1 .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=io_pmod_in[3] I2=sys_ctrl_ins.rx_sync_09 I3=sys_ctrl_ins.rx_sync_type09 O=lvds_rx_09_inst.i_sync_input .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[1] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[2] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[2] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[11] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[12] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=w_lvds_rx_09_d0 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[13] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000100 -.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[14] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100101010101010 -.gate SB_LUT4 I0=$false I1=io_pmod_in[3] I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_09_inst.i_sync_input +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[15] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111111000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[16] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[17] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[18] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[19] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[20] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[3] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[21] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[22] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=spi_if_ins.o_load_cmd I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] O=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[23] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[2] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[24] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[3] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[25] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[12] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[26] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[10] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_10_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[27] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[13] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[28] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[11] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_11_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[29] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[14] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[30] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[12] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_12_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[4] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[15] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[5] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[13] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_13_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[6] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[16] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[7] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[14] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_14_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[8] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[17] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[9] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[15] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_15_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[10] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[18] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.r_state_if[0] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[16] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_16_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[19] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_O[0] E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_09_inst.o_fifo_data[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[17] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_17_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_D E=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E Q=lvds_rx_09_inst.o_fifo_push R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[20] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.r_state_if[1] O=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[18] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_18_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_CARRY CI=lvds_rx_09_inst.r_phase_count[0] CO=lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] I0=lvds_rx_09_inst.r_phase_count[1] I1=$true +.attr src "top.v:381.11-392.4|lvds_rx.v:64.28-64.45|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_phase_count[1] I2=$true I3=lvds_rx_09_inst.r_phase_count[0] O=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[21] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:64.28-64.45|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] I1=$false I2=$true I3=lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] O=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[19] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_19_D +.attr src "top.v:381.11-392.4|lvds_rx.v:64.28-64.45|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001011001101001 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] O=lvds_rx_09_inst.r_phase_count[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[1] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_1_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] O=lvds_rx_09_inst.r_phase_count[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[4] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] I2=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] I3=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] O=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[22] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[1] E=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_09_inst.r_state_if[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[20] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_20_D +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[0] E=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_09_inst.r_state_if[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[23] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[1] I2=lvds_rx_09_inst.r_state_if[0] I3=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] O=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[21] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_21_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[1] I2=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] I3=lvds_rx_09_inst.r_state_if[0] O=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[24] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000011111111 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d1_SB_LUT4_I2_O[1] I2=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I3=lvds_rx_09_inst.r_state_if[0] O=lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[22] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_22_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[29] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[30] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[25] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[23] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_23_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[28] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[29] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[26] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[19] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[20] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[24] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_24_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[18] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[19] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[27] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[17] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[18] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[25] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_25_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[16] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[17] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[28] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[15] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[16] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[26] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_26_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[14] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[15] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[29] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[13] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[14] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[27] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_27_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[12] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[13] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[30] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[11] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[12] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[28] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_28_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[10] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[11] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[31] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[27] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[28] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[29] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_29_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[9] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[10] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[8] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[5] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[7] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[3] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_3_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[6] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[6] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[5] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[4] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_4_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[4] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[7] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[3] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[5] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_5_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[2] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[8] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[6] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_6_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[0] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[9] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[26] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[27] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[7] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_7_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[25] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[26] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[10] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[24] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[25] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[8] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_8_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[23] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[24] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[11] R=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[22] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[23] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[9] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_9_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[21] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[22] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.o_fifo_data[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.o_fifo_data[20] O=lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_D[21] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFE C=lvds_clock D=w_lvds_rx_09_d0 E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[1] +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_09_inst.i_sync_input E=lvds_rx_09_inst.r_sync_input_SB_DFFER_Q_E Q=lvds_rx_09_inst.r_sync_input R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=lvds_clock D=lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1_D E=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O Q=lvds_rx_09_inst.o_fifo_data[0] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.r_state_if[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[1] O=lvds_rx_09_inst.r_sync_input_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_09_d1 I2=lvds_rx_09_inst.r_sync_input I3=lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] O=lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.r_state_if[1] O=lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.i_ddr_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O Q=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=io_pmod_in[2] I2=sys_ctrl_ins.rx_sync_24 I3=sys_ctrl_ins.rx_sync_type24 O=lvds_rx_24_inst.i_sync_input .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[1] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[2] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0] +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[11] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[12] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011000000 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=w_lvds_rx_24_d0 I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1] +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[13] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000001100 -.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[14] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000000110011 -.gate SB_LUT4 I0=$false I1=io_pmod_in[2] I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] I3=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] O=lvds_rx_24_inst.i_sync_input +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[15] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[16] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[17] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[2] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[18] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[3] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[19] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[12] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[20] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[10] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_10_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[3] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[13] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[21] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[11] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_11_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[22] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[14] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[23] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[12] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_12_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[24] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[15] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[25] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[13] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_13_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[26] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[16] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[27] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[14] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_14_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[28] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[17] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[29] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[15] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_15_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[30] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[18] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[4] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[16] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_16_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[5] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[19] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[6] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[17] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_17_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[7] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[20] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[8] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[18] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_18_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[9] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[21] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[10] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[19] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_19_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[1] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_1_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.i_ddr_data[1] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[4] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_O[0] E=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O Q=lvds_rx_24_inst.o_fifo_data[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[22] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_D E=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E Q=lvds_rx_24_inst.o_fifo_push R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[20] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_20_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.r_state_if[1] O=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[23] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_CARRY CI=lvds_rx_24_inst.r_phase_count[0] CO=lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] I0=lvds_rx_24_inst.r_phase_count[1] I1=$true +.attr src "top.v:394.11-407.4|lvds_rx.v:64.28-64.45|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_phase_count[1] I2=$true I3=lvds_rx_24_inst.r_phase_count[0] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:394.11-407.4|lvds_rx.v:64.28-64.45|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] I1=$false I2=$true I3=lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[21] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_21_D +.attr src "top.v:394.11-407.4|lvds_rx.v:64.28-64.45|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001011001101001 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] O=lvds_rx_24_inst.r_phase_count[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[24] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 O=lvds_rx_24_inst.r_phase_count[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_D E=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[22] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_22_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] I2=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1] I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[25] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101100000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_D E=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_1_D E=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] I2=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100111100000000 +.gate SB_LUT4 I0=lvds_rx_24_inst.r_state_if[1] I1=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] I2=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2] I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101100000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3 I2=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[0] I3=lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[23] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_23_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[1] E=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_state_if[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[0] E=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_state_if[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[1] I2=lvds_rx_24_inst.r_state_if[0] I3=w_lvds_rx_24_d1_SB_LUT4_I2_O[2] O=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[1] I2=w_lvds_rx_24_d1_SB_LUT4_I2_O[2] I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000011111111 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d0_SB_LUT4_I2_O[1] I2=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] I3=lvds_rx_24_inst.r_state_if[0] O=lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[29] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[30] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[26] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[28] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[29] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[24] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_24_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[19] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[20] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[27] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[18] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[19] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[25] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_25_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[17] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[18] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[28] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[16] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[17] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[26] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_26_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[15] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[16] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[29] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[14] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[15] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[27] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_27_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[13] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[14] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[30] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[12] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[13] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[28] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_28_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[11] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[12] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[31] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[10] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[11] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[29] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_29_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[27] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[28] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_2_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[9] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[10] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[5] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[8] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[3] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_3_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[7] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[6] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[6] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[4] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_4_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[5] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[7] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[4] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[5] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_5_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[8] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[2] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[6] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_6_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[1] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[9] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[0] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[7] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_7_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[26] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[27] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[10] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[25] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[26] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[8] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_8_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[24] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[25] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFESR C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[11] R=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[23] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[24] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[9] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_9_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[22] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[23] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.o_fifo_data[0] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[21] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[22] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[1] +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.o_fifo_data[20] O=lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_D[21] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=lvds_clock D=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_1_D E=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=lvds_rx_24_inst.o_fifo_data[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_rx_24_inst.i_sync_input E=lvds_rx_24_inst.r_sync_input_SB_DFFER_Q_E Q=lvds_rx_24_inst.r_sync_input R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_24_d0 O=lvds_rx_24_inst.o_fifo_data_SB_DFFE_Q_D +.attr src "top.v:394.11-407.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.r_state_if[0] I3=w_lvds_rx_24_d0_SB_LUT4_I2_O[1] O=lvds_rx_24_inst.r_sync_input_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] E=i_rst_b_SB_LUT4_I3_O Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=w_lvds_rx_24_d1 I2=lvds_rx_24_inst.r_sync_input I3=lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] O=lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_tx.v:58.5-128.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFNSR C=lvds_clock D=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D_SB_DFFNSR_Q_D Q=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000000110011 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.r_state_if[1] O=lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:88.2-96.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" -.gate SB_LUT4 I0=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D_SB_DFFNSR_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_DFFS C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.empty_o Q=lvds_tx_inst.fifo_empty_d1 S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010101010101 -.gate SB_LUT4 I0=lvds_tx_inst.r_pulled I1=tx_fifo.rd_addr_gray[9] I2=tx_fifo.wr_addr_gray_rd_r[9] I3=lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:64.5-67.8|/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_DFFS C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.fifo_empty_d1 Q=lvds_tx_inst.fifo_empty_d2 S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001010001 -.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[2] I3=tx_fifo.wr_addr_gray_rd_r[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] +.attr src "top.v:441.11-453.6|lvds_tx.v:64.5-67.8|/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_LUT4 I0=lvds_tx_inst.r_state[1] I1=lvds_tx_inst.fifo_empty_d2 I2=lvds_tx_inst.r_state[0] I3=lvds_tx_inst.tx_state_d2 O=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110000000000110 -.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled I2=tx_fifo.wr_addr_gray_rd_r[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001000000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_phase_count[2] I2=lvds_tx_inst.r_phase_count[3] I3=lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] O=lvds_tx_inst.frame_boundary .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110000001100 -.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1] I3=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[1] I1=lvds_tx_inst.r_fifo_data[9] I2=lvds_tx_inst.r_phase_count[2] I3=lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_phase_count[0] I3=lvds_tx_inst.r_phase_count[1] O=lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[8] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.r_dir O=lvds_tx_inst.i_tx_state .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000110000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[7] I1=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.pending_load_SB_DFFER_Q_D E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.pending_load R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100100000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr[1] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.fifo_empty_d2 I2=lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[1] I3=lvds_tx_inst.tx_state_d2 O=lvds_tx_inst.pending_load_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[5] I1=tx_fifo.wr_addr_gray_rd_r[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] O=lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[31] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[31] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001001000001 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=lvds_tx_inst.r_pulled O=lvds_tx_inst.r_pulled_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[30] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[30] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=o_led1_SB_DFFER_Q_E Q=o_led0 R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[21] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[21] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[0] I1=o_led0 I2=o_led1_SB_LUT4_I1_I2[2] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led0_SB_LUT4_I1_O[3] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[20] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[20] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001101011111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=o_led0_SB_LUT4_I1_O[1] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[19] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[19] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100111111111111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=o_led1_SB_LUT4_I1_I2[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[18] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[18] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[17] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[17] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=o_led1_SB_DFFER_Q_E Q=o_led1 R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[16] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[16] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "io_ctrl.v:111.5-207.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I3[3] O=o_led1_SB_DFFER_Q_E +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[15] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[15] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_dir_state[1] I1=o_led1 I2=o_led1_SB_LUT4_I1_I2[2] I3=o_led1_SB_LUT4_I1_I3[3] O=o_led1_SB_LUT4_I1_O[3] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[14] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[14] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001101011111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=o_led1_SB_LUT4_I1_I3[3] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[13] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[13] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=io_ctrl_ins.pmod_state[1] I1=io_ctrl_ins.lna_rx_shutdown_state I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=o_led1_SB_LUT4_I1_O[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[12] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[12] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100101000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[0] I3=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=o_led1_SB_LUT4_I1_I2[3] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[29] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[29] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[1] I3=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] O=o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[11] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[11] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=o_miso_$_TBUF__Y_E Y=o_miso -.attr src "top.v:152.19-152.43" -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=w_smi_read_req I3=smi_ctrl_ins.r_dir O=o_smi_read_req +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[10] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[10] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000000110011 -.gate SB_DFFSR C=i_glob_clock D=r_counter_SB_DFFSR_Q_D Q=r_counter R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[9] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=r_counter O=r_counter_SB_DFFSR_Q_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[8] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[7] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[7] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_1_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[6] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[6] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[6] I1=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_1_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[5] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[4] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[3] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[2] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_2_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[5] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[28] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[28] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_2_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[1] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[0] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[27] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[27] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[26] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[26] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001111 -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_3_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[4] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[25] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[25] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[4] I1=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_3_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[24] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[24] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[23] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[23] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[22] E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_fifo_data[22] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_4_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[3] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[3] E=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E Q=lvds_tx_inst.r_gap_frame_count[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[3] I1=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_4_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[2] E=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E Q=lvds_tx_inst.r_gap_frame_count[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010111000001100 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[1] E=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E Q=lvds_tx_inst.r_gap_frame_count[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_5_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[0] E=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E Q=lvds_tx_inst.r_gap_frame_count[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] I1=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] O=r_tx_data_SB_DFFE_Q_5_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_gap_frame_count[3] I2=$true I3=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] O=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:199.50-199.74|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_gap_frame_count[2] I2=$true I3=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] O=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111011111111 -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_6_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[1] +.attr src "top.v:441.11-453.6|lvds_tx.v:199.50-199.74|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_gap_frame_count[1] I2=$true I3=lvds_tx_inst.r_gap_frame_count[0] O=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_6_D +.attr src "top.v:441.11-453.6|lvds_tx.v:199.50-199.74|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_tx_inst.r_gap_frame_count[0] O=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_CARRY CI=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] CO=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] I0=lvds_tx_inst.r_gap_frame_count[2] I1=$true +.attr src "top.v:441.11-453.6|lvds_tx.v:199.50-199.74|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=lvds_tx_inst.r_gap_frame_count[0] CO=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] I0=lvds_tx_inst.r_gap_frame_count[1] I1=$true +.attr src "top.v:441.11-453.6|lvds_tx.v:199.50-199.74|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFS C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[3] Q=lvds_tx_inst.r_phase_count[3] S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=io_ctrl_ins.o_data_out[1] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_DFFS C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[2] Q=lvds_tx_inst.r_phase_count[2] S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001101011111 -.gate SB_DFFE C=i_glob_clock D=r_tx_data_SB_DFFE_Q_7_D E=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O Q=r_tx_data[0] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_DFFS C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[1] Q=lvds_tx_inst.r_phase_count[1] S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:225.3-239.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_7_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_DFFS C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[0] Q=lvds_tx_inst.r_phase_count[0] S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_phase_count[3] I2=$true I3=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[3] O=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:224.30-224.50|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_phase_count[2] I2=$true I3=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[2] O=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011111100000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:224.30-224.50|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_phase_count[1] I2=$true I3=lvds_tx_inst.r_phase_count[0] O=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001111 -.gate SB_LUT4 I0=$false I1=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] O=r_tx_data_SB_DFFE_Q_D +.attr src "top.v:441.11-453.6|lvds_tx.v:224.30-224.50|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=lvds_tx_inst.r_phase_count[0] O=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110011111111 -.gate SB_DFFER C=r_counter D=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_CARRY CI=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[2] CO=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[3] I0=lvds_tx_inst.r_phase_count[2] I1=$true +.attr src "top.v:441.11-453.6|lvds_tx.v:224.30-224.50|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=lvds_tx_inst.r_phase_count[0] CO=lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[2] I0=lvds_tx_inst.r_phase_count[1] I1=$true +.attr src "top.v:441.11-453.6|lvds_tx.v:224.30-224.50|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFR C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_pulled_SB_DFFR_Q_D Q=lvds_tx_inst.r_pulled R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.pending_load_SB_DFFER_Q_D I3=lvds_tx_inst.frame_boundary O=lvds_tx_inst.r_pulled_SB_DFFR_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O Q=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_pulled I3=i_rst_b O=tx_fifo.rd_addr_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[1] I2=spi_if_ins.o_ioc[0] I3=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_O[1] E=lvds_tx_inst.r_state_SB_DFFER_Q_E Q=lvds_tx_inst.r_state[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_O[0] E=lvds_tx_inst.r_state_SB_DFFER_Q_E Q=lvds_tx_inst.r_state[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100001111 -.gate SB_DFFSR C=lvds_clock D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] I2=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_O[1] I3=lvds_tx_inst.frame_boundary O=lvds_tx_inst.r_state_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:62.2-70.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] O=rx_fifo.full_o_SB_DFFSR_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] I3=lvds_tx_inst.frame_boundary O=lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111111110000000 -.gate SB_LUT4 I0=rx_fifo.full_o I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] I2=lvds_tx_inst.r_state[0] I3=lvds_tx_inst.r_state[1] O=lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101000000010 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O[0] I2=rx_fifo.full_o_SB_LUT4_I0_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_sync_count[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[7] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFER_Q_1_D E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_sync_count[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001001 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I3=lvds_tx_inst.r_sync_count[0] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_sync_count[2] I2=$true I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0100000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0] +.attr src "top.v:441.11-453.6|lvds_tx.v:131.78-131.97|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000100010100 +.gate SB_LUT4 I0=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[1] I2=lvds_tx_inst.r_state[0] I3=lvds_tx_inst.r_state[1] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[31] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011001101011010 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110011001110 +.gate SB_LUT4 I0=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[1] I2=lvds_tx_inst.r_state[0] I3=lvds_tx_inst.r_state[1] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[14] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000110000000101 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110011001110 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[14] I1=tx_fifo.rd_data_o[14] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[8] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[7] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[30] I1=tx_fifo.rd_data_o[30] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[30] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[29] I1=tx_fifo.rd_data_o[29] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[29] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[20] I1=tx_fifo.rd_data_o[20] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[20] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[19] I1=tx_fifo.rd_data_o[19] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[19] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[18] I1=tx_fifo.rd_data_o[18] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[18] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[3] I1=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[17] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[17] I1=tx_fifo.rd_data_o[17] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[16] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 I0=$false I1=rx_fifo.wr_addr[2] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[16] I1=tx_fifo.rd_data_o[16] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[15] I1=tx_fifo.rd_data_o[15] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[15] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[13] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[3] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[13] I1=tx_fifo.rd_data_o[13] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[12] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[12] I1=tx_fifo.rd_data_o[12] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[4] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=rx_fifo.wr_addr[2] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.mem_i.0.0_WCLKE I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] O=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[11] I1=tx_fifo.rd_data_o[11] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[11] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110000000000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[1] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] O=rx_fifo.full_o_SB_LUT4_I0_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[10] I1=tx_fifo.rd_data_o[10] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[10] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001001 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.wr_addr[1] I2=rx_fifo.rd_addr_gray_wr_r[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.full_o_SB_LUT4_I0_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[28] I1=tx_fifo.rd_data_o[28] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[28] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=rx_fifo.full_o_SB_LUT4_I1_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[9] I1=tx_fifo.rd_data_o[9] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I1_O E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[8] I1=tx_fifo.rd_data_o[8] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[7] I1=tx_fifo.rd_data_o[7] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I3[3] O=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[6] I1=tx_fifo.rd_data_o[6] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o I3=rx_fifo.full_o_SB_LUT4_I2_I3[1] O=rx_fifo.full_o_SB_LUT4_I2_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[5] I1=tx_fifo.rd_data_o[5] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_I3[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[4] I1=tx_fifo.rd_data_o[4] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111101100000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] O=rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[3] I1=tx_fifo.rd_data_o[3] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] Q=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[2] I1=tx_fifo.rd_data_o[2] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[1] I1=tx_fifo.rd_data_o[1] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=tx_fifo.rd_data_o[0] I1=lvds_tx_inst.r_fifo_data[0] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010110000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[27] I1=tx_fifo.rd_data_o[27] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[27] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_state[0] I2=lvds_tx_inst.r_state[1] I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[26] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100010000010 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[26] I1=tx_fifo.rd_data_o[26] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[25] I1=tx_fifo.rd_data_o[25] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[25] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_CARRY CI=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 CO=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q_SB_LUT4_I1_I3 I0=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1] I1=$true -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFER C=lvds_clock D=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_D E=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O Q=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[24] I1=tx_fifo.rd_data_o[24] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[24] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0] I1=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[23] I1=tx_fifo.rd_data_o[23] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[23] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111000001010000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0] I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[22] I1=tx_fifo.rd_data_o[22] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[22] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] I1=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I2=$true I3=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q_SB_LUT4_I1_I3 O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[21] I1=tx_fifo.rd_data_o[21] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O[21] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001000101000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[31] I1=tx_fifo.rd_data_o[31] I2=lvds_tx_inst.pending_load I3=lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_sync_count[0] I1=lvds_tx_inst.r_sync_count[1] I2=lvds_tx_inst.r_sync_count[2] I3=lvds_tx_inst.r_sync_count[3] O=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" -.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx -.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000001 +.gate SB_CARRY CI=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] CO=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] I0=lvds_tx_inst.r_sync_count[2] I1=$true +.attr src "top.v:441.11-453.6|lvds_tx.v:131.78-131.97|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=lvds_tx_inst.r_sync_count[0] CO=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[2] I0=lvds_tx_inst.r_sync_count[1] I1=$true +.attr src "top.v:441.11-453.6|lvds_tx.v:131.78-131.97|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFFES C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFES_Q_D E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_sync_count[3] S=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" +.gate SB_DFFES C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.r_sync_count_SB_DFFES_Q_1_D E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.r_sync_count[1] S=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" +.gate SB_LUT4 I0=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_sync_count[1] I2=$true I3=lvds_tx_inst.r_sync_count[0] O=lvds_tx_inst.r_sync_count_SB_DFFES_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:131.78-131.97|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110101110111110 +.gate SB_LUT4 I0=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I1=lvds_tx_inst.r_sync_count[3] I2=$true I3=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[3] O=lvds_tx_inst.r_sync_count_SB_DFFES_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:131.78-131.97|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110101110111110 +.gate SB_DFFR C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.tx_state_d2 Q=lvds_tx_inst.r_tx_state_q R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_tx_state_q I2=lvds_tx_inst.tx_state_d2 I3=lvds_tx_inst.sent_first_sync O=lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111001100000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[3] I2=lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] I3=lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[2] O=lvds_tx_inst.sent_first_sync_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111111111000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.sent_first_sync_SB_DFFER_Q_D E=lvds_tx_inst.frame_boundary Q=lvds_tx_inst.sent_first_sync R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] I1=lvds_tx_inst.sent_first_sync I2=lvds_tx_inst.r_state[0] I3=lvds_tx_inst.r_state[1] O=lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101011111100 +.gate SB_LUT4 I0=lvds_tx_inst.r_gap_frame_count[0] I1=lvds_tx_inst.r_gap_frame_count[1] I2=lvds_tx_inst.r_gap_frame_count[2] I3=lvds_tx_inst.r_gap_frame_count[3] O=lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000001 +.gate SB_LUT4 I0=lvds_tx_inst.fifo_empty_d2 I1=lvds_tx_inst.tx_state_d2 I2=lvds_tx_inst.sent_first_sync I3=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[3] O=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1011111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_state[0] I3=lvds_tx_inst.r_state[1] O=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=lvds_tx_inst.r_state[0] I1=lvds_tx_inst.r_state[1] I2=lvds_tx_inst.fifo_empty_d2 I3=lvds_tx_inst.tx_state_d2 O=lvds_tx_inst.sent_first_sync_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001011100010001 +.gate SB_DFFR C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.i_tx_state Q=lvds_tx_inst.tx_state_d1 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:50.5-53.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFR C=lvds_rx_09_inst.i_ddr_clk D=lvds_tx_inst.tx_state_d1 Q=lvds_tx_inst.tx_state_d2 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:441.11-453.6|lvds_tx.v:50.5-53.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate $_TBUF_ A=spi_if_ins.spi.o_spi_miso E=i_ss_SB_LUT4_I3_O Y=o_miso +.attr src "top.v:152.19-152.43" +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=w_smi_read_req I3=smi_ctrl_ins.r_dir O=o_smi_read_req +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000000110011 +.gate SB_DFFSR C=i_glob_clock D=r_counter_SB_DFFSR_Q_D Q=r_counter R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=r_counter O=r_counter_SB_DFFSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[7] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[6] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[5] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[4] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[3] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[2] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[1] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_glob_clock D=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[0] E=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O Q=r_tx_data[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:225.3-239.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFSR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.full_o_SB_DFFSR_Q_D Q=rx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:62.2-70.5|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] O=rx_fifo.full_o_SB_DFFSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111110000000 +.gate SB_LUT4 I0=rx_fifo.wr_en_i I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.rd_addr_gray_wr_r[9] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100001010000001 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[3] I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[7] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] I1=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] I2=rx_fifo.rd_addr_gray_wr_r[6] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001100010000001 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] I3=rx_fifo.wr_addr[1] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000100101000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[0] I3=rx_fifo.rd_addr_gray_wr_r[0] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010001000001 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o I3=lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[2] O=lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.full_o I3=lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[1] O=lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] I2=rx_fifo.rd_addr_gray_wr_r[9] I3=rx_fifo.full_o O=rx_fifo.full_o_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=rx_fifo.wr_en_i I1=rx_fifo.full_o_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_gray_wr_r[8] I3=rx_fifo.full_o_SB_LUT4_I3_O[3] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000100000000 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I1=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[1] I2=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] I3=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] I1=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] I2=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] I3=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] I1=rx_fifo.rd_addr_gray_wr_r[1] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] I3=rx_fifo.rd_addr_gray_wr_r[7] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] I2=rx_fifo.rd_addr_gray_wr_r[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[5] I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr[0] I2=rx_fifo.rd_addr_gray_wr_r[0] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] O=rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=rx_fifo.full_o_SB_LUT4_I3_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[16] RDATA[2]=rx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[18] RDATA[6]=rx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[17] RDATA[10]=rx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[19] RDATA[14]=rx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[16] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[18] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[17] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[19] WDATA[14]=$undef WDATA[15]=$undef WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1382,33 +1647,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=rx_fifo.mem_i.0.0_WCLKE O=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] I2=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2] O=rx_fifo.mem_i.0.0_WCLKE -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111110000110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA_1 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[20] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[22] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[21] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[23] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[19] I2=lvds_rx_09_inst.o_fifo_data[19] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.0_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[20] RDATA[2]=rx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[22] RDATA[6]=rx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[21] RDATA[10]=rx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[23] RDATA[14]=rx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1427,25 +1668,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[21] I2=lvds_rx_09_inst.o_fifo_data[21] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[22] I2=lvds_rx_09_inst.o_fifo_data[22] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[20] I2=lvds_rx_09_inst.o_fifo_data[20] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[23] I2=lvds_rx_24_inst.o_fifo_data[23] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.1_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[24] RDATA[2]=rx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[26] RDATA[6]=rx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[25] RDATA[10]=rx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[27] RDATA[14]=rx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[24] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[26] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[25] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[27] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1464,25 +1689,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[25] I2=lvds_rx_09_inst.o_fifo_data[25] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA_1 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[28] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[30] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[29] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[31] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[24] I2=lvds_rx_09_inst.o_fifo_data[24] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[27] I2=lvds_rx_09_inst.o_fifo_data[27] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.2_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[28] RDATA[2]=rx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[30] RDATA[6]=rx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[29] RDATA[10]=rx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[31] RDATA[14]=rx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_i.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_i.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_i.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_i.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1501,25 +1710,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[29] I2=lvds_rx_09_inst.o_fifo_data[29] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[28] I2=lvds_rx_24_inst.o_fifo_data[28] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[31] I2=lvds_rx_24_inst.o_fifo_data[31] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_i.0.3_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.0_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.0_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.0_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.0_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[0] RDATA[2]=rx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[2] RDATA[6]=rx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[1] RDATA[10]=rx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[3] RDATA[14]=rx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[0] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[2] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[1] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[3] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1538,25 +1731,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[1] I2=lvds_rx_09_inst.o_fifo_data[1] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA_1 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[4] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[6] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[5] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[7] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[2] I2=lvds_rx_09_inst.o_fifo_data[2] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[0] I2=lvds_rx_09_inst.o_fifo_data[0] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.0_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[4] RDATA[2]=rx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[6] RDATA[6]=rx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[5] RDATA[10]=rx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[7] RDATA[14]=rx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.1_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.1_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.1_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.1_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1575,25 +1752,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[5] I2=lvds_rx_09_inst.o_fifo_data[5] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA_1 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[4] I2=lvds_rx_24_inst.o_fifo_data[4] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[7] I2=lvds_rx_09_inst.o_fifo_data[7] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.1_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.2_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.2_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.2_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.2_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[8] RDATA[2]=rx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[10] RDATA[6]=rx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[9] RDATA[10]=rx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[11] RDATA[14]=rx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[8] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[10] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[9] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[11] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1612,25 +1773,9 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA_1 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=rx_fifo.rd_en_i RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_rx_09_inst.i_ddr_clk WCLKE=rx_fifo.wr_en_i WDATA[0]=$undef WDATA[1]=rx_fifo.wr_data_i[12] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=rx_fifo.wr_data_i[14] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=rx_fifo.wr_data_i[13] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=rx_fifo.wr_data_i[15] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[10] I2=lvds_rx_09_inst.o_fifo_data[10] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[8] I2=lvds_rx_09_inst.o_fifo_data[8] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA_3 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[11] I2=lvds_rx_09_inst.o_fifo_data[11] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.2_WDATA -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_RAM40_4K MASK[0]=$false MASK[1]=$false MASK[2]=$false MASK[3]=$false MASK[4]=$false MASK[5]=$false MASK[6]=$false MASK[7]=$false MASK[8]=$false MASK[9]=$false MASK[10]=$false MASK[11]=$false MASK[12]=$false MASK[13]=$false MASK[14]=$false MASK[15]=$false RADDR[0]=rx_fifo.rd_addr[2] RADDR[1]=rx_fifo.rd_addr[3] RADDR[2]=rx_fifo.rd_addr[4] RADDR[3]=rx_fifo.rd_addr[5] RADDR[4]=rx_fifo.rd_addr[6] RADDR[5]=rx_fifo.rd_addr[7] RADDR[6]=rx_fifo.rd_addr[8] RADDR[7]=rx_fifo.rd_addr_gray[9] RADDR[8]=rx_fifo.rd_addr[1] RADDR[9]=rx_fifo.rd_addr[0] RADDR[10]=$false RCLK=r_counter RCLKE=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O RDATA[0]=rx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=rx_fifo.rd_data_o[12] RDATA[2]=rx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=rx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=rx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=rx_fifo.rd_data_o[14] RDATA[6]=rx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=rx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=rx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=rx_fifo.rd_data_o[13] RDATA[10]=rx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=rx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=rx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=rx_fifo.rd_data_o[15] RDATA[14]=rx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=rx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=rx_fifo.wr_addr[2] WADDR[1]=rx_fifo.wr_addr[3] WADDR[2]=rx_fifo.wr_addr[4] WADDR[3]=rx_fifo.wr_addr[5] WADDR[4]=rx_fifo.wr_addr[6] WADDR[5]=rx_fifo.wr_addr[7] WADDR[6]=rx_fifo.wr_addr[8] WADDR[7]=rx_fifo.wr_addr_gray[9] WADDR[8]=rx_fifo.wr_addr[1] WADDR[9]=rx_fifo.wr_addr[0] WADDR[10]=$false WCLK=lvds_clock WCLKE=rx_fifo.mem_i.0.0_WCLKE WDATA[0]=$false WDATA[1]=rx_fifo.mem_q.0.3_WDATA_3 WDATA[2]=$false WDATA[3]=$false WDATA[4]=$false WDATA[5]=rx_fifo.mem_q.0.3_WDATA_2 WDATA[6]=$false WDATA[7]=$false WDATA[8]=$false WDATA[9]=rx_fifo.mem_q.0.3_WDATA_1 WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=rx_fifo.mem_q.0.3_WDATA WDATA[14]=$false WDATA[15]=$false WE=$true -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" .param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx @@ -1649,2600 +1794,3555 @@ .param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx .param READ_MODE 10 .param WRITE_MODE 10 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[13] I2=lvds_rx_09_inst.o_fifo_data[13] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA_1 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[14] I2=lvds_rx_09_inst.o_fifo_data[14] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA_2 -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA_3 +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111000011001100 -.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_data[15] I2=lvds_rx_09_inst.o_fifo_data[15] I3=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] O=rx_fifo.mem_q.0.3_WDATA +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[6] I1=rx_fifo.wr_addr_gray_rd_r[4] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001001000001 -.gate SB_LUT4 I0=$false I1=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[2] I1=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[4] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[5] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[6] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[7] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=rx_fifo.rd_addr[8] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[3] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[5] I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] I3=rx_fifo.wr_addr_gray_rd_r[6] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.rd_addr[2] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.rd_addr[1] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_SB_DFFESR_Q_8_D +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] I1=rx_fifo.wr_addr_gray_rd_r[4] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001010001000001 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[2] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[7] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] I1=rx_fifo.wr_addr_gray_rd_r[9] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=rx_fifo.rd_en_i O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000100000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=rx_fifo.wr_addr_gray_rd_r[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[0] I2=rx_fifo.wr_addr_gray_rd_r[0] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.rd_addr_SB_DFFESR_Q_E Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[0] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] O=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray[9] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr[1] I2=rx_fifo.wr_addr_gray_rd_r[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000010100 -.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[8] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] I0=$false I1=rx_fifo.rd_addr[8] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=rx_fifo.rd_addr[7] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=rx_fifo.rd_addr[6] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=rx_fifo.rd_addr[5] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=rx_fifo.rd_addr[4] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=rx_fifo.rd_addr[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=rx_fifo.rd_addr[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.rd_addr[0] CO=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=rx_fifo.rd_addr[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[8] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[7] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[6] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O Q=rx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[5] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[1] O=rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[4] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[3] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[8] Q=rx_fifo.rd_addr_gray_wr[8] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[7] Q=rx_fifo.rd_addr_gray_wr[7] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[1] I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[6] Q=rx_fifo.rd_addr_gray_wr[6] +.attr src "top.v:420.5-433.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.rd_addr[0] O=rx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[5] Q=rx_fifo.rd_addr_gray_wr[5] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[9] Q=rx_fifo.rd_addr_gray_wr[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[4] Q=rx_fifo.rd_addr_gray_wr[4] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[8] Q=rx_fifo.rd_addr_gray_wr[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[3] Q=rx_fifo.rd_addr_gray_wr[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[7] Q=rx_fifo.rd_addr_gray_wr[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[2] Q=rx_fifo.rd_addr_gray_wr[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[6] Q=rx_fifo.rd_addr_gray_wr[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[1] Q=rx_fifo.rd_addr_gray_wr[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[5] Q=rx_fifo.rd_addr_gray_wr[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray[0] Q=rx_fifo.rd_addr_gray_wr[0] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[4] Q=rx_fifo.rd_addr_gray_wr[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[9] Q=rx_fifo.rd_addr_gray_wr_r[9] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[3] Q=rx_fifo.rd_addr_gray_wr[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[8] Q=rx_fifo.rd_addr_gray_wr_r[8] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[2] Q=rx_fifo.rd_addr_gray_wr[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[7] Q=rx_fifo.rd_addr_gray_wr_r[7] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[1] Q=rx_fifo.rd_addr_gray_wr[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[6] Q=rx_fifo.rd_addr_gray_wr_r[6] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray[0] Q=rx_fifo.rd_addr_gray_wr[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[5] Q=rx_fifo.rd_addr_gray_wr_r[5] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[9] Q=rx_fifo.rd_addr_gray_wr_r[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[4] Q=rx_fifo.rd_addr_gray_wr_r[4] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[8] Q=rx_fifo.rd_addr_gray_wr_r[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[3] Q=rx_fifo.rd_addr_gray_wr_r[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[7] Q=rx_fifo.rd_addr_gray_wr_r[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[2] Q=rx_fifo.rd_addr_gray_wr_r[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[6] Q=rx_fifo.rd_addr_gray_wr_r[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[1] Q=rx_fifo.rd_addr_gray_wr_r[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[5] Q=rx_fifo.rd_addr_gray_wr_r[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFF C=lvds_clock D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0] +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[4] Q=rx_fifo.rd_addr_gray_wr_r[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[3] Q=rx_fifo.rd_addr_gray_wr_r[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[2] Q=rx_fifo.rd_addr_gray_wr_r[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[1] Q=rx_fifo.rd_addr_gray_wr_r[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.rd_addr_gray_wr[0] Q=rx_fifo.rd_addr_gray_wr_r[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_en_i I3=i_rst_b O=rx_fifo.rd_addr_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_pull_1 I2=w_smi_read_req I3=smi_ctrl_ins.r_fifo_pull O=rx_fifo.rd_en_i .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_8_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_8_D +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=rx_fifo.wr_addr[8] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3 I0=$false I1=rx_fifo.wr_addr[7] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[6] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[5] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[4] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[3] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[2] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=rx_fifo.wr_addr[1] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[9] I1=rx_fifo.rd_addr_gray_wr_r[0] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[3] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.full_o_SB_LUT4_I3_O[1] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[5] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001100110001 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[6] I1=rx_fifo.rd_addr_gray_wr_r[4] I2=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2] +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[6] I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010001011110011 -.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_wr_r[8] I1=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000011101011 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_wr_r[2] I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.wr_addr_SB_DFFESR_Q_E Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[0] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[3] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] O=rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray[9] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr_gray_wr_r[4] I3=rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] I0=$false I1=rx_fifo.wr_addr[8] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] I0=$false I1=rx_fifo.wr_addr[7] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] I0=$false I1=rx_fifo.wr_addr[6] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] I0=$false I1=rx_fifo.wr_addr[5] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] I0=$false I1=rx_fifo.wr_addr[4] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] I0=$false I1=rx_fifo.wr_addr[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] I0=$false I1=rx_fifo.wr_addr[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr[0] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] I0=$false I1=rx_fifo.wr_addr[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[8] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[7] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[6] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[5] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[4] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[3] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[2] I3=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=lvds_clock D=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O Q=rx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr[1] I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[1] O=rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D +.attr src "top.v:420.5-433.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=rx_fifo.wr_addr[0] O=rx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=rx_fifo.wr_addr[8] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=rx_fifo.wr_addr[7] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=rx_fifo.wr_addr[6] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=rx_fifo.wr_addr[5] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=rx_fifo.wr_addr[4] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=rx_fifo.wr_addr[3] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=rx_fifo.wr_addr[1] CO=rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=rx_fifo.wr_addr[2] +.attr src "top.v:420.5-433.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[9] Q=rx_fifo.wr_addr_gray_rd[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[8] Q=rx_fifo.wr_addr_gray_rd[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[7] Q=rx_fifo.wr_addr_gray_rd[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[6] Q=rx_fifo.wr_addr_gray_rd[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[5] Q=rx_fifo.wr_addr_gray_rd[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[4] Q=rx_fifo.wr_addr_gray_rd[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[3] Q=rx_fifo.wr_addr_gray_rd[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[2] Q=rx_fifo.wr_addr_gray_rd[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[1] Q=rx_fifo.wr_addr_gray_rd[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray[0] Q=rx_fifo.wr_addr_gray_rd[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[9] Q=rx_fifo.wr_addr_gray_rd_r[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[8] Q=rx_fifo.wr_addr_gray_rd_r[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[7] Q=rx_fifo.wr_addr_gray_rd_r[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[6] Q=rx_fifo.wr_addr_gray_rd_r[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[5] Q=rx_fifo.wr_addr_gray_rd_r[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[4] Q=rx_fifo.wr_addr_gray_rd_r[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[3] Q=rx_fifo.wr_addr_gray_rd_r[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[2] Q=rx_fifo.wr_addr_gray_rd_r[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[1] Q=rx_fifo.wr_addr_gray_rd_r[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=rx_fifo.wr_addr_gray_rd[0] Q=rx_fifo.wr_addr_gray_rd_r[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=r_counter D=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=smi_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.attr src "top.v:420.5-433.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[31] I2=lvds_rx_24_inst.o_fifo_data[31] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[31] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=smi_ctrl_ins.i_cs_SB_DFFESR_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[30] I2=lvds_rx_24_inst.o_fifo_data[30] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[30] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D Q=smi_ctrl_ins.int_cnt_rx[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[21] I2=lvds_rx_24_inst.o_fifo_data[21] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[21] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" -.gate SB_DFFNSR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D Q=smi_ctrl_ins.int_cnt_rx[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[20] I2=lvds_rx_24_inst.o_fifo_data[20] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[20] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[19] I2=lvds_rx_24_inst.o_fifo_data[19] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[19] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[18] I2=lvds_rx_24_inst.o_fifo_data[18] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[18] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0] E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[2] R=o_led0_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[17] I2=lvds_rx_24_inst.o_fifo_data[17] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[17] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.full_o E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[1] R=o_led0_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[16] I2=lvds_rx_24_inst.o_fifo_data[16] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[16] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESS C=r_counter D=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_D E=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E Q=smi_ctrl_ins.o_data_out[0] S=o_led0_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[15] I2=lvds_rx_24_inst.o_fifo_data[15] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[15] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_smi_read_req O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[14] I2=lvds_rx_24_inst.o_fifo_data[14] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[14] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] I3=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[13] I2=lvds_rx_24_inst.o_fifo_data[13] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[13] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=i_rst_b I1=smi_ctrl_ins.i_cs I2=spi_if_ins.o_ioc[1] I3=spi_if_ins.o_fetch_cmd O=smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[12] I2=lvds_rx_24_inst.o_fifo_data[12] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[12] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_LUT4 I0=io_ctrl_ins.o_data_out[2] I1=smi_ctrl_ins.o_data_out[2] I2=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[29] I2=lvds_rx_24_inst.o_fifo_data[29] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[29] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001010100111111 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[7] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[11] I2=lvds_rx_24_inst.o_fifo_data[11] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[11] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[6] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[10] I2=lvds_rx_24_inst.o_fifo_data[10] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[10] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[9] I2=lvds_rx_24_inst.o_fifo_data[9] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[14] I1=smi_ctrl_ins.r_fifo_pulled_data[6] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[8] I2=lvds_rx_24_inst.o_fifo_data[8] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101000001100 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[30] I1=smi_ctrl_ins.r_fifo_pulled_data[22] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[7] I2=lvds_rx_24_inst.o_fifo_data[7] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[5] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[6] I2=lvds_rx_24_inst.o_fifo_data[6] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[5] I2=lvds_rx_24_inst.o_fifo_data[5] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[13] I1=smi_ctrl_ins.r_fifo_pulled_data[5] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[4] I2=lvds_rx_24_inst.o_fifo_data[4] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101000001100 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[29] I1=smi_ctrl_ins.r_fifo_pulled_data[21] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[3] I2=lvds_rx_24_inst.o_fifo_data[3] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[4] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[2] I2=lvds_rx_24_inst.o_fifo_data[2] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[28] I2=lvds_rx_24_inst.o_fifo_data[28] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[28] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[12] I1=smi_ctrl_ins.r_fifo_pulled_data[4] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[1] I2=lvds_rx_24_inst.o_fifo_data[1] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[0] I2=lvds_rx_24_inst.o_fifo_data[0] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101000001100 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[28] I1=smi_ctrl_ins.r_fifo_pulled_data[20] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[27] I2=lvds_rx_24_inst.o_fifo_data[27] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[27] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[26] I2=lvds_rx_24_inst.o_fifo_data[26] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[26] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[25] I2=lvds_rx_24_inst.o_fifo_data[25] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[25] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[11] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.r_fifo_pulled_data[3] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[24] I2=lvds_rx_24_inst.o_fifo_data[24] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[24] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010001000110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[27] I1=smi_ctrl_ins.r_fifo_pulled_data[19] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[23] I2=lvds_rx_24_inst.o_fifo_data[23] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[23] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.o_fifo_data[22] I2=lvds_rx_24_inst.o_fifo_data[22] I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_data_i[22] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_en_i I3=i_rst_b O=rx_fifo.wr_addr_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[10] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[2] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.o_fifo_push I2=lvds_rx_09_inst.o_fifo_push I3=smi_ctrl_ins.r_channel O=rx_fifo.wr_en_i .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010001100100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[26] I1=smi_ctrl_ins.r_fifo_pulled_data[18] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100110011110000 +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.byte_ix_SB_DFFR_Q_D Q=smi_ctrl_ins.byte_ix[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[1] +.attr src "/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.byte_ix_SB_DFFR_Q_1_D Q=smi_ctrl_ins.byte_ix[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D +.attr src "/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=smi_ctrl_ins.d_byte[7] I1=smi_ctrl_ins.byte_ix[0] I2=smi_ctrl_ins.byte_ix[2] I3=smi_ctrl_ins.swe_edge O=smi_ctrl_ins.byte_ix_SB_DFFR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[9] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000100011110000 +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.byte_ix_SB_DFFR_Q_2_D Q=smi_ctrl_ins.byte_ix[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010001100100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[25] I1=smi_ctrl_ins.r_fifo_pulled_data[17] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=smi_ctrl_ins.d_byte[7] I1=smi_ctrl_ins.byte_ix[2] I2=smi_ctrl_ins.byte_ix[1] I3=smi_ctrl_ins.swe_edge O=smi_ctrl_ins.byte_ix_SB_DFFR_Q_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D E=i_rst_b Q=smi_ctrl_ins.o_smi_data_out[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100010011110000 +.gate SB_LUT4 I0=smi_ctrl_ins.d_byte[7] I1=smi_ctrl_ins.byte_ix[1] I2=smi_ctrl_ins.byte_ix[3] I3=smi_ctrl_ins.swe_edge O=smi_ctrl_ins.byte_ix_SB_DFFR_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100010011110000 +.gate SB_DFFS C=r_counter D=smi_ctrl_ins.byte_ix_SB_DFFS_Q_D Q=smi_ctrl_ins.byte_ix[0] S=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[8] I1=smi_ctrl_ins.int_cnt_rx[4] I2=smi_ctrl_ins.int_cnt_rx[3] I3=smi_ctrl_ins.r_fifo_pulled_data[0] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" +.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.swe_edge I2=smi_ctrl_ins.byte_ix[3] I3=smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[2] O=smi_ctrl_ins.byte_ix_SB_DFFS_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010001100100000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[24] I1=smi_ctrl_ins.r_fifo_pulled_data[16] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[0] I1=smi_ctrl_ins.byte_ix[0] I2=smi_ctrl_ins.swe_edge I3=smi_ctrl_ins.d_byte[7] O=smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1010001100110011 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.byte_ix[1] I3=smi_ctrl_ins.byte_ix[2] O=smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[15] I1=smi_ctrl_ins.r_fifo_pulled_data[7] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000000000001111 +.gate SB_LUT4 I0=smi_ctrl_ins.frame_sr[23] I1=smi_ctrl_ins.frame_sr[15] I2=smi_ctrl_ins.byte_ix[3] I3=smi_ctrl_ins.frame_sr[7] O=smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000101000001100 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[31] I1=smi_ctrl_ins.r_fifo_pulled_data[23] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001000000000000 +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[7] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010000011000000 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[6] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:59.5-102.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_load_cmd I2=spi_if_ins.o_fetch_cmd I3=o_led1_SB_LUT4_I1_I2[2] O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[5] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000000000 -.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[4] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:142.5-151.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.r_fifo_pull_1 I2=w_smi_read_req I3=smi_ctrl_ins.r_fifo_pull O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[3] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O O=smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[2] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_pull_trigger Q=smi_ctrl_ins.r_fifo_pull R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[1] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:142.5-151.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[31] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[31] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=smi_ctrl_ins.d_q3[0] E=smi_ctrl_ins.swe_edge Q=smi_ctrl_ins.d_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[30] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[30] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[7] Q=smi_ctrl_ins.d_q1[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[21] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[21] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[6] Q=smi_ctrl_ins.d_q1[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[20] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[20] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[5] Q=smi_ctrl_ins.d_q1[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[19] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[19] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[4] Q=smi_ctrl_ins.d_q1[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[18] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[18] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[3] Q=smi_ctrl_ins.d_q1[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[17] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[17] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[2] Q=smi_ctrl_ins.d_q1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[16] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[16] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[1] Q=smi_ctrl_ins.d_q1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[15] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[15] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.i_smi_data_in[0] Q=smi_ctrl_ins.d_q1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[14] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[14] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[7] Q=smi_ctrl_ins.d_q2[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[13] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[13] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[6] Q=smi_ctrl_ins.d_q2[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[12] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[12] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[5] Q=smi_ctrl_ins.d_q2[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[29] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[29] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[4] Q=smi_ctrl_ins.d_q2[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[11] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[11] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[3] Q=smi_ctrl_ins.d_q2[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[10] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[10] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[2] Q=smi_ctrl_ins.d_q2[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[9] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[9] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[1] Q=smi_ctrl_ins.d_q2[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[8] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q1[0] Q=smi_ctrl_ins.d_q2[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[7] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[7] Q=smi_ctrl_ins.d_q3[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[6] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[6] Q=smi_ctrl_ins.d_q3[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[5] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[5] Q=smi_ctrl_ins.d_q3[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[4] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[4] Q=smi_ctrl_ins.d_q3[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[3] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[3] Q=smi_ctrl_ins.d_q3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[2] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[2] Q=smi_ctrl_ins.d_q3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[28] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[28] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[1] Q=smi_ctrl_ins.d_q3[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[1] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=r_counter D=smi_ctrl_ins.d_q2[0] Q=smi_ctrl_ins.d_q3[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[0] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:176.1-181.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[7] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E Q=smi_ctrl_ins.frame_sr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[27] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[27] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[4] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E Q=smi_ctrl_ins.frame_sr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[26] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[26] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[3] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[11] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[25] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[25] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[2] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[10] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[24] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[24] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[1] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[23] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[23] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[0] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[22] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[22] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[7] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[23] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.r_fifo_push Q=smi_ctrl_ins.r_fifo_push_1 R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[6] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[22] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:260.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=smi_ctrl_ins.r_fifo_push I3=smi_ctrl_ins.r_fifo_push_1 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[5] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[21] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000110000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[4] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[20] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr[2] I2=tx_fifo.rd_addr_gray_wr_r[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[3] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[19] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[8] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[2] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[18] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001010111110 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[3] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E Q=smi_ctrl_ins.frame_sr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[1] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[17] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[0] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E Q=smi_ctrl_ins.frame_sr[16] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[8] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[7] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[6] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[5] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[4] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[3] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[2] -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.swe_edge I3=smi_ctrl_ins.byte_ix[1] O=smi_ctrl_ins.frame_sr_SB_DFFER_Q_21_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[2] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E Q=smi_ctrl_ins.frame_sr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[1] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E Q=smi_ctrl_ins.frame_sr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[0] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E Q=smi_ctrl_ins.frame_sr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[4] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[7] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[15] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[6] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[14] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[5] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[13] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[4] E=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E Q=smi_ctrl_ins.frame_sr[12] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.swe_edge I3=smi_ctrl_ins.byte_ix[2] O=smi_ctrl_ins.frame_sr_SB_DFFER_Q_9_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.swe_edge I3=smi_ctrl_ins.byte_ix[0] O=smi_ctrl_ins.frame_sr_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:66.24-66.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[5] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] O=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D[6] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=smi_ctrl_ins.i_cs R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_DFFSR C=r_counter D=smi_ctrl_ins.w_fifo_push_trigger Q=smi_ctrl_ins.r_fifo_push R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_D[1] Q=smi_ctrl_ins.int_cnt_rx[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_1_D[0] Q=smi_ctrl_ins.int_cnt_rx[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_1_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:260.5-269.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=$false I2=i_smi_soe_se I3=i_rst_b O=smi_ctrl_ins.soe_and_reset +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_smi_swe_srw I3=i_rst_b O=smi_ctrl_ins.swe_and_reset +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.o_data_out_SB_DFFER_Q_D E=smi_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=smi_ctrl_ins.o_data_out[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:57.5-87.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.o_data_out_SB_DFFER_Q_1_D E=smi_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=smi_ctrl_ins.o_data_out[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "top.v:547.12-578.4|smi_ctrl.v:57.5-87.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=smi_ctrl_ins.r_channel O=smi_ctrl_ins.o_data_out_SB_DFFER_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D Q=smi_ctrl_ins.tx_reg_state[3] +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.o_data_out_SB_DFFER_Q_2_D E=smi_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=smi_ctrl_ins.o_data_out[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:57.5-87.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=tx_fifo.full_o O=smi_ctrl_ins.o_data_out_SB_DFFER_Q_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_1_D Q=smi_ctrl_ins.tx_reg_state[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.o_data_out_SB_DFFER_Q_3_D E=smi_ctrl_ins.o_data_out_SB_DFFER_Q_E Q=smi_ctrl_ins.o_data_out[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_1_D +.attr src "top.v:547.12-578.4|smi_ctrl.v:57.5-87.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[0] I2=w_smi_read_req I3=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] O=smi_ctrl_ins.o_data_out_SB_DFFER_Q_3_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D Q=smi_ctrl_ins.tx_reg_state[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] I3=smi_ctrl_ins.r_dir O=smi_ctrl_ins.o_data_out_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=smi_ctrl_ins.o_data_out_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[7] Q=smi_ctrl_ins.o_smi_data_out[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[6] Q=smi_ctrl_ins.o_smi_data_out[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[5] Q=smi_ctrl_ins.o_smi_data_out[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[4] Q=smi_ctrl_ins.o_smi_data_out[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[3] Q=smi_ctrl_ins.o_smi_data_out[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[2] Q=smi_ctrl_ins.o_smi_data_out[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[1] Q=smi_ctrl_ins.o_smi_data_out[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[0] Q=smi_ctrl_ins.o_smi_data_out[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[7] I1=smi_ctrl_ins.r_fifo_pulled_data[15] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[6] I1=smi_ctrl_ins.r_fifo_pulled_data[14] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[22] I1=smi_ctrl_ins.r_fifo_pulled_data[30] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[5] I1=smi_ctrl_ins.r_fifo_pulled_data[13] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[21] I1=smi_ctrl_ins.r_fifo_pulled_data[29] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[4] I1=smi_ctrl_ins.r_fifo_pulled_data[12] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[20] I1=smi_ctrl_ins.r_fifo_pulled_data[28] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[3] I1=smi_ctrl_ins.r_fifo_pulled_data[11] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[19] I1=smi_ctrl_ins.r_fifo_pulled_data[27] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[2] I1=smi_ctrl_ins.r_fifo_pulled_data[10] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[18] I1=smi_ctrl_ins.r_fifo_pulled_data[26] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[1] I1=smi_ctrl_ins.r_fifo_pulled_data[9] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[17] I1=smi_ctrl_ins.r_fifo_pulled_data[25] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[0] I1=smi_ctrl_ins.r_fifo_pulled_data[8] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[16] I1=smi_ctrl_ins.r_fifo_pulled_data[24] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_pulled_data[23] I1=smi_ctrl_ins.r_fifo_pulled_data[31] I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[4] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[29] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[3] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[28] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[9] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[19] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[8] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[18] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[2] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_2_D +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[22] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[17] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_DFFN C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D Q=smi_ctrl_ins.tx_reg_state[0] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=$true E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[16] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] I3=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[21] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[13] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=i_rst_b I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[3] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[20] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[12] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100000001010 -.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.i_smi_data_in[7] I2=smi_ctrl_ins.tx_reg_state[2] I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1] +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[19] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[11] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011000000 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.i_smi_data_in[7] I3=smi_ctrl_ins.tx_reg_state[1] O=smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[18] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[10] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_DFFNE C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D E=i_rst_b Q=smi_ctrl_ins.w_fifo_pull_trigger +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[17] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:122.5-140.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:4.57-4.103" -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[16] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[2] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[27] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[6] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[5] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[4] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[3] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[2] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[1] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.d_byte[0] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[1] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[26] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[0] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[25] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[14] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[24] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[13] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[23] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[12] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[22] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[11] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[21] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=smi_ctrl_ins.frame_sr[10] E=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O Q=smi_ctrl_ins.o_tx_fifo_pushed_data[20] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.push_pulse_SB_DFFR_Q_D Q=smi_ctrl_ins.push_pulse R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o I3=smi_ctrl_ins.push_req O=smi_ctrl_ins.push_pulse_SB_DFFR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_DFFNSR C=smi_ctrl_ins.swe_and_reset D=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D Q=smi_ctrl_ins.w_fifo_push_trigger R=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.push_pulse I3=i_rst_b O=tx_fifo.wr_addr_SB_DFFESR_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.push_req_SB_DFFR_Q_D Q=smi_ctrl_ins.push_req R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:192.1-257.4|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=smi_ctrl_ins.d_byte[7] I1=smi_ctrl_ins.swe_edge I2=smi_ctrl_ins.byte_ix[0] I3=smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] O=smi_ctrl_ins.push_req_SB_DFFR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000011111111 +.gate SB_LUT4 I0=tx_fifo.full_o I1=smi_ctrl_ins.push_req I2=smi_ctrl_ins.swe_edge I3=smi_ctrl_ins.byte_ix[3] O=smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_channel_SB_DFFER_Q_E Q=smi_ctrl_ins.r_channel R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:57.5-87.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=smi_ctrl_ins.i_cs I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] I3=spi_if_ins.o_load_cmd O=smi_ctrl_ins.r_channel_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=smi_ctrl_ins.r_dir_SB_DFFER_Q_E Q=smi_ctrl_ins.r_dir R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:57.5-87.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=spi_if_ins.o_fetch_cmd I1=smi_ctrl_ins.i_cs I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] I3=spi_if_ins.o_load_cmd O=smi_ctrl_ins.r_dir_SB_DFFER_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000000000000 +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.r_fifo_pull Q=smi_ctrl_ins.r_fifo_pull_1 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:129.5-137.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.w_fifo_pull_trigger Q=smi_ctrl_ins.r_fifo_pull R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:129.5-137.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[31] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[31] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[30] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[30] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "smi_ctrl.v:178.5-258.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:17.59-17.105" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=smi_ctrl_ins.i_smi_data_in[7] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_D +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[21] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[21] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[20] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[20] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[19] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[19] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[18] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[18] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[17] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[17] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[16] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[16] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[15] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[15] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[14] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[14] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[13] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[13] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[12] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[12] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[29] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[29] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[11] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[11] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[10] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[10] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[9] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[9] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[8] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[7] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[6] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[5] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[4] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[3] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[2] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[28] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[28] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[1] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[0] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[27] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[27] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[26] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[26] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[25] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[25] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[24] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[24] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[23] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[23] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_DFFNER C=smi_ctrl_ins.soe_and_reset D=rx_fifo.rd_data_o[22] E=smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNER_Q_E Q=smi_ctrl_ins.r_fifo_pulled_data[22] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:12.63-12.116" +.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=i_smi_soe_se O=smi_ctrl_ins.soe_and_reset +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.d_byte[7] I2=smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[1] I3=smi_ctrl_ins.swe_edge O=smi_ctrl_ins.swe_edge_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.swe_q2 I3=smi_ctrl_ins.swe_q2_d O=smi_ctrl_ins.swe_edge +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=i_smi_swe_srw O=smi_ctrl_ins.swe_in_norm +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=smi_ctrl_ins.tx_reg_state[3] I3=smi_ctrl_ins.tx_reg_state[0] O=smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.swe_in_norm Q=smi_ctrl_ins.swe_q1 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:158.1-168.4|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.swe_q1 Q=smi_ctrl_ins.swe_q2 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:158.1-168.4|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFR C=r_counter D=smi_ctrl_ins.swe_q2 Q=smi_ctrl_ins.swe_q2_d R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:158.1-168.4|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFNR C=smi_ctrl_ins.soe_and_reset D=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNR_Q_D Q=smi_ctrl_ins.w_fifo_pull_trigger R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:547.12-578.4|smi_ctrl.v:106.5-126.8|/usr/bin/../share/yosys/ice40/ff_map.v:7.57-7.103" +.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.int_cnt_rx[4] I3=smi_ctrl_ins.int_cnt_rx[3] O=smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNR_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011001100111111 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[0] D_OUT_0=smi_ctrl_ins.o_smi_data_out[0] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:532.5-537.4" +.attr src "top.v:595.5-600.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[1] D_OUT_0=smi_ctrl_ins.o_smi_data_out[1] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:541.5-546.4" +.attr src "top.v:604.5-609.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[2] D_OUT_0=smi_ctrl_ins.o_smi_data_out[2] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:550.5-555.4" +.attr src "top.v:613.5-618.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[3] D_OUT_0=smi_ctrl_ins.o_smi_data_out[3] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:559.5-564.4" +.attr src "top.v:622.5-627.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[4] D_OUT_0=smi_ctrl_ins.o_smi_data_out[4] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:568.5-573.4" +.attr src "top.v:631.5-636.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[5] D_OUT_0=smi_ctrl_ins.o_smi_data_out[5] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:577.5-582.4" +.attr src "top.v:640.5-645.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_IO CLOCK_ENABLE=$true D_IN_0=w_smi_data_input[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6] +.gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[6] D_OUT_0=smi_ctrl_ins.o_smi_data_out[6] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:586.5-591.4" +.attr src "top.v:649.5-654.4" .param PIN_TYPE 101001 .param PULLUP 0 .gate SB_IO CLOCK_ENABLE=$true D_IN_0=smi_ctrl_ins.i_smi_data_in[7] D_OUT_0=smi_ctrl_ins.o_smi_data_out[7] OUTPUT_ENABLE=smi_ctrl_ins.r_dir PACKAGE_PIN=io_smi_data[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "top.v:595.5-600.4" +.attr src "top.v:658.5-663.4" .param PIN_TYPE 101001 .param PULLUP 0 -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_cs_SB_DFFESR_Q_D[3] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=spi_if_ins.o_cs[3] R=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=spi_if_ins.o_cs_SB_DFFESR_Q_D[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=spi_if_ins.o_cs_SB_DFFESR_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[5] I3=spi_if_ins.spi.o_rx_byte[6] O=spi_if_ins.o_cs_SB_DFFESR_Q_D[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=spi_if_ins.o_cs_SB_DFFESR_Q_D[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.gate SB_LUT4 I0=io_ctrl_ins.i_cs I1=spi_if_ins.o_cs[3] I2=sys_ctrl_ins.i_cs I3=smi_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111111011101000 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000100000000 +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=spi_if_ins.o_cs[3] I2=sys_ctrl_ins.i_cs I3=io_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000010111 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000100000000 +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[4] I1=spi_if_ins.o_cs_SB_LUT4_I1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=io_ctrl_ins.o_data_out[4] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000100 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[2] I1=spi_if_ins.o_cs_SB_LUT4_I1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=io_ctrl_ins.o_data_out[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000010 -.gate SB_DFFER C=r_counter D=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] E=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E Q=spi_if_ins.o_cs_SB_LUT4_I0_3_O[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=sys_ctrl_ins.o_data_out[2] I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[2] I3=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[3] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "sys_ctrl.v:83.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111100011111111 +.gate SB_LUT4 I0=smi_ctrl_ins.o_data_out[1] I1=spi_if_ins.o_cs_SB_LUT4_I1_O[1] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=io_ctrl_ins.o_data_out[1] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=sys_ctrl_ins.o_data_out[1] I3=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=sys_ctrl_ins.o_data_out[4] I3=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0] I3=r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_D[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=$false I1=smi_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I1_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_cs[3] I1=smi_ctrl_ins.i_cs I2=io_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011111100000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[0] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I3_O[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=sys_ctrl_ins.o_data_out[0] I3=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=sys_ctrl_ins.o_data_out[7] I3=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=sys_ctrl_ins.o_data_out[6] I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=io_ctrl_ins.o_data_out[6] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111100010001000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=sys_ctrl_ins.o_data_out[5] I3=spi_if_ins.o_cs_SB_LUT4_I2_O[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000011111111 +.gate SB_LUT4 I0=sys_ctrl_ins.o_data_out[3] I1=spi_if_ins.o_cs_SB_LUT4_I2_O[0] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=io_ctrl_ins.o_data_out[3] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111100010001000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[7] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I3_O[2] O=spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_cs[3] I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111111101000 +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=io_ctrl_ins.i_cs I2=spi_if_ins.o_cs[3] I3=sys_ctrl_ins.i_cs O=spi_if_ins.o_cs_SB_LUT4_I2_1_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111011101000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_cs_SB_LUT4_I2_1_O[0] I3=i_rst_b O=spi_if_ins.o_cs_SB_LUT4_I2_1_O_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000010000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.o_cs_SB_LUT4_I0_O[1] O=spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=$false I1=io_ctrl_ins.o_data_out[5] I2=spi_if_ins.o_cs_SB_LUT4_I3_O[1] I3=spi_if_ins.o_cs_SB_LUT4_I3_O[2] O=spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000111111 +.gate SB_LUT4 I0=smi_ctrl_ins.i_cs I1=io_ctrl_ins.i_cs I2=sys_ctrl_ins.i_cs I3=spi_if_ins.o_cs[3] O=spi_if_ins.o_cs_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000100000000 +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[7] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[7] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[7] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[6] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[6] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[6] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[5] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[5] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[5] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[4] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[3] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[2] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[1] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O Q=spi_if_ins.o_data_in[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_data_in_SB_DFFE_Q_E Q=spi_if_ins.o_data_in[0] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_fetch_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] E=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_fetch_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] I2=i_rst_b I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[0] I3=spi_if_ins.state_if[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] I3=spi_if_ins.state_if[2] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111100001111 -.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] I3=i_rst_b O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010100000100000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000110100000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] O=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000000011110011 -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[4] +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[4] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=spi_if_ins.o_ioc[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[3] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[3] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=spi_if_ins.o_ioc[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[2] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[2] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=spi_if_ins.o_ioc[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[1] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[1] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=spi_if_ins.o_ioc[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=spi_if_ins.o_ioc[0] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_rx_byte[0] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=spi_if_ins.o_ioc[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_load_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E Q=spi_if_ins.o_load_cmd R=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] I1=spi_if_ins.state_if[2] I2=spi_if_ins.spi.o_rx_data_valid I3=i_rst_b O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if[0] I3=spi_if_ins.state_if[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111111111110000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000110000 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] I3=i_rst_b O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 .gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.o_load_cmd_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 .gate SB_DFFE C=r_counter D=r_tx_data[7] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[6] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[5] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[4] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[3] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[2] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[1] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=r_tx_data[0] E=spi_if_ins.r_tx_byte_SB_DFFE_Q_E Q=spi_if_ins.r_tx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] I3=i_rst_b O=spi_if_ins.r_tx_byte_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=spi_if_ins.spi.o_rx_data_valid I1=spi_if_ins.state_if[2] I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] E=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E Q=spi_if_ins.r_tx_data_valid R=spi_if_ins.spi.o_rx_data_valid .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101011100000000 -.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] I1=spi_if_ins.state_if[2] I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] O=spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001111100000000 +.gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.r_tx_data_valid O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] O=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.gate SB_LUT4 I0=spi_if_ins.spi.SCKr[2] I1=spi_if_ins.spi.r_tx_bit_count[0] I2=spi_if_ins.spi.r_tx_bit_count[2] I3=spi_if_ins.spi.SCKr[1] O=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111110000000000 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000100000000 .gate SB_DFF C=r_counter D=spi_if_ins.spi.SCKr[1] Q=spi_if_ins.spi.SCKr[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:134.10-149.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=spi_if_ins.spi.SCKr[0] Q=spi_if_ins.spi.SCKr[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:134.10-149.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=i_sck Q=spi_if_ins.spi.SCKr[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:62.3-62.62|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.SCKr[2] I2=spi_if_ins.spi.SCKr[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111111100110000 +.attr src "top.v:134.10-149.4|spi_slave.v:62.3-62.62|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[7] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[6] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[5] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[4] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[3] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[2] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[1] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=r_counter D=spi_if_ins.spi.r_rx_byte[0] E=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFF C=r_counter D=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O Q=spi_if_ins.spi.o_rx_data_valid .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.state_if[2] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] O=spi_if_ins.o_ioc_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000001000 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.o_data_in_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.o_spi_miso -.attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFFE C=r_counter D=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.o_spi_miso .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000011001111 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_bit_count[2] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=spi_if_ins.r_tx_byte[7] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1010100011111101 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[7] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] I1=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] I3=spi_if_ins.spi.r_tx_bit_count[1] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101001100000000 -.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[6] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110111011110000 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[0] I1=spi_if_ins.spi.r_tx_byte[4] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001010011 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] I3=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111110000001010 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[2] I1=spi_if_ins.spi.r_tx_byte[6] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_bit_count[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1111110000110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[1] I2=spi_if_ins.spi.r_tx_byte[0] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000110000001010 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[3] I1=spi_if_ins.spi.r_tx_byte[7] I2=spi_if_ins.spi.r_tx_bit_count[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_byte[3] I2=spi_if_ins.spi.r_tx_byte[2] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100101000000000 +.gate SB_LUT4 I0=spi_if_ins.spi.r_tx_byte[1] I1=spi_if_ins.spi.r_tx_byte[5] I2=spi_if_ins.spi.r_tx_bit_count[0] I3=spi_if_ins.spi.r_tx_bit_count[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=spi_if_ins.spi.r_tx_bit_count[1] I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1100111110100000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.SCKr[2] I2=spi_if_ins.spi.SCKr[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000000011 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000011111111 .gate SB_DFF C=r_counter D=spi_if_ins.spi.r_rx_done Q=spi_if_ins.spi.r2_rx_done .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=spi_if_ins.spi.r2_rx_done Q=spi_if_ins.spi.r3_rx_done .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:48.3-59.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:134.10-149.4|spi_slave.v:48.3-59.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r3_rx_done I3=spi_if_ins.spi.r2_rx_done O=spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D Q=spi_if_ins.spi.r_rx_bit_count[2] R=i_ss -.attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D Q=spi_if_ins.spi.r_rx_bit_count[1] R=i_ss +.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[2] Q=spi_if_ins.spi.r_rx_bit_count[2] R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_1_D +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[1] Q=spi_if_ins.spi.r_rx_bit_count[1] R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D Q=spi_if_ins.spi.r_rx_bit_count[0] R=i_ss +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_DFFSR C=i_sck D=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[0] Q=spi_if_ins.spi.r_rx_bit_count[0] R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:134.10-149.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:134.10-149.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=spi_if_ins.spi.r_rx_bit_count[0] CO=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[1] -.attr src "spi_slave.v:32.25-32.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=spi_if_ins.spi.r_rx_bit_count[0] CO=spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] I0=$false I1=spi_if_ins.spi.r_rx_bit_count[1] +.attr src "top.v:134.10-149.4|spi_slave.v:32.25-32.43|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[6] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFE C=i_sck D=i_mosi E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O Q=spi_if_ins.spi.r_rx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" .gate SB_DFFESR C=i_sck D=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] E=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_rx_done R=i_ss .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_LUT4 I0=$false I1=$false I2=i_ss I3=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111100000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[2] I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_rx_bit_count[1] I2=spi_if_ins.spi.r_rx_bit_count[0] I3=spi_if_ins.spi.r_rx_bit_count[2] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=i_ss I1=spi_if_ins.spi.r_rx_bit_count[2] I2=spi_if_ins.spi.r_rx_bit_count[1] I3=spi_if_ins.spi.r_rx_bit_count[0] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.gate SB_LUT4 I0=i_ss I1=spi_if_ins.spi.r_rx_bit_count[0] I2=spi_if_ins.spi.r_rx_bit_count[2] I3=spi_if_ins.spi.r_rx_bit_count[1] O=spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110101110101010 +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110101010111010 -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[5] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[6] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[4] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[5] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[3] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[4] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[2] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[3] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[1] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[2] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=spi_if_ins.spi.r_temp_rx_byte[0] E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[1] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFE C=i_sck D=i_mosi E=i_ss_SB_LUT4_I3_O Q=spi_if_ins.spi.r_temp_rx_byte[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFE C=i_sck D=i_mosi E=o_miso_$_TBUF__Y_E Q=spi_if_ins.spi.r_temp_rx_byte[0] +.attr src "top.v:134.10-149.4|spi_slave.v:27.3-42.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_DFFESR C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[0] E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.r_tx_bit_count[0] R=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:27.3-42.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_DFFESR C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=$true I3=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:134.10-149.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=$true I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D +.attr src "top.v:134.10-149.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 -.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[2] S=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.gate SB_CARRY CI=spi_if_ins.spi.r_tx_bit_count[0] CO=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] I0=spi_if_ins.spi.r_tx_bit_count[1] I1=$true +.attr src "top.v:134.10-149.4|spi_slave.v:75.27-75.45|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2] Q=spi_if_ins.spi.r_tx_bit_count[1] S=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[2] E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.r_tx_bit_count[2] S=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=$true I3=spi_if_ins.spi.r_tx_bit_count[0] O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_1_D +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_DFFESS C=r_counter D=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D[1] E=spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E Q=spi_if_ins.spi.r_tx_bit_count[1] S=spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[2] I2=$true I3=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 O=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:25.66-25.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[7] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[7] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=spi_if_ins.spi.r_tx_bit_count[0] CO=spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3 I0=spi_if_ins.spi.r_tx_bit_count[1] I1=$true -.attr src "spi_slave.v:75.27-75.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[7] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[7] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[6] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[6] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[6] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[6] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[5] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[5] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[5] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[5] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[4] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[4] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[4] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[4] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[3] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[3] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[3] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[3] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[2] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[2] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[2] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[2] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[1] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[1] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[1] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[1] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.r_tx_byte[0] E=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E Q=spi_if_ins.spi.r_tx_byte[0] R=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O +.attr src "top.v:134.10-149.4|spi_slave.v:68.3-84.6|spi_if.v:43.13-54.4|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.r_tx_bit_count[1] I2=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] I3=spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] O=spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_slave.v:68.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000011111111 +.gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_1_D E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_byte[7] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] I2=spi_if_ins.spi.o_rx_byte[7] I3=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110011110000 -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_data_valid I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=i_rst_b I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] O=spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[0] I3=spi_if_ins.state_if[1] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000110000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=spi_if_ins.state_if[2] I1=spi_if_ins.state_if[0] I2=spi_if_ins.state_if[1] I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000011000000 -.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1011110000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.state_if[2] I2=spi_if_ins.state_if[1] I3=spi_if_ins.state_if[0] O=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" .param LUT_INIT 0000001100000000 .gate SB_DFFESR C=r_counter D=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] E=spi_if_ins.state_if_SB_DFFESR_Q_E Q=spi_if_ins.state_if[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=spi_if_ins.spi.o_rx_data_valid I2=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] I3=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] I2=spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] I3=spi_if_ins.spi.o_rx_data_valid O=spi_if_ins.state_if_SB_DFFESR_Q_2_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000110000000000 -.gate SB_LUT4 I0=i_rst_b I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2] I3=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3] O=spi_if_ins.state_if_SB_DFFESR_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_LUT4 I0=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[0] I1=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] I2=spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[2] I3=i_rst_b O=spi_if_ins.state_if_SB_DFFESR_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101010111011111 -.gate SB_DFFE C=r_counter D=sys_ctrl_ins.i_cs_SB_DFFE_Q_D E=spi_if_ins.o_ioc_SB_DFFE_Q_E Q=sys_ctrl_ins.i_cs +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101111111111 +.gate SB_DFFE C=r_counter D=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] E=spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O Q=sys_ctrl_ins.i_cs .attr module_not_derived 00000000000000000000000000000001 -.attr src "spi_if.v:56.3-109.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" -.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=sys_ctrl_ins.i_cs_SB_DFFE_Q_D +.attr src "top.v:134.10-149.4|spi_if.v:56.3-109.6|/usr/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.spi.o_rx_byte[6] I3=spi_if_ins.spi.o_rx_byte[5] O=sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000000000001111 -.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] O=spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=spi_if_ins.o_ioc[1] I1=spi_if_ins.o_ioc[0] I2=i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2] I3=o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2] +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_1_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111011100100000 -.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_2_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:62.2-70.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.rx_sync_type24 O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1111100010001000 -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_3_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100110000001100 -.gate SB_LUT4 I0=$false I1=tx_fifo.full_o_SB_LUT4_I1_O[0] I2=tx_fifo.full_o_SB_LUT4_I1_O[1] I3=tx_fifo.full_o_SB_LUT4_I1_O[2] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2] +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.rx_sync_type09 O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_3_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_4_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.tx_sample_gap[3] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_4_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000000000 -.gate SB_LUT4 I0=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0] I1=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1] I2=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2] I3=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1] +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_5_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.tx_sample_gap[2] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_5_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010000000000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[9] I1=tx_fifo.wr_addr[1] I2=tx_fifo.rd_addr_gray_wr_r[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.full_o_SB_LUT4_I1_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_6_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100000111100 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.tx_sample_gap[1] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_6_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=sys_ctrl_ins.o_data_out_SB_DFFER_Q_7_D E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O Q=sys_ctrl_ins.o_data_out[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.tx_sample_gap[0] I3=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_7_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000011111111 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E Q=sys_ctrl_ins.rx_sync_09 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] I2=spi_if_ins.o_ioc[0] I3=spi_if_ins.o_ioc[1] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] I1=spi_if_ins.o_ioc[0] I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2[0] I3=spi_if_ins.o_ioc[1] O=i_button_SB_LUT4_I2_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011111101000101 +.gate SB_LUT4 I0=$false I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2[0] I2=spi_if_ins.o_ioc[0] I3=spi_if_ins.o_ioc[1] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=spi_if_ins.o_ioc[2] I3=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=io_ctrl_ins.i_cs_SB_LUT4_I2_O[1] I1=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] I2=sys_ctrl_ins.i_cs I3=spi_if_ins.o_fetch_cmd O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I1_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1110000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] I3=spi_if_ins.o_ioc[2] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=spi_if_ins.o_ioc[0] I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[1] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000100000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[2] I2=spi_if_ins.o_ioc[4] I3=spi_if_ins.o_ioc[3] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000000000000011 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_ioc[4] I2=spi_if_ins.o_ioc[3] I3=spi_if_ins.o_ioc[2] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=spi_if_ins.o_fetch_cmd I2=sys_ctrl_ins.i_cs I3=spi_if_ins.o_load_cmd O=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E Q=sys_ctrl_ins.rx_sync_24 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[4] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.rx_sync_type09 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[5] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.rx_sync_type24 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[3] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.tx_sample_gap[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[2] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.tx_sample_gap[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[1] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.tx_sample_gap[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[0] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.tx_sample_gap[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[6] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.tx_sync_type09 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.tx_sync_type09 O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_DFFER C=r_counter D=spi_if_ins.o_data_in[7] E=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O Q=sys_ctrl_ins.tx_sync_type24 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:155.12-180.4|sys_ctrl.v:83.5-152.8|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=$false I1=$false I2=sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0] I3=sys_ctrl_ins.tx_sync_type24 O=sys_ctrl_ins.o_data_out_SB_DFFER_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.empty_o_SB_LUT4_O_I3 O=tx_fifo.empty_o +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFFSR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D Q=tx_fifo.empty_o_SB_LUT4_O_I3 R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:88.2-96.5|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] I1=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] I2=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] I3=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] I1=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[1] I2=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[2] I3=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[1] I1=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=lvds_tx_inst.r_pulled O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[2] I1=tx_fifo.rd_addr[2] I2=tx_fifo.rd_addr[3] I3=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[1] I1=tx_fifo.rd_addr[1] I2=tx_fifo.rd_addr[2] I3=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000011101011 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[5] I2=tx_fifo.rd_addr[6] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[9] I1=tx_fifo.rd_addr_gray[9] I2=lvds_tx_inst.r_pulled I3=tx_fifo.empty_o_SB_LUT4_O_I3 O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000001101 +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[0] I1=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[1] I2=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] I3=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001000000000000 +.gate SB_LUT4 I0=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[0] I1=tx_fifo.rd_addr[7] I2=tx_fifo.wr_addr_gray_rd_r[7] I3=tx_fifo.rd_addr[8] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001100010000001 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[4] I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr[5] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=tx_fifo.rd_addr[0] I1=tx_fifo.wr_addr_gray_rd_r[0] I2=tx_fifo.rd_addr[1] I3=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100100000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr[4] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[6] I3=tx_fifo.rd_addr[6] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[5] I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr[6] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100110000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[8] I3=tx_fifo.rd_addr[8] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0101110011000101 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[1] I2=tx_fifo.rd_addr[2] I3=tx_fifo.wr_addr_gray_rd_r[1] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_DFFSR C=r_counter D=tx_fifo.full_o_SB_DFFSR_Q_D Q=tx_fifo.full_o R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:62.2-70.5|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] I1=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[1] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_DFFSR_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111110000000 +.gate SB_LUT4 I0=smi_ctrl_ins.push_pulse I1=tx_fifo.full_o_SB_LUT4_I3_I1[9] I2=tx_fifo.rd_addr_gray_wr_r[9] I3=tx_fifo.full_o O=tx_fifo.full_o_SB_LUT4_I3_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100000100000000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] O=tx_fifo.full_o_SB_LUT4_I3_I1[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[5] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[6] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[7] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.rd_addr[8] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] O=tx_fifo.full_o_SB_LUT4_I3_I1[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] O=tx_fifo.full_o_SB_LUT4_I3_I1[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] O=tx_fifo.full_o_SB_LUT4_I3_I1[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] O=tx_fifo.full_o_SB_LUT4_I3_I1[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[4] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[3] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 CO=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI I0=$false I1=tx_fifo.rd_addr[2] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] -.attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] O=tx_fifo.full_o_SB_LUT4_I3_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI O=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] O=tx_fifo.full_o_SB_LUT4_I3_I1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[1] I3=tx_fifo.wr_addr[0] O=tx_fifo.full_o_SB_LUT4_I3_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.full_o_SB_LUT4_I3_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.full_o_SB_LUT4_I3_O[2] I3=tx_fifo.full_o_SB_LUT4_I3_O[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 O=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1011000000000000 +.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] I1=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.rd_addr[1] -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[1] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] I3=tx_fifo.rd_addr_gray_wr_r[2] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[0] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] I2=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2] I3=lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] I1=tx_fifo.rd_addr_gray_wr_r[0] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000010010000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[6] I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[5] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1101000000000000 +.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0] I1=tx_fifo.rd_addr_gray_wr_r[9] I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[8] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=tx_fifo.rd_addr[4] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001100010000001 +.gate SB_LUT4 I0=$false I1=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] I3=tx_fifo.wr_addr[1] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000000110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.wr_addr_gray_rd_r[4] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001111000000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[0] I3=tx_fifo.rd_addr_gray_wr_r[0] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[1] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] I2=smi_ctrl_ins.push_pulse I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110000000000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[3] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 1111000000001111 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[3] I2=tx_fifo.rd_addr[2] I3=tx_fifo.wr_addr_gray_rd_r[2] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2] +.gate SB_LUT4 I0=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] I1=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[4] I2=tx_fifo.wr_addr_gray_rd_r[3] I3=tx_fifo.rd_addr[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000001 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1001000000000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.wr_addr_gray_rd_r[7] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[7] I2=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_wr_r[8] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray[9] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.wr_addr_gray_rd_r[8] I3=tx_fifo.rd_addr[8] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr[1] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0011101010100011 -.gate SB_LUT4 I0=tx_fifo.rd_addr[7] I1=tx_fifo.rd_addr[6] I2=tx_fifo.wr_addr_gray_rd_r[6] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[7] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[8] I0=$false I1=tx_fifo.wr_addr[8] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[6] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[7] I0=$false I1=tx_fifo.wr_addr[7] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[5] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[6] I0=$false I1=tx_fifo.wr_addr[6] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[4] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[5] I0=$false I1=tx_fifo.wr_addr[5] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[4] I0=$false I1=tx_fifo.wr_addr[4] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] I0=$false I1=tx_fifo.wr_addr[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr[1] CO=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] I0=$false I1=tx_fifo.wr_addr[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[7] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[6] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[2] I2=tx_fifo.wr_addr_gray_rd_r[1] I3=tx_fifo.rd_addr[1] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[5] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[4] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:77.15-77.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2] O=tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_SB_DFFNESR_Q_8_D +.attr src "top.v:514.3-530.4|complex_fifo.v:66.24-66.35|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[6] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] I2=tx_fifo.rd_addr_gray_wr_r[8] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] O=tx_fifo.full_o_SB_LUT4_I3_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_i.0.0_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[16] RDATA[2]=tx_fifo.mem_i.0.0_RDATA[2] RDATA[3]=tx_fifo.mem_i.0.0_RDATA[3] RDATA[4]=tx_fifo.mem_i.0.0_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[18] RDATA[6]=tx_fifo.mem_i.0.0_RDATA[6] RDATA[7]=tx_fifo.mem_i.0.0_RDATA[7] RDATA[8]=tx_fifo.mem_i.0.0_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[17] RDATA[10]=tx_fifo.mem_i.0.0_RDATA[10] RDATA[11]=tx_fifo.mem_i.0.0_RDATA[11] RDATA[12]=tx_fifo.mem_i.0.0_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[19] RDATA[14]=tx_fifo.mem_i.0.0_RDATA[14] RDATA[15]=tx_fifo.mem_i.0.0_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[16] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[18] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[17] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[19] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_i.0.1_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[20] RDATA[2]=tx_fifo.mem_i.0.1_RDATA[2] RDATA[3]=tx_fifo.mem_i.0.1_RDATA[3] RDATA[4]=tx_fifo.mem_i.0.1_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[22] RDATA[6]=tx_fifo.mem_i.0.1_RDATA[6] RDATA[7]=tx_fifo.mem_i.0.1_RDATA[7] RDATA[8]=tx_fifo.mem_i.0.1_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[21] RDATA[10]=tx_fifo.mem_i.0.1_RDATA[10] RDATA[11]=tx_fifo.mem_i.0.1_RDATA[11] RDATA[12]=tx_fifo.mem_i.0.1_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[23] RDATA[14]=tx_fifo.mem_i.0.1_RDATA[14] RDATA[15]=tx_fifo.mem_i.0.1_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[20] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[22] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[21] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[23] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2] +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_i.0.2_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[24] RDATA[2]=tx_fifo.mem_i.0.2_RDATA[2] RDATA[3]=tx_fifo.mem_i.0.2_RDATA[3] RDATA[4]=tx_fifo.mem_i.0.2_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[26] RDATA[6]=tx_fifo.mem_i.0.2_RDATA[6] RDATA[7]=tx_fifo.mem_i.0.2_RDATA[7] RDATA[8]=tx_fifo.mem_i.0.2_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[25] RDATA[10]=tx_fifo.mem_i.0.2_RDATA[10] RDATA[11]=tx_fifo.mem_i.0.2_RDATA[11] RDATA[12]=tx_fifo.mem_i.0.2_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[27] RDATA[14]=tx_fifo.mem_i.0.2_RDATA[14] RDATA[15]=tx_fifo.mem_i.0.2_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[24] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[26] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[25] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[27] WDATA[14]=$undef WDATA[15]=$undef WE=$true .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_i.0.3_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[28] RDATA[2]=tx_fifo.mem_i.0.3_RDATA[2] RDATA[3]=tx_fifo.mem_i.0.3_RDATA[3] RDATA[4]=tx_fifo.mem_i.0.3_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[30] RDATA[6]=tx_fifo.mem_i.0.3_RDATA[6] RDATA[7]=tx_fifo.mem_i.0.3_RDATA[7] RDATA[8]=tx_fifo.mem_i.0.3_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[29] RDATA[10]=tx_fifo.mem_i.0.3_RDATA[10] RDATA[11]=tx_fifo.mem_i.0.3_RDATA[11] RDATA[12]=tx_fifo.mem_i.0.3_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[31] RDATA[14]=tx_fifo.mem_i.0.3_RDATA[14] RDATA[15]=tx_fifo.mem_i.0.3_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[28] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=$false WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[29] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[16] WDATA[14]=$undef WDATA[15]=$undef WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_q.0.0_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[0] RDATA[2]=tx_fifo.mem_q.0.0_RDATA[2] RDATA[3]=tx_fifo.mem_q.0.0_RDATA[3] RDATA[4]=tx_fifo.mem_q.0.0_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[2] RDATA[6]=tx_fifo.mem_q.0.0_RDATA[6] RDATA[7]=tx_fifo.mem_q.0.0_RDATA[7] RDATA[8]=tx_fifo.mem_q.0.0_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[1] RDATA[10]=tx_fifo.mem_q.0.0_RDATA[10] RDATA[11]=tx_fifo.mem_q.0.0_RDATA[11] RDATA[12]=tx_fifo.mem_q.0.0_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[3] RDATA[14]=tx_fifo.mem_q.0.0_RDATA[14] RDATA[15]=tx_fifo.mem_q.0.0_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=$false WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[2] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[1] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[3] WDATA[14]=$undef WDATA[15]=$undef WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_q.0.1_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[4] RDATA[2]=tx_fifo.mem_q.0.1_RDATA[2] RDATA[3]=tx_fifo.mem_q.0.1_RDATA[3] RDATA[4]=tx_fifo.mem_q.0.1_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[6] RDATA[6]=tx_fifo.mem_q.0.1_RDATA[6] RDATA[7]=tx_fifo.mem_q.0.1_RDATA[7] RDATA[8]=tx_fifo.mem_q.0.1_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[5] RDATA[10]=tx_fifo.mem_q.0.1_RDATA[10] RDATA[11]=tx_fifo.mem_q.0.1_RDATA[11] RDATA[12]=tx_fifo.mem_q.0.1_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[7] RDATA[14]=tx_fifo.mem_q.0.1_RDATA[14] RDATA[15]=tx_fifo.mem_q.0.1_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[4] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[6] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[5] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[7] WDATA[14]=$undef WDATA[15]=$undef WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_q.0.2_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[8] RDATA[2]=tx_fifo.mem_q.0.2_RDATA[2] RDATA[3]=tx_fifo.mem_q.0.2_RDATA[3] RDATA[4]=tx_fifo.mem_q.0.2_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[10] RDATA[6]=tx_fifo.mem_q.0.2_RDATA[6] RDATA[7]=tx_fifo.mem_q.0.2_RDATA[7] RDATA[8]=tx_fifo.mem_q.0.2_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[9] RDATA[10]=tx_fifo.mem_q.0.2_RDATA[10] RDATA[11]=tx_fifo.mem_q.0.2_RDATA[11] RDATA[12]=tx_fifo.mem_q.0.2_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[11] RDATA[14]=tx_fifo.mem_q.0.2_RDATA[14] RDATA[15]=tx_fifo.mem_q.0.2_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[8] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[10] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[9] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=smi_ctrl_ins.o_tx_fifo_pushed_data[11] WDATA[14]=$undef WDATA[15]=$undef WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=tx_fifo.rd_addr[2] RADDR[1]=tx_fifo.rd_addr[3] RADDR[2]=tx_fifo.rd_addr[4] RADDR[3]=tx_fifo.rd_addr[5] RADDR[4]=tx_fifo.rd_addr[6] RADDR[5]=tx_fifo.rd_addr[7] RADDR[6]=tx_fifo.rd_addr[8] RADDR[7]=tx_fifo.rd_addr_gray[9] RADDR[8]=tx_fifo.rd_addr[1] RADDR[9]=tx_fifo.rd_addr[0] RADDR[10]=$false RCLK=lvds_rx_09_inst.i_ddr_clk RCLKE=lvds_tx_inst.r_pulled RDATA[0]=tx_fifo.mem_q.0.3_RDATA[0] RDATA[1]=tx_fifo.rd_data_o[12] RDATA[2]=tx_fifo.mem_q.0.3_RDATA[2] RDATA[3]=tx_fifo.mem_q.0.3_RDATA[3] RDATA[4]=tx_fifo.mem_q.0.3_RDATA[4] RDATA[5]=tx_fifo.rd_data_o[14] RDATA[6]=tx_fifo.mem_q.0.3_RDATA[6] RDATA[7]=tx_fifo.mem_q.0.3_RDATA[7] RDATA[8]=tx_fifo.mem_q.0.3_RDATA[8] RDATA[9]=tx_fifo.rd_data_o[13] RDATA[10]=tx_fifo.mem_q.0.3_RDATA[10] RDATA[11]=tx_fifo.mem_q.0.3_RDATA[11] RDATA[12]=tx_fifo.mem_q.0.3_RDATA[12] RDATA[13]=tx_fifo.rd_data_o[15] RDATA[14]=tx_fifo.mem_q.0.3_RDATA[14] RDATA[15]=tx_fifo.mem_q.0.3_RDATA[15] RE=$true WADDR[0]=tx_fifo.wr_addr[2] WADDR[1]=tx_fifo.wr_addr[3] WADDR[2]=tx_fifo.wr_addr[4] WADDR[3]=tx_fifo.wr_addr[5] WADDR[4]=tx_fifo.wr_addr[6] WADDR[5]=tx_fifo.wr_addr[7] WADDR[6]=tx_fifo.wr_addr[8] WADDR[7]=tx_fifo.wr_addr_gray[9] WADDR[8]=tx_fifo.wr_addr[1] WADDR[9]=tx_fifo.wr_addr[0] WADDR[10]=$false WCLK=r_counter WCLKE=smi_ctrl_ins.push_pulse WDATA[0]=$undef WDATA[1]=smi_ctrl_ins.o_tx_fifo_pushed_data[12] WDATA[2]=$undef WDATA[3]=$undef WDATA[4]=$undef WDATA[5]=smi_ctrl_ins.o_tx_fifo_pushed_data[16] WDATA[6]=$undef WDATA[7]=$undef WDATA[8]=$undef WDATA[9]=smi_ctrl_ins.o_tx_fifo_pushed_data[13] WDATA[10]=$undef WDATA[11]=$undef WDATA[12]=$undef WDATA[13]=$false WDATA[14]=$undef WDATA[15]=$undef WE=$true +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/brams_map.v:204.532-204.765" +.param INIT_0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_3 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_4 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_5 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_6 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_7 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_9 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_B xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_C xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_D xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_E xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param INIT_F xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +.param READ_MODE 10 +.param WRITE_MODE 10 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_1_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1] +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] I3=tx_fifo.wr_addr_gray_rd_r[7] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] I1=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] I2=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] O=tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[8] I1=tx_fifo.wr_addr_gray_rd_r[9] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100001010000001 +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[4] I1=tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] I2=tx_fifo.wr_addr_gray_rd_r[5] I3=tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] I1=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] I2=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] I3=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1000000000000000 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[3] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr[0] I2=tx_fifo.wr_addr_gray_rd_r[0] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000111100000011 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0011110011000011 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_rd_r[3] I1=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000011101011 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray_rd_r[4] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[6] I2=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1] I3=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3] +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100000000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=tx_fifo.wr_addr_gray_rd_r[2] I2=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1] +.gate SB_DFFESR C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D E=tx_fifo.rd_addr_SB_DFFESR_Q_E Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:72.2-80.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[0] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] O=tx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_gray[9] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] I0=$false I1=tx_fifo.rd_addr[8] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=tx_fifo.rd_addr[7] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=tx_fifo.rd_addr[6] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=tx_fifo.rd_addr[5] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=tx_fifo.rd_addr[4] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=tx_fifo.rd_addr[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=tx_fifo.rd_addr[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.rd_addr[0] CO=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=tx_fifo.rd_addr[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[8] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[7] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[6] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[5] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000001100110000 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[4] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] I3=tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_7_D +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[3] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2] E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[2] I3=tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_DFFNESR C=lvds_clock D=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D E=lvds_tx_inst.r_pulled_SB_LUT4_I3_O Q=tx_fifo.rd_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.rd_addr[1] I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:72.2-80.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:22.66-22.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[1] O=tx_fifo.rd_addr_gray_SB_DFFNESR_Q_9_D +.attr src "top.v:514.3-530.4|complex_fifo.v:77.15-77.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.rd_addr[0] O=tx_fifo.rd_addr_gray_SB_LUT4_I2_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" .param LUT_INIT 0000000011111111 .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[9] Q=tx_fifo.rd_addr_gray_wr[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[8] Q=tx_fifo.rd_addr_gray_wr[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[7] Q=tx_fifo.rd_addr_gray_wr[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[6] Q=tx_fifo.rd_addr_gray_wr[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[5] Q=tx_fifo.rd_addr_gray_wr[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[4] Q=tx_fifo.rd_addr_gray_wr[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[3] Q=tx_fifo.rd_addr_gray_wr[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[2] Q=tx_fifo.rd_addr_gray_wr[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[1] Q=tx_fifo.rd_addr_gray_wr[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray[0] Q=tx_fifo.rd_addr_gray_wr[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[9] Q=tx_fifo.rd_addr_gray_wr_r[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[8] Q=tx_fifo.rd_addr_gray_wr_r[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[7] Q=tx_fifo.rd_addr_gray_wr_r[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[6] Q=tx_fifo.rd_addr_gray_wr_r[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[5] Q=tx_fifo.rd_addr_gray_wr_r[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[4] Q=tx_fifo.rd_addr_gray_wr_r[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[3] Q=tx_fifo.rd_addr_gray_wr_r[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[2] Q=tx_fifo.rd_addr_gray_wr_r[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[1] Q=tx_fifo.rd_addr_gray_wr_r[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" .gate SB_DFF C=r_counter D=tx_fifo.rd_addr_gray_wr[0] Q=tx_fifo.rd_addr_gray_wr_r[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:57.2-60.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:57.2-60.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[8] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[7] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[6] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[6] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[7] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[5] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[7] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[8] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[8] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[4] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[3] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[6] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO CO=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI I0=$false I1=tx_fifo.wr_addr[5] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[6] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[2] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[1] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[0] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.full_o_SB_LUT4_I3_I1[9] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[4] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO I0=$false I1=tx_fifo.wr_addr[4] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[5] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[3] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[9] I3=tx_fifo.full_o_SB_LUT4_I3_I1[8] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[3] I3=tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[6] I3=tx_fifo.full_o_SB_LUT4_I3_I1[7] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 CO=tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[2] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 O=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] I1=tx_fifo.rd_addr_gray_wr_r[7] I2=tx_fifo.rd_addr_gray_wr_r[4] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100110010110 -.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3 I0=$false I1=tx_fifo.wr_addr[1] -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[0] I3=tx_fifo.full_o_SB_LUT4_I3_I1[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 1111000000001111 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[4] I3=tx_fifo.full_o_SB_LUT4_I3_I1[5] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[7] I3=tx_fifo.full_o_SB_LUT4_I3_I1[8] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] I2=tx_fifo.rd_addr_gray_wr_r[5] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000001001 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[5] I3=tx_fifo.full_o_SB_LUT4_I3_I1[6] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[3] I3=tx_fifo.full_o_SB_LUT4_I3_I1[4] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[5] I1=tx_fifo.rd_addr_gray_wr_r[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] O=tx_fifo.full_o_SB_LUT4_I1_O[2] +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001001000001 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[1] I3=tx_fifo.full_o_SB_LUT4_I3_I1[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" .param LUT_INIT 0000111111110000 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr[1] I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.full_o_SB_LUT4_I3_I1[2] I3=tx_fifo.full_o_SB_LUT4_I3_I1[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:51.15-51.29|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] E=tx_fifo.wr_addr_SB_DFFESR_Q_E Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:46.2-54.5|/usr/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" +.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_gray[9] I3=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] O=tx_fifo.full_o_SB_LUT4_I3_I1[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" .param LUT_INIT 0110100110010110 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_8_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr[0] R=i_rst_b_SB_LUT4_I3_O +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] I0=$false I1=tx_fifo.wr_addr[8] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] I0=$false I1=tx_fifo.wr_addr[7] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] I0=$false I1=tx_fifo.wr_addr[6] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] I0=$false I1=tx_fifo.wr_addr[5] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] I0=$false I1=tx_fifo.wr_addr[4] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] I0=$false I1=tx_fifo.wr_addr[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] I0=$false I1=tx_fifo.wr_addr[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=tx_fifo.wr_addr[0] CO=tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] I0=$false I1=tx_fifo.wr_addr[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:51.15-51.29|/usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[0] O=tx_fifo.wr_addr_SB_DFFESR_Q_8_D +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[8] Q=tx_fifo.wr_addr_gray_rd[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[9] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[7] Q=tx_fifo.wr_addr_gray_rd[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[8] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[6] Q=tx_fifo.wr_addr_gray_rd[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_1_D +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[5] Q=tx_fifo.wr_addr_gray_rd[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[7] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[4] Q=tx_fifo.wr_addr_gray_rd[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_2_D +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[3] Q=tx_fifo.wr_addr_gray_rd[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[6] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[2] Q=tx_fifo.wr_addr_gray_rd[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[1] Q=tx_fifo.wr_addr_gray_rd[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[5] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray[0] Q=tx_fifo.wr_addr_gray_rd[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[4] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[9] Q=tx_fifo.wr_addr_gray_rd_r[9] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[8] Q=tx_fifo.wr_addr_gray_rd_r[8] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[3] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[7] Q=tx_fifo.wr_addr_gray_rd_r[7] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[6] Q=tx_fifo.wr_addr_gray_rd_r[6] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.rd_addr_gray_wr_r[2] I2=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[5] Q=tx_fifo.wr_addr_gray_rd_r[5] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1100111101000101 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[8] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[4] Q=tx_fifo.wr_addr_gray_rd_r[4] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[7] I1=tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] I3=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[3] Q=tx_fifo.wr_addr_gray_rd_r[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001101001 -.gate SB_LUT4 I0=$false I1=tx_fifo.rd_addr_gray_wr_r[4] I2=tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[2] Q=tx_fifo.wr_addr_gray_rd_r[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100001100111100 -.gate SB_LUT4 I0=tx_fifo.rd_addr_gray_wr_r[3] I1=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1] I2=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] I3=tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3] +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[1] Q=tx_fifo.wr_addr_gray_rd_r[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000100011 -.gate SB_LUT4 I0=$false I1=$false I2=tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] I3=tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2] +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=lvds_rx_09_inst.i_ddr_clk D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000111111110000 -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2] E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[1] R=i_rst_b_SB_LUT4_I3_O +.attr src "top.v:514.3-530.4|complex_fifo.v:83.2-86.5|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d0 I3=w_lvds_rx_09_d1 O=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_DFFESR C=r_counter D=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D E=smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O Q=tx_fifo.wr_addr_gray[0] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=w_lvds_rx_09_d0_SB_LUT4_I2_O[2] I1=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=lvds_rx_09_inst.r_state_if[0] I3=lvds_rx_09_inst.r_state_if[1] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:46.2-54.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119" -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=tx_fifo.wr_addr[1] O=tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011000010111111 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O Q=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[9] Q=tx_fifo.wr_addr_gray_rd[9] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_1_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O Q=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[8] Q=tx_fifo.wr_addr_gray_rd[8] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_1_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[7] Q=tx_fifo.wr_addr_gray_rd[7] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101100000000 +.gate SB_DFFER C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_D E=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O Q=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[6] Q=tx_fifo.wr_addr_gray_rd[6] +.attr src "top.v:381.11-392.4|lvds_rx.v:36.3-84.6|/usr/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" +.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[5] Q=tx_fifo.wr_addr_gray_rd[5] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100111100000000 +.gate SB_LUT4 I0=lvds_rx_09_inst.r_state_if[1] I1=lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[1] I2=lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] I3=lvds_rx_09_inst.r_state_if[0] O=w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[4] Q=tx_fifo.wr_addr_gray_rd[4] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101100000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[1] I2=w_lvds_rx_09_d1 I3=w_lvds_rx_09_d0 O=w_lvds_rx_09_d1_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[3] Q=tx_fifo.wr_addr_gray_rd[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_09_inst.r_state_if[0] I2=w_lvds_rx_09_d1_SB_LUT4_I2_O[1] I3=i_rst_b O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[2] Q=tx_fifo.wr_addr_gray_rd[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111110000000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[1] I2=w_lvds_rx_24_d0 I3=w_lvds_rx_24_d1 O=w_lvds_rx_24_d0_SB_LUT4_I2_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[1] Q=tx_fifo.wr_addr_gray_rd[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=$false I1=lvds_rx_24_inst.r_state_if[0] I2=w_lvds_rx_24_d0_SB_LUT4_I2_O[1] I3=i_rst_b O=w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I2_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray[0] Q=tx_fifo.wr_addr_gray_rd[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111110000000000 +.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_24_d1 I3=w_lvds_rx_24_d0 O=w_lvds_rx_24_d1_SB_LUT4_I2_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[9] Q=tx_fifo.wr_addr_gray_rd_r[9] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=w_lvds_rx_24_d1_SB_LUT4_I2_O[2] I1=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[0] I2=lvds_rx_24_inst.r_state_if[0] I3=lvds_rx_24_inst.r_state_if[1] O=lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_DFFER_Q_E .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[8] Q=tx_fifo.wr_addr_gray_rd_r[8] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011000010111111 +.gate SB_DFFR C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_tx_d1_SB_DFFR_Q_D[1] Q=w_lvds_tx_d0 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[7] Q=tx_fifo.wr_addr_gray_rd_r[7] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_DFFR C=lvds_rx_09_inst.i_ddr_clk D=w_lvds_tx_d1_SB_DFFR_Q_D[0] Q=w_lvds_tx_d1 R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[6] Q=tx_fifo.wr_addr_gray_rd_r[6] +.attr src "top.v:441.11-453.6|lvds_tx.v:71.5-226.8|/usr/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" +.gate SB_LUT4 I0=lvds_tx_inst.r_phase_count[1] I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] I2=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[2] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] O=w_lvds_tx_d1_SB_DFFR_Q_D[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[5] Q=tx_fifo.wr_addr_gray_rd_r[5] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111111101110000 +.gate SB_LUT4 I0=$false I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[0] I2=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] I3=lvds_tx_inst.r_phase_count[3] O=w_lvds_tx_d1_SB_DFFR_Q_D[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[4] Q=tx_fifo.wr_addr_gray_rd_r[4] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=lvds_tx_inst.r_phase_count[1] I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] I2=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[2] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[3] Q=tx_fifo.wr_addr_gray_rd_r[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000111 +.gate SB_LUT4 I0=lvds_tx_inst.r_phase_count[1] I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[1] I2=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[2] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[2] Q=tx_fifo.wr_addr_gray_rd_r[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000111 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[20] I1=lvds_tx_inst.r_fifo_data[28] I2=lvds_tx_inst.r_phase_count[0] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[1] Q=tx_fifo.wr_addr_gray_rd_r[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001100000101 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[16] I1=lvds_tx_inst.r_fifo_data[24] I2=lvds_tx_inst.r_phase_count[2] I3=lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_DFFN C=lvds_clock D=tx_fifo.wr_addr_gray_rd[0] Q=tx_fifo.wr_addr_gray_rd_r[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[18] I1=lvds_tx_inst.r_fifo_data[26] I2=lvds_tx_inst.r_phase_count[2] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:83.2-86.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:1.51-1.90" -.gate SB_LUT4 I0=w_lvds_rx_09_d1 I1=w_lvds_rx_09_d0 I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=w_lvds_rx_09_d1_SB_LUT4_I0_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[22] I1=lvds_tx_inst.r_fifo_data[30] I2=lvds_tx_inst.r_phase_count[0] I3=lvds_tx_inst.r_phase_count[2] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000011111011 -.gate SB_LUT4 I0=$false I1=$false I2=i_rst_b I3=w_lvds_rx_09_d1_SB_LUT4_I0_O[1] O=w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011111101010000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[4] I1=lvds_tx_inst.r_fifo_data[12] I2=lvds_tx_inst.r_phase_count[0] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=$false I1=$false I2=w_lvds_rx_09_d1 I3=w_lvds_rx_09_d0 O=w_lvds_rx_09_d1_SB_LUT4_I2_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001100000101 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[0] I1=lvds_tx_inst.r_fifo_data[8] I2=lvds_tx_inst.r_phase_count[2] I3=lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 0000000011110000 -.gate SB_LUT4 I0=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 I1=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 I2=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] I3=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] O=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[2] I1=lvds_tx_inst.r_fifo_data[10] I2=lvds_tx_inst.r_phase_count[2] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000000000000000 -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_DFFER_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[6] I1=lvds_tx_inst.r_fifo_data[14] I2=lvds_tx_inst.r_phase_count[0] I3=lvds_tx_inst.r_phase_count[2] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I1=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] I2=$true I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_DFFER_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011111101010000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[21] I1=lvds_tx_inst.r_fifo_data[29] I2=lvds_tx_inst.r_phase_count[0] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0010100010000010 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1111001100000101 +.gate SB_LUT4 I0=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] I2=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] I3=lvds_tx_inst.r_phase_count[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000000000000001 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[3] I1=lvds_tx_inst.r_fifo_data[11] I2=lvds_tx_inst.r_phase_count[2] I3=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I2=w_lvds_rx_09_d1_SB_LUT4_I2_O[2] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[0] I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[1] I2=lvds_tx_inst.r_phase_count[0] I3=lvds_tx_inst.r_phase_count[1] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0101000011011101 -.gate SB_LUT4 I0=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 I1=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] I2=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I3=w_lvds_rx_09_d1_SB_LUT4_I2_O[3] O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_fifo_data[5] I2=lvds_tx_inst.r_fifo_data[13] I3=lvds_tx_inst.r_phase_count[2] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0111001101010000 -.gate SB_LUT4 I0=$false I1=$false I2=$false I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_fifo_data[7] I2=lvds_tx_inst.r_fifo_data[15] I3=lvds_tx_inst.r_phase_count[2] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" -.param LUT_INIT 0000000011111111 -.gate SB_CARRY CI=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O CO=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 I0=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1] I1=$true -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" -.gate SB_DFFER C=lvds_clock D=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_DFFER_Q_D E=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E Q=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] R=i_rst_b_SB_LUT4_I3_O +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] I1=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[3] I2=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] I3=lvds_tx_inst.r_phase_count[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:36.3-84.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" -.gate SB_LUT4 I0=lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] I1=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2] I2=$true I3=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 O=w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_DFFER_Q_D +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000101100000000 +.gate SB_LUT4 I0=$false I1=lvds_tx_inst.r_fifo_data[19] I2=lvds_tx_inst.r_fifo_data[27] I3=lvds_tx_inst.r_phase_count[2] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "lvds_rx.v:64.28-64.45|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1000001000101000 -.gate SB_LUT4 I0=w_lvds_rx_24_d1 I1=w_lvds_rx_24_d0 I2=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] I3=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] O=lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1111000011001100 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[17] I1=lvds_tx_inst.r_fifo_data[25] I2=lvds_tx_inst.r_phase_count[2] I3=lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[3] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011010100000000 +.gate SB_LUT4 I0=$false I1=$false I2=lvds_tx_inst.r_phase_count[1] I3=lvds_tx_inst.r_phase_count[0] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111100000000 +.gate SB_LUT4 I0=lvds_tx_inst.r_fifo_data[23] I1=lvds_tx_inst.r_fifo_data[31] I2=lvds_tx_inst.r_phase_count[0] I3=lvds_tx_inst.r_phase_count[2] O=w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000010000000000 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0011111101010000 .gate SB_DFFSR C=r_counter D=w_smi_read_req_SB_DFFSR_Q_D Q=w_smi_read_req R=i_rst_b_SB_LUT4_I3_O .attr module_not_derived 00000000000000000000000000000001 -.attr src "complex_fifo.v:88.2-96.5|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" -.gate SB_LUT4 I0=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0] I1=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1] I2=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2] I3=rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3] O=w_smi_read_req_SB_DFFSR_Q_D +.attr src "top.v:420.5-433.4|complex_fifo.v:88.2-96.5|/usr/bin/../share/yosys/ice40/ff_map.v:19.59-19.105" +.gate SB_LUT4 I0=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[0] I1=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[2] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] O=w_smi_read_req_SB_DFFSR_Q_D .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0001001100110011 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[0] I1=w_smi_read_req I2=rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] I3=w_smi_read_req_SB_LUT4_I1_I3[3] O=w_smi_read_req_SB_LUT4_I1_O[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0000011101110111 +.gate SB_LUT4 I0=$false I1=w_smi_read_req I2=w_smi_read_req_SB_LUT4_I1_I2[1] I3=w_smi_read_req_SB_LUT4_I1_I2[2] O=w_smi_read_req_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000000100001 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.wr_addr_gray_rd_r[4] O=w_smi_read_req_SB_LUT4_I1_I3[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 0000001100000000 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[8] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[9] I3=rx_fifo.rd_addr[8] O=w_smi_read_req_SB_LUT4_I1_I2[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 1100000000001100 -.gate SB_LUT4 I0=rx_fifo.rd_addr[8] I1=rx_fifo.rd_addr[7] I2=rx_fifo.wr_addr_gray_rd_r[7] I3=w_smi_read_req_SB_LUT4_I1_O[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100001010000001 +.gate SB_LUT4 I0=$false I1=rx_fifo.wr_addr_gray_rd_r[2] I2=rx_fifo.rd_addr[2] I3=rx_fifo.rd_addr[3] O=w_smi_read_req_SB_LUT4_I1_I2[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110100100000000 -.gate SB_LUT4 I0=rx_fifo.rd_addr[7] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=rx_fifo.rd_addr[6] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100111100 +.gate SB_LUT4 I0=$false I1=w_smi_read_req_SB_LUT4_I1_O[0] I2=w_smi_read_req_SB_LUT4_I1_O[1] I3=w_smi_read_req_SB_LUT4_I1_O[2] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=$false I1=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] I2=rx_fifo.rd_addr[6] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001101001 -.gate SB_LUT4 I0=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] I1=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100001100000000 +.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[0] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[1] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O[2] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000001000000000 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[2] I2=rx_fifo.rd_addr[1] I3=rx_fifo.wr_addr_gray_rd_r[1] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" +.param LUT_INIT 1100000000000000 +.gate SB_LUT4 I0=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[0] I1=rx_fifo.wr_addr_gray_rd_r[8] I2=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[2] I3=rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0011110011000011 -.gate SB_LUT4 I0=rx_fifo.rd_addr[6] I1=rx_fifo.wr_addr_gray_rd_r[5] I2=rx_fifo.rd_addr[4] I3=rx_fifo.wr_addr_gray_rd_r[4] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 1001000000000000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[7] I3=rx_fifo.rd_addr[8] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000100110010000 -.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[9] I1=rx_fifo.rd_addr_gray[9] I2=rx_fifo.wr_addr_gray_rd_r[8] I3=rx_fifo.rd_addr[8] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr[5] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 1110011101111110 -.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[3] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] I1=rx_fifo.wr_addr_gray_rd_r[6] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[2] I3=rx_fifo.rd_addr[7] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0000000001101111 -.gate SB_LUT4 I0=$false I1=rx_fifo.rd_addr[6] I2=rx_fifo.wr_addr_gray_rd_r[5] I3=rx_fifo.rd_addr[5] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110000000001001 +.gate SB_LUT4 I0=rx_fifo.wr_addr_gray_rd_r[1] I1=rx_fifo.rd_addr[1] I2=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[2] I3=rx_fifo.rd_addr[2] O=w_smi_read_req_SB_LUT4_I1_O[1] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" -.param LUT_INIT 0000000000111100 -.gate SB_LUT4 I0=rx_fifo.rd_addr[4] I1=rx_fifo.wr_addr_gray_rd_r[3] I2=rx_fifo.rd_addr[3] I3=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0100001010000001 +.gate SB_LUT4 I0=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] I1=rx_fifo.rd_addr[4] I2=rx_fifo.wr_addr_gray_rd_r[4] I3=rx_fifo.rd_addr[5] O=w_smi_read_req_SB_LUT4_I1_O[2] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" -.param LUT_INIT 0110011000001111 -.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[2] I3=rx_fifo.wr_addr_gray_rd_r[2] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0001100010000001 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.wr_addr_gray_rd_r[3] I3=rx_fifo.rd_addr[3] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] .attr module_not_derived 00000000000000000000000000000001 -.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" -.param LUT_INIT 1111000000001111 -.names rx_fifo.wr_addr[2] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[0] +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.gate SB_LUT4 I0=$false I1=$false I2=rx_fifo.rd_addr[0] I3=rx_fifo.wr_addr_gray_rd_r[0] O=w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" +.param LUT_INIT 0000111111110000 +.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[1] +.names tx_fifo.rd_addr_gray_wr_r[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[1] 1 1 -.names rx_fifo.mem_i.0.0_WCLKE rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2] +.names rx_fifo.wr_addr_gray_rd_r[1] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[0] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[1] +.names rx_fifo.rd_addr[1] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[1] 1 1 -.names io_ctrl_ins.rf_pin_state[3] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[0] +.names rx_fifo.rd_addr[2] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_I2[3] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[2] +.names lvds_tx_inst.r_phase_count[1] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state o_led1_SB_LUT4_I1_I2[0] +.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] 1 1 -.names io_ctrl_ins.pmod_dir_state[4] o_led1_SB_LUT4_I1_I2[1] +.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[0] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_17_I3[1] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2] +.names lvds_tx_inst.r_fifo_data[21] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[0] +.names lvds_tx_inst.r_fifo_data[29] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] 1 1 -.names i_config[3] i_button_SB_LUT4_I0_I3[0] +.names lvds_tx_inst.r_phase_count[0] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2] 1 1 -.names io_ctrl_ins.pmod_dir_state[6] i_button_SB_LUT4_I0_I3[1] +.names smi_ctrl_ins.d_byte[7] smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[0] 1 1 -.names o_led1_SB_LUT4_I1_I2[2] i_button_SB_LUT4_I0_I3[2] +.names smi_ctrl_ins.swe_edge smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[1] 1 1 -.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[0] +.names smi_ctrl_ins.byte_ix[0] smi_ctrl_ins.push_req_SB_DFFR_Q_D_SB_LUT4_O_I3[2] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] 1 1 -.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.names lvds_tx_inst.r_fifo_data[2] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[0] 1 1 -.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] +.names lvds_tx_inst.r_fifo_data[10] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[1] 1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] +.names lvds_tx_inst.r_phase_count[2] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[2] 1 1 -.names io_ctrl_ins.rf_pin_state[6] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] +.names lvds_tx_inst.fifo_empty_d2 lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +.names lvds_tx_inst.tx_state_d2 lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[1] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.wr_addr_SB_DFFESR_Q_D[0] +.names lvds_tx_inst.sent_first_sync lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[2] 1 1 -.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[0] +.names smi_ctrl_ins.swe_edge smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[0] 1 1 -.names o_led1_SB_LUT4_I1_I2[3] io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[1] +.names smi_ctrl_ins.byte_ix[3] smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0] +.names lvds_tx_inst.sent_first_sync_SB_LUT4_I2_O[1] lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[1] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1] +.names lvds_tx_inst.frame_boundary lvds_tx_inst.r_state_SB_DFFER_Q_E_SB_LUT4_O_I1[2] 1 1 -.names o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[0] +.names tx_fifo.wr_addr[1] tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] 1 1 -.names io_ctrl_ins.o_data_out[6] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0] +.names lvds_tx_inst.r_phase_count[3] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2] +.names lvds_rx_09_inst.r_state_if[1] w_lvds_rx_09_d0_SB_LUT4_I2_O[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3] +.names lvds_rx_09_inst.r_state_if[0] w_lvds_rx_09_d0_SB_LUT4_I2_O[1] 1 1 -.names tx_fifo.rd_addr[4] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[0] +.names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] +.names lvds_tx_inst.r_phase_count[0] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[2] 1 1 -.names w_lvds_rx_09_d1 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[0] +.names lvds_tx_inst.r_phase_count[1] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1_I0[3] 1 1 -.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2] +.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] 1 1 -.names w_lvds_rx_09_d1_SB_LUT4_I2_O[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[3] +.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] 1 1 -.names spi_if_ins.o_ioc[0] o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.names spi_if_ins.o_cs_SB_LUT4_I2_O[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.names sys_ctrl_ins.o_data_out[7] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] 1 1 -.names $true rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] 1 1 -.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q_SB_LUT4_I1_I3 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] +.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] 1 1 -.names i_rst_b w_lvds_rx_09_d1_SB_LUT4_I0_O[0] +.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] 1 1 -.names io_ctrl_ins.rx_h_state i_button_SB_LUT4_I0_O[0] +.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] 1 1 -.names o_led1_SB_LUT4_I1_I2[3] i_button_SB_LUT4_I0_O[1] +.names io_ctrl_ins.debug_mode[1] io_ctrl_ins.led1_state_SB_LUT4_I3_O[0] 1 1 -.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] +.names io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] io_ctrl_ins.led1_state_SB_LUT4_I3_O[1] 1 1 -.names w_lvds_rx_24_d0 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] +.names sys_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[0] 1 1 -.names w_lvds_rx_24_d1 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[0] +.names spi_if_ins.o_cs_SB_LUT4_I2_O[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[1] 1 1 -.names rx_fifo.full_o_SB_LUT4_I2_I3[1] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2] +.names spi_if_ins.o_cs_SB_LUT4_I3_O[2] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_1_O[2] 1 1 -.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1] +.names smi_ctrl_ins.d_byte[7] smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[0] 1 1 -.names i_config[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[0] +.names smi_ctrl_ins.swe_edge smi_ctrl_ins.byte_ix_SB_LUT4_I2_O[2] 1 1 -.names o_led1_SB_LUT4_I1_I3[3] io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[1] +.names lvds_rx_09_inst.r_state_if[0] w_lvds_rx_09_d1_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[0] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[0] 1 1 -.names i_ss spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[0] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_26_I3[1] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[1] +.names smi_ctrl_ins.byte_ix[0] smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.names smi_ctrl_ins.swe_edge smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[2] 1 1 -.names io_ctrl_ins.pmod_dir_state[0] o_led1_SB_LUT4_I1_I3[0] +.names smi_ctrl_ins.d_byte[7] smi_ctrl_ins.byte_ix_SB_DFFS_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3] 1 1 -.names o_led0 o_led1_SB_LUT4_I1_I3[1] +.names io_ctrl_ins.o_data_out[0] spi_if_ins.o_cs_SB_LUT4_I3_O[0] 1 1 -.names o_led1_SB_LUT4_I1_I2[2] o_led1_SB_LUT4_I1_I3[2] +.names io_ctrl_ins.debug_mode[1] io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[1] 1 1 -.names smi_ctrl_ins.o_data_out[0] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +.names i_rst_b io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[2] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[0] +.names w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I1[3] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] 1 1 -.names $true rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[2] +.names lvds_tx_inst.r_phase_count[3] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_2_I0[3] 1 1 -.names rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[3] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D[1] rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0] +.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] 1 1 -.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I0_O[0] +.names io_ctrl_ins.tr_vc_1_b_state io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[0] 1 1 -.names rx_fifo.rd_addr[4] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0] +.names io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1] +.names sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] io_ctrl_ins.i_cs_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.rd_addr[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2] +.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[0] spi_if_ins.state_if_SB_DFFESR_Q_2_D[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0] +.names spi_if_ins.spi.o_rx_byte[7] spi_if_ins.state_if_SB_DFFESR_Q_2_D[1] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[0] +.names io_ctrl_ins.rf_mode[1] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[0] 1 1 -.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.names io_ctrl_ins.led0_state_SB_LUT4_I3_I1[2] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[1] 1 1 -.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +.names smi_ctrl_ins.o_data_out[4] spi_if_ins.o_cs_SB_LUT4_I1_O[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.names spi_if_ins.o_cs_SB_LUT4_I3_O[1] spi_if_ins.o_cs_SB_LUT4_I1_O[2] 1 1 -.names i_rst_b spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] +.names io_ctrl_ins.o_data_out[4] spi_if_ins.o_cs_SB_LUT4_I1_O[3] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] +.names spi_if_ins.o_fetch_cmd io_ctrl_ins.led0_state_SB_LUT4_I3_I1[0] 1 1 -.names spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] +.names io_ctrl_ins.i_cs io_ctrl_ins.led0_state_SB_LUT4_I3_I1[1] 1 1 -.names io_ctrl_ins.tr_vc_1_state io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[0] +.names spi_if_ins.o_load_cmd io_ctrl_ins.led0_state_SB_LUT4_I3_I1[3] 1 1 -.names o_led1_SB_LUT4_I1_I2[3] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[1] +.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] 1 1 -.names io_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[0] +.names tx_fifo.rd_addr_gray_wr_r[4] tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2] 1 1 -.names smi_ctrl_ins.o_data_out[2] spi_if_ins.o_cs_SB_LUT4_I0_4_O[1] +.names w_smi_read_req w_smi_read_req_SB_LUT4_I1_I2[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[1] o_led0_SB_LUT4_I1_O[0] +.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] 1 1 -.names io_pmod_in[3] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[0] +.names tx_fifo.wr_addr_gray_rd_r[5] tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[0] +.names tx_fifo.rd_addr[7] tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[1] 1 1 -.names spi_if_ins.o_ioc[1] i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0] +.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[2] 1 1 -.names spi_if_ins.o_ioc[0] i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1] +.names tx_fifo.rd_addr[8] tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_I0[3] 1 1 -.names o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] +.names io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[0] +.names io_ctrl_ins.rf_pin_state[6] io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[1] +.names smi_ctrl_ins.o_data_out[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[0] 1 1 -.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[3] +.names spi_if_ins.o_cs_SB_LUT4_I1_O[1] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] 1 1 -.names tx_fifo.rd_addr[7] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[0] +.names spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.full_o rx_fifo.full_o_SB_LUT4_I2_I3[0] +.names spi_if_ins.state_if[2] spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] +.names lvds_rx_09_inst.r_state_if[1] lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.names lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[2] 1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[1] +.names lvds_rx_09_inst.r_state_if[0] lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[3] 1 1 -.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0] w_lvds_rx_09_d1_SB_LUT4_I2_O[0] +.names tx_fifo.rd_addr[0] tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[0] 1 1 -.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] w_lvds_rx_09_d1_SB_LUT4_I2_O[1] +.names tx_fifo.wr_addr_gray_rd_r[0] tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[1] 1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[0] +.names tx_fifo.rd_addr[1] tx_fifo.empty_o_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_2_I3[2] 1 1 -.names spi_if_ins.o_ioc[0] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[1] +.names tx_fifo.rd_addr_gray_wr_r[6] tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.names tx_fifo.rd_addr_gray_wr_r[8] tx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[0] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[4] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_16_I3[1] 1 1 -.names io_ctrl_ins.pmod_dir_state[3] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[0] +.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_I2_O[3] 1 1 -.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[1] +.names rx_fifo.wr_addr_gray_rd_r[9] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[0] +.names rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[2] +.names rx_fifo.rd_en_i rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2] rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[3] +.names sys_ctrl_ins.o_data_out[5] spi_if_ins.o_cs_SB_LUT4_I2_O[1] 1 1 -.names spi_if_ins.o_ioc[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[0] +.names tx_fifo.wr_addr_gray_rd_r[7] tx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] 1 1 -.names o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[2] io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1] +.names io_ctrl_ins.pmod_dir_state[0] io_ctrl_ins.led0_state_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[0] w_smi_read_req_SB_LUT4_I1_I3[0] +.names sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] io_ctrl_ins.led0_state_SB_LUT4_I3_O[1] 1 1 -.names w_smi_read_req w_smi_read_req_SB_LUT4_I1_I3[1] +.names lvds_rx_24_inst.r_state_if[0] w_lvds_rx_24_d0_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] w_smi_read_req_SB_LUT4_I1_I3[2] +.names i_rst_b w_lvds_rx_24_d0_SB_LUT4_I2_O[2] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0] +.names smi_ctrl_ins.r_fifo_pulled_data[6] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1] +.names smi_ctrl_ins.r_fifo_pulled_data[14] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[1] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_1_I3[2] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0] +.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[0] 1 1 -.names w_lvds_rx_24_d1 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[0] +.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[2] 1 1 -.names w_lvds_rx_24_d0 rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[1] +.names sys_ctrl_ins.tx_sample_gap[2] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2] rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[2] +.names tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] tx_fifo.full_o_SB_LUT4_I3_O[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.names tx_fifo.rd_addr_gray_wr_r[0] tx_fifo.full_o_SB_LUT4_I3_O[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] +.names io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[1] io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2] tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.names tx_fifo.wr_addr_gray_rd_r[1] tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0] +.names tx_fifo.rd_addr[1] tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.wr_addr_SB_DFFESR_Q_D[1] rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1] +.names tx_fifo.rd_addr[2] tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[2] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0] +.names spi_if_ins.o_cs_SB_LUT4_I2_O[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[0] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[1] +.names sys_ctrl_ins.o_data_out[1] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_2_O[1] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[2] +.names tx_fifo.wr_addr_gray_rd_r[2] tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0] +.names tx_fifo.rd_addr[2] tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[1] tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1] +.names tx_fifo.rd_addr[3] tx_fifo.empty_o_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_4_D[1] rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0] +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] 1 1 -.names rx_fifo.rd_addr[8] w_smi_read_req_SB_LUT4_I1_O[0] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] 1 1 -.names rx_fifo.rd_addr[7] w_smi_read_req_SB_LUT4_I1_O[1] +.names rx_fifo.wr_addr[1] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I0[3] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[7] w_smi_read_req_SB_LUT4_I1_O[2] +.names lvds_tx_inst.r_fifo_data[29] lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[0] +.names tx_fifo.rd_data_o[29] lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1] +.names lvds_tx_inst.pending_load lvds_tx_inst.fifo_empty_d2_SB_LUT4_I1_O[2] 1 1 -.names lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[1] w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[0] +.names io_ctrl_ins.rf_mode[0] io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] 1 1 -.names $true w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[2] +.names io_ctrl_ins.rf_mode[2] io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] 1 1 -.names w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I3_O w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3] +.names io_ctrl_ins.rf_mode[1] io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] 1 1 -.names io_pmod_in[2] lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[0] +.names rx_fifo.wr_addr_gray_rd_r[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[5] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.names rx_fifo.wr_addr_gray_rd_r[6] rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[7] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.names i_rst_b spi_if_ins.o_cs_SB_LUT4_I2_1_O[1] 1 1 -.names rx_fifo.rd_addr[4] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[0] +.names w_lvds_rx_24_d1 lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[1] +.names lvds_rx_24_inst.r_sync_input lvds_rx_24_inst.r_sync_input_SB_LUT4_I2_I3[1] 1 1 -.names rx_fifo.rd_addr[3] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[2] +.names lvds_tx_inst.r_phase_count[1] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[9] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0] +.names rx_fifo.full_o lvds_rx_09_inst.r_sync_input_SB_LUT4_I2_I3[0] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1] +.names rx_fifo.rd_addr_gray_wr_r[1] rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_7_D[0] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2] +.names rx_fifo.rd_addr_gray_wr_r[7] rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] 1 1 -.names rx_fifo.rd_addr[7] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[6] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1] +.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[2] 1 1 -.names rx_fifo.rd_addr[6] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I0[3] 1 1 -.names io_ctrl_ins.o_data_out[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0] +.names i_button_SB_LUT4_I2_I1[1] io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[2] +.names i_config[3] io_ctrl_ins.rx_h_b_state_SB_LUT4_I0_O[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3] +.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[3] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] +.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[6] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0] +.names lvds_rx_24_inst.r_state_if[0] lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[1] +.names lvds_rx_24_inst.r_state_if[1] lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_O[2] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2] +.names lvds_tx_inst.sent_first_sync_SB_LUT4_I2_I3[3] lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[0] 1 1 -.names tx_fifo.rd_addr[7] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[0] +.names lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] lvds_tx_inst.r_tx_state_q_SB_LUT4_I1_O[1] 1 1 -.names tx_fifo.rd_addr[6] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[1] +.names io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[6] tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2] +.names io_ctrl_ins.rf_pin_state[4] io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0] +.names rx_fifo.wr_addr_gray_rd_r[8] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I1_O[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[2] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[0] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_14_I3[1] 1 1 -.names tx_fifo.rd_addr_gray_wr_r[4] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0] +.names lvds_tx_inst.r_fifo_data[20] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[0] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[1] +.names lvds_tx_inst.r_fifo_data[28] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[1] 1 1 -.names smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[2] +.names lvds_tx_inst.r_phase_count[0] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I3[2] 1 1 -.names spi_if_ins.o_ioc[1] o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +.names rx_fifo.rd_addr[4] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[1] 1 1 -.names spi_if_ins.o_ioc[0] o_led0_SB_LUT4_I1_O_SB_LUT4_O_I3[1] +.names rx_fifo.wr_addr_gray_rd_r[4] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0] +.names rx_fifo.rd_addr[5] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] 1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[1] +.names rx_fifo.wr_addr_gray_rd_r[6] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[1] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[7] rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.names rx_fifo.rd_addr[7] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[3] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[3] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.names rx_fifo.wr_addr_gray_rd_r[4] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] 1 1 -.names spi_if_ins.o_ioc[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[0] +.names rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] 1 1 -.names spi_if_ins.o_ioc[0] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[1] +.names rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[2] rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0] +.names w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I1[0] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0] tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1] +.names rx_fifo.rd_addr[6] w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1] 1 1 -.names spi_if_ins.o_fetch_cmd sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[0] +.names io_ctrl_ins.rx_h_b_state io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[0] 1 1 -.names sys_ctrl_ins.i_cs sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[1] +.names sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[1] io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[2] 1 1 -.names spi_if_ins.spi.SCKr[2] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.names io_ctrl_ins.pmod_dir_state[6] io_ctrl_ins.rx_h_state_SB_LUT4_I0_I1[3] 1 1 -.names spi_if_ins.spi.SCKr[1] spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[0] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[2] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_23_I3[1] 1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[1] +.names tx_fifo.rd_addr_gray_wr_r[5] tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] 1 1 -.names io_ctrl_ins.o_data_out[4] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0] +.names smi_ctrl_ins.push_pulse tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[2] +.names spi_if_ins.o_ioc[0] io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_I3[1] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_4_O[3] r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3] +.names lvds_tx_inst.r_phase_count[1] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[8] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0] +.names rx_fifo.wr_en_i rx_fifo.full_o_SB_LUT4_I3_O[0] 1 1 -.names rx_fifo.wr_addr_gray_rd_r[1] rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0] +.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.full_o_SB_LUT4_I3_O[2] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0] tx_fifo.wr_addr_SB_DFFESR_Q_5_D[1] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0] tx_fifo.wr_addr_SB_DFFESR_Q_7_D[1] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_4_I3[1] 1 1 -.names i_rst_b spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[0] +.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1[1] 1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[0] +.names lvds_rx_24_inst.r_state_if[1] w_lvds_rx_24_d1_SB_LUT4_I2_O[0] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.wr_addr_SB_DFFESR_Q_4_D[1] +.names lvds_rx_24_inst.r_state_if[0] w_lvds_rx_24_d1_SB_LUT4_I2_O[1] 1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.names sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[2] i_button_SB_LUT4_I2_I1[0] 1 1 -.names smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0] +.names io_ctrl_ins.rf_mode[2] i_button_SB_LUT4_I2_I1[2] 1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1] +.names smi_ctrl_ins.r_fifo_pulled_data[1] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[0] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[3] tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[0] +.names smi_ctrl_ins.r_fifo_pulled_data[9] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[9] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_6_I3[2] 1 1 -.names rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[0] 1 1 -.names lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[0] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O_13_I3[1] 1 1 -.names io_ctrl_ins.pmod_dir_state[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0] +.names spi_if_ins.o_cs_SB_LUT4_I2_O[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[0] 1 1 -.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.names sys_ctrl_ins.o_data_out[4] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I1_O[1] 1 1 -.names rx_fifo.full_o_SB_LUT4_I2_I3_SB_LUT4_O_I3[3] lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1] +.names spi_if_ins.o_ioc[0] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[8] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0] +.names sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2[0] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[2] 1 1 -.names tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0] +.names spi_if_ins.o_ioc[1] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[3] 1 1 -.names w_lvds_rx_09_d1_SB_LUT4_I2_O[3] lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[1] +.names lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[0] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[0] +.names lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[0] 1 1 -.names i_rst_b smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[0] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[2] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[1] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_I0_1_I1[3] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[2] 1 1 -.names spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[1] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I0[3] 1 1 -.names spi_if_ins.r_tx_byte[7] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[0] +.names rx_fifo.rd_addr_gray_wr_r[4] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1] 1 1 -.names spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[1] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[3] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[6] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0] +.names rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[4] rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_2_I0[3] 1 1 -.names r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[1] lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[1] +.names lvds_tx_inst.r_phase_count[3] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1[2] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_2_Q[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0] +.names lvds_tx_inst.r_fifo_data[0] lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[0] 1 1 -.names o_led0_SB_LUT4_I1_O[1] io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[1] +.names lvds_tx_inst.r_fifo_data[8] lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[1] 1 1 -.names o_led0_SB_LUT4_I1_O[1] io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[1] +.names lvds_tx_inst.r_phase_count[2] lvds_tx_inst.frame_boundary_SB_LUT4_O_I3[2] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0] o_led1_SB_LUT4_I1_O[0] +.names $false lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[1] 1 1 -.names o_led0_SB_LUT4_I1_O[1] o_led1_SB_LUT4_I1_O[1] +.names $true lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[2] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[0] lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0] +.names lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3_SB_LUT4_I1_I2[3] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_7_D[0] lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1] +.names smi_ctrl_ins.r_fifo_pulled_data[2] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[0] 1 1 -.names spi_if_ins.spi.r_tx_bit_count[2] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0] +.names smi_ctrl_ins.r_fifo_pulled_data[10] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[1] 1 1 -.names spi_if_ins.spi.o_rx_data_valid spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_5_I3[2] 1 1 -.names tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0] tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[1] +.names smi_ctrl_ins.r_fifo_pulled_data[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[0] 1 1 -.names io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[1] io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.names smi_ctrl_ins.r_fifo_pulled_data[12] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[1] 1 1 -.names rx_fifo.rd_addr_gray_wr_r[5] rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_3_I3[2] 1 1 -.names rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[1] rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0] +.names smi_ctrl_ins.r_fifo_pulled_data[0] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[0] 1 1 -.names rx_fifo.rd_data_o[8] rx_fifo.mem_q.0.2_RDATA[1] +.names smi_ctrl_ins.r_fifo_pulled_data[8] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[1] 1 1 -.names rx_fifo.rd_data_o[10] rx_fifo.mem_q.0.2_RDATA[5] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_7_I3[2] 1 1 -.names rx_fifo.rd_data_o[9] rx_fifo.mem_q.0.2_RDATA[9] +.names smi_ctrl_ins.r_fifo_pulled_data[7] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[0] 1 1 -.names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13] +.names smi_ctrl_ins.r_fifo_pulled_data[15] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[1] 1 1 -.names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_I3[2] 1 1 -.names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5] +.names smi_ctrl_ins.r_fifo_pulled_data[3] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[0] 1 1 -.names rx_fifo.rd_data_o[25] rx_fifo.mem_i.0.2_RDATA[9] +.names smi_ctrl_ins.r_fifo_pulled_data[11] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[1] 1 1 -.names rx_fifo.rd_data_o[27] rx_fifo.mem_i.0.2_RDATA[13] +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_4_I3[2] 1 1 -.names rx_fifo.rd_data_o[20] rx_fifo.mem_i.0.1_RDATA[1] +.names spi_if_ins.o_cs_SB_LUT4_I2_O[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[0] 1 1 -.names rx_fifo.rd_data_o[22] rx_fifo.mem_i.0.1_RDATA[5] +.names sys_ctrl_ins.o_data_out[0] spi_if_ins.o_cs_SB_LUT4_I1_O_SB_LUT4_I2_O[1] 1 1 -.names rx_fifo.rd_data_o[21] rx_fifo.mem_i.0.1_RDATA[9] +.names i_button_SB_LUT4_I2_I1[1] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0] 1 1 -.names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13] +.names i_config[2] io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1] 1 1 -.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1] +.names lvds_tx_inst.sent_first_sync lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[1] 1 1 -.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[2] 1 1 -.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.sent_first_sync_SB_LUT4_I1_I0[3] 1 1 -.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13] +.names rx_fifo.wr_en_i rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[0] +1 1 +.names io_ctrl_ins.pmod_dir_state[4] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[0] +1 1 +.names i_config[1] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O[3] +1 1 +.names tx_fifo.rd_addr_gray_wr_r[9] tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +1 1 +.names tx_fifo.wr_addr_gray[9] tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[2] +1 1 +.names tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[8] tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +1 1 +.names spi_if_ins.o_ioc[0] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2[1] +1 1 +.names spi_if_ins.o_ioc[1] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2[2] +1 1 +.names lvds_tx_inst.fifo_empty_d2 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[0] +1 1 +.names lvds_tx_inst.tx_state_d2 lvds_tx_inst.sent_first_sync_SB_LUT4_I1_O[2] +1 1 +.names spi_if_ins.spi.r_tx_byte[0] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.spi.r_tx_byte[4] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[0] spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +1 1 +.names i_button_SB_LUT4_I2_I1[1] io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[0] +1 1 +.names i_button io_ctrl_ins.rx_h_state_SB_LUT4_I0_O[1] +1 1 +.names lvds_tx_inst.r_fifo_data[4] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[0] +1 1 +.names lvds_tx_inst.r_fifo_data[12] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[1] +1 1 +.names lvds_tx_inst.r_phase_count[0] w_lvds_tx_d1_SB_DFFR_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I3[2] +1 1 +.names spi_if_ins.o_ioc[2] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0_SB_LUT4_I0_I2_SB_LUT4_I1_O_SB_LUT4_O_I3[0] +1 1 +.names sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I0[0] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[0] +1 1 +.names spi_if_ins.o_ioc[0] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[2] +1 1 +.names spi_if_ins.o_ioc[1] sys_ctrl_ins.rx_sync_09_SB_DFFER_Q_E_SB_LUT4_O_I1[3] +1 1 +.names $true lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[0] +1 1 +.names lvds_rx_09_inst.r_phase_count[0] lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[1] +1 1 +.names $true lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[0] +1 1 +.names lvds_rx_24_inst.r_phase_count[0] lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[1] +1 1 +.names $true lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +1 1 +.names lvds_tx_inst.r_sync_count[0] lvds_tx_inst.r_sync_count_SB_DFFER_Q_D_SB_LUT4_O_I3[1] +1 1 +.names smi_ctrl_ins.r_fifo_pulled_data[5] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[0] +1 1 +.names smi_ctrl_ins.r_fifo_pulled_data[13] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[1] +1 1 +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.o_smi_data_out_SB_DFFNR_Q_D_SB_LUT4_O_2_I3[2] +1 1 +.names $true lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[0] +1 1 +.names lvds_tx_inst.r_gap_frame_count[0] lvds_tx_inst.r_gap_frame_count_SB_DFFER_Q_D_SB_LUT4_O_I3[1] +1 1 +.names $true lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[0] +1 1 +.names lvds_tx_inst.r_phase_count[0] lvds_tx_inst.r_phase_count_SB_DFFS_Q_D_SB_LUT4_O_I3[1] +1 1 +.names $false rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[0] +1 1 +.names rx_fifo.wr_addr[0] rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[1] +1 1 +.names $false rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[0] +1 1 +.names rx_fifo.wr_addr[1] rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[1] +1 1 +.names $false rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[0] +1 1 +.names rx_fifo.rd_addr[0] rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[1] +1 1 +.names smi_ctrl_ins.int_cnt_rx[4] smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_1_D[1] +1 1 +.names smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_1_D[0] smi_ctrl_ins.int_cnt_rx_SB_DFFNR_Q_D[0] +1 1 +.names $false spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.spi.r_rx_bit_count[0] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[1] +1 1 +.names spi_if_ins.spi.r_rx_bit_count[1] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[1] +1 1 +.names spi_if_ins.spi.r_rx_bit_count[2] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[2] +1 1 +.names spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D[0] spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D[0] +1 1 +.names $true spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +1 1 +.names spi_if_ins.spi.r_tx_bit_count[0] spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] +1 1 +.names $false tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[0] +1 1 +.names tx_fifo.wr_addr[0] tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[1] +1 1 +.names $false tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +1 1 +.names tx_fifo.wr_addr[1] tx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +1 1 +.names $false tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[0] +1 1 +.names tx_fifo.rd_addr[0] tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[1] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[0] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[1] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[2] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[4] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[5] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[7] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[8] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[10] +1 1 +.names $false spi_if_ins.o_cs_SB_DFFESR_Q_D[11] +1 1 +.names tx_fifo.rd_data_o[8] tx_fifo.mem_q.0.2_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[10] tx_fifo.mem_q.0.2_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[9] tx_fifo.mem_q.0.2_RDATA[9] +1 1 +.names tx_fifo.rd_data_o[11] tx_fifo.mem_q.0.2_RDATA[13] +1 1 +.names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[5] rx_fifo.mem_q.0.1_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[7] rx_fifo.mem_q.0.1_RDATA[13] 1 1 .names rx_fifo.rd_data_o[0] rx_fifo.mem_q.0.0_RDATA[1] 1 1 @@ -4252,13 +5352,37 @@ 1 1 .names rx_fifo.rd_data_o[3] rx_fifo.mem_q.0.0_RDATA[13] 1 1 -.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1] +.names tx_fifo.rd_data_o[28] tx_fifo.mem_i.0.3_RDATA[1] 1 1 -.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5] +.names tx_fifo.rd_data_o[30] tx_fifo.mem_i.0.3_RDATA[5] 1 1 -.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9] +.names tx_fifo.rd_data_o[29] tx_fifo.mem_i.0.3_RDATA[9] 1 1 -.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13] +.names tx_fifo.rd_data_o[31] tx_fifo.mem_i.0.3_RDATA[13] +1 1 +.names rx_fifo.rd_data_o[8] rx_fifo.mem_q.0.2_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[10] rx_fifo.mem_q.0.2_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[9] rx_fifo.mem_q.0.2_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[11] rx_fifo.mem_q.0.2_RDATA[13] +1 1 +.names tx_fifo.rd_data_o[0] tx_fifo.mem_q.0.0_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[2] tx_fifo.mem_q.0.0_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[1] tx_fifo.mem_q.0.0_RDATA[9] +1 1 +.names tx_fifo.rd_data_o[3] tx_fifo.mem_q.0.0_RDATA[13] +1 1 +.names rx_fifo.rd_data_o[12] rx_fifo.mem_q.0.3_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[14] rx_fifo.mem_q.0.3_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[13] rx_fifo.mem_q.0.3_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[15] rx_fifo.mem_q.0.3_RDATA[13] 1 1 .names rx_fifo.rd_data_o[28] rx_fifo.mem_i.0.3_RDATA[1] 1 1 @@ -4268,21 +5392,71 @@ 1 1 .names rx_fifo.rd_data_o[31] rx_fifo.mem_i.0.3_RDATA[13] 1 1 -.names rx_fifo.rd_data_o[4] rx_fifo.mem_q.0.1_RDATA[1] +.names rx_fifo.rd_data_o[20] rx_fifo.mem_i.0.1_RDATA[1] 1 1 -.names rx_fifo.rd_data_o[6] rx_fifo.mem_q.0.1_RDATA[5] +.names rx_fifo.rd_data_o[22] rx_fifo.mem_i.0.1_RDATA[5] 1 1 -.names rx_fifo.rd_data_o[5] rx_fifo.mem_q.0.1_RDATA[9] +.names rx_fifo.rd_data_o[21] rx_fifo.mem_i.0.1_RDATA[9] 1 1 -.names rx_fifo.rd_data_o[7] rx_fifo.mem_q.0.1_RDATA[13] +.names rx_fifo.rd_data_o[23] rx_fifo.mem_i.0.1_RDATA[13] +1 1 +.names rx_fifo.rd_data_o[24] rx_fifo.mem_i.0.2_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[26] rx_fifo.mem_i.0.2_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[25] rx_fifo.mem_i.0.2_RDATA[9] +1 1 +.names rx_fifo.rd_data_o[27] rx_fifo.mem_i.0.2_RDATA[13] +1 1 +.names tx_fifo.rd_data_o[16] tx_fifo.mem_i.0.0_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[18] tx_fifo.mem_i.0.0_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[17] tx_fifo.mem_i.0.0_RDATA[9] +1 1 +.names tx_fifo.rd_data_o[19] tx_fifo.mem_i.0.0_RDATA[13] +1 1 +.names tx_fifo.rd_data_o[4] tx_fifo.mem_q.0.1_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[6] tx_fifo.mem_q.0.1_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[5] tx_fifo.mem_q.0.1_RDATA[9] +1 1 +.names tx_fifo.rd_data_o[7] tx_fifo.mem_q.0.1_RDATA[13] +1 1 +.names tx_fifo.rd_data_o[20] tx_fifo.mem_i.0.1_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[22] tx_fifo.mem_i.0.1_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[21] tx_fifo.mem_i.0.1_RDATA[9] +1 1 +.names tx_fifo.rd_data_o[23] tx_fifo.mem_i.0.1_RDATA[13] +1 1 +.names tx_fifo.rd_data_o[24] tx_fifo.mem_i.0.2_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[26] tx_fifo.mem_i.0.2_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[25] tx_fifo.mem_i.0.2_RDATA[9] +1 1 +.names tx_fifo.rd_data_o[27] tx_fifo.mem_i.0.2_RDATA[13] +1 1 +.names tx_fifo.rd_data_o[12] tx_fifo.mem_q.0.3_RDATA[1] +1 1 +.names tx_fifo.rd_data_o[14] tx_fifo.mem_q.0.3_RDATA[5] +1 1 +.names tx_fifo.rd_data_o[13] tx_fifo.mem_q.0.3_RDATA[9] 1 1 -.names o_led1_SB_LUT4_I1_I2[2] io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[1] +.names tx_fifo.rd_data_o[15] tx_fifo.mem_q.0.3_RDATA[13] 1 1 -.names lvds_tx_inst.r_pulled lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[0] +.names rx_fifo.rd_data_o[16] rx_fifo.mem_i.0.0_RDATA[1] +1 1 +.names rx_fifo.rd_data_o[18] rx_fifo.mem_i.0.0_RDATA[5] +1 1 +.names rx_fifo.rd_data_o[17] rx_fifo.mem_i.0.0_RDATA[9] 1 1 -.names tx_fifo.rd_addr_gray[9] lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1] +.names rx_fifo.rd_data_o[19] rx_fifo.mem_i.0.0_RDATA[13] 1 1 -.names tx_fifo.wr_addr_gray_rd_r[9] lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2] +.names smi_ctrl_ins.r_channel channel 1 1 .names spi_if_ins.spi.o_spi_miso int_miso 1 1 @@ -4330,26 +5504,14 @@ 1 1 .names r_counter io_ctrl_ins.i_sys_clk 1 1 -.names o_led0 io_ctrl_ins.led0_state -1 1 -.names o_led1 io_ctrl_ins.led1_state -1 1 -.names o_led0 io_ctrl_ins.o_led0 +.names io_ctrl_ins.led0_state io_ctrl_ins.o_led0 1 1 -.names o_led1 io_ctrl_ins.o_led1 +.names io_ctrl_ins.led1_state io_ctrl_ins.o_led1 1 1 .names $true io_ctrl_ins.o_mixer_en 1 1 .names $false io_ctrl_ins.o_mixer_fm 1 1 -.names io_ctrl_ins.pmod_state[0] io_ctrl_ins.o_pmod[0] -1 1 -.names io_ctrl_ins.pmod_state[1] io_ctrl_ins.o_pmod[1] -1 1 -.names io_ctrl_ins.pmod_state[2] io_ctrl_ins.o_pmod[2] -1 1 -.names io_ctrl_ins.pmod_state[3] io_ctrl_ins.o_pmod[3] -1 1 .names io_ctrl_ins.rx_h_state io_ctrl_ins.o_rx_h_tx_l 1 1 .names io_ctrl_ins.rx_h_b_state io_ctrl_ins.o_rx_h_tx_l_b @@ -4364,17 +5526,15 @@ 1 1 .names io_ctrl_ins.tr_vc_2_state io_ctrl_ins.o_tr_vc2 1 1 -.names io_ctrl_ins.pmod_state[0] io_pmod_out[0] +.names $undef io_pmod_out[0] 1 1 -.names io_ctrl_ins.pmod_state[1] io_pmod_out[1] +.names $undef io_pmod_out[1] 1 1 -.names io_ctrl_ins.pmod_state[2] io_pmod_out[2] +.names $undef io_pmod_out[2] 1 1 -.names io_ctrl_ins.pmod_state[3] io_pmod_out[3] +.names $undef io_pmod_out[3] 1 1 -.names lvds_clock lvds_clock_buf -1 1 -.names lvds_clock lvds_rx_09_inst.i_ddr_clk +.names lvds_rx_09_inst.i_ddr_clk lvds_clock_buf 1 1 .names w_lvds_rx_09_d1 lvds_rx_09_inst.i_ddr_data[0] 1 1 @@ -4384,107 +5544,143 @@ 1 1 .names i_rst_b lvds_rx_09_inst.i_rst_b 1 1 -.names lvds_clock lvds_rx_09_inst.o_fifo_write_clk +.names lvds_rx_09_inst.r_state_if[0] lvds_rx_09_inst.o_debug_state[0] +1 1 +.names lvds_rx_09_inst.r_state_if[1] lvds_rx_09_inst.o_debug_state[1] 1 1 -.names lvds_clock lvds_rx_24_inst.i_ddr_clk +.names lvds_rx_09_inst.i_ddr_clk lvds_rx_09_inst.o_fifo_write_clk +1 1 +.names lvds_rx_09_inst.i_ddr_clk lvds_rx_24_inst.i_ddr_clk 1 1 .names rx_fifo.full_o lvds_rx_24_inst.i_fifo_full 1 1 .names i_rst_b lvds_rx_24_inst.i_rst_b 1 1 -.names lvds_clock lvds_rx_24_inst.o_fifo_write_clk +.names lvds_rx_24_inst.r_state_if[0] lvds_rx_24_inst.o_debug_state[0] +1 1 +.names lvds_rx_24_inst.r_state_if[1] lvds_rx_24_inst.o_debug_state[1] +1 1 +.names lvds_rx_09_inst.i_ddr_clk lvds_rx_24_inst.o_fifo_write_clk +1 1 +.names $undef lvds_tx_inst.INIT +1 1 +.names $false lvds_tx_inst.debug_lb_d1 +1 1 +.names $false lvds_tx_inst.debug_lb_d2 +1 1 +.names lvds_rx_09_inst.i_ddr_clk lvds_tx_inst.i_ddr_clk +1 1 +.names $undef lvds_tx_inst.i_debug_lb +1 1 +.names tx_fifo.rd_data_o[0] lvds_tx_inst.i_fifo_data[0] +1 1 +.names tx_fifo.rd_data_o[1] lvds_tx_inst.i_fifo_data[1] +1 1 +.names tx_fifo.rd_data_o[2] lvds_tx_inst.i_fifo_data[2] +1 1 +.names tx_fifo.rd_data_o[3] lvds_tx_inst.i_fifo_data[3] +1 1 +.names tx_fifo.rd_data_o[4] lvds_tx_inst.i_fifo_data[4] +1 1 +.names tx_fifo.rd_data_o[5] lvds_tx_inst.i_fifo_data[5] +1 1 +.names tx_fifo.rd_data_o[6] lvds_tx_inst.i_fifo_data[6] +1 1 +.names tx_fifo.rd_data_o[7] lvds_tx_inst.i_fifo_data[7] +1 1 +.names tx_fifo.rd_data_o[8] lvds_tx_inst.i_fifo_data[8] 1 1 -.names lvds_clock lvds_tx_inst.i_ddr_clk +.names tx_fifo.rd_data_o[9] lvds_tx_inst.i_fifo_data[9] 1 1 -.names $undef lvds_tx_inst.i_debug_lb +.names tx_fifo.rd_data_o[10] lvds_tx_inst.i_fifo_data[10] 1 1 -.names i_rst_b lvds_tx_inst.i_rst_b +.names tx_fifo.rd_data_o[11] lvds_tx_inst.i_fifo_data[11] 1 1 -.names $undef lvds_tx_inst.i_sample_gap[0] +.names tx_fifo.rd_data_o[12] lvds_tx_inst.i_fifo_data[12] 1 1 -.names $undef lvds_tx_inst.i_sample_gap[1] +.names tx_fifo.rd_data_o[13] lvds_tx_inst.i_fifo_data[13] 1 1 -.names $undef lvds_tx_inst.i_sample_gap[2] +.names tx_fifo.rd_data_o[14] lvds_tx_inst.i_fifo_data[14] 1 1 -.names $undef lvds_tx_inst.i_sample_gap[3] +.names tx_fifo.rd_data_o[15] lvds_tx_inst.i_fifo_data[15] 1 1 -.names $false lvds_tx_inst.o_ddr_data[0] +.names tx_fifo.rd_data_o[16] lvds_tx_inst.i_fifo_data[16] 1 1 -.names $false lvds_tx_inst.o_ddr_data[1] +.names tx_fifo.rd_data_o[17] lvds_tx_inst.i_fifo_data[17] 1 1 -.names lvds_tx_inst.r_pulled lvds_tx_inst.o_fifo_pull +.names tx_fifo.rd_data_o[18] lvds_tx_inst.i_fifo_data[18] 1 1 -.names lvds_clock lvds_tx_inst.o_fifo_read_clk +.names tx_fifo.rd_data_o[19] lvds_tx_inst.i_fifo_data[19] 1 1 -.names $false lvds_tx_inst.o_sync_state_bit +.names tx_fifo.rd_data_o[20] lvds_tx_inst.i_fifo_data[20] 1 1 -.names $false lvds_tx_inst.o_tx_state_bit +.names tx_fifo.rd_data_o[21] lvds_tx_inst.i_fifo_data[21] 1 1 -.names $false lvds_tx_inst.r_fifo_data[0] +.names tx_fifo.rd_data_o[22] lvds_tx_inst.i_fifo_data[22] 1 1 -.names $false lvds_tx_inst.r_fifo_data[1] +.names tx_fifo.rd_data_o[23] lvds_tx_inst.i_fifo_data[23] 1 1 -.names $false lvds_tx_inst.r_fifo_data[2] +.names tx_fifo.rd_data_o[24] lvds_tx_inst.i_fifo_data[24] 1 1 -.names $false lvds_tx_inst.r_fifo_data[3] +.names tx_fifo.rd_data_o[25] lvds_tx_inst.i_fifo_data[25] 1 1 -.names $false lvds_tx_inst.r_fifo_data[4] +.names tx_fifo.rd_data_o[26] lvds_tx_inst.i_fifo_data[26] 1 1 -.names $false lvds_tx_inst.r_fifo_data[5] +.names tx_fifo.rd_data_o[27] lvds_tx_inst.i_fifo_data[27] 1 1 -.names $false lvds_tx_inst.r_fifo_data[6] +.names tx_fifo.rd_data_o[28] lvds_tx_inst.i_fifo_data[28] 1 1 -.names $false lvds_tx_inst.r_fifo_data[7] +.names tx_fifo.rd_data_o[29] lvds_tx_inst.i_fifo_data[29] 1 1 -.names $false lvds_tx_inst.r_fifo_data[8] +.names tx_fifo.rd_data_o[30] lvds_tx_inst.i_fifo_data[30] 1 1 -.names $false lvds_tx_inst.r_fifo_data[9] +.names tx_fifo.rd_data_o[31] lvds_tx_inst.i_fifo_data[31] 1 1 -.names $false lvds_tx_inst.r_fifo_data[10] +.names tx_fifo.empty_o lvds_tx_inst.i_fifo_empty 1 1 -.names $false lvds_tx_inst.r_fifo_data[11] +.names i_rst_b lvds_tx_inst.i_rst_b 1 1 -.names $false lvds_tx_inst.r_fifo_data[12] +.names $undef lvds_tx_inst.i_sample_gap[0] 1 1 -.names $false lvds_tx_inst.r_fifo_data[13] +.names $undef lvds_tx_inst.i_sample_gap[1] 1 1 -.names $false lvds_tx_inst.r_fifo_data[14] +.names $undef lvds_tx_inst.i_sample_gap[2] 1 1 -.names $false lvds_tx_inst.r_fifo_data[15] +.names $undef lvds_tx_inst.i_sample_gap[3] 1 1 -.names $false lvds_tx_inst.r_fifo_data[16] +.names w_lvds_tx_d1 lvds_tx_inst.o_ddr_data[0] 1 1 -.names $false lvds_tx_inst.r_fifo_data[17] +.names w_lvds_tx_d0 lvds_tx_inst.o_ddr_data[1] 1 1 -.names $false lvds_tx_inst.r_fifo_data[18] +.names lvds_tx_inst.r_pulled lvds_tx_inst.o_fifo_pull 1 1 -.names $false lvds_tx_inst.r_fifo_data[19] +.names lvds_rx_09_inst.i_ddr_clk lvds_tx_inst.o_fifo_read_clk 1 1 -.names $false lvds_tx_inst.r_fifo_data[20] +.names lvds_tx_inst.r_state[0] lvds_tx_inst.o_tx_fsm_state[0] 1 1 -.names $false lvds_tx_inst.r_fifo_data[21] +.names lvds_tx_inst.r_state[1] lvds_tx_inst.o_tx_fsm_state[1] 1 1 -.names $false lvds_tx_inst.r_fifo_data[22] +.names $false lvds_tx_inst.o_tx_fsm_state[2] 1 1 -.names $false lvds_tx_inst.r_fifo_data[23] +.names $false lvds_tx_inst.r_debug_lb 1 1 -.names $false lvds_tx_inst.r_fifo_data[24] +.names lvds_tx_inst.fifo_empty_d2 lvds_tx_inst.r_fifo_empty 1 1 -.names $false lvds_tx_inst.r_fifo_data[25] +.names $false lvds_tx_inst.r_sample_gap[0] 1 1 -.names $false lvds_tx_inst.r_fifo_data[26] +.names $false lvds_tx_inst.r_sample_gap[1] 1 1 -.names $false lvds_tx_inst.r_fifo_data[27] +.names $false lvds_tx_inst.r_sample_gap[2] 1 1 -.names $false lvds_tx_inst.r_fifo_data[28] +.names $false lvds_tx_inst.r_sample_gap[3] 1 1 -.names $false lvds_tx_inst.r_fifo_data[29] +.names $false lvds_tx_inst.r_state[2] 1 1 -.names $false lvds_tx_inst.r_fifo_data[30] +.names lvds_tx_inst.tx_state_d2 lvds_tx_inst.r_tx_state 1 1 -.names $false lvds_tx_inst.r_fifo_data[31] +.names io_ctrl_ins.led0_state o_led0 1 1 -.names $false lvds_tx_inst.r_state +.names io_ctrl_ins.led1_state o_led1 1 1 .names $undef o_mixer_en 1 1 @@ -4498,7 +5694,7 @@ 1 1 .names io_ctrl_ins.lna_tx_shutdown_state o_shdn_tx_lna 1 1 -.names i_smi_swe_srw o_smi_write_req +.names $undef o_smi_write_req 1 1 .names io_ctrl_ins.tr_vc_1_state o_tr_vc1 1 1 @@ -4514,10 +5710,30 @@ 1 1 .names rx_fifo.wr_addr_gray[9] rx_fifo.wr_addr[9] 1 1 -.names lvds_clock rx_fifo.wr_clk_i +.names lvds_rx_09_inst.i_ddr_clk rx_fifo.wr_clk_i 1 1 .names i_rst_b rx_fifo.wr_rst_b_i 1 1 +.names $undef smi_ctrl_ins.frame_sr[5] +1 1 +.names $undef smi_ctrl_ins.frame_sr[6] +1 1 +.names $undef smi_ctrl_ins.frame_sr[24] +1 1 +.names $undef smi_ctrl_ins.frame_sr[25] +1 1 +.names $undef smi_ctrl_ins.frame_sr[26] +1 1 +.names $undef smi_ctrl_ins.frame_sr[27] +1 1 +.names $undef smi_ctrl_ins.frame_sr[28] +1 1 +.names $undef smi_ctrl_ins.frame_sr[29] +1 1 +.names $undef smi_ctrl_ins.frame_sr[30] +1 1 +.names $undef smi_ctrl_ins.frame_sr[31] +1 1 .names spi_if_ins.o_data_in[0] smi_ctrl_ins.i_data_in[0] 1 1 .names spi_if_ins.o_data_in[1] smi_ctrl_ins.i_data_in[1] @@ -4614,20 +5830,6 @@ 1 1 .names rx_fifo.rd_data_o[31] smi_ctrl_ins.i_rx_fifo_pulled_data[31] 1 1 -.names w_smi_data_input[0] smi_ctrl_ins.i_smi_data_in[0] -1 1 -.names w_smi_data_input[1] smi_ctrl_ins.i_smi_data_in[1] -1 1 -.names w_smi_data_input[2] smi_ctrl_ins.i_smi_data_in[2] -1 1 -.names w_smi_data_input[3] smi_ctrl_ins.i_smi_data_in[3] -1 1 -.names w_smi_data_input[4] smi_ctrl_ins.i_smi_data_in[4] -1 1 -.names w_smi_data_input[5] smi_ctrl_ins.i_smi_data_in[5] -1 1 -.names w_smi_data_input[6] smi_ctrl_ins.i_smi_data_in[6] -1 1 .names i_smi_soe_se smi_ctrl_ins.i_smi_soe_se 1 1 .names i_smi_swe_srw smi_ctrl_ins.i_smi_swe_srw @@ -4642,36 +5844,10 @@ 1 1 .names $false smi_ctrl_ins.int_cnt_rx[2] 1 1 -.names $false smi_ctrl_ins.int_cnt_tx[0] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[1] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[2] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[3] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[4] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[5] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[6] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[7] -1 1 -.names $false smi_ctrl_ins.int_cnt_tx[8] -1 1 -.names $undef smi_ctrl_ins.int_cnt_tx[9] -1 1 -.names $undef smi_ctrl_ins.int_cnt_tx[10] -1 1 -.names $undef smi_ctrl_ins.int_cnt_tx[11] -1 1 -.names $undef smi_ctrl_ins.int_cnt_tx[12] +.names smi_ctrl_ins.r_channel smi_ctrl_ins.o_channel 1 1 .names $false smi_ctrl_ins.o_data_out[3] 1 1 -.names $false smi_ctrl_ins.o_data_out[4] -1 1 .names $false smi_ctrl_ins.o_data_out[5] 1 1 .names $false smi_ctrl_ins.o_data_out[6] @@ -4680,73 +5856,23 @@ 1 1 .names smi_ctrl_ins.r_dir smi_ctrl_ins.o_dir 1 1 +.names rx_fifo.rd_en_i smi_ctrl_ins.o_rx_fifo_pull +1 1 .names w_smi_read_req smi_ctrl_ins.o_smi_read_req 1 1 .names r_counter smi_ctrl_ins.o_tx_fifo_clock 1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[0] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[1] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[2] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[3] +.names smi_ctrl_ins.push_pulse smi_ctrl_ins.o_tx_fifo_push 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[4] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[5] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[6] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[7] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[8] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[9] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[10] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[11] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[12] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[13] +.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[0] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[14] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] smi_ctrl_ins.o_tx_fifo_pushed_data[14] 1 1 .names $false smi_ctrl_ins.o_tx_fifo_pushed_data[15] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[16] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[17] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[18] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[19] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[20] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[21] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[22] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[23] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[24] -1 1 -.names $false smi_ctrl_ins.o_tx_fifo_pushed_data[25] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[26] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[27] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[28] -1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[29] -1 1 .names $false smi_ctrl_ins.o_tx_fifo_pushed_data[30] 1 1 -.names $undef smi_ctrl_ins.o_tx_fifo_pushed_data[31] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] smi_ctrl_ins.o_tx_fifo_pushed_data[31] 1 1 .names r_tx_data[0] spi_if_ins.i_data_out[0] 1 1 @@ -4864,6 +5990,14 @@ 1 1 .names $undef sys_ctrl_ins.o_debug_loopback_tx 1 1 +.names sys_ctrl_ins.rx_sync_09 sys_ctrl_ins.o_rx_sync_09 +1 1 +.names sys_ctrl_ins.rx_sync_24 sys_ctrl_ins.o_rx_sync_24 +1 1 +.names sys_ctrl_ins.rx_sync_type09 sys_ctrl_ins.o_rx_sync_type09 +1 1 +.names sys_ctrl_ins.rx_sync_type24 sys_ctrl_ins.o_rx_sync_type24 +1 1 .names $undef sys_ctrl_ins.o_tx_sample_gap[0] 1 1 .names $undef sys_ctrl_ins.o_tx_sample_gap[1] @@ -4872,8 +6006,78 @@ 1 1 .names $undef sys_ctrl_ins.o_tx_sample_gap[3] 1 1 +.names sys_ctrl_ins.tx_sync_type09 sys_ctrl_ins.o_tx_sync_type09 +1 1 +.names sys_ctrl_ins.tx_sync_type24 sys_ctrl_ins.o_tx_sync_type24 +1 1 +.names $false tp_data[0] +1 1 +.names $undef tp_data[1] +1 1 +.names $undef tp_data[2] +1 1 +.names $undef tp_data[3] +1 1 +.names $undef tp_data[4] +1 1 +.names $undef tp_data[5] +1 1 +.names $undef tp_data[6] +1 1 +.names $undef tp_data[7] +1 1 +.names $undef tp_data[8] +1 1 +.names $undef tp_data[9] +1 1 +.names $undef tp_data[10] +1 1 +.names $undef tp_data[11] +1 1 +.names $undef tp_data[12] +1 1 +.names $undef tp_data[13] +1 1 +.names $true tp_data[14] +1 1 +.names $false tp_data[15] +1 1 +.names $true tp_data[16] +1 1 +.names $undef tp_data[17] +1 1 +.names $undef tp_data[18] +1 1 +.names $undef tp_data[19] +1 1 +.names $undef tp_data[20] +1 1 +.names $undef tp_data[21] +1 1 +.names $undef tp_data[22] +1 1 +.names $undef tp_data[23] +1 1 +.names $undef tp_data[24] +1 1 +.names $undef tp_data[25] +1 1 +.names $undef tp_data[26] +1 1 +.names $undef tp_data[27] +1 1 +.names $undef tp_data[28] +1 1 +.names $undef tp_data[29] +1 1 +.names $false tp_data[30] +1 1 +.names $true tp_data[31] +1 1 .names tx_fifo.rd_addr_gray[9] tx_fifo.rd_addr[9] 1 1 +.names lvds_rx_09_inst.i_ddr_clk tx_fifo.rd_clk_i +1 1 .names lvds_tx_inst.r_pulled tx_fifo.rd_en_i 1 1 .names i_rst_b tx_fifo.rd_rst_b_i @@ -4884,67 +6088,69 @@ 1 1 .names $false tx_fifo.wr_data_i[0] 1 1 -.names $undef tx_fifo.wr_data_i[1] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[1] tx_fifo.wr_data_i[1] 1 1 -.names $undef tx_fifo.wr_data_i[2] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[2] tx_fifo.wr_data_i[2] 1 1 -.names $undef tx_fifo.wr_data_i[3] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[3] tx_fifo.wr_data_i[3] 1 1 -.names $undef tx_fifo.wr_data_i[4] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[4] tx_fifo.wr_data_i[4] 1 1 -.names $undef tx_fifo.wr_data_i[5] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[5] tx_fifo.wr_data_i[5] 1 1 -.names $undef tx_fifo.wr_data_i[6] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[6] tx_fifo.wr_data_i[6] 1 1 -.names $false tx_fifo.wr_data_i[7] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[7] tx_fifo.wr_data_i[7] 1 1 -.names $false tx_fifo.wr_data_i[8] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[8] tx_fifo.wr_data_i[8] 1 1 -.names $false tx_fifo.wr_data_i[9] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[9] tx_fifo.wr_data_i[9] 1 1 -.names $false tx_fifo.wr_data_i[10] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[10] tx_fifo.wr_data_i[10] 1 1 -.names $false tx_fifo.wr_data_i[11] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[11] tx_fifo.wr_data_i[11] 1 1 -.names $false tx_fifo.wr_data_i[12] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[12] tx_fifo.wr_data_i[12] 1 1 -.names $false tx_fifo.wr_data_i[13] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[13] tx_fifo.wr_data_i[13] 1 1 -.names $undef tx_fifo.wr_data_i[14] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] tx_fifo.wr_data_i[14] 1 1 .names $false tx_fifo.wr_data_i[15] 1 1 -.names $undef tx_fifo.wr_data_i[16] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] tx_fifo.wr_data_i[16] 1 1 -.names $false tx_fifo.wr_data_i[17] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[17] tx_fifo.wr_data_i[17] 1 1 -.names $false tx_fifo.wr_data_i[18] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[18] tx_fifo.wr_data_i[18] 1 1 -.names $false tx_fifo.wr_data_i[19] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[19] tx_fifo.wr_data_i[19] 1 1 -.names $false tx_fifo.wr_data_i[20] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[20] tx_fifo.wr_data_i[20] 1 1 -.names $false tx_fifo.wr_data_i[21] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[21] tx_fifo.wr_data_i[21] 1 1 -.names $false tx_fifo.wr_data_i[22] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[22] tx_fifo.wr_data_i[22] 1 1 -.names $false tx_fifo.wr_data_i[23] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[23] tx_fifo.wr_data_i[23] 1 1 -.names $false tx_fifo.wr_data_i[24] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[24] tx_fifo.wr_data_i[24] 1 1 -.names $false tx_fifo.wr_data_i[25] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[25] tx_fifo.wr_data_i[25] 1 1 -.names $undef tx_fifo.wr_data_i[26] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[26] tx_fifo.wr_data_i[26] 1 1 -.names $undef tx_fifo.wr_data_i[27] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[27] tx_fifo.wr_data_i[27] 1 1 -.names $undef tx_fifo.wr_data_i[28] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[28] tx_fifo.wr_data_i[28] 1 1 -.names $undef tx_fifo.wr_data_i[29] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[29] tx_fifo.wr_data_i[29] 1 1 .names $false tx_fifo.wr_data_i[30] 1 1 -.names $undef tx_fifo.wr_data_i[31] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] tx_fifo.wr_data_i[31] +1 1 +.names smi_ctrl_ins.push_pulse tx_fifo.wr_en_i 1 1 .names i_rst_b tx_fifo.wr_rst_b_i 1 1 @@ -4956,6 +6162,98 @@ 1 1 .names $undef tx_sample_gap[3] 1 1 +.names $undef tx_test_cntr[0] +1 1 +.names $undef tx_test_cntr[1] +1 1 +.names $undef tx_test_cntr[2] +1 1 +.names $undef tx_test_cntr[3] +1 1 +.names $undef tx_test_cntr[4] +1 1 +.names $undef tx_test_cntr[5] +1 1 +.names $undef tx_test_cntr[6] +1 1 +.names $undef tx_test_cntr[7] +1 1 +.names $undef tx_test_cntr[8] +1 1 +.names $undef tx_test_cntr[9] +1 1 +.names $undef tx_test_cntr[10] +1 1 +.names $undef tx_test_cntr[11] +1 1 +.names $undef tx_test_cntr[12] +1 1 +.names $false tx_wr_data[0] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[1] tx_wr_data[1] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[2] tx_wr_data[2] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[3] tx_wr_data[3] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[4] tx_wr_data[4] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[5] tx_wr_data[5] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[6] tx_wr_data[6] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[7] tx_wr_data[7] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[8] tx_wr_data[8] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[9] tx_wr_data[9] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[10] tx_wr_data[10] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[11] tx_wr_data[11] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[12] tx_wr_data[12] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[13] tx_wr_data[13] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] tx_wr_data[14] +1 1 +.names $false tx_wr_data[15] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] tx_wr_data[16] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[17] tx_wr_data[17] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[18] tx_wr_data[18] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[19] tx_wr_data[19] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[20] tx_wr_data[20] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[21] tx_wr_data[21] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[22] tx_wr_data[22] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[23] tx_wr_data[23] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[24] tx_wr_data[24] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[25] tx_wr_data[25] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[26] tx_wr_data[26] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[27] tx_wr_data[27] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[28] tx_wr_data[28] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[29] tx_wr_data[29] +1 1 +.names $false tx_wr_data[30] +1 1 +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] tx_wr_data[31] +1 1 +.names smi_ctrl_ins.push_pulse tx_wr_en +1 1 .names r_counter w_clock_sys 1 1 .names sys_ctrl_ins.i_cs w_cs[0] @@ -4982,10 +6280,6 @@ 1 1 .names spi_if_ins.o_load_cmd w_load 1 1 -.names $false w_lvds_tx_d0 -1 1 -.names $false w_lvds_tx_d1 -1 1 .names lvds_rx_09_inst.o_fifo_data[0] w_rx_09_fifo_data[0] 1 1 .names lvds_rx_09_inst.o_fifo_data[1] w_rx_09_fifo_data[1] @@ -5050,7 +6344,9 @@ 1 1 .names lvds_rx_09_inst.o_fifo_data[31] w_rx_09_fifo_data[31] 1 1 -.names lvds_clock w_rx_09_fifo_write_clk +.names lvds_rx_09_inst.o_fifo_push w_rx_09_fifo_push +1 1 +.names lvds_rx_09_inst.i_ddr_clk w_rx_09_fifo_write_clk 1 1 .names lvds_rx_24_inst.o_fifo_data[0] w_rx_24_fifo_data[0] 1 1 @@ -5116,7 +6412,9 @@ 1 1 .names lvds_rx_24_inst.o_fifo_data[31] w_rx_24_fifo_data[31] 1 1 -.names lvds_clock w_rx_24_fifo_write_clk +.names lvds_rx_24_inst.o_fifo_push w_rx_24_fifo_push +1 1 +.names lvds_rx_09_inst.i_ddr_clk w_rx_24_fifo_write_clk 1 1 .names spi_if_ins.o_data_in[0] w_rx_data[0] 1 1 @@ -5134,8 +6432,74 @@ 1 1 .names spi_if_ins.o_data_in[7] w_rx_data[7] 1 1 +.names rx_fifo.wr_data_i[0] w_rx_fifo_data[0] +1 1 +.names rx_fifo.wr_data_i[1] w_rx_fifo_data[1] +1 1 +.names rx_fifo.wr_data_i[2] w_rx_fifo_data[2] +1 1 +.names rx_fifo.wr_data_i[3] w_rx_fifo_data[3] +1 1 +.names rx_fifo.wr_data_i[4] w_rx_fifo_data[4] +1 1 +.names rx_fifo.wr_data_i[5] w_rx_fifo_data[5] +1 1 +.names rx_fifo.wr_data_i[6] w_rx_fifo_data[6] +1 1 +.names rx_fifo.wr_data_i[7] w_rx_fifo_data[7] +1 1 +.names rx_fifo.wr_data_i[8] w_rx_fifo_data[8] +1 1 +.names rx_fifo.wr_data_i[9] w_rx_fifo_data[9] +1 1 +.names rx_fifo.wr_data_i[10] w_rx_fifo_data[10] +1 1 +.names rx_fifo.wr_data_i[11] w_rx_fifo_data[11] +1 1 +.names rx_fifo.wr_data_i[12] w_rx_fifo_data[12] +1 1 +.names rx_fifo.wr_data_i[13] w_rx_fifo_data[13] +1 1 +.names rx_fifo.wr_data_i[14] w_rx_fifo_data[14] +1 1 +.names rx_fifo.wr_data_i[15] w_rx_fifo_data[15] +1 1 +.names rx_fifo.wr_data_i[16] w_rx_fifo_data[16] +1 1 +.names rx_fifo.wr_data_i[17] w_rx_fifo_data[17] +1 1 +.names rx_fifo.wr_data_i[18] w_rx_fifo_data[18] +1 1 +.names rx_fifo.wr_data_i[19] w_rx_fifo_data[19] +1 1 +.names rx_fifo.wr_data_i[20] w_rx_fifo_data[20] +1 1 +.names rx_fifo.wr_data_i[21] w_rx_fifo_data[21] +1 1 +.names rx_fifo.wr_data_i[22] w_rx_fifo_data[22] +1 1 +.names rx_fifo.wr_data_i[23] w_rx_fifo_data[23] +1 1 +.names rx_fifo.wr_data_i[24] w_rx_fifo_data[24] +1 1 +.names rx_fifo.wr_data_i[25] w_rx_fifo_data[25] +1 1 +.names rx_fifo.wr_data_i[26] w_rx_fifo_data[26] +1 1 +.names rx_fifo.wr_data_i[27] w_rx_fifo_data[27] +1 1 +.names rx_fifo.wr_data_i[28] w_rx_fifo_data[28] +1 1 +.names rx_fifo.wr_data_i[29] w_rx_fifo_data[29] +1 1 +.names rx_fifo.wr_data_i[30] w_rx_fifo_data[30] +1 1 +.names rx_fifo.wr_data_i[31] w_rx_fifo_data[31] +1 1 .names rx_fifo.full_o w_rx_fifo_full 1 1 +.names rx_fifo.rd_en_i w_rx_fifo_pull +1 1 .names rx_fifo.rd_data_o[0] w_rx_fifo_pulled_data[0] 1 1 .names rx_fifo.rd_data_o[1] w_rx_fifo_pulled_data[1] @@ -5200,14 +6564,38 @@ 1 1 .names rx_fifo.rd_data_o[31] w_rx_fifo_pulled_data[31] 1 1 -.names lvds_clock w_rx_fifo_write_clk +.names rx_fifo.wr_en_i w_rx_fifo_push +1 1 +.names lvds_rx_09_inst.i_ddr_clk w_rx_fifo_write_clk +1 1 +.names sys_ctrl_ins.rx_sync_09 w_rx_sync_09 +1 1 +.names sys_ctrl_ins.rx_sync_24 w_rx_sync_24 1 1 .names lvds_rx_09_inst.i_sync_input w_rx_sync_input_09 1 1 .names lvds_rx_24_inst.i_sync_input w_rx_sync_input_24 1 1 +.names sys_ctrl_ins.rx_sync_type09 w_rx_sync_type_09 +1 1 +.names sys_ctrl_ins.rx_sync_type24 w_rx_sync_type_24 +1 1 .names smi_ctrl_ins.r_dir w_smi_data_direction 1 1 +.names smi_ctrl_ins.i_smi_data_in[0] w_smi_data_input[0] +1 1 +.names smi_ctrl_ins.i_smi_data_in[1] w_smi_data_input[1] +1 1 +.names smi_ctrl_ins.i_smi_data_in[2] w_smi_data_input[2] +1 1 +.names smi_ctrl_ins.i_smi_data_in[3] w_smi_data_input[3] +1 1 +.names smi_ctrl_ins.i_smi_data_in[4] w_smi_data_input[4] +1 1 +.names smi_ctrl_ins.i_smi_data_in[5] w_smi_data_input[5] +1 1 +.names smi_ctrl_ins.i_smi_data_in[6] w_smi_data_input[6] +1 1 .names smi_ctrl_ins.i_smi_data_in[7] w_smi_data_input[7] 1 1 .names smi_ctrl_ins.o_smi_data_out[0] w_smi_data_output[0] @@ -5248,74 +6636,172 @@ 1 1 .names smi_ctrl_ins.o_data_out[2] w_tx_data_smi[2] 1 1 +.names $false w_tx_data_smi[3] +1 1 +.names smi_ctrl_ins.o_data_out[4] w_tx_data_smi[4] +1 1 +.names sys_ctrl_ins.o_data_out[0] w_tx_data_sys[0] +1 1 +.names sys_ctrl_ins.o_data_out[1] w_tx_data_sys[1] +1 1 +.names sys_ctrl_ins.o_data_out[2] w_tx_data_sys[2] +1 1 +.names sys_ctrl_ins.o_data_out[3] w_tx_data_sys[3] +1 1 +.names sys_ctrl_ins.o_data_out[4] w_tx_data_sys[4] +1 1 +.names sys_ctrl_ins.o_data_out[5] w_tx_data_sys[5] +1 1 +.names sys_ctrl_ins.o_data_out[6] w_tx_data_sys[6] +1 1 +.names sys_ctrl_ins.o_data_out[7] w_tx_data_sys[7] +1 1 .names $false w_tx_fifo_data[0] 1 1 -.names $undef w_tx_fifo_data[1] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[1] w_tx_fifo_data[1] 1 1 -.names $undef w_tx_fifo_data[2] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[2] w_tx_fifo_data[2] 1 1 -.names $undef w_tx_fifo_data[3] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[3] w_tx_fifo_data[3] 1 1 -.names $undef w_tx_fifo_data[4] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[4] w_tx_fifo_data[4] 1 1 -.names $undef w_tx_fifo_data[5] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[5] w_tx_fifo_data[5] 1 1 -.names $undef w_tx_fifo_data[6] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[6] w_tx_fifo_data[6] 1 1 -.names $false w_tx_fifo_data[7] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[7] w_tx_fifo_data[7] 1 1 -.names $false w_tx_fifo_data[8] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[8] w_tx_fifo_data[8] 1 1 -.names $false w_tx_fifo_data[9] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[9] w_tx_fifo_data[9] 1 1 -.names $false w_tx_fifo_data[10] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[10] w_tx_fifo_data[10] 1 1 -.names $false w_tx_fifo_data[11] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[11] w_tx_fifo_data[11] 1 1 -.names $false w_tx_fifo_data[12] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[12] w_tx_fifo_data[12] 1 1 -.names $false w_tx_fifo_data[13] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[13] w_tx_fifo_data[13] 1 1 -.names $undef w_tx_fifo_data[14] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] w_tx_fifo_data[14] 1 1 .names $false w_tx_fifo_data[15] 1 1 -.names $undef w_tx_fifo_data[16] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[16] w_tx_fifo_data[16] 1 1 -.names $false w_tx_fifo_data[17] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[17] w_tx_fifo_data[17] 1 1 -.names $false w_tx_fifo_data[18] +.names smi_ctrl_ins.o_tx_fifo_pushed_data[18] w_tx_fifo_data[18] 1 1 -.names $false w_tx_fifo_data[19] +.names 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} }, "spi_if_ins.spi.r_tx_byte": { "hide_name": 0, - "bits": [ 1015, 1014, 1017, 1016, 1011, 1007, 1010, 1006 ], + "bits": [ 1159, 1166, 1162, 1164, 1160, 1167, 1163, 1165 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_byte", - "src": "spi_slave.v:23.13-23.22" + "src": "top.v:134.10-149.4|spi_slave.v:23.13-23.22|spi_if.v:43.13-54.4" } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 987 ], + "bits": [ 1193 ], "attributes": { } }, "spi_if_ins.state_if": { "hide_name": 0, - "bits": [ 967, 966, 960 ], + "bits": [ 1115, 1116, 1114 ], "attributes": { "hdlname": "spi_if_ins state_if", - "src": "spi_if.v:29.14-29.22" + "src": "top.v:134.10-149.4|spi_if.v:29.14-29.22" } }, "spi_if_ins.state_if_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 1044 ], + "bits": [ 1195 ], "attributes": { } }, - "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2": { + "spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I1": { "hide_name": 0, - "bits": [ 962, 963 ], + "bits": [ 1124, 1113 ], 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"hide_name": 0, - "bits": [ 1043 ], + "bits": [ 1194 ], "attributes": { } }, "spi_if_ins.w_rx_data": { "hide_name": 0, - "bits": [ 956, 955, 954, 953, 952, 76, 75, 950 ], + "bits": [ 1108, 1107, 1106, 1105, 1104, 1080, 1079, 1102 ], "attributes": { "hdlname": "spi_if_ins w_rx_data", - "src": "spi_if.v:31.14-31.23" + "src": "top.v:134.10-149.4|spi_if.v:31.14-31.23" } }, "spi_if_ins.w_rx_data_valid": { "hide_name": 0, - "bits": [ 962 ], + "bits": [ 1113 ], "attributes": { "hdlname": "spi_if_ins w_rx_data_valid", - "src": "spi_if.v:30.14-30.29" + "src": "top.v:134.10-149.4|spi_if.v:30.14-30.29" } }, "sys_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 189 ], + "bits": [ 1081 ], "attributes": { "hdlname": "sys_ctrl_ins i_cs", - "src": "sys_ctrl.v:9.29-9.33" + "src": "top.v:155.12-180.4|sys_ctrl.v:9.29-9.33" } }, "sys_ctrl_ins.i_cs_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 74 ], - "attributes": { - } - }, - "sys_ctrl_ins.i_cs_SB_LUT4_I2_I3": { - "hide_name": 0, - "bits": [ 129, 189, 1046 ], + "bits": [ 71, 1617, 1618, 1619 ], "attributes": { "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + "src": "top.v:134.10-149.4|spi_if.v:65.11-70.18|spi_if.v:0.0-0.0|/usr/bin/../share/yosys/techmap.v:575.21-575.22", + "unused_bits": "1 2 3" } }, "sys_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 140, 138, 89, 136, 134, 133, 132, 130 ], + "bits": [ 61, 58, 140, 138, 137, 135, 133, 130 ], "attributes": { "hdlname": "sys_ctrl_ins i_data_in", - "src": "sys_ctrl.v:7.29-7.38" + "src": "top.v:155.12-180.4|sys_ctrl.v:7.29-7.38" } }, "sys_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 129 ], + "bits": [ 72 ], "attributes": { "hdlname": "sys_ctrl_ins i_fetch_cmd", - "src": "sys_ctrl.v:10.29-10.40" + "src": "top.v:155.12-180.4|sys_ctrl.v:10.29-10.40" } }, "sys_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 55, 54, 60, 59, 58 ], + "bits": [ 75, 78, 77, 80, 79 ], "attributes": { "hdlname": "sys_ctrl_ins i_ioc", - "src": "sys_ctrl.v:6.29-6.34" + "src": "top.v:155.12-180.4|sys_ctrl.v:6.29-6.34" } }, "sys_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 146 ], + "bits": [ 83 ], "attributes": { "hdlname": "sys_ctrl_ins i_load_cmd", - "src": "sys_ctrl.v:11.29-11.39" + "src": "top.v:155.12-180.4|sys_ctrl.v:11.29-11.39" } }, "sys_ctrl_ins.i_rst_b": { @@ -40451,15 +44252,71 @@ "bits": [ 3 ], "attributes": { "hdlname": "sys_ctrl_ins i_rst_b", - "src": "sys_ctrl.v:3.29-3.36" + "src": "top.v:155.12-180.4|sys_ctrl.v:3.29-3.36" } }, "sys_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 70 ], + "bits": [ 57 ], "attributes": { "hdlname": "sys_ctrl_ins i_sys_clk", - "src": "sys_ctrl.v:4.29-4.38" + "src": "top.v:155.12-180.4|sys_ctrl.v:4.29-4.38" + } + }, + "sys_ctrl_ins.o_data_out": { + "hide_name": 0, + "bits": [ 1094, 1090, 1086, 1100, 1091, 1098, 1097, 1095 ], + "attributes": { + "hdlname": "sys_ctrl_ins o_data_out", + "src": "top.v:155.12-180.4|sys_ctrl.v:8.29-8.39" + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_1_D": { + "hide_name": 0, + "bits": [ 1199 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_2_D": { + "hide_name": 0, + "bits": [ 1200 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_3_D": { + "hide_name": 0, + "bits": [ 1202 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_4_D": { + "hide_name": 0, + "bits": [ 1203 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_5_D": { + "hide_name": 0, + "bits": [ 1205 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_6_D": { + "hide_name": 0, + "bits": [ 1207 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_7_D": { + "hide_name": 0, + "bits": [ 1209 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_DFFER_Q_D": { + "hide_name": 0, + "bits": [ 1197 ], + "attributes": { } }, "sys_ctrl_ins.o_debug_loopback_tx": { @@ -40467,7 +44324,39 @@ "bits": [ "x" ], "attributes": { "hdlname": "sys_ctrl_ins o_debug_loopback_tx", - "src": "sys_ctrl.v:17.29-17.48" + "src": "top.v:155.12-180.4|sys_ctrl.v:17.29-17.48" + } + }, + "sys_ctrl_ins.o_rx_sync_09": { + "hide_name": 0, + "bits": [ 167 ], + "attributes": { + "hdlname": "sys_ctrl_ins o_rx_sync_09", + "src": "top.v:155.12-180.4|sys_ctrl.v:25.29-25.41" + } + }, + "sys_ctrl_ins.o_rx_sync_24": { + "hide_name": 0, + "bits": [ 258 ], + "attributes": { + "hdlname": "sys_ctrl_ins o_rx_sync_24", + "src": "top.v:155.12-180.4|sys_ctrl.v:26.29-26.41" + } + }, + "sys_ctrl_ins.o_rx_sync_type09": { + "hide_name": 0, + "bits": [ 168 ], + "attributes": { + "hdlname": "sys_ctrl_ins o_rx_sync_type09", + "src": "top.v:155.12-180.4|sys_ctrl.v:20.29-20.45" + } + }, + "sys_ctrl_ins.o_rx_sync_type24": { + "hide_name": 0, + "bits": [ 259 ], + "attributes": { + "hdlname": "sys_ctrl_ins o_rx_sync_type24", + "src": "top.v:155.12-180.4|sys_ctrl.v:21.29-21.45" } }, "sys_ctrl_ins.o_tx_sample_gap": { @@ -40475,547 +44364,659 @@ "bits": [ "x", "x", "x", "x" ], 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"bits": [ 817, 615, 1549, 607 ], "attributes": { "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + "src": "/usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "w_tx_data_io": { "hide_name": 0, - "bits": [ 112, 98, 106, 101, 123, 121, 119, 117 ], + "bits": [ 117, 106, 102, 109, 121, 128, 125, 123 ], "attributes": { "src": "top.v:108.14-108.26" } }, "w_tx_data_smi": { "hide_name": 0, - "bits": [ 417, 410, 804 ], + "bits": [ 978, 976, 974, "0", 972 ], + "attributes": { + } + }, + "w_tx_data_sys": { + "hide_name": 0, + "bits": [ 1094, 1090, 1086, 1100, 1091, 1098, 1097, 1095 ], "attributes": { + "src": "top.v:107.14-107.27" } }, "w_tx_fifo_data": { "hide_name": 0, - "bits": [ "0", "x", "x", "x", "x", "x", "x", "0", "0", "0", "0", "0", "0", "0", "x", "0", "x", "0", "0", "0", "0", "0", "0", "0", "0", "0", "x", "x", "x", "x", "0", "x" ], + "bits": [ "0", 1055, 1054, 1053, 1052, 1051, 1050, 1049, 1047, 1046, 1045, 1044, 1043, 1042, 1041, "0", 1041, 1040, 1039, 1038, 1062, 1061, 1060, 1059, 1058, 1057, 1056, 1048, 1037, 1036, "0", 1041 ], + "attributes": { + "src": "top.v:474.17-474.31" + } + }, + "w_tx_fifo_empty": { + "hide_name": 0, + "bits": [ 352 ], "attributes": { - "src": "top.v:458.15-458.29" + "src": "top.v:471.10-471.25" } }, "w_tx_fifo_full": { "hide_name": 0, - "bits": [ 371 ], + "bits": [ 519 ], "attributes": { - "src": "top.v:454.8-454.22" + "src": "top.v:470.10-470.24" } }, "w_tx_fifo_pull": { "hide_name": 0, - "bits": [ 333 ], + "bits": [ 453 ], + "attributes": { + "src": "top.v:475.10-475.24" + } + }, + "w_tx_fifo_pulled_data": { + "hide_name": 0, + "bits": [ 497, 496, 495, 494, 492, 491, 490, 488, 487, 486, 484, 483, 482, 480, 468, 478, 477, 475, 473, 472, 471, 505, 504, 503, 502, 501, 500, 498, 485, 470, 469, 506 ], + "attributes": { + "src": "top.v:476.17-476.38" + } + }, + "w_tx_fifo_push": { + "hide_name": 0, + "bits": [ 1064 ], "attributes": { - "src": "top.v:459.8-459.22" + "src": "top.v:473.10-473.24" } }, "w_tx_fifo_read_clk": { "hide_name": 0, - "bits": [ 164 ], + "bits": [ 46 ], + "attributes": { + "src": "top.v:472.10-472.28" + } + }, + "w_tx_fsm_state": { + "hide_name": 0, + "bits": [ 356, 355, "0" ], + "attributes": { + "src": "top.v:477.16-477.30" + } + }, + "w_tx_sync_type_09": { + "hide_name": 0, + "bits": [ 1217 ], + "attributes": { + "src": "top.v:113.8-113.25" + } + }, + "w_tx_sync_type_24": { + "hide_name": 0, + "bits": [ 1218 ], "attributes": { - "src": "top.v:456.8-456.26" + "src": "top.v:114.8-114.25" } } } diff --git a/firmware/top.v b/firmware/top.v index b7cd827d..6b46a4f4 100644 --- a/firmware/top.v +++ b/firmware/top.v @@ -162,9 +162,9 @@ module top ( .i_fetch_cmd(w_fetch), .i_load_cmd(w_load), - .o_debug_fifo_push(), - .o_debug_fifo_pull(), - .o_debug_smi_test(), + //.o_debug_fifo_push(), + //.o_debug_fifo_pull(), + //.o_debug_smi_test(), .o_debug_loopback_tx(w_debug_lb_tx), .o_tx_sample_gap(tx_sample_gap), @@ -179,8 +179,8 @@ module top ( .o_tx_sync_24(w_tx_sync_24) ); - wire w_debug_fifo_push; - wire w_debug_fifo_pull; + //wire w_debug_fifo_push; + //wire w_debug_fifo_pull; wire w_debug_lb_tx; wire [3:0] tx_sample_gap; @@ -200,7 +200,7 @@ module top ( .i_config(i_config), .o_led0 (o_led0), .o_led1 (o_led1), - .o_pmod (io_pmod_out[3:0]), + //.o_pmod (io_pmod_out[3:0]), // disabled for sending debug info // Analog interfaces .o_mixer_fm(/*o_mixer_fm*/), @@ -247,7 +247,7 @@ module top ( //--------------------------------------------- // Differential clock signal (DDR) wire lvds_clock; // The direct clock input - wire lvds_clock_buf; // The clock input after global buffer (improved fanout) + //wire lvds_clock_buf; // The clock input after global buffer (improved fanout) SB_IO #( .PIN_TYPE (6'b000001), // Input only, direct mode @@ -258,7 +258,13 @@ module top ( .D_IN_0(lvds_clock) ); // Wire out to 'lvds_clock' - assign lvds_clock_buf = lvds_clock; + //assign lvds_clock_buf = lvds_clock; // <- this is not good practice, as it uses a logic cell to buffer the clock + // Promote to a real global clock + wire lvds_clock_buf; + SB_GB gb_lvds ( + .USER_SIGNAL_TO_GLOBAL_BUFFER(lvds_clock), + .GLOBAL_BUFFER_OUTPUT(lvds_clock_buf) + ); //--------------------------------------------- // LVDS RX - I/Q Data @@ -296,45 +302,57 @@ module top ( //---------------------------------------------- // LVDS TX - I/Q Data //---------------------------------------------- + // One coherent TX clock net for *everything* (no inversion). + + //wire tx_clk_data = ~lvds_clock_buf; + + // If the modem samples on the "other" half, flip edges by swapping Z & O below. + // (No need to invert tx_clk.) + //wire d_rise = w_lvds_tx_d0; // data to present on posedge of tx_clk + //wire d_fall = w_lvds_tx_d1; // data to present on negedge of tx_clk // Non-inverting, P-side of pair SB_IO #( .PIN_TYPE (6'b010000), // {PIN_OUTPUT_DDR, PIN_OUTPUT_REGISTER } - .IO_STANDARD("SB_LVCMOS"), + .IO_STANDARD("SB_LVCMOS") ) iq_tx_p ( .PACKAGE_PIN(o_iq_tx_p), - .OUTPUT_CLK(~lvds_clock_buf), - .D_OUT_0(~w_lvds_tx_d0), - .D_OUT_1(~w_lvds_tx_d1) + .OUTPUT_CLK(lvds_clock_buf), + .D_OUT_0(~w_lvds_tx_d1), + .D_OUT_1(~w_lvds_tx_d0) ); // Inverting, N-side of pair SB_IO #( .PIN_TYPE (6'b010000), // {PIN_OUTPUT_DDR, PIN_OUTPUT_REGISTER } - .IO_STANDARD("SB_LVCMOS"), + .IO_STANDARD("SB_LVCMOS") ) iq_tx_n ( .PACKAGE_PIN(o_iq_tx_n), - .OUTPUT_CLK(~lvds_clock_buf), - .D_OUT_0(w_lvds_tx_d0), - .D_OUT_1(w_lvds_tx_d1) + .OUTPUT_CLK(lvds_clock_buf), + .D_OUT_0(w_lvds_tx_d1), + .D_OUT_1(w_lvds_tx_d0) ); // Non-inverting, P-side clock SB_IO #( - .PIN_TYPE(6'b011001), + .PIN_TYPE(6'b010000), .IO_STANDARD("SB_LVCMOS") ) iq_tx_clk_p ( .PACKAGE_PIN(o_iq_tx_clk_p), - .D_OUT_0(lvds_clock_buf), + .OUTPUT_CLK(lvds_clock_buf), // The clock output + .D_OUT_0(1'b1), + .D_OUT_1(1'b0) ); // Inverting, N-side clock SB_IO #( - .PIN_TYPE(6'b011001), + .PIN_TYPE(6'b010000), .IO_STANDARD("SB_LVCMOS") ) iq_tx_clk_n ( .PACKAGE_PIN(o_iq_tx_clk_n), - .D_OUT_0(~lvds_clock_buf), + .OUTPUT_CLK(lvds_clock_buf), // The clock output + .D_OUT_0(1'b0), + .D_OUT_1(1'b1) ); @@ -398,7 +416,7 @@ module top ( complex_fifo #( .ADDR_WIDTH(10), // 1024 samples - .DATA_WIDTH(16), // 2x16 for I and Q + .DATA_WIDTH(16) // 2x16 for I and Q ) rx_fifo ( .wr_rst_b_i(i_rst_b), .wr_clk_i(w_rx_fifo_write_clk), @@ -411,7 +429,7 @@ module top ( .rd_data_o(w_rx_fifo_pulled_data), .full_o(w_rx_fifo_full), - .empty_o(w_rx_fifo_empty), + .empty_o(w_rx_fifo_empty) ); //========================================================================= @@ -429,54 +447,99 @@ module top ( .o_fifo_pull(w_tx_fifo_pull), .i_fifo_data(w_tx_fifo_pulled_data), .i_sample_gap(tx_sample_gap), - .i_tx_state(~w_smi_data_direction), - .i_sync_input(w_tx_sync_input_09), - .i_debug_lb(w_debug_lb_tx), - .o_tx_state_bit(), - .o_sync_state_bit(), - ); + .i_tx_state(!w_smi_data_direction), + .i_debug_lb(w_debug_lb_tx), + .o_tx_fsm_state(w_tx_fsm_state) + ); + + //assign io_pmod[0] = ~lvds_clock_buf; + //assign io_pmod[1] = w_lvds_tx_d0; + //assign io_pmod[2] = w_lvds_tx_d1; + //assign io_pmod[0] = w_smi_write_req; + //assign io_pmod[1] = i_smi_swe_srw; + //assign io_pmod[2] = w_tx_fifo_push; + //assign io_pmod[3] = w_smi_tx_state[0]; + //assign io_pmod[4] = w_smi_tx_state[1]; + //assign io_pmod[5] = w_tx_fifo_full; + //assign io_pmod[6] = w_tx_fifo_empty; + //assign io_pmod[7] = w_tx_fifo_pull; + + //assign io_pmod[7:0] = w_smi_data_input; + //assign o_smi_write_req = i_smi_swe_srw; // <-removed for new smi_ctrl tx_side + + wire w_tx_fifo_full; + wire w_tx_fifo_empty; + wire w_tx_fifo_read_clk; + wire w_tx_fifo_push; + wire [31:0] w_tx_fifo_data; + wire w_tx_fifo_pull; + wire [31:0] w_tx_fifo_pulled_data; + wire [2:0] w_tx_fsm_state; + + // ------------------------------------------------------------ + // TEMP TX PRODUCER (sys clock domain) — drives FIFO directly + // ------------------------------------------------------------ + localparam TEST_TX = 1'b0; // set 0 to return to normal + reg tx_test_en; + reg [12:0] tx_test_cntr; + + // (optional) throttle so we don't overrun the FIFO if sys_clk >> lvds_clk + localparam integer PUSH_EVERY = 1; // push every sys tick; try 4/8 if needed + reg [$clog2(PUSH_EVERY)-1:0] push_div; + + always @(posedge w_clock_sys or negedge i_rst_b) begin + if (!i_rst_b) begin + tx_test_en <= 1'b1; // enable generator by default + tx_test_cntr <= 32'h0000_0000; + push_div <= '0; + end else begin + // simple throttle + push_div <= push_div + 1'b1; + + if (tx_test_en && !w_tx_fifo_full && (push_div == 0)) begin + tx_test_cntr <= tx_test_cntr + 13'h1; // test pattern + end + end + end - //assign io_pmod[0] = ~lvds_clock_buf; - //assign io_pmod[1] = w_lvds_tx_d0; - //assign io_pmod[2] = w_lvds_tx_d1; - //assign io_pmod[0] = w_smi_write_req; - //assign io_pmod[1] = i_smi_swe_srw; - //assign io_pmod[2] = w_tx_fifo_push; - //assign io_pmod[3] = w_smi_tx_state[0]; - //assign io_pmod[4] = w_smi_tx_state[1]; - //assign io_pmod[5] = w_tx_fifo_full; - //assign io_pmod[6] = w_tx_fifo_empty; - //assign io_pmod[7] = w_tx_fifo_pull; - - //assign io_pmod[7:0] = w_smi_data_input; - assign o_smi_write_req = i_smi_swe_srw; - - wire w_tx_fifo_full; - wire w_tx_fifo_empty; - wire w_tx_fifo_read_clk; - wire w_tx_fifo_push; - wire [31:0] w_tx_fifo_data; - wire w_tx_fifo_pull; - wire [31:0] w_tx_fifo_pulled_data; - - complex_fifo #( +wire tp_push = tx_test_en && !w_tx_fifo_full && (push_div == 0); +wire [31:0] tp_data = {2'b10,tx_test_cntr,1'b1,2'b01,tx_test_cntr + 13'd2048,1'b0}; // or a fixed frame you prefer + +wire tx_wr_en = TEST_TX ? tp_push : w_tx_fifo_push; +wire [31:0] tx_wr_data = TEST_TX ? tp_data : w_tx_fifo_data; + +complex_fifo #( .ADDR_WIDTH(10), // 1024 samples - .DATA_WIDTH(16), // 2x16 for I and Q - ) tx_fifo ( + .DATA_WIDTH(16) // 2x16 for I and Q +) tx_fifo ( // smi clock is writing .wr_rst_b_i(i_rst_b), .wr_clk_i(w_clock_sys), .wr_en_i(w_tx_fifo_push), + //.wr_en_i(tx_wr_en), // <— was w_tx_fifo_push for test generator .wr_data_i(w_tx_fifo_data), + //.wr_data_i(tx_wr_data), // <— was w_tx_fifo_data for test generator .full_o(w_tx_fifo_full), // lvds clock is pulling (reading) .rd_rst_b_i(i_rst_b), - .rd_clk_i(~lvds_clock_buf), + .rd_clk_i(lvds_clock_buf), .rd_en_i(w_tx_fifo_pull), .rd_data_o(w_tx_fifo_pulled_data), - .empty_o(w_tx_fifo_empty), + .empty_o(w_tx_fifo_empty) ); + +// // ------------------------------ +// // TX FIFO debug taps (put next to tx_fifo) +// // ------------------------------ + +// // Latch low nibble of the frame written into FIFO (sys clock domain) +// reg [3:0] dbg_wr_nib; +// always @(posedge w_clock_sys or negedge i_rst_b) begin +// if (!i_rst_b) dbg_wr_nib <= 4'h0; +// else if (w_tx_fifo_push && !w_tx_fifo_full) +// dbg_wr_nib <= w_tx_fifo_data[3:0]; +// end wire channel; wire w_smi_data_direction; @@ -605,4 +668,22 @@ module top ( //assign o_led0 = w_smi_data_direction; //assign o_led1 = channel; + //assign io_pmod_out[0] = w_tx_fsm_state[0]; + //assign io_pmod_out[1] = w_tx_fsm_state[1]; + //assign io_pmod_out[2] = w_tx_fsm_state[2]; + //assign io_pmod_out[3] = w_tx_fifo_empty; + + //assign io_pmod_out[2] = w_smi_tx_state[0]; + //assign io_pmod_out[3] = w_smi_tx_state[1]; + + //assign io_pmod_out[0] = w_tx_fifo_pull; + //assign io_pmod_out[1] = w_tx_fifo_push; + //assign io_pmod_out[2] = w_tx_fifo_full; + //assign io_pmod_out[3] = w_tx_fifo_empty; + + //assign io_pmod_out[0] = dbg_wr_nib[0]; + //assign io_pmod_out[1] = dbg_wr_nib[1]; + //assign io_pmod_out[2] = dbg_wr_nib[2]; + //assign io_pmod_out[3] = dbg_wr_nib[3]; + endmodule // top diff --git a/software/libcariboulite/CMakeLists.txt b/software/libcariboulite/CMakeLists.txt index d7e74a3a..1db41b67 100644 --- a/software/libcariboulite/CMakeLists.txt +++ b/software/libcariboulite/CMakeLists.txt @@ -3,19 +3,30 @@ project(cariboulite VERSION 1.2.0 LANGUAGES C CXX DESCRIPTION "CaribouLite RpiSDR C API") + +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O3 -ffast-math -fno-math-errno -funroll-loops") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -O3 -ffast-math -fno-math-errno -funroll-loops") + set(CMAKE_BUILD_TYPE Release) set(CMAKE_POSITION_INDEPENDENT_CODE ON) # Bring the headers include_directories(./src) +include_directories(./src/at86rf215) # AT86RF215 headers include_directories(${PROJECT_SOURCE_DIR}/src) add_compile_options(-Wall -Wextra -Wno-unused-variable -Wno-missing-braces) # ------------------------------------ # MAIN - Source files for main library # ------------------------------------ -set(SOURCES_LIB src/cariboulite.c src/cariboulite_setup.c src/cariboulite_events.c src/cariboulite_radio.c) +set(SOURCES_LIB src/cariboulite.c + src/cariboulite_setup.c + src/cariboulite_events.c + src/cariboulite_radio.c + src/cariboulite_sys_storage.c + src/cariboulite_sys_accessor.c) + set(TARGET_LINK_LIBS datatypes production_utils caribou_fpga @@ -27,11 +38,14 @@ set(TARGET_LINK_LIBS datatypes io_utils zf_log rt - m - pthread) + m) set(SOURCES_CPP_LIB src/CaribouLiteCpp.cpp src/CaribouLiteRadioCpp.cpp) +# Enable POSIX/GNU extensions so siginfo_t and SA_SIGINFO are visible +add_definitions(-D_POSIX_C_SOURCE=200809L) +add_compile_definitions(_GNU_SOURCE) + # Add internal project dependencies add_subdirectory(src/datatypes EXCLUDE_FROM_ALL) add_subdirectory(src/caribou_programming EXCLUDE_FROM_ALL) @@ -47,17 +61,34 @@ add_subdirectory(src/iir EXCLUDE_FROM_ALL) # Create the library cariboulite add_library(cariboulite STATIC ${SOURCES_LIB} ${SOURCES_CPP_LIB}) -target_link_libraries(cariboulite PRIVATE ${TARGET_LINK_LIBS}) +target_link_libraries(cariboulite PUBLIC ${TARGET_LINK_LIBS}) set_target_properties(cariboulite PROPERTIES PUBLIC_HEADER "src/cariboulite.h;src/cariboulite_radio.h;src/CaribouLite.hpp") -set_target_properties(cariboulite PROPERTIES OUTPUT_NAME cariboulite) +set_target_properties(cariboulite PROPERTIES OUTPUT_NAME cariboulite_static) add_library(cariboulite_shared SHARED ${SOURCES_LIB} ${SOURCES_CPP_LIB}) -target_link_libraries(cariboulite_shared PRIVATE ${TARGET_LINK_LIBS}) +target_link_libraries(cariboulite_shared PUBLIC ${TARGET_LINK_LIBS}) set_target_properties(cariboulite_shared PROPERTIES PUBLIC_HEADER "src/cariboulite.h;src/cariboulite_radio.h;src/CaribouLite.hpp") set_property(TARGET cariboulite_shared PROPERTY POSITION_INDEPENDENT_CODE 1) set_target_properties(cariboulite_shared PROPERTIES OUTPUT_NAME cariboulite) +#-------------------------------------- +# add pthread scheduling support +#-------------------------------------- +find_package(Threads REQUIRED) + +#-------------------------------------- +# add ncurses support +#-------------------------------------- +find_package(Curses REQUIRED) + +#-------------------------------------- +# add ALSA support +#-------------------------------------- +find_package(ALSA REQUIRED) +#include_directories(${PROJECT_SOURCE_DIR}/include) + +include_directories(${CURSES_INCLUDE_DIR}) #-------------------------------------- # create the Soapy shared object @@ -68,6 +99,8 @@ if (NOT SoapySDR_FOUND) return() endif () + + if(CMAKE_COMPILER_IS_GNUCXX) include(CheckCXXCompilerFlag) CHECK_CXX_COMPILER_FLAG("-std=c++11" HAS_STD_CXX11) @@ -113,7 +146,12 @@ SOAPY_SDR_MODULE_UTIL( # ---------------------------------- set(SOURCES_CARIBOU_PROGRAMMER test/caribou_programmer.c) set(SOURCES_FPGA_COMM test/fpga_comm_test.c) -set(SOURCES_TEST_MAIN src/cariboulite_test_app.c src/app_menu.c) +set(SOURCES_TEST_MAIN + src/cariboulite_test_app.c + src/app_menu.c + src/tone48k.c + src/nbfm4m_mod.c + src/alsa48k_source.c) set(SOURCES_MAIN src/cariboulite_util.c) set(SOURCES_PROD src/cariboulite_production.c) @@ -124,8 +162,14 @@ add_executable(cariboulite_util ${SOURCES_MAIN}) target_link_libraries(caribou_programmer cariboulite) target_link_libraries(fpgacomm cariboulite) -target_link_libraries(cariboulite_test_app cariboulite) -target_link_libraries(cariboulite_util cariboulite) +target_link_libraries(cariboulite_test_app + PRIVATE + cariboulite_shared + ${CURSES_LIBRARIES} + m + Threads::Threads + ALSA::ALSA) +target_link_libraries(cariboulite_util cariboulite_shared) set_target_properties( caribou_programmer PROPERTIES RUNTIME_OUTPUT_DIRECTORY test) set_target_properties( fpgacomm PROPERTIES RUNTIME_OUTPUT_DIRECTORY test) diff --git a/software/libcariboulite/src/alsa48k_source.c b/software/libcariboulite/src/alsa48k_source.c new file mode 100644 index 00000000..396d4e12 --- /dev/null +++ b/software/libcariboulite/src/alsa48k_source.c @@ -0,0 +1,291 @@ +#include "alsa48k_source.h" +#include +#include +#include +#include +#include + +#ifndef CLAMPF +#define CLAMPF(x,lo,hi) ((x) < (lo) ? (lo) : ((x) > (hi) ? (hi) : (x))) +#endif + +struct alsa48k_source { + snd_pcm_t* pcm; + float gain; + + // capture format + unsigned int fs; // 48000 + unsigned int ch; // 1 + snd_pcm_format_t fmt; // SND_PCM_FORMAT_S16_LE + + // ALSA sizes + snd_pcm_uframes_t period; // typically 480 (10 ms) + snd_pcm_uframes_t bufsize;// e.g. period * 8 + + // temp capture buffer (int16 from ALSA) and float ring + int16_t* cap_i16; // period frames + float* ring; + size_t rcap; // ring capacity in frames + size_t rhead; // read index + size_t rtail; // write index + size_t rcount; // frames stored +}; + +static int alsa_recover_xrun(snd_pcm_t* pcm, int err) +{ + if (err == -EPIPE) { // overrun/underrun + snd_pcm_prepare(pcm); + return 0; + } else if (err == -ESTRPIPE) { + // suspended, try to resume + while ((err = snd_pcm_resume(pcm)) == -EAGAIN) { + struct timespec ts = { .tv_sec = 0, .tv_nsec = 1000000 }; + nanosleep(&ts, NULL); + } + if (err < 0) snd_pcm_prepare(pcm); + return 0; + } + return err; +} + +static int alsa_set_hw_params(snd_pcm_t* pcm, + unsigned int* fs_io, + unsigned int* ch_io, + snd_pcm_format_t fmt, + snd_pcm_uframes_t* period_io, + snd_pcm_uframes_t* bufsize_io) +{ + int rc; + snd_pcm_hw_params_t* hw = NULL; + snd_pcm_hw_params_malloc(&hw); + snd_pcm_hw_params_any(pcm, hw); + + // Interleaved capture + rc = snd_pcm_hw_params_set_access(pcm, hw, SND_PCM_ACCESS_RW_INTERLEAVED); + if (rc < 0) goto done; + + // Format + rc = snd_pcm_hw_params_set_format(pcm, hw, fmt); + if (rc < 0) goto done; + + // Channels + unsigned int ch = *ch_io; + rc = snd_pcm_hw_params_set_channels(pcm, hw, ch); + if (rc < 0) goto done; + + // Rate (set near 48000) + unsigned int fs = *fs_io, fs_set = 0; + int dir = 0; + rc = snd_pcm_hw_params_set_rate_near(pcm, hw, &fs, &dir); + if (rc < 0) goto done; + fs_set = fs; + if (fs_set != *fs_io) { rc = -EINVAL; goto done; } // insist on 48k exact + + // Period size (try 480 frames => 10 ms) + snd_pcm_uframes_t period = *period_io; + dir = 0; + rc = snd_pcm_hw_params_set_period_size_near(pcm, hw, &period, &dir); + if (rc < 0) goto done; + + // Buffer size (use 8 periods) + snd_pcm_uframes_t bufsize = period * 8; + rc = snd_pcm_hw_params_set_buffer_size_near(pcm, hw, &bufsize); + if (rc < 0) goto done; + + // Apply + rc = snd_pcm_hw_params(pcm, hw); + if (rc < 0) goto done; + + // Read back what we actually got + snd_pcm_hw_params_get_rate(hw, &fs_set, 0); + snd_pcm_hw_params_get_channels(hw, &ch); + snd_pcm_hw_params_get_period_size(hw, &period, 0); + snd_pcm_hw_params_get_buffer_size(hw, &bufsize); + + *fs_io = fs_set; + *ch_io = ch; + *period_io = period; + *bufsize_io= bufsize; + rc = 0; + +done: + if (hw) snd_pcm_hw_params_free(hw); + return rc; +} + +static int alsa_set_sw_params(snd_pcm_t* pcm, snd_pcm_uframes_t period) +{ + int rc; + snd_pcm_sw_params_t* sw = NULL; + snd_pcm_sw_params_malloc(&sw); + snd_pcm_sw_params_current(pcm, sw); + + // Start when at least one period is available in the buffer + rc = snd_pcm_sw_params_set_start_threshold(pcm, sw, period); + if (rc < 0) goto done; + + // Wake up when at least one period is ready + rc = snd_pcm_sw_params_set_avail_min(pcm, sw, period); + if (rc < 0) goto done; + + rc = snd_pcm_sw_params(pcm, sw); +done: + if (sw) snd_pcm_sw_params_free(sw); + return rc; +} + +alsa48k_source_t* alsa48k_create(const char* device, float gain) +{ + alsa48k_source_t* s = (alsa48k_source_t*)calloc(1, sizeof(*s)); + if (!s) return NULL; + + s->fs = 48000; + s->ch = 1; + s->fmt = SND_PCM_FORMAT_S16_LE; + s->gain = gain; + + const char* dev = device ? device : "default"; + int rc = snd_pcm_open(&s->pcm, dev, SND_PCM_STREAM_CAPTURE, 0 /* blocking */); + if (rc < 0) { free(s); return NULL; } + + // recommend blocking capture; we keep our own small ring and do quick reads + s->period = 480; // target 10 ms + s->bufsize = s->period * 8; + + rc = alsa_set_hw_params(s->pcm, &s->fs, &s->ch, s->fmt, &s->period, &s->bufsize); + if (rc < 0) { snd_pcm_close(s->pcm); free(s); return NULL; } + + rc = alsa_set_sw_params(s->pcm, s->period); + if (rc < 0) { snd_pcm_close(s->pcm); free(s); return NULL; } + + // allocate temp capture buffer (period frames) and a modest ring (~170 ms) + s->cap_i16 = (int16_t*)malloc(sizeof(int16_t) * s->period * s->ch); + s->rcap = (size_t)(s->period * 17); // ~170 ms ring at 10 ms period + s->ring = (float*)malloc(sizeof(float) * s->rcap); + if (!s->cap_i16 || !s->ring) { + alsa48k_destroy(s); + return NULL; + } + + // Prime the device + rc = snd_pcm_prepare(s->pcm); + if (rc < 0) { alsa48k_destroy(s); return NULL; } + + s->rhead = s->rtail = s->rcount = 0; + return s; +} + +static void ring_push(alsa48k_source_t* s, const float* src, size_t n) +{ + // Drop oldest if overflow (keep newest) + if (n > s->rcap) { + src += (n - s->rcap); + n = s->rcap; + } + while (s->rcount + n > s->rcap) { + // pop one frame (overwrite oldest) + s->rhead = (s->rhead + 1) % s->rcap; + s->rcount--; + } + // write n frames + size_t tail_to_end = s->rcap - s->rtail; + size_t first = (n < tail_to_end) ? n : tail_to_end; + memcpy(&s->ring[s->rtail], src, first * sizeof(float)); + s->rtail = (s->rtail + first) % s->rcap; + size_t remain = n - first; + if (remain) { + memcpy(&s->ring[s->rtail], src + first, remain * sizeof(float)); + s->rtail = (s->rtail + remain) % s->rcap; + } + s->rcount += n; +} + +static size_t ring_pop(alsa48k_source_t* s, float* dst, size_t n) +{ + size_t take = (n < s->rcount) ? n : s->rcount; + size_t head_to_end = s->rcap - s->rhead; + size_t first = (take < head_to_end) ? take : head_to_end; + memcpy(dst, &s->ring[s->rhead], first * sizeof(float)); + s->rhead = (s->rhead + first) % s->rcap; + size_t remain = take - first; + if (remain) { + memcpy(dst + first, &s->ring[s->rhead], remain * sizeof(float)); + s->rhead = (s->rhead + remain) % s->rcap; + } + s->rcount -= take; + return take; +} + +static int pcm_capture_once(alsa48k_source_t* s) +{ + // read up to one period (blocking read is OK; period is small) + snd_pcm_sframes_t got = snd_pcm_readi(s->pcm, s->cap_i16, s->period); + if (got < 0) { + if (alsa_recover_xrun(s->pcm, (int)got) < 0) return (int)got; + got = snd_pcm_readi(s->pcm, s->cap_i16, s->period); + if (got < 0) return (int)got; + } + if (got == 0) return 0; + + // convert to float and push + const float g = s->gain; + static float tmpf[8192]; // enough for typical period sizes + if ((size_t)got > sizeof(tmpf)/sizeof(tmpf[0])) { + // fallback allocate for unusually large period + float* dyn = (float*)malloc(sizeof(float) * (size_t)got); + if (!dyn) return -ENOMEM; + for (snd_pcm_sframes_t i = 0; i < got; i++) { + float x = (float)s->cap_i16[i] / 32768.0f; + dyn[i] = CLAMPF(x * g, -1.0f, 1.0f); + } + ring_push(s, dyn, (size_t)got); + free(dyn); + } else { + for (snd_pcm_sframes_t i = 0; i < got; i++) { + float x = (float)s->cap_i16[i] / 32768.0f; + tmpf[i] = CLAMPF(x * g, -1.0f, 1.0f); + } + ring_push(s, tmpf, (size_t)got); + } + return (int)got; +} + +size_t alsa48k_read(alsa48k_source_t* s, float* dst, size_t max_frames) +{ + if (!s || !dst || max_frames == 0) return 0; + + // If we already have enough in the ring, just pop and return. + if (s->rcount >= max_frames) { + return ring_pop(s, dst, max_frames); + } + + // Otherwise, capture until we can satisfy the request (bounded wait). + const int max_loops = 8; // ~80 ms worst case (period ~10 ms) + int loops = 0; + + while (s->rcount < max_frames && loops < max_loops) { + int rc = pcm_capture_once(s); + if (rc < 0) { + // On error, return what we do have (could be 0) + break; + } + if (rc == 0) { + // No new data; brief nap + struct timespec ts = { .tv_sec = 0, .tv_nsec = 2000000 }; // 2 ms + nanosleep(&ts, NULL); + } + loops++; + } + + // pop whatever is available up to max_frames + return ring_pop(s, dst, max_frames); +} + +void alsa48k_destroy(alsa48k_source_t* s) +{ + if (!s) return; + if (s->pcm) snd_pcm_close(s->pcm); + free(s->cap_i16); + free(s->ring); + free(s); +} \ No newline at end of file diff --git a/software/libcariboulite/src/alsa48k_source.h b/software/libcariboulite/src/alsa48k_source.h new file mode 100644 index 00000000..c532d56a --- /dev/null +++ b/software/libcariboulite/src/alsa48k_source.h @@ -0,0 +1,9 @@ +#pragma once +#include + +typedef struct alsa48k_source alsa48k_source_t; + +// device examples: "default", "hw:1,0" +alsa48k_source_t* alsa48k_create(const char* device, float gain); +size_t alsa48k_read(alsa48k_source_t* s, float* dst, size_t max_frames); +void alsa48k_destroy(alsa48k_source_t* s); \ No newline at end of file diff --git a/software/libcariboulite/src/app_menu.c b/software/libcariboulite/src/app_menu.c index 2196b98a..ca613779 100644 --- a/software/libcariboulite/src/app_menu.c +++ b/software/libcariboulite/src/app_menu.c @@ -1,6 +1,64 @@ +// Enable POSIX/GNU extensions +#ifndef _POSIX_C_SOURCE +# define _POSIX_C_SOURCE 200809L +#endif +#ifndef _GNU_SOURCE +# define _GNU_SOURCE +#endif +#ifndef CLOCK_MONOTONIC +# define CLOCK_MONOTONIC CLOCK_REALTIME +#endif + #include #include "cariboulite.h" #include "cariboulite_setup.h" +#include "caribou_smi/caribou_smi.h" +#include +#include +#include +#include +#include +#include +#include // if you want offsetof +#include +#include + +_Static_assert(sizeof(caribou_smi_sample_complex_int16) == 4, + "caribou_smi_sample_complex_int16 must be 4 bytes (2x int16)"); + +#ifdef CARIBOU_SMI_BYTES_PER_SAMPLE +_Static_assert(CARIBOU_SMI_BYTES_PER_SAMPLE == sizeof(caribou_smi_sample_complex_int16), + "CARIBOU_SMI_BYTES_PER_SAMPLE must match complex sample size"); +#endif + +#include "audio48k_source.h" +#include "alsa48k_source.h" +#include "nbfm4m_mod.h" + + +// included here, to use ncurcus for a text-baused UI for my additions +#include "ncurses.h" + +// include here, for testing and access to level registers +#include + +// include here, for testing +#define SOURCE "/home/pi/src/cariboulite/firmware/top.bin" + + + +#include +static pthread_mutex_t g_hw_lock = PTHREAD_MUTEX_INITIALIZER; +#define HW_LOCK() pthread_mutex_lock(&g_hw_lock) +#define HW_UNLOCK() pthread_mutex_unlock(&g_hw_lock) +#include +#include +#include + +bool nbfm_tx_ready = false; +volatile bool nbfm_tx_active = false; +bool nbfm_rx_ready = false; +volatile bool nbfm_rx_active = false; //================================================= typedef enum @@ -16,6 +74,10 @@ typedef enum app_selection_modem_tx_cw, app_selection_modem_rx_iq, app_selection_synthesizer, + app_selection_nbfm_tx_tone, + app_selection_nbfm_rx, + app_selection_nbfm_modem_selftest, + app_selection_monitor_modem_status, app_selection_quit = 99, } app_selection_en; @@ -39,6 +101,17 @@ static void fpga_smi_fifo(sys_st *sys); static void modem_tx_cw(sys_st *sys); static void modem_rx_iq(sys_st *sys); static void synthesizer(sys_st *sys); +static void nbfm_tx_tone(sys_st *sys); +static void nbfm_rx(sys_st *sys); +static void nbfm_modem_selftest(sys_st *sys); +static void monitor_modem_status(sys_st *sys); + +// --- forward declarations for pthread entry points --- +static void* dsp_producer_thread_func(void* arg); +static void* tx_writer_thread_func(void* arg); +static void* rx_reader_thread_func(void* arg); +static void* nbfm_demod_thread(void* arg); +static void* audio_writer_thread(void* arg); //================================================= app_menu_item_st handles[] = @@ -54,9 +127,75 @@ app_menu_item_st handles[] = {app_selection_modem_tx_cw, modem_tx_cw, "Modem transmit CW signal",}, {app_selection_modem_rx_iq, modem_rx_iq, "Modem receive I/Q stream",}, {app_selection_synthesizer, synthesizer, "Synthesizer 85-4200 MHz",}, + {app_selection_nbfm_tx_tone, nbfm_tx_tone, "NBFM TX Tone",}, + {app_selection_nbfm_rx, nbfm_rx, "NBFM RX",}, + {app_selection_nbfm_modem_selftest, nbfm_modem_selftest, "NBFM modem Self-Test",}, + {app_selection_monitor_modem_status, monitor_modem_status, "Monitor Modem Status",}, }; #define NUM_HANDLES (int)(sizeof(handles)/sizeof(app_menu_item_st)) +// constants +#define SR 4000000.0 // sample rate +#define DF 2500.0 // peak deviation (Hz) +#define FM 700.0 // modulating tone (Hz) +#define AMP 2047.0 // amplitude (safe for 13-bit signed) + +//================================================= +static inline uint64_t mono_ns(void){ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return (uint64_t)ts.tv_sec*1000000000ull + ts.tv_nsec; +} + +static int set_rt_and_affinity_prio(int prio, int cpu_req) +{ + struct sched_param sp = { .sched_priority = prio }; + if (pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp) != 0) { + sp.sched_priority = 0; + pthread_setschedparam(pthread_self(), SCHED_OTHER, &sp); + } + + long ncpu = sysconf(_SC_NPROCESSORS_ONLN); + if (ncpu < 1) ncpu = 1; + int cpu = (cpu_req >= 0) ? cpu_req : 0; + if (cpu >= ncpu) cpu = (int)(ncpu - 1); + + cpu_set_t set; CPU_ZERO(&set); CPU_SET(cpu, &set); + int rc = pthread_setaffinity_np(pthread_self(), sizeof(set), &set); + if (rc != 0) { + fprintf(stderr, "[affinity] pid=%ld th=%lu prio=%d cpu_req=%d FAILED: %s\n", + (long)getpid(), (unsigned long)pthread_self(), prio, cpu_req, strerror(rc)); + return -1; + } +#ifdef __linux__ + int on = sched_getcpu(); + fprintf(stderr, "[affinity] th=%lu prio=%d pinned to CPU %d/%ld\n", + (unsigned long)pthread_self(), prio, on, ncpu); +#endif + mlockall(MCL_CURRENT | MCL_FUTURE); + return 0; +} + +static inline void set_rt_and_affinity(void) +{ + // Hard RT priority and CPU affinity for the calling thread + struct sched_param sp = { .sched_priority = 40 }; // 1..99; 40 is sane + pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp); + +#ifdef __linux__ + cpu_set_t set; + CPU_ZERO(&set); + CPU_SET(2, &set); // keep this away from CPU0 IRQs + pthread_setaffinity_np(pthread_self(), sizeof(set), &set); +#endif + + // Avoid page faults while streaming + mlockall(MCL_CURRENT | MCL_FUTURE); +} + +static inline void smi_idle(sys_st* sys) { + caribou_smi_set_driver_streaming_state(&sys->smi, (smi_stream_state_en)0); +} //================================================= static void app_hard_reset_fpga(sys_st *sys) @@ -93,7 +232,8 @@ static void app_fpga_programming(sys_st *sys) printf("FPGA Programming:\n"); sys->force_fpga_reprogramming = true; - int res = cariboulite_configure_fpga (sys, cariboulite_firmware_source_blob, NULL); + int res = cariboulite_configure_fpga (sys, cariboulite_firmware_source_file, SOURCE); + //int res = cariboulite_configure_fpga (sys, cariboulite_firmware_source_blob, NULL); if (res < 0) { printf(" ERROR: FPGA programming failed `%d`\n", res); @@ -243,15 +383,15 @@ static void modem_tx_cw(sys_st *sys) while (1) { printf(" Parameters:\n"); - printf(" [1] Frequency @ Low Channel [%.2f MHz]\n", current_freq_lo); - printf(" [2] Frequency @ High Channel [%.2f MHz]\n", current_freq_hi); - printf(" [3] Power out @ Low Channel [%.2f dBm]\n", current_power_lo); - printf(" [4] Power out @ High Channel [%.2f dBm]\n", current_power_hi); - printf(" [5] On/off CW output @ Low Channel [Currently %s]\n", state_lo?"ON":"OFF"); - printf(" [6] On/off CW output @ High Channel [Currently %s]\n", state_hi?"ON":"OFF"); - printf(" [7] Low Channel decrease frequency (5MHz)\n"); - printf(" [8] Low Channel increase frequency (5MHz)\n"); - printf(" [9] Hi Channel decrease frequency (5MHz)\n"); + printf(" [ 1] Frequency @ Low Channel [%.2f MHz]\n", current_freq_lo); + printf(" [ 2] Frequency @ High Channel [%.2f MHz]\n", current_freq_hi); + printf(" [ 3] Power out @ Low Channel [%.2f dBm]\n", current_power_lo); + printf(" [ 4] Power out @ High Channel [%.2f dBm]\n", current_power_hi); + printf(" [ 5] On/off CW output @ Low Channel [Currently %s]\n", state_lo?"ON":"OFF"); + printf(" [ 6] On/off CW output @ High Channel [Currently %s]\n", state_hi?"ON":"OFF"); + printf(" [ 7] Low Channel decrease frequency (5MHz)\n"); + printf(" [ 8] Low Channel increase frequency (5MHz)\n"); + printf(" [ 9] Hi Channel decrease frequency (5MHz)\n"); printf(" [10] Hi Channel increase frequency (5MHz)\n"); printf(" [99] Return to Main Menu\n"); printf(" Choice: "); @@ -446,6 +586,8 @@ static void print_iq(char* prefix, cariboulite_sample_complex_int16* buffer, siz static void* reader_thread_func(void* arg) { + pthread_setname_np(pthread_self(), "reader_thread"); + set_rt_and_affinity(); iq_test_reader_st* ctrl = (iq_test_reader_st*)arg; cariboulite_radio_state_st *cur_radio = NULL; size_t read_len = caribou_smi_get_native_batch_samples(&ctrl->sys->smi); @@ -728,48 +870,2232 @@ static void synthesizer(sys_st *sys) } +//======helper function=====display a 8 bit number========================== +void print_binairy8(uint8_t value) { + for (int i = 7; i >= 0; --i) { + putchar((value & (1 << i)) ? '1' : '0'); + if (i % 8 == 0 && i != 0) putchar(' '); + } + putchar('\n'); +} -//================================================= -int app_menu(sys_st* sys) +static void write_exact_alsa_16(snd_pcm_t* pcm, + const int16_t* mono, + size_t frames, + unsigned channels) { - printf("\n"); - printf(" ____ _ _ _ _ _ \n"); - printf(" / ___|__ _ _ __(_) |__ ___ _ _| | (_) |_ ___ \n"); - printf(" | | / _` | '__| | '_ \\ / _ \\| | | | | | | __/ _ \\ \n"); - printf(" | |__| (_| | | | | |_) | (_) | |_| | |___| | || __/ \n"); - printf(" \\____\\__,_|_| |_|_.__/ \\___/ \\__,_|_____|_|\\__\\___| \n"); - printf("\n\n"); + if (channels == 1) { + // write mono directly + size_t left = frames; + const int16_t* p = mono; + while (left) { + snd_pcm_sframes_t w = snd_pcm_writei(pcm, p, left); + if (w == -EPIPE) { snd_pcm_prepare(pcm); continue; } + if (w == -EAGAIN) continue; + if (w < 0) { fprintf(stderr,"ALSA write err: %s\n", snd_strerror((int)w)); break; } + p += w; left -= (size_t)w; + } + return; + } + + // duplicate mono → stereo into a small stack buffer (safe for 480 frames) + int16_t interleaved[480 * 2]; + while (frames) { + size_t chunk = frames > 480 ? 480 : frames; + for (size_t i = 0, j = 0; i < chunk; ++i) { + int16_t s = mono[i]; + interleaved[j++] = s; + interleaved[j++] = s; + } + size_t left = chunk; + const int16_t* p = interleaved; + while (left) { + snd_pcm_sframes_t w = snd_pcm_writei(pcm, p, left); + if (w == -EPIPE) { snd_pcm_prepare(pcm); continue; } + if (w == -EAGAIN) continue; + if (w < 0) { fprintf(stderr,"ALSA write err: %s\n", snd_strerror((int)w)); break; } + p += w * 2; // 2 samples per frame + left -= (size_t)w; + } + mono += chunk; + frames -= chunk; + } +} + +//================================================= + +// ===== 10 ms AUDIO FIFO (producer: demod, consumer: ALSA) ===== +typedef struct { + int16_t pcm[480]; // mono, 48 kHz, 10 ms +} aud10_frame_t; + +typedef struct { + aud10_frame_t* q; + size_t cap, r, w, count; + pthread_mutex_t m; + pthread_cond_t can_put, can_get; + bool stop; + size_t drops; +} aud10_fifo_t; + +static void aud10_fifo_init(aud10_fifo_t* f, size_t cap){ + memset(f,0,sizeof(*f)); + f->q = (aud10_frame_t*)calloc(cap,sizeof(aud10_frame_t)); + f->cap = cap; + pthread_mutex_init(&f->m,NULL); + pthread_cond_init(&f->can_put,NULL); + pthread_cond_init(&f->can_get,NULL); +} +static void aud10_fifo_destroy(aud10_fifo_t* f){ + if(!f) return; + pthread_mutex_destroy(&f->m); + pthread_cond_destroy(&f->can_put); + pthread_cond_destroy(&f->can_get); + free(f->q); +} +static void aud10_fifo_stop(aud10_fifo_t* f){ + pthread_mutex_lock(&f->m); + f->stop = true; + pthread_cond_broadcast(&f->can_put); + pthread_cond_broadcast(&f->can_get); + pthread_mutex_unlock(&f->m); +} +static bool aud10_fifo_put(aud10_fifo_t* f, const aud10_frame_t* frm, int timeout_ms){ + struct timespec ts; clock_gettime(CLOCK_MONOTONIC,&ts); + ts.tv_nsec += (long)timeout_ms*1000000L; while(ts.tv_nsec>=1000000000L){ts.tv_nsec-=1000000000L; ts.tv_sec++;} + pthread_mutex_lock(&f->m); + while(!f->stop && f->count==f->cap){ + if(timeout_ms<0){ pthread_cond_wait(&f->can_put,&f->m); } + else if(pthread_cond_timedwait(&f->can_put,&f->m,&ts)==ETIMEDOUT){ pthread_mutex_unlock(&f->m); return false; } + } + if(f->stop){ pthread_mutex_unlock(&f->m); return false; } + f->q[f->w] = *frm; f->w=(f->w+1)%f->cap; f->count++; + pthread_cond_signal(&f->can_get); + pthread_mutex_unlock(&f->m); + return true; +} +static bool aud10_fifo_get(aud10_fifo_t* f, aud10_frame_t* out, int timeout_ms){ + struct timespec ts; clock_gettime(CLOCK_MONOTONIC,&ts); + ts.tv_nsec += (long)timeout_ms*1000000L; while(ts.tv_nsec>=1000000000L){ts.tv_nsec-=1000000000L; ts.tv_sec++;} + pthread_mutex_lock(&f->m); + while(!f->stop && f->count==0){ + if(timeout_ms<0){ pthread_cond_wait(&f->can_get,&f->m); } + else if(pthread_cond_timedwait(&f->can_get,&f->m,&ts)==ETIMEDOUT){ pthread_mutex_unlock(&f->m); return false; } + } + if(f->stop){ pthread_mutex_unlock(&f->m); return false; } + *out = f->q[f->r]; f->r=(f->r+1)%f->cap; f->count--; + pthread_cond_signal(&f->can_put); + pthread_mutex_unlock(&f->m); + return true; +} + +// Peek audio FIFO depth without disturbing it +static inline void aud10_fifo_peek_depth(aud10_fifo_t* f, size_t* count, size_t* cap){ + pthread_mutex_lock(&f->m); + *count = f->count; + *cap = f->cap; + pthread_mutex_unlock(&f->m); +} + +typedef struct { + bool active; + snd_pcm_t* pcm; + unsigned channels; + aud10_fifo_t* fifo; // source of 10 ms audio frames + size_t xruns; +} audio_writer_ctrl_t; + +static void* audio_writer_thread(void* arg){ + + audio_writer_ctrl_t* a = (audio_writer_ctrl_t*)arg; + pthread_setname_np(pthread_self(),"audio_writer_thread"); + + //set_rt_and_affinity(); + //set_rt_and_affinity_prio(42,-1); + set_rt_and_affinity_prio(46,0); + + // optional: make period/blocking behavior nicer + while(a->active){ + aud10_frame_t frm; + if(!aud10_fifo_get(a->fifo,&frm, /*timeout_ms=*/-1)){ + // starved: write silence to keep clock steady + //int16_t zeros[480]={0}; + //write_exact_alsa_16(a->pcm, zeros, 480, a->channels); + //continue; + break; + } + // write one 10 ms block; handle xrun inside write_exact_alsa_16() + write_exact_alsa_16(a->pcm, frm.pcm, 480, a->channels); + } + return NULL; +} + + +// forward decls placed before tx_writer_ctrl_st +typedef struct rf10_fifo_s rf10_fifo_t; +typedef struct rf10_frame_s rf10_frame_t; + +typedef struct { + bool active; + rf10_fifo_t* fifo_in; // 10ms @ 4MS/s IQ frames from rx_reader + float deemph_tau; // e.g., 75e-6 (NA) or 50e-6 (EU) + float fs_rf; // 4e6 + float fs_audio; // 48000 + volatile bool reset; // set true to force state re-init + int prime_blocks_10ms; // e.g., 20 blocks = 200 ms @ 48k + bool priming; // internal flag + + // state + float deemph_y; + int16_t last_i, last_q; // FM discrim previous sample + + // ALSA sink + snd_pcm_t* pcm; + unsigned pcm_rate; + unsigned pcm_channels; + float pcm_gain; + uint64_t pcm_total_frames; // diag counter + aud10_fifo_t* afifo_out; // where the 10 ms audio frames go +} nbfm_demod_ctrl_t; + +typedef struct { + bool active; + cariboulite_radio_state_st *radio; + cariboulite_sample_complex_int16 *rx_buffer; + size_t rx_buffer_size; - while (1) - { - int choice = -1; - printf(" Select a function:\n"); - for (int i = 0; i < NUM_HANDLES; i++) - { - printf(" [%d] %s\n", handles[i].num, handles[i].text); - } - printf(" [%d] %s\n", app_selection_quit, "Quit"); + // new + rf10_fifo_t* rx_fifo; +} rx_reader_ctrl_st; - printf(" Choice: "); - if (scanf("%d", &choice) != 1) continue; +typedef struct { + bool active; + cariboulite_radio_state_st *radio; + cariboulite_sample_complex_int16 *tx_buffer; + size_t tx_buffer_size; + + // (live path) + bool live_from_mic; // set true to enable live generation + alsa48k_source_t* mic; // ALSA handle + nbfm4m_mod_t* fm; // 48k->4M NBFM + float* a48k; // 480-float scratch + iq16_t* iq4m; // 40k-IQ scratch + + // test tone generator for the FM modulator + bool tone_mode; // true => synthesize 600 Hz audio + float tone_phase; // [0..2π) + float tone_hz; // default 600.0f + float tone_amp; // audio amplitude (0..1), e.g. 0.8f + + // new + rf10_fifo_t* fifo; // FIFO for 10 ms frames + +} tx_writer_ctrl_st; + +// ======================= 10 ms frame FIFO (producer: DSP, consumer: TX writer) ======================= +struct rf10_frame_s { + // One 10 ms RF frame @ 4 MS/s = 40,000 IQ16 pairs + // Reuse your iq16_t type: struct { int16_t i, q; }; + iq16_t data[40000]; +}; + +struct rf10_fifo_s { + rf10_frame_t* q; + size_t cap; // number of frames (e.g., 8) + size_t r; // read index (consumer) + size_t w; // write index (producer) + size_t count; // how many frames ready + pthread_mutex_t m; + pthread_cond_t can_put; + pthread_cond_t can_get; + bool drop_oldest_on_full; // if true, overwrite oldest when full + bool stop; + + // diagnostics + size_t max_depth, min_depth; + size_t drops, puts, gets, timeouts_put, timeouts_get; +}; + +typedef struct { + bool active; + tx_writer_ctrl_st* tx; // reuse your modulator/mic/tone fields + rf10_fifo_t* fifo; +} dsp_producer_ctrl_t; + +// -------------------- PIPELINE PARAMS -------------------- +typedef struct { + // Radio + double freq_hz; // e.g., 430.1e6 + int tx_power_dbm; // e.g., -3 + + // Baseband source for NBFM mod + bool tone_mode; // true => synth audio + float tone_hz; // default 600.0f + float tone_amp; // 0..1 (e.g., 0.4f) + const char* mic_dev; // ALSA capture device or NULL for no mic + + // NBFM modulator config (kept same as your current) + float out_scale; // e.g., 4000.0f + float f_dev_hz; // e.g., 2500.0f +} tx_params_t; + +typedef struct { + // Radio + double freq_hz; // e.g., 430.1e6 + + // Demod/audio + const char* pcm_dev; // ALSA playback device ("plughw:3,0" etc.) + float deemph_tau_s; // 50e-6 (EU) or 75e-6 (NA) + float pcm_gain; // e.g., 8000.0f + + // Fixed rates + float fs_rf; // 4e6 + float fs_audio; // 48e3 +} rx_params_t; + + +// -------------------- PIPELINE HANDLES -------------------- +typedef struct { + // Allocated/owned objects + rf10_fifo_t txq; + tx_writer_ctrl_st tx_ctrl; + dsp_producer_ctrl_t dsp_ctrl; + + // Threads + pthread_t dsp_thread; + pthread_t tx_thread; + + // State + bool inited; + bool running; + + // Binding + sys_st* sys; + cariboulite_radio_state_st* radio; +} tx_pipeline_t; + +typedef struct { + // Allocated/owned objects + rf10_fifo_t rxq; // IQ@4M → 10ms frames + aud10_fifo_t afifo; // 10ms PCM for ALSA + rx_reader_ctrl_st rx_ctrl; + nbfm_demod_ctrl_t demod; + audio_writer_ctrl_t aw; + + // Threads + pthread_t rx_thread; + pthread_t demod_thread; + pthread_t aw_thread; + + // State + bool inited; + bool running; + + // Binding + sys_st* sys; + cariboulite_radio_state_st* radio; +} rx_pipeline_t; + + +// -------------------- PIPELINE APIS (TX) -------------------- +int tx_pipeline_init (tx_pipeline_t* p, sys_st* sys, + cariboulite_radio_state_st* radio, + const tx_params_t* par); +int tx_pipeline_start (tx_pipeline_t* p); +void tx_pipeline_stop (tx_pipeline_t* p); +void tx_pipeline_destroy(tx_pipeline_t* p); + +// -------------------- PIPELINE APIS (RX) -------------------- +int rx_pipeline_init (rx_pipeline_t* p, sys_st* sys, + cariboulite_radio_state_st* radio, + const rx_params_t* par); +int rx_pipeline_start (rx_pipeline_t* p); +void rx_pipeline_stop (rx_pipeline_t* p); +void rx_pipeline_destroy(rx_pipeline_t* p); + +static void rf10_fifo_init(rf10_fifo_t* f, size_t cap, bool drop_oldest) +{ + memset(f, 0, sizeof(*f)); + f->q = (rf10_frame_t*)calloc(cap, sizeof(rf10_frame_t)); + f->cap = cap; + f->min_depth = cap; + f->drop_oldest_on_full = drop_oldest; + pthread_mutex_init(&f->m, NULL); + pthread_cond_init(&f->can_put, NULL); + pthread_cond_init(&f->can_get, NULL); +} + +static void rf10_fifo_reset_stats(rf10_fifo_t* f) +{ + pthread_mutex_lock(&f->m); + f->puts = f->gets = f->drops = 0; + f->timeouts_put = f->timeouts_get = 0; + f->max_depth = f->count; + f->min_depth = f->count; + pthread_mutex_unlock(&f->m); +} + +typedef struct { + size_t cap, count; + size_t puts, gets, drops; + size_t timeouts_put, timeouts_get; + size_t max_depth, min_depth; +} rf10_stats_t; + +static void rf10_fifo_get_stats(rf10_fifo_t* f, rf10_stats_t* s) +{ + pthread_mutex_lock(&f->m); + s->cap = f->cap; + s->count = f->count; + s->puts = f->puts; + s->gets = f->gets; + s->drops = f->drops; + s->timeouts_put = f->timeouts_put; + s->timeouts_get = f->timeouts_get; + s->max_depth = f->max_depth; + s->min_depth = f->min_depth; + pthread_mutex_unlock(&f->m); +} + +static void rf10_fifo_destroy(rf10_fifo_t* f) +{ + if (!f) return; + pthread_mutex_destroy(&f->m); + pthread_cond_destroy(&f->can_put); + pthread_cond_destroy(&f->can_get); + free(f->q); +} + +static bool rf10_fifo_put(rf10_fifo_t* f, const rf10_frame_t* frm, int timeout_ms) +{ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + ts.tv_nsec += (long)timeout_ms * 1000000L; + while (ts.tv_nsec >= 1000000000L) { ts.tv_nsec -= 1000000000L; ts.tv_sec++; } + + pthread_mutex_lock(&f->m); + while (!f->stop && f->count == f->cap && !f->drop_oldest_on_full) { + if (timeout_ms < 0) { + pthread_cond_wait(&f->can_put, &f->m); + } else { + if (pthread_cond_timedwait(&f->can_put, &f->m, &ts) == ETIMEDOUT) { + f->timeouts_put++; // <-- count the timeout + pthread_mutex_unlock(&f->m); + return false; + } + } + } + if (f->stop) { pthread_mutex_unlock(&f->m); return false; } + + if (f->count == f->cap && f->drop_oldest_on_full) { + // overwrite oldest + f->r = (f->r + 1) % f->cap; + f->count--; + f->drops++; // <-- count the drop + } + + f->q[f->w] = *frm; + f->w = (f->w + 1) % f->cap; + f->count++; + f->puts++; // <-- count after success + if (f->count > f->max_depth) f->max_depth = f->count; + + pthread_cond_signal(&f->can_get); + pthread_mutex_unlock(&f->m); + return true; +} + +static bool rf10_fifo_get(rf10_fifo_t* f, rf10_frame_t* out, int timeout_ms) +{ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + ts.tv_nsec += (long)timeout_ms * 1000000L; + while (ts.tv_nsec >= 1000000000L) { ts.tv_nsec -= 1000000000L; ts.tv_sec++; } + + pthread_mutex_lock(&f->m); + while (!f->stop && f->count == 0) { + if (timeout_ms < 0) { + pthread_cond_wait(&f->can_get, &f->m); + } else { + if (pthread_cond_timedwait(&f->can_get, &f->m, &ts) == ETIMEDOUT) { + f->timeouts_get++; // <-- count the timeout + pthread_mutex_unlock(&f->m); + return false; + } + } + } + if (f->stop) { pthread_mutex_unlock(&f->m); return false; } + + *out = f->q[f->r]; + f->r = (f->r + 1) % f->cap; + f->count--; + f->gets++; // <-- count after success + if (f->count < f->min_depth) f->min_depth = f->count; + + pthread_cond_signal(&f->can_put); + pthread_mutex_unlock(&f->m); + return true; +} + +static void rf10_fifo_stop(rf10_fifo_t* f) +{ + pthread_mutex_lock(&f->m); + f->stop = true; + pthread_cond_broadcast(&f->can_put); + pthread_cond_broadcast(&f->can_get); + pthread_mutex_unlock(&f->m); +} + +// must be visible before any thread uses them +static cariboulite_sample_complex_int16 latest_rx_sample = (cariboulite_sample_complex_int16){0}; +static cariboulite_sample_complex_int16 latest_tx_sample = (cariboulite_sample_complex_int16){0}; + +// prototypes so C knows exact signatures before first use +static inline void fill_tone_48k(tx_writer_ctrl_st* ctrl, float* buf, size_t n); +static void read_audio_exact(alsa48k_source_t* mic, float* buf, size_t need); + + +static void* dsp_producer_thread_func(void* arg) +{ + pthread_setname_np(pthread_self(), "dsp_producer_thread"); + //set_rt_and_affinity(); // make sure this logs failures + //set_rt_and_affinity_prio(45,-1); + set_rt_and_affinity_prio(40,0); + + dsp_producer_ctrl_t* ctrl = (dsp_producer_ctrl_t*)arg; + if (!ctrl || !ctrl->tx || !ctrl->tx->fm || !ctrl->fifo || + !ctrl->tx->a48k || !ctrl->tx->iq4m) + return NULL; + + const uint64_t PERIOD_NS = 10ull * 1000ull * 1000ull; // 10 ms + uint64_t next_ns = mono_ns(); // anchor current time + uint64_t last_wake = 0; + size_t frame_idx = 0; + + while (ctrl->active) { + // ---- schedule next absolute wake ---- + next_ns += PERIOD_NS; + struct timespec next_ts = { + .tv_sec = (time_t)(next_ns / 1000000000ull), + .tv_nsec = (long)(next_ns % 1000000000ull) + }; + + // ---- sleep until the absolute deadline, handle EINTR ---- + int rc; + do { + rc = clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &next_ts, NULL); + } while (rc == EINTR); + + // ---- timing diagnostics ---- + uint64_t now = mono_ns(); + if (last_wake) { + double dt_ms = (now - last_wake) / 1e6; + if ((frame_idx++ % 50) == 0) + fprintf(stderr, "producer: dt = %.3f ms rc = %d\n", dt_ms, rc); + } + last_wake = now; + + // ---- if sleep failed or we drifted >50 ms, re-anchor ---- + if (rc != 0 || now > next_ns + 5 * PERIOD_NS) { + next_ns = now; + fprintf(stderr, "producer: re-anchor (rc=%d)\n", rc); + } + + // ============================================================ + // 1) Generate 10 ms of audio @ 48 kHz (480 samples) + // ============================================================ + if (ctrl->tx->tone_mode) { + fill_tone_48k(ctrl->tx, ctrl->tx->a48k, 480); + } else if (ctrl->tx->mic) { + read_audio_exact(ctrl->tx->mic, ctrl->tx->a48k, 480); + } else { + memset(ctrl->tx->a48k, 0, 480 * sizeof(float)); + } + + // ============================================================ + // 2) Push into NBFM modulator, pull 10 ms @ 4 MS/s (40 k IQ) + // ============================================================ + nbfm4m_push_audio(ctrl->tx->fm, ctrl->tx->a48k, 480); + + size_t pulled = 0; + while (pulled < 40000) { + pulled += nbfm4m_pull_iq(ctrl->tx->fm, + ctrl->tx->iq4m + pulled, + 40000 - pulled); + } + + // ============================================================ + // 3) Pack one rf10_frame_t and push to FIFO (tag TX_EN) + // ============================================================ + rf10_frame_t frm; + for (size_t i = 0; i < 40000; i++) { + frm.data[i].i = ctrl->tx->iq4m[i].i | 0x0001; // TX_EN in LSB + frm.data[i].q = ctrl->tx->iq4m[i].q; + } + + // Optional live sample for UI/debug + latest_tx_sample.i = frm.data[20000].i; + latest_tx_sample.q = frm.data[20000].q; + + // Blocking put; don’t drop frames + bool ok = rf10_fifo_put(ctrl->fifo, &frm, -1); + if (!ok) break; // stop signal + } + + return NULL; +} + +static size_t tx_sample_index = 0; + + +static inline void fill_tone_48k(tx_writer_ctrl_st* ctrl, float* buf, size_t n) +{ + // audio sample rate is fixed at 48 kHz + const float fs = 48000.0f; + const float amp = ctrl->tone_amp; // 0..1 + const float dphi = 2.0f * (float)M_PI * (ctrl->tone_hz / fs); + float phase = ctrl->tone_phase; + + for (size_t i = 0; i < n; i++) { + phase += dphi; + if (phase >= 2.0f * (float)M_PI) phase -= 2.0f * (float)M_PI; + buf[i] = amp * sinf(phase); + } + + ctrl->tone_phase = phase; +} + + +static void* rx_reader_thread_func(void* arg) +{ + pthread_setname_np(pthread_self(),"rx_reader_thread"); + //set_rt_and_affinity(); + //set_rt_and_affinity_prio(30, -1); + // Highest prio; reader must never be blocked by DSP/ALSA + set_rt_and_affinity_prio(70, 2); // falls back to CPU0 if missing + + rx_reader_ctrl_st* ctrl = (rx_reader_ctrl_st*)arg; + caribou_smi_st *smi = &ctrl->radio->sys->smi; + + const size_t want = 40000; // 10 ms @ 4 MS/s + cariboulite_sample_complex_int16* buf = ctrl->rx_buffer; + cariboulite_sample_meta* meta = malloc(sizeof(*meta) * want); + + size_t have = 0; + while (ctrl->active) { + int ret = cariboulite_radio_read_samples(ctrl->radio, buf + have, meta, want - have); + if (ret > 0) have += (size_t)ret; + + if (have == want) { + rf10_frame_t frm; + for (size_t i=0;irx_fifo /*add to ctrl*/, &frm, -1); + if (!rf10_fifo_put(ctrl->rx_fifo, &frm, /*timeout_ms=*/-1)) { + // FIFO full -> overwrite oldest already happened; just continue + // (you can keep a counter if you want to log drops) + } + have = 0; + } + } + free(meta); + return NULL; +} + + +static const char* pcm_state_name(snd_pcm_state_t s){ + switch (s){ + case SND_PCM_STATE_OPEN: return "OPEN"; + case SND_PCM_STATE_SETUP: return "SETUP"; + case SND_PCM_STATE_PREPARED: return "PREPARED"; + case SND_PCM_STATE_RUNNING: return "RUNNING"; + case SND_PCM_STATE_XRUN: return "XRUN"; + case SND_PCM_STATE_DRAINING: return "DRAINING"; + case SND_PCM_STATE_PAUSED: return "PAUSED"; + case SND_PCM_STATE_SUSPENDED: return "SUSPENDED"; + case SND_PCM_STATE_DISCONNECTED: return "DISCONNECTED"; + default: return "?"; + } +} + +// after alsa_open_playback() succeeds: +static void alsa_tune_sw(snd_pcm_t* pcm){ + snd_pcm_sw_params_t *sw = NULL; + snd_pcm_sw_params_malloc(&sw); + snd_pcm_sw_params_current(pcm, sw); + + snd_pcm_uframes_t psize=0, bsize=0; + snd_pcm_get_params(pcm, &bsize, &psize); // (buffer_size, period_size) + + // Don't start until the buffer is nearly full — prevents initial XRUN/stutter. + snd_pcm_sw_params_set_start_threshold(pcm, sw, bsize - psize); + // Wake writer when at least one period is free. + snd_pcm_sw_params_set_avail_min(pcm, sw, psize); + + snd_pcm_sw_params(pcm, sw); + snd_pcm_sw_params_free(sw); +} + +static int alsa_open_playback(snd_pcm_t **ppcm, + const char* dev, + unsigned *out_rate, + unsigned *out_channels) +{ + snd_pcm_t* pcm = NULL; + snd_pcm_hw_params_t* hw = NULL; + int rc; + + const char* card = dev && *dev ? dev : "default"; + if ((rc = snd_pcm_open(&pcm, card, SND_PCM_STREAM_PLAYBACK, 0)) < 0) { + fprintf(stderr, "ALSA: open(%s) failed: %s\n", card, snd_strerror(rc)); + return -1; + } + + snd_pcm_hw_params_malloc(&hw); + snd_pcm_hw_params_any(pcm, hw); + snd_pcm_hw_params_set_access(pcm, hw, SND_PCM_ACCESS_RW_INTERLEAVED); + snd_pcm_hw_params_set_format(pcm, hw, SND_PCM_FORMAT_S16_LE); + + unsigned rate = 48000; int dir = 0; + snd_pcm_hw_params_set_rate_near(pcm, hw, &rate, &dir); + + // try mono first; if it fails we’ll retry with 2ch + unsigned ch = 1; + rc = snd_pcm_hw_params_set_channels(pcm, hw, ch); + if (rc < 0) { + ch = 2; + rc = snd_pcm_hw_params_set_channels(pcm, hw, ch); + if (rc < 0) { fprintf(stderr,"ALSA: channels failed: %s\n", snd_strerror(rc)); goto fail; } + } + + // make buffer a bit deeper to avoid XRUN storms + snd_pcm_uframes_t period = 480; // 10 ms + snd_pcm_uframes_t buffer = 2400; // 50 ms + snd_pcm_hw_params_set_period_size_near(pcm, hw, &period, NULL); + snd_pcm_hw_params_set_buffer_size_near(pcm, hw, &buffer); + + if ((rc = snd_pcm_hw_params(pcm, hw)) < 0) { fprintf(stderr,"ALSA: hw_params: %s\n", snd_strerror(rc)); goto fail; } + snd_pcm_hw_params_free(hw); + + if ((rc = snd_pcm_prepare(pcm)) < 0) { fprintf(stderr,"ALSA: prepare: %s\n", snd_strerror(rc)); snd_pcm_close(pcm); return -1; } + + fprintf(stderr, "ALSA: opened %s, %uch, S16_LE, %u Hz\n", card, ch, rate); + *ppcm = pcm; + if (out_rate) *out_rate = rate; + if (out_channels) *out_channels = ch; + return 0; + +fail: + snd_pcm_hw_params_free(hw); + snd_pcm_close(pcm); + return -1; +} + +// ========================= TX PIPELINE ========================= +int tx_pipeline_init(tx_pipeline_t* p, sys_st* sys, + cariboulite_radio_state_st* radio, + const tx_params_t* par) +{ + if (!p || !sys || !radio || !par) return -1; + memset(p, 0, sizeof(*p)); + p->sys = sys; + p->radio = radio; + + // FIFOs + rf10_fifo_init(&p->txq, /*cap=*/64, /*drop_oldest_on_full=*/false); + + // tx_ctrl wiring (reuse your structures/threads) + p->tx_ctrl.active = true; + p->tx_ctrl.radio = radio; + p->tx_ctrl.fifo = &p->txq; + p->tx_ctrl.live_from_mic = (par->mic_dev && *par->mic_dev); + p->tx_ctrl.mic = NULL; // (open later if needed) + p->tx_ctrl.tone_mode = par->tone_mode; + p->tx_ctrl.tone_hz = par->tone_hz; + p->tx_ctrl.tone_amp = par->tone_amp; + p->tx_ctrl.tone_phase = 0.0f; + p->tx_ctrl.fm = NULL; + p->tx_ctrl.a48k = NULL; + p->tx_ctrl.iq4m = NULL; + + // NBFM mod init + nbfm4m_cfg_t cfg = { + .audio_fs = 48000.0, + .rf_fs = 4000000.0, + .f_dev_hz = par->f_dev_hz, // 2500.0 + .preemph_tau_s = 0.0, + .out_scale = par->out_scale, // 4000.0 + .linear_interp = 1, + }; + p->tx_ctrl.fm = nbfm4m_create(&cfg); + p->tx_ctrl.a48k = (float*) calloc(480, sizeof(float)); + p->tx_ctrl.iq4m = (iq16_t*)calloc(40000, sizeof(iq16_t)); + if (!p->tx_ctrl.fm || !p->tx_ctrl.a48k || !p->tx_ctrl.iq4m) { + if (p->tx_ctrl.fm) nbfm4m_destroy(p->tx_ctrl.fm); + if (p->tx_ctrl.a48k) free(p->tx_ctrl.a48k); + if (p->tx_ctrl.iq4m) free(p->tx_ctrl.iq4m); + rf10_fifo_destroy(&p->txq); + return -2; + } + + // Optional mic + if (p->tx_ctrl.live_from_mic) { + p->tx_ctrl.mic = alsa48k_create(par->mic_dev, 1.0f); + if (!p->tx_ctrl.mic) { + // mic failed — fall back to tone + p->tx_ctrl.live_from_mic = false; + p->tx_ctrl.tone_mode = true; + } + } + + // Radio basic set + HW_LOCK(); + cariboulite_radio_set_frequency(radio, true, (double*)&par->freq_hz); + cariboulite_radio_set_tx_power (radio, par->tx_power_dbm); + HW_UNLOCK(); + + // Prepare DSP/Writer threads (running idle until .start) + p->dsp_ctrl.active = true; + p->dsp_ctrl.tx = &p->tx_ctrl; + p->dsp_ctrl.fifo = &p->txq; + if (pthread_create(&p->dsp_thread, NULL, dsp_producer_thread_func, &p->dsp_ctrl) != 0) + return -3; + + if (pthread_create(&p->tx_thread, NULL, tx_writer_thread_func, &p->tx_ctrl) != 0) + return -4; + + p->inited = true; + p->running = false; + return 0; +} + +int tx_pipeline_start(tx_pipeline_t* p) +{ + if (!p || !p->inited || p->running) return -1; + + // Disable RX if it was on and arm TX chain + if (nbfm_rx_active) { + nbfm_rx_active = false; + HW_LOCK(); + cariboulite_radio_activate_channel(p->radio, cariboulite_channel_dir_rx, false); + HW_UNLOCK(); + usleep(2000); + } + + HW_LOCK(); + caribou_fpga_set_io_ctrl_mode(&p->sys->fpga, 0, caribou_fpga_io_ctrl_rfm_tx_lowpass); + cariboulite_radio_activate_channel(p->radio, cariboulite_channel_dir_tx, true); + // give writer a head-start so FIFO fills a bit + struct timespec ts = { .tv_sec = 0, .tv_nsec = 30*1000*1000 }; + nanosleep(&ts, NULL); + caribou_smi_set_driver_streaming_state(&p->sys->smi, (smi_stream_state_en)3); // TX + HW_UNLOCK(); + + __sync_synchronize(); + nbfm_tx_active = true; + + p->running = true; + return 0; +} + +void tx_pipeline_stop(tx_pipeline_t* p) +{ + if (!p || !p->inited || !p->running) return; + + nbfm_tx_active = false; + __sync_synchronize(); + + HW_LOCK(); + caribou_smi_set_driver_streaming_state(&p->sys->smi, (smi_stream_state_en)0); // idle + cariboulite_radio_activate_channel(p->radio, cariboulite_channel_dir_tx, false); + caribou_fpga_set_io_ctrl_mode(&p->sys->fpga, 0, caribou_fpga_io_ctrl_rfm_low_power); + HW_UNLOCK(); + + p->running = false; +} + +void tx_pipeline_destroy(tx_pipeline_t* p) +{ + if (!p || !p->inited) return; + + tx_pipeline_stop(p); + + // stop threads and free + p->tx_ctrl.active = false; + p->dsp_ctrl.active = false; + rf10_fifo_stop(&p->txq); + + pthread_cancel(p->tx_thread); + pthread_cancel(p->dsp_thread); + pthread_join(p->tx_thread, NULL); + pthread_join(p->dsp_thread, NULL); + + rf10_fifo_destroy(&p->txq); + + if (p->tx_ctrl.iq4m) free(p->tx_ctrl.iq4m); + if (p->tx_ctrl.a48k) free(p->tx_ctrl.a48k); + if (p->tx_ctrl.fm) nbfm4m_destroy(p->tx_ctrl.fm); + if (p->tx_ctrl.mic) alsa48k_destroy(p->tx_ctrl.mic); + + p->inited = false; +} + +// ========================= RX PIPELINE ========================= +int rx_pipeline_init(rx_pipeline_t* p, sys_st* sys, + cariboulite_radio_state_st* radio, + const rx_params_t* par) +{ + if (!p || !sys || !radio || !par) return -1; + memset(p, 0, sizeof(*p)); + p->sys = sys; + p->radio = radio; + + // FIFOs + rf10_fifo_init(&p->rxq, /*cap=*/128, /*drop_oldest_on_full=*/true); + aud10_fifo_init(&p->afifo, /*cap=*/24); + + // Open ALSA playback + unsigned rate=0, channels=0; + if (alsa_open_playback(&p->demod.pcm, par->pcm_dev, &rate, &channels) != 0) { + aud10_fifo_destroy(&p->afifo); + rf10_fifo_destroy(&p->rxq); + return -2; + } + alsa_tune_sw(p->demod.pcm); + + // Audio writer + p->aw.active = true; + p->aw.pcm = p->demod.pcm; + p->aw.channels = channels ? channels : 1; + p->aw.fifo = &p->afifo; + if (pthread_create(&p->aw_thread, NULL, audio_writer_thread, &p->aw) != 0) + return -3; + + // Demod setup + p->demod.reset = true; + p->demod.prime_blocks_10ms = 20; // 20 * 10ms = 200 ms + p->demod.priming = true; + p->demod.active = true; + p->demod.fifo_in = &p->rxq; + p->demod.afifo_out = &p->afifo; + p->demod.fs_rf = par->fs_rf; // 4e6 + p->demod.fs_audio = par->fs_audio; // 48e3 + p->demod.deemph_tau = par->deemph_tau_s; + p->demod.pcm_gain = par->pcm_gain; + p->demod.pcm_total_frames = 0; + p->demod.pcm_channels = p->aw.channels; + p->demod.pcm_rate = rate; + + if (pthread_create(&p->demod_thread, NULL, nbfm_demod_thread, &p->demod) != 0) + return -4; + + // Reader (prepare only — start later in rx_pipeline_start) + p->rx_ctrl.active = false; + p->rx_ctrl.radio = radio; + p->rx_ctrl.rx_buffer = NULL; // allocate on start + p->rx_ctrl.rx_buffer_size = 0; + p->rx_ctrl.rx_fifo = &p->rxq; + + // Set radio frequency + HW_LOCK(); + cariboulite_radio_set_frequency(radio, true, (double*)&par->freq_hz); + HW_UNLOCK(); + + p->inited = true; + p->running = false; + return 0; +} + +int rx_pipeline_start(rx_pipeline_t* p) +{ + if (!p || !p->inited || p->running) return -1; + + // Stop TX if needed + if (nbfm_tx_active) { + nbfm_tx_active = false; + __sync_synchronize(); + HW_LOCK(); + caribou_smi_set_driver_streaming_state(&p->sys->smi, (smi_stream_state_en)0); + cariboulite_radio_activate_channel(p->radio, cariboulite_channel_dir_tx, false); + caribou_fpga_set_io_ctrl_mode(&p->sys->fpga, 0, caribou_fpga_io_ctrl_rfm_low_power); + HW_UNLOCK(); + } + + HW_LOCK(); + caribou_fpga_set_io_ctrl_mode(&p->sys->fpga, 0, caribou_fpga_io_ctrl_rfm_rx_lowpass); + cariboulite_radio_activate_channel(p->radio, cariboulite_channel_dir_rx, true); + caribou_smi_set_driver_streaming_state(&p->sys->smi, (smi_stream_state_en)1); // RX on S1G + HW_UNLOCK(); + + // start reader now (only when RX is active) + p->rx_ctrl.active = true; + p->rx_ctrl.radio = p->radio; + if (!p->rx_ctrl.rx_buffer) { + p->rx_ctrl.rx_buffer = malloc(sizeof(cariboulite_sample_complex_int16) * 40000); + p->rx_ctrl.rx_buffer_size = 40000; + p->rx_ctrl.rx_fifo = &p->rxq; + } + pthread_create(&p->rx_thread, NULL, rx_reader_thread_func, &p->rx_ctrl); + + __sync_synchronize(); + + p->demod.prime_blocks_10ms = 8; // gentle start whenever RX is toggled on + p->demod.reset = true; // demod thread will reinit on next loop + + nbfm_rx_active = true; + + p->running = true; + return 0; +} + +void rx_pipeline_stop(rx_pipeline_t* p) +{ + if (!p || !p->inited || !p->running) return; + + nbfm_rx_active = false; + __sync_synchronize(); + + HW_LOCK(); + cariboulite_radio_activate_channel(p->radio, cariboulite_channel_dir_rx, false); + caribou_smi_set_driver_streaming_state(&p->sys->smi, (smi_stream_state_en)0); + caribou_fpga_set_io_ctrl_mode(&p->sys->fpga, 0, caribou_fpga_io_ctrl_rfm_low_power); + HW_UNLOCK(); + + // join reader here + p->rx_ctrl.active = false; + pthread_cancel(p->rx_thread); + pthread_join(p->rx_thread, NULL); + + + p->running = false; +} + +void rx_pipeline_destroy(rx_pipeline_t* p) +{ + if (!p || !p->inited) return; + + rx_pipeline_stop(p); + + // stop threads and free + p->rx_ctrl.active = false; + p->demod.active = false; + p->aw.active = false; + rf10_fifo_stop(&p->rxq); + aud10_fifo_stop(&p->afifo); + + pthread_cancel(p->rx_thread); + pthread_cancel(p->demod_thread); + pthread_cancel(p->aw_thread); + pthread_join(p->rx_thread, NULL); + pthread_join(p->demod_thread, NULL); + pthread_join(p->aw_thread, NULL); + + if (p->rx_ctrl.rx_buffer) { + free(p->rx_ctrl.rx_buffer); + p->rx_ctrl.rx_buffer = NULL; + } + + if (p->demod.pcm) snd_pcm_close(p->demod.pcm); + aud10_fifo_destroy(&p->afifo); + rf10_fifo_destroy(&p->rxq); + + p->inited = false; +} + +// --- helper to reinitialize all demod state (C version) --- +static void reinit_demod_state( + float *pi50, float *pq50, int *have_prev50, + float *dc_y, float *x_prev_audio, + float *deemph_state, float *lpf_y, + float *y_prev_50k, float *y_curr_50k, + double *phase48, double *corr48, + double *depth_ema, int *servo_tick, + int *primed, int *nout, + int *priming_blocks_left, + nbfm_demod_ctrl_t *c) +{ + // previous complex @50k + *pi50 = 0.0f; *pq50 = 0.0f; *have_prev50 = 0; + + // 48k chain state + *dc_y = 0.0f; *x_prev_audio = 0.0f; + *deemph_state = 0.0f; + *lpf_y = 0.0f; + *y_prev_50k = 0.0f; + *y_curr_50k = 0.0f; + + // resampler servo / accumulator + *phase48 = 0.0; + *corr48 = 0.0; + *depth_ema = 0.0; + *servo_tick = 0; + *primed = 0; + + // audio packer + *nout = 0; + + // priming counter + *priming_blocks_left = c->prime_blocks_10ms; + c->priming = (*priming_blocks_left > 0); +} + +// --- simple 1st-order de-emphasis (continuous-time tau) at fs samples/s +static inline float deemph(float x, float *y, float tau, float fs) +{ + const float a = expf(-1.0f/(fs * tau)); // pole + const float b = 1.0f - a; // zero gain so DC passes less + *y = a * (*y) + b * x; + return *y; +} + +// --- audio-rate deemphasis (48 kHz) --- +static inline float deemph_48k(float x, float *z, float tau_s) +{ + if (tau_s <= 0.f) return x; // bypass if tau==0 + const float fs = 48000.f; + const float a = expf(-1.0f/(fs * tau_s)); + const float b = 1.0f - a; + *z = a * (*z) + b * x; + return *z; +} + +static inline float fast_atan2f(float y, float x) { + // 7th-order minimax (or a lighter 3rd-order) — plenty of references online + // placeholder: use your preferred fast atan2f implementation + const float ONEQTR_PI = (float)M_PI_4; // π/4 + const float THRQTR_PI = (float)(3.0f * M_PI_4); // 3π/4 + float abs_y = fabsf(y) + 1e-10f; // prevent 0/0 + float angle; + if (x >= 0.0f) { + float r = (x - abs_y) / (x + abs_y); + angle = ONEQTR_PI - ONEQTR_PI * r; + } else { + float r = (x + abs_y) / (abs_y - x); + angle = THRQTR_PI - ONEQTR_PI * r; + } + return (y < 0.0f) ? -angle : angle; +} + +// Ultra-fast small-angle atan2f approximation +// Error < 0.005 rad for |y/x| < 0.3 (typical in NBFM discriminator) +static inline float fast_atan2f_small(float y, float x) +{ + // approximate atan(y/x) ≈ y / (|x| + 0.28f*|y|) + float abs_y = fabsf(y); + float abs_x = fabsf(x); + float angle = y / (abs_x + 0.28f * abs_y + 1e-10f); + if (x < 0.0f) + angle = (y >= 0.0f ? (float)M_PI + angle : -((float)M_PI - angle)); + return angle; +} + + +// --- FM discriminator (atan2), 3/250 resample to 48k, deemphasis at 48k --- +// --- Pre-demod CIC decimator (20 x 4) -> 50 kS/s, then limiter+atan2, 50k->48k, deemph @48k --- +// --- FM discriminator (atan2), 4M->50k integrate&dump, adaptive 50k->48k, deemph @48k --- +// --- FM discriminator (atan2), 4M->50k I&D, fixed 50k->48k (24/25), DC block, deemph @48k +// --- NBFM demod: I/Q integrate&dump to 50k -> limiter -> discriminator @50k +// -> fixed 24/25 resample to 48k -> DC block -> deemph -> light LPF +static void* nbfm_demod_thread(void* arg) +{ + pthread_setname_np(pthread_self(),"nbfm_demod_thread"); + set_rt_and_affinity_prio(55,1); + + nbfm_demod_ctrl_t* c = (nbfm_demod_ctrl_t*)arg; + if (!c || !c->fifo_in || !c->pcm) return NULL; + + // 4e6 -> 50k via integrate & dump: 20x then 4x (total 80x) + enum { D1 = 20, D2 = 4 }; // 4e6 / 80 = 50 kS/s + const float fs_mid = 50000.0f; + + // FM deviation (matches your TX) + const float f_dev = 2500.0f; + const float K_norm = fs_mid / (2.0f * (float)M_PI * f_dev); // scale dphi -> ~±1 at ±dev + + // 50k -> 48k via fixed rational 24/25 (exact) + const int L = 24, M = 25; // kept for reference (acc not used) + int acc = 0; // (unused but harmless) + float y_prev_50k = 0.0f, y_curr_50k = 0.0f; + + // Optional vector limiter + const int use_limiter = 1; + + // DC blocker at 48k (~5 Hz HPF) + const float dc_fc = 5.0f; + const float dc_a = expf(-2.0f * (float)M_PI * dc_fc / 48000.0f); + float dc_y = 0.0f, x_prev_audio = 0.0f; + + // De-emphasis state (48k) + float deemph_state = 0.0f; + + // Gentle audio LPF post-deemph (~3.2 kHz, 1st order) + const float lpf_fc = 3200.0f; + const float lpf_a = expf(-2.0f * (float)M_PI * lpf_fc / 48000.0f); + const float lpf_b = 1.0f - lpf_a; + float lpf_y = 0.0f; + + // Previous decimated complex sample for discriminator + float pi50 = 0.0f, pq50 = 0.0f; + int have_prev50 = 0; + + // --- adaptive 50k -> 48k servo (NON-static so reset works) --- + double phase48 = 0.0; // in [0..1) + double corr48 = 0.0; // small fractional correction (unitless) + double depth_ema = 0.0; // smoothed FIFO depth + int servo_tick = 0; + int primed = 0; + + // audio packer + int nout = 0; // NOTE: int (matches reinit_demod_state signature) + int priming_blocks_left = 0; + + // ---------------- Working buffers ---------------- + int16_t audio_10ms[480]; // 10 ms @ 48 kHz + size_t a10_len = 0; // (unused: you can remove if you like) + + // I&D accumulators on I and Q (do NOT demod at 4M) + float ai1 = 0.0f, aq1 = 0.0f; int cnt1 = 0; + float ai2 = 0.0f, aq2 = 0.0f; int cnt2 = 0; + + // heartbeat + uint64_t last_log_ms = 0; + + // ------------- Initialize once ------------- + if (c->prime_blocks_10ms <= 0) c->prime_blocks_10ms = 8; // sensible default + c->reset = true; // force clean start + reinit_demod_state(&pi50,&pq50,&have_prev50, + &dc_y,&x_prev_audio, + &deemph_state,&lpf_y, + &y_prev_50k,&y_curr_50k, + &phase48,&corr48, + &depth_ema,&servo_tick, + &primed,&nout, + &priming_blocks_left, c); + c->reset = false; + + while (c->active) { + + // allow external reset (e.g., after first-start flicker or frequency change) + if (c->reset) { + reinit_demod_state(&pi50,&pq50,&have_prev50, + &dc_y,&x_prev_audio, + &deemph_state,&lpf_y, + &y_prev_50k,&y_curr_50k, + &phase48,&corr48, + &depth_ema,&servo_tick, + &primed,&nout, + &priming_blocks_left, c); + c->reset = false; + } + + rf10_frame_t frm; + if (!rf10_fifo_get(c->fifo_in, &frm, -1)) continue; + + for (size_t n = 0; n < 40000; n++) { + // --- accumulate @ 4M (stage-1) --- + ai1 += (float)frm.data[n].i; + aq1 += (float)frm.data[n].q; + if (++cnt1 != D1) continue; + + // boxcar avg #1 + float i1 = ai1 / (float)D1; + float q1 = aq1 / (float)D1; + ai1 = aq1 = 0.0f; cnt1 = 0; + + // --- accumulate @ 200k (stage-2 to 50k) --- + ai2 += i1; + aq2 += q1; + if (++cnt2 != D2) continue; + + // boxcar avg #2 -> 50 kS/s complex sample + float i50 = ai2 / (float)D2; + float q50 = aq2 / (float)D2; + ai2 = aq2 = 0.0f; cnt2 = 0; + + // --- limiter (unit vector) --- + if (use_limiter) { + float m2 = i50*i50 + q50*q50; + if (m2 > 0.0f) { + float invm = 1.0f / sqrtf(m2); + i50 *= invm; q50 *= invm; + } + } + + // --- discriminator at 50 kS/s using previous 50k sample --- + float y50 = 0.0f; + if (have_prev50) { + const float re = i50 * pi50 + q50 * pq50; + const float im = q50 * pi50 - i50 * pq50; + const float dphi = fast_atan2f_small(im, re); + y50 = dphi * K_norm; // normalize to ~±1 @ ±dev + } else { + have_prev50 = 1; + } + pi50 = i50; pq50 = q50; + + // --- 50k → 48k adaptive resampler (fractional-step with tiny PLL/servo) --- + // Nominal outputs per 50k input (r < 1 for downsampling) + const double r_nom = 48000.0 / 50000.0; // 0.96 + const int upd_every_inputs = 500; // ≈10 ms @ 50 kS/s + const double alpha = 0.05; // EMA smoothing + const double ki = 2.0e-4; // integral gain + const double corr_ppm_cap = 3.0e-4; // ±300 ppm clamp + const double corr_ppm_slew = 1.0e-5; // ±10 ppm per update + const double target_fill = 0.50; // 50% of capacity + const double deadband = 0.01; // ±2% fill deadband + + // Update every ~10 ms worth of 50k inputs + if (++servo_tick >= upd_every_inputs) { + servo_tick = 0; + + size_t acnt = 0, acap = 0; + aud10_fifo_peek_depth(c->afifo_out, &acnt, &acap); + const double fill = (acap ? (double)acnt / (double)acap : 0.0); + + // smooth depth + if (depth_ema == 0.0) depth_ema = (double)acnt; // init on first call + depth_ema = (1.0 - alpha) * depth_ema + alpha * (double)acnt; + + // engage after we’re in the neighborhood (prevents big initial pulls) + if (!primed) { + if (fill >= 0.35) primed = 1; // start controlling once buffer >35% + } + + double err = 0.0; + if (primed) { + const double target = target_fill * (double)acap; + const double err_raw = (double)depth_ema - target; // +err => overfilling + if (fabs(err_raw) > deadband * (double)acap) + err = err_raw; + } + + // integral update with slew limit + double corr_prev = corr48; + corr48 += -ki * (err / (double)acap); // unitless; negative feedback + + // slew limit (per update) to avoid pitch steps + double dc = corr48 - corr_prev; + if (dc > corr_ppm_slew) corr48 = corr_prev + corr_ppm_slew; + if (dc < -corr_ppm_slew) corr48 = corr_prev - corr_ppm_slew; + + // hard clamp + if (corr48 > corr_ppm_cap) corr48 = corr_ppm_cap; + if (corr48 < -corr_ppm_cap) corr48 = -corr_ppm_cap; + + // emergency nudges + if (fill > 0.95) corr48 = fmin(corr48, -5e-4); + if (fill < 0.05) corr48 = fmax(corr48, 5e-4); + } + + // Interpolation endpoints for this 50k interval + y_prev_50k = y_curr_50k; + y_curr_50k = y50; + + // Advance phase by "outputs per input" this step (r < 1) + const double r = r_nom * (1.0 + corr48); + phase48 += r; + + // If we crossed 1.0, emit exactly one 48k sample at that crossing + if (phase48 >= 1.0) { + const double frac = (phase48 - 1.0) / r; // ∈ [0..1) + float y_lin = y_prev_50k + (float)frac * (y_curr_50k - y_prev_50k); + + // === 48k audio chain === + float x = y_lin; + float y = (x - x_prev_audio) + dc_a * dc_y; + x_prev_audio = x; + dc_y = y; if (fabsf(dc_y) < 1e-20f) dc_y = 0.0f; + + float yd = deemph_48k(y, &deemph_state, c->deemph_tau); + if (fabsf(deemph_state) < 1e-20f) deemph_state = 0.0f; + + lpf_y = lpf_a * lpf_y + lpf_b * yd; + float ya = lpf_y; + if (fabsf(lpf_y) < 1e-20f) lpf_y = 0.0f; + + float s = ya * c->pcm_gain; + if (s > 32767.f) s = 32767.f; + if (s < -32768.f) s = -32768.f; + audio_10ms[nout++] = (int16_t)lrintf(s); + + // hand off in 10 ms chunks + if (nout == 480) { + aud10_frame_t af; memcpy(af.pcm, audio_10ms, sizeof(audio_10ms)); + aud10_fifo_put(c->afifo_out, &af, /*timeout_ms=*/10); + c->pcm_total_frames += 480; + nout = 0; + + // heartbeat (optional) + struct timespec ts; clock_gettime(CLOCK_MONOTONIC, &ts); + uint64_t ms = (uint64_t)ts.tv_sec * 1000 + ts.tv_nsec / 1000000; + if (!last_log_ms) last_log_ms = ms; + if (ms - last_log_ms >= 1000) { + size_t acnt=0, acap=0; + aud10_fifo_peek_depth(c->afifo_out, &acnt, &acap); + fprintf(stderr, + "DEMOD: frames=%llu (%.1fs) ALSA=%s aud_fifo=%zu/%zu (%.0f%%) corr=%.5f\n", + (unsigned long long)c->pcm_total_frames, + (double)c->pcm_total_frames / (double)c->pcm_rate, + pcm_state_name(snd_pcm_state(c->pcm)), + acnt, acap, 100.0 * (double)acnt / (double)acap, + corr48); + last_log_ms = ms; + } + } + + // keep fractional remainder + phase48 -= 1.0; + } + } + } + return NULL; +} + +// helper: fill exactly N audio frames (blocking in small steps) +static void read_audio_exact(alsa48k_source_t* mic, float* buf, size_t need) +{ + size_t have = 0; + while (have < need) { + size_t got = alsa48k_read(mic, buf + have, need - have); + if (got == 0) { + // tiny sleep to avoid hot spin if device is momentarily empty + struct timespec ts = { .tv_sec = 0, .tv_nsec = 2 * 1000 * 1000 }; // 2 ms + nanosleep(&ts, NULL); + } + have += got; + } +} + +static void* tx_writer_thread_func(void* arg) +{ + pthread_setname_np(pthread_self(), "tx_writer_thread"); + //set_rt_and_affinity(); + //set_rt_and_affinity_prio(42,-1); + set_rt_and_affinity_prio(48,0); + + + tx_writer_ctrl_st* ctrl = (tx_writer_ctrl_st*)arg; + if (!ctrl || !ctrl->radio || !ctrl->radio->sys) return NULL; + + caribou_smi_st *smi = &ctrl->radio->sys->smi; + if (!smi || smi->filedesc < 0) return NULL; + + rf10_fifo_t* fifo = ctrl->fifo; + if (!fifo) return NULL; + + const caribou_smi_channel_en ch = + (ctrl->radio == &ctrl->radio->sys->radio_low) ? + caribou_smi_channel_900 : caribou_smi_channel_2400; + + // non-blocking fd + int flags = fcntl(smi->filedesc, F_GETFL, 0); + if (flags != -1) fcntl(smi->filedesc, F_SETFL, flags | O_NONBLOCK); + + // Discover kernel "native" buffer and its quarter size (in samples) + size_t native_bytes = caribou_smi_get_native_batch_samples(smi); + const int BYTES_PER_SAMPLE = (int)sizeof(caribou_smi_sample_complex_int16); + size_t quarter_samples = (native_bytes / 4) / BYTES_PER_SAMPLE; + if (quarter_samples == 0) quarter_samples = 8192; // safe default if ioctl failed + + // Arm TX state once, then just keep feeding + int tx_active_hw = 0; + + while (1) { + pthread_testcancel(); + if (!ctrl->active) break; + + if (!nbfm_tx_active) { + if (tx_active_hw) { + caribou_smi_set_driver_streaming_state(smi, (smi_stream_state_en)0); + tx_active_hw = 0; + } + // light idle: don't busy spin + struct timespec ts = {0, 2000000}; // 2 ms + nanosleep(&ts, NULL); + continue; + } + + if (!tx_active_hw) { + caribou_smi_set_driver_streaming_state(smi, (smi_stream_state_en)3); // TX + tx_active_hw = 1; + } + + // Get one frame from the producer (blocking). Size = 40k IQ16 samples. + rf10_frame_t frm; + if (!rf10_fifo_get(fifo, &frm, /*timeout_ms=*/-1)) { + continue; + } + + // Stream it out in chunks ≈ kernel quarter (keep kfifo topped up) + size_t off = 0; + const size_t total = sizeof(frm.data) / sizeof(frm.data[0]); // 40000 samples + struct pollfd pfd = { .fd = smi->filedesc, .events = POLLOUT, .revents = 0 }; + + while (off < total && nbfm_tx_active) { + // Aim for quarter-sized writes; last piece can be smaller + size_t todo = total - off; + if (todo > quarter_samples) todo = quarter_samples; + + // Wait until driver is ready to accept bytes + int pr = poll(&pfd, 1, 10); // short timeout; loop if needed + if (pr <= 0 || !(pfd.revents & POLLOUT)) continue; + + caribou_smi_sample_complex_int16 *p = + (caribou_smi_sample_complex_int16 *)(frm.data + off); + + int sent = caribou_smi_write_samples(smi, ch, p, (int)todo); // returns *samples* + if (sent > 0) { + off += (size_t)sent; + } else if (sent == 0 || (sent < 0 && (errno == EAGAIN || errno == EWOULDBLOCK))) { + // transient backpressure -> try again + continue; + } else { + // hard error: drop to idle cleanly + nbfm_tx_active = false; + break; + } + } + } + + if (tx_active_hw) { + caribou_smi_set_driver_streaming_state(smi, (smi_stream_state_en)0); + HW_LOCK(); + cariboulite_radio_activate_channel(ctrl->radio, cariboulite_channel_dir_tx, false); + HW_UNLOCK(); + } + return NULL; +} + +// ---------- convenience: running state ---------- +static inline bool tx_pipeline_running(const tx_pipeline_t* p) { return p && p->running; } +static inline bool rx_pipeline_running(const rx_pipeline_t* p) { return p && p->running; } + +// ---------- TX: retune / power (safe during run) ---------- +int tx_pipeline_set_freq_power(tx_pipeline_t* p, double freq_hz, int tx_power_dbm) +{ + if (!p || !p->sys || !p->radio) return -1; + HW_LOCK(); + cariboulite_radio_set_frequency(p->radio, true, &freq_hz); + cariboulite_radio_set_tx_power(p->radio, tx_power_dbm); + HW_UNLOCK(); + return 0; +} + +// ---------- RX: retune ---------- +int rx_pipeline_set_freq(rx_pipeline_t* p, double freq_hz) +{ + if (!p || !p->sys || !p->radio) return -1; + HW_LOCK(); + cariboulite_radio_set_frequency(p->radio, true, &freq_hz); + HW_UNLOCK(); + + // If running, gently reset demod so clicks/flicker are avoided post-retune + if (p->running) { + p->demod.prime_blocks_10ms = 4; // ~40 ms is often enough on retunes + p->demod.reset = true; + } + return 0; +} + +// ---------- RX: audio controls ---------- +int rx_pipeline_set_pcm_gain(rx_pipeline_t* p, float gain) +{ + if (!p) return -1; + p->demod.pcm_gain = gain; + return 0; +} +int rx_pipeline_set_deemph(rx_pipeline_t* p, float tau_s) +{ + if (!p) return -1; + p->demod.deemph_tau = tau_s; + return 0; +} + +// ---------- TX FIFO stats shim (useful for UI) ---------- +typedef struct { + rf10_stats_t txq; +} tx_pipeline_stats_t; + +static inline void tx_pipeline_get_stats(tx_pipeline_t* p, tx_pipeline_stats_t* out) +{ + if (!p || !out) return; + rf10_fifo_get_stats(&p->txq, &out->txq); +} + +// ---------- RX FIFO stats shim (useful for UI) ---------- +typedef struct { + rf10_stats_t rxq; +} rx_pipeline_stats_t; + +static inline void rx_pipeline_get_stats(rx_pipeline_t* p, rx_pipeline_stats_t* out) +{ + if (!p || !out) return; + rf10_fifo_get_stats(&p->rxq, &out->rxq); +} + +static void nbfm_tx_tone(sys_st *sys) +{ + tx_pipeline_t tx = {0}; + tx_params_t par = { + .freq_hz = 430100000.0, + .tx_power_dbm = -3, + .tone_mode = true, + .tone_hz = 600.0f, + .tone_amp = 0.4f, + .mic_dev = NULL, + .out_scale = 4000.0f, + .f_dev_hz = 2500.0f, + }; + + if (tx_pipeline_init(&tx, sys, &sys->radio_low, &par) != 0) { + fprintf(stderr, "[tx_tone] init failed\n"); + return; + } + + for (;;) { + int choice = -1; + printf("TX freq: %.0f Hz power: %d dBm\n", par.freq_hz, par.tx_power_dbm); + printf(" [1] Toggle NBFM TX [99] Return\n"); + printf(" Choice: "); + if (scanf("%d", &choice) != 1) continue; + if (choice == 1) { + if (!tx.running) { + if (tx_pipeline_start(&tx) == 0) printf("TX: ON\n"); + } else { + tx_pipeline_stop(&tx); + printf("TX: OFF\n"); + } + } else if (choice == 99) { + break; + } + } + + tx_pipeline_destroy(&tx); + printf("NBFM TX tone stopped.\n"); +} + +static void nbfm_rx(sys_st *sys) +{ + rx_pipeline_t rx = {0}; + rx_params_t par = { + .freq_hz = 430100000.0, + .pcm_dev = "plughw:3,0", + .deemph_tau_s = 50e-6f, + .pcm_gain = 8000.0f, + .fs_rf = 4000000.0f, + .fs_audio = 48000.0f, + }; + + if (rx_pipeline_init(&rx, sys, &sys->radio_low, &par) != 0) { + fprintf(stderr, "[rx] init failed\n"); + return; + } + + for (;;) { + int choice = -1; + printf("RX freq: %.0f Hz\n", par.freq_hz); + printf(" [1] Toggle NBFM RX [99] Return\n"); + printf(" Choice: "); + if (scanf("%d", &choice) != 1) continue; + if (choice == 1) { + if (!rx.running) { + if (rx_pipeline_start(&rx) == 0) printf("RX: ON\n"); + } else { + rx_pipeline_stop(&rx); + printf("RX: OFF\n"); + } + } else if (choice == 99) { + break; + } + } + + rx_pipeline_destroy(&rx); + printf("NBFM RX stopped.\n"); +} + +// --- Self-test: synthesize audio -> nbfm modulation -> IQ@4M -> nbfm demodulation -> ALSA --- +static void nbfm_modem_selftest(sys_st *sys) +{ + (void)sys; + + // 1) Create RX FIFO and start the existing demod thread pointing to ALSA + rf10_fifo_t rxq; + rf10_fifo_init(&rxq, /*cap=*/128, /*drop_oldest_on_full=*/false); + + nbfm_demod_ctrl_t dm = { + .active = true, + .fifo_in = &rxq, + .deemph_tau = 50e-6f, // or 75e-6f + .fs_rf = 4000000.0f, + .fs_audio = 48000.0f, + .deemph_y = 0.0f, + .last_i = 0, + .last_q = 0, + .pcm = NULL, + }; + + // before starting demod_th + aud10_fifo_t afifo; + aud10_fifo_init(&afifo, 64); + + // Use your playback opener (change device as needed: "default", "plughw:USB,0", etc.) + unsigned rate=0, ch=0; + if (alsa_open_playback(&dm.pcm, "plughw:3,0", &dm.pcm_rate, &dm.pcm_channels) != 0) { + fprintf(stderr, "[selftest] alsa_open_playback failed\n"); + rf10_fifo_destroy(&rxq); + return; + } + + alsa_tune_sw(dm.pcm); + + // ping: quick ping of 2.525 kHz quindar tone to verify audio path is working + int16_t ping[12000]; // 0.25s @ 48k + for (int i = 0; i < 12000; i++) { + float x = sinf(2.f * M_PI * 2525.f * (float)i / 48000.f); + ping[i] = (int16_t)lrintf(0.6f * 32767.f * x); + } + write_exact_alsa_16(dm.pcm, ping, 12000, /*channels*/dm.pcm_channels); // same as speaker-test + + + audio_writer_ctrl_t aw = { + .active = true, + .pcm = dm.pcm, + .channels = dm.pcm_channels, + .fifo = &afifo, + }; + pthread_t aw_th; + pthread_create(&aw_th, NULL, audio_writer_thread, &aw); + + dm.afifo_out = &afifo; + dm.pcm_gain = 12000.0f; + dm.pcm_channels = ch ? ch : 1; + + pthread_t demod_th; + pthread_create(&demod_th, NULL, nbfm_demod_thread, &dm); + + // 2) Build the NBFM modulator you already use in TX + nbfm4m_cfg_t cfg = { + .audio_fs = 48000.0, + .rf_fs = 4000000.0, + .f_dev_hz = 2500.0, + .preemph_tau_s = 0.0, + .out_scale = 4000.0f, + .linear_interp = 1, + }; + nbfm4m_mod_t* fm = nbfm4m_create(&cfg); + float* a48k = (float*)calloc(480, sizeof(float)); // 10 ms audio + iq16_t* iq4m = (iq16_t*)calloc(40000, sizeof(iq16_t)); // 10 ms RF + + if (!fm || !a48k || !iq4m) { + fprintf(stderr, "[selftest] alloc/mod create failed\n"); + if (fm) nbfm4m_destroy(fm); + free(a48k); free(iq4m); + dm.active = false; + rf10_fifo_stop(&rxq); + pthread_join(demod_th, NULL); + if (dm.pcm) snd_pcm_close(dm.pcm); + rf10_fifo_destroy(&rxq); + return; + } + + // 3) Run for N seconds: generate 600 Hz tone audio -> mod -> pull 40k IQ -> push to demod FIFO + const double seconds = 15.0; + const size_t loops = (size_t)(seconds * 100.0); // 100 * 10ms per second + float tone_phase = 0.0f, tone_hz = 600.0f, tone_amp = 0.6f; + const float dphi = 2.0f * (float)M_PI * (tone_hz / 48000.0f); + + for (size_t k = 0; k < loops; k++) { + // Fill 10 ms of 48k audio using your existing tone gen helper + // (If you want to use the local code: replicate fill_tone_48k logic here.) + for (size_t i = 0; i < 480; i++) { + tone_phase += dphi; + if (tone_phase >= 2.0f * (float)M_PI) tone_phase -= 2.0f * (float)M_PI; + a48k[i] = tone_amp * sinf(tone_phase); + } + + nbfm4m_push_audio(fm, a48k, 480); + + size_t pulled = 0; + while (pulled < 40000) { + pulled += nbfm4m_pull_iq(fm, iq4m + pulled, 40000 - pulled); + } + + // diagnostics: peak amplitude of the 10 ms IQ frame + int16_t peak = 0; + for (size_t i = 0; i < 40000; i++) { + int16_t ai = (int16_t)abs(iq4m[i].i); + int16_t aq = (int16_t)abs(iq4m[i].q); + if (ai > peak) peak = ai; + if (aq > peak) peak = aq; + } + static int frames_gen = 0; + if ((frames_gen++ % 50) == 0) { + fprintf(stderr, "MOD: iq_peak=%d (out_scale=%g)\n", peak, cfg.out_scale); + } + + rf10_frame_t frm; + for (size_t i = 0; i < 40000; i++) { + frm.data[i].i = iq4m[i].i; + frm.data[i].q = iq4m[i].q; + } + + // Block until demod thread consumes (no drops in self-test) + if (!rf10_fifo_put(&rxq, &frm, -1)) break; + } + + // 4) Teardown + dm.active = false; + aw.active = false; + rf10_fifo_stop(&rxq); + aud10_fifo_stop(&afifo); + pthread_join(demod_th, NULL); + pthread_cancel(aw_th); + pthread_join(aw_th, NULL); + + // ping: quick ping of 2.475 kHz tone to signal audio path is closing + // int16_t ping[12000]; // 0.25s @ 48k + for (int i = 0; i < 12000; i++) { + float x = sinf(2.f * M_PI * 2475.f * (float)i / 48000.f); + ping[i] = (int16_t)lrintf(0.6f * 32767.f * x); + } + write_exact_alsa_16(dm.pcm, ping, 12000, /*channels*/dm.pcm_channels); // same as speaker-test + usleep(250 * 1000); // wait a little so the tone doesn't get cut off + + if (dm.pcm) snd_pcm_close(dm.pcm); + aud10_fifo_destroy(&afifo); + rf10_fifo_destroy(&rxq); + nbfm4m_destroy(fm); + + free(a48k); + free(iq4m); + + fprintf(stderr, "[selftest] done — you should have heard a 600 Hz tone.\n"); +} + +void monitor_modem_status(sys_st *sys) +{ + //mlockall(MCL_CURRENT | MCL_FUTURE); + + // --- NEW: pipelines --- + tx_pipeline_t txp = {0}; + rx_pipeline_t rxp = {0}; + + tx_params_t txpar = { + .freq_hz = 430100000.0, + .tx_power_dbm = -3, + .tone_mode = true, + .tone_hz = 600.0f, + .tone_amp = 0.4f, + .mic_dev = NULL, + .out_scale = 4000.0f, + .f_dev_hz = 2500.0f, + }; + + rx_params_t rxpar = { + .freq_hz = 430100000.0, + .pcm_dev = "plughw:3,0", + .deemph_tau_s = 50e-6f, + .pcm_gain = 8000.0f, + .fs_rf = 4000000.0f, + .fs_audio = 48000.0f, + }; + + // init once (threads idle until start) + tx_pipeline_init(&txp, sys, &sys->radio_low, &txpar); + rx_pipeline_init(&rxp, sys, &sys->radio_low, &rxpar); + + nbfm_tx_active = false; + nbfm_rx_active = false; + + initscr(); // Initialize ncurses mode + cbreak(); + noecho(); + timeout(200); + + double frequency = 430100000; // Default frequency in Hz + int tx_power = -3; // Default power in dBm + + int iq_tx_buffer_size = (1u << 18); + int iq_rx_buffer_size = (1u << 18); + cariboulite_sample_complex_int16 iq_tx_buffer[iq_tx_buffer_size]; // complex CS16 samples (I, Q interleaved) + cariboulite_sample_complex_int16 iq_rx_buffer[iq_rx_buffer_size]; // complex CS16 samples (I, Q interleaved) + + + cariboulite_radio_state_st *radio = &sys->radio_low; // radio_high (HiF) || radio_low (S1G) + at86rf215_st *modem = &sys->modem; + caribou_fpga_st *fpga = &sys->fpga; + caribou_smi_st *smi = &sys->smi; + + caribou_fpga_smi_fifo_status_st status = {0}; + uint8_t *val = (uint8_t *)&status; + + uint8_t debug = 0x00; + caribou_fpga_io_ctrl_rfm_en mode = 0x00; + + pthread_t rx_thread; + rx_reader_ctrl_st rx_ctrl = { + .active = true, + .radio = radio, + .rx_buffer = iq_rx_buffer, + .rx_buffer_size = iq_rx_buffer_size, + }; + + tx_writer_ctrl_st tx_ctrl = { + .active = true, + .radio = radio, + .tx_buffer = iq_tx_buffer, + .tx_buffer_size = iq_tx_buffer_size, + }; + + + + //int screen_max_y; + int screen_max_x; + // int ret = 0; + + // Set up the radio + HW_LOCK(); + cariboulite_radio_set_frequency(radio, true, &frequency); + cariboulite_radio_set_tx_power(radio, tx_power); + HW_UNLOCK(); + radio->tx_loopback_anabled = false; // disbale | enable TX loopback for testing + radio->tx_control_with_iq_if = true; // disable | enable TX control with IQ interface + + time_t current_time; + clock_t loop_start, loop_end; + float elapsed_time = 0.0; + + static unsigned slow = 0; + + // main loop to monitor modem status + while (1) + { + + loop_start = clock(); + //getmaxyx(stdscr, screen_max_y, screen_max_x); + screen_max_x = getmaxx(stdscr); + clear(); + + time(¤t_time); + move(0,0); + printw("CaribouLite Radio [T]=TX ON/OFF [R]=RX ON/OFF [Q]=QUIT [X]=RESET"); + move(0, screen_max_x - 12); + printw("%12ld",current_time); + move(1,0); + printw(" TX Loopback: %s",radio->tx_loopback_anabled?"on":"off"); + //printw(" TX Frequency: %.0f Hz", round(frequency/1000)*1000); + //printw(" TX Power: %d dBm", tx_power); + printw(" TX Frequency: %.0f Hz", round(txpar.freq_hz/1000)*1000); + printw(" TX Power: %d dBm", txpar.tx_power_dbm); + move(1, screen_max_x - 12); + printw("%12.5f",elapsed_time); + move(2,0); + printw("Modem Status Registers:"); + move(3,0); + //refresh(); + + uint8_t data[3] = {0}; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF_IQIFC0, data, 3); + HW_UNLOCK(); + uint8_t iqifc0 = data[0]; + uint8_t iqifc1 = data[1]; + uint8_t iqifc2 = data[2]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF_CFG, data, 1); + HW_UNLOCK(); + uint8_t rf_cfg = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF_CLKO, data, 1); + HW_UNLOCK(); + uint8_t rf_clko = data[0]; + printw(" RF_CFG:0x%02X RF_CLKO:0x%02X\n", rf_cfg, rf_clko); + printw(" IQIFC0:0x%02X IQIFC1:0x%02X IQIFC2:0x%02X\n", iqifc0, iqifc1, iqifc2); + //refresh(); + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_TXDFE, data, 1); + HW_UNLOCK(); + uint8_t rf09_txdfe = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_TXDFE, data, 1); + HW_UNLOCK(); + uint8_t rf24_txdfe = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_RXDFE, data, 1); + HW_UNLOCK(); + uint8_t rf09_rxdfe = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_RXDFE, data, 1); + HW_UNLOCK(); + uint8_t rf24_rxdfe = data[0]; + printw(" RF09-RXFDE :0x%02X RF24-RXDFE :0x%02X\n", rf09_rxdfe, rf24_rxdfe); + printw(" RF09-TXFDE :0x%02X RF24-TXDFE :0x%02X\n", rf09_txdfe, rf24_txdfe); + //refresh(); + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_STATE, data, 1); + HW_UNLOCK(); + uint8_t rf09_state = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_STATE, data, 1); + HW_UNLOCK(); + uint8_t rf24_state = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_IRQS, data, 1); + HW_UNLOCK(); + uint8_t rf09_irqs = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_IRQS, data, 1); + HW_UNLOCK(); + uint8_t rf24_irqs = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_IRQM, data, 1); + HW_UNLOCK(); + uint8_t rf09_irqm = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_IRQM, data, 1); + HW_UNLOCK(); + uint8_t rf24_irqm = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_PAC, data, 1); + HW_UNLOCK(); + uint8_t rf09_pac = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_PAC, data, 1); + HW_UNLOCK(); + uint8_t rf24_pac = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF09_PADFE, data, 1); + HW_UNLOCK(); + uint8_t rf09_padfe = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, REG_RF24_PADFE, data, 1); + HW_UNLOCK(); + uint8_t rf24_padfe = data[0]; + HW_LOCK(); + at86rf215_read_buffer(modem, 0x0127, data, 2); //REG_RF09_TXDACI, REG_RF09_TXDACQ + HW_UNLOCK(); + uint8_t rf09_txdaci = data[0]; + uint8_t rf09_txdacq = data[1]; + HW_LOCK(); + at86rf215_read_buffer(modem, 0x0227, data, 2); //REG_RF24_TXDACI, REG_RF24_TXDACQ + HW_UNLOCK(); + uint8_t rf24_txdaci = data[0]; + uint8_t rf24_txdacq = data[1]; + printw(" RF09-PADFE :0x%02X RF24-PADFE :0x%02X\n", rf09_padfe, rf24_padfe); + printw(" RF09-PAC :0x%02X RF24-PAC :0x%02X\n", rf09_pac, rf24_pac); + printw(" RF09-IRQM :0x%02X RF24-IRQM :0x%02X\n", rf09_irqm, rf24_irqm); + printw(" RF09-IQRS :0x%02X RF24-IRQS :0x%02X\n", rf09_irqs, rf24_irqs); + printw(" RF09-STATE :0x%02X RF24-STATE :0x%02X\n", rf09_state, rf24_state); + printw(" RF09-TXDACI:0x%02X RF24-TXDACI:0x%02X\n", rf09_txdaci, rf24_txdaci); + printw(" RF09-TXDACQ:0x%02X RF24-TXDACQ:0x%02X\n", rf09_txdacq, rf24_txdacq); + //refresh(); + HW_LOCK(); + caribou_fpga_get_smi_ctrl_fifo_status(&sys->fpga, &status); + HW_UNLOCK(); + printw("FPGA SMI info (0x%02X):\n", *val); + printw(" RX FIFO EMPTY: %d\n", status.rx_fifo_empty); + printw(" TX FIFO FULL : %d\n", status.tx_fifo_full); + printw(" SMI CHANNEL : %d // 0=RX09 1=RX24\n", status.smi_channel); + printw(" SMI DIRECTION: %d // 0=TX 1=RX\n", status.smi_direction); + //refresh(); + HW_LOCK(); + caribou_fpga_get_io_ctrl_mode(&sys->fpga, &debug, &mode); + HW_UNLOCK(); + printw(" DEBUG = %d, MODE: '%s'\n", debug, caribou_fpga_get_mode_name(mode)); + //refresh(); + printw("IQ Data Stream:\n"); + printw(" TX_I:0x%08X TX_Q:0x%08X\n", latest_tx_sample.i, latest_tx_sample.q); + printw(" RX_I:0x%08X RX_Q:0x%08X\n", latest_rx_sample.i, latest_rx_sample.q); + //refresh(); + //smi_state = caribou_smi_get_driver_streaming_state(smi); + //printw("SMI driver state: 0x%02X // 0=idle 1=RX09 2=RX24 3=TX\n",(uint8_t) smi->state); + uint8_t tx_sample_gap = 1; + HW_LOCK(); + caribou_fpga_get_sys_ctrl_tx_sample_gap(fpga, &tx_sample_gap); + HW_UNLOCK(); + //printw("TX sample gap: %d\n", tx_sample_gap); + //refresh(); + + // --- TX FIFO stats panel --- + + tx_pipeline_stats_t tst; + tx_pipeline_get_stats(&txp, &tst); + rf10_stats_t stx = tst.txq; + float tx_fill_pct = (stx.cap ? (100.0f * (float)stx.count / (float)stx.cap) : 0.f); + + // optional: rates since last sample + static struct timespec tx_last_ts = {0}; + static rf10_stats_t tx_last_s = {0}; + double tx_rate_puts = 0.0, tx_rate_gets = 0.0; + + struct timespec now; + clock_gettime(CLOCK_MONOTONIC, &now); + if (tx_last_ts.tv_sec != 0) { + double dt = (now.tv_sec - tx_last_ts.tv_sec) + (now.tv_nsec - tx_last_ts.tv_nsec)/1e9; + if (dt > 0.0) { + tx_rate_puts = (double)(stx.puts - tx_last_s.puts) / dt; + tx_rate_gets = (double)(stx.gets - tx_last_s.gets) / dt; + } + } + tx_last_ts = now; tx_last_s = stx; + + printw("Linux TX FIFO:\n"); + printw(" depth: %zu/%zu (%.0f%%), min:%zu max:%zu\n", + stx.count, stx.cap, tx_fill_pct, stx.min_depth, stx.max_depth); + printw(" puts:%zu gets:%zu drops:%zu tO_put:%zu tO_get:%zu\n", + stx.puts, stx.gets, stx.drops, stx.timeouts_put, stx.timeouts_get); + printw(" rate: puts %.1f/s, gets %.1f/s (expect ~100 fps @ 10ms)\n", + tx_rate_puts, tx_rate_gets); + + // If you want to highlight trouble: + if (stx.min_depth == 0) printw(" NOTE: Under-runs observed (producer late)\n"); + if (stx.drops > 0) printw(" NOTE: Overwrites occurred (producer faster than writer)\n"); + if (stx.timeouts_put > 0) printw(" NOTE: Producer timed out waiting to enqueue\n"); + if (stx.timeouts_get > 0) printw(" NOTE: Writer timed out waiting for frames\n"); + + rx_pipeline_stats_t rst; + rx_pipeline_get_stats(&rxp, &rst); + rf10_stats_t srx = rst.rxq; + float rx_fill_pct = (srx.cap ? (100.0f * (float)srx.count / (float)srx.cap) : 0.f); + + // optional: rates since last sample + static struct timespec rx_last_ts = {0}; + static rf10_stats_t rx_last_s = {0}; + double rx_rate_puts = 0.0, rx_rate_gets = 0.0; + + if (rx_last_ts.tv_sec != 0) { + double dt = (now.tv_sec - rx_last_ts.tv_sec) + (now.tv_nsec - rx_last_ts.tv_nsec)/1e9; + if (dt > 0.0) { + rx_rate_puts = (double)(srx.puts - rx_last_s.puts) / dt; + rx_rate_gets = (double)(srx.gets - rx_last_s.gets) / dt; + } + } + rx_last_ts = now; rx_last_s = srx; + + printw("Linux RX FIFO:\n"); + printw(" depth: %zu/%zu (%.0f%%), min:%zu max:%zu\n", + srx.count, srx.cap, rx_fill_pct, srx.min_depth, srx.max_depth); + printw(" puts:%zu gets:%zu drops:%zu tO_put:%zu tO_get:%zu\n", + srx.puts, srx.gets, srx.drops, srx.timeouts_put, srx.timeouts_get); + printw(" rate: puts %.1f/s, gets %.1f/s (expect ~100 fps @ 10ms)\n", + rx_rate_puts, rx_rate_gets); + + // Same “trouble” hints, adapted to RX roles + if (srx.min_depth == 0) printw(" NOTE: Under-runs observed (reader late)\n"); + if (srx.drops > 0) printw(" NOTE: Overwrites occurred (demod slower than reader)\n"); + if (srx.timeouts_put > 0) printw(" NOTE: Reader timed out waiting to enqueue\n"); + if (srx.timeouts_get > 0) printw(" NOTE: Demod timed out waiting for frames\n"); + + char key = 0; + key = getch(); + + if(key == 'q') // Press 'q' to exit + { + break; + } + + if (key == 'x' || key == 'X') { // reset FIFO diagnostics + rf10_fifo_reset_stats(&txp.txq); + rf10_fifo_reset_stats(&rxp.rxq); + } + + // --- T: toggle TX --- + if (key == 't') { + if (!tx_pipeline_running(&txp)) { + // ensure RX is off (pipeline start already does this defensively) + rx_pipeline_stop(&rxp); + tx_pipeline_start(&txp); + } else { + tx_pipeline_stop(&txp); + } + } + + // --- R: toggle RX --- + if (key == 'r') { + if (!rx_pipeline_running(&rxp)) { + tx_pipeline_stop(&txp); + rx_pipeline_start(&rxp); + } else { + rx_pipeline_stop(&rxp); + } + } + + loop_end = clock(); + elapsed_time = (float)(loop_end - loop_start)/ (float)CLOCKS_PER_SEC; + + } + + smi_idle(sys); // force driver to IDLE (unblocks reads/writes if they’re waiting) + + HW_LOCK(); + cariboulite_radio_activate_channel(radio, cariboulite_channel_dir_tx, false); + cariboulite_radio_activate_channel(radio, cariboulite_channel_dir_rx, false); + HW_UNLOCK(); + usleep(30 * 1000); + + // put driver idle first + smi_idle(sys); + + // stop/destroy pipelines (order doesn’t matter now) + tx_pipeline_destroy(&txp); + rx_pipeline_destroy(&rxp); + + printw("Monitoring stopped.\n"); + //refresh(); + endwin(); // End ncurses mode + return; +} + +//================================================= +int app_menu(sys_st* sys) +{ + printf("\n"); + printf(" ____ _ _ _ _ _ \n"); + printf(" / ___|__ _ _ __(_) |__ ___ _ _| | (_) |_ ___ \n"); + printf(" | | / _` | '__| | '_ \\ / _ \\| | | | | | | __/ _ \\ \n"); + printf(" | |__| (_| | | | | |_) | (_) | |_| | |___| | || __/ \n"); + printf(" \\____\\__,_|_| |_|_.__/ \\___/ \\__,_|_____|_|\\__\\___| \n"); + printf("\n\n"); + + while (1) + { + int choice = -1; + printf(" Select a function:\n"); + for (int i = 0; i < NUM_HANDLES; i++) + { + printf(" [%2d] %s\n", handles[i].num, handles[i].text); + } + printf(" [%2d] %s\n", app_selection_quit, "Quit"); + + printf(" Choice: "); + if (scanf("%2d", &choice) != 1) continue; + + if ((app_selection_en)(choice) == app_selection_quit) return 0; + for (int i = 0; i < NUM_HANDLES; i++) + { + if (handles[i].num == (app_selection_en)(choice)) + { + if (handles[i].handle != NULL) + { + printf("\n=====================================\n"); + handles[i].handle(sys); + printf("\n=====================================\n"); + } + else + { + printf(" Choice %d is not implemented\n", choice); + } + } + } - if ((app_selection_en)(choice) == app_selection_quit) return 0; - for (int i = 0; i < NUM_HANDLES; i++) - { - if (handles[i].num == (app_selection_en)(choice)) - { - if (handles[i].handle != NULL) - { - printf("\n=====================================\n"); - handles[i].handle(sys); - printf("\n=====================================\n"); - } - else - { - printf(" Choice %d is not implemented\n", choice); - } - } - } } return 1; } diff --git a/software/libcariboulite/src/at86rf215/at86rf215.c b/software/libcariboulite/src/at86rf215/at86rf215.c index a4042ed8..217b0eee 100644 --- a/software/libcariboulite/src/at86rf215/at86rf215.c +++ b/software/libcariboulite/src/at86rf215/at86rf215.c @@ -421,6 +421,10 @@ void at86rf215_get_iq_if_cfg(at86rf215_st* dev, at86rf215_iq_interface_config_st if (verbose) { printf("Current I/Q interface settings:\n"); + printf(" RF_IQIFC0: 0x%02x\n",data[0]); + printf(" RF_IQIFC1: 0x%02x\n",data[1]); + printf(" RF_IQIFC2: 0x%02x\n",data[2]); + printf("\n"); printf(" Loopback (RX => TX): %s\n", cfg->loopback_enable?"enabled":"disabled"); printf(" Drive strength: %d mA\n", cfg->drv_strength+1); @@ -433,6 +437,7 @@ void at86rf215_get_iq_if_cfg(at86rf215_st* dev, at86rf215_iq_interface_config_st printf(" Common mode voltage: %d mV\n", (cfg->common_mode_voltage+1) * 50 + 100); } + printf(" TX control with I/Q data: %s\n", cfg->tx_control_with_iq_if?"enabled":"disabled"); printf(" I/Q interface for sub-GHz: %s\n", cfg->radio09_mode==at86rf215_iq_if_mode?"enabled":"diabled"); printf(" I/Q interface for 2.4-GHz: %s\n", cfg->radio24_mode==at86rf215_iq_if_mode?"enabled":"diabled"); printf(" I/Q Clock <=> Data skew: %.3f ns\n", cfg->clock_skew+1.906f); @@ -525,14 +530,71 @@ void at86rf215_setup_iq_radio_transmit (at86rf215_st* dev, at86rf215_rf_channel_ /* It is assumed, that the radio has been reset before and is in State TRXOFF. All interrupts in register RFn_IRQS should be enabled (RFn_IRQM=0x3f). */ + + at86rf215_iq_clock_data_skew_en skew = 2; // 0 = 1.906 ns, 1 = 2.906 ns, 2 = 3.906 ns, 3 = 4.906 ns + uint8_t iqloopback = 0; // 0 = disabled, 1 = enabled + double frequency = 430100000; // Hz + int tx_power = -10; // dBm + // 1. Set TRXOFF mode - // 2. Enable all interrupts in 09,_24_IRQS - // 3. Enable I/Q radio mode - setting IQIFC1.CHPM=1 at AT86RF215 + at86rf215_radio_set_state(dev, radio, at86rf215_radio_state_cmd_trx_off); + + // 2. Enable all radio interrupts in 09,_24_IRQS + at86rf215_radio_irq_st int_mask = { + .wake_up_por = 1, + .trx_ready = 1, + .energy_detection_complete = 1, + .battery_low = 1, + .trx_error = 1, + .IQ_if_sync_fail = 1, + .res = 0, + }; + at86rf215_radio_setup_interrupt_mask(dev, radio, &int_mask); + + // 3. Enable I/Q radio mode - setting IQIFC1.CHPM=1 at AT86RF215 (in AT86RF215IQ it is the only choice) + at86rf215_iq_interface_config_st iq_if_config = + { + .loopback_enable = iqloopback, + .drv_strength = at86rf215_iq_drive_current_4ma, + .common_mode_voltage = at86rf215_iq_common_mode_v_ieee1596_1v2, + .tx_control_with_iq_if = false, + .radio09_mode = at86rf215_iq_if_mode, + .radio24_mode = at86rf215_iq_if_mode, + .clock_skew = skew, + }; + at86rf215_setup_iq_if(dev, &iq_if_config); + // 4. Configure the Transmitter Frontend: // Set the transmitter analog frontend sub-registers TXCUTC.LPFCUT and TXCUTC.PARAMP // Set the transmitter digital frontend sub-registers TXDFE.SR and TXDFE.RCUT + at86rf215_radio_tx_ctrl_st tx_config = + { + .pa_ramping_time = at86rf215_radio_tx_pa_ramp_32usec, + .current_reduction = at86rf215_radio_pa_current_reduction_0ma, + .tx_power = tx_power, + .analog_bw = at86rf215_radio_tx_cut_off_80khz, + .digital_bw = at86rf215_radio_rx_f_cut_half_fs, + .fs = at86rf215_radio_rx_sample_rate_4000khz, + .direct_modulation = 0, + }; + at86rf215_radio_setup_tx_ctrl(dev, radio, &tx_config); + + at86rf215_radio_external_ctrl_st aux_cfg = + { + .ext_lna_bypass_available = 0, + .agc_backoff = 0, + .analog_voltage_external = 0, + .analog_voltage_enable_in_off = 0, + .int_power_amplifier_voltage = 2, + .fe_pad_configuration = 1, + }; + at86rf215_radio_setup_external_settings(dev, radio, &aux_cfg); + + // 5. Configure the channel parameters, see section "Channel Configuration" on page 62 and transmit power + at86rf215_setup_channel(dev, radio, frequency); + // 6. Optional: Perform ED measurement, see section "Energy Measurement" on page 56. The following steps are recommended: // Configure the measurement period, see register RFn_EDD. // Switch to State RX. @@ -540,11 +602,18 @@ void at86rf215_setup_iq_radio_transmit (at86rf215_st* dev, at86rf215_rf_channel_ // For single and continuous ED modes a measurement starts if the mode is written to sub-register EDC.EDM. // The completion of the measurement is indicated by the interrupt IRQS.EDC. The resulting ED value can be read from register RFn_EDV. // For the automatic mode, a measurement starts by setting bit AGCC.FRZC=1. After the completion of the measurement period, the ED value can be read from register RFn_EDV. + // 7. Switch to State TXPREP; interrupt IRQS.TRXRDY is issued. + at86rf215_radio_set_state(dev, radio, at86rf215_radio_state_cmd_tx_prep); + + // 8. To start the actual transmission, there are two possibilities, depending on the setting of sub-register IQIFC0.EEC: // IQIFC0.EEC=0 => Enable the radio transmitter by writing command TX to the register RFn_CMD via SPI. // IQIFC0.EEC=1 => The transmitter is activated automatically with the TX start signal embedded in I_DATA[0], + at86rf215_radio_set_state(dev, radio, at86rf215_radio_state_cmd_tx); + // 9. To finish a transmission depends on the setting of bit IQIFC0.EEC: + // IQIFC0.EEC=0 => To leave the State TX, write command TXPREP to the register RFn_CMD. Reaching State TXPREP is indicated by the interrupt IRQS.TRXRDY. // IQIFC0.EEC=1 => If the bit I_DATA[0] is set to 0 (see Figure 6-4 on page 47) the ramp down process of the PA is started automatically. After ramp down the transmitter switches back to State TXPREP. } @@ -564,7 +633,8 @@ void at86rf215_setup_iq_radio_receive (at86rf215_st* dev, at86rf215_rf_channel_e // 2. Enable all radio interrupts in 09,_24_IRQS - at86rf215_radio_irq_st int_mask = { + at86rf215_radio_irq_st int_mask = + { .wake_up_por = 1, .trx_ready = 1, .energy_detection_complete = 1, diff --git a/software/libcariboulite/src/audio48k_source.h b/software/libcariboulite/src/audio48k_source.h new file mode 100644 index 00000000..b5749925 --- /dev/null +++ b/software/libcariboulite/src/audio48k_source.h @@ -0,0 +1,16 @@ +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct audio48k_source audio48k_source_t; + +audio48k_source_t* tone48k_create(double freq_hz, float amplitude); +size_t audio48k_read(audio48k_source_t* s, float* dst, size_t max_frames); +void audio48k_destroy(audio48k_source_t* s); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/software/libcariboulite/src/caribou-mini.c b/software/libcariboulite/src/caribou-mini.c new file mode 100644 index 00000000..4a7b6261 --- /dev/null +++ b/software/libcariboulite/src/caribou-mini.c @@ -0,0 +1,537 @@ +// caribou-mini.c — minimal, real-time friendly CaribouLite control app +// Features +// - Hard/soft reset FPGA +// - Program FPGA from file (SOURCE) +// - Monitor key SMI/FPGA/modem registers at ~10 Hz +// - Toggle RX and TX (TX = continuous 600 Hz complex tone) +// - TX thread owns activation + streaming with prefill; UI is non-blocking +// - RT scheduling, CPU affinity, mlockall +// +// Notes +// - Adjust include paths and link flags to your environment. +// - Ensure EEC=1 (TX_EN on I.MSB). We set the MSB of I for every symbol during TX. +// - Replace init/shutdown calls with your actual CaribouLite setup if names differ. +// +// Build (example; adapt libs as needed): +// gcc -O2 -pipe -Wall -Wextra -pthread caribou-mini.c -o caribou-mini -lncurses -lm -lcariboulite +// You may also need: -lat86rf215 -lcariboufpga -lcaribousmi (depending on how the lib is packaged) +// Run with privileges for RT scheduling, or grant capability: +// sudo setcap 'cap_sys_nice=eip' ./caribou-mini +// ./caribou-mini [firmware.bit] + +// Enable POSIX/GNU extensions for sigaction/siginfo_t, etc. +#ifndef _POSIX_C_SOURCE +# define _POSIX_C_SOURCE 200809L +#endif +#ifndef _GNU_SOURCE +# define _GNU_SOURCE +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +// CaribouLite headers (adjust paths/names if needed) +#include "cariboulite.h" +#include "cariboulite_setup.h" +#include + +CARIBOULITE_CONFIG_DEFAULT(cariboulite_sys); + +// ---------------- Configuration ----------------- +#ifndef SOURCE + #define SOURCE "./top.bin" // default firmware image path (overridden by argv[1]) +#endif + +#define APP_SAMPLE_RATE 4000000.0 // Hz (adjust to your configured SMI/DUC rate) +#define TONE_HZ 600.0 // FM test tone baseband frequency (complex sinusoid) +#define TX_PREFILL_CHUNKS 12 // initial prefill chunks +#define TX_CHUNK_MAX_SAMPS 16384 // 16k complex samples per write (~64 KB) +#define RING_SAMPLES_POW2 18 // 2^18 complex samples ~ 131 ms @ 2 MS/s (65 ms @ 4 MS/s) + +// ---------------- Types & Globals ---------------- +typedef struct { + sys_st *sys; // CaribouLite system + cariboulite_radio_state_st *radio; // using S1G (low) by default + at86rf215_st *modem; + caribou_fpga_st *fpga; + caribou_smi_st *smi; +} app_ctx_t; + +static atomic_bool g_run = true; +static atomic_bool g_tx_want = false; // UI intent: TX on/off +static atomic_bool g_rx_want = false; // UI intent: RX on/off +static atomic_bool g_tx_running = false; +static atomic_bool g_rx_running = false; + +// Snapshots updated by monitor thread, read by UI +typedef struct { + uint8_t iqifc0, iqifc1, iqifc2; + uint8_t rf09_txdfe, rf24_txdfe; + uint8_t rf09_rxdfe, rf24_rxdfe; + uint8_t rf09_state, rf24_state; + uint8_t rf09_irqs, rf24_irqs; + uint8_t rf09_irqm, rf24_irqm; + uint8_t rf09_pac, rf24_pac; + uint8_t rf09_padfe, rf24_padfe; + uint8_t smi_info_raw; + uint8_t smi_rx_fifo_empty; + uint8_t smi_tx_fifo_full; + uint8_t smi_channel; + uint8_t smi_direction; + uint8_t rffe_debug; + caribou_fpga_io_ctrl_rfm_en rffe_mode; + uint8_t driver_state; // 0=idle 1=RX09 2=RX24 3=TX (per your struct) +} mon_snapshot_t; + +static mon_snapshot_t g_mon = {0}; + +// TX ring buffer +static const size_t RING_SAMPLES = (1u << RING_SAMPLES_POW2); +static cariboulite_sample_complex_int16 *g_tx_ring = NULL; // [I,Q] as struct {int16_t i; int16_t q;} +static size_t g_tx_idx = 0; // producer index (thread-owned) + +// latest samples for UI +static atomic_int g_last_tx_i = 0; +static atomic_int g_last_tx_q = 0; +static atomic_int g_last_rx_i = 0; +static atomic_int g_last_rx_q = 0; + +// ---------------- Utilities ---------------- +static inline void set_rt_and_affinity(int prio, int cpu) +{ + (void)prio; (void)cpu; // Temporary disable RT unitl stable +// struct sched_param sp = { .sched_priority = prio }; +// pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp); +// #ifdef __linux__ +// if (cpu >= 0) { +// cpu_set_t set; CPU_ZERO(&set); CPU_SET(cpu, &set); +// pthread_setaffinity_np(pthread_self(), sizeof(set), &set); +// } +// #endif +// mlockall(MCL_CURRENT | MCL_FUTURE); +} + + +static void app_sa_handler(int sig, siginfo_t *si, void *uctx) +{ + (void)si; (void)uctx; + atomic_store(&g_tx_want, false); + atomic_store(&g_rx_want, false); + atomic_store(&g_run, false); + const char msg[] = "caught signal, shutting down...\n"; + write(STDERR_FILENO, msg, sizeof(msg)-1); +} + +static int install_app_signal_handlers(void) +{ + struct sigaction sa; + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = app_sa_handler; + sa.sa_flags = SA_SIGINFO; + + int rc = 0; + rc |= sigaction(SIGINT, &sa, NULL); + rc |= sigaction(SIGTERM, &sa, NULL); + rc |= sigaction(SIGSEGV, &sa, NULL); + rc |= sigaction(SIGHUP, &sa, NULL); + return rc; +} + +static inline int16_t set_tx_en(int16_t i) { return i | 0x8000; } // EEC=1 => TX_EN on I.MSB + +static void force_radio_idle(app_ctx_t *ctx) +{ + // best-effort: turn both dirs off on the current radio + if (ctx && ctx->radio) { + cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_tx, false); + cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_rx, false); + } +} + +static void fill_tx_ring_tone(double fs_hz) +{ + // Generate a continuous complex sinusoid at TONE_HZ (cos + j*sin), + // amplitude ~0.5 FS, and set TX_EN bit on I.MSB. + const double two_pi_f_over_fs = 2.0 * M_PI * TONE_HZ / fs_hz; + double ph = 0.0; + + for (size_t n = 0; n < RING_SAMPLES; n++) { + double c = cos(ph), s = sin(ph); + int16_t I = (int16_t)(c * 4000.0); + int16_t Q = (int16_t)(s * 4000.0); + I = set_tx_en(I); + g_tx_ring[n].i = I; g_tx_ring[n].q = Q; + ph += two_pi_f_over_fs; + if (ph >= 2.0 * M_PI) ph -= 2.0 * M_PI; + } +} + +// ---------------- Threads ---------------- +static void *monitor_thread(void *arg) +{ + app_ctx_t *ctx = (app_ctx_t *)arg; + const int period_ms = 100; // 10 Hz + + while (atomic_load(&g_run)) { + if (!ctx || !ctx->fpga || !ctx->modem || !ctx->smi) { + usleep(1000); + continue; + } + + caribou_fpga_smi_fifo_status_st st = {0}; + int rc = caribou_fpga_get_smi_ctrl_fifo_status(ctx->fpga, &st); + if (rc == 0) { + g_mon.smi_info_raw = *((uint8_t*)&st); + g_mon.smi_rx_fifo_empty = st.rx_fifo_empty; + g_mon.smi_tx_fifo_full = st.tx_fifo_full; + g_mon.smi_channel = st.smi_channel; + g_mon.smi_direction = st.smi_direction; + } else { + // If driver not ready, don’t crash the app — just note it + g_mon.smi_info_raw = 0xFF; + } + + uint8_t d[3] = {0}; + at86rf215_read_buffer(ctx->modem, REG_RF_IQIFC0, d, 3); + g_mon.iqifc0 = d[0]; g_mon.iqifc1 = d[1]; g_mon.iqifc2 = d[2]; + + at86rf215_read_buffer(ctx->modem, REG_RF09_TXDFE, d, 1); g_mon.rf09_txdfe = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_TXDFE, d, 1); g_mon.rf24_txdfe = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF09_RXDFE, d, 1); g_mon.rf09_rxdfe = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_RXDFE, d, 1); g_mon.rf24_rxdfe = d[0]; + + at86rf215_read_buffer(ctx->modem, REG_RF09_STATE, d, 1); g_mon.rf09_state = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_STATE, d, 1); g_mon.rf24_state = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF09_IRQS, d, 1); g_mon.rf09_irqs = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_IRQS, d, 1); g_mon.rf24_irqs = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF09_IRQM, d, 1); g_mon.rf09_irqm = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_IRQM, d, 1); g_mon.rf24_irqm = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF09_PAC, d, 1); g_mon.rf09_pac = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_PAC, d, 1); g_mon.rf24_pac = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF09_PADFE, d, 1); g_mon.rf09_padfe = d[0]; + at86rf215_read_buffer(ctx->modem, REG_RF24_PADFE, d, 1); g_mon.rf24_padfe = d[0]; + + uint8_t debug=0; caribou_fpga_io_ctrl_rfm_en mode=0; + if (caribou_fpga_get_io_ctrl_mode(ctx->fpga, &debug, &mode) == 0) { + g_mon.rffe_debug = debug; g_mon.rffe_mode = mode; + } + + // driver state snapshot (guard) + if (ctx->smi) g_mon.driver_state = (uint8_t)ctx->smi->state; + + struct timespec ts = { .tv_sec = 0, .tv_nsec = 100 * 1000000L }; + nanosleep(&ts, NULL); + } + return NULL; +} + +static void *rx_thread(void *arg) +{ + app_ctx_t *ctx = (app_ctx_t *)arg; + set_rt_and_affinity(40, 1); // moderate RT prio on another core + + size_t batch = caribou_smi_get_native_batch_samples(ctx->smi); + if (batch == 0) batch = 4096; + + cariboulite_sample_complex_int16 *buf = (cariboulite_sample_complex_int16*)malloc(sizeof(*buf) * batch); + cariboulite_sample_meta *md = (cariboulite_sample_meta*)malloc(sizeof(*md) * batch); + + bool running = false; + + while (atomic_load(&g_run)) { + bool want = atomic_load(&g_rx_want); + + if (want && !running) { + cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_rx, true); + running = true; + atomic_store(&g_rx_running, true); + } + if (!want && running) { + cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_rx, false); + running = false; + atomic_store(&g_rx_running, false); + } + + if (running) { + int got = cariboulite_radio_read_samples(ctx->radio, buf, md, batch); + if (got > 0) { + cariboulite_sample_complex_int16 s = buf[got>>1]; + atomic_store(&g_last_rx_i, s.i); + atomic_store(&g_last_rx_q, s.q); + } else if (got == 0) { + sched_yield(); + } else { + usleep(200); + } + } else { + usleep(1000); + } + } + + + if (running) { cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_rx, false); } + atomic_store(&g_rx_running, false); + free(md); free(buf); + return NULL; +} + +static void *tx_thread(void *arg) +{ + app_ctx_t *ctx = (app_ctx_t *)arg; + set_rt_and_affinity(80, 2); // high RT prio, third core + + size_t native = caribou_smi_get_native_batch_samples(ctx->smi); + size_t chunk = native ? native : 1024; + if (chunk > 2048) chunk = 2048; + if (chunk > RING_SAMPLES) chunk = RING_SAMPLES; + + bool running = false; + + while (atomic_load(&g_run)) { + bool want = atomic_load(&g_tx_want); + + if (want && !running) { + // Radio setup (idempotent) + double f = 430.1e6; cariboulite_radio_set_frequency(ctx->radio, true, &f); + cariboulite_radio_set_tx_power(ctx->radio, -10); + cariboulite_radio_set_tx_bandwidth(ctx->radio, cariboulite_radio_tx_cut_off_80khz); + + // Activate and prefill + if (cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_tx, true) == 0) { + running = true; + atomic_store(&g_tx_running, true); + for (int i = 0; i < TX_PREFILL_CHUNKS; i++) { + int sent = cariboulite_radio_write_samples(ctx->radio, &g_tx_ring[g_tx_idx], chunk); + if (sent <= 0) break; + g_tx_idx = (g_tx_idx + (size_t)sent) % RING_SAMPLES; + } + sched_yield(); + } + } + + if (!want && running) { + cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_tx, false); + running = false; + atomic_store(&g_tx_running, false); + } + + if (running) { + int sent = cariboulite_radio_write_samples(ctx->radio, &g_tx_ring[g_tx_idx], chunk); + if (sent > 0) { + cariboulite_sample_complex_int16 s = g_tx_ring[g_tx_idx]; + atomic_store(&g_last_tx_i, s.i); + atomic_store(&g_last_tx_q, s.q); + g_tx_idx = (g_tx_idx + (size_t)sent) % RING_SAMPLES; + } else if (sent == 0) { + //sched_yield(); + usleep(500); + } else { + atomic_store(&g_tx_want, false); // fatal error, stop + usleep(1000); + } + } else { + usleep(1000); + } + } + + if (running) { cariboulite_radio_activate_channel(ctx->radio, cariboulite_channel_dir_tx, false); } + atomic_store(&g_tx_running, false); + return NULL; +} + +// ---------------- UI & Main ---------------- +static void draw_ui(const app_ctx_t *ctx) +{ + erase(); + + time_t now = time(NULL); + mvprintw(0, 0, "caribou-mini — %s", ctime(&now)); + + mvprintw(2, 0, "Keys: [H]ard reset [S]oft reset [P]rogram FPGA [T]X toggle [R]X toggle [Q]uit"); + + mvprintw(4, 0, "TX want: %s RX want: %s", atomic_load(&g_tx_want)?"ON":"OFF", atomic_load(&g_rx_want)?"ON":"OFF"); + + mvprintw(6, 0, "SMI info: 0x%02X RX_EMPTY:%d TX_FULL:%d CH:%d DIR:%d drv_state:%u", + g_mon.smi_info_raw, g_mon.smi_rx_fifo_empty, g_mon.smi_tx_fifo_full, + g_mon.smi_channel, g_mon.smi_direction, g_mon.driver_state); + + mvprintw(8, 0, "IQIFC0:0x%02X IQIFC1:0x%02X IQIFC2:0x%02X", + g_mon.iqifc0, g_mon.iqifc1, g_mon.iqifc2); + mvprintw(9, 0, "RF09 TXDFE:0x%02X RXDFE:0x%02X RF24 TXDFE:0x%02X RXDFE:0x%02X", + g_mon.rf09_txdfe, g_mon.rf09_rxdfe, g_mon.rf24_txdfe, g_mon.rf24_rxdfe); + mvprintw(10, 0, "RF09 STATE:0x%02X IRQM:0x%02X IRQS:0x%02X PAC:0x%02X PADFE:0x%02X", + g_mon.rf09_state, g_mon.rf09_irqm, g_mon.rf09_irqs, g_mon.rf09_pac, g_mon.rf09_padfe); + mvprintw(11, 0, "RF24 STATE:0x%02X IRQM:0x%02X IRQS:0x%02X PAC:0x%02X PADFE:0x%02X", + g_mon.rf24_state, g_mon.rf24_irqm, g_mon.rf24_irqs, g_mon.rf24_pac, g_mon.rf24_padfe); + + mvprintw(13, 0, "RFFE: debug=%u mode=%s", g_mon.rffe_debug, caribou_fpga_get_mode_name(g_mon.rffe_mode)); + + mvprintw(15, 0, "Last TX sample: I=0x%04X Q=0x%04X Last RX sample: I=0x%04X Q=0x%04X", + (uint16_t)(atomic_load(&g_last_tx_i) & 0xFFFF), (uint16_t)(atomic_load(&g_last_tx_q) & 0xFFFF), + (uint16_t)(atomic_load(&g_last_rx_i) & 0xFFFF), (uint16_t)(atomic_load(&g_last_rx_q) & 0xFFFF)); + + refresh(); +} + +static void program_fpga(app_ctx_t *ctx, const char *fw) +{ + // stop streaming during reprogram + atomic_store(&g_tx_want, false); + atomic_store(&g_rx_want, false); + // brief wait for threads to quiesce + for (int i = 0; i < 50 && (atomic_load(&g_tx_running) || atomic_load(&g_rx_running)); ++i) usleep(1000); + + + // Hard reset first + caribou_fpga_hard_reset(ctx->fpga); + + // Tell the library we want to (re)program now + ctx->sys->force_fpga_reprogramming = true; + + // Configure from file path `fw` + int r = cariboulite_configure_fpga(ctx->sys, cariboulite_firmware_source_file, fw); + if (r < 0) { + mvprintw(17, 0, "FPGA programming failed (%d)\n", r); + return; + } + + mvprintw(17, 0, "FPGA programmed from '%s'\n", fw); + + // Soft reset + brief settle, then read versions + caribou_fpga_soft_reset(ctx->fpga); + io_utils_usleep(100000); + caribou_fpga_get_versions(ctx->fpga, NULL); +} + +int main(int argc, char **argv) +{ + const char *fw_path = (argc > 1) ? argv[1] : SOURCE; + + app_ctx_t ctx; + memset(&ctx, 0, sizeof(ctx)); + + // ---- Bringup (test-app style, robust) ---- + // Use the same global singleton the test app uses. + extern sys_st cariboulite_sys; // declared by CARIBOULITE_CONFIG_DEFAULT + // Make sure the default config symbol exists in one TU: + // CARIBOULITE_CONFIG_DEFAULT(cariboulite_sys); // put this at top of THIS file if not elsewhere + + // Init the driver (not the lightweight lib init) + cariboulite_sys.force_fpga_reprogramming = 0; + if (cariboulite_init_driver(&cariboulite_sys, NULL) != 0) { + fprintf(stderr, "cariboulite_init_driver failed\n"); + return 1; + } + + // Wire our ctx to the SAME objects the driver mode sets up + ctx.sys = &cariboulite_sys; + ctx.radio = &ctx.sys->radio_low; // (or radio_high if you prefer HiF) + ctx.modem = &ctx.sys->modem; + ctx.fpga = &ctx.sys->fpga; + ctx.smi = &ctx.sys->smi; + if (!ctx.sys || !ctx.fpga || !ctx.modem || !ctx.smi || !ctx.radio) { + fprintf(stderr, "internal pointers are NULL after driver init\n"); + cariboulite_release_driver(&cariboulite_sys); + return 1; + } + + // Use the driver’s signal handler pattern OR keep yours — your handler is fine. + if (install_app_signal_handlers() != 0) { + perror("sigaction"); + cariboulite_release_driver(&cariboulite_sys); + return 1; + } + + + // Prepare TX ring and tone + g_tx_ring = (cariboulite_sample_complex_int16*)malloc(sizeof(*g_tx_ring) * RING_SAMPLES); + if (!g_tx_ring) { fprintf(stderr, "malloc g_tx_ring failed\n"); return 1; } + fill_tx_ring_tone(APP_SAMPLE_RATE); + + + // ---- UI ---- + initscr(); cbreak(); noecho(); nodelay(stdscr, TRUE); + + // One-time show versions + mvprintw(0, 0, "Board & library versions\n"); + cariboulite_print_board_info(ctx.sys, false); + caribou_fpga_get_versions(ctx.fpga, NULL); + cariboulite_lib_version_st v={0}; cariboulite_lib_version(&v); + mvprintw(1, 0, "Lib ver: %d.%d.%d\n", v.major_version, v.minor_version, v.revision); + refresh(); + napms(800); + + // Threads + pthread_t th_mon, th_rx, th_tx; + pthread_create(&th_mon, NULL, monitor_thread, &ctx); + pthread_create(&th_rx, NULL, rx_thread, &ctx); + pthread_create(&th_tx, NULL, tx_thread, &ctx); + + bool need_redraw = true; + while (atomic_load(&g_run)) { + int ch = getch(); + if (ch != ERR) { + switch (ch) { + case 'q': case 'Q': + atomic_store(&g_tx_want, false); + atomic_store(&g_rx_want, false); + force_radio_idle(&ctx); + atomic_store(&g_run, false); + break; + case 'h': case 'H': + atomic_store(&g_tx_want, false); + atomic_store(&g_rx_want, false); + for (int i = 0; i < 50 && (atomic_load(&g_tx_running) || atomic_load(&g_rx_running)); ++i) usleep(1000); + caribou_fpga_hard_reset(ctx.fpga); + need_redraw = true; + break; + case 's': case 'S': + atomic_store(&g_tx_want, false); + atomic_store(&g_rx_want, false); + for (int i = 0; i < 50 && (atomic_load(&g_tx_running) || atomic_load(&g_rx_running)); ++i) usleep(1000); + caribou_fpga_soft_reset(ctx.fpga); + need_redraw = true; + break; + case 'p': case 'P': program_fpga(&ctx, fw_path); need_redraw = true; break; + case 't': case 'T': atomic_store(&g_tx_want, !atomic_load(&g_tx_want)); break; + case 'r': case 'R': atomic_store(&g_rx_want, !atomic_load(&g_rx_want)); break; + default: break; + } + } + if (need_redraw || ch != ERR) { + draw_ui(&ctx); + need_redraw = false; + } + napms(50); // UI pacing; TX/RX run independently at RT priority + } + + // ---- Shutdown ---- + atomic_store(&g_tx_want, false); + atomic_store(&g_rx_want, false); + force_radio_idle(&ctx); + usleep(10*1000); // give HW/driver a moment + pthread_join(th_tx, NULL); + pthread_join(th_rx, NULL); + pthread_join(th_mon, NULL); + + endwin(); + free(g_tx_ring); + + cariboulite_release_driver(&cariboulite_sys); + + return 0; +} diff --git a/software/libcariboulite/src/caribou_fpga/caribou_fpga.c b/software/libcariboulite/src/caribou_fpga/caribou_fpga.c index 45a52f61..da4f74d2 100644 --- a/software/libcariboulite/src/caribou_fpga/caribou_fpga.c +++ b/software/libcariboulite/src/caribou_fpga/caribou_fpga.c @@ -213,7 +213,7 @@ int caribou_fpga_program_to_fpga(caribou_fpga_st* dev, unsigned char *buffer, si } //-------------------------------------------------------------- -int caribou_fpga_program_to_fpga_from_file(caribou_fpga_st* dev, char *filename, bool force_prog) +int caribou_fpga_program_to_fpga_from_file(caribou_fpga_st* dev, const char *filename, bool force_prog) { caribou_fpga_get_status(dev, NULL); if (dev->status == caribou_fpga_status_not_programmed || force_prog) @@ -346,7 +346,7 @@ static char caribou_fpga_mode_names[][64] = "RX lowpass (up-conversion) (2)", "RX hipass (down-conversion) (3)", "TX lowpass (down-conversion) (4)", - "RX hipass (up-conversion) (5)", + "TX hipass (up-conversion) (5)", }; char* caribou_fpga_get_mode_name (caribou_fpga_io_ctrl_rfm_en mode) @@ -457,7 +457,11 @@ int caribou_fpga_set_sys_ctrl_sync_source (caribou_fpga_st* dev, caribou_fpga_sy .ioc = IOC_SYS_CTRL_TX_SAMPLE_GAP, }; int ret = caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &actual_val); - if (ret != 0) return -1; + if (ret != 0) + { + ZF_LOGE("Failed to read IOC_SYS_CTRL_TX_SAMPLE_GAP"); + return -1; + } temp = actual_val & 0xF; uint8_t cur_rx_09 = (actual_val >> 4) & 0x1; @@ -476,6 +480,7 @@ int caribou_fpga_set_sys_ctrl_sync_source (caribou_fpga_st* dev, caribou_fpga_sy temp |= cur_tx_24 << 7; oc.rw = caribou_fpga_rw_write; + ZF_LOGI("Writing IOC_SYS_CTRL_TX_SAMPLE_GAP: 0x%02X\n", temp); return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &temp); } @@ -538,7 +543,7 @@ int caribou_fpga_set_io_ctrl_mode (caribou_fpga_st* dev, uint8_t debug_mode, car .ioc = IOC_IO_CTRL_MODE }; - uint8_t mode = (debug_mode << 0) | (rfm&0x7)<<2; + uint8_t mode = ((debug_mode&0x3) << 0) | (rfm&0x7)<<2; return caribou_fpga_spi_transfer (dev, (uint8_t*)(&oc), &mode); } diff --git a/software/libcariboulite/src/caribou_fpga/caribou_fpga.h b/software/libcariboulite/src/caribou_fpga/caribou_fpga.h index 94d46381..93f3a4fe 100644 --- a/software/libcariboulite/src/caribou_fpga/caribou_fpga.h +++ b/software/libcariboulite/src/caribou_fpga/caribou_fpga.h @@ -85,8 +85,9 @@ typedef struct uint8_t rx_fifo_empty : 1; // LSB uint8_t tx_fifo_full : 1; uint8_t smi_channel: 1; - uint8_t i_smi_test : 1; - uint8_t reserved : 4; // MSB + uint8_t i_smi_test : 1; // always zero + uint8_t smi_direction : 1; + uint8_t reserved : 3; // MSB } caribou_fpga_smi_fifo_status_st; /** @@ -94,10 +95,19 @@ typedef struct */ typedef enum { - caribou_fpga_smi_channel_0 = 0, - caribou_fpga_smi_channel_1 = 1, + caribou_fpga_smi_channel_0 = 0, // RX09 + caribou_fpga_smi_channel_1 = 1, // RX24 } caribou_fpga_smi_channel_en; +/** + * @brief SMI direction select + */ +typedef enum +{ + caribou_fpga_smi_direction_0 = 0, // TX + caribou_fpga_smi_direction_1 = 1, // RX +} caribou_fpga_smi_direction_en; + /** * @brief Syncronization bit (metadata) source. Either software * setting using "caribou_fpga_set_sys_ctrl_soft_sync_value" @@ -156,7 +166,7 @@ int caribou_fpga_hard_reset_keep(caribou_fpga_st* dev, bool reset); // programming int caribou_fpga_get_status(caribou_fpga_st* dev, caribou_fpga_status_en *stat); int caribou_fpga_program_to_fpga(caribou_fpga_st* dev, unsigned char *buffer, size_t len, bool force_prog); -int caribou_fpga_program_to_fpga_from_file(caribou_fpga_st* dev, char *filename, bool force_prog); +int caribou_fpga_program_to_fpga_from_file(caribou_fpga_st* dev, const char *filename, bool force_prog); // System Controller int caribou_fpga_get_versions (caribou_fpga_st* dev, caribou_fpga_versions_st *vers); diff --git a/software/libcariboulite/src/caribou_programming/caribou_prog.c b/software/libcariboulite/src/caribou_programming/caribou_prog.c index ae150244..4fdbae83 100644 --- a/software/libcariboulite/src/caribou_programming/caribou_prog.c +++ b/software/libcariboulite/src/caribou_programming/caribou_prog.c @@ -303,7 +303,7 @@ int caribou_prog_configure_from_buffer( caribou_prog_st *dev, * @param bitfilename path to the file containing the fpga bitstream * @return int success(0), error (-1) */ -int caribou_prog_configure(caribou_prog_st *dev, char *bitfilename) +int caribou_prog_configure(caribou_prog_st *dev, const char *bitfilename) { FILE *fd = NULL; int ct = 0; diff --git a/software/libcariboulite/src/caribou_programming/caribou_prog.h b/software/libcariboulite/src/caribou_programming/caribou_prog.h index 0835dcfd..b7dcd8c0 100644 --- a/software/libcariboulite/src/caribou_programming/caribou_prog.h +++ b/software/libcariboulite/src/caribou_programming/caribou_prog.h @@ -28,7 +28,7 @@ typedef struct int caribou_prog_init(caribou_prog_st *dev, io_utils_spi_st* io_spi); int caribou_prog_release(caribou_prog_st *dev); -int caribou_prog_configure(caribou_prog_st *dev, char *bitfilename); +int caribou_prog_configure(caribou_prog_st *dev, const char *bitfilename); int caribou_prog_configure_from_buffer( caribou_prog_st *dev, uint8_t *buffer, uint32_t buffer_size); diff --git a/software/libcariboulite/src/caribou_smi/caribou_smi.c b/software/libcariboulite/src/caribou_smi/caribou_smi.c index 72408326..dcdb628a 100644 --- a/software/libcariboulite/src/caribou_smi/caribou_smi.c +++ b/software/libcariboulite/src/caribou_smi/caribou_smi.c @@ -5,7 +5,9 @@ #define ZF_LOG_TAG "CARIBOU_SMI" #include "zf_log/zf_log.h" -#define _GNU_SOURCE +// #ifndef _GNU_SOURCE +// #define _GNU_SOURCE +// #endif #include #include @@ -17,6 +19,7 @@ #include #include #include +#include // for mlockall, MCL_CURRENT, MCL_FUTURE #include #include #include @@ -25,18 +28,54 @@ #include "caribou_smi.h" #include "smi_utils.h" #include "io_utils/io_utils.h" +#include +#include +#include + +#ifndef CARIBOU_SMI_BYTES_PER_SAMPLE + #define CARIBOU_SMI_BYTES_PER_SAMPLE (sizeof(caribou_smi_sample_complex_int16)) +#endif + //========================================================================= +// int caribou_smi_set_driver_streaming_state(caribou_smi_st* dev, smi_stream_state_en state) +// { +// int ret = ioctl(dev->filedesc, SMI_STREAM_IOC_SET_STREAM_STATUS, state); +// if (ret != 0) +// { +// ZF_LOGE("failed setting smi stream state (%d)", state); +// return -1; +// } +// dev->state = state; +// return 0; +// } + +/* --- TX leftover accumulator (shared between write/start/stop) --- */ +static caribou_smi_sample_complex_int16 g_tx_accum[16384]; +static size_t g_tx_accum_n = 0; + +static inline void caribou_smi_tx_accum_reset(void) +{ + g_tx_accum_n = 0; +} + int caribou_smi_set_driver_streaming_state(caribou_smi_st* dev, smi_stream_state_en state) { - int ret = ioctl(dev->filedesc, SMI_STREAM_IOC_SET_STREAM_STATUS, state); - if (ret != 0) - { - ZF_LOGE("failed setting smi stream state (%d)", state); - return -1; + static pthread_mutex_t mtx = PTHREAD_MUTEX_INITIALIZER; + static smi_stream_state_en last = smi_stream_idle; + + pthread_mutex_lock(&mtx); + if (state == last) { + pthread_mutex_unlock(&mtx); + return 0; // no-op: desired == current (cached) } - dev->state = state; - return 0; + + int r = ioctl(dev->filedesc, SMI_STREAM_IOC_SET_STREAM_STATUS, state); + if (r == 0) { + last = state; // update only on success + } + pthread_mutex_unlock(&mtx); + return r; } //========================================================================= @@ -45,6 +84,43 @@ smi_stream_state_en caribou_smi_get_driver_streaming_state(caribou_smi_st* dev) return dev->state; } + +//========================================================================= +/* --- helpers for “exact quarter” writes and priming ---*/ +static void caribou_smi_boost_sched(void) +{ +#ifdef MCL_CURRENT + // lock current+future pages in RAM + (void)mlockall(MCL_CURRENT | MCL_FUTURE); +#endif + + // switch to SCHED_FIFO if permitted + struct sched_param sp = { .sched_priority = 50 }; + (void)sched_setscheduler(0, SCHED_FIFO, &sp); +} + +static inline size_t smi_quarter_bytes(const caribou_smi_st *dev) +{ + return (size_t)(dev->native_batch_len / 4); +} + +/* Block until exactly 'len' bytes are written (handles EINTR/EAGAIN). */ +static int write_all(int fd, const uint8_t *buf, size_t len) +{ + size_t off = 0; + while (off < len) { + ssize_t r = write(fd, buf + off, len - off); + if (r > 0) { off += (size_t)r; continue; } + if (r < 0 && errno == EINTR) continue; + if (r < 0 && (errno == EAGAIN || errno == EWOULDBLOCK)) { + (void)poll(&(struct pollfd){ .fd = fd, .events = POLLOUT }, 1, 1); + continue; + } + return -1; // real error + } + return 0; +} + //========================================================================= static void caribou_smi_print_smi_settings(caribou_smi_st* dev, struct smi_settings *settings) { @@ -56,7 +132,7 @@ static void caribou_smi_print_smi_settings(caribou_smi_st* dev, struct smi_setti printf(" dma enable: %c, passthru enable: %c\n", settings->dma_enable ? 'Y':'N', settings->dma_passthrough_enable ? 'Y':'N'); printf(" dma threshold read: %d, write: %d\n", settings->dma_read_thresh, settings->dma_write_thresh); printf(" dma panic threshold read: %d, write: %d\n", settings->dma_panic_read_thresh, settings->dma_panic_write_thresh); - printf(" native kernel chunk size: %d bytes\n", dev->native_batch_len); + printf(" native kernel chunk size: %ld bytes\n", dev->native_batch_len); } //========================================================================= @@ -90,14 +166,14 @@ static int caribou_smi_get_smi_settings(caribou_smi_st *dev, struct smi_settings //========================================================================= static int caribou_smi_setup_settings (caribou_smi_st* dev, struct smi_settings *settings, bool print) { - settings->read_setup_time = 0; - settings->read_strobe_time = 5; - settings->read_hold_time = 0; + settings->read_setup_time = 1; + settings->read_strobe_time = 3; // orginal value: 5 + settings->read_hold_time = 1; settings->read_pace_time = 0; - settings->write_setup_time = 0; - settings->write_strobe_time = 5; - settings->write_hold_time = 0; + settings->write_setup_time = 1; + settings->write_strobe_time = 3; // orginal value: 5 + settings->write_hold_time = 1; settings->write_pace_time = 0; // 8 bit on each transmission (4 TRX per sample) @@ -110,7 +186,7 @@ static int caribou_smi_setup_settings (caribou_smi_st* dev, struct smi_settings settings->pack_data = 1; // External DREQs enabled - settings->dma_passthrough_enable = 1; + settings->dma_passthrough_enable = 1; // orginal: 1 // RX DREQ Threshold Level. // A RX DREQ will be generated when the RX FIFO exceeds this threshold level. @@ -118,13 +194,13 @@ static int caribou_smi_setup_settings (caribou_smi_st* dev, struct smi_settings // If the DMA is set to perform burst reads, the threshold must ensure that there is // sufficient data in the FIFO to satisfy the burst // Instruction: Lower is faster response - settings->dma_read_thresh = 1; + settings->dma_read_thresh = 1; // 0 - 511 range (9 bit) // TX DREQ Threshold Level. // A TX DREQ will be generated when the TX FIFO drops below this threshold level. // This will instruct an external AXI TX DMA to write more data to the TX FIFO. // Instruction: Higher is faster response - settings->dma_write_thresh = 254; + settings->dma_write_thresh = 254; //381; // orginal: 254 // RX Panic Threshold level. // A RX Panic will be generated when the RX FIFO exceeds this threshold level. @@ -136,7 +212,7 @@ static int caribou_smi_setup_settings (caribou_smi_st* dev, struct smi_settings // A TX Panic will be generated when the TX FIFO drops below this threshold level. // This will instruct the AXI TX DMA to increase the priority of its bus requests. // Instruction: Higher is more aggresive - settings->dma_panic_write_thresh = 224; + settings->dma_panic_write_thresh = 495; // 397; // orginal: 224 if (print) { @@ -440,26 +516,65 @@ static int caribou_smi_poll(caribou_smi_st* dev, uint32_t timeout_num_millisec, return fds.revents & POLLIN || fds.revents & POLLOUT; } -//========================================================================= +//==old======================================================================= +// static int caribou_smi_timeout_write(caribou_smi_st* dev, +// uint8_t* buffer, +// size_t len, +// uint32_t timeout_num_millisec) +// { +// int res = caribou_smi_poll(dev, timeout_num_millisec, smi_stream_dir_smi_to_device); + +// if (res < 0) +// { +// ZF_LOGD("poll error"); +// return -1; +// } +// else if (res == 0) // timeout +// { +// ZF_LOGD("===> smi write fd timeout"); +// return 0; +// } + +// return write(dev->filedesc, buffer, len); +// } + +//==new======================================================================= static int caribou_smi_timeout_write(caribou_smi_st* dev, - uint8_t* buffer, - size_t len, - uint32_t timeout_num_millisec) + uint8_t* buffer, + size_t len, + uint32_t timeout_ms) { - int res = caribou_smi_poll(dev, timeout_num_millisec, smi_stream_dir_smi_to_device); + uint8_t *p = buffer; + size_t left = len; + int wrote_total = 0; + + while (left > 0) { + ssize_t r = write(dev->filedesc, p, left); + if (r > 0) { + p += r; + left -= (size_t)r; + wrote_total += (int)r; + continue; + } + if (r < 0) { + if (errno == EINTR) continue; // retry immediately + if (errno == EAGAIN || errno == EWOULDBLOCK) { + // wait for POLLOUT briefly + int ready = caribou_smi_poll(dev, timeout_ms, smi_stream_dir_smi_to_device); + if (ready > 0) continue; // try write again + // timeout or poll error → return what we have so far + return wrote_total; + } + // other error + return (wrote_total > 0) ? wrote_total : -1; + } - if (res < 0) - { - ZF_LOGD("poll error"); - return -1; - } - else if (res == 0) // timeout - { - //ZF_LOGD("===> smi write fd timeout"); - return 0; + // r == 0 should not happen for a blocking char device; treat as “not ready” + int ready = caribou_smi_poll(dev, timeout_ms, smi_stream_dir_smi_to_device); + if (ready <= 0) return wrote_total; // timeout or error: partial is fine } - return write(dev->filedesc, buffer, len); + return wrote_total; } //========================================================================= @@ -540,6 +655,7 @@ int caribou_smi_init(caribou_smi_st* dev, return -1; } dev->filedesc = fd; + caribou_smi_boost_sched(); // optional: reduces micro-stalls // Setup the bus I/Os // -------------------------------------------- @@ -684,10 +800,18 @@ int caribou_smi_read(caribou_smi_st* dev, caribou_smi_channel_en channel, #define SMI_TX_SAMPLE_SOF (1<<2) #define SMI_TX_SAMPLE_MODEM_TX_CTRL (1<<1) #define SMI_TX_SAMPLE_COND_TX_CTRL (1<<0) +//======helper function==================================================== +void print_binairy32(uint32_t value) { + for (int i = 31; i >= 0; --i) { + putchar((value & (1 << i)) ? '1' : '0'); + if (i % 8 == 0 && i != 0) putchar(' '); + } + putchar('\n'); +} //========================================================================= -static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t data_length, caribou_smi_sample_complex_int16* sample_offset) +static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t data_length, const caribou_smi_sample_complex_int16* sample_offset) { - caribou_smi_sample_complex_int16* cmplx_vec = sample_offset; + const caribou_smi_sample_complex_int16* cmplx_vec = sample_offset; uint32_t *samples = (uint32_t*)(data); // Sample Structure @@ -697,8 +821,8 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t for (unsigned int i = 0; i < (data_length / CARIBOU_SMI_BYTES_PER_SAMPLE); i++) { - int32_t ii = 0xFFFF; //cmplx_vec[i].i; - int32_t qq = 0; //cmplx_vec[i].q; + int32_t ii = cmplx_vec[i].i; + int32_t qq = cmplx_vec[i].q; ii &= 0x1FFF; qq &= 0x1FFF; @@ -708,59 +832,301 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t s |= (ii & 0x1); s <<= 6; s |= (qq >> 7) & 0x3F; s <<= 8; s |= (qq & 0x7F); + //s = 0x80000000; // we need only one bit to be correct... - //if (i < 2) printf("0x%08X\n", s); - - samples[i] = __builtin_bswap32(s); - //samples[i] = s; + //if (i < 2) + //{ + // printf("0x%08X ", s); + // print_binairy32(s); + //} + + //samples[i] = __builtin_bswap32(s); + samples[i] = s; // like this we have 0 missed 'programmed write'. } } -//========================================================================= +//==old====================================================================== +// int caribou_smi_write(caribou_smi_st* dev, caribou_smi_channel_en channel, +// caribou_smi_sample_complex_int16* samples, size_t length_samples) +// { +// size_t left_to_write = length_samples * CARIBOU_SMI_BYTES_PER_SAMPLE; // in bytes +// size_t written_so_far = 0; // in samples +// //uint32_t to_millisec = (2 * length_samples * 1000) / CARIBOU_SMI_SAMPLE_RATE; +// uint32_t to_millisec = (2 * length_samples * 1000) / dev->sample_rate; +// if (to_millisec < 2) to_millisec = 2; + +// smi_stream_state_en state = smi_stream_tx_channel; + +// // apply the state +// // if (caribou_smi_set_driver_streaming_state(dev, state) != 0) +// // { +// // printf("caribou_smi_set_driver_streaming_state -> Failed\n"); +// // return -1; +// // } + +// while (left_to_write) +// { +// // prepare the buffer +// caribou_smi_sample_complex_int16* sample_offset = samples + written_so_far; +// size_t current_write_len = (left_to_write > dev->native_batch_len) ? dev->native_batch_len : left_to_write; + +// // make sure the written bytes length is a whole sample multiplication +// // if the number of remaining bytes is smaller than sample size -> finish; +// current_write_len &= 0xFFFFFFFC; +// if (!current_write_len) break; + +// caribou_smi_generate_data(dev, dev->write_temp_buffer, current_write_len, sample_offset); + +// int ret = caribou_smi_timeout_write(dev, dev->write_temp_buffer, current_write_len, to_millisec); +// if (ret < 0) +// { +// return -1; +// } +// else if (ret == 0) break; + +// left_to_write -= (size_t)ret; // subtract *actual* bytes written +// written_so_far += (size_t)ret / CARIBOU_SMI_BYTES_PER_SAMPLE; +// } + +// return written_so_far; +// } + +//==new==================================================================== int caribou_smi_write(caribou_smi_st* dev, caribou_smi_channel_en channel, - caribou_smi_sample_complex_int16* samples, size_t length_samples) + caribou_smi_sample_complex_int16* samples, size_t length_samples) { - size_t left_to_write = length_samples * CARIBOU_SMI_BYTES_PER_SAMPLE; // in bytes - size_t written_so_far = 0; // in samples - uint32_t to_millisec = (2 * length_samples * 1000) / CARIBOU_SMI_SAMPLE_RATE; - if (to_millisec < 2) to_millisec = 2; + const size_t q_bytes = smi_quarter_bytes(dev); // exact DMA period (bytes) + const size_t bytes_total = length_samples * CARIBOU_SMI_BYTES_PER_SAMPLE; - smi_stream_state_en state = smi_stream_tx_channel; + // We only transmit whole quarters; keep a static “last” IQ for padding tails + static caribou_smi_sample_complex_int16 last = {0, 0}; - // apply the state - if (caribou_smi_set_driver_streaming_state(dev, state) != 0) - { - printf("caribou_smi_set_driver_streaming_state -> Failed\n"); - return -1; + size_t bytes_left = bytes_total; + size_t wrote_samps = 0; + + // 1) Send as many *full* quarters as we can + while (bytes_left >= q_bytes) { + // Pack exactly one quarter into write_temp_buffer + const size_t this_samp = q_bytes / CARIBOU_SMI_BYTES_PER_SAMPLE; + caribou_smi_generate_data(dev, dev->write_temp_buffer, q_bytes, samples + wrote_samps); + + // Blocking write of the whole quarter + if (write_all(dev->filedesc, (uint8_t*)dev->write_temp_buffer, q_bytes) != 0) + return (int)wrote_samps; // short on error (never return a partial quarter) + + // Track the last IQ we sent (for tail padding later) + last = samples[wrote_samps + this_samp - 1]; + + wrote_samps += this_samp; + bytes_left -= q_bytes; } - while (left_to_write) - { - // prepare the buffer - caribou_smi_sample_complex_int16* sample_offset = samples + written_so_far; - size_t current_write_len = (left_to_write > dev->native_batch_len) ? dev->native_batch_len : left_to_write; - - // make sure the written bytes length is a whole sample multiplication - // if the number of remaining bytes is smaller than sample size -> finish; - current_write_len &= 0xFFFFFFFC; - if (!current_write_len) break; + // 2) Handle tail < one quarter: pad with the last sample to complete a clean quarter + if (bytes_left > 0) { + const size_t this_samp = q_bytes / CARIBOU_SMI_BYTES_PER_SAMPLE; + + // Build a temporary quarter of IQ: the real tail first, then pad with 'last' + // We reuse write_temp_buffer as a staging area. + // Step A: copy real tail + const size_t tail_samp = bytes_left / CARIBOU_SMI_BYTES_PER_SAMPLE; + if (tail_samp) { + caribou_smi_generate_data(dev, dev->write_temp_buffer, + tail_samp * CARIBOU_SMI_BYTES_PER_SAMPLE, + samples + wrote_samps); + last = samples[wrote_samps + tail_samp - 1]; + } - caribou_smi_generate_data(dev, dev->write_temp_buffer, current_write_len, sample_offset); + // Step B: synthesize padding samples = 'last' + if (tail_samp < this_samp) { + // Create a tiny view of identical samples for padding + caribou_smi_sample_complex_int16 pad = last; + // We can re-use the same last sample repeatedly: + size_t pad_samp = this_samp - tail_samp; + // Lay the pad samples into a small local stack array in chunks + // to avoid big allocations; 64 is enough since we only need to + // generate data into the *remaining* bytes of the quarter. + caribou_smi_sample_complex_int16 chunk[64]; + size_t produced = 0; + size_t dst_off_bytes = tail_samp * CARIBOU_SMI_BYTES_PER_SAMPLE; + + while (produced < pad_samp) { + size_t n = (pad_samp - produced) < 64 ? (pad_samp - produced) : 64; + for (size_t i = 0; i < n; i++) chunk[i] = pad; + + caribou_smi_generate_data(dev, + ((uint8_t*)dev->write_temp_buffer) + dst_off_bytes, + n * CARIBOU_SMI_BYTES_PER_SAMPLE, + chunk); + produced += n; + dst_off_bytes += n * CARIBOU_SMI_BYTES_PER_SAMPLE; + } + } - int ret = caribou_smi_timeout_write(dev, dev->write_temp_buffer, current_write_len, to_millisec); - if (ret < 0) - { - return -1; + // Write the completed quarter + if (write_all(dev->filedesc, (uint8_t*)dev->write_temp_buffer, q_bytes) != 0) + return (int)wrote_samps; + + wrote_samps += this_samp; // we advanced one full quarter worth of samples + bytes_left = 0; + } + + return (int)wrote_samps; +} + +// int caribou_smi_write_samples(caribou_smi_st *dev, +// caribou_smi_channel_en ch, +// const caribou_smi_sample_complex_int16 *samples, +// int n_samples) +// { +// (void)ch; // channel via driver state + +// if (!dev || dev->filedesc < 0 || !samples || n_samples <= 0) +// return -EINVAL; + +// const size_t bps = (size_t)CARIBOU_SMI_BYTES_PER_SAMPLE; +// const size_t total_bytes = (size_t)n_samples * bps; + +// size_t bytes_left = total_bytes; +// size_t consumed_samples = 0; + +// // Use a small write timeout; driver/DMA will pull as ready. +// const uint32_t to_ms = 5; + +// while (bytes_left) { +// // write at most native chunk; keep it whole-sample aligned +// size_t cur = (bytes_left > dev->native_batch_len) ? dev->native_batch_len : bytes_left; +// cur &= ~(bps - 1); // round down to whole sample +// if (!cur) break; + +// // Pack caller’s samples for this chunk into write_temp_buffer +// size_t cur_samp = cur / bps; +// caribou_smi_generate_data(dev, +// (uint8_t*)dev->write_temp_buffer, +// cur, +// (caribou_smi_sample_complex_int16*)(samples + consumed_samples)); + +// // Write (may be partial); returns bytes actually written +// int w = caribou_smi_timeout_write(dev, +// (uint8_t*)dev->write_temp_buffer, +// cur, +// to_ms); +// if (w < 0) { +// // hard error +// return (consumed_samples > 0) ? (int)consumed_samples : w; +// } +// if (w == 0) { +// // timed out this round; report what we consumed so far +// break; +// } + +// // Convert bytes written back to samples *we can advance the source by* +// size_t w_whole = (size_t)w & ~(bps - 1); +// size_t w_samp = w_whole / bps; + +// consumed_samples += w_samp; +// bytes_left -= w_whole; + +// if (w_whole < cur) { +// // short write; let caller feed again later +// break; +// } +// } + +// return (int)consumed_samples; +// } + +int caribou_smi_write_samples(caribou_smi_st *dev, + caribou_smi_channel_en ch, + const caribou_smi_sample_complex_int16 *samples, + int n_samples) +{ + (void)ch; + + if (!dev || dev->filedesc < 0 || !samples || n_samples <= 0) + return -EINVAL; + + const size_t bps = (size_t)CARIBOU_SMI_BYTES_PER_SAMPLE; + const size_t total_bytes = (size_t)n_samples * bps; + + size_t bytes_left = total_bytes; + size_t consumed_samples = 0; + + // Give the kernel/DMA a bit more breathing room per attempt. + const uint32_t per_try_timeout_ms = 25; + + while (bytes_left) { + // Choose a modest chunk to smooth out scheduling jitter. + size_t cur = bytes_left; + if (cur > dev->native_batch_len) cur = dev->native_batch_len; + + // round down to whole sample + cur &= ~(bps - 1); + if (!cur) break; + + // Generate payload for this chunk + size_t cur_samp = cur / bps; + caribou_smi_generate_data(dev, + (uint8_t*)dev->write_temp_buffer, + cur, + (const caribou_smi_sample_complex_int16*)(samples + consumed_samples)); + + // Try to push the entire chunk, tolerate partial/timeouts inside this loop + size_t off = 0; + int attempts = 0; + + while (off < cur) { + int w = caribou_smi_timeout_write(dev, + (uint8_t*)dev->write_temp_buffer + off, + (int)(cur - off), + per_try_timeout_ms); + if (w < 0) { + // hard error: return what we did manage to consume so far (in samples) or the error if nothing + return (consumed_samples > 0) ? (int)consumed_samples : w; + } + if (w == 0) { + // just a timeout; allow a few retries before giving up this call + if (++attempts >= 4) { + // return what we've advanced so far; caller can call us again immediately + goto done; + } + continue; // retry same offset + } + + // advance by whole samples only + size_t w_whole = (size_t)w & ~(bps - 1); + off += w_whole; + + // reset attempts after forward progress + attempts = 0; + + // If the driver ever gave us a non-sample-aligned write (shouldn't happen), + // discard the tail bytes from this chunk to preserve alignment. + if ((size_t)w != w_whole) { + break; // finish this chunk; we'll regenerate cleanly next call + } } - else if (ret == 0) break; - written_so_far += current_write_len / CARIBOU_SMI_BYTES_PER_SAMPLE; - left_to_write -= ret; + // We successfully pushed 'off' bytes (sample-aligned) + size_t pushed_samp = off / bps; + consumed_samples += pushed_samp; + bytes_left -= off; + + // If we didn't finish the chunk (e.g., non-aligned w), fall out to return early. + if (off < cur) break; } - return written_so_far; +done: + return (int)consumed_samples; } +// Optionally keep the older name as a thin wrapper: +// int caribou_smi_write(caribou_smi_st* dev, caribou_smi_channel_en ch, +// caribou_smi_sample_complex_int16* samples, size_t length_samples) +// { +// int n = (int)length_samples; +// return caribou_smi_write_samples(dev, ch, samples, n); +// } + //========================================================================= size_t caribou_smi_get_native_batch_samples(caribou_smi_st* dev) { @@ -780,4 +1146,55 @@ int caribou_smi_flush_fifo(caribou_smi_st* dev) return -1; } return 0; +} + +int caribou_smi_start_tx(caribou_smi_st *dev) +{ + if (!dev) return -EINVAL; + if (dev->state == smi_stream_tx_channel) return 0; + + // 1) Arm TX in the kernel FIRST + if (caribou_smi_set_driver_streaming_state(dev, smi_stream_tx_channel) != 0) + return -1; + dev->state = smi_stream_tx_channel; + + // 2) Prefill a few chunks of steady zeros using the SAME writer + const size_t bps = (size_t)CARIBOU_SMI_BYTES_PER_SAMPLE; + const size_t q_bytes = (size_t)(dev->native_batch_len / 4); + const size_t q_samp = q_bytes / bps; + + caribou_smi_sample_complex_int16 zero = {0, 0}; + + // Build one zero quarter in write_temp_buffer + for (size_t i = 0; i < q_samp; ++i) { + ((caribou_smi_sample_complex_int16*)dev->write_temp_buffer)[i] = zero; + } + // Pack it to device format + caribou_smi_generate_data(dev, (uint8_t*)dev->write_temp_buffer, q_bytes, + (caribou_smi_sample_complex_int16*)dev->write_temp_buffer); + + // Push a few quarters (non-blocking, allow partials/timeouts) + for (int i = 0; i < 8; ++i) { + int w = caribou_smi_timeout_write(dev, + (uint8_t*)dev->write_temp_buffer, + q_bytes, + 5); + if (w <= 0) break; // fine; DMA will pull as it goes + } + + return 0; +} + +int caribou_smi_stop(caribou_smi_st *dev) { + + if (!dev) return -EINVAL; + + /* Drop any partial block so next TX starts clean */ + //caribou_smi_tx_accum_reset(); + + if (dev->state == smi_stream_idle) return 0; + if (caribou_smi_set_driver_streaming_state(dev, smi_stream_idle) != 0) return -1; + + dev->state = smi_stream_idle; + return 0; } \ No newline at end of file diff --git a/software/libcariboulite/src/caribou_smi/caribou_smi.h b/software/libcariboulite/src/caribou_smi/caribou_smi.h index 72456b75..46b736bd 100644 --- a/software/libcariboulite/src/caribou_smi/caribou_smi.h +++ b/software/libcariboulite/src/caribou_smi/caribou_smi.h @@ -54,8 +54,8 @@ typedef enum // associated with CS16 - total 4 bytes / element typedef struct { - int16_t i; // LSB - int16_t q; // MSB + int16_t i; // MSB + int16_t q; // LSB } caribou_smi_sample_complex_int16; typedef struct @@ -95,9 +95,19 @@ smi_stream_state_en caribou_smi_get_driver_streaming_state(caribou_smi_st* dev); int caribou_smi_read(caribou_smi_st* dev, caribou_smi_channel_en channel, caribou_smi_sample_complex_int16* buffer, caribou_smi_sample_meta* metadata, size_t length_samples); - + +// This version of caribou_smi_writes(...) expects smaples but retruns bytes. +// Deprecated: use caribou_smi_write_samples() instead. int caribou_smi_write(caribou_smi_st* dev, caribou_smi_channel_en channel, - caribou_smi_sample_complex_int16* buffer, size_t length_samples); + caribou_smi_sample_complex_int16* buffer, size_t length_samples); + +// Write N *samples* (each sizeof(caribou_smi_sample_complex_int16)). +// Returns number of *samples* actually accepted, 0 if back-pressured, +// or -errno on error. +int caribou_smi_write_samples(caribou_smi_st *smi, + caribou_smi_channel_en ch, + const caribou_smi_sample_complex_int16 *samples, + int n_samples); size_t caribou_smi_get_native_batch_samples(caribou_smi_st* dev); diff --git a/software/libcariboulite/src/caribou_smi/caribou_smi_modules.c b/software/libcariboulite/src/caribou_smi/caribou_smi_modules.c index 59b157b0..0f9c987d 100644 --- a/software/libcariboulite/src/caribou_smi/caribou_smi_modules.c +++ b/software/libcariboulite/src/caribou_smi/caribou_smi_modules.c @@ -5,7 +5,7 @@ #define ZF_LOG_DEF_SRCLOC ZF_LOG_SRCLOC_LONG #define ZF_LOG_TAG "CARIBOU_SMI_MODULES" -#define _GNU_SOURCE +//#define _GNU_SOURCE #include #include #include diff --git a/software/libcariboulite/src/cariboulite_fpga_firmware.h b/software/libcariboulite/src/cariboulite_fpga_firmware.h index e610570b..0833f112 100644 --- a/software/libcariboulite/src/cariboulite_fpga_firmware.h +++ b/software/libcariboulite/src/cariboulite_fpga_firmware.h @@ -17,16 +17,16 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2024-04-09 - * Time: 13:13:50 + * Date: 2025-10-04 + * Time: 11:07:28 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 50, - .tm_min = 13, - .tm_hour = 13, - .tm_mday = 9, - .tm_mon = 3, /* +1 */ - .tm_year = 124, /* +1900 */ + .tm_sec = 28, + .tm_min = 7, + .tm_hour = 11, + .tm_mday = 4, + .tm_mon = 9, /* +1 */ + .tm_year = 125, /* +1900 */ }; /* @@ -38,382 +38,382 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x10, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -421,16 +421,16 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, + 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, @@ -438,726 +438,726 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 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0x00, 0x02, 0x41, 0x00, 0x00, 0x10, 0xA1, 0xC0, 0x01, 0x04, 0x00, 0x00, + 0x02, 0x00, 0x02, 0x00, 0x40, 0x04, 0x10, 0x00, 0x02, 0x84, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, + 0x28, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + 0x04, 0x06, 0x28, 0xF4, 0xE9, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x2A, + 0x00, 0x00, 0x08, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xA9, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x38, 0x20, 0x01, 0x8F, 0xB4, 0x08, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x71, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + 0xA0, 0x00, 0x00, 0x2C, 0x42, 0x00, 0x00, 0x00, 0x32, 0x9E, 0x80, 0x00, 0x00, 0x00, 0x0A, 0x99, + 0x76, 0x02, 0x28, 0x05, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, 0x00, 0x00, 0x00, 0x30, 0x10, 0xA7, + 0xDE, 0x14, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x01, 0xE4, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, + 0x00, 0x03, 0x16, 0x40, 0x01, 0xC0, 0x80, 0x00, 0x2A, 0x58, 0x6C, 0x47, 0xC0, 0x00, 0x00, 0x00, + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0x00, 0x41, 0x60, 0x00, 0x02, 0x00, 0x84, + 0x00, 0xA0, 0x10, 0x00, 0x08, 0x00, 0x23, 0xE4, 0x00, 0x22, 0x02, 0x80, 0x00, 0x00, 0x90, 0x00, + 0x0C, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x30, 0x68, 0x04, 0xE9, 0xF0, 0x00, 0x00, 0x84, 0x00, + 0x00, 0x02, 0xA0, 0x7E, 0x0E, 0x00, 0x00, 0x24, 0x08, 0x00, 0x01, 0x00, 0xE0, 0x04, 0xC0, 0x00, + 0x6E, 0x70, 0x05, 0x20, 0x08, 0x20, 0xE0, 0x78, 0x80, 0x04, 0x80, 0x00, 0x00, 0x00, 0xE0, 0x08, + 0x02, 0x00, 0x80, 0xB4, 0x08, 0x00, 0xA4, 0x0C, 0x80, 0x00, 0x00, 0x01, 0x0D, 0xB7, 0x46, 0x80, + 0x51, 0x00, 0x00, 0x00, 0x0F, 0x0A, 0x00, 0x14, 0x01, 0x20, 0xC3, 0x40, 0x21, 0x00, 0x00, 0x00, + 0x00, 0x0D, 0x00, 0x94, 0x04, 0x5A, 0x06, 0x80, 0x40, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xC1, + 0xD0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x56, 0x5E, 0x28, 0x02, 0x50, 0x00, 0x20, 0x60, 0x80, 0x00, + 0x09, 0x00, 0x87, 0x20, 0x3C, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x18, 0x51, 0x00, 0x0F, 0xF0, + 0x24, 0x03, 0x80, 0x05, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0xC0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20, 0x00, 0x03, 0x25, 0xC0, 0x00, 0x00, + 0x02, 0x80, 0x1C, 0x07, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x09, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x60, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x81, 0x80, 0x00, 0x00, 0x60, 0x70, 0x00, 0x00, 0x09, 0x00, 0x00, 0x01, 0xE0, 0x00, + 0x40, 0x00, 0x00, 0x02, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x08, 0x00, 0x50, 0x00, 0x00, 0x00, 0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x8B, 0x30, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xA9, 0x58, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/software/libcariboulite/src/cariboulite_radio.c b/software/libcariboulite/src/cariboulite_radio.c index af93fa89..847f12d0 100644 --- a/software/libcariboulite/src/cariboulite_radio.c +++ b/software/libcariboulite/src/cariboulite_radio.c @@ -39,6 +39,7 @@ int cariboulite_radio_init(cariboulite_radio_state_st* radio, sys_st *sys, carib radio->cw_output = false; radio->lo_output = false; radio->tx_loopback_anabled = false; + radio->tx_control_with_iq_if = true; radio->smi_channel_id = GET_SMI_CH(type); // activation of the channel @@ -488,7 +489,7 @@ int cariboulite_radio_set_tx_bandwidth(cariboulite_radio_state_st* radio, .tx_power = 18 + radio->tx_power, // same as before .analog_bw = (at86rf215_radio_tx_cut_off_en)tx_bw, .digital_bw = (at86rf215_radio_f_cut_en)radio->tx_fcut, // same as before - .fs = (at86rf215_radio_sample_rate_en)radio->tx_fs, // same as before + .fs = (at86rf215_radio_sample_rate_en)radio->tx_fs, // same as before .direct_modulation = 0, }; @@ -1126,13 +1127,15 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, if (radio->smi_channel_id == caribou_smi_channel_900) { modem_iq_config.radio09_mode = at86rf215_iq_if_mode; - modem_iq_config.radio24_mode = at86rf215_baseband_mode; + //modem_iq_config.radio24_mode = at86rf215_baseband_mode; // both radios need to be in iq_if mode + modem_iq_config.radio24_mode = at86rf215_iq_if_mode; modem_iq_config.clock_skew = at86rf215_iq_clock_data_skew_4_906ns; smi_state = smi_stream_rx_channel_0; } else if (radio->smi_channel_id == caribou_smi_channel_2400) { - modem_iq_config.radio09_mode = at86rf215_baseband_mode; + //modem_iq_config.radio09_mode = at86rf215_baseband_mode; // both radios need to be in iq_if mode + modem_iq_config.radio09_mode = at86rf215_iq_if_mode; modem_iq_config.radio24_mode = at86rf215_iq_if_mode; modem_iq_config.clock_skew = at86rf215_iq_clock_data_skew_4_906ns; smi_state = smi_stream_rx_channel_1; @@ -1160,15 +1163,29 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, //=========================================================== else if (radio->channel_direction == cariboulite_channel_dir_tx) { + at86rf215_radio_irq_st int_mask = { + .wake_up_por = 1, + .trx_ready = 1, + .energy_detection_complete = 1, + .battery_low = 1, + .trx_error = 1, + .IQ_if_sync_fail = 1, + .res = 0, + }; + at86rf215_radio_setup_interrupt_mask(&radio->sys->modem, GET_MODEM_CH(radio->type), &int_mask); + at86rf215_iq_interface_config_st modem_iq_config = { .loopback_enable = radio->tx_loopback_anabled, + //.loopback_enable = 0, .drv_strength = at86rf215_iq_drive_current_4ma, .common_mode_voltage = at86rf215_iq_common_mode_v_ieee1596_1v2, .tx_control_with_iq_if = !radio->cw_output, + //.tx_control_with_iq_if = radio->tx_control_with_iq_if, // we always use the modem tx control .radio09_mode = at86rf215_iq_if_mode, .radio24_mode = at86rf215_iq_if_mode, .clock_skew = at86rf215_iq_clock_data_skew_2_906ns, + }; at86rf215_setup_iq_if(&radio->sys->modem, &modem_iq_config); @@ -1218,9 +1235,19 @@ int cariboulite_radio_activate_channel(cariboulite_radio_state_st* radio, 0, 0x3F); // apply the state - caribou_smi_set_driver_streaming_state(&radio->sys->smi, smi_stream_tx_channel); + //caribou_smi_set_driver_streaming_state(&radio->sys->smi, smi_stream_tx_channel); + // turn on the SMI stream + if (caribou_smi_set_driver_streaming_state(&radio->sys->smi, smi_stream_tx_channel) != 0) + { + ZF_LOGD("Failed to configure modem with cmd_tx"); + return -1; + } caribou_fpga_set_smi_ctrl_data_direction (&radio->sys->fpga, 0); - //cariboulite_radio_set_modem_state(radio, cariboulite_radio_state_cmd_tx); + + if(!radio->tx_control_with_iq_if) + { + cariboulite_radio_set_modem_state(radio, cariboulite_radio_state_cmd_tx); + } } } @@ -1302,7 +1329,10 @@ int cariboulite_radio_write_samples(cariboulite_radio_state_st* radio, { ZF_LOGD("SMI writing operation returned timeout"); } - + //else if (ret > 0) + //{ + // ZF_LOGD("SMI writing operation succeeded, %d samples written", ret); + //} return ret; } diff --git a/software/libcariboulite/src/cariboulite_radio.h b/software/libcariboulite/src/cariboulite_radio.h index 9abbc4e6..983a11f1 100644 --- a/software/libcariboulite/src/cariboulite_radio.h +++ b/software/libcariboulite/src/cariboulite_radio.h @@ -174,6 +174,7 @@ typedef struct cariboulite_radio_sample_rate_en tx_fs; bool tx_loopback_anabled; + bool tx_control_with_iq_if; // if true, the modem will control TX with I/Q data // at86rf215_radio_energy_detection_st rx_energy_detection; float rx_energy_detection_value; diff --git a/software/libcariboulite/src/cariboulite_setup.c b/software/libcariboulite/src/cariboulite_setup.c index f5ea7575..7df28f06 100644 --- a/software/libcariboulite/src/cariboulite_setup.c +++ b/software/libcariboulite/src/cariboulite_setup.c @@ -5,6 +5,13 @@ #define ZF_LOG_TAG "CARIBOULITE Setup" #include "zf_log/zf_log.h" +// Enable POSIX/GNU extensions so siginfo_t and SA_SIGINFO are visible +#ifndef _POSIX_C_SOURCE +# define _POSIX_C_SOURCE 200809L +#endif +#ifndef _GNU_SOURCE +# define _GNU_SOURCE +#endif #include #include @@ -250,7 +257,7 @@ int cariboulite_release_io (sys_st* sys) } //======================================================================================= -int cariboulite_configure_fpga (sys_st* sys, cariboulite_firmware_source_en src, char* fpga_bin_path) +int cariboulite_configure_fpga (sys_st* sys, cariboulite_firmware_source_en src, const char* fpga_bin_path) { int ret = 0; switch (src) diff --git a/software/libcariboulite/src/cariboulite_setup.h b/software/libcariboulite/src/cariboulite_setup.h index 1c3d3899..11173d00 100644 --- a/software/libcariboulite/src/cariboulite_setup.h +++ b/software/libcariboulite/src/cariboulite_setup.h @@ -179,7 +179,7 @@ int cariboulite_setup_signal_handler (sys_st *sys, * NULL should be passed here. * @return 0 (success), -1 (fail) */ -int cariboulite_configure_fpga (sys_st* sys, cariboulite_firmware_source_en src, char* fpga_bin_path); +int cariboulite_configure_fpga (sys_st* sys, cariboulite_firmware_source_en src, const char* fpga_bin_path); /** * @brief Release resources diff --git a/software/libcariboulite/src/cariboulite_sys_accessor.c b/software/libcariboulite/src/cariboulite_sys_accessor.c new file mode 100644 index 00000000..9c90aef6 --- /dev/null +++ b/software/libcariboulite/src/cariboulite_sys_accessor.c @@ -0,0 +1,10 @@ +// src/cariboulite_sys_accessor.c +#include "cariboulite_setup.h" + +// cariboulite_sys is defined inside the library build. +// This accessor returns its address without exposing the data symbol. +extern sys_st cariboulite_sys; + +sys_st *cariboulite_get_sys(void) { + return &cariboulite_sys; +} \ No newline at end of file diff --git a/software/libcariboulite/src/cariboulite_sys_storage.c b/software/libcariboulite/src/cariboulite_sys_storage.c new file mode 100644 index 00000000..de359eae --- /dev/null +++ b/software/libcariboulite/src/cariboulite_sys_storage.c @@ -0,0 +1,5 @@ +// src/cariboulite_sys_storage.c +#include "cariboulite_setup.h" + +// This provides the storage for the global system object used by the lib. +sys_st cariboulite_sys = {0}; diff --git a/software/libcariboulite/src/cariboulite_test_app.c b/software/libcariboulite/src/cariboulite_test_app.c index 8e7252fa..38774e5e 100644 --- a/software/libcariboulite/src/cariboulite_test_app.c +++ b/software/libcariboulite/src/cariboulite_test_app.c @@ -2,6 +2,14 @@ #define ZF_LOG_LEVEL ZF_LOG_VERBOSE #endif +// Enable POSIX/GNU extensions so siginfo_t and SA_SIGINFO are visible +#ifndef _POSIX_C_SOURCE +# define _POSIX_C_SOURCE 200809L +#endif +#ifndef _GNU_SOURCE +# define _GNU_SOURCE +#endif + #define ZF_LOG_DEF_SRCLOC ZF_LOG_SRCLOC_LONG #define ZF_LOG_TAG "CARIBOULITE Test" #include "zf_log/zf_log.h" diff --git a/software/libcariboulite/src/hat/hat.c b/software/libcariboulite/src/hat/hat.c index 844fa9ce..abf2dc6b 100644 --- a/software/libcariboulite/src/hat/hat.c +++ b/software/libcariboulite/src/hat/hat.c @@ -387,39 +387,74 @@ int hat_fill_in(hat_st *hat) strcpy(VENDOR_PSTR_POINT(vinf), hat->product_name); // read 128 random bits from /dev/urandom + // int random_file = open("/dev/urandom", O_RDONLY); + // void* temp_serial_loc = (void*)&vinf->serial_1; + // ssize_t result = read(random_file, temp_serial_loc, 16); + // close(random_file); + + // if (result <= 0) + // { + // printf("Unable to read from /dev/urandom to set up UUID"); + // return -1; + // } + // else + // { + // //put in the version + // vinf->serial_3 = (vinf->serial_3 & 0xffff0fff) | 0x00004000; + + // //put in the variant + // vinf->serial_2 = (vinf->serial_2 & 0x3fffffff) | 0x80000000; + + // printf("Gen UUID=%08x-%04x-%04x-%04x-%04x%08x\n", vinf->serial_4, + // vinf->serial_3>>16, + // vinf->serial_3 & 0xffff, + // vinf->serial_2>>16, + // vinf->serial_2 & 0xffff, + // vinf->serial_1); + // sprintf(hat->generated_uuid, "%08x-%04x-%04x-%04x-%04x%08x", vinf->serial_4, + // vinf->serial_3>>16, + // vinf->serial_3 & 0xffff, + // vinf->serial_2>>16, + // vinf->serial_2 & 0xffff, + // vinf->serial_1); + // serial_from_uuid(hat->generated_uuid, &hat->generated_serial); + // } + uint32_t rnd[4]; int random_file = open("/dev/urandom", O_RDONLY); - void* temp_serial_loc = (void*)&vinf->serial_1; - ssize_t result = read(random_file, temp_serial_loc, 16); - close(random_file); - - if (result <= 0) - { - printf("Unable to read from /dev/urandom to set up UUID"); + ssize_t result = read(random_file, rnd, sizeof(rnd)); + if (result != sizeof(rnd)) { + close(random_file); + fprintf(stderr, "Unable to read 16 bytes from /dev/urandom\n"); return -1; } - else - { - //put in the version - vinf->serial_3 = (vinf->serial_3 & 0xffff0fff) | 0x00004000; - - //put in the variant - vinf->serial_2 = (vinf->serial_2 & 0x3fffffff) | 0x80000000; - - printf("Gen UUID=%08x-%04x-%04x-%04x-%04x%08x\n", vinf->serial_4, - vinf->serial_3>>16, - vinf->serial_3 & 0xffff, - vinf->serial_2>>16, - vinf->serial_2 & 0xffff, - vinf->serial_1); - sprintf(hat->generated_uuid, "%08x-%04x-%04x-%04x-%04x%08x", vinf->serial_4, - vinf->serial_3>>16, - vinf->serial_3 & 0xffff, - vinf->serial_2>>16, - vinf->serial_2 & 0xffff, - vinf->serial_1); - serial_from_uuid(hat->generated_uuid, &hat->generated_serial); - } - + + close(random_file); + + vinf->serial_1 = rnd[0]; + vinf->serial_2 = rnd[1]; + vinf->serial_3 = rnd[2]; + vinf->serial_4 = rnd[3]; + + //put in the version + vinf->serial_3 = (vinf->serial_3 & 0xffff0fff) | 0x00004000; + + //put in the variant + vinf->serial_2 = (vinf->serial_2 & 0x3fffffff) | 0x80000000; + + printf("Gen UUID=%08x-%04x-%04x-%04x-%04x%08x\n", vinf->serial_4, + vinf->serial_3>>16, + vinf->serial_3 & 0xffff, + vinf->serial_2>>16, + vinf->serial_2 & 0xffff, + vinf->serial_1); + sprintf(hat->generated_uuid, "%08x-%04x-%04x-%04x-%04x%08x", vinf->serial_4, + vinf->serial_3>>16, + vinf->serial_3 & 0xffff, + vinf->serial_2>>16, + vinf->serial_2 & 0xffff, + vinf->serial_1); + serial_from_uuid(hat->generated_uuid, &hat->generated_serial); + atom->type = ATOM_VENDOR_TYPE; atom->count = header->numatoms; atom->dlen = VENDOR_INFO_COMPACT_SIZE(vinf) + 2; diff --git a/software/libcariboulite/src/io_utils/io_utils.c b/software/libcariboulite/src/io_utils/io_utils.c index f19ca40f..d0917684 100644 --- a/software/libcariboulite/src/io_utils/io_utils.c +++ b/software/libcariboulite/src/io_utils/io_utils.c @@ -117,5 +117,10 @@ inline int io_utils_setup_interrupt(int gpio, gpioAlertFuncEx_t cb, void* context) { - return 0; //gpioSetAlertFuncEx(gpio, cb, context); + // surpress 'unused parameter' warnings + (void)gpio; + (void)cb; + (void)context; + + return 0; //gpioSetAlertFuncEx(gpio, cb, context); } diff --git a/software/libcariboulite/src/math_compat.h b/software/libcariboulite/src/math_compat.h new file mode 100644 index 00000000..06b75524 --- /dev/null +++ b/software/libcariboulite/src/math_compat.h @@ -0,0 +1,13 @@ +#pragma once +#include + +/* Provide M_PI and friends if the C library didn't */ +#ifndef M_PI +# define M_PI 3.14159265358979323846 +#endif +#ifndef M_TWOPI +# define M_TWOPI (2.0 * M_PI) +#endif +#ifndef M_PI_2 +# define M_PI_2 1.57079632679489661923 +#endif \ No newline at end of file diff --git a/software/libcariboulite/src/nbfm4m_mod.c b/software/libcariboulite/src/nbfm4m_mod.c new file mode 100644 index 00000000..7f62c15d --- /dev/null +++ b/software/libcariboulite/src/nbfm4m_mod.c @@ -0,0 +1,112 @@ +#include "nbfm4m_mod.h" +#include +#include +#include "math_compat.h" + +typedef struct { double a0,a1; float x1; } preemph_t; +static void preemph_init(preemph_t* p,double fs,double tau){ + if(tau<=0){p->a0=1;p->a1=0;p->x1=0;return;} + double T=1.0/fs, alpha=tau/(tau+T); + p->a0=1.0+alpha; p->a1=-alpha; p->x1=0; +} +static inline float preemph_run(preemph_t* p,float x){ + float y=(float)p->a0*x+(float)p->a1*p->x1; p->x1=x; return y; +} + +struct nbfm4m_mod { + double fs_a, fs_rf, f_dev, R, a_to_rf, k; + float out_scale; int lin; + double phase, dphi_cur, dphi_next, interp_step, interp_acc; + preemph_t pe; + float* afifo; size_t cap, head, tail, cnt; + + //new + uint32_t lm_phase; + int use_lin; +}; + +nbfm4m_mod_t* nbfm4m_create(const nbfm4m_cfg_t* c){ + nbfm4m_mod_t* m=(nbfm4m_mod_t*)calloc(1,sizeof(*m)); + m->fs_a=c?c->audio_fs:48000.0; m->fs_rf=c?c->rf_fs:4000000.0; + m->f_dev=c?c->f_dev_hz:2500.0; m->out_scale=c?c->out_scale:12000.0f; + m->lin=c?c->linear_interp:1; m->R=m->fs_rf/m->fs_a; m->a_to_rf=1.0/m->R; + m->k=2.0*M_PI*m->f_dev/m->fs_rf; preemph_init(&m->pe,m->fs_a,c?c->preemph_tau_s:0.0); + m->interp_acc=1.0; m->cap=4096; m->afifo=(float*)calloc(m->cap,sizeof(float)); + + //new + m->lm_phase = 0; m->use_lin = m->lin; + return m; +} +void nbfm4m_destroy(nbfm4m_mod_t* m) { + if(!m)return; + free(m->afifo); + free(m); +} + +size_t nbfm4m_push_audio(nbfm4m_mod_t* m,const float* a,size_t N) { + size_t p=0; + for(size_t n=0;ncnt == m->cap) break; + m->afifo[m->tail] = a[n]; + m->tail=(m->tail+1)%m->cap; + m->cnt++; p++; + } + return p; +} +static int fetch_audio(nbfm4m_mod_t* m) { + if (m->cnt == 0) return 0; + + float x = m->afifo[m->head]; + m->head = (m->head+1)%m->cap; + m->cnt--; + + if (x>1) x=1; + else if (x<-1) x=-1; + + float xp=preemph_run(&m->pe,x); + m->dphi_next=m->k*(double)xp; + return 1; +} + +size_t nbfm4m_pull_iq(nbfm4m_mod_t* m, iq16_t* dst, size_t N) +{ + const uint32_t L = 250; // up by 250 + const uint32_t M = 3; // down by 3 + size_t out = 0; + + while (out < N) { + // Advance resampler phase (exact integer arithmetic) + m->lm_phase += M; + if (m->lm_phase >= L) { + m->lm_phase -= L; + + // Move current -> next and fetch next audio-derived freq + m->dphi_cur = m->dphi_next; + if (!fetch_audio(m)) { + // no new audio; hold frequency (rare if producer keeps up) + m->dphi_next = m->dphi_cur; + } + } + + // Linear interpolation of frequency between audio ticks (optional) + double frac = m->use_lin ? (double)m->lm_phase / (double)L : 0.0; + double dphi = m->dphi_cur + (m->dphi_next - m->dphi_cur) * frac; + + // Integrate to phase with robust wrap + m->phase += dphi; + if (m->phase > M_PI) m->phase -= 2.0 * M_PI; + if (m->phase < -M_PI) m->phase += 2.0 * M_PI; + + float ci = (float)cos(m->phase); + float sq = (float)sin(m->phase); + int32_t I = (int32_t)lrintf(ci * m->out_scale); + int32_t Q = (int32_t)lrintf(sq * m->out_scale); + if (I > 32767) I = 32767; else if (I < -32768) I = -32768; + if (Q > 32767) Q = 32767; else if (Q < -32768) Q = -32768; + + dst[out].i = (int16_t)I; + dst[out].q = (int16_t)Q; + out++; + } + return out; +} \ No newline at end of file diff --git a/software/libcariboulite/src/nbfm4m_mod.h b/software/libcariboulite/src/nbfm4m_mod.h new file mode 100644 index 00000000..d5382716 --- /dev/null +++ b/software/libcariboulite/src/nbfm4m_mod.h @@ -0,0 +1,28 @@ +#pragma once +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct __attribute__((__packed__)) { int16_t i; int16_t q; } iq16_t; +typedef struct nbfm4m_mod nbfm4m_mod_t; + +typedef struct { + double audio_fs; // 48000.0 + double rf_fs; // 4000000.0 + double f_dev_hz; // e.g., 2500.0 + double preemph_tau_s; // 0 to disable + float out_scale; // e.g., 12000 + int linear_interp; // 1 = better quality +} nbfm4m_cfg_t; + +nbfm4m_mod_t* nbfm4m_create(const nbfm4m_cfg_t* cfg); +void nbfm4m_destroy(nbfm4m_mod_t* m); +size_t nbfm4m_push_audio(nbfm4m_mod_t* m, const float* audio48k, size_t frames); +size_t nbfm4m_pull_iq (nbfm4m_mod_t* m, iq16_t* dst, size_t max_frames); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/software/libcariboulite/src/tone48k.c b/software/libcariboulite/src/tone48k.c new file mode 100644 index 00000000..87adc635 --- /dev/null +++ b/software/libcariboulite/src/tone48k.c @@ -0,0 +1,22 @@ +#include "audio48k_source.h" +#include +#include +#include "math_compat.h" + +struct audio48k_source { double ph, dph; float amp; }; + +audio48k_source_t* tone48k_create(double f, float a) { + audio48k_source_t* s = (audio48k_source_t*)calloc(1,sizeof(*s)); + s->ph = 0.0; s->dph = 2.0*M_PI*f/48000.0; s->amp = a; return s; +} + +size_t audio48k_read(audio48k_source_t* s, float* dst, size_t n) { + for (size_t i=0;iamp * sin(s->ph)); + s->ph += s->dph; + if (s->ph > M_PI) s->ph -= 2.0*M_PI; + } + return n; +} + +void audio48k_destroy(audio48k_source_t* s) { free(s); } \ No newline at end of file diff --git a/software/utils/generate_bin_blob b/software/utils/generate_bin_blob index da230a3e..31b0d1d5 100755 Binary files a/software/utils/generate_bin_blob and b/software/utils/generate_bin_blob differ