H004: implement packed low-rank canvas layout before claiming 32B/Gaussian

[cashcon57]

Gate

In-vitro Bundle D1 arithmetic refuted the broad H004 32 bytes/Gaussian claim as stated.

Evidence

Memo: docs/research/2026-05-08-h004-canvas-l2-residency-arithmetic.md

Key findings:

• No exact fp16-packed runtime canvas struct exists today.
• Current v6 CanvasState is fp32 SoA: positions, scales, rotations, opacities, colors.
• Current v6 + ST-score state is 36 + 4R bytes/Gaussian.
• At N=16K, R=64, current v6 + ST-score is ~4.56 MiB, about 76% of 3080 Ti's 6 MiB L2 before tile lists, conic scratch, output tiles, or model activations.
• The 32B/Gaussian target only holds for a future packed fp16 low-rank record at R=4 or R=8; it fails at R=64 even under favorable packing.

Required fix

• Add the actual packed inference runtime record or update the v6.2/H004 docs so L2 residency is described as a future low-rank packed-runtime property only.
• Keep R=64 out of any 32B/Gaussian arithmetic.
• Re-run D1 after the packed runtime layout lands.