From external feedback (2026-05-08): consider RepVGG-style (or ECBSR/RepSR) multi-branch reparameterizable training in the student backbone — train with 3×3 + 1×1 + identity branches in parallel, fuse to a single 3×3 at inference for zero added inference cost.
Current state: student backbone (oss/sr/v6/student/, commit aba1fc8) is FasterNet-based per FSR-4 architectural observations memo. FasterNet was chosen because AMD's MIT-licensed FSR 4 source validates it on shipping hardware.
This issue: AFTER v6.2-pico-002 baseline converges, ablate three configurations:
- Current FasterNet baseline
- FasterNet with RepBlock inside the 1×1 expand path (non-standard hybrid)
- Pure RepVGG-style stack (drops FasterNet partial-conv pattern)
Quality target: +0.1-0.3 dB PSNR vs FasterNet baseline at same inference cost. If hybrid (#2) wins, consider for v6.2-pico-002.2.
Refs:
- RepVGG: Ding et al., CVPR 2021
- ECBSR: edge-oriented conv block for SR (mobile)
- RepSR: ESRGAN-family reparameterization
Companion: docs/research/2026-05-08-fsr4-architecture-observations.md
From external feedback (2026-05-08): consider RepVGG-style (or ECBSR/RepSR) multi-branch reparameterizable training in the student backbone — train with 3×3 + 1×1 + identity branches in parallel, fuse to a single 3×3 at inference for zero added inference cost.
Current state: student backbone (oss/sr/v6/student/, commit aba1fc8) is FasterNet-based per FSR-4 architectural observations memo. FasterNet was chosen because AMD's MIT-licensed FSR 4 source validates it on shipping hardware.
This issue: AFTER v6.2-pico-002 baseline converges, ablate three configurations:
Quality target: +0.1-0.3 dB PSNR vs FasterNet baseline at same inference cost. If hybrid (#2) wins, consider for v6.2-pico-002.2.
Refs:
Companion: docs/research/2026-05-08-fsr4-architecture-observations.md