diff --git a/tests/HierBitSlice/HierBitSlice.log b/tests/HierBitSlice/HierBitSlice.log index ca514400a5..ead4b450eb 100644 --- a/tests/HierBitSlice/HierBitSlice.log +++ b/tests/HierBitSlice/HierBitSlice.log @@ -8610,6 +8610,26 @@ design: (work@int_execute_stage) \_begin: (work@int_execute_stage), line:293:9, endln:319:12 |vpiCaseType:1 |vpiQualifier:1 + |vpiCondition: + \_hier_path: (of_instruction.branch_type), line:294:26, endln:294:52 + |vpiParent: + \_case_stmt: , line:294:13, endln:318:20 + |vpiActual: + \_ref_obj: (of_instruction), line:294:26, endln:294:40 + |vpiParent: + \_hier_path: (of_instruction.branch_type), line:294:26, endln:294:52 + |vpiName:of_instruction + |vpiActual: + \_struct_var: (work@int_execute_stage.of_instruction), line:62:39, endln:62:53 + |vpiActual: + \_ref_obj: (work@int_execute_stage.branch_type), line:294:41, endln:294:52 + |vpiParent: + \_hier_path: (of_instruction.branch_type), line:294:26, endln:294:52 + |vpiName:branch_type + |vpiFullName:work@int_execute_stage.branch_type + |vpiActual: + \_typespec_member: (branch_type), line:37:19, endln:37:30 + |vpiName:of_instruction.branch_type |vpiCaseItem: \_case_item: , line:295:17, endln:299:20 |vpiParent: @@ -8945,6 +8965,26 @@ design: (work@int_execute_stage) \_begin: (work@int_execute_stage), line:324:5, endln:339:8 |vpiCaseType:1 |vpiQualifier:1 + |vpiCondition: + \_hier_path: (of_instruction.branch_type), line:332:22, endln:332:48 + |vpiParent: + \_case_stmt: , line:332:9, endln:338:16 + |vpiActual: + \_ref_obj: (of_instruction), line:332:22, endln:332:36 + |vpiParent: + \_hier_path: (of_instruction.branch_type), line:332:22, endln:332:48 + |vpiName:of_instruction + |vpiActual: + \_struct_var: (work@int_execute_stage.of_instruction), line:62:39, endln:62:53 + |vpiActual: + \_ref_obj: (work@int_execute_stage.branch_type), line:332:37, endln:332:48 + |vpiParent: + \_hier_path: (of_instruction.branch_type), line:332:22, endln:332:48 + |vpiName:branch_type + |vpiFullName:work@int_execute_stage.branch_type + |vpiActual: + \_typespec_member: (branch_type), line:37:19, endln:37:30 + |vpiName:of_instruction.branch_type |vpiCaseItem: \_case_item: , line:333:13, endln:334:63 |vpiParent: @@ -12418,6 +12458,26 @@ design: (work@int_execute_stage) \_begin: (work@int_execute_stage.lane_alu_gen[0]), line:241:13, endln:271:16 |vpiCaseType:1 |vpiQualifier:1 + |vpiCondition: + \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 + |vpiParent: + \_case_stmt: , line:242:17, endln:270:24 + |vpiActual: + \_ref_obj: (of_instruction), line:242:30, endln:242:44 + |vpiParent: + \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 + |vpiName:of_instruction + |vpiActual: + \_struct_var: (work@int_execute_stage.of_instruction), line:62:39, endln:62:53 + |vpiActual: + \_ref_obj: (work@int_execute_stage.lane_alu_gen[0].alu_op), line:242:45, endln:242:51 + |vpiParent: + \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 + |vpiName:alu_op + |vpiFullName:work@int_execute_stage.lane_alu_gen[0].alu_op + |vpiActual: + \_typespec_member: (alu_op), line:30:14, endln:30:20 + |vpiName:of_instruction.alu_op |vpiCaseItem: \_case_item: , line:243:21, endln:244:50 |vpiParent: @@ -17312,6 +17372,26 @@ design: (work@int_execute_stage) \_begin: (work@int_execute_stage.lane_alu_gen[1]), line:241:13, endln:271:16 |vpiCaseType:1 |vpiQualifier:1 + |vpiCondition: + \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 + |vpiParent: + \_case_stmt: , line:242:17, endln:270:24 + |vpiActual: + \_ref_obj: (of_instruction), line:242:30, endln:242:44 + |vpiParent: + \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 + |vpiName:of_instruction + |vpiActual: + \_struct_var: (work@int_execute_stage.of_instruction), line:62:39, endln:62:53 + |vpiActual: + \_ref_obj: (work@int_execute_stage.lane_alu_gen[1].alu_op), line:242:45, endln:242:51 + |vpiParent: + \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 + |vpiName:alu_op + |vpiFullName:work@int_execute_stage.lane_alu_gen[1].alu_op + |vpiActual: + \_typespec_member: (alu_op), line:30:14, endln:30:20 + |vpiName:of_instruction.alu_op |vpiCaseItem: \_case_item: , line:243:21, endln:244:50 |vpiParent: diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log index 33bbfb3399..4378993f2f 100644 --- a/third_party/tests/CoresSweRV/CoresSweRV.log +++ b/third_party/tests/CoresSweRV/CoresSweRV.log @@ -5410,8 +5410,11 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:34:9: Non synthesizable construct, uvm_link_base [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:181:37: Non synthesizable construct, [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:181:1: Non synthesizable construct, uvm_cause_effect_link +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:138:17: Non synthesizable construct, clone [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:135:1: Non synthesizable construct, uvm_class_clone +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:97:14: Non synthesizable construct, compare [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:94:1: Non synthesizable construct, uvm_class_comp +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:117:14: Non synthesizable construct, convert2string [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:114:1: Non synthesizable construct, uvm_class_converter [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_pair.svh:38:1: Non synthesizable construct, uvm_class_pair [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_cmdline_processor.svh:27:1: Non synthesizable construct, uvm_cmd_line_verb @@ -5739,8 +5742,10 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh:51:1: Non synthesizable construct, uvm_reg_mem_hdl_paths_seq [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/reg/sequences/uvm_reg_mem_shared_access_seq.svh:61:1: Non synthesizable construct, uvm_reg_shared_access_seq [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:654:30: Non synthesizable construct, get_factory +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:655:20: Non synthesizable construct, create_component_by_type [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:645:9: Non synthesizable construct, uvm_registry_component_creator [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:670:30: Non synthesizable construct, get_factory +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:672:20: Non synthesizable construct, create_object_by_type [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:661:9: Non synthesizable construct, uvm_registry_object_creator [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_resource_db_options.svh:101:14: Non synthesizable construct, get_arg_matches [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_resource_db_options.svh:49:1: Non synthesizable construct, uvm_resource_db_options @@ -5817,6 +5822,7 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:50:7: Non synthesizable construct, run_test [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:66:12: Non synthesizable construct, get_root [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:89:12: Non synthesizable construct, get_root +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:90:14: Non synthesizable construct, uvm_report_enabled [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:108:12: Non synthesizable construct, get_root [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:109:7: Non synthesizable construct, uvm_report [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:136:12: Non synthesizable construct, get_root diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 96956a4a21..06196339ae 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -80,9 +80,9 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): -- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 12%] Generating 12_beh_lib.sv -[ 12%] Generating 10_lsu_bus_intf.sv -[ 18%] Generating 11_ifu_bp_ctl.sv +[ 6%] Generating 10_lsu_bus_intf.sv +[ 12%] Generating 11_ifu_bp_ctl.sv +[ 18%] Generating 12_beh_lib.sv [ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv @@ -5501,8 +5501,11 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:34:9: Non synthesizable construct, uvm_link_base [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:181:37: Non synthesizable construct, [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:181:1: Non synthesizable construct, uvm_cause_effect_link +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:138:17: Non synthesizable construct, clone [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:135:1: Non synthesizable construct, uvm_class_clone +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:97:14: Non synthesizable construct, compare [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:94:1: Non synthesizable construct, uvm_class_comp +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:117:14: Non synthesizable construct, convert2string [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:114:1: Non synthesizable construct, uvm_class_converter [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_pair.svh:38:1: Non synthesizable construct, uvm_class_pair [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_cmdline_processor.svh:27:1: Non synthesizable construct, uvm_cmd_line_verb @@ -5830,8 +5833,10 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh:51:1: Non synthesizable construct, uvm_reg_mem_hdl_paths_seq [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/reg/sequences/uvm_reg_mem_shared_access_seq.svh:61:1: Non synthesizable construct, uvm_reg_shared_access_seq [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:654:30: Non synthesizable construct, get_factory +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:655:20: Non synthesizable construct, create_component_by_type [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:645:9: Non synthesizable construct, uvm_registry_component_creator [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:670:30: Non synthesizable construct, get_factory +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:672:20: Non synthesizable construct, create_object_by_type [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:661:9: Non synthesizable construct, uvm_registry_object_creator [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_resource_db_options.svh:101:14: Non synthesizable construct, get_arg_matches [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_resource_db_options.svh:49:1: Non synthesizable construct, uvm_resource_db_options @@ -5908,6 +5913,7 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:50:7: Non synthesizable construct, run_test [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:66:12: Non synthesizable construct, get_root [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:89:12: Non synthesizable construct, get_root +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:90:14: Non synthesizable construct, uvm_report_enabled [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:108:12: Non synthesizable construct, get_root [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:109:7: Non synthesizable construct, uvm_report [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:136:12: Non synthesizable construct, get_root diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log index b998fbde5f..801c1f0c3c 100644 --- a/third_party/tests/Opentitan/Opentitan.log +++ b/third_party/tests/Opentitan/Opentitan.log @@ -7183,8 +7183,11 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:34:9: Non synthesizable construct, uvm_link_base [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:181:37: Non synthesizable construct, [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_links.svh:181:1: Non synthesizable construct, uvm_cause_effect_link +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:138:17: Non synthesizable construct, clone [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:135:1: Non synthesizable construct, uvm_class_clone +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:97:14: Non synthesizable construct, compare [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:94:1: Non synthesizable construct, uvm_class_comp +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:117:14: Non synthesizable construct, convert2string [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_policies.svh:114:1: Non synthesizable construct, uvm_class_converter [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/comps/uvm_pair.svh:38:1: Non synthesizable construct, uvm_class_pair [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_cmdline_processor.svh:27:1: Non synthesizable construct, uvm_cmd_line_verb @@ -7512,8 +7515,10 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh:51:1: Non synthesizable construct, uvm_reg_mem_hdl_paths_seq [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/reg/sequences/uvm_reg_mem_shared_access_seq.svh:61:1: Non synthesizable construct, uvm_reg_shared_access_seq [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:654:30: Non synthesizable construct, get_factory +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:655:20: Non synthesizable construct, create_component_by_type [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:645:9: Non synthesizable construct, uvm_registry_component_creator [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:670:30: Non synthesizable construct, get_factory +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:672:20: Non synthesizable construct, create_object_by_type [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_registry.svh:661:9: Non synthesizable construct, uvm_registry_object_creator [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_resource_db_options.svh:101:14: Non synthesizable construct, get_arg_matches [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_resource_db_options.svh:49:1: Non synthesizable construct, uvm_resource_db_options @@ -7590,6 +7595,7 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:50:7: Non synthesizable construct, run_test [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:66:12: Non synthesizable construct, get_root [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:89:12: Non synthesizable construct, get_root +[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:90:14: Non synthesizable construct, uvm_report_enabled [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:108:12: Non synthesizable construct, get_root [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:109:7: Non synthesizable construct, uvm_report [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:136:12: Non synthesizable construct, get_root