From 06fb37961c23848dbe56febffd63549e0f5524ac Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 18 Apr 2023 11:18:34 -0700 Subject: [PATCH 1/2] wip non-elab primitive instances --- include/Surelog/Design/ModuleDefinition.h | 12 + include/Surelog/DesignCompile/CompileHelper.h | 5 + src/DesignCompile/CompileHelper.cpp | 144 + src/DesignCompile/CompileModule.cpp | 11 +- src/DesignCompile/UhdmWriter.cpp | 17 +- tests/ArianeElab/ArianeElab.log | 4 + tests/ArianeElab2/ArianeElab2.log | 4 + tests/ArrayExprFuncArg/ArrayExprFunArg.log | 2 + .../AssignmentPatternInAssignmentPattern.log | 2 + tests/Attributes/Attributes.log | 2 + tests/Attributes2/Attributes2.log | 2 + tests/BindStmt/BindStmt.log | 10 + tests/Bindings/Bindings.log | 4 + tests/BitsArray/BitsArray.log | 2 + tests/BitsHierPath/BitsHierPath.log | 8 + tests/BlackBox/BlackBox.log | 2 + tests/BlackBox/BlackBoxInst.log | 2 + tests/BlackBox/BlackBoxSubMod.log | 2 + .../BlackParrotSkipParam.log | 2 + tests/CarryTrans/CarryTrans.log | 136 +- tests/Cell/Cell.log | 6 + tests/ClogParam/ClogParam.log | 2 + .../ComplexParamOverload.log | 8 + .../ComplexParamOverload2.log | 8 + tests/Connection/Connection.log | 2 + tests/ConstHighConn/ConstHighConn.log | 2 + tests/ConstPort/ConstPort.log | 2 + tests/CovMacro/CovMacro.log | 4 + tests/DefParamFromParam/DefParamFromParam.log | 2 + tests/DefaultAssign/DefaultAssign.log | 2 + tests/DefaultNetType/DefaultNetType.log | 2 + .../DefaultPatternAssign.log | 6 + tests/DefaultPatternInt/DefaultPatternInt.log | 2 + .../DefaultPatternModule.log | 2 + tests/Delay2Param/Delay2Param.log | 2 +- tests/DollarBits/DollarBits.log | 2 + tests/DoublePres/DoublePres.log | 2 + tests/EarlgreyPackParam/EarlgreyPackParam.log | 4 + tests/ElabCParam/ElabCParam.log | 2 + tests/ElabIf/ElabIf.log | 6 + tests/EmptyAssign/EmptyAssign.log | 2 + tests/EnumConstElab/EnumConstElab.log | 4 + tests/Escape/Escape.log | 2 +- tests/FSMBsp13/FSMBsp13.log | 6 + tests/ForElab/ForElab.log | 2 +- tests/FuncDeclScope/FuncDeclScope.log | 2 + tests/FuncIoTypespec/FuncIoTypespec.log | 2 + tests/FuncParam/FuncParam.log | 4 + tests/FuncRetArray/FuncRetArray.log | 2 + tests/GateLevel/GateLevel.log | 183 +- tests/Gates/Gates.log | 520 ++- tests/GenNet/GenNet.log | 2 + tests/GenScopeFunc/GenScopeFunc.log | 2 + tests/GenerateInterface/GenerateInterface.log | 4 + tests/GenerateRegion/GenerateRegion.log | 2 + tests/GenerateUnnamed/GenerateUnnamed.log | 16 +- tests/HierPathBind/HierPathBind.log | 2 + tests/HierPathEval/HierPathEval.log | 2 + tests/HierPathOverride/HierPathOverride.log | 2 + tests/HighConnPart/HighConnPart.log | 2 + tests/Implicit/Implicit.log | 135 +- tests/ImplicitPorts2/ImplicitPorts2.log | 2 + tests/IntegerConcat/IntegerConcat.log | 2 + tests/InterfAlways/InterfAlways.log | 2 + tests/InterfHierPath/InterfHierPath.log | 2 + tests/InterfType/InterfType.log | 4 + tests/InterfTypeBad/InterfTypeBad.log | 2 + tests/InterfaceElab/InterfaceElab.log | 6 + tests/InterfaceModExp/InterfaceModExp.log | 4 + tests/InterfaceModPort/InterfaceModPort.log | 8 + tests/InterfaceProcess/InterfaceProcess.log | 2 + tests/InvalidTypeParam/InvalidTypeParam.log | 2 + tests/LargeHex/LargeHex.log | 2 + tests/LargeValue2Struct/LargeValue2Struct.log | 2 + tests/LibraryIntercon/LibraryIntercon.log | 24 +- tests/LocalParam/LocalParam.log | 4 + tests/LogicSize/LogicSize.log | 2 + tests/LongHex/LongHex.log | 2 + tests/Loop/Loop.log | 6 + tests/LoopParamOver/LoopParamOver.log | 2 + tests/MaskNeg/MaskNeg.log | 2 + tests/ModPortHighConn/ModPortHighConn.log | 4 + tests/ModPortParam/ModPortParam.log | 4 + .../MultiConcatValueSize.log | 2 + tests/NoParamSubs/NoParamSubs.log | 2 + tests/OldLibrary/OldLibrary.log | 12 +- tests/OneNetInterf/OneNetInterf.log | 12 + tests/OneNetModPort/OneNetModPort.log | 10 + .../OneNetModPortGeneric.log | 14 + tests/OneNetRange/OneNetRange.log | 12 + tests/PAssignType/PAssignType.log | 4 + tests/PackedEnumPort/PackedEnumPort.log | 2 + tests/ParamArray/ParamArray.log | 2 + tests/ParamArraySelect/ParamArraySelect.log | 2 + tests/ParamByValue/ParamByValue.log | 4 + tests/ParamComplex/ParamComplex.log | 2 + .../ParamComplexVerilator.log | 2 + tests/ParamConcat/ParamConcat.log | 2 + tests/ParamConst/ParamConst.log | 4 + tests/ParamElab/ParamElab.log | 2 + tests/ParamElabMulti/ParamElabMulti.log | 2 + tests/ParamFile/ParamFile.log | 2 + tests/ParamFile/ParamFileNoTop.log | 2 + tests/ParamFile/ParamFileOverr.log | 2 + tests/ParamFromPackage/ParamFromPackage.log | 2 + tests/ParamIndex/ParamIndex.log | 10 + tests/ParamMultiConcat/ParamMultiConcat.log | 2 + tests/ParamNoDefault/ParamNoDefault.log | 2 + tests/ParamNoImport/ParamNoImport.log | 2 + tests/ParamNoSubst/ParamNoSubst.log | 4 + tests/ParamOverload1/ParamOverload1.log | 6 + tests/ParamOverload2/ParamOverload2.log | 2 + tests/ParamOverloadProp/ParamOverloadProp.log | 2 + tests/ParamOverloading/ParamOverloading.log | 4 + tests/ParamRef/ParamRef.log | 4 + tests/ParamScope/ParamScope.log | 6 + tests/ParamTypespec2/ParamTypespec2.log | 2 + tests/PartSelect4/PartSelect4.log | 2 + tests/PortByName/PortByName.log | 2 + tests/PortDefaultValue/PortDefaultValue.log | 2 + tests/PortWildcard/PortWildcard.log | 2 + tests/PoundParam/PoundParam.log | 4 + tests/PreprocLine/PreprocLine.log | 60 +- tests/PrimTermExpr/PrimTermExpr.log | 56 +- tests/ScalarParam/ScalarParam.log | 2 + tests/SignedBin/SignedBin.log | 2 + tests/SplitFile/SplitFile.log | 2 +- tests/StringParameter/StringParameter.log | 2 + tests/StructArrayNet/StructArrayNet.log | 2 + tests/StructUnsizedVal/StructUnsizedVal.log | 6 + tests/StructVar/StructVar.log | 6 + tests/TaggedParam/TaggedParam.log | 2 + tests/TestSepCompNoHash/TestSepCompNoHash.log | 8 +- tests/TimeUnit/TimeUnit.log | 2 +- tests/TypeParam/TypeParam.log | 6 + tests/TypeParam2/TypeParam2.log | 2 + tests/TypeParamElab/TypeParamElab.log | 4 + tests/TypeParamOverride/TypeParamOverride.log | 2 + tests/TypespecExpr/TypespecExpr.log | 2 + tests/Udp/Udp.log | 2 +- tests/UhdmCoverage/UhdmCoverage.log | 2 + tests/UnitDefParam/UnitDefParam.log | 12 + tests/UnitElab/UnitElab.log | 18 +- .../UnitElabExternNested.log | 2 +- tests/UnitLibrary/UnitLibrary.log | 10 +- tests/UnsizedConstInst/UnsizedConstInst.log | 4 + tests/UnsizedParam/UnsizedParam.log | 4 + tests/WildConn/WildConn.log | 2 + third_party/UHDM | 2 +- third_party/antlr4 | 2 +- third_party/googletest | 2 +- .../tests/CoresSweRVMP/CoresSweRVMP.log | 58 +- .../tests/NyuziProcessor/NyuziProcessor.log | 322 +- .../SimpleParserTest/SimpleParserTest.log | 37 +- third_party/tests/Sky130Cell/Sky130Cell.log | 2940 +++++++++++++++++ third_party/tests/ariane/Ariane.log | 12 +- third_party/tests/oh/BasicOh.log | 604 ++-- 157 files changed, 4931 insertions(+), 857 deletions(-) diff --git a/include/Surelog/Design/ModuleDefinition.h b/include/Surelog/Design/ModuleDefinition.h index e01c9e3c84..e72826839c 100644 --- a/include/Surelog/Design/ModuleDefinition.h +++ b/include/Surelog/Design/ModuleDefinition.h @@ -103,6 +103,14 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder { void setRefModules(std::vector* modules) { m_ref_modules = modules; } + + UHDM::VectorOfprimitive* getPrimitives() { return m_subPrimitives; } + UHDM::VectorOfprimitive_array* getPrimitiveArrays() { return m_subPrimitiveArrays; } + UHDM::VectorOfgen_scope_array* getGenScopeArrays() { return m_subGenScopeArrays; } + + void setPrimitives(UHDM::VectorOfprimitive* primitives) { m_subPrimitives = primitives; } + void setPrimitiveArrays(UHDM::VectorOfprimitive_array* primitives) { m_subPrimitiveArrays = primitives; } + void setGenScpeArrays(UHDM::VectorOfgen_scope_array* gen_arrays) { m_subGenScopeArrays = gen_arrays; } private: const std::string m_name; @@ -115,6 +123,10 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder { UHDM::VectorOfattribute* attributes_ = nullptr; std::vector* m_moduleArrays = nullptr; std::vector* m_ref_modules = nullptr; + UHDM::VectorOfprimitive* m_subPrimitives = nullptr; + UHDM::VectorOfprimitive_array* m_subPrimitiveArrays = nullptr; + UHDM::VectorOfgen_scope_array* m_subGenScopeArrays = nullptr; + }; class ModuleDefinitionFactory { diff --git a/include/Surelog/DesignCompile/CompileHelper.h b/include/Surelog/DesignCompile/CompileHelper.h index 38ac17a728..654f0992de 100644 --- a/include/Surelog/DesignCompile/CompileHelper.h +++ b/include/Surelog/DesignCompile/CompileHelper.h @@ -429,12 +429,17 @@ class CompileHelper final { const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign); + uint32_t getBuiltinType(VObjectType type); + void compileLetDeclaration(DesignComponent* component, const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign); void compileInstantiation(ModuleDefinition* mod, const FileContent* fC, CompileDesign* compileDesign, NodeId id, ValuedComponentI* instance); + void compileGateInstantiation(ModuleDefinition* mod, const FileContent* fC, + CompileDesign* compileDesign, NodeId id, + ValuedComponentI* instance); void compileHighConn(ModuleDefinition* component, const FileContent* fC, CompileDesign* compileDesign, NodeId id, UHDM::VectorOfport* ports); diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index 3250f700ab..1bd9b0a059 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -2460,6 +2460,150 @@ void CompileHelper::compileInstantiation(ModuleDefinition* mod, } } + +uint32_t CompileHelper::getBuiltinType(VObjectType type) { + switch (type) { + case VObjectType::slNInpGate_And: + return vpiAndPrim; + case VObjectType::slNInpGate_Or: + return vpiOrPrim; + case VObjectType::slNInpGate_Nor: + return vpiNorPrim; + case VObjectType::slNInpGate_Nand: + return vpiNandPrim; + case VObjectType::slNInpGate_Xor: + return vpiXorPrim; + case VObjectType::slNInpGate_Xnor: + return vpiXnorPrim; + case VObjectType::slNOutGate_Buf: + return vpiBufPrim; + case VObjectType::slNOutGate_Not: + return vpiNotPrim; + case VObjectType::slPassEnSwitch_Tranif0: + return vpiTranif0Prim; + case VObjectType::slPassEnSwitch_Tranif1: + return vpiTranif1Prim; + case VObjectType::slPassEnSwitch_RTranif1: + return vpiRtranif1Prim; + case VObjectType::slPassEnSwitch_RTranif0: + return vpiRtranif0Prim; + case VObjectType::slPassSwitch_Tran: + return vpiTranPrim; + case VObjectType::slPassSwitch_RTran: + return vpiRtranPrim; + case VObjectType::slCmosSwitchType_Cmos: + return vpiCmosPrim; + case VObjectType::slCmosSwitchType_RCmos: + return vpiRcmosPrim; + case VObjectType::slEnableGateType_Bufif0: + return vpiBufif0Prim; + case VObjectType::slEnableGateType_Bufif1: + return vpiBufif1Prim; + case VObjectType::slEnableGateType_Notif0: + return vpiNotif0Prim; + case VObjectType::slEnableGateType_Notif1: + return vpiNotif1Prim; + case VObjectType::slMosSwitchType_NMos: + return vpiNmosPrim; + case VObjectType::slMosSwitchType_PMos: + return vpiPmosPrim; + case VObjectType::slMosSwitchType_RNMos: + return vpiRnmosPrim; + case VObjectType::slMosSwitchType_RPMos: + return vpiRpmosPrim; + case VObjectType::slPullup: + return vpiPullupPrim; + case VObjectType::slPulldown: + return vpiPulldownPrim; + default: + return 0; + } +} + +void CompileHelper::compileGateInstantiation(ModuleDefinition* mod, + const FileContent* fC, + CompileDesign* compileDesign, + NodeId id, + ValuedComponentI* instance) { + UHDM::Serializer& s = compileDesign->getSerializer(); + UHDM::primitive* gate = nullptr; + UHDM::primitive_array* gate_array = nullptr; + NodeId gatenode = fC->Child(fC->Parent(id)); + VObjectType gatetype = fC->Type(gatenode); + int32_t vpiGateType = getBuiltinType(gatetype); + NodeId Name_of_instance = fC->Child(id); + NodeId Name = fC->Child(Name_of_instance); + NodeId Unpacked_dimension = fC->Sibling(Name); + if (vpiGateType == vpiPmosPrim || vpiGateType == vpiRpmosPrim || + vpiGateType == vpiNmosPrim || vpiGateType == vpiRnmosPrim || + vpiGateType == vpiCmosPrim || vpiGateType == vpiRcmosPrim || + vpiGateType == vpiTranif1Prim || vpiGateType == vpiTranif0Prim || + vpiGateType == vpiRtranif1Prim || vpiGateType == vpiRtranif0Prim || + vpiGateType == vpiTranPrim || vpiGateType == vpiRtranPrim) { + gate = s.MakeSwitch_tran(); + if (fC->Type(Unpacked_dimension) == VObjectType::slUnpacked_dimension) { + gate_array = s.MakeSwitch_array(); + VectorOfprimitive* prims = s.MakePrimitiveVec(); + int32_t size; + VectorOfrange* ranges = + compileRanges(mod, fC, Unpacked_dimension, compileDesign, nullptr, + instance, false, size, false); + gate_array->Primitives(prims); + gate_array->Ranges(ranges); + prims->push_back(gate); + if (mod->getPrimitiveArrays() == nullptr) { + mod->setPrimitiveArrays(s.MakePrimitive_arrayVec()); + } + mod->getPrimitiveArrays()->push_back(gate_array); + } else { + if (mod->getPrimitives() == nullptr) { + mod->setPrimitives(s.MakePrimitiveVec()); + } + mod->getPrimitives()->push_back(gate); + } + gate->VpiPrimType(vpiGateType); + } else { + gate = s.MakeGate(); + if (fC->Type(Unpacked_dimension) == VObjectType::slUnpacked_dimension) { + gate_array = s.MakeGate_array(); + gate_array->VpiName(fC->SymName(Name)); + fC->populateCoreMembers(id, id, gate_array); + VectorOfprimitive* prims = s.MakePrimitiveVec(); + gate_array->Primitives(prims); + int32_t size; + VectorOfrange* ranges = + compileRanges(mod, fC, Unpacked_dimension, compileDesign, nullptr, + instance, false, size, false); + gate_array->Ranges(ranges); + prims->push_back(gate); + if (mod->getPrimitiveArrays() == nullptr) { + mod->setPrimitiveArrays(s.MakePrimitive_arrayVec()); + } + mod->getPrimitiveArrays()->push_back(gate_array); + } else { + if (mod->getPrimitives() == nullptr) { + mod->setPrimitives(s.MakePrimitiveVec()); + } + mod->getPrimitives()->push_back(gate); + } + + gate->VpiPrimType(vpiGateType); + } + /* + if (UHDM::VectorOfexpr* delays = child->getNetlist()->delays()) { + if (delays->size() == 1) { + gate->Delay((*delays)[0]); + } + } + */ + if (gate) { + gate->VpiName(fC->SymName(Name)); + // gate->VpiDefName(child->getModuleName()); + fC->populateCoreMembers(id, id, gate); + } + // writePrimTerms(child, gate, vpiGateType, s); +} + void CompileHelper::compileHighConn(ModuleDefinition* component, const FileContent* fC, CompileDesign* compileDesign, NodeId instId, diff --git a/src/DesignCompile/CompileModule.cpp b/src/DesignCompile/CompileModule.cpp index b6881f127b..4f447a60a5 100644 --- a/src/DesignCompile/CompileModule.cpp +++ b/src/DesignCompile/CompileModule.cpp @@ -768,8 +768,6 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) { } case VObjectType::slParam_assignment: case VObjectType::slHierarchical_instance: - case VObjectType::slN_input_gate_instance: - case VObjectType::slN_output_gate_instance: case VObjectType::slUdp_instance: case VObjectType::slUdp_instantiation: case VObjectType::slGate_instantiation: @@ -785,6 +783,15 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) { m_module->addObject(type, fnid); break; } + case VObjectType::slN_input_gate_instance: + case VObjectType::slN_output_gate_instance: { + if (collectType != CollectType::OTHER) break; + FileCNodeId fnid(fC, id); + m_module->addObject(type, fnid); + m_helper.compileGateInstantiation(m_module, fC, m_compileDesign, id, + m_instance); + break; + } case VObjectType::slInterface_instantiation: case VObjectType::slModule_instantiation: case VObjectType::slProgram_instantiation: { diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index d8055c271b..6abc61b368 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -1229,9 +1229,11 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m, } } // Module Instantiation - if (std::vector* subModules = mod->getRefModules()) { m->Ref_modules(subModules); + for (auto subModArr : *subModules) { + subModArr->VpiParent(m); + } } if (VectorOfmodule_array* subModuleArrays = mod->getModuleArrays()) { m->Module_arrays(subModuleArrays); @@ -1239,7 +1241,18 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m, subModArr->VpiParent(m); } } - + if (UHDM::VectorOfprimitive* subModules = mod->getPrimitives()) { + m->Primitives(subModules); + for (auto subModArr : *subModules) { + subModArr->VpiParent(m); + } + } + if (UHDM::VectorOfprimitive_array* subModules = mod->getPrimitiveArrays()) { + m->Primitive_arrays(subModules); + for (auto subModArr : *subModules) { + subModArr->VpiParent(m); + } + } // Interface instantiation const std::vector& signals = mod->getSignals(); if (!signals.empty()) { diff --git a/tests/ArianeElab/ArianeElab.log b/tests/ArianeElab/ArianeElab.log index af04e554c1..1487c7cb0e 100644 --- a/tests/ArianeElab/ArianeElab.log +++ b/tests/ArianeElab/ArianeElab.log @@ -97155,6 +97155,8 @@ design: (work@top) \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11 |vpiRefModule: \_ref_module: work@ex_stage (ex_stage_i), line:2064:9, endln:2064:19 + |vpiParent: + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10 |vpiName:ex_stage_i |vpiDefName:work@ex_stage |vpiActual: @@ -107616,6 +107618,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@ariane (i_ariane), line:2072:9, endln:2072:17 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10 |vpiName:i_ariane |vpiDefName:work@ariane |vpiActual: diff --git a/tests/ArianeElab2/ArianeElab2.log b/tests/ArianeElab2/ArianeElab2.log index ed18cb2249..88712b16a7 100644 --- a/tests/ArianeElab2/ArianeElab2.log +++ b/tests/ArianeElab2/ArianeElab2.log @@ -97787,6 +97787,8 @@ design: (work@top) \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11 |vpiRefModule: \_ref_module: work@ex_stage (ex_stage_i), line:2120:9, endln:2120:19 + |vpiParent: + \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10 |vpiName:ex_stage_i |vpiDefName:work@ex_stage |vpiActual: @@ -108539,6 +108541,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@ariane (i_ariane), line:2128:9, endln:2128:17 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10 |vpiName:i_ariane |vpiDefName:work@ariane |vpiActual: diff --git a/tests/ArrayExprFuncArg/ArrayExprFunArg.log b/tests/ArrayExprFuncArg/ArrayExprFunArg.log index 670a391629..7ab9cbcf9e 100644 --- a/tests/ArrayExprFuncArg/ArrayExprFunArg.log +++ b/tests/ArrayExprFuncArg/ArrayExprFunArg.log @@ -657,6 +657,8 @@ design: (work@main) |vpiDefName:work@main |vpiRefModule: \_ref_module: work@top (top1), line:47:9, endln:47:13 + |vpiParent: + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ArrayExprFuncArg/dut.sv, line:46:1, endln:48:10 |vpiName:top1 |vpiDefName:work@top |vpiActual: diff --git a/tests/AssignmentPatternInAssignmentPattern/AssignmentPatternInAssignmentPattern.log b/tests/AssignmentPatternInAssignmentPattern/AssignmentPatternInAssignmentPattern.log index 8263f01018..e6206bbed5 100644 --- a/tests/AssignmentPatternInAssignmentPattern/AssignmentPatternInAssignmentPattern.log +++ b/tests/AssignmentPatternInAssignmentPattern/AssignmentPatternInAssignmentPattern.log @@ -2384,6 +2384,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@foo (f), line:42:5, endln:42:6 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignmentPatternInAssignmentPattern/dut.sv, line:40:1, endln:44:10 |vpiName:f |vpiDefName:work@foo |vpiActual: diff --git a/tests/Attributes/Attributes.log b/tests/Attributes/Attributes.log index aa4f224215..51c4722a99 100644 --- a/tests/Attributes/Attributes.log +++ b/tests/Attributes/Attributes.log @@ -2144,6 +2144,8 @@ design: (work@foo) \_logic_net: ($37) |vpiRefModule: \_ref_module: work@bar (bar_instance), line:19:7, endln:19:19 + |vpiParent: + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10 |vpiName:bar_instance |vpiDefName:work@bar |vpiActual: diff --git a/tests/Attributes2/Attributes2.log b/tests/Attributes2/Attributes2.log index b4df24c220..1ab53fb9cd 100644 --- a/tests/Attributes2/Attributes2.log +++ b/tests/Attributes2/Attributes2.log @@ -948,6 +948,8 @@ design: (work@foo) \_logic_typespec: , line:9:28, endln:9:32 |vpiRefModule: \_ref_module: work@bar (bar_instance_1), line:11:7, endln:11:21 + |vpiParent: + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10 |vpiName:bar_instance_1 |vpiDefName:work@bar |vpiActual: diff --git a/tests/BindStmt/BindStmt.log b/tests/BindStmt/BindStmt.log index e0fe07a5e2..cc7ad4da66 100644 --- a/tests/BindStmt/BindStmt.log +++ b/tests/BindStmt/BindStmt.log @@ -669,6 +669,8 @@ design: (work@testbench) \_logic_net: (a) |vpiRefModule: \_ref_module: work@sub (sub1), line:10:7, endln:10:11 + |vpiParent: + \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10 |vpiName:sub1 |vpiDefName:work@sub |vpiActual: @@ -781,6 +783,8 @@ design: (work@testbench) \_logic_net: (work@testbench.u1.lce_tracer2.a), line:13:75, endln:13:76 |vpiRefModule: \_ref_module: work@sub (sub1), line:15:7, endln:15:11 + |vpiParent: + \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10 |vpiName:sub1 |vpiDefName:work@sub |vpiActual: @@ -793,6 +797,8 @@ design: (work@testbench) |vpiDefName:work@inter |vpiRefModule: \_ref_module: work@bp_lce (u1), line:21:23, endln:21:25 + |vpiParent: + \_module_inst: work@inter (work@inter), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:19:1, endln:23:10 |vpiName:u1 |vpiDefName:work@bp_lce |vpiActual: @@ -853,12 +859,16 @@ design: (work@testbench) \_logic_typespec: , line:25:25, endln:25:30 |vpiRefModule: \_ref_module: work@bp_lce (u1), line:27:24, endln:27:26 + |vpiParent: + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:u1 |vpiDefName:work@bp_lce |vpiActual: \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10 |vpiRefModule: \_ref_module: work@inter (tt), line:28:9, endln:28:11 + |vpiParent: + \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10 |vpiName:tt |vpiDefName:work@inter |vpiActual: diff --git a/tests/Bindings/Bindings.log b/tests/Bindings/Bindings.log index 233d5565ae..1f55191e85 100644 --- a/tests/Bindings/Bindings.log +++ b/tests/Bindings/Bindings.log @@ -2790,12 +2790,16 @@ design: (work@dut1) \_logic_net: (lockup) |vpiRefModule: \_ref_module: work@bsg_dff_reset (a1), line:56:32, endln:56:34 + |vpiParent: + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiName:a1 |vpiDefName:work@bsg_dff_reset |vpiActual: \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10 |vpiRefModule: \_ref_module: work@bsg_dff_reset (a2), line:58:17, endln:58:19 + |vpiParent: + \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10 |vpiName:a2 |vpiDefName:work@bsg_dff_reset |vpiActual: diff --git a/tests/BitsArray/BitsArray.log b/tests/BitsArray/BitsArray.log index d49c3cec6d..6138e0a6f8 100644 --- a/tests/BitsArray/BitsArray.log +++ b/tests/BitsArray/BitsArray.log @@ -392,6 +392,8 @@ design: (work@top) |vpiNetType:36 |vpiRefModule: \_ref_module: work@aes_reg_status (u_reg_status_key_init), line:17:6, endln:17:27 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10 |vpiName:u_reg_status_key_init |vpiDefName:work@aes_reg_status |vpiActual: diff --git a/tests/BitsHierPath/BitsHierPath.log b/tests/BitsHierPath/BitsHierPath.log index 272774a1ab..ebf14b1a3d 100644 --- a/tests/BitsHierPath/BitsHierPath.log +++ b/tests/BitsHierPath/BitsHierPath.log @@ -542,24 +542,32 @@ design: (work@top) \_struct_typespec: (pkg::struct_t), line:2:11, endln:2:17 |vpiRefModule: \_ref_module: work@dut (dut1), line:13:33, endln:13:37 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut1 |vpiDefName:work@dut |vpiActual: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 |vpiRefModule: \_ref_module: work@dut (dut2), line:14:31, endln:14:35 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut2 |vpiDefName:work@dut |vpiActual: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 |vpiRefModule: \_ref_module: work@dut (dut3), line:15:29, endln:15:33 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut3 |vpiDefName:work@dut |vpiActual: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:8:1, endln:9:10 |vpiRefModule: \_ref_module: work@dut (dut4), line:16:36, endln:16:40 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsHierPath/dut.sv, line:11:1, endln:17:10 |vpiName:dut4 |vpiDefName:work@dut |vpiActual: diff --git a/tests/BlackBox/BlackBox.log b/tests/BlackBox/BlackBox.log index 63f9f7650f..fe806f274e 100644 --- a/tests/BlackBox/BlackBox.log +++ b/tests/BlackBox/BlackBox.log @@ -278,6 +278,8 @@ design: (work@top) \_logic_net: (o) |vpiRefModule: \_ref_module: work@nyuzi (nyuzi), line:29:8, endln:29:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:nyuzi |vpiDefName:work@nyuzi |vpiActual: diff --git a/tests/BlackBox/BlackBoxInst.log b/tests/BlackBox/BlackBoxInst.log index dafdaf33c6..618fb81cfc 100644 --- a/tests/BlackBox/BlackBoxInst.log +++ b/tests/BlackBox/BlackBoxInst.log @@ -276,6 +276,8 @@ design: (work@top) \_logic_net: (o) |vpiRefModule: \_ref_module: work@nyuzi (nyuzi), line:29:8, endln:29:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:nyuzi |vpiDefName:work@nyuzi |vpiActual: diff --git a/tests/BlackBox/BlackBoxSubMod.log b/tests/BlackBox/BlackBoxSubMod.log index eb386abfac..4bc37296e0 100644 --- a/tests/BlackBox/BlackBoxSubMod.log +++ b/tests/BlackBox/BlackBoxSubMod.log @@ -268,6 +268,8 @@ design: (work@top) \_logic_net: (o) |vpiRefModule: \_ref_module: work@nyuzi (nyuzi), line:29:8, endln:29:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:25:1, endln:34:10 |vpiName:nyuzi |vpiDefName:work@nyuzi |vpiActual: diff --git a/tests/BlackParrotSkipParam/BlackParrotSkipParam.log b/tests/BlackParrotSkipParam/BlackParrotSkipParam.log index 51c139ee99..96853b5002 100644 --- a/tests/BlackParrotSkipParam/BlackParrotSkipParam.log +++ b/tests/BlackParrotSkipParam/BlackParrotSkipParam.log @@ -1019,6 +1019,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@bsg_counter_set_en (mtime_counter), line:14:2, endln:14:15 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BlackParrotSkipParam/dut.sv, line:9:1, endln:17:10 |vpiName:mtime_counter |vpiDefName:work@bsg_counter_set_en |vpiActual: diff --git a/tests/CarryTrans/CarryTrans.log b/tests/CarryTrans/CarryTrans.log index 96d8c45270..a7a92567c2 100644 --- a/tests/CarryTrans/CarryTrans.log +++ b/tests/CarryTrans/CarryTrans.log @@ -854,7 +854,7 @@ enum_const 5 enum_typespec 1 enum_var 1 function 9 -gate 4 +gate 8 int_typespec 9 int_var 4 io_decl 11 @@ -883,7 +883,7 @@ enum_const 10 enum_typespec 2 enum_var 1 function 18 -gate 4 +gate 12 int_typespec 9 int_var 4 io_decl 22 @@ -894,9 +894,9 @@ module_inst 7 operation 15 package 2 port 85 -prim_term 49 -ref_obj 106 -switch_tran 12 +prim_term 98 +ref_obj 155 +switch_tran 24 task 18 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/CarryTrans/slpp_all/surelog.uhdm ... @@ -1485,6 +1485,34 @@ design: (work@carry_rtl) \_logic_net: (work@carry_gate.cout), line:9:12, endln:9:16 |vpiTypedef: \_logic_typespec: , line:9:12, endln:9:12 + |vpiPrimitive: + \_gate: (work@carry_gate.g1), line:12:5, endln:12:16 + |vpiParent: + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + |vpiName:g1 + |vpiFullName:work@carry_gate.g1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@carry_gate.g2), line:13:5, endln:13:16 + |vpiParent: + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + |vpiName:g2 + |vpiFullName:work@carry_gate.g2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@carry_gate.g3), line:14:5, endln:14:16 + |vpiParent: + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + |vpiName:g3 + |vpiFullName:work@carry_gate.g3 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@carry_gate.g4), line:15:4, endln:15:21 + |vpiParent: + \_module_inst: work@carry_gate (work@carry_gate), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:8:1, endln:16:10 + |vpiName:g4 + |vpiFullName:work@carry_gate.g4 + |vpiPrimType:4 |uhdmallModules: \_module_inst: work@carry_rtl (work@carry_rtl), file:${SURELOG_DIR}/tests/CarryTrans/dut.sv, line:1:1, endln:5:10 |vpiParent: @@ -2123,7 +2151,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.x), line:12:8, endln:12:9 |vpiParent: - \_gate: work@and (work@carry_gate.g1), line:12:5, endln:12:16 + \_prim_term: , line:12:8, endln:12:9 |vpiName:x |vpiFullName:work@carry_gate.x |vpiActual: @@ -2137,7 +2165,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.a), line:12:11, endln:12:12 |vpiParent: - \_gate: work@and (work@carry_gate.g1), line:12:5, endln:12:16 + \_prim_term: , line:12:11, endln:12:12 |vpiName:a |vpiFullName:work@carry_gate.a |vpiActual: @@ -2151,7 +2179,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.b), line:12:14, endln:12:15 |vpiParent: - \_gate: work@and (work@carry_gate.g1), line:12:5, endln:12:16 + \_prim_term: , line:12:14, endln:12:15 |vpiName:b |vpiFullName:work@carry_gate.b |vpiActual: @@ -2172,7 +2200,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.y), line:13:8, endln:13:9 |vpiParent: - \_gate: work@and (work@carry_gate.g2), line:13:5, endln:13:16 + \_prim_term: , line:13:8, endln:13:9 |vpiName:y |vpiFullName:work@carry_gate.y |vpiActual: @@ -2186,7 +2214,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.a), line:13:11, endln:13:12 |vpiParent: - \_gate: work@and (work@carry_gate.g2), line:13:5, endln:13:16 + \_prim_term: , line:13:11, endln:13:12 |vpiName:a |vpiFullName:work@carry_gate.a |vpiActual: @@ -2200,7 +2228,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.c), line:13:14, endln:13:15 |vpiParent: - \_gate: work@and (work@carry_gate.g2), line:13:5, endln:13:16 + \_prim_term: , line:13:14, endln:13:15 |vpiName:c |vpiFullName:work@carry_gate.c |vpiActual: @@ -2221,7 +2249,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.z), line:14:8, endln:14:9 |vpiParent: - \_gate: work@and (work@carry_gate.g3), line:14:5, endln:14:16 + \_prim_term: , line:14:8, endln:14:9 |vpiName:z |vpiFullName:work@carry_gate.z |vpiActual: @@ -2235,7 +2263,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.b), line:14:11, endln:14:12 |vpiParent: - \_gate: work@and (work@carry_gate.g3), line:14:5, endln:14:16 + \_prim_term: , line:14:11, endln:14:12 |vpiName:b |vpiFullName:work@carry_gate.b |vpiActual: @@ -2249,7 +2277,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.c), line:14:14, endln:14:15 |vpiParent: - \_gate: work@and (work@carry_gate.g3), line:14:5, endln:14:16 + \_prim_term: , line:14:14, endln:14:15 |vpiName:c |vpiFullName:work@carry_gate.c |vpiActual: @@ -2270,7 +2298,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.cout), line:15:7, endln:15:11 |vpiParent: - \_gate: work@or (work@carry_gate.g4), line:15:4, endln:15:21 + \_prim_term: , line:15:7, endln:15:11 |vpiName:cout |vpiFullName:work@carry_gate.cout |vpiActual: @@ -2284,7 +2312,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.x), line:15:13, endln:15:14 |vpiParent: - \_gate: work@or (work@carry_gate.g4), line:15:4, endln:15:21 + \_prim_term: , line:15:13, endln:15:14 |vpiName:x |vpiFullName:work@carry_gate.x |vpiActual: @@ -2298,7 +2326,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.y), line:15:16, endln:15:17 |vpiParent: - \_gate: work@or (work@carry_gate.g4), line:15:4, endln:15:21 + \_prim_term: , line:15:16, endln:15:17 |vpiName:y |vpiFullName:work@carry_gate.y |vpiActual: @@ -2312,7 +2340,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_gate.z), line:15:19, endln:15:20 |vpiParent: - \_gate: work@or (work@carry_gate.g4), line:15:4, endln:15:21 + \_prim_term: , line:15:19, endln:15:20 |vpiName:z |vpiFullName:work@carry_gate.z |vpiActual: @@ -2536,7 +2564,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i1), line:25:12, endln:25:14 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n1), line:25:9, endln:25:23 + \_prim_term: , line:25:12, endln:25:14 |vpiName:i1 |vpiFullName:work@carry_trans.i1 |vpiActual: @@ -2550,7 +2578,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.zero), line:25:15, endln:25:19 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n1), line:25:9, endln:25:23 + \_prim_term: , line:25:15, endln:25:19 |vpiName:zero |vpiFullName:work@carry_trans.zero |vpiActual: @@ -2564,7 +2592,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.a), line:25:21, endln:25:22 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n1), line:25:9, endln:25:23 + \_prim_term: , line:25:21, endln:25:22 |vpiName:a |vpiFullName:work@carry_trans.a |vpiActual: @@ -2585,7 +2613,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i1), line:26:12, endln:26:14 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n2), line:26:9, endln:26:24 + \_prim_term: , line:26:12, endln:26:14 |vpiName:i1 |vpiFullName:work@carry_trans.i1 |vpiActual: @@ -2599,7 +2627,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.zero), line:26:16, endln:26:20 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n2), line:26:9, endln:26:24 + \_prim_term: , line:26:16, endln:26:20 |vpiName:zero |vpiFullName:work@carry_trans.zero |vpiActual: @@ -2613,7 +2641,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.b), line:26:22, endln:26:23 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n2), line:26:9, endln:26:24 + \_prim_term: , line:26:22, endln:26:23 |vpiName:b |vpiFullName:work@carry_trans.b |vpiActual: @@ -2634,7 +2662,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cn), line:27:12, endln:27:14 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n3), line:27:9, endln:27:22 + \_prim_term: , line:27:12, endln:27:14 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiActual: @@ -2648,7 +2676,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i1), line:27:16, endln:27:18 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n3), line:27:9, endln:27:22 + \_prim_term: , line:27:16, endln:27:18 |vpiName:i1 |vpiFullName:work@carry_trans.i1 |vpiActual: @@ -2662,7 +2690,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.c), line:27:20, endln:27:21 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n3), line:27:9, endln:27:22 + \_prim_term: , line:27:20, endln:27:21 |vpiName:c |vpiFullName:work@carry_trans.c |vpiActual: @@ -2683,7 +2711,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i2), line:28:12, endln:28:14 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n4), line:28:9, endln:28:24 + \_prim_term: , line:28:12, endln:28:14 |vpiName:i2 |vpiFullName:work@carry_trans.i2 |vpiActual: @@ -2697,7 +2725,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.zero), line:28:16, endln:28:20 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n4), line:28:9, endln:28:24 + \_prim_term: , line:28:16, endln:28:20 |vpiName:zero |vpiFullName:work@carry_trans.zero |vpiActual: @@ -2711,7 +2739,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.b), line:28:22, endln:28:23 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n4), line:28:9, endln:28:24 + \_prim_term: , line:28:22, endln:28:23 |vpiName:b |vpiFullName:work@carry_trans.b |vpiActual: @@ -2732,7 +2760,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cn), line:29:12, endln:29:14 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n5), line:29:9, endln:29:22 + \_prim_term: , line:29:12, endln:29:14 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiActual: @@ -2746,7 +2774,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i2), line:29:16, endln:29:18 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n5), line:29:9, endln:29:22 + \_prim_term: , line:29:16, endln:29:18 |vpiName:i2 |vpiFullName:work@carry_trans.i2 |vpiActual: @@ -2760,7 +2788,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.a), line:29:20, endln:29:21 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n5), line:29:9, endln:29:22 + \_prim_term: , line:29:20, endln:29:21 |vpiName:a |vpiFullName:work@carry_trans.a |vpiActual: @@ -2781,7 +2809,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i3), line:30:12, endln:30:14 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p1), line:30:9, endln:30:23 + \_prim_term: , line:30:12, endln:30:14 |vpiName:i3 |vpiFullName:work@carry_trans.i3 |vpiActual: @@ -2795,7 +2823,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.one), line:30:16, endln:30:19 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p1), line:30:9, endln:30:23 + \_prim_term: , line:30:16, endln:30:19 |vpiName:one |vpiFullName:work@carry_trans.one |vpiActual: @@ -2809,7 +2837,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.a), line:30:21, endln:30:22 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p1), line:30:9, endln:30:23 + \_prim_term: , line:30:21, endln:30:22 |vpiName:a |vpiFullName:work@carry_trans.a |vpiActual: @@ -2830,7 +2858,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i3), line:31:12, endln:31:14 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p2), line:31:9, endln:31:23 + \_prim_term: , line:31:12, endln:31:14 |vpiName:i3 |vpiFullName:work@carry_trans.i3 |vpiActual: @@ -2844,7 +2872,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.one), line:31:16, endln:31:19 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p2), line:31:9, endln:31:23 + \_prim_term: , line:31:16, endln:31:19 |vpiName:one |vpiFullName:work@carry_trans.one |vpiActual: @@ -2858,7 +2886,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.b), line:31:21, endln:31:22 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p2), line:31:9, endln:31:23 + \_prim_term: , line:31:21, endln:31:22 |vpiName:b |vpiFullName:work@carry_trans.b |vpiActual: @@ -2879,7 +2907,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cn), line:32:12, endln:32:14 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p3), line:32:9, endln:32:22 + \_prim_term: , line:32:12, endln:32:14 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiActual: @@ -2893,7 +2921,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i3), line:32:16, endln:32:18 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p3), line:32:9, endln:32:22 + \_prim_term: , line:32:16, endln:32:18 |vpiName:i3 |vpiFullName:work@carry_trans.i3 |vpiActual: @@ -2907,7 +2935,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.c), line:32:20, endln:32:21 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p3), line:32:9, endln:32:22 + \_prim_term: , line:32:20, endln:32:21 |vpiName:c |vpiFullName:work@carry_trans.c |vpiActual: @@ -2928,7 +2956,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i4), line:33:12, endln:33:14 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p4), line:33:9, endln:33:23 + \_prim_term: , line:33:12, endln:33:14 |vpiName:i4 |vpiFullName:work@carry_trans.i4 |vpiActual: @@ -2942,7 +2970,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.one), line:33:16, endln:33:19 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p4), line:33:9, endln:33:23 + \_prim_term: , line:33:16, endln:33:19 |vpiName:one |vpiFullName:work@carry_trans.one |vpiActual: @@ -2956,7 +2984,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.b), line:33:21, endln:33:22 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p4), line:33:9, endln:33:23 + \_prim_term: , line:33:21, endln:33:22 |vpiName:b |vpiFullName:work@carry_trans.b |vpiActual: @@ -2977,7 +3005,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cn), line:34:12, endln:34:14 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p5), line:34:9, endln:34:22 + \_prim_term: , line:34:12, endln:34:14 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiActual: @@ -2991,7 +3019,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.i4), line:34:16, endln:34:18 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p5), line:34:9, endln:34:22 + \_prim_term: , line:34:16, endln:34:18 |vpiName:i4 |vpiFullName:work@carry_trans.i4 |vpiActual: @@ -3005,7 +3033,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.a), line:34:20, endln:34:21 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p5), line:34:9, endln:34:22 + \_prim_term: , line:34:20, endln:34:21 |vpiName:a |vpiFullName:work@carry_trans.a |vpiActual: @@ -3026,7 +3054,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cout), line:35:12, endln:35:16 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n6), line:35:9, endln:35:27 + \_prim_term: , line:35:12, endln:35:16 |vpiName:cout |vpiFullName:work@carry_trans.cout |vpiActual: @@ -3040,7 +3068,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.zero), line:35:18, endln:35:22 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n6), line:35:9, endln:35:27 + \_prim_term: , line:35:18, endln:35:22 |vpiName:zero |vpiFullName:work@carry_trans.zero |vpiActual: @@ -3054,7 +3082,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cn), line:35:24, endln:35:26 |vpiParent: - \_switch_tran: work@tranif1 (work@carry_trans.n6), line:35:9, endln:35:27 + \_prim_term: , line:35:24, endln:35:26 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiActual: @@ -3075,7 +3103,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cout), line:36:12, endln:36:16 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p6), line:36:9, endln:36:26 + \_prim_term: , line:36:12, endln:36:16 |vpiName:cout |vpiFullName:work@carry_trans.cout |vpiActual: @@ -3089,7 +3117,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.one), line:36:18, endln:36:21 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p6), line:36:9, endln:36:26 + \_prim_term: , line:36:18, endln:36:21 |vpiName:one |vpiFullName:work@carry_trans.one |vpiActual: @@ -3103,7 +3131,7 @@ design: (work@carry_rtl) |vpiExpr: \_ref_obj: (work@carry_trans.cn), line:36:23, endln:36:25 |vpiParent: - \_switch_tran: work@tranif0 (work@carry_trans.p6), line:36:9, endln:36:26 + \_prim_term: , line:36:23, endln:36:25 |vpiName:cn |vpiFullName:work@carry_trans.cn |vpiActual: diff --git a/tests/Cell/Cell.log b/tests/Cell/Cell.log index b834146839..213e881643 100644 --- a/tests/Cell/Cell.log +++ b/tests/Cell/Cell.log @@ -651,6 +651,8 @@ design: (work@top) |vpiCellInstance:1 |vpiRefModule: \_ref_module: work@assigner (asgn), line:9:32, endln:9:36 + |vpiParent: + \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 |vpiName:asgn |vpiDefName:work@assigner |vpiActual: @@ -663,12 +665,16 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@middleman (mdl1), line:2:28, endln:2:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 |vpiName:mdl1 |vpiDefName:work@middleman |vpiActual: \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/Cell/cell.v, line:8:1, endln:10:10 |vpiRefModule: \_ref_module: work@middleman (mdl0), line:3:28, endln:3:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Cell/dut.sv, line:1:1, endln:4:10 |vpiName:mdl0 |vpiDefName:work@middleman |vpiActual: diff --git a/tests/ClogParam/ClogParam.log b/tests/ClogParam/ClogParam.log index 86df9cbae0..663fec41fc 100644 --- a/tests/ClogParam/ClogParam.log +++ b/tests/ClogParam/ClogParam.log @@ -467,6 +467,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@otp_ctrl_ecc_reg (u_otp_ctrl_ecc_reg), line:17:6, endln:17:24 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClogParam/dut.sv, line:7:1, endln:19:16 |vpiName:u_otp_ctrl_ecc_reg |vpiDefName:work@otp_ctrl_ecc_reg |vpiActual: diff --git a/tests/ComplexParamOverload/ComplexParamOverload.log b/tests/ComplexParamOverload/ComplexParamOverload.log index 48c77e4184..8132929b0c 100644 --- a/tests/ComplexParamOverload/ComplexParamOverload.log +++ b/tests/ComplexParamOverload/ComplexParamOverload.log @@ -766,6 +766,8 @@ design: (work@top) |vpiDefName:work@almost_top |vpiRefModule: \_ref_module: work@prim_pad_attr (u_prim_pad_attr), line:60:6, endln:60:21 + |vpiParent: + \_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:54:1, endln:63:10 |vpiName:u_prim_pad_attr |vpiDefName:work@prim_pad_attr |vpiActual: @@ -893,6 +895,8 @@ design: (work@top) |vpiDefName:work@prim_pad_attr |vpiRefModule: \_ref_module: work@prim_submodule (u_submodule), line:49:6, endln:49:17 + |vpiParent: + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:42:1, endln:52:10 |vpiName:u_submodule |vpiDefName:work@prim_submodule |vpiActual: @@ -932,6 +936,8 @@ design: (work@top) |vpiDefName:work@prim_submodule |vpiRefModule: \_ref_module: work@prim_generic (u_impl_generic), line:37:6, endln:37:20 + |vpiParent: + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:32:1, endln:40:10 |vpiName:u_impl_generic |vpiDefName:work@prim_generic |vpiActual: @@ -981,6 +987,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@almost_top (u_top), line:71:6, endln:71:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload/dut.sv, line:65:1, endln:74:10 |vpiName:u_top |vpiDefName:work@almost_top |vpiActual: diff --git a/tests/ComplexParamOverload2/ComplexParamOverload2.log b/tests/ComplexParamOverload2/ComplexParamOverload2.log index e50c170090..192b066720 100644 --- a/tests/ComplexParamOverload2/ComplexParamOverload2.log +++ b/tests/ComplexParamOverload2/ComplexParamOverload2.log @@ -647,6 +647,8 @@ design: (work@top) |vpiDefName:work@almost_top |vpiRefModule: \_ref_module: work@prim_pad_attr (u_prim_pad_attr), line:52:6, endln:52:21 + |vpiParent: + \_module_inst: work@almost_top (work@almost_top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:46:1, endln:55:10 |vpiName:u_prim_pad_attr |vpiDefName:work@prim_pad_attr |vpiActual: @@ -756,6 +758,8 @@ design: (work@top) |vpiDefName:work@prim_pad_attr |vpiRefModule: \_ref_module: work@prim_submodule (u_submodule), line:40:6, endln:40:17 + |vpiParent: + \_module_inst: work@prim_pad_attr (work@prim_pad_attr), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:35:1, endln:44:10 |vpiName:u_submodule |vpiDefName:work@prim_submodule |vpiActual: @@ -822,6 +826,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@prim_generic_pad_attr (u_impl_generic), line:29:6, endln:29:20 + |vpiParent: + \_module_inst: work@prim_submodule (work@prim_submodule), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:24:1, endln:32:10 |vpiName:u_impl_generic |vpiDefName:work@prim_generic_pad_attr |vpiActual: @@ -875,6 +881,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@almost_top (u_top), line:63:6, endln:63:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ComplexParamOverload2/dut.sv, line:57:1, endln:66:10 |vpiName:u_top |vpiDefName:work@almost_top |vpiActual: diff --git a/tests/Connection/Connection.log b/tests/Connection/Connection.log index e17c77f2a0..8a68846584 100644 --- a/tests/Connection/Connection.log +++ b/tests/Connection/Connection.log @@ -615,6 +615,8 @@ design: (work@top) \_logic_typespec: , line:1:18, endln:1:18 |vpiRefModule: \_ref_module: work@ibex_csr (u_mie_csr), line:3:6, endln:3:15 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Connection/dut.sv, line:1:1, endln:10:10 |vpiName:u_mie_csr |vpiDefName:work@ibex_csr |vpiActual: diff --git a/tests/ConstHighConn/ConstHighConn.log b/tests/ConstHighConn/ConstHighConn.log index c612967334..c78fbae7c5 100644 --- a/tests/ConstHighConn/ConstHighConn.log +++ b/tests/ConstHighConn/ConstHighConn.log @@ -201,6 +201,8 @@ design: (work@top) \_logic_typespec: , line:5:20, endln:5:25 |vpiRefModule: \_ref_module: work@dut (d), line:7:8, endln:7:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ConstHighConn/dut.sv, line:5:1, endln:9:10 |vpiName:d |vpiDefName:work@dut |vpiActual: diff --git a/tests/ConstPort/ConstPort.log b/tests/ConstPort/ConstPort.log index d269841620..65b3b519ba 100644 --- a/tests/ConstPort/ConstPort.log +++ b/tests/ConstPort/ConstPort.log @@ -163,6 +163,8 @@ design: (work@cipher_core) \_enum_typespec: (aes_pkg::ciph_op_e), line:2:1, endln:5:13 |vpiRefModule: \_ref_module: work@mix_columns (key_mix_columns), line:17:15, endln:17:30 + |vpiParent: + \_module_inst: work@cipher_core (work@cipher_core), file:${SURELOG_DIR}/tests/ConstPort/dut.sv, line:13:1, endln:20:10 |vpiName:key_mix_columns |vpiDefName:work@mix_columns |vpiActual: diff --git a/tests/CovMacro/CovMacro.log b/tests/CovMacro/CovMacro.log index c16dff6682..0635b21c2e 100644 --- a/tests/CovMacro/CovMacro.log +++ b/tests/CovMacro/CovMacro.log @@ -1774,12 +1774,16 @@ design: (work@top) \_real_var: (work@top.r), line:7:10, endln:7:11 |vpiRefModule: \_ref_module: work@DUT (unit1), line:8:9, endln:8:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:unit1 |vpiDefName:work@DUT |vpiActual: \_module_inst: work@DUT (work@DUT), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:2:1, endln:3:10 |vpiRefModule: \_ref_module: work@DUT (unit2), line:9:9, endln:9:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 |vpiName:unit2 |vpiDefName:work@DUT |vpiActual: diff --git a/tests/DefParamFromParam/DefParamFromParam.log b/tests/DefParamFromParam/DefParamFromParam.log index f85db56972..5c110df30c 100644 --- a/tests/DefParamFromParam/DefParamFromParam.log +++ b/tests/DefParamFromParam/DefParamFromParam.log @@ -261,6 +261,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@fifo (fifo_inst), line:10:10, endln:10:19 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefParamFromParam/dut.sv, line:6:1, endln:13:10 |vpiName:fifo_inst |vpiDefName:work@fifo |vpiActual: diff --git a/tests/DefaultAssign/DefaultAssign.log b/tests/DefaultAssign/DefaultAssign.log index ec06fd480d..40a310097c 100644 --- a/tests/DefaultAssign/DefaultAssign.log +++ b/tests/DefaultAssign/DefaultAssign.log @@ -310,6 +310,8 @@ design: (work@dut) \_logic_var: (work@dut.data), line:6:14, endln:6:18 |vpiRefModule: \_ref_module: work@foo (f), line:12:5, endln:12:6 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DefaultAssign/dut.sv, line:4:1, endln:14:10 |vpiName:f |vpiDefName:work@foo |vpiActual: diff --git a/tests/DefaultNetType/DefaultNetType.log b/tests/DefaultNetType/DefaultNetType.log index d07315c8c1..efb440d685 100644 --- a/tests/DefaultNetType/DefaultNetType.log +++ b/tests/DefaultNetType/DefaultNetType.log @@ -834,6 +834,8 @@ design: (work@ok) |vpiAlwaysType:2 |vpiRefModule: \_ref_module: work@M1 (m1), line:47:4, endln:47:6 + |vpiParent: + \_module_inst: work@bad2 (work@bad2), file:${SURELOG_DIR}/tests/DefaultNetType/dut.sv, line:28:1, endln:49:10 |vpiName:m1 |vpiDefName:work@M1 |vpiActual: diff --git a/tests/DefaultPatternAssign/DefaultPatternAssign.log b/tests/DefaultPatternAssign/DefaultPatternAssign.log index 5fdad13a14..b445b5da07 100644 --- a/tests/DefaultPatternAssign/DefaultPatternAssign.log +++ b/tests/DefaultPatternAssign/DefaultPatternAssign.log @@ -502,6 +502,8 @@ design: (work@top) |vpiDefName:work@lower |vpiRefModule: \_ref_module: work@bottom (bottom_u), line:14:5, endln:14:13 + |vpiParent: + \_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/DefaultPatternAssign/dut.sv, line:9:1, endln:15:10 |vpiName:bottom_u |vpiDefName:work@bottom |vpiActual: @@ -541,6 +543,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@upper (upper_u), line:24:9, endln:24:16 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DefaultPatternAssign/dut.sv, line:22:1, endln:25:10 |vpiName:upper_u |vpiDefName:work@upper |vpiActual: @@ -580,6 +584,8 @@ design: (work@top) |vpiDefName:work@upper |vpiRefModule: \_ref_module: work@lower (lower_u), line:19:9, endln:19:16 + |vpiParent: + \_module_inst: work@upper (work@upper), file:${SURELOG_DIR}/tests/DefaultPatternAssign/dut.sv, line:17:1, endln:20:10 |vpiName:lower_u |vpiDefName:work@lower |vpiActual: diff --git a/tests/DefaultPatternInt/DefaultPatternInt.log b/tests/DefaultPatternInt/DefaultPatternInt.log index 1ca5dcd5f9..61ead87e85 100644 --- a/tests/DefaultPatternInt/DefaultPatternInt.log +++ b/tests/DefaultPatternInt/DefaultPatternInt.log @@ -689,6 +689,8 @@ design: (work@main) |vpiDefName:work@main |vpiRefModule: \_ref_module: work@top (top1), line:33:9, endln:33:13 + |vpiParent: + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/DefaultPatternInt/dut.sv, line:32:1, endln:34:10 |vpiName:top1 |vpiDefName:work@top |vpiActual: diff --git a/tests/DefaultPatternModule/DefaultPatternModule.log b/tests/DefaultPatternModule/DefaultPatternModule.log index 67e16012c6..eb0f62fb5f 100644 --- a/tests/DefaultPatternModule/DefaultPatternModule.log +++ b/tests/DefaultPatternModule/DefaultPatternModule.log @@ -469,6 +469,8 @@ design: (work@main) |vpiDefName:work@main |vpiRefModule: \_ref_module: work@top (top1), line:30:9, endln:30:13 + |vpiParent: + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/DefaultPatternModule/dut.sv, line:29:1, endln:31:10 |vpiName:top1 |vpiDefName:work@top |vpiActual: diff --git a/tests/Delay2Param/Delay2Param.log b/tests/Delay2Param/Delay2Param.log index 908e6eb912..865963613e 100644 --- a/tests/Delay2Param/Delay2Param.log +++ b/tests/Delay2Param/Delay2Param.log @@ -467,7 +467,7 @@ range 6 ref_obj 23 sys_func_call 3 table_entry 2 -udp 1 +udp 2 udp_defn 1 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Delay2Param/slpp_all/surelog.uhdm ... diff --git a/tests/DollarBits/DollarBits.log b/tests/DollarBits/DollarBits.log index 177448c258..468af06569 100644 --- a/tests/DollarBits/DollarBits.log +++ b/tests/DollarBits/DollarBits.log @@ -334,6 +334,8 @@ design: (work@dut) |vpiConstType:9 |vpiRefModule: \_ref_module: work@other (oth), line:8:33, endln:8:36 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/DollarBits/dut.sv, line:7:1, endln:9:10 |vpiName:oth |vpiDefName:work@other |vpiActual: diff --git a/tests/DoublePres/DoublePres.log b/tests/DoublePres/DoublePres.log index 3584f67267..fa8b889a22 100644 --- a/tests/DoublePres/DoublePres.log +++ b/tests/DoublePres/DoublePres.log @@ -1929,6 +1929,8 @@ design: (work@top) \_logic_typespec: , line:1:32, endln:1:32 |vpiRefModule: \_ref_module: work@dut (d), line:3:37, endln:3:38 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DoublePres/dut.sv, line:1:1, endln:6:10 |vpiName:d |vpiDefName:work@dut |vpiActual: diff --git a/tests/EarlgreyPackParam/EarlgreyPackParam.log b/tests/EarlgreyPackParam/EarlgreyPackParam.log index bdeea70971..39a0e73420 100644 --- a/tests/EarlgreyPackParam/EarlgreyPackParam.log +++ b/tests/EarlgreyPackParam/EarlgreyPackParam.log @@ -806,6 +806,8 @@ design: (work@test) |vpiDefName:work@prim_alert_sender |vpiRefModule: \_ref_module: work@prim_diff_decode (dec_ack), line:21:5, endln:21:12 + |vpiParent: + \_module_inst: work@prim_alert_sender (work@prim_alert_sender), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:13:1, endln:26:11 |vpiName:dec_ack |vpiDefName:work@prim_diff_decode |vpiActual: @@ -887,6 +889,8 @@ design: (work@test) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@aes (u_aes), line:45:4, endln:45:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:41:1, endln:47:10 |vpiName:u_aes |vpiDefName:work@aes |vpiActual: diff --git a/tests/ElabCParam/ElabCParam.log b/tests/ElabCParam/ElabCParam.log index bdf7b934c9..c35f173ec0 100644 --- a/tests/ElabCParam/ElabCParam.log +++ b/tests/ElabCParam/ElabCParam.log @@ -1670,6 +1670,8 @@ design: (work@socket_1n) |vpiDefName:work@fifo_sync |vpiRefModule: \_ref_module: work@prim_fifo_sync (reqfifo), line:30:38, endln:30:45 + |vpiParent: + \_module_inst: work@fifo_sync (work@fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:24:1, endln:33:10 |vpiName:reqfifo |vpiDefName:work@prim_fifo_sync |vpiActual: diff --git a/tests/ElabIf/ElabIf.log b/tests/ElabIf/ElabIf.log index 9b2e038449..a50a0fa667 100644 --- a/tests/ElabIf/ElabIf.log +++ b/tests/ElabIf/ElabIf.log @@ -645,6 +645,8 @@ design: (work@top) |vpiDefName:work@middleman |vpiRefModule: \_ref_module: work@assigner (asgn), line:14:32, endln:14:36 + |vpiParent: + \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 |vpiName:asgn |vpiDefName:work@assigner |vpiActual: @@ -657,12 +659,16 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@middleman (mdl1), line:2:28, endln:2:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 |vpiName:mdl1 |vpiDefName:work@middleman |vpiActual: \_module_inst: work@middleman (work@middleman), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:13:1, endln:15:10 |vpiRefModule: \_ref_module: work@middleman (mdl0), line:3:28, endln:3:32 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ElabIf/dut.sv, line:1:1, endln:4:10 |vpiName:mdl0 |vpiDefName:work@middleman |vpiActual: diff --git a/tests/EmptyAssign/EmptyAssign.log b/tests/EmptyAssign/EmptyAssign.log index eead611b49..fef8cb6f8d 100644 --- a/tests/EmptyAssign/EmptyAssign.log +++ b/tests/EmptyAssign/EmptyAssign.log @@ -402,6 +402,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (dut), line:15:27, endln:15:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EmptyAssign/dut.sv, line:13:1, endln:17:10 |vpiName:dut |vpiDefName:work@dut |vpiActual: diff --git a/tests/EnumConstElab/EnumConstElab.log b/tests/EnumConstElab/EnumConstElab.log index 5ff6c8ce9e..61237b0f5d 100644 --- a/tests/EnumConstElab/EnumConstElab.log +++ b/tests/EnumConstElab/EnumConstElab.log @@ -618,6 +618,8 @@ design: (work@top) |vpiDefName:work@prim_subreg_shadow |vpiRefModule: \_ref_module: work@prim_subreg (staged_reg), line:23:6, endln:23:16 + |vpiParent: + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:6:1, endln:24:10 |vpiName:staged_reg |vpiDefName:work@prim_subreg |vpiActual: @@ -778,6 +780,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_subreg_shadow (u_ctrl_reg_shadowed), line:43:6, endln:43:25 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/EnumConstElab/dut.sv, line:26:1, endln:44:10 |vpiName:u_ctrl_reg_shadowed |vpiDefName:work@prim_subreg_shadow |vpiActual: diff --git a/tests/Escape/Escape.log b/tests/Escape/Escape.log index c168b1de1d..87ef4689e6 100644 --- a/tests/Escape/Escape.log +++ b/tests/Escape/Escape.log @@ -101,7 +101,7 @@ enum_typespec 1 enum_var 1 event_control 1 function 10 -gate 1 +gate 2 immediate_assert 1 int_typespec 9 int_var 4 diff --git a/tests/FSMBsp13/FSMBsp13.log b/tests/FSMBsp13/FSMBsp13.log index c693dca7fc..8cfc27fedc 100644 --- a/tests/FSMBsp13/FSMBsp13.log +++ b/tests/FSMBsp13/FSMBsp13.log @@ -16112,6 +16112,8 @@ design: (work@top) \_logic_net: (work@top.keys), line:5:5, endln:5:9 |vpiRefModule: \_ref_module: work@FSM1 (F1), line:11:6, endln:11:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:F1 |vpiDefName:work@FSM1 |vpiActual: @@ -16158,6 +16160,8 @@ design: (work@top) \_logic_net: (work@top.wr), line:7:10, endln:7:12 |vpiRefModule: \_ref_module: work@FSM2 (F2), line:17:6, endln:17:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:F2 |vpiDefName:work@FSM2 |vpiActual: @@ -16196,6 +16200,8 @@ design: (work@top) \_logic_net: (work@top.Fsm2Out), line:8:12, endln:8:19 |vpiRefModule: \_ref_module: work@FSM3 (F3), line:22:6, endln:22:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:1:1, endln:146:10 |vpiName:F3 |vpiDefName:work@FSM3 |vpiActual: diff --git a/tests/ForElab/ForElab.log b/tests/ForElab/ForElab.log index 72af59f511..f7401e4e2c 100644 --- a/tests/ForElab/ForElab.log +++ b/tests/ForElab/ForElab.log @@ -78,7 +78,7 @@ Instance tree: bit_typespec 2 constant 136 design 1 -gate 3 +gate 6 gen_scope 10 gen_scope_array 10 int_typespec 21 diff --git a/tests/FuncDeclScope/FuncDeclScope.log b/tests/FuncDeclScope/FuncDeclScope.log index f13a54a926..5a3d10e97c 100644 --- a/tests/FuncDeclScope/FuncDeclScope.log +++ b/tests/FuncDeclScope/FuncDeclScope.log @@ -492,6 +492,8 @@ design: (work@top) |vpiFullName:work@top.o |vpiRefModule: \_ref_module: work@intf (interf), line:28:8, endln:28:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncDeclScope/dut.sv, line:21:1, endln:40:10 |vpiName:interf |vpiDefName:work@intf |vpiActual: diff --git a/tests/FuncIoTypespec/FuncIoTypespec.log b/tests/FuncIoTypespec/FuncIoTypespec.log index cad4f90670..165d7e54a5 100644 --- a/tests/FuncIoTypespec/FuncIoTypespec.log +++ b/tests/FuncIoTypespec/FuncIoTypespec.log @@ -3646,6 +3646,8 @@ design: (work@top) |vpiConstType:9 |vpiRefModule: \_ref_module: work@shift (inst), line:97:5, endln:97:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FuncIoTypespec/dut.sv, line:83:1, endln:102:10 |vpiName:inst |vpiDefName:work@shift |vpiActual: diff --git a/tests/FuncParam/FuncParam.log b/tests/FuncParam/FuncParam.log index 354236da69..6aadbc2f42 100644 --- a/tests/FuncParam/FuncParam.log +++ b/tests/FuncParam/FuncParam.log @@ -589,12 +589,16 @@ design: (work@aes_prng) |vpiDefName:work@aes_prng |vpiRefModule: \_ref_module: work@prim_lfsr (u_lfsr16), line:13:6, endln:13:14 + |vpiParent: + \_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 |vpiName:u_lfsr16 |vpiDefName:work@prim_lfsr |vpiActual: \_module_inst: work@prim_lfsr (work@prim_lfsr), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:1:1, endln:8:10 |vpiRefModule: \_ref_module: work@prim_lfsr (u_lfsr18), line:17:6, endln:17:14 + |vpiParent: + \_module_inst: work@aes_prng (work@aes_prng), file:${SURELOG_DIR}/tests/FuncParam/dut.sv, line:10:1, endln:19:10 |vpiName:u_lfsr18 |vpiDefName:work@prim_lfsr |vpiActual: diff --git a/tests/FuncRetArray/FuncRetArray.log b/tests/FuncRetArray/FuncRetArray.log index 996a8a7cc8..ab70690801 100644 --- a/tests/FuncRetArray/FuncRetArray.log +++ b/tests/FuncRetArray/FuncRetArray.log @@ -407,6 +407,8 @@ design: (work@main) |vpiDefName:work@main |vpiRefModule: \_ref_module: work@top (top1), line:23:12, endln:23:16 + |vpiParent: + \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/FuncRetArray/dut.sv, line:22:1, endln:24:10 |vpiName:top1 |vpiDefName:work@top |vpiActual: diff --git a/tests/GateLevel/GateLevel.log b/tests/GateLevel/GateLevel.log index 1ac8d7c89f..ead2a4cf0b 100644 --- a/tests/GateLevel/GateLevel.log +++ b/tests/GateLevel/GateLevel.log @@ -785,7 +785,7 @@ enum_const 5 enum_typespec 1 enum_var 1 function 9 -gate 13 +gate 23 int_typespec 9 int_var 4 io_decl 11 @@ -813,7 +813,7 @@ enum_const 10 enum_typespec 2 enum_var 1 function 18 -gate 13 +gate 36 int_typespec 9 int_var 4 io_decl 22 @@ -821,12 +821,12 @@ logic_net 30 logic_typespec 15 logic_var 1 module_inst 7 -operation 15 +operation 30 package 2 port 76 -prim_term 40 -ref_obj 77 -switch_tran 1 +prim_term 80 +ref_obj 118 +switch_tran 2 task 18 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/GateLevel/slpp_all/surelog.uhdm ... @@ -1536,6 +1536,69 @@ design: (work@LogicGates) \_ref_obj: |vpiActual: \_logic_net: (work@LogicGates.y10), line:1:53, endln:1:56 + |vpiPrimitive: + \_gate: (work@LogicGates), line:5:6, endln:5:14 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@LogicGates), line:6:5, endln:6:13 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@LogicGates), line:7:6, endln:7:12 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@LogicGates), line:8:7, endln:8:15 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@LogicGates), line:9:6, endln:9:14 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@LogicGates), line:10:6, endln:10:14 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@LogicGates), line:11:7, endln:11:15 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiFullName:work@LogicGates + |vpiPrimType:6 + |vpiPrimitive: + \_gate: (work@LogicGates.a1), line:13:14, endln:13:25 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiName:a1 + |vpiFullName:work@LogicGates.a1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@LogicGates.a2), line:14:13, endln:14:31 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiName:a2 + |vpiFullName:work@LogicGates.a2 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@LogicGates.a3), line:15:25, endln:15:38 + |vpiParent: + \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 + |vpiName:a3 + |vpiFullName:work@LogicGates.a3 + |vpiPrimType:2 |uhdmtopModules: \_module_inst: work@LogicGates (work@LogicGates), file:${SURELOG_DIR}/tests/GateLevel/dut.sv, line:1:1, endln:20:10 |vpiName:work@LogicGates @@ -1907,7 +1970,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y1), line:5:7, endln:5:9 |vpiParent: - \_gate: work@and (work@LogicGates.), line:5:6, endln:5:14 + \_prim_term: , line:5:7, endln:5:9 |vpiName:y1 |vpiFullName:work@LogicGates.y1 |vpiActual: @@ -1921,7 +1984,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:5:10, endln:5:11 |vpiParent: - \_gate: work@and (work@LogicGates.), line:5:6, endln:5:14 + \_prim_term: , line:5:10, endln:5:11 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -1935,7 +1998,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:5:12, endln:5:13 |vpiParent: - \_gate: work@and (work@LogicGates.), line:5:6, endln:5:14 + \_prim_term: , line:5:12, endln:5:13 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -1955,7 +2018,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y2), line:6:6, endln:6:8 |vpiParent: - \_gate: work@or (work@LogicGates.), line:6:5, endln:6:13 + \_prim_term: , line:6:6, endln:6:8 |vpiName:y2 |vpiFullName:work@LogicGates.y2 |vpiActual: @@ -1969,7 +2032,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:6:9, endln:6:10 |vpiParent: - \_gate: work@or (work@LogicGates.), line:6:5, endln:6:13 + \_prim_term: , line:6:9, endln:6:10 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -1983,7 +2046,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:6:11, endln:6:12 |vpiParent: - \_gate: work@or (work@LogicGates.), line:6:5, endln:6:13 + \_prim_term: , line:6:11, endln:6:12 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2003,7 +2066,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y3), line:7:7, endln:7:9 |vpiParent: - \_gate: work@not (work@LogicGates.), line:7:6, endln:7:12 + \_prim_term: , line:7:7, endln:7:9 |vpiName:y3 |vpiFullName:work@LogicGates.y3 |vpiActual: @@ -2017,7 +2080,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:7:10, endln:7:11 |vpiParent: - \_gate: work@not (work@LogicGates.), line:7:6, endln:7:12 + \_prim_term: , line:7:10, endln:7:11 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2037,7 +2100,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y4), line:8:8, endln:8:10 |vpiParent: - \_gate: work@nand (work@LogicGates.), line:8:7, endln:8:15 + \_prim_term: , line:8:8, endln:8:10 |vpiName:y4 |vpiFullName:work@LogicGates.y4 |vpiActual: @@ -2051,7 +2114,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:8:11, endln:8:12 |vpiParent: - \_gate: work@nand (work@LogicGates.), line:8:7, endln:8:15 + \_prim_term: , line:8:11, endln:8:12 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2065,7 +2128,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:8:13, endln:8:14 |vpiParent: - \_gate: work@nand (work@LogicGates.), line:8:7, endln:8:15 + \_prim_term: , line:8:13, endln:8:14 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2085,7 +2148,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y5), line:9:7, endln:9:9 |vpiParent: - \_gate: work@nor (work@LogicGates.), line:9:6, endln:9:14 + \_prim_term: , line:9:7, endln:9:9 |vpiName:y5 |vpiFullName:work@LogicGates.y5 |vpiActual: @@ -2099,7 +2162,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:9:10, endln:9:11 |vpiParent: - \_gate: work@nor (work@LogicGates.), line:9:6, endln:9:14 + \_prim_term: , line:9:10, endln:9:11 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2113,7 +2176,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:9:12, endln:9:13 |vpiParent: - \_gate: work@nor (work@LogicGates.), line:9:6, endln:9:14 + \_prim_term: , line:9:12, endln:9:13 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2133,7 +2196,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y6), line:10:7, endln:10:9 |vpiParent: - \_gate: work@xor (work@LogicGates.), line:10:6, endln:10:14 + \_prim_term: , line:10:7, endln:10:9 |vpiName:y6 |vpiFullName:work@LogicGates.y6 |vpiActual: @@ -2147,7 +2210,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:10:10, endln:10:11 |vpiParent: - \_gate: work@xor (work@LogicGates.), line:10:6, endln:10:14 + \_prim_term: , line:10:10, endln:10:11 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2161,7 +2224,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:10:12, endln:10:13 |vpiParent: - \_gate: work@xor (work@LogicGates.), line:10:6, endln:10:14 + \_prim_term: , line:10:12, endln:10:13 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2181,7 +2244,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y7), line:11:8, endln:11:10 |vpiParent: - \_gate: work@xnor (work@LogicGates.), line:11:7, endln:11:15 + \_prim_term: , line:11:8, endln:11:10 |vpiName:y7 |vpiFullName:work@LogicGates.y7 |vpiActual: @@ -2195,7 +2258,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:11:11, endln:11:12 |vpiParent: - \_gate: work@xnor (work@LogicGates.), line:11:7, endln:11:15 + \_prim_term: , line:11:11, endln:11:12 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2209,7 +2272,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:11:13, endln:11:14 |vpiParent: - \_gate: work@xnor (work@LogicGates.), line:11:7, endln:11:15 + \_prim_term: , line:11:13, endln:11:14 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2236,7 +2299,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y8), line:13:18, endln:13:20 |vpiParent: - \_gate: work@and (work@LogicGates.a1), line:13:14, endln:13:25 + \_prim_term: , line:13:18, endln:13:20 |vpiName:y8 |vpiFullName:work@LogicGates.y8 |vpiActual: @@ -2250,7 +2313,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:13:21, endln:13:22 |vpiParent: - \_gate: work@and (work@LogicGates.a1), line:13:14, endln:13:25 + \_prim_term: , line:13:21, endln:13:22 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2264,7 +2327,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:13:23, endln:13:24 |vpiParent: - \_gate: work@and (work@LogicGates.a1), line:13:14, endln:13:25 + \_prim_term: , line:13:23, endln:13:24 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2279,9 +2342,13 @@ design: (work@LogicGates) |vpiPrimType:4 |vpiDelay: \_operation: , line:14:6, endln:14:12 + |vpiParent: + \_gate: work@or (work@LogicGates.a2), line:14:13, endln:14:31 |vpiOpType:37 |vpiOperand: \_operation: , line:14:8, endln:14:9 + |vpiParent: + \_operation: , line:14:6, endln:14:12 |vpiOpType:38 |vpiOperand: \_constant: , line:14:8, endln:14:9 @@ -2291,6 +2358,8 @@ design: (work@LogicGates) |vpiConstType:9 |vpiOperand: \_operation: , line:14:10, endln:14:11 + |vpiParent: + \_operation: , line:14:6, endln:14:12 |vpiOpType:38 |vpiOperand: \_constant: , line:14:10, endln:14:11 @@ -2306,7 +2375,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.y9), line:14:17, endln:14:19 |vpiParent: - \_gate: work@or (work@LogicGates.a2), line:14:13, endln:14:31 + \_prim_term: , line:14:17, endln:14:19 |vpiName:y9 |vpiFullName:work@LogicGates.y9 |vpiActual: @@ -2320,7 +2389,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:14:20, endln:14:21 |vpiParent: - \_gate: work@or (work@LogicGates.a2), line:14:13, endln:14:31 + \_prim_term: , line:14:20, endln:14:21 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2334,7 +2403,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:14:22, endln:14:23 |vpiParent: - \_gate: work@or (work@LogicGates.a2), line:14:13, endln:14:31 + \_prim_term: , line:14:22, endln:14:23 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2348,7 +2417,7 @@ design: (work@LogicGates) |vpiExpr: \_operation: , line:14:25, endln:14:30 |vpiParent: - \_gate: work@or (work@LogicGates.a2), line:14:13, endln:14:31 + \_prim_term: , line:14:25, endln:14:30 |vpiOpType:29 |vpiOperand: \_ref_obj: (work@LogicGates.a2.a), line:14:25, endln:14:26 @@ -2376,9 +2445,13 @@ design: (work@LogicGates) |vpiPrimType:2 |vpiDelay: \_operation: , line:15:8, endln:15:23 + |vpiParent: + \_gate: work@nand (work@LogicGates.a3), line:15:25, endln:15:38 |vpiOpType:37 |vpiOperand: \_operation: , line:15:10, endln:15:15 + |vpiParent: + \_operation: , line:15:8, endln:15:23 |vpiOpType:38 |vpiOperand: \_constant: , line:15:10, endln:15:11 @@ -2400,6 +2473,8 @@ design: (work@LogicGates) |vpiConstType:9 |vpiOperand: \_operation: , line:15:17, endln:15:22 + |vpiParent: + \_operation: , line:15:8, endln:15:23 |vpiOpType:38 |vpiOperand: \_constant: , line:15:17, endln:15:18 @@ -2427,7 +2502,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.nn), line:15:29, endln:15:31 |vpiParent: - \_gate: work@nand (work@LogicGates.a3), line:15:25, endln:15:38 + \_prim_term: , line:15:29, endln:15:31 |vpiName:nn |vpiFullName:work@LogicGates.nn |vpiActual: @@ -2441,7 +2516,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:15:33, endln:15:34 |vpiParent: - \_gate: work@nand (work@LogicGates.a3), line:15:25, endln:15:38 + \_prim_term: , line:15:33, endln:15:34 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2455,7 +2530,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:15:36, endln:15:37 |vpiParent: - \_gate: work@nand (work@LogicGates.a3), line:15:25, endln:15:38 + \_prim_term: , line:15:36, endln:15:37 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2470,9 +2545,13 @@ design: (work@LogicGates) |vpiPrimType:9 |vpiDelay: \_operation: , line:16:10, endln:16:20 + |vpiParent: + \_gate: work@bufif0 (work@LogicGates.a4), line:16:21, endln:16:36 |vpiOpType:37 |vpiOperand: \_operation: , line:16:12, endln:16:13 + |vpiParent: + \_operation: , line:16:10, endln:16:20 |vpiOpType:38 |vpiOperand: \_constant: , line:16:12, endln:16:13 @@ -2482,6 +2561,8 @@ design: (work@LogicGates) |vpiConstType:9 |vpiOperand: \_operation: , line:16:15, endln:16:16 + |vpiParent: + \_operation: , line:16:10, endln:16:20 |vpiOpType:38 |vpiOperand: \_constant: , line:16:15, endln:16:16 @@ -2491,6 +2572,8 @@ design: (work@LogicGates) |vpiConstType:9 |vpiOperand: \_operation: , line:16:18, endln:16:19 + |vpiParent: + \_operation: , line:16:10, endln:16:20 |vpiOpType:38 |vpiOperand: \_constant: , line:16:18, endln:16:19 @@ -2506,7 +2589,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.out2), line:16:25, endln:16:29 |vpiParent: - \_gate: work@bufif0 (work@LogicGates.a4), line:16:21, endln:16:36 + \_prim_term: , line:16:25, endln:16:29 |vpiName:out2 |vpiFullName:work@LogicGates.out2 |vpiActual: @@ -2520,7 +2603,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:16:31, endln:16:32 |vpiParent: - \_gate: work@bufif0 (work@LogicGates.a4), line:16:21, endln:16:36 + \_prim_term: , line:16:31, endln:16:32 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2534,7 +2617,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:16:34, endln:16:35 |vpiParent: - \_gate: work@bufif0 (work@LogicGates.a4), line:16:21, endln:16:36 + \_prim_term: , line:16:34, endln:16:35 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2549,9 +2632,13 @@ design: (work@LogicGates) |vpiPrimType:9 |vpiDelay: \_operation: , line:17:10, endln:17:32 + |vpiParent: + \_gate: work@bufif0 (work@LogicGates.a5), line:17:33, endln:17:48 |vpiOpType:37 |vpiOperand: \_operation: , line:17:12, endln:17:17 + |vpiParent: + \_operation: , line:17:10, endln:17:32 |vpiOpType:38 |vpiOperand: \_constant: , line:17:12, endln:17:13 @@ -2573,6 +2660,8 @@ design: (work@LogicGates) |vpiConstType:9 |vpiOperand: \_operation: , line:17:19, endln:17:24 + |vpiParent: + \_operation: , line:17:10, endln:17:32 |vpiOpType:38 |vpiOperand: \_constant: , line:17:19, endln:17:20 @@ -2594,6 +2683,8 @@ design: (work@LogicGates) |vpiConstType:9 |vpiOperand: \_operation: , line:17:26, endln:17:31 + |vpiParent: + \_operation: , line:17:10, endln:17:32 |vpiOpType:38 |vpiOperand: \_constant: , line:17:26, endln:17:27 @@ -2621,7 +2712,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.out3), line:17:37, endln:17:41 |vpiParent: - \_gate: work@bufif0 (work@LogicGates.a5), line:17:33, endln:17:48 + \_prim_term: , line:17:37, endln:17:41 |vpiName:out3 |vpiFullName:work@LogicGates.out3 |vpiActual: @@ -2635,7 +2726,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.a), line:17:43, endln:17:44 |vpiParent: - \_gate: work@bufif0 (work@LogicGates.a5), line:17:33, endln:17:48 + \_prim_term: , line:17:43, endln:17:44 |vpiName:a |vpiFullName:work@LogicGates.a |vpiActual: @@ -2649,7 +2740,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.b), line:17:46, endln:17:47 |vpiParent: - \_gate: work@bufif0 (work@LogicGates.a5), line:17:33, endln:17:48 + \_prim_term: , line:17:46, endln:17:47 |vpiName:b |vpiFullName:work@LogicGates.b |vpiActual: @@ -2670,7 +2761,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.p1), line:18:12, endln:18:14 |vpiParent: - \_switch_tran: work@pmos (work@LogicGates.a6), line:18:8, endln:18:21 + \_prim_term: , line:18:12, endln:18:14 |vpiName:p1 |vpiFullName:work@LogicGates.p1 |vpiActual: @@ -2684,7 +2775,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.p2), line:18:15, endln:18:17 |vpiParent: - \_switch_tran: work@pmos (work@LogicGates.a6), line:18:8, endln:18:21 + \_prim_term: , line:18:15, endln:18:17 |vpiName:p2 |vpiFullName:work@LogicGates.p2 |vpiActual: @@ -2698,7 +2789,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.p3), line:18:18, endln:18:20 |vpiParent: - \_switch_tran: work@pmos (work@LogicGates.a6), line:18:8, endln:18:21 + \_prim_term: , line:18:18, endln:18:20 |vpiName:p3 |vpiFullName:work@LogicGates.p3 |vpiActual: @@ -2719,7 +2810,7 @@ design: (work@LogicGates) |vpiExpr: \_ref_obj: (work@LogicGates.p1), line:19:14, endln:19:16 |vpiParent: - \_gate: work@pullup (work@LogicGates.a7), line:19:10, endln:19:17 + \_prim_term: , line:19:14, endln:19:16 |vpiName:p1 |vpiFullName:work@LogicGates.p1 |vpiActual: diff --git a/tests/Gates/Gates.log b/tests/Gates/Gates.log index fbd8de858e..165ce111ce 100644 --- a/tests/Gates/Gates.log +++ b/tests/Gates/Gates.log @@ -3164,15 +3164,15 @@ begin 7 class_defn 8 class_typespec 4 class_var 3 -constant 90 +constant 92 delay_control 33 design 1 enum_const 5 enum_typespec 1 enum_var 1 function 9 -gate 34 -gate_array 1 +gate 65 +gate_array 2 initial 7 int_typespec 9 int_var 4 @@ -3185,7 +3185,7 @@ operation 21 package 2 port 124 prim_term 116 -range 5 +range 6 ref_obj 219 switch_tran 2 sys_func_call 16 @@ -3200,15 +3200,15 @@ begin 14 class_defn 8 class_typespec 4 class_var 3 -constant 90 +constant 92 delay_control 66 design 1 enum_const 10 enum_typespec 2 enum_var 1 function 18 -gate 34 -gate_array 1 +gate 99 +gate_array 3 initial 14 int_typespec 9 int_var 4 @@ -3217,13 +3217,13 @@ logic_net 136 logic_typespec 29 logic_var 1 module_inst 32 -operation 27 +operation 42 package 2 port 128 -prim_term 116 -range 5 -ref_obj 318 -switch_tran 2 +prim_term 232 +range 7 +ref_obj 434 +switch_tran 4 sys_func_call 32 task 18 === UHDM Object Stats End === @@ -3929,6 +3929,20 @@ design: (work@gates) |vpiParent: \_delay_control: , line:140:3, endln:140:5 |vpiName:$finish + |vpiPrimitive: + \_gate: (work@and_from_nand.U1), line:129:6, endln:129:16 + |vpiParent: + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + |vpiName:U1 + |vpiFullName:work@and_from_nand.U1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@and_from_nand.U2), line:130:6, endln:130:17 + |vpiParent: + \_module_inst: work@and_from_nand (work@and_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:124:1, endln:143:10 + |vpiName:U2 + |vpiFullName:work@and_from_nand.U2 + |vpiPrimType:2 |uhdmallModules: \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 |vpiParent: @@ -4217,6 +4231,33 @@ design: (work@gates) |vpiParent: \_delay_control: , line:173:3, endln:173:6 |vpiName:$finish + |vpiPrimitive: + \_gate: (work@delay_example), line:151:38, endln:151:48 + |vpiParent: + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + |vpiFullName:work@delay_example + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@delay_example.u_and), line:153:29, endln:153:48 + |vpiParent: + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + |vpiName:u_and + |vpiFullName:work@delay_example.u_and + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@delay_example.u_nand), line:157:29, endln:157:48 + |vpiParent: + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + |vpiName:u_nand + |vpiFullName:work@delay_example.u_nand + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@delay_example.u_buf), line:159:29, endln:159:46 + |vpiParent: + \_module_inst: work@delay_example (work@delay_example), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:145:1, endln:176:10 + |vpiName:u_buf + |vpiFullName:work@delay_example.u_buf + |vpiPrimType:7 |uhdmallModules: \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 |vpiParent: @@ -4450,6 +4491,34 @@ design: (work@gates) |vpiActual: \_logic_net: (work@dff_from_nand.CLK), line:64:7, endln:64:10 |vpiAlwaysType:1 + |vpiPrimitive: + \_gate: (work@dff_from_nand.U1), line:66:6, endln:66:18 + |vpiParent: + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + |vpiName:U1 + |vpiFullName:work@dff_from_nand.U1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@dff_from_nand.U2), line:67:6, endln:67:18 + |vpiParent: + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + |vpiName:U2 + |vpiFullName:work@dff_from_nand.U2 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@dff_from_nand.U3), line:68:6, endln:68:20 + |vpiParent: + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + |vpiName:U3 + |vpiFullName:work@dff_from_nand.U3 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@dff_from_nand.U4), line:69:6, endln:69:20 + |vpiParent: + \_module_inst: work@dff_from_nand (work@dff_from_nand), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:62:1, endln:83:10 + |vpiName:U4 + |vpiFullName:work@dff_from_nand.U4 + |vpiPrimType:2 |uhdmallModules: \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiParent: @@ -4477,6 +4546,34 @@ design: (work@gates) |vpiName:in2 |vpiFullName:work@gate_array.in2 |vpiNetType:1 + |vpiPrimitiveArray: + \_gate_array: (work@gate_array.n_gate), line:233:6, endln:233:34 + |vpiParent: + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + |vpiName:n_gate + |vpiFullName:work@gate_array.n_gate + |vpiRange: + \_range: , line:233:13, endln:233:18 + |vpiLeftRange: + \_constant: , line:233:14, endln:233:15 + |vpiParent: + \_range: , line:233:13, endln:233:18 + |vpiDecompile:7 + |vpiSize:64 + |UINT:7 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:233:16, endln:233:17 + |vpiParent: + \_range: , line:233:13, endln:233:18 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiPrimitive: + \_gate: (n_gate), line:233:6, endln:233:34 + |vpiName:n_gate + |vpiPrimType:2 |uhdmallModules: \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiParent: @@ -4816,6 +4913,27 @@ design: (work@gates) |vpiParent: \_delay_control: , line:24:3, endln:24:5 |vpiName:$finish + |vpiPrimitive: + \_gate: (work@gates.U1), line:8:5, endln:8:17 + |vpiParent: + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + |vpiName:U1 + |vpiFullName:work@gates.U1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@gates.U2), line:9:5, endln:9:29 + |vpiParent: + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + |vpiName:U2 + |vpiFullName:work@gates.U2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@gates.U3), line:10:5, endln:10:25 + |vpiParent: + \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 + |vpiName:U3 + |vpiFullName:work@gates.U3 + |vpiPrimType:5 |uhdmallModules: \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 |vpiParent: @@ -4896,6 +5014,18 @@ design: (work@gates) \_logic_net: (work@half_adder.B), line:222:34, endln:222:35 |vpiTypedef: \_logic_typespec: , line:223:8, endln:223:8 + |vpiPrimitive: + \_gate: (work@half_adder), line:225:12, endln:225:23 + |vpiParent: + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + |vpiFullName:work@half_adder + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@half_adder), line:226:12, endln:226:25 + |vpiParent: + \_module_inst: work@half_adder (work@half_adder), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:222:1, endln:227:10 + |vpiFullName:work@half_adder + |vpiPrimType:1 |uhdmallModules: \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 |vpiParent: @@ -5400,6 +5530,48 @@ design: (work@gates) |vpiActual: \_logic_net: (work@mux_from_gates.c3), line:86:14, endln:86:16 |vpiAlwaysType:1 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:89:5, endln:89:15 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:90:5, endln:90:15 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:92:5, endln:92:24 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:93:5, endln:93:20 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:94:5, endln:94:20 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:95:5, endln:95:16 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@mux_from_gates), line:97:4, endln:97:20 + |vpiParent: + \_module_inst: work@mux_from_gates (work@mux_from_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:85:1, endln:121:10 + |vpiFullName:work@mux_from_gates + |vpiPrimType:4 |uhdmallModules: \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 |vpiParent: @@ -5739,6 +5911,27 @@ design: (work@gates) |vpiParent: \_delay_control: , line:203:3, endln:203:5 |vpiName:$finish + |vpiPrimitive: + \_gate: (work@n_in_primitive.u_and1), line:184:5, endln:184:28 + |vpiParent: + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + |vpiName:u_and1 + |vpiFullName:work@n_in_primitive.u_and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@n_in_primitive.u_and2), line:186:5, endln:186:38 + |vpiParent: + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + |vpiName:u_and2 + |vpiFullName:work@n_in_primitive.u_and2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@n_in_primitive.u_xnor1), line:188:6, endln:188:35 + |vpiParent: + \_module_inst: work@n_in_primitive (work@n_in_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:178:1, endln:206:10 + |vpiName:u_xnor1 + |vpiFullName:work@n_in_primitive.u_xnor1 + |vpiPrimType:6 |uhdmallModules: \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 |vpiParent: @@ -5808,6 +6001,27 @@ design: (work@gates) |vpiName:in |vpiFullName:work@n_out_primitive.in |vpiNetType:1 + |vpiPrimitive: + \_gate: (work@n_out_primitive.u_buf0), line:214:5, endln:214:20 + |vpiParent: + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + |vpiName:u_buf0 + |vpiFullName:work@n_out_primitive.u_buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 + |vpiParent: + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + |vpiName:u_buf1 + |vpiFullName:work@n_out_primitive.u_buf1 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@n_out_primitive.u_not0), line:218:5, endln:218:37 + |vpiParent: + \_module_inst: work@n_out_primitive (work@n_out_primitive), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:208:1, endln:220:10 + |vpiName:u_not0 + |vpiFullName:work@n_out_primitive.u_not0 + |vpiPrimType:8 |uhdmallModules: \_module_inst: work@switch_primitives (work@switch_primitives), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:52:1, endln:60:10 |vpiParent: @@ -6082,6 +6296,20 @@ design: (work@gates) |vpiActual: \_logic_net: (work@transmission_gates.in), line:31:22, endln:31:24 |vpiAlwaysType:1 + |vpiPrimitive: + \_gate: (work@transmission_gates.U2), line:35:6, endln:35:17 + |vpiParent: + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + |vpiName:U2 + |vpiFullName:work@transmission_gates.U2 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@transmission_gates.U3), line:36:5, endln:36:16 + |vpiParent: + \_module_inst: work@transmission_gates (work@transmission_gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:29:1, endln:50:10 + |vpiName:U3 + |vpiFullName:work@transmission_gates.U3 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@gates (work@gates), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:1:1, endln:27:10 |vpiName:work@gates @@ -6397,7 +6625,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.out0), line:8:8, endln:8:12 |vpiParent: - \_gate: work@not (work@gates.U1), line:8:5, endln:8:17 + \_prim_term: , line:8:8, endln:8:12 |vpiName:out0 |vpiFullName:work@gates.out0 |vpiActual: @@ -6411,7 +6639,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in1), line:8:13, endln:8:16 |vpiParent: - \_gate: work@not (work@gates.U1), line:8:5, endln:8:17 + \_prim_term: , line:8:13, endln:8:16 |vpiName:in1 |vpiFullName:work@gates.in1 |vpiActual: @@ -6432,7 +6660,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.out1), line:9:8, endln:9:12 |vpiParent: - \_gate: work@and (work@gates.U2), line:9:5, endln:9:29 + \_prim_term: , line:9:8, endln:9:12 |vpiName:out1 |vpiFullName:work@gates.out1 |vpiActual: @@ -6446,7 +6674,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in1), line:9:13, endln:9:16 |vpiParent: - \_gate: work@and (work@gates.U2), line:9:5, endln:9:29 + \_prim_term: , line:9:13, endln:9:16 |vpiName:in1 |vpiFullName:work@gates.in1 |vpiActual: @@ -6460,7 +6688,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in2), line:9:17, endln:9:20 |vpiParent: - \_gate: work@and (work@gates.U2), line:9:5, endln:9:29 + \_prim_term: , line:9:17, endln:9:20 |vpiName:in2 |vpiFullName:work@gates.in2 |vpiActual: @@ -6474,7 +6702,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in3), line:9:21, endln:9:24 |vpiParent: - \_gate: work@and (work@gates.U2), line:9:5, endln:9:29 + \_prim_term: , line:9:21, endln:9:24 |vpiName:in3 |vpiFullName:work@gates.in3 |vpiActual: @@ -6488,7 +6716,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in4), line:9:25, endln:9:28 |vpiParent: - \_gate: work@and (work@gates.U2), line:9:5, endln:9:29 + \_prim_term: , line:9:25, endln:9:28 |vpiName:in4 |vpiFullName:work@gates.in4 |vpiActual: @@ -6509,7 +6737,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.out2), line:10:8, endln:10:12 |vpiParent: - \_gate: work@xor (work@gates.U3), line:10:5, endln:10:25 + \_prim_term: , line:10:8, endln:10:12 |vpiName:out2 |vpiFullName:work@gates.out2 |vpiActual: @@ -6523,7 +6751,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in1), line:10:13, endln:10:16 |vpiParent: - \_gate: work@xor (work@gates.U3), line:10:5, endln:10:25 + \_prim_term: , line:10:13, endln:10:16 |vpiName:in1 |vpiFullName:work@gates.in1 |vpiActual: @@ -6537,7 +6765,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in2), line:10:17, endln:10:20 |vpiParent: - \_gate: work@xor (work@gates.U3), line:10:5, endln:10:25 + \_prim_term: , line:10:17, endln:10:20 |vpiName:in2 |vpiFullName:work@gates.in2 |vpiActual: @@ -6551,7 +6779,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gates.in3), line:10:21, endln:10:24 |vpiParent: - \_gate: work@xor (work@gates.U3), line:10:5, endln:10:25 + \_prim_term: , line:10:21, endln:10:24 |vpiName:in3 |vpiFullName:work@gates.in3 |vpiActual: @@ -6784,7 +7012,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.data_bus), line:34:11, endln:34:19 |vpiParent: - \_gate: work@bufif0 (work@transmission_gates.U1), line:34:8, endln:34:40 + \_prim_term: , line:34:11, endln:34:19 |vpiName:data_bus |vpiFullName:work@transmission_gates.data_bus |vpiActual: @@ -6798,7 +7026,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.in), line:34:20, endln:34:22 |vpiParent: - \_gate: work@bufif0 (work@transmission_gates.U1), line:34:8, endln:34:40 + \_prim_term: , line:34:20, endln:34:22 |vpiName:in |vpiFullName:work@transmission_gates.in |vpiActual: @@ -6812,7 +7040,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.data_enable_low), line:34:24, endln:34:39 |vpiParent: - \_gate: work@bufif0 (work@transmission_gates.U1), line:34:8, endln:34:40 + \_prim_term: , line:34:24, endln:34:39 |vpiName:data_enable_low |vpiFullName:work@transmission_gates.data_enable_low |vpiActual: @@ -6833,7 +7061,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.out1), line:35:9, endln:35:13 |vpiParent: - \_gate: work@buf (work@transmission_gates.U2), line:35:6, endln:35:17 + \_prim_term: , line:35:9, endln:35:13 |vpiName:out1 |vpiFullName:work@transmission_gates.out1 |vpiActual: @@ -6847,7 +7075,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.in), line:35:14, endln:35:16 |vpiParent: - \_gate: work@buf (work@transmission_gates.U2), line:35:6, endln:35:17 + \_prim_term: , line:35:14, endln:35:16 |vpiName:in |vpiFullName:work@transmission_gates.in |vpiActual: @@ -6868,7 +7096,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.out2), line:36:8, endln:36:12 |vpiParent: - \_gate: work@not (work@transmission_gates.U3), line:36:5, endln:36:16 + \_prim_term: , line:36:8, endln:36:12 |vpiName:out2 |vpiFullName:work@transmission_gates.out2 |vpiActual: @@ -6882,7 +7110,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@transmission_gates.in), line:36:13, endln:36:15 |vpiParent: - \_gate: work@not (work@transmission_gates.U3), line:36:5, endln:36:16 + \_prim_term: , line:36:13, endln:36:15 |vpiName:in |vpiFullName:work@transmission_gates.in |vpiActual: @@ -6963,7 +7191,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@switch_primitives.net1), line:57:19, endln:57:23 |vpiParent: - \_switch_tran: work@tranif0 (work@switch_primitives.my_gate1), line:57:9, endln:57:36 + \_prim_term: , line:57:19, endln:57:23 |vpiName:net1 |vpiFullName:work@switch_primitives.net1 |vpiActual: @@ -6977,7 +7205,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@switch_primitives.net2), line:57:25, endln:57:29 |vpiParent: - \_switch_tran: work@tranif0 (work@switch_primitives.my_gate1), line:57:9, endln:57:36 + \_prim_term: , line:57:25, endln:57:29 |vpiName:net2 |vpiFullName:work@switch_primitives.net2 |vpiActual: @@ -6991,7 +7219,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@switch_primitives.net3), line:57:31, endln:57:35 |vpiParent: - \_switch_tran: work@tranif0 (work@switch_primitives.my_gate1), line:57:9, endln:57:36 + \_prim_term: , line:57:31, endln:57:35 |vpiName:net3 |vpiFullName:work@switch_primitives.net3 |vpiActual: @@ -7012,7 +7240,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@switch_primitives.net4), line:58:20, endln:58:24 |vpiParent: - \_switch_tran: work@rtranif1 (work@switch_primitives.my_gate2), line:58:10, endln:58:37 + \_prim_term: , line:58:20, endln:58:24 |vpiName:net4 |vpiFullName:work@switch_primitives.net4 |vpiActual: @@ -7026,7 +7254,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@switch_primitives.net5), line:58:26, endln:58:30 |vpiParent: - \_switch_tran: work@rtranif1 (work@switch_primitives.my_gate2), line:58:10, endln:58:37 + \_prim_term: , line:58:26, endln:58:30 |vpiName:net5 |vpiFullName:work@switch_primitives.net5 |vpiActual: @@ -7040,7 +7268,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@switch_primitives.net6), line:58:32, endln:58:36 |vpiParent: - \_switch_tran: work@rtranif1 (work@switch_primitives.my_gate2), line:58:10, endln:58:37 + \_prim_term: , line:58:32, endln:58:36 |vpiName:net6 |vpiFullName:work@switch_primitives.net6 |vpiActual: @@ -7286,7 +7514,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.X), line:66:10, endln:66:11 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), line:66:6, endln:66:18 + \_prim_term: , line:66:10, endln:66:11 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiActual: @@ -7300,7 +7528,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.D), line:66:12, endln:66:13 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), line:66:6, endln:66:18 + \_prim_term: , line:66:12, endln:66:13 |vpiName:D |vpiFullName:work@dff_from_nand.D |vpiActual: @@ -7314,7 +7542,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.CLK), line:66:14, endln:66:17 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), line:66:6, endln:66:18 + \_prim_term: , line:66:14, endln:66:17 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiActual: @@ -7335,7 +7563,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.Y), line:67:10, endln:67:11 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U2), line:67:6, endln:67:18 + \_prim_term: , line:67:10, endln:67:11 |vpiName:Y |vpiFullName:work@dff_from_nand.Y |vpiActual: @@ -7349,7 +7577,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.X), line:67:12, endln:67:13 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U2), line:67:6, endln:67:18 + \_prim_term: , line:67:12, endln:67:13 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiActual: @@ -7363,7 +7591,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.CLK), line:67:14, endln:67:17 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U2), line:67:6, endln:67:18 + \_prim_term: , line:67:14, endln:67:17 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiActual: @@ -7384,7 +7612,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.Q), line:68:10, endln:68:11 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U3), line:68:6, endln:68:20 + \_prim_term: , line:68:10, endln:68:11 |vpiName:Q |vpiFullName:work@dff_from_nand.Q |vpiActual: @@ -7398,7 +7626,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.Q_BAR), line:68:12, endln:68:17 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U3), line:68:6, endln:68:20 + \_prim_term: , line:68:12, endln:68:17 |vpiName:Q_BAR |vpiFullName:work@dff_from_nand.Q_BAR |vpiActual: @@ -7412,7 +7640,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.X), line:68:18, endln:68:19 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U3), line:68:6, endln:68:20 + \_prim_term: , line:68:18, endln:68:19 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiActual: @@ -7433,7 +7661,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.Q_BAR), line:69:10, endln:69:15 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U4), line:69:6, endln:69:20 + \_prim_term: , line:69:10, endln:69:15 |vpiName:Q_BAR |vpiFullName:work@dff_from_nand.Q_BAR |vpiActual: @@ -7447,7 +7675,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.Q), line:69:16, endln:69:17 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U4), line:69:6, endln:69:20 + \_prim_term: , line:69:16, endln:69:17 |vpiName:Q |vpiFullName:work@dff_from_nand.Q |vpiActual: @@ -7461,7 +7689,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@dff_from_nand.Y), line:69:18, endln:69:19 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U4), line:69:6, endln:69:20 + \_prim_term: , line:69:18, endln:69:19 |vpiName:Y |vpiFullName:work@dff_from_nand.Y |vpiActual: @@ -7981,7 +8209,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.a_inv), line:89:6, endln:89:11 |vpiParent: - \_gate: work@not (work@mux_from_gates.), line:89:5, endln:89:15 + \_prim_term: , line:89:6, endln:89:11 |vpiName:a_inv |vpiFullName:work@mux_from_gates.a_inv |vpiActual: @@ -7995,7 +8223,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.A), line:89:13, endln:89:14 |vpiParent: - \_gate: work@not (work@mux_from_gates.), line:89:5, endln:89:15 + \_prim_term: , line:89:13, endln:89:14 |vpiName:A |vpiFullName:work@mux_from_gates.A |vpiActual: @@ -8015,7 +8243,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.b_inv), line:90:6, endln:90:11 |vpiParent: - \_gate: work@not (work@mux_from_gates.), line:90:5, endln:90:15 + \_prim_term: , line:90:6, endln:90:11 |vpiName:b_inv |vpiFullName:work@mux_from_gates.b_inv |vpiActual: @@ -8029,7 +8257,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.B), line:90:13, endln:90:14 |vpiParent: - \_gate: work@not (work@mux_from_gates.), line:90:5, endln:90:15 + \_prim_term: , line:90:13, endln:90:14 |vpiName:B |vpiFullName:work@mux_from_gates.B |vpiActual: @@ -8049,7 +8277,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y0), line:92:6, endln:92:8 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:92:5, endln:92:24 + \_prim_term: , line:92:6, endln:92:8 |vpiName:y0 |vpiFullName:work@mux_from_gates.y0 |vpiActual: @@ -8063,7 +8291,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.c0), line:92:9, endln:92:11 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:92:5, endln:92:24 + \_prim_term: , line:92:9, endln:92:11 |vpiName:c0 |vpiFullName:work@mux_from_gates.c0 |vpiActual: @@ -8077,7 +8305,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.a_inv), line:92:12, endln:92:17 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:92:5, endln:92:24 + \_prim_term: , line:92:12, endln:92:17 |vpiName:a_inv |vpiFullName:work@mux_from_gates.a_inv |vpiActual: @@ -8091,7 +8319,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.b_inv), line:92:18, endln:92:23 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:92:5, endln:92:24 + \_prim_term: , line:92:18, endln:92:23 |vpiName:b_inv |vpiFullName:work@mux_from_gates.b_inv |vpiActual: @@ -8111,7 +8339,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y1), line:93:6, endln:93:8 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:93:5, endln:93:20 + \_prim_term: , line:93:6, endln:93:8 |vpiName:y1 |vpiFullName:work@mux_from_gates.y1 |vpiActual: @@ -8125,7 +8353,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.c1), line:93:9, endln:93:11 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:93:5, endln:93:20 + \_prim_term: , line:93:9, endln:93:11 |vpiName:c1 |vpiFullName:work@mux_from_gates.c1 |vpiActual: @@ -8139,7 +8367,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.a_inv), line:93:12, endln:93:17 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:93:5, endln:93:20 + \_prim_term: , line:93:12, endln:93:17 |vpiName:a_inv |vpiFullName:work@mux_from_gates.a_inv |vpiActual: @@ -8153,7 +8381,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.B), line:93:18, endln:93:19 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:93:5, endln:93:20 + \_prim_term: , line:93:18, endln:93:19 |vpiName:B |vpiFullName:work@mux_from_gates.B |vpiActual: @@ -8173,7 +8401,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y2), line:94:6, endln:94:8 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:94:5, endln:94:20 + \_prim_term: , line:94:6, endln:94:8 |vpiName:y2 |vpiFullName:work@mux_from_gates.y2 |vpiActual: @@ -8187,7 +8415,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.c2), line:94:9, endln:94:11 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:94:5, endln:94:20 + \_prim_term: , line:94:9, endln:94:11 |vpiName:c2 |vpiFullName:work@mux_from_gates.c2 |vpiActual: @@ -8201,7 +8429,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.A), line:94:12, endln:94:13 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:94:5, endln:94:20 + \_prim_term: , line:94:12, endln:94:13 |vpiName:A |vpiFullName:work@mux_from_gates.A |vpiActual: @@ -8215,7 +8443,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.b_inv), line:94:14, endln:94:19 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:94:5, endln:94:20 + \_prim_term: , line:94:14, endln:94:19 |vpiName:b_inv |vpiFullName:work@mux_from_gates.b_inv |vpiActual: @@ -8235,7 +8463,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y3), line:95:6, endln:95:8 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:95:5, endln:95:16 + \_prim_term: , line:95:6, endln:95:8 |vpiName:y3 |vpiFullName:work@mux_from_gates.y3 |vpiActual: @@ -8249,7 +8477,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.c3), line:95:9, endln:95:11 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:95:5, endln:95:16 + \_prim_term: , line:95:9, endln:95:11 |vpiName:c3 |vpiFullName:work@mux_from_gates.c3 |vpiActual: @@ -8263,7 +8491,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.A), line:95:12, endln:95:13 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:95:5, endln:95:16 + \_prim_term: , line:95:12, endln:95:13 |vpiName:A |vpiFullName:work@mux_from_gates.A |vpiActual: @@ -8277,7 +8505,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.B), line:95:14, endln:95:15 |vpiParent: - \_gate: work@and (work@mux_from_gates.), line:95:5, endln:95:16 + \_prim_term: , line:95:14, endln:95:15 |vpiName:B |vpiFullName:work@mux_from_gates.B |vpiActual: @@ -8297,7 +8525,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.Y), line:97:5, endln:97:6 |vpiParent: - \_gate: work@or (work@mux_from_gates.), line:97:4, endln:97:20 + \_prim_term: , line:97:5, endln:97:6 |vpiName:Y |vpiFullName:work@mux_from_gates.Y |vpiActual: @@ -8311,7 +8539,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y0), line:97:8, endln:97:10 |vpiParent: - \_gate: work@or (work@mux_from_gates.), line:97:4, endln:97:20 + \_prim_term: , line:97:8, endln:97:10 |vpiName:y0 |vpiFullName:work@mux_from_gates.y0 |vpiActual: @@ -8325,7 +8553,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y1), line:97:11, endln:97:13 |vpiParent: - \_gate: work@or (work@mux_from_gates.), line:97:4, endln:97:20 + \_prim_term: , line:97:11, endln:97:13 |vpiName:y1 |vpiFullName:work@mux_from_gates.y1 |vpiActual: @@ -8339,7 +8567,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y2), line:97:14, endln:97:16 |vpiParent: - \_gate: work@or (work@mux_from_gates.), line:97:4, endln:97:20 + \_prim_term: , line:97:14, endln:97:16 |vpiName:y2 |vpiFullName:work@mux_from_gates.y2 |vpiActual: @@ -8353,7 +8581,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@mux_from_gates.y3), line:97:17, endln:97:19 |vpiParent: - \_gate: work@or (work@mux_from_gates.), line:97:4, endln:97:20 + \_prim_term: , line:97:17, endln:97:19 |vpiName:y3 |vpiFullName:work@mux_from_gates.y3 |vpiActual: @@ -8561,7 +8789,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@and_from_nand.W), line:129:9, endln:129:10 |vpiParent: - \_gate: work@nand (work@and_from_nand.U1), line:129:6, endln:129:16 + \_prim_term: , line:129:9, endln:129:10 |vpiName:W |vpiFullName:work@and_from_nand.W |vpiActual: @@ -8575,7 +8803,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@and_from_nand.X), line:129:11, endln:129:12 |vpiParent: - \_gate: work@nand (work@and_from_nand.U1), line:129:6, endln:129:16 + \_prim_term: , line:129:11, endln:129:12 |vpiName:X |vpiFullName:work@and_from_nand.X |vpiActual: @@ -8589,7 +8817,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@and_from_nand.Y), line:129:14, endln:129:15 |vpiParent: - \_gate: work@nand (work@and_from_nand.U1), line:129:6, endln:129:16 + \_prim_term: , line:129:14, endln:129:15 |vpiName:Y |vpiFullName:work@and_from_nand.Y |vpiActual: @@ -8610,7 +8838,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@and_from_nand.F), line:130:9, endln:130:10 |vpiParent: - \_gate: work@nand (work@and_from_nand.U2), line:130:6, endln:130:17 + \_prim_term: , line:130:9, endln:130:10 |vpiName:F |vpiFullName:work@and_from_nand.F |vpiActual: @@ -8624,7 +8852,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@and_from_nand.W), line:130:12, endln:130:13 |vpiParent: - \_gate: work@nand (work@and_from_nand.U2), line:130:6, endln:130:17 + \_prim_term: , line:130:12, endln:130:13 |vpiName:W |vpiFullName:work@and_from_nand.W |vpiActual: @@ -8638,7 +8866,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@and_from_nand.W), line:130:15, endln:130:16 |vpiParent: - \_gate: work@nand (work@and_from_nand.U2), line:130:6, endln:130:17 + \_prim_term: , line:130:15, endln:130:16 |vpiName:W |vpiFullName:work@and_from_nand.W |vpiActual: @@ -8933,7 +9161,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.out1), line:151:39, endln:151:43 |vpiParent: - \_gate: work@or (work@delay_example.u_or), line:151:38, endln:151:48 + \_prim_term: , line:151:39, endln:151:43 |vpiName:out1 |vpiFullName:work@delay_example.out1 |vpiActual: @@ -8947,7 +9175,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.b), line:151:44, endln:151:45 |vpiParent: - \_gate: work@or (work@delay_example.u_or), line:151:38, endln:151:48 + \_prim_term: , line:151:44, endln:151:45 |vpiName:b |vpiFullName:work@delay_example.b |vpiActual: @@ -8961,7 +9189,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.c), line:151:46, endln:151:47 |vpiParent: - \_gate: work@or (work@delay_example.u_or), line:151:38, endln:151:48 + \_prim_term: , line:151:46, endln:151:47 |vpiName:c |vpiFullName:work@delay_example.c |vpiActual: @@ -8976,9 +9204,13 @@ design: (work@gates) |vpiPrimType:1 |vpiDelay: \_operation: , line:153:8, endln:153:14 + |vpiParent: + \_gate: work@and (work@delay_example.u_and), line:153:29, endln:153:48 |vpiOpType:37 |vpiOperand: \_operation: , line:153:10, endln:153:11 + |vpiParent: + \_operation: , line:153:8, endln:153:14 |vpiOpType:38 |vpiOperand: \_constant: , line:153:10, endln:153:11 @@ -8988,6 +9220,8 @@ design: (work@gates) |vpiConstType:9 |vpiOperand: \_operation: , line:153:12, endln:153:13 + |vpiParent: + \_operation: , line:153:8, endln:153:14 |vpiOpType:38 |vpiOperand: \_constant: , line:153:12, endln:153:13 @@ -9003,7 +9237,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.out2), line:153:39, endln:153:43 |vpiParent: - \_gate: work@and (work@delay_example.u_and), line:153:29, endln:153:48 + \_prim_term: , line:153:39, endln:153:43 |vpiName:out2 |vpiFullName:work@delay_example.out2 |vpiActual: @@ -9017,7 +9251,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.b), line:153:44, endln:153:45 |vpiParent: - \_gate: work@and (work@delay_example.u_and), line:153:29, endln:153:48 + \_prim_term: , line:153:44, endln:153:45 |vpiName:b |vpiFullName:work@delay_example.b |vpiActual: @@ -9031,7 +9265,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.c), line:153:46, endln:153:47 |vpiParent: - \_gate: work@and (work@delay_example.u_and), line:153:29, endln:153:48 + \_prim_term: , line:153:46, endln:153:47 |vpiName:c |vpiFullName:work@delay_example.c |vpiActual: @@ -9046,9 +9280,13 @@ design: (work@gates) |vpiPrimType:10 |vpiDelay: \_operation: , line:155:11, endln:155:19 + |vpiParent: + \_gate: work@bufif1 (work@delay_example.u_nor), line:155:32, endln:155:51 |vpiOpType:37 |vpiOperand: \_operation: , line:155:13, endln:155:14 + |vpiParent: + \_operation: , line:155:11, endln:155:19 |vpiOpType:38 |vpiOperand: \_constant: , line:155:13, endln:155:14 @@ -9058,6 +9296,8 @@ design: (work@gates) |vpiConstType:9 |vpiOperand: \_operation: , line:155:15, endln:155:16 + |vpiParent: + \_operation: , line:155:11, endln:155:19 |vpiOpType:38 |vpiOperand: \_constant: , line:155:15, endln:155:16 @@ -9067,6 +9307,8 @@ design: (work@gates) |vpiConstType:9 |vpiOperand: \_operation: , line:155:17, endln:155:18 + |vpiParent: + \_operation: , line:155:11, endln:155:19 |vpiOpType:38 |vpiOperand: \_constant: , line:155:17, endln:155:18 @@ -9082,7 +9324,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.out3), line:155:42, endln:155:46 |vpiParent: - \_gate: work@bufif1 (work@delay_example.u_nor), line:155:32, endln:155:51 + \_prim_term: , line:155:42, endln:155:46 |vpiName:out3 |vpiFullName:work@delay_example.out3 |vpiActual: @@ -9096,7 +9338,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.b), line:155:47, endln:155:48 |vpiParent: - \_gate: work@bufif1 (work@delay_example.u_nor), line:155:32, endln:155:51 + \_prim_term: , line:155:47, endln:155:48 |vpiName:b |vpiFullName:work@delay_example.b |vpiActual: @@ -9110,7 +9352,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.c), line:155:49, endln:155:50 |vpiParent: - \_gate: work@bufif1 (work@delay_example.u_nor), line:155:32, endln:155:51 + \_prim_term: , line:155:49, endln:155:50 |vpiName:c |vpiFullName:work@delay_example.c |vpiActual: @@ -9125,6 +9367,8 @@ design: (work@gates) |vpiPrimType:2 |vpiDelay: \_operation: , line:157:8, endln:157:16 + |vpiParent: + \_gate: work@nand (work@delay_example.u_nand), line:157:29, endln:157:48 |vpiOpType:38 |vpiOperand: \_constant: , line:157:10, endln:157:11 @@ -9152,7 +9396,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.out4), line:157:39, endln:157:43 |vpiParent: - \_gate: work@nand (work@delay_example.u_nand), line:157:29, endln:157:48 + \_prim_term: , line:157:39, endln:157:43 |vpiName:out4 |vpiFullName:work@delay_example.out4 |vpiActual: @@ -9166,7 +9410,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.b), line:157:44, endln:157:45 |vpiParent: - \_gate: work@nand (work@delay_example.u_nand), line:157:29, endln:157:48 + \_prim_term: , line:157:44, endln:157:45 |vpiName:b |vpiFullName:work@delay_example.b |vpiActual: @@ -9180,7 +9424,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.c), line:157:46, endln:157:47 |vpiParent: - \_gate: work@nand (work@delay_example.u_nand), line:157:29, endln:157:48 + \_prim_term: , line:157:46, endln:157:47 |vpiName:c |vpiFullName:work@delay_example.c |vpiActual: @@ -9195,9 +9439,13 @@ design: (work@gates) |vpiPrimType:7 |vpiDelay: \_operation: , line:159:8, endln:159:22 + |vpiParent: + \_gate: work@buf (work@delay_example.u_buf), line:159:29, endln:159:46 |vpiOpType:37 |vpiOperand: \_operation: , line:159:10, endln:159:15 + |vpiParent: + \_operation: , line:159:8, endln:159:22 |vpiOpType:38 |vpiOperand: \_constant: , line:159:10, endln:159:11 @@ -9219,6 +9467,8 @@ design: (work@gates) |vpiConstType:9 |vpiOperand: \_operation: , line:159:16, endln:159:21 + |vpiParent: + \_operation: , line:159:8, endln:159:22 |vpiOpType:38 |vpiOperand: \_constant: , line:159:16, endln:159:17 @@ -9246,7 +9496,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.out5), line:159:39, endln:159:43 |vpiParent: - \_gate: work@buf (work@delay_example.u_buf), line:159:29, endln:159:46 + \_prim_term: , line:159:39, endln:159:43 |vpiName:out5 |vpiFullName:work@delay_example.out5 |vpiActual: @@ -9260,7 +9510,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.b), line:159:44, endln:159:45 |vpiParent: - \_gate: work@buf (work@delay_example.u_buf), line:159:29, endln:159:46 + \_prim_term: , line:159:44, endln:159:45 |vpiName:b |vpiFullName:work@delay_example.b |vpiActual: @@ -9275,9 +9525,13 @@ design: (work@gates) |vpiPrimType:12 |vpiDelay: \_operation: , line:161:8, endln:161:28 + |vpiParent: + \_gate: work@notif1 (work@delay_example.u_notif1), line:161:29, endln:161:48 |vpiOpType:37 |vpiOperand: \_operation: , line:161:10, endln:161:15 + |vpiParent: + \_operation: , line:161:8, endln:161:28 |vpiOpType:38 |vpiOperand: \_constant: , line:161:10, endln:161:11 @@ -9299,6 +9553,8 @@ design: (work@gates) |vpiConstType:9 |vpiOperand: \_operation: , line:161:16, endln:161:21 + |vpiParent: + \_operation: , line:161:8, endln:161:28 |vpiOpType:38 |vpiOperand: \_constant: , line:161:16, endln:161:17 @@ -9320,6 +9576,8 @@ design: (work@gates) |vpiConstType:9 |vpiOperand: \_operation: , line:161:22, endln:161:27 + |vpiParent: + \_operation: , line:161:8, endln:161:28 |vpiOpType:38 |vpiOperand: \_constant: , line:161:22, endln:161:23 @@ -9347,7 +9605,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.out6), line:161:39, endln:161:43 |vpiParent: - \_gate: work@notif1 (work@delay_example.u_notif1), line:161:29, endln:161:48 + \_prim_term: , line:161:39, endln:161:43 |vpiName:out6 |vpiFullName:work@delay_example.out6 |vpiActual: @@ -9361,7 +9619,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.b), line:161:44, endln:161:45 |vpiParent: - \_gate: work@notif1 (work@delay_example.u_notif1), line:161:29, endln:161:48 + \_prim_term: , line:161:44, endln:161:45 |vpiName:b |vpiFullName:work@delay_example.b |vpiActual: @@ -9375,7 +9633,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@delay_example.c), line:161:46, endln:161:47 |vpiParent: - \_gate: work@notif1 (work@delay_example.u_notif1), line:161:29, endln:161:48 + \_prim_term: , line:161:46, endln:161:47 |vpiName:c |vpiFullName:work@delay_example.c |vpiActual: @@ -9695,7 +9953,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.out1), line:184:13, endln:184:17 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and1), line:184:5, endln:184:28 + \_prim_term: , line:184:13, endln:184:17 |vpiName:out1 |vpiFullName:work@n_in_primitive.out1 |vpiActual: @@ -9709,7 +9967,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in1), line:184:19, endln:184:22 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and1), line:184:5, endln:184:28 + \_prim_term: , line:184:19, endln:184:22 |vpiName:in1 |vpiFullName:work@n_in_primitive.in1 |vpiActual: @@ -9723,7 +9981,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in2), line:184:24, endln:184:27 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and1), line:184:5, endln:184:28 + \_prim_term: , line:184:24, endln:184:27 |vpiName:in2 |vpiFullName:work@n_in_primitive.in2 |vpiActual: @@ -9744,7 +10002,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.out2), line:186:13, endln:186:17 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and2), line:186:5, endln:186:38 + \_prim_term: , line:186:13, endln:186:17 |vpiName:out2 |vpiFullName:work@n_in_primitive.out2 |vpiActual: @@ -9758,7 +10016,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in1), line:186:19, endln:186:22 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and2), line:186:5, endln:186:38 + \_prim_term: , line:186:19, endln:186:22 |vpiName:in1 |vpiFullName:work@n_in_primitive.in1 |vpiActual: @@ -9772,7 +10030,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in2), line:186:24, endln:186:27 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and2), line:186:5, endln:186:38 + \_prim_term: , line:186:24, endln:186:27 |vpiName:in2 |vpiFullName:work@n_in_primitive.in2 |vpiActual: @@ -9786,7 +10044,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in3), line:186:29, endln:186:32 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and2), line:186:5, endln:186:38 + \_prim_term: , line:186:29, endln:186:32 |vpiName:in3 |vpiFullName:work@n_in_primitive.in3 |vpiActual: @@ -9800,7 +10058,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in4), line:186:34, endln:186:37 |vpiParent: - \_gate: work@and (work@n_in_primitive.u_and2), line:186:5, endln:186:38 + \_prim_term: , line:186:34, endln:186:37 |vpiName:in4 |vpiFullName:work@n_in_primitive.in4 |vpiActual: @@ -9821,7 +10079,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.out3), line:188:15, endln:188:19 |vpiParent: - \_gate: work@xnor (work@n_in_primitive.u_xnor1), line:188:6, endln:188:35 + \_prim_term: , line:188:15, endln:188:19 |vpiName:out3 |vpiFullName:work@n_in_primitive.out3 |vpiActual: @@ -9835,7 +10093,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in1), line:188:21, endln:188:24 |vpiParent: - \_gate: work@xnor (work@n_in_primitive.u_xnor1), line:188:6, endln:188:35 + \_prim_term: , line:188:21, endln:188:24 |vpiName:in1 |vpiFullName:work@n_in_primitive.in1 |vpiActual: @@ -9849,7 +10107,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in2), line:188:26, endln:188:29 |vpiParent: - \_gate: work@xnor (work@n_in_primitive.u_xnor1), line:188:6, endln:188:35 + \_prim_term: , line:188:26, endln:188:29 |vpiName:in2 |vpiFullName:work@n_in_primitive.in2 |vpiActual: @@ -9863,7 +10121,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_in_primitive.in3), line:188:31, endln:188:34 |vpiParent: - \_gate: work@xnor (work@n_in_primitive.u_xnor1), line:188:6, endln:188:35 + \_prim_term: , line:188:31, endln:188:34 |vpiName:in3 |vpiFullName:work@n_in_primitive.in3 |vpiActual: @@ -9971,7 +10229,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out), line:214:13, endln:214:16 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf0), line:214:5, endln:214:20 + \_prim_term: , line:214:13, endln:214:16 |vpiName:out |vpiFullName:work@n_out_primitive.out |vpiActual: @@ -9985,7 +10243,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.in), line:214:17, endln:214:19 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf0), line:214:5, endln:214:20 + \_prim_term: , line:214:17, endln:214:19 |vpiName:in |vpiFullName:work@n_out_primitive.in |vpiActual: @@ -10006,7 +10264,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_0), line:216:13, endln:216:18 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 + \_prim_term: , line:216:13, endln:216:18 |vpiName:out_0 |vpiFullName:work@n_out_primitive.out_0 |vpiActual: @@ -10020,7 +10278,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_1), line:216:20, endln:216:25 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 + \_prim_term: , line:216:20, endln:216:25 |vpiName:out_1 |vpiFullName:work@n_out_primitive.out_1 |vpiActual: @@ -10034,7 +10292,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_2), line:216:27, endln:216:32 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 + \_prim_term: , line:216:27, endln:216:32 |vpiName:out_2 |vpiFullName:work@n_out_primitive.out_2 |vpiActual: @@ -10048,7 +10306,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_3), line:216:34, endln:216:39 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 + \_prim_term: , line:216:34, endln:216:39 |vpiName:out_3 |vpiFullName:work@n_out_primitive.out_3 |vpiActual: @@ -10062,7 +10320,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.in), line:216:41, endln:216:43 |vpiParent: - \_gate: work@buf (work@n_out_primitive.u_buf1), line:216:5, endln:216:44 + \_prim_term: , line:216:41, endln:216:43 |vpiName:in |vpiFullName:work@n_out_primitive.in |vpiActual: @@ -10083,7 +10341,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_a), line:218:13, endln:218:18 |vpiParent: - \_gate: work@not (work@n_out_primitive.u_not0), line:218:5, endln:218:37 + \_prim_term: , line:218:13, endln:218:18 |vpiName:out_a |vpiFullName:work@n_out_primitive.out_a |vpiActual: @@ -10097,7 +10355,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_b), line:218:20, endln:218:25 |vpiParent: - \_gate: work@not (work@n_out_primitive.u_not0), line:218:5, endln:218:37 + \_prim_term: , line:218:20, endln:218:25 |vpiName:out_b |vpiFullName:work@n_out_primitive.out_b |vpiActual: @@ -10111,7 +10369,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.out_c), line:218:27, endln:218:32 |vpiParent: - \_gate: work@not (work@n_out_primitive.u_not0), line:218:5, endln:218:37 + \_prim_term: , line:218:27, endln:218:32 |vpiName:out_c |vpiFullName:work@n_out_primitive.out_c |vpiActual: @@ -10125,7 +10383,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@n_out_primitive.in), line:218:34, endln:218:36 |vpiParent: - \_gate: work@not (work@n_out_primitive.u_not0), line:218:5, endln:218:37 + \_prim_term: , line:218:34, endln:218:36 |vpiName:in |vpiFullName:work@n_out_primitive.in |vpiActual: @@ -10264,7 +10522,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@half_adder.Sum), line:225:13, endln:225:16 |vpiParent: - \_gate: work@xor (work@half_adder.U1), line:225:12, endln:225:23 + \_prim_term: , line:225:13, endln:225:16 |vpiName:Sum |vpiFullName:work@half_adder.Sum |vpiActual: @@ -10278,7 +10536,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@half_adder.A), line:225:18, endln:225:19 |vpiParent: - \_gate: work@xor (work@half_adder.U1), line:225:12, endln:225:23 + \_prim_term: , line:225:18, endln:225:19 |vpiName:A |vpiFullName:work@half_adder.A |vpiActual: @@ -10292,7 +10550,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@half_adder.B), line:225:21, endln:225:22 |vpiParent: - \_gate: work@xor (work@half_adder.U1), line:225:12, endln:225:23 + \_prim_term: , line:225:21, endln:225:22 |vpiName:B |vpiFullName:work@half_adder.B |vpiActual: @@ -10319,7 +10577,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@half_adder.Carry), line:226:13, endln:226:18 |vpiParent: - \_gate: work@and (work@half_adder.U2), line:226:12, endln:226:25 + \_prim_term: , line:226:13, endln:226:18 |vpiName:Carry |vpiFullName:work@half_adder.Carry |vpiActual: @@ -10333,7 +10591,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@half_adder.A), line:226:20, endln:226:21 |vpiParent: - \_gate: work@and (work@half_adder.U2), line:226:12, endln:226:25 + \_prim_term: , line:226:20, endln:226:21 |vpiName:A |vpiFullName:work@half_adder.A |vpiActual: @@ -10347,7 +10605,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@half_adder.B), line:226:23, endln:226:24 |vpiParent: - \_gate: work@and (work@half_adder.U2), line:226:12, endln:226:25 + \_prim_term: , line:226:23, endln:226:24 |vpiName:B |vpiFullName:work@half_adder.B |vpiActual: @@ -10405,10 +10663,14 @@ design: (work@gates) |vpiTopModule:1 |vpiPrimitiveArray: \_gate_array: (work@gate_array.n_gate), line:233:6, endln:233:34 + |vpiParent: + \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 |vpiName:n_gate |vpiFullName:work@gate_array.n_gate |vpiRange: \_range: , line:233:13, endln:233:18 + |vpiParent: + \_gate_array: (work@gate_array.n_gate), line:233:6, endln:233:34 |vpiLeftRange: \_constant: , line:233:14, endln:233:15 |vpiParent: @@ -10428,7 +10690,7 @@ design: (work@gates) |vpiPrimitive: \_gate: work@nand (work@gate_array.n_gate), line:233:6, endln:233:34 |vpiParent: - \_module_inst: work@gate_array (work@gate_array), file:${SURELOG_DIR}/tests/Gates/dut.sv, line:230:1, endln:235:10 + \_gate_array: (work@gate_array.n_gate), line:233:6, endln:233:34 |vpiDefName:work@nand |vpiName:n_gate |vpiFullName:work@gate_array.n_gate @@ -10441,7 +10703,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gate_array.out), line:233:20, endln:233:23 |vpiParent: - \_gate: work@nand (work@gate_array.n_gate), line:233:6, endln:233:34 + \_prim_term: , line:233:20, endln:233:23 |vpiName:out |vpiFullName:work@gate_array.out |vpiActual: @@ -10455,7 +10717,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gate_array.in1), line:233:25, endln:233:28 |vpiParent: - \_gate: work@nand (work@gate_array.n_gate), line:233:6, endln:233:34 + \_prim_term: , line:233:25, endln:233:28 |vpiName:in1 |vpiFullName:work@gate_array.in1 |vpiActual: @@ -10469,7 +10731,7 @@ design: (work@gates) |vpiExpr: \_ref_obj: (work@gate_array.in2), line:233:30, endln:233:33 |vpiParent: - \_gate: work@nand (work@gate_array.n_gate), line:233:6, endln:233:34 + \_prim_term: , line:233:30, endln:233:33 |vpiName:in2 |vpiFullName:work@gate_array.in2 |vpiActual: diff --git a/tests/GenNet/GenNet.log b/tests/GenNet/GenNet.log index 2d8c74afcf..13478bee33 100644 --- a/tests/GenNet/GenNet.log +++ b/tests/GenNet/GenNet.log @@ -334,6 +334,8 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@prim_subreg_arb (m1), line:22:4, endln:22:6 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenNet/dut.sv, line:17:1, endln:23:10 |vpiName:m1 |vpiDefName:work@prim_subreg_arb |vpiActual: diff --git a/tests/GenScopeFunc/GenScopeFunc.log b/tests/GenScopeFunc/GenScopeFunc.log index fe651278b4..eacf428e02 100644 --- a/tests/GenScopeFunc/GenScopeFunc.log +++ b/tests/GenScopeFunc/GenScopeFunc.log @@ -239,6 +239,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@mod (c), line:15:8, endln:15:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeFunc/dut.sv, line:14:1, endln:16:10 |vpiName:c |vpiDefName:work@mod |vpiActual: diff --git a/tests/GenerateInterface/GenerateInterface.log b/tests/GenerateInterface/GenerateInterface.log index 8005da8646..4866e8e149 100644 --- a/tests/GenerateInterface/GenerateInterface.log +++ b/tests/GenerateInterface/GenerateInterface.log @@ -1350,6 +1350,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@abc_if (intf), line:17:10, endln:17:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:16:1, endln:19:10 |vpiName:intf |vpiDefName:work@abc_if |vpiActual: @@ -1435,6 +1437,8 @@ design: (work@top) |vpiConstType:9 |vpiRefModule: \_ref_module: work@pins_if (intf), line:35:26, endln:35:30 + |vpiParent: + \_module_inst: work@top2 (work@top2), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:34:1, endln:43:10 |vpiName:intf |vpiDefName:work@pins_if |vpiActual: diff --git a/tests/GenerateRegion/GenerateRegion.log b/tests/GenerateRegion/GenerateRegion.log index f0bab91d57..8d4e59647d 100644 --- a/tests/GenerateRegion/GenerateRegion.log +++ b/tests/GenerateRegion/GenerateRegion.log @@ -1236,6 +1236,8 @@ design: (work@oh_delay) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@test (t), line:73:11, endln:73:12 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenerateRegion/dut.sv, line:69:1, endln:74:10 |vpiName:t |vpiDefName:work@test |vpiActual: diff --git a/tests/GenerateUnnamed/GenerateUnnamed.log b/tests/GenerateUnnamed/GenerateUnnamed.log index 038d3eeab0..ea0a63aba2 100644 --- a/tests/GenerateUnnamed/GenerateUnnamed.log +++ b/tests/GenerateUnnamed/GenerateUnnamed.log @@ -1053,7 +1053,7 @@ enum_const 5 enum_typespec 1 enum_var 1 function 9 -gate 8 +gate 16 gen_scope 17 gen_scope_array 17 int_typespec 17 @@ -1566,6 +1566,13 @@ design: (work@test1) |vpiName:c |vpiFullName:work@test1.c |vpiNetType:1 + |vpiPrimitive: + \_gate: (work@test1.sg1), line:11:6, endln:11:18 + |vpiParent: + \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 + |vpiName:sg1 + |vpiFullName:work@test1.sg1 + |vpiPrimType:4 |uhdmallModules: \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 |vpiParent: @@ -1639,6 +1646,13 @@ design: (work@test1) |vpiName:c |vpiFullName:work@test2.c |vpiNetType:1 + |vpiPrimitive: + \_gate: (work@test2.sg1), line:70:6, endln:70:18 + |vpiParent: + \_module_inst: work@test2 (work@test2), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:60:1, endln:115:10 + |vpiName:sg1 + |vpiFullName:work@test2.sg1 + |vpiPrimType:4 |uhdmtopModules: \_module_inst: work@test1 (work@test1), file:${SURELOG_DIR}/tests/GenerateUnnamed/top.v, line:1:1, endln:56:10 |vpiName:work@test1 diff --git a/tests/HierPathBind/HierPathBind.log b/tests/HierPathBind/HierPathBind.log index 6df3ce62a9..ccfe51af2c 100644 --- a/tests/HierPathBind/HierPathBind.log +++ b/tests/HierPathBind/HierPathBind.log @@ -312,6 +312,8 @@ design: (work@top) \_logic_net: (work@top.o), line:5:26, endln:5:27 |vpiRefModule: \_ref_module: work@dut (d), line:12:8, endln:12:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:d |vpiDefName:work@dut |vpiActual: diff --git a/tests/HierPathEval/HierPathEval.log b/tests/HierPathEval/HierPathEval.log index 5fdd4e8b05..aa1ed03a2f 100644 --- a/tests/HierPathEval/HierPathEval.log +++ b/tests/HierPathEval/HierPathEval.log @@ -625,6 +625,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_pad_attr (u_prim_pad_attr), line:52:6, endln:52:21 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathEval/dut.sv, line:46:1, endln:55:10 |vpiName:u_prim_pad_attr |vpiDefName:work@prim_pad_attr |vpiActual: diff --git a/tests/HierPathOverride/HierPathOverride.log b/tests/HierPathOverride/HierPathOverride.log index 43d946512c..8a7d8ddc8d 100644 --- a/tests/HierPathOverride/HierPathOverride.log +++ b/tests/HierPathOverride/HierPathOverride.log @@ -1377,6 +1377,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_pad_attr (u_prim_pad_attr), line:49:7, endln:49:22 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathOverride/dut.sv, line:44:1, endln:50:10 |vpiName:u_prim_pad_attr |vpiDefName:work@prim_pad_attr |vpiActual: diff --git a/tests/HighConnPart/HighConnPart.log b/tests/HighConnPart/HighConnPart.log index 7bcd3e8569..88185de3d4 100644 --- a/tests/HighConnPart/HighConnPart.log +++ b/tests/HighConnPart/HighConnPart.log @@ -394,6 +394,8 @@ design: (work@Device) |vpiConstType:9 |vpiRefModule: \_ref_module: work@Helper (instance2), line:12:12, endln:12:21 + |vpiParent: + \_module_inst: work@Device (work@Device), file:${SURELOG_DIR}/tests/HighConnPart/dut.sv, line:3:1, endln:19:10 |vpiName:instance2 |vpiDefName:work@Helper |vpiActual: diff --git a/tests/Implicit/Implicit.log b/tests/Implicit/Implicit.log index 66036269f7..bf536e3b94 100644 --- a/tests/Implicit/Implicit.log +++ b/tests/Implicit/Implicit.log @@ -103,7 +103,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === design 1 -gate 2 +gate 4 logic_net 10 logic_typespec 2 module_inst 2 @@ -115,13 +115,13 @@ ref_obj 5 === UHDM Object Stats Begin (Elaborated Model) === design 1 -gate 2 +gate 6 logic_net 10 logic_typespec 2 module_inst 2 port 5 -prim_term 5 -ref_obj 5 +prim_term 10 +ref_obj 10 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Implicit/slpp_all/surelog.uhdm ... @@ -132,182 +132,195 @@ ref_obj 5 [INF:UH0711] Decompiling UHDM... ====== UHDM ======= -design: (work@dff_from_nand), id:18 +design: (work@dff_from_nand), id:20 |vpiElaborated:1 |vpiName:work@dff_from_nand |uhdmallModules: -\_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 +\_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiParent: - \_design: (work@dff_from_nand), id:18 + \_design: (work@dff_from_nand), id:20 |vpiFullName:work@dff_from_nand |vpiDefName:work@dff_from_nand |vpiNet: - \_logic_net: (work@dff_from_nand.Q), id:20, line:3:6, endln:3:7 + \_logic_net: (work@dff_from_nand.Q), id:22, line:3:6, endln:3:7 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:Q |vpiFullName:work@dff_from_nand.Q |vpiNetType:1 |vpiNet: - \_logic_net: (work@dff_from_nand.Q_BAR), id:21, line:3:8, endln:3:13 + \_logic_net: (work@dff_from_nand.Q_BAR), id:23, line:3:8, endln:3:13 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:Q_BAR |vpiFullName:work@dff_from_nand.Q_BAR |vpiNetType:1 |vpiNet: - \_logic_net: (work@dff_from_nand.D), id:22, line:4:6, endln:4:7 + \_logic_net: (work@dff_from_nand.D), id:24, line:4:6, endln:4:7 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:D |vpiFullName:work@dff_from_nand.D |vpiNetType:48 |vpiNet: - \_logic_net: (work@dff_from_nand.CLK), id:23, line:4:8, endln:4:11 + \_logic_net: (work@dff_from_nand.CLK), id:25, line:4:8, endln:4:11 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:19, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiNetType:48 + |vpiPrimitive: + \_gate: (work@dff_from_nand.U1), id:0, line:6:6, endln:6:18 + |vpiParent: + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + |vpiName:U1 + |vpiFullName:work@dff_from_nand.U1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@dff_from_nand), id:1, line:7:5, endln:7:15 + |vpiParent: + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:21, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + |vpiFullName:work@dff_from_nand + |vpiPrimType:8 |uhdmtopModules: -\_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 +\_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:work@dff_from_nand |vpiDefName:work@dff_from_nand |vpiTop:1 |vpiNet: - \_logic_net: (work@dff_from_nand.Q), id:1, line:3:6, endln:3:7 + \_logic_net: (work@dff_from_nand.Q), id:3, line:3:6, endln:3:7 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: - \_logic_typespec: , id:0, line:3:1, endln:3:5 + \_logic_typespec: , id:2, line:3:1, endln:3:5 |vpiName:Q |vpiFullName:work@dff_from_nand.Q |vpiNetType:1 |vpiNet: - \_logic_net: (work@dff_from_nand.Q_BAR), id:2, line:3:8, endln:3:13 + \_logic_net: (work@dff_from_nand.Q_BAR), id:4, line:3:8, endln:3:13 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: - \_logic_typespec: , id:0, line:3:1, endln:3:5 + \_logic_typespec: , id:2, line:3:1, endln:3:5 |vpiName:Q_BAR |vpiFullName:work@dff_from_nand.Q_BAR |vpiNetType:1 |vpiNet: - \_logic_net: (work@dff_from_nand.D), id:4, line:4:6, endln:4:7 + \_logic_net: (work@dff_from_nand.D), id:6, line:4:6, endln:4:7 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: - \_logic_typespec: , id:3, line:4:1, endln:4:4 + \_logic_typespec: , id:5, line:4:1, endln:4:4 |vpiName:D |vpiFullName:work@dff_from_nand.D |vpiNetType:48 |vpiNet: - \_logic_net: (work@dff_from_nand.CLK), id:5, line:4:8, endln:4:11 + \_logic_net: (work@dff_from_nand.CLK), id:7, line:4:8, endln:4:11 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiTypespec: - \_logic_typespec: , id:3, line:4:1, endln:4:4 + \_logic_typespec: , id:5, line:4:1, endln:4:4 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiNetType:48 |vpiNet: - \_logic_net: (work@dff_from_nand.X), id:8, line:6:10, endln:6:11 + \_logic_net: (work@dff_from_nand.X), id:10, line:6:10, endln:6:11 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiNetType:1 |vpiNet: - \_logic_net: (work@dff_from_nand.X_BAR), id:15, line:7:6, endln:7:11 + \_logic_net: (work@dff_from_nand.X_BAR), id:17, line:7:6, endln:7:11 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiName:X_BAR |vpiFullName:work@dff_from_nand.X_BAR |vpiNetType:1 |vpiTopModule:1 |vpiPrimitive: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_gate: work@nand (work@dff_from_nand.U1), id:34, line:6:6, endln:6:18 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiDefName:work@nand |vpiName:U1 |vpiFullName:work@dff_from_nand.U1 |vpiPrimType:2 |vpiPrimTerm: - \_prim_term: , id:26, line:6:10, endln:6:11 + \_prim_term: , id:35, line:6:10, endln:6:11 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_gate: work@nand (work@dff_from_nand.U1), id:34, line:6:6, endln:6:18 |vpiDirection:2 |vpiExpr: - \_ref_obj: (work@dff_from_nand.X), id:7, line:6:10, endln:6:11 + \_ref_obj: (work@dff_from_nand.X), id:36, line:6:10, endln:6:11 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_prim_term: , id:35, line:6:10, endln:6:11 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiActual: - \_logic_net: (work@dff_from_nand.X), id:8, line:6:10, endln:6:11 + \_logic_net: (work@dff_from_nand.X), id:10, line:6:10, endln:6:11 |vpiPrimTerm: - \_prim_term: , id:27, line:6:12, endln:6:13 + \_prim_term: , id:37, line:6:12, endln:6:13 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_gate: work@nand (work@dff_from_nand.U1), id:34, line:6:6, endln:6:18 |vpiDirection:1 |vpiTermIndex:1 |vpiExpr: - \_ref_obj: (work@dff_from_nand.D), id:10, line:6:12, endln:6:13 + \_ref_obj: (work@dff_from_nand.D), id:38, line:6:12, endln:6:13 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_prim_term: , id:37, line:6:12, endln:6:13 |vpiName:D |vpiFullName:work@dff_from_nand.D |vpiActual: - \_logic_net: (work@dff_from_nand.D), id:4, line:4:6, endln:4:7 + \_logic_net: (work@dff_from_nand.D), id:6, line:4:6, endln:4:7 |vpiPrimTerm: - \_prim_term: , id:28, line:6:14, endln:6:17 + \_prim_term: , id:39, line:6:14, endln:6:17 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_gate: work@nand (work@dff_from_nand.U1), id:34, line:6:6, endln:6:18 |vpiDirection:1 |vpiTermIndex:2 |vpiExpr: - \_ref_obj: (work@dff_from_nand.CLK), id:12, line:6:14, endln:6:17 + \_ref_obj: (work@dff_from_nand.CLK), id:40, line:6:14, endln:6:17 |vpiParent: - \_gate: work@nand (work@dff_from_nand.U1), id:25, line:6:6, endln:6:18 + \_prim_term: , id:39, line:6:14, endln:6:17 |vpiName:CLK |vpiFullName:work@dff_from_nand.CLK |vpiActual: - \_logic_net: (work@dff_from_nand.CLK), id:5, line:4:8, endln:4:11 + \_logic_net: (work@dff_from_nand.CLK), id:7, line:4:8, endln:4:11 |vpiPrimitive: - \_gate: work@not (work@dff_from_nand.), id:29, line:7:5, endln:7:15 + \_gate: work@not (work@dff_from_nand.), id:41, line:7:5, endln:7:15 |vpiParent: - \_module_inst: work@dff_from_nand (work@dff_from_nand), id:24, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 + \_module_inst: work@dff_from_nand (work@dff_from_nand), id:26, file:${SURELOG_DIR}/tests/Implicit/dut.sv, line:2:1, endln:8:10 |vpiDefName:work@not |vpiFullName:work@dff_from_nand. |vpiPrimType:8 |vpiPrimTerm: - \_prim_term: , id:30, line:7:6, endln:7:11 + \_prim_term: , id:42, line:7:6, endln:7:11 |vpiParent: - \_gate: work@not (work@dff_from_nand.), id:29, line:7:5, endln:7:15 + \_gate: work@not (work@dff_from_nand.), id:41, line:7:5, endln:7:15 |vpiDirection:2 |vpiExpr: - \_ref_obj: (work@dff_from_nand.X_BAR), id:14, line:7:6, endln:7:11 + \_ref_obj: (work@dff_from_nand.X_BAR), id:43, line:7:6, endln:7:11 |vpiParent: - \_gate: work@not (work@dff_from_nand.), id:29, line:7:5, endln:7:15 + \_prim_term: , id:42, line:7:6, endln:7:11 |vpiName:X_BAR |vpiFullName:work@dff_from_nand.X_BAR |vpiActual: - \_logic_net: (work@dff_from_nand.X_BAR), id:15, line:7:6, endln:7:11 + \_logic_net: (work@dff_from_nand.X_BAR), id:17, line:7:6, endln:7:11 |vpiPrimTerm: - \_prim_term: , id:31, line:7:13, endln:7:14 + \_prim_term: , id:44, line:7:13, endln:7:14 |vpiParent: - \_gate: work@not (work@dff_from_nand.), id:29, line:7:5, endln:7:15 + \_gate: work@not (work@dff_from_nand.), id:41, line:7:5, endln:7:15 |vpiDirection:1 |vpiTermIndex:1 |vpiExpr: - \_ref_obj: (work@dff_from_nand.X), id:17, line:7:13, endln:7:14 + \_ref_obj: (work@dff_from_nand.X), id:45, line:7:13, endln:7:14 |vpiParent: - \_gate: work@not (work@dff_from_nand.), id:29, line:7:5, endln:7:15 + \_prim_term: , id:44, line:7:13, endln:7:14 |vpiName:X |vpiFullName:work@dff_from_nand.X |vpiActual: - \_logic_net: (work@dff_from_nand.X), id:8, line:6:10, endln:6:11 + \_logic_net: (work@dff_from_nand.X), id:10, line:6:10, endln:6:11 =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ImplicitPorts2/ImplicitPorts2.log b/tests/ImplicitPorts2/ImplicitPorts2.log index 13677f1c7d..e18001ebc8 100644 --- a/tests/ImplicitPorts2/ImplicitPorts2.log +++ b/tests/ImplicitPorts2/ImplicitPorts2.log @@ -255,6 +255,8 @@ design: (work@implicit) |vpiNetType:1 |vpiRefModule: \_ref_module: work@dff (u0), line:6:7, endln:6:9 + |vpiParent: + \_module_inst: work@implicit (work@implicit), file:${SURELOG_DIR}/tests/ImplicitPorts2/dut.sv, line:1:1, endln:8:10 |vpiName:u0 |vpiDefName:work@dff |vpiActual: diff --git a/tests/IntegerConcat/IntegerConcat.log b/tests/IntegerConcat/IntegerConcat.log index 53692bb492..fe7501f1c4 100644 --- a/tests/IntegerConcat/IntegerConcat.log +++ b/tests/IntegerConcat/IntegerConcat.log @@ -1277,6 +1277,8 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@test (t), line:25:29, endln:25:30 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/IntegerConcat/dut.sv, line:22:1, endln:26:10 |vpiName:t |vpiDefName:work@test |vpiActual: diff --git a/tests/InterfAlways/InterfAlways.log b/tests/InterfAlways/InterfAlways.log index 4609f446c4..434cfade2c 100644 --- a/tests/InterfAlways/InterfAlways.log +++ b/tests/InterfAlways/InterfAlways.log @@ -228,6 +228,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@sw_test_status_if (u_sw), line:8:22, endln:8:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfAlways/dut.sv, line:7:1, endln:9:10 |vpiName:u_sw |vpiDefName:work@sw_test_status_if |vpiActual: diff --git a/tests/InterfHierPath/InterfHierPath.log b/tests/InterfHierPath/InterfHierPath.log index 621ac1b846..47970d04ee 100644 --- a/tests/InterfHierPath/InterfHierPath.log +++ b/tests/InterfHierPath/InterfHierPath.log @@ -238,6 +238,8 @@ design: (work@or_ex) |vpiName:a |vpiRefModule: \_ref_module: work@logic_gate_if (lg), line:12:17, endln:12:19 + |vpiParent: + \_module_inst: work@or_ex (work@or_ex), file:${SURELOG_DIR}/tests/InterfHierPath/dut.sv, line:8:1, endln:16:10 |vpiName:lg |vpiDefName:work@logic_gate_if |vpiActual: diff --git a/tests/InterfType/InterfType.log b/tests/InterfType/InterfType.log index 4a55605032..e3f816eeac 100644 --- a/tests/InterfType/InterfType.log +++ b/tests/InterfType/InterfType.log @@ -219,12 +219,16 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@tnoc_types (i_types), line:15:16, endln:15:23 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiName:i_types |vpiDefName:work@tnoc_types |vpiActual: \_interface_inst: work@tnoc_types (work@tnoc_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:1:1, endln:4:13 |vpiRefModule: \_ref_module: work@tnoc_flit_if (tnoc), line:16:14, endln:16:18 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiName:tnoc |vpiDefName:work@tnoc_flit_if |vpiActual: diff --git a/tests/InterfTypeBad/InterfTypeBad.log b/tests/InterfTypeBad/InterfTypeBad.log index 847206aad6..92db725239 100644 --- a/tests/InterfTypeBad/InterfTypeBad.log +++ b/tests/InterfTypeBad/InterfTypeBad.log @@ -225,6 +225,8 @@ design: (work@dut) |vpiFullName:work@dut.i_types |vpiRefModule: \_ref_module: work@tnoc_flit_if (tnoc), line:16:14, endln:16:18 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfTypeBad/dut.sv, line:13:1, endln:18:10 |vpiName:tnoc |vpiDefName:work@tnoc_flit_if |vpiActual: diff --git a/tests/InterfaceElab/InterfaceElab.log b/tests/InterfaceElab/InterfaceElab.log index 37bce2629e..6a8a202c3b 100644 --- a/tests/InterfaceElab/InterfaceElab.log +++ b/tests/InterfaceElab/InterfaceElab.log @@ -345,6 +345,8 @@ design: (work@testharness) |vpiDefName:work@peripherals |vpiRefModule: \_ref_module: work@REG_BUS (reg_bus), line:25:7, endln:25:14 + |vpiParent: + \_module_inst: work@peripherals (work@peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:21:1, endln:29:10 |vpiName:reg_bus |vpiDefName:work@REG_BUS |vpiActual: @@ -358,6 +360,8 @@ design: (work@testharness) \_logic_net: (work@testharness.i_peripherals.clk_i), line:25:16, endln:25:21 |vpiRefModule: \_ref_module: work@apb_to_reg (i_apb_to_reg), line:27:12, endln:27:24 + |vpiParent: + \_module_inst: work@peripherals (work@peripherals), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:21:1, endln:29:10 |vpiName:i_apb_to_reg |vpiDefName:work@apb_to_reg |vpiActual: @@ -378,6 +382,8 @@ design: (work@testharness) |vpiDefName:work@testharness |vpiRefModule: \_ref_module: work@peripherals (i_peripherals), line:34:16, endln:34:29 + |vpiParent: + \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 |vpiName:i_peripherals |vpiDefName:work@peripherals |vpiActual: diff --git a/tests/InterfaceModExp/InterfaceModExp.log b/tests/InterfaceModExp/InterfaceModExp.log index 2c24466514..c42408f6ed 100644 --- a/tests/InterfaceModExp/InterfaceModExp.log +++ b/tests/InterfaceModExp/InterfaceModExp.log @@ -538,12 +538,16 @@ design: (work@top) |vpiName:$display |vpiRefModule: \_ref_module: work@I (inst), line:15:5, endln:15:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiName:inst |vpiDefName:work@I |vpiActual: \_interface_inst: work@I (work@I), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:1:1, endln:7:13 |vpiRefModule: \_ref_module: work@sub (s), line:16:7, endln:16:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiName:s |vpiDefName:work@sub |vpiActual: diff --git a/tests/InterfaceModPort/InterfaceModPort.log b/tests/InterfaceModPort/InterfaceModPort.log index 51a4478439..c8342e6f7f 100644 --- a/tests/InterfaceModPort/InterfaceModPort.log +++ b/tests/InterfaceModPort/InterfaceModPort.log @@ -2109,6 +2109,8 @@ design: (work@interface_modports) |vpiAlwaysType:1 |vpiRefModule: \_ref_module: work@mem_if (miff), line:119:8, endln:119:12 + |vpiParent: + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:miff |vpiDefName:work@mem_if |vpiActual: @@ -2122,6 +2124,8 @@ design: (work@interface_modports) \_logic_var: (work@interface_modports.clk), line:114:7, endln:114:14 |vpiRefModule: \_ref_module: work@memory_ctrl (U_ctrl), line:120:13, endln:120:19 + |vpiParent: + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:U_ctrl |vpiDefName:work@memory_ctrl |vpiActual: @@ -2135,6 +2139,8 @@ design: (work@interface_modports) \_logic_net: (miff) |vpiRefModule: \_ref_module: work@memory_model (U_model), line:121:14, endln:121:21 + |vpiParent: + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:U_model |vpiDefName:work@memory_model |vpiActual: @@ -2148,6 +2154,8 @@ design: (work@interface_modports) \_logic_net: (miff) |vpiRefModule: \_ref_module: work@test (U_test), line:122:8, endln:122:14 + |vpiParent: + \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 |vpiName:U_test |vpiDefName:work@test |vpiActual: diff --git a/tests/InterfaceProcess/InterfaceProcess.log b/tests/InterfaceProcess/InterfaceProcess.log index 2396e9f576..f3c75ff2c8 100644 --- a/tests/InterfaceProcess/InterfaceProcess.log +++ b/tests/InterfaceProcess/InterfaceProcess.log @@ -243,6 +243,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@sw_test_status_if (u_sw), line:14:22, endln:14:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceProcess/dut.sv, line:13:1, endln:15:10 |vpiName:u_sw |vpiDefName:work@sw_test_status_if |vpiActual: diff --git a/tests/InvalidTypeParam/InvalidTypeParam.log b/tests/InvalidTypeParam/InvalidTypeParam.log index 2bc81e0d41..f75834080d 100644 --- a/tests/InvalidTypeParam/InvalidTypeParam.log +++ b/tests/InvalidTypeParam/InvalidTypeParam.log @@ -145,6 +145,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@Interface (intf), line:6:20, endln:6:24 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InvalidTypeParam/dut.sv, line:5:1, endln:7:10 |vpiName:intf |vpiDefName:work@Interface |vpiActual: diff --git a/tests/LargeHex/LargeHex.log b/tests/LargeHex/LargeHex.log index 73411e91e6..f7a1d218d1 100644 --- a/tests/LargeHex/LargeHex.log +++ b/tests/LargeHex/LargeHex.log @@ -1277,6 +1277,8 @@ design: (work@tlul_socket_1n) |vpiNetType:36 |vpiRefModule: \_ref_module: work@tlul_fifo_sync (fifo_d), line:16:7, endln:16:13 + |vpiParent: + \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/LargeHex/dut.sv, line:6:1, endln:18:10 |vpiName:fifo_d |vpiDefName:work@tlul_fifo_sync |vpiActual: diff --git a/tests/LargeValue2Struct/LargeValue2Struct.log b/tests/LargeValue2Struct/LargeValue2Struct.log index 59524f08ee..ac39e04eab 100644 --- a/tests/LargeValue2Struct/LargeValue2Struct.log +++ b/tests/LargeValue2Struct/LargeValue2Struct.log @@ -1412,6 +1412,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_sec_anchor_flop (u_key_out_anchor), line:28:5, endln:28:21 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LargeValue2Struct/dut.sv, line:21:1, endln:30:10 |vpiName:u_key_out_anchor |vpiDefName:work@prim_sec_anchor_flop |vpiActual: diff --git a/tests/LibraryIntercon/LibraryIntercon.log b/tests/LibraryIntercon/LibraryIntercon.log index 03510e8452..31de67a5c6 100644 --- a/tests/LibraryIntercon/LibraryIntercon.log +++ b/tests/LibraryIntercon/LibraryIntercon.log @@ -9,47 +9,47 @@ LIB: work ${SURELOG_DIR}/tests/LibraryIntercon/lib.map LIB: realLib - ${SURELOG_DIR}/tests/LibraryIntercon/driver.svr ${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr + ${SURELOG_DIR}/tests/LibraryIntercon/driver.svr LIB: logicLib ${SURELOG_DIR}/tests/LibraryIntercon/driver.sv - ${SURELOG_DIR}/tests/LibraryIntercon/top.sv ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv + ${SURELOG_DIR}/tests/LibraryIntercon/top.sv [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/lib.map". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". - [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv". -[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". -[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top". +[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg". [WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp". +[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top". + [INF:CP0300] Compilation... [INF:CP0301] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: Compile package "NetsPkg". diff --git a/tests/LocalParam/LocalParam.log b/tests/LocalParam/LocalParam.log index 822c3ffffb..23a03e5b88 100644 --- a/tests/LocalParam/LocalParam.log +++ b/tests/LocalParam/LocalParam.log @@ -1209,6 +1209,8 @@ design: (work@top) \_logic_typespec: , line:1:49, endln:1:52 |vpiRefModule: \_ref_module: work@assigner (asgn0), line:2:26, endln:2:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:asgn0 |vpiDefName:work@assigner |vpiActual: @@ -1231,6 +1233,8 @@ design: (work@top) \_logic_net: (work@top.o1), line:1:38, endln:1:40 |vpiRefModule: \_ref_module: work@assigner (asgn1), line:3:26, endln:3:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LocalParam/dut.sv, line:1:1, endln:4:10 |vpiName:asgn1 |vpiDefName:work@assigner |vpiActual: diff --git a/tests/LogicSize/LogicSize.log b/tests/LogicSize/LogicSize.log index 0820b8e977..346786aa57 100644 --- a/tests/LogicSize/LogicSize.log +++ b/tests/LogicSize/LogicSize.log @@ -303,6 +303,8 @@ design: (work@top) \_logic_typespec: , line:6:19, endln:6:24 |vpiRefModule: \_ref_module: work@dut (u_dut), line:10:6, endln:10:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicSize/dut.sv, line:6:1, endln:13:10 |vpiName:u_dut |vpiDefName:work@dut |vpiActual: diff --git a/tests/LongHex/LongHex.log b/tests/LongHex/LongHex.log index 98e0806d9e..a8d3c6ed89 100644 --- a/tests/LongHex/LongHex.log +++ b/tests/LongHex/LongHex.log @@ -631,6 +631,8 @@ design: (work@aes_core) |vpiDefName:work@aes_core |vpiRefModule: \_ref_module: work@aes_cipher_core (u_aes_cipher_core), line:14:6, endln:14:23 + |vpiParent: + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/LongHex/dut.sv, line:11:1, endln:15:10 |vpiName:u_aes_cipher_core |vpiDefName:work@aes_cipher_core |vpiActual: diff --git a/tests/Loop/Loop.log b/tests/Loop/Loop.log index 94b427839e..ef768ecf60 100644 --- a/tests/Loop/Loop.log +++ b/tests/Loop/Loop.log @@ -205,6 +205,8 @@ design: (work@top) |vpiDefName:work@loop |vpiRefModule: \_ref_module: work@loop (u1), line:7:9, endln:7:11 + |vpiParent: + \_module_inst: work@loop (work@loop), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:6:1, endln:8:10 |vpiName:u1 |vpiDefName:work@loop |vpiActual: @@ -246,12 +248,16 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@test (u1), line:2:9, endln:2:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiName:u1 |vpiDefName:work@test |vpiActual: \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:10:1, endln:16:10 |vpiRefModule: \_ref_module: work@loop (u2), line:3:9, endln:3:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/Loop/dut.sv, line:1:1, endln:4:10 |vpiName:u2 |vpiDefName:work@loop |vpiActual: diff --git a/tests/LoopParamOver/LoopParamOver.log b/tests/LoopParamOver/LoopParamOver.log index fb403e30c1..bea6c643bd 100644 --- a/tests/LoopParamOver/LoopParamOver.log +++ b/tests/LoopParamOver/LoopParamOver.log @@ -312,6 +312,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@Foo (sub), line:12:16, endln:12:19 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LoopParamOver/dut.sv, line:8:1, endln:13:10 |vpiName:sub |vpiDefName:work@Foo |vpiActual: diff --git a/tests/MaskNeg/MaskNeg.log b/tests/MaskNeg/MaskNeg.log index e64e3772e5..39b0cd17f1 100644 --- a/tests/MaskNeg/MaskNeg.log +++ b/tests/MaskNeg/MaskNeg.log @@ -172,6 +172,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (u_dut), line:8:6, endln:8:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MaskNeg/dut.sv, line:5:1, endln:9:10 |vpiName:u_dut |vpiDefName:work@dut |vpiActual: diff --git a/tests/ModPortHighConn/ModPortHighConn.log b/tests/ModPortHighConn/ModPortHighConn.log index 71f3b3acdf..7d66533c34 100644 --- a/tests/ModPortHighConn/ModPortHighConn.log +++ b/tests/ModPortHighConn/ModPortHighConn.log @@ -134,6 +134,8 @@ design: (work@top) |vpiNetType:1 |vpiRefModule: \_ref_module: work@moduleA (instanceA), line:7:13, endln:7:22 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:instanceA |vpiDefName:work@moduleA |vpiActual: @@ -174,6 +176,8 @@ design: (work@top) |vpiConstType:9 |vpiRefModule: \_ref_module: work@moduleA (instanceD), line:10:13, endln:10:22 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ModPortHighConn/dut.sv, line:5:1, endln:11:10 |vpiName:instanceD |vpiDefName:work@moduleA |vpiActual: diff --git a/tests/ModPortParam/ModPortParam.log b/tests/ModPortParam/ModPortParam.log index 3d430946a2..33de4d8c1a 100644 --- a/tests/ModPortParam/ModPortParam.log +++ b/tests/ModPortParam/ModPortParam.log @@ -191,12 +191,16 @@ design: (work@Core) |vpiDefName:work@Core |vpiRefModule: \_ref_module: work@PerformanceCounterIF (perfCounterIF), line:14:23, endln:14:36 + |vpiParent: + \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiName:perfCounterIF |vpiDefName:work@PerformanceCounterIF |vpiActual: \_interface_inst: work@PerformanceCounterIF (work@PerformanceCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:1:1, endln:6:13 |vpiRefModule: \_ref_module: work@CSR_Unit (csrUnit), line:16:11, endln:16:18 + |vpiParent: + \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiName:csrUnit |vpiDefName:work@CSR_Unit |vpiActual: diff --git a/tests/MultiConcatValueSize/MultiConcatValueSize.log b/tests/MultiConcatValueSize/MultiConcatValueSize.log index 7056033a8c..fd183e6885 100644 --- a/tests/MultiConcatValueSize/MultiConcatValueSize.log +++ b/tests/MultiConcatValueSize/MultiConcatValueSize.log @@ -2198,6 +2198,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@sub_top (u_sub), line:59:6, endln:59:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:52:1, endln:60:10 |vpiName:u_sub |vpiDefName:work@sub_top |vpiActual: diff --git a/tests/NoParamSubs/NoParamSubs.log b/tests/NoParamSubs/NoParamSubs.log index 1d69df2024..cfa7884fce 100644 --- a/tests/NoParamSubs/NoParamSubs.log +++ b/tests/NoParamSubs/NoParamSubs.log @@ -432,6 +432,8 @@ design: (work@top) |vpiConstType:9 |vpiRefModule: \_ref_module: work@dut (u_dut), line:10:6, endln:10:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/NoParamSubs/dut.sv, line:6:1, endln:13:10 |vpiName:u_dut |vpiDefName:work@dut |vpiActual: diff --git a/tests/OldLibrary/OldLibrary.log b/tests/OldLibrary/OldLibrary.log index af58a26fae..3892e5d00d 100644 --- a/tests/OldLibrary/OldLibrary.log +++ b/tests/OldLibrary/OldLibrary.log @@ -2,28 +2,28 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/top.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". - [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/top.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/top.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v". -[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/top.v:1:1: No timescale set for "top". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v". -[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3". +[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/top.v:1:1: No timescale set for "top". [WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2". [WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: No timescale set for "CELL1". +[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3". + [INF:CP0300] Compilation... [INF:CP0303] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: Compile module "work@CELL1". diff --git a/tests/OneNetInterf/OneNetInterf.log b/tests/OneNetInterf/OneNetInterf.log index 01257aaa67..de6259f4c6 100644 --- a/tests/OneNetInterf/OneNetInterf.log +++ b/tests/OneNetInterf/OneNetInterf.log @@ -519,6 +519,8 @@ design: (work@dut) \_logic_typespec: , line:2:34, endln:2:37 |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:3:13, endln:3:19 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: @@ -541,6 +543,8 @@ design: (work@dut) \_logic_net: (work@dut.o), line:2:38, endln:2:39 |vpiRefModule: \_ref_module: work@middle (middle1), line:4:10, endln:4:17 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:middle1 |vpiDefName:work@middle |vpiActual: @@ -579,6 +583,8 @@ design: (work@dut) |vpiName:ConnectTB |vpiRefModule: \_ref_module: work@SUB (sub1), line:11:7, endln:11:11 + |vpiParent: + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 |vpiName:sub1 |vpiDefName:work@SUB |vpiActual: @@ -633,6 +639,8 @@ design: (work@dut) |vpiNetType:1 |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:16:13, endln:16:19 + |vpiParent: + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: @@ -655,6 +663,8 @@ design: (work@dut) \_logic_net: (work@tb.o), line:15:10, endln:15:11 |vpiRefModule: \_ref_module: work@middle (dut1), line:17:10, endln:17:14 + |vpiParent: + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:dut1 |vpiDefName:work@middle |vpiActual: @@ -668,6 +678,8 @@ design: (work@dut) \_logic_net: (conntb) |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15 + |vpiParent: + \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiName:tb |vpiDefName:work@TESTBENCH |vpiActual: diff --git a/tests/OneNetModPort/OneNetModPort.log b/tests/OneNetModPort/OneNetModPort.log index 6465c06d9f..21ca16fc77 100644 --- a/tests/OneNetModPort/OneNetModPort.log +++ b/tests/OneNetModPort/OneNetModPort.log @@ -500,12 +500,16 @@ design: (work@TOP) |vpiDefName:work@TOP |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:16:13, endln:16:19 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:tb |vpiDefName:work@TESTBENCH |vpiActual: @@ -613,12 +617,16 @@ design: (work@TOP) \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:5:13, endln:5:19 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:9:1, endln:20:13 |vpiRefModule: \_ref_module: work@middle (middle1), line:6:10, endln:6:17 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiName:middle1 |vpiDefName:work@middle |vpiActual: @@ -660,6 +668,8 @@ design: (work@TOP) |vpiIsModPort:1 |vpiRefModule: \_ref_module: work@SUB (sub1), line:23:7, endln:23:11 + |vpiParent: + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 |vpiName:sub1 |vpiDefName:work@SUB |vpiActual: diff --git a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log index 8c20d365be..a43c27fc2c 100644 --- a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log +++ b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log @@ -566,12 +566,16 @@ design: (work@TOP) |vpiDefName:work@TOP |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:16:13, endln:16:19 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiRefModule: \_ref_module: work@dut (dut1), line:17:7, endln:17:11 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:dut1 |vpiDefName:work@dut |vpiActual: @@ -606,6 +610,8 @@ design: (work@TOP) |vpiName:observe |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:tb |vpiDefName:work@TESTBENCH |vpiActual: @@ -626,6 +632,8 @@ design: (work@TOP) |vpiName:tb |vpiRefModule: \_ref_module: work@OBSERVER (obs), line:19:12, endln:19:15 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:obs |vpiDefName:work@OBSERVER |vpiActual: @@ -734,12 +742,16 @@ design: (work@TOP) \_logic_net: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:5:13, endln:5:19 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: \_interface_inst: work@ConnectTB (work@ConnectTB), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:9:1, endln:20:13 |vpiRefModule: \_ref_module: work@middle (middle1), line:6:10, endln:6:17 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiName:middle1 |vpiDefName:work@middle |vpiActual: @@ -785,6 +797,8 @@ design: (work@TOP) |vpiName:intf |vpiRefModule: \_ref_module: work@SUB (sub1), line:23:7, endln:23:11 + |vpiParent: + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 |vpiName:sub1 |vpiDefName:work@SUB |vpiActual: diff --git a/tests/OneNetRange/OneNetRange.log b/tests/OneNetRange/OneNetRange.log index 220781e7c5..dd4039cddb 100644 --- a/tests/OneNetRange/OneNetRange.log +++ b/tests/OneNetRange/OneNetRange.log @@ -643,6 +643,8 @@ design: (work@TOP) |vpiNetType:1 |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:20:22, endln:20:28 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: @@ -665,6 +667,8 @@ design: (work@TOP) \_logic_net: (work@TOP.o), line:19:20, endln:19:21 |vpiRefModule: \_ref_module: work@dut (dut1), line:21:16, endln:21:20 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:dut1 |vpiDefName:work@dut |vpiActual: @@ -699,6 +703,8 @@ design: (work@TOP) |vpiName:con_o |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:22:22, endln:22:24 + |vpiParent: + \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:tb |vpiDefName:work@TESTBENCH |vpiActual: @@ -856,6 +862,8 @@ design: (work@TOP) |vpiConstType:9 |vpiRefModule: \_ref_module: work@ConnectTB (conntb), line:3:30, endln:3:36 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiName:conntb |vpiDefName:work@ConnectTB |vpiActual: @@ -878,6 +886,8 @@ design: (work@TOP) \_logic_net: (work@TOP.dut1.o), line:2:85, endln:2:86 |vpiRefModule: \_ref_module: work@middle (middle1), line:4:27, endln:4:34 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiName:middle1 |vpiDefName:work@middle |vpiActual: @@ -939,6 +949,8 @@ design: (work@TOP) |vpiName:ConnectTB |vpiRefModule: \_ref_module: work@SUB (sub1), line:12:24, endln:12:28 + |vpiParent: + \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |vpiName:sub1 |vpiDefName:work@SUB |vpiActual: diff --git a/tests/PAssignType/PAssignType.log b/tests/PAssignType/PAssignType.log index 650cb166dc..30b6e1b9f3 100644 --- a/tests/PAssignType/PAssignType.log +++ b/tests/PAssignType/PAssignType.log @@ -580,6 +580,8 @@ design: (work@aes_core) |vpiFullName:work@aes_core.ctrl_q |vpiRefModule: \_ref_module: work@shadow (shadow_reg), line:25:33, endln:25:43 + |vpiParent: + \_module_inst: work@aes_core (work@aes_core), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:22:1, endln:26:10 |vpiName:shadow_reg |vpiDefName:work@shadow |vpiActual: @@ -635,6 +637,8 @@ design: (work@aes_core) |vpiDefName:work@shadow |vpiRefModule: \_ref_module: work@subreg (commit_reg), line:19:29, endln:19:39 + |vpiParent: + \_module_inst: work@shadow (work@shadow), file:${SURELOG_DIR}/tests/PAssignType/dut.sv, line:16:1, endln:20:10 |vpiName:commit_reg |vpiDefName:work@subreg |vpiActual: diff --git a/tests/PackedEnumPort/PackedEnumPort.log b/tests/PackedEnumPort/PackedEnumPort.log index c171773d64..10a56a65c2 100644 --- a/tests/PackedEnumPort/PackedEnumPort.log +++ b/tests/PackedEnumPort/PackedEnumPort.log @@ -417,6 +417,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@lc_ctrl_fsm (u_lc_ctrl_fsm), line:34:16, endln:34:29 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PackedEnumPort/dut.sv, line:24:1, endln:37:16 |vpiName:u_lc_ctrl_fsm |vpiDefName:work@lc_ctrl_fsm |vpiActual: diff --git a/tests/ParamArray/ParamArray.log b/tests/ParamArray/ParamArray.log index dce1544edb..8a1a926632 100644 --- a/tests/ParamArray/ParamArray.log +++ b/tests/ParamArray/ParamArray.log @@ -2132,6 +2132,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@otp_ctrl_lci (u_otp_ctrl_lci), line:48:5, endln:48:19 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArray/dut.sv, line:43:1, endln:50:10 |vpiName:u_otp_ctrl_lci |vpiDefName:work@otp_ctrl_lci |vpiActual: diff --git a/tests/ParamArraySelect/ParamArraySelect.log b/tests/ParamArraySelect/ParamArraySelect.log index bf5e5d7d7a..d5728d08a2 100644 --- a/tests/ParamArraySelect/ParamArraySelect.log +++ b/tests/ParamArraySelect/ParamArraySelect.log @@ -2660,6 +2660,8 @@ design: (work@top) |vpiNetType:36 |vpiRefModule: \_ref_module: work@otp_ctrl_lci (u_otp_ctrl_lci), line:56:5, endln:56:19 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiName:u_otp_ctrl_lci |vpiDefName:work@otp_ctrl_lci |vpiActual: diff --git a/tests/ParamByValue/ParamByValue.log b/tests/ParamByValue/ParamByValue.log index 549da54775..06385476f9 100644 --- a/tests/ParamByValue/ParamByValue.log +++ b/tests/ParamByValue/ParamByValue.log @@ -668,6 +668,8 @@ design: (work@top) |vpiDefName:work@prim_flop |vpiRefModule: \_ref_module: work@generic_flop (impl_generic), line:16:7, endln:16:19 + |vpiParent: + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:12:1, endln:18:10 |vpiName:impl_generic |vpiDefName:work@generic_flop |vpiActual: @@ -896,6 +898,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_flop (state_regs), line:25:5, endln:25:15 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamByValue/dut.sv, line:20:1, endln:27:10 |vpiName:state_regs |vpiDefName:work@prim_flop |vpiActual: diff --git a/tests/ParamComplex/ParamComplex.log b/tests/ParamComplex/ParamComplex.log index 0eb4fbd1e0..6ad1f4000d 100644 --- a/tests/ParamComplex/ParamComplex.log +++ b/tests/ParamComplex/ParamComplex.log @@ -1291,6 +1291,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (asgn0), line:14:8, endln:14:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplex/dut.sv, line:9:1, endln:15:10 |vpiName:asgn0 |vpiDefName:work@dut |vpiActual: diff --git a/tests/ParamComplexVerilator/ParamComplexVerilator.log b/tests/ParamComplexVerilator/ParamComplexVerilator.log index 9dca2eb754..29546e9160 100644 --- a/tests/ParamComplexVerilator/ParamComplexVerilator.log +++ b/tests/ParamComplexVerilator/ParamComplexVerilator.log @@ -1291,6 +1291,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (asgn0), line:14:8, endln:14:13 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamComplexVerilator/dut.sv, line:9:1, endln:15:10 |vpiName:asgn0 |vpiDefName:work@dut |vpiActual: diff --git a/tests/ParamConcat/ParamConcat.log b/tests/ParamConcat/ParamConcat.log index 84270e4f54..7952d8b8dd 100644 --- a/tests/ParamConcat/ParamConcat.log +++ b/tests/ParamConcat/ParamConcat.log @@ -1099,6 +1099,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@ibex_csr (u_mstatus_csr), line:18:5, endln:18:18 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConcat/dut.sv, line:6:1, endln:19:10 |vpiName:u_mstatus_csr |vpiDefName:work@ibex_csr |vpiActual: diff --git a/tests/ParamConst/ParamConst.log b/tests/ParamConst/ParamConst.log index 2a66f81f8b..498346225a 100644 --- a/tests/ParamConst/ParamConst.log +++ b/tests/ParamConst/ParamConst.log @@ -1423,6 +1423,8 @@ design: (work@top) |vpiDefName:work@prim_flop |vpiRefModule: \_ref_module: work@generic_flop (impl_generic), line:15:7, endln:15:19 + |vpiParent: + \_module_inst: work@prim_flop (work@prim_flop), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:12:1, endln:16:10 |vpiName:impl_generic |vpiDefName:work@generic_flop |vpiActual: @@ -1651,6 +1653,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_flop (state_regs), line:23:5, endln:23:15 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamConst/dut.sv, line:18:1, endln:25:10 |vpiName:state_regs |vpiDefName:work@prim_flop |vpiActual: diff --git a/tests/ParamElab/ParamElab.log b/tests/ParamElab/ParamElab.log index 43a28581cb..3286adcbd7 100644 --- a/tests/ParamElab/ParamElab.log +++ b/tests/ParamElab/ParamElab.log @@ -997,6 +997,8 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@test (t), line:5:11, endln:5:12 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamElab/dut.sv, line:1:1, endln:6:10 |vpiName:t |vpiDefName:work@test |vpiActual: diff --git a/tests/ParamElabMulti/ParamElabMulti.log b/tests/ParamElabMulti/ParamElabMulti.log index 2b8aab34fe..e3b5ef6883 100644 --- a/tests/ParamElabMulti/ParamElabMulti.log +++ b/tests/ParamElabMulti/ParamElabMulti.log @@ -1327,6 +1327,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@sub_top (u_sub), line:59:6, endln:59:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:52:1, endln:61:10 |vpiName:u_sub |vpiDefName:work@sub_top |vpiActual: diff --git a/tests/ParamFile/ParamFile.log b/tests/ParamFile/ParamFile.log index c34b41532e..26d5455f16 100644 --- a/tests/ParamFile/ParamFile.log +++ b/tests/ParamFile/ParamFile.log @@ -311,6 +311,8 @@ design: (work@dut) \_logic_typespec: , line:3:20, endln:3:25 |vpiRefModule: \_ref_module: work@ram_1p (u_ram), line:7:6, endln:7:11 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:u_ram |vpiDefName:work@ram_1p |vpiActual: diff --git a/tests/ParamFile/ParamFileNoTop.log b/tests/ParamFile/ParamFileNoTop.log index 68d45cd0b6..c80e05b6c7 100644 --- a/tests/ParamFile/ParamFileNoTop.log +++ b/tests/ParamFile/ParamFileNoTop.log @@ -315,6 +315,8 @@ design: (unnamed) \_logic_typespec: , line:3:20, endln:3:25 |vpiRefModule: \_ref_module: work@ram_1p (u_ram), line:7:6, endln:7:11 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:u_ram |vpiDefName:work@ram_1p |vpiActual: diff --git a/tests/ParamFile/ParamFileOverr.log b/tests/ParamFile/ParamFileOverr.log index c30d71667f..cd6c7cc9e5 100644 --- a/tests/ParamFile/ParamFileOverr.log +++ b/tests/ParamFile/ParamFileOverr.log @@ -309,6 +309,8 @@ design: (work@dut) \_logic_typespec: , line:3:20, endln:3:25 |vpiRefModule: \_ref_module: work@ram_1p (u_ram), line:7:6, endln:7:11 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamFile/dut.sv, line:3:1, endln:10:10 |vpiName:u_ram |vpiDefName:work@ram_1p |vpiActual: diff --git a/tests/ParamFromPackage/ParamFromPackage.log b/tests/ParamFromPackage/ParamFromPackage.log index e7b78de41a..55a6d37f7d 100644 --- a/tests/ParamFromPackage/ParamFromPackage.log +++ b/tests/ParamFromPackage/ParamFromPackage.log @@ -606,6 +606,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@aes_cipher_core (u_aes_cipher_core), line:13:29, endln:13:46 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamFromPackage/dut.sv, line:12:1, endln:14:10 |vpiName:u_aes_cipher_core |vpiDefName:work@aes_cipher_core |vpiActual: diff --git a/tests/ParamIndex/ParamIndex.log b/tests/ParamIndex/ParamIndex.log index 07db025984..ae1771b147 100644 --- a/tests/ParamIndex/ParamIndex.log +++ b/tests/ParamIndex/ParamIndex.log @@ -486,24 +486,32 @@ design: (work@top) |vpiFullName:work@mid.DATA0 |vpiRefModule: \_ref_module: work@bottom (u1), line:13:22, endln:13:24 + |vpiParent: + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiName:u1 |vpiDefName:work@bottom |vpiActual: \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiRefModule: \_ref_module: work@bottom (u2), line:14:33, endln:14:35 + |vpiParent: + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiName:u2 |vpiDefName:work@bottom |vpiActual: \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiRefModule: \_ref_module: work@bottom (u3), line:15:33, endln:15:35 + |vpiParent: + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiName:u3 |vpiDefName:work@bottom |vpiActual: \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:19:1, endln:23:10 |vpiRefModule: \_ref_module: work@bottom (u4), line:16:34, endln:16:36 + |vpiParent: + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:11:1, endln:17:10 |vpiName:u4 |vpiDefName:work@bottom |vpiActual: @@ -533,6 +541,8 @@ design: (work@top) |vpiFullName:work@top.DATATOP |vpiRefModule: \_ref_module: work@mid (u0), line:7:22, endln:7:24 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamIndex/dut.sv, line:2:1, endln:9:10 |vpiName:u0 |vpiDefName:work@mid |vpiActual: diff --git a/tests/ParamMultiConcat/ParamMultiConcat.log b/tests/ParamMultiConcat/ParamMultiConcat.log index 926ba856e4..f816440627 100644 --- a/tests/ParamMultiConcat/ParamMultiConcat.log +++ b/tests/ParamMultiConcat/ParamMultiConcat.log @@ -413,6 +413,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (u_dut), line:15:6, endln:15:11 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamMultiConcat/dut.sv, line:9:1, endln:18:10 |vpiName:u_dut |vpiDefName:work@dut |vpiActual: diff --git a/tests/ParamNoDefault/ParamNoDefault.log b/tests/ParamNoDefault/ParamNoDefault.log index eb1b89d8cf..629438a59e 100644 --- a/tests/ParamNoDefault/ParamNoDefault.log +++ b/tests/ParamNoDefault/ParamNoDefault.log @@ -328,6 +328,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (u_dut), line:17:17, endln:17:22 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamNoDefault/dut.sv, line:6:1, endln:18:10 |vpiName:u_dut |vpiDefName:work@dut |vpiActual: diff --git a/tests/ParamNoImport/ParamNoImport.log b/tests/ParamNoImport/ParamNoImport.log index 1e431cdde3..be75095aed 100644 --- a/tests/ParamNoImport/ParamNoImport.log +++ b/tests/ParamNoImport/ParamNoImport.log @@ -360,6 +360,8 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@test (t), line:16:48, endln:16:49 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamNoImport/dut.sv, line:14:1, endln:18:10 |vpiName:t |vpiDefName:work@test |vpiActual: diff --git a/tests/ParamNoSubst/ParamNoSubst.log b/tests/ParamNoSubst/ParamNoSubst.log index 24715231af..c5af627619 100644 --- a/tests/ParamNoSubst/ParamNoSubst.log +++ b/tests/ParamNoSubst/ParamNoSubst.log @@ -582,6 +582,8 @@ design: (work@aes_core), id:150 |vpiFullName:work@aes_core.ctrl_q |vpiRefModule: \_ref_module: work@prim_subreg_shadow (ctrl_shadowed_reg), id:81, line:25:45, endln:25:62 + |vpiParent: + \_module_inst: work@aes_core (work@aes_core), id:152, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:22:1, endln:26:10 |vpiName:ctrl_shadowed_reg |vpiDefName:work@prim_subreg_shadow |vpiActual: @@ -686,6 +688,8 @@ design: (work@aes_core), id:150 |vpiDefName:work@prim_subreg_shadow |vpiRefModule: \_ref_module: work@prim_subreg (committed_reg), id:98, line:19:34, endln:19:47 + |vpiParent: + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), id:155, file:${SURELOG_DIR}/tests/ParamNoSubst/dut.sv, line:16:1, endln:20:10 |vpiName:committed_reg |vpiDefName:work@prim_subreg |vpiActual: diff --git a/tests/ParamOverload1/ParamOverload1.log b/tests/ParamOverload1/ParamOverload1.log index 8828376e76..ac1b5b82f8 100644 --- a/tests/ParamOverload1/ParamOverload1.log +++ b/tests/ParamOverload1/ParamOverload1.log @@ -419,6 +419,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@dut (u_dut1), line:7:29, endln:7:35 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:u_dut1 |vpiDefName:work@dut |vpiActual: @@ -433,6 +435,8 @@ design: (work@top) \_int_var: (work@top.o), line:6:23, endln:6:24 |vpiRefModule: \_ref_module: work@dut (u_dut2), line:8:8, endln:8:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:u_dut2 |vpiDefName:work@dut |vpiActual: @@ -447,6 +451,8 @@ design: (work@top) \_int_var: (work@top.o), line:6:23, endln:6:24 |vpiRefModule: \_ref_module: work@dut (u_dut3), line:9:20, endln:9:26 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload1/dut.sv, line:6:1, endln:10:10 |vpiName:u_dut3 |vpiDefName:work@dut |vpiActual: diff --git a/tests/ParamOverload2/ParamOverload2.log b/tests/ParamOverload2/ParamOverload2.log index 2d7e7eeefb..3fad4627de 100644 --- a/tests/ParamOverload2/ParamOverload2.log +++ b/tests/ParamOverload2/ParamOverload2.log @@ -762,6 +762,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@keymgr (u_keymgr), line:17:6, endln:17:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload2/dut.sv, line:14:1, endln:18:10 |vpiName:u_keymgr |vpiDefName:work@keymgr |vpiActual: diff --git a/tests/ParamOverloadProp/ParamOverloadProp.log b/tests/ParamOverloadProp/ParamOverloadProp.log index 7f288c1bda..db87e619aa 100644 --- a/tests/ParamOverloadProp/ParamOverloadProp.log +++ b/tests/ParamOverloadProp/ParamOverloadProp.log @@ -245,6 +245,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_flop (u_prim_flop), line:4:6, endln:4:17 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloadProp/dut.sv, line:1:1, endln:5:10 |vpiName:u_prim_flop |vpiDefName:work@prim_flop |vpiActual: diff --git a/tests/ParamOverloading/ParamOverloading.log b/tests/ParamOverloading/ParamOverloading.log index 9cb053c3bf..9661cb0d55 100644 --- a/tests/ParamOverloading/ParamOverloading.log +++ b/tests/ParamOverloading/ParamOverloading.log @@ -555,6 +555,8 @@ design: (work@top) |vpiDefName:work@prim_subreg_shadow |vpiRefModule: \_ref_module: work@prim_subreg (staged_reg), line:20:6, endln:20:16 + |vpiParent: + \_module_inst: work@prim_subreg_shadow (work@prim_subreg_shadow), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:7:1, endln:22:10 |vpiName:staged_reg |vpiDefName:work@prim_subreg |vpiActual: @@ -716,6 +718,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@prim_subreg_shadow (u_ctrl_reg_shadowed), line:40:6, endln:40:25 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverloading/dut.sv, line:24:1, endln:41:10 |vpiName:u_ctrl_reg_shadowed |vpiDefName:work@prim_subreg_shadow |vpiActual: diff --git a/tests/ParamRef/ParamRef.log b/tests/ParamRef/ParamRef.log index b786ba17ed..34a82adbdc 100644 --- a/tests/ParamRef/ParamRef.log +++ b/tests/ParamRef/ParamRef.log @@ -589,6 +589,8 @@ design: (work@top_earlgrey) |vpiDefName:work@rv_core_ibex |vpiRefModule: \_ref_module: work@ibex_core (u_core), line:22:5, endln:22:11 + |vpiParent: + \_module_inst: work@rv_core_ibex (work@rv_core_ibex), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:18:1, endln:23:10 |vpiName:u_core |vpiDefName:work@ibex_core |vpiActual: @@ -656,6 +658,8 @@ design: (work@top_earlgrey) |vpiDefName:work@top_earlgrey |vpiRefModule: \_ref_module: work@rv_core_ibex (u_rv_core_ibex), line:15:5, endln:15:19 + |vpiParent: + \_module_inst: work@top_earlgrey (work@top_earlgrey), file:${SURELOG_DIR}/tests/ParamRef/dut.sv, line:10:1, endln:16:10 |vpiName:u_rv_core_ibex |vpiDefName:work@rv_core_ibex |vpiActual: diff --git a/tests/ParamScope/ParamScope.log b/tests/ParamScope/ParamScope.log index 1276c58fb5..d109ca5b36 100644 --- a/tests/ParamScope/ParamScope.log +++ b/tests/ParamScope/ParamScope.log @@ -495,6 +495,8 @@ design: (work@top) |vpiDefName:work@lower |vpiRefModule: \_ref_module: work@bottom (bottom_u), line:14:5, endln:14:13 + |vpiParent: + \_module_inst: work@lower (work@lower), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:9:1, endln:15:10 |vpiName:bottom_u |vpiDefName:work@bottom |vpiActual: @@ -534,6 +536,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@upper (upper_u), line:24:9, endln:24:16 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:22:1, endln:25:10 |vpiName:upper_u |vpiDefName:work@upper |vpiActual: @@ -573,6 +577,8 @@ design: (work@top) |vpiDefName:work@upper |vpiRefModule: \_ref_module: work@lower (lower_u), line:19:9, endln:19:16 + |vpiParent: + \_module_inst: work@upper (work@upper), file:${SURELOG_DIR}/tests/ParamScope/dut.sv, line:17:1, endln:20:10 |vpiName:lower_u |vpiDefName:work@lower |vpiActual: diff --git a/tests/ParamTypespec2/ParamTypespec2.log b/tests/ParamTypespec2/ParamTypespec2.log index b6c913f874..d36ffe9240 100644 --- a/tests/ParamTypespec2/ParamTypespec2.log +++ b/tests/ParamTypespec2/ParamTypespec2.log @@ -701,6 +701,8 @@ design: (work@top) |vpiSigned:1 |vpiRefModule: \_ref_module: work@nmi_gen (u_nmi_gen), line:22:12, endln:22:21 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamTypespec2/dut.sv, line:21:1, endln:26:10 |vpiName:u_nmi_gen |vpiDefName:work@nmi_gen |vpiActual: diff --git a/tests/PartSelect4/PartSelect4.log b/tests/PartSelect4/PartSelect4.log index 054d1195d0..ddd72dcc6b 100644 --- a/tests/PartSelect4/PartSelect4.log +++ b/tests/PartSelect4/PartSelect4.log @@ -527,6 +527,8 @@ design: (work@xbar_main) |vpiDefName:work@xbar_main |vpiRefModule: \_ref_module: work@tlul_socket_1n (u_s1n_25), line:12:61, endln:12:69 + |vpiParent: + \_module_inst: work@xbar_main (work@xbar_main), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:11:1, endln:13:10 |vpiName:u_s1n_25 |vpiDefName:work@tlul_socket_1n |vpiActual: diff --git a/tests/PortByName/PortByName.log b/tests/PortByName/PortByName.log index 716dc8edb0..b2b1be76ad 100644 --- a/tests/PortByName/PortByName.log +++ b/tests/PortByName/PortByName.log @@ -309,6 +309,8 @@ design: (work@top) |vpiNetType:36 |vpiRefModule: \_ref_module: work@ibex_id_stage (id_stage_i), line:5:17, endln:5:27 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortByName/dut.sv, line:1:1, endln:11:10 |vpiName:id_stage_i |vpiDefName:work@ibex_id_stage |vpiActual: diff --git a/tests/PortDefaultValue/PortDefaultValue.log b/tests/PortDefaultValue/PortDefaultValue.log index f12385b50a..eb4e0f98cb 100644 --- a/tests/PortDefaultValue/PortDefaultValue.log +++ b/tests/PortDefaultValue/PortDefaultValue.log @@ -169,6 +169,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@bus_conn (u1), line:3:10, endln:3:12 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortDefaultValue/dut.sv, line:2:1, endln:4:10 |vpiName:u1 |vpiDefName:work@bus_conn |vpiActual: diff --git a/tests/PortWildcard/PortWildcard.log b/tests/PortWildcard/PortWildcard.log index efd3176fe4..63f6d8232b 100644 --- a/tests/PortWildcard/PortWildcard.log +++ b/tests/PortWildcard/PortWildcard.log @@ -1021,6 +1021,8 @@ design: (work@dut) \_logic_typespec: , line:16:7, endln:16:12 |vpiRefModule: \_ref_module: work@rvdff (freezerfpc_ff), line:17:15, endln:17:28 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/PortWildcard/dut.sv, line:15:1, endln:21:10 |vpiName:freezerfpc_ff |vpiDefName:work@rvdff |vpiActual: diff --git a/tests/PoundParam/PoundParam.log b/tests/PoundParam/PoundParam.log index 6c6d9e9ea7..2c8ebeaa37 100644 --- a/tests/PoundParam/PoundParam.log +++ b/tests/PoundParam/PoundParam.log @@ -1384,6 +1384,8 @@ design: (work@test) \_logic_typespec: , line:37:7, endln:37:7 |vpiRefModule: \_ref_module: work@dffr (park_reg), line:39:11, endln:39:19 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PoundParam/dut.v, line:35:1, endln:51:10 |vpiName:park_reg |vpiDefName:work@dffr |vpiActual: @@ -1462,6 +1464,8 @@ design: (work@test) \_port: , line:43:40, endln:43:45 |vpiRefModule: \_ref_module: work@dffr (logic), line:45:10, endln:45:15 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PoundParam/dut.v, line:35:1, endln:51:10 |vpiName:logic |vpiDefName:work@dffr |vpiActual: diff --git a/tests/PreprocLine/PreprocLine.log b/tests/PreprocLine/PreprocLine.log index 406a71a05f..372563fdd9 100644 --- a/tests/PreprocLine/PreprocLine.log +++ b/tests/PreprocLine/PreprocLine.log @@ -16,38 +16,38 @@ n u<3> t p<4> l<1:8> el<1:11> n<> u<4> t p<66> c<2> s<64> l<1:1> el<1:12> n<> u<5> t p<17> s<6> l<3:9> el<3:10> n u<6> t p<17> s<16> l<3:10> el<3:17> -n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t p<8> l<3:18> el<3:98> -n<> u<8> t p<9> c<7> l<3:18> el<3:98> -n<> u<9> t p<10> c<8> l<3:18> el<3:98> -n<> u<10> t p<16> c<9> s<15> l<3:18> el<3:98> -n<3> u<11> t p<12> l<3:100> el<3:101> -n<> u<12> t p<13> c<11> l<3:100> el<3:101> -n<> u<13> t p<14> c<12> l<3:100> el<3:101> -n<> u<14> t p<15> c<13> l<3:100> el<3:101> -n<> u<15> t p<16> c<14> l<3:100> el<3:101> -n<> u<16> t p<17> c<10> l<3:18> el<3:101> -n<> u<17> t p<18> c<5> l<3:9> el<3:102> -n<> u<18> t p<19> c<17> l<3:9> el<3:103> -n<> u<19> t p<20> c<18> l<3:9> el<3:103> -n<> u<20> t p<21> c<19> l<3:9> el<3:103> -n<> u<21> t p<57> c<20> s<38> l<3:9> el<3:103> +n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t p<8> l<3:18> el<3:64> +n<> u<8> t p<9> c<7> l<3:18> el<3:64> +n<> u<9> t p<10> c<8> l<3:18> el<3:64> +n<> u<10> t p<16> c<9> s<15> l<3:18> el<3:64> +n<3> u<11> t p<12> l<3:66> el<3:67> +n<> u<12> t p<13> c<11> l<3:66> el<3:67> +n<> u<13> t p<14> c<12> l<3:66> el<3:67> +n<> u<14> t p<15> c<13> l<3:66> el<3:67> +n<> u<15> t p<16> c<14> l<3:66> el<3:67> +n<> u<16> t p<17> c<10> l<3:18> el<3:67> +n<> u<17> t p<18> c<5> l<3:9> el<3:68> +n<> u<18> t p<19> c<17> l<3:9> el<3:69> +n<> u<19> t p<20> c<18> l<3:9> el<3:69> +n<> u<20> t p<21> c<19> l<3:9> el<3:69> +n<> u<21> t p<57> c<20> s<38> l<3:9> el<3:69> n<> u<22> t p<34> s<23> l<5:9> el<5:10> n u<23> t p<34> s<33> l<5:10> el<5:17> -n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t p<25> l<5:18> el<5:98> -n<> u<25> t p<26> c<24> l<5:18> el<5:98> -n<> u<26> t p<27> c<25> l<5:18> el<5:98> -n<> u<27> t p<33> c<26> s<32> l<5:18> el<5:98> -n<102> u<28> t p<29> l<5:100> el<5:103> -n<> u<29> t p<30> c<28> l<5:100> el<5:103> -n<> u<30> t p<31> c<29> l<5:100> el<5:103> -n<> u<31> t p<32> c<30> l<5:100> el<5:103> -n<> u<32> t p<33> c<31> l<5:100> el<5:103> -n<> u<33> t p<34> c<27> l<5:18> el<5:103> -n<> u<34> t p<35> c<22> l<5:9> el<5:104> -n<> u<35> t p<36> c<34> l<5:9> el<5:105> -n<> u<36> t p<37> c<35> l<5:9> el<5:105> -n<> u<37> t p<38> c<36> l<5:9> el<5:105> -n<> u<38> t p<57> c<37> s<55> l<5:9> el<5:105> +n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t p<25> l<5:18> el<5:64> +n<> u<25> t p<26> c<24> l<5:18> el<5:64> +n<> u<26> t p<27> c<25> l<5:18> el<5:64> +n<> u<27> t p<33> c<26> s<32> l<5:18> el<5:64> +n<102> u<28> t p<29> l<5:66> el<5:69> +n<> u<29> t p<30> c<28> l<5:66> el<5:69> +n<> u<30> t p<31> c<29> l<5:66> el<5:69> +n<> u<31> t p<32> c<30> l<5:66> el<5:69> +n<> u<32> t p<33> c<31> l<5:66> el<5:69> +n<> u<33> t p<34> c<27> l<5:18> el<5:69> +n<> u<34> t p<35> c<22> l<5:9> el<5:70> +n<> u<35> t p<36> c<34> l<5:9> el<5:71> +n<> u<36> t p<37> c<35> l<5:9> el<5:71> +n<> u<37> t p<38> c<36> l<5:9> el<5:71> +n<> u<38> t p<57> c<37> s<55> l<5:9> el<5:71> n<> u<39> t p<51> s<40> f<0> l<10:9> el<10:10> n u<40> t p<51> s<50> f<0> l<10:10> el<10:17> n<""> u<41> t p<42> f<0> l<10:18> el<10:20> diff --git a/tests/PrimTermExpr/PrimTermExpr.log b/tests/PrimTermExpr/PrimTermExpr.log index eb594258ea..05e21c0037 100644 --- a/tests/PrimTermExpr/PrimTermExpr.log +++ b/tests/PrimTermExpr/PrimTermExpr.log @@ -148,7 +148,7 @@ AST_DEBUG_END bit_select 2 constant 10 design 1 -gate 2 +gate 4 logic_net 10 logic_typespec 9 module_inst 5 @@ -160,17 +160,17 @@ ref_obj 16 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -bit_select 2 +bit_select 4 constant 10 design 1 -gate 2 +gate 6 logic_net 10 logic_typespec 9 module_inst 5 port 21 -prim_term 6 +prim_term 12 range 4 -ref_obj 21 +ref_obj 27 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PrimTermExpr/slpp_all/surelog.uhdm ... @@ -298,6 +298,20 @@ design: (work@encoder_4to2_gates) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiPrimitive: + \_gate: (work@encoder_4to2_gates.o1), line:5:4, endln:5:19 + |vpiParent: + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + |vpiName:o1 + |vpiFullName:work@encoder_4to2_gates.o1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@encoder_4to2_gates.o2), line:6:4, endln:6:19 + |vpiParent: + \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 + |vpiName:o2 + |vpiFullName:work@encoder_4to2_gates.o2 + |vpiPrimType:4 |uhdmtopModules: \_module_inst: work@encoder_4to2_gates (work@encoder_4to2_gates), file:${SURELOG_DIR}/tests/PrimTermExpr/dut.sv, line:1:1, endln:8:10 |vpiName:work@encoder_4to2_gates @@ -486,11 +500,15 @@ design: (work@encoder_4to2_gates) \_gate: work@or (work@encoder_4to2_gates.o1), line:5:4, endln:5:19 |vpiDirection:2 |vpiExpr: - \_bit_select: (work@encoder_4to2_gates.o1.y), line:5:8, endln:5:12 + \_bit_select: (work@encoder_4to2_gates.y), line:5:8, endln:5:12 |vpiParent: - \_gate: work@or (work@encoder_4to2_gates.o1), line:5:4, endln:5:19 + \_ref_obj: (work@encoder_4to2_gates.o1.o1) + |vpiParent: + \_prim_term: , line:5:8, endln:5:12 + |vpiName:o1 + |vpiFullName:work@encoder_4to2_gates.o1.o1 |vpiName:y - |vpiFullName:work@encoder_4to2_gates.o1.y + |vpiFullName:work@encoder_4to2_gates.y |vpiIndex: \_constant: , line:5:10, endln:5:11 |vpiParent: @@ -499,6 +517,8 @@ design: (work@encoder_4to2_gates) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiActual: + \_logic_net: (work@encoder_4to2_gates.y), line:1:40, endln:1:41 |vpiPrimTerm: \_prim_term: , line:5:13, endln:5:15 |vpiParent: @@ -508,7 +528,7 @@ design: (work@encoder_4to2_gates) |vpiExpr: \_ref_obj: (work@encoder_4to2_gates.i1), line:5:13, endln:5:15 |vpiParent: - \_gate: work@or (work@encoder_4to2_gates.o1), line:5:4, endln:5:19 + \_prim_term: , line:5:13, endln:5:15 |vpiName:i1 |vpiFullName:work@encoder_4to2_gates.i1 |vpiActual: @@ -522,7 +542,7 @@ design: (work@encoder_4to2_gates) |vpiExpr: \_ref_obj: (work@encoder_4to2_gates.i3), line:5:16, endln:5:18 |vpiParent: - \_gate: work@or (work@encoder_4to2_gates.o1), line:5:4, endln:5:19 + \_prim_term: , line:5:16, endln:5:18 |vpiName:i3 |vpiFullName:work@encoder_4to2_gates.i3 |vpiActual: @@ -541,11 +561,15 @@ design: (work@encoder_4to2_gates) \_gate: work@or (work@encoder_4to2_gates.o2), line:6:4, endln:6:19 |vpiDirection:2 |vpiExpr: - \_bit_select: (work@encoder_4to2_gates.o2.y), line:6:8, endln:6:12 + \_bit_select: (work@encoder_4to2_gates.y), line:6:8, endln:6:12 |vpiParent: - \_gate: work@or (work@encoder_4to2_gates.o2), line:6:4, endln:6:19 + \_ref_obj: (work@encoder_4to2_gates.o2.o2) + |vpiParent: + \_prim_term: , line:6:8, endln:6:12 + |vpiName:o2 + |vpiFullName:work@encoder_4to2_gates.o2.o2 |vpiName:y - |vpiFullName:work@encoder_4to2_gates.o2.y + |vpiFullName:work@encoder_4to2_gates.y |vpiIndex: \_constant: , line:6:10, endln:6:11 |vpiParent: @@ -554,6 +578,8 @@ design: (work@encoder_4to2_gates) |vpiSize:64 |UINT:1 |vpiConstType:9 + |vpiActual: + \_logic_net: (work@encoder_4to2_gates.y), line:1:40, endln:1:41 |vpiPrimTerm: \_prim_term: , line:6:13, endln:6:15 |vpiParent: @@ -563,7 +589,7 @@ design: (work@encoder_4to2_gates) |vpiExpr: \_ref_obj: (work@encoder_4to2_gates.i2), line:6:13, endln:6:15 |vpiParent: - \_gate: work@or (work@encoder_4to2_gates.o2), line:6:4, endln:6:19 + \_prim_term: , line:6:13, endln:6:15 |vpiName:i2 |vpiFullName:work@encoder_4to2_gates.i2 |vpiActual: @@ -577,7 +603,7 @@ design: (work@encoder_4to2_gates) |vpiExpr: \_ref_obj: (work@encoder_4to2_gates.i3), line:6:16, endln:6:18 |vpiParent: - \_gate: work@or (work@encoder_4to2_gates.o2), line:6:4, endln:6:19 + \_prim_term: , line:6:16, endln:6:18 |vpiName:i3 |vpiFullName:work@encoder_4to2_gates.i3 |vpiActual: diff --git a/tests/ScalarParam/ScalarParam.log b/tests/ScalarParam/ScalarParam.log index 9dd61477af..6d44217107 100644 --- a/tests/ScalarParam/ScalarParam.log +++ b/tests/ScalarParam/ScalarParam.log @@ -193,6 +193,8 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@param_test (t1), line:16:5, endln:16:7 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ScalarParam/dut.sv, line:12:1, endln:18:10 |vpiName:t1 |vpiDefName:work@param_test |vpiActual: diff --git a/tests/SignedBin/SignedBin.log b/tests/SignedBin/SignedBin.log index 2111ad5062..dca5c1c8e3 100644 --- a/tests/SignedBin/SignedBin.log +++ b/tests/SignedBin/SignedBin.log @@ -126,6 +126,8 @@ design: (work@dut) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@prim_subreg (s), line:9:13, endln:9:14 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/SignedBin/dut.sv, line:7:1, endln:10:10 |vpiName:s |vpiDefName:work@prim_subreg |vpiActual: diff --git a/tests/SplitFile/SplitFile.log b/tests/SplitFile/SplitFile.log index bd21e16229..5e3820c8bd 100644 --- a/tests/SplitFile/SplitFile.log +++ b/tests/SplitFile/SplitFile.log @@ -225,7 +225,7 @@ enum_typespec 1 enum_var 1 event_control 1 function 9 -gate 1 +gate 2 int_typespec 9 int_var 4 interface_inst 3 diff --git a/tests/StringParameter/StringParameter.log b/tests/StringParameter/StringParameter.log index 87a19c62e2..1ca741eb53 100644 --- a/tests/StringParameter/StringParameter.log +++ b/tests/StringParameter/StringParameter.log @@ -118,6 +118,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@parameter_module (test_module), line:5:11, endln:5:22 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StringParameter/dut.sv, line:1:1, endln:6:10 |vpiName:test_module |vpiDefName:work@parameter_module |vpiActual: diff --git a/tests/StructArrayNet/StructArrayNet.log b/tests/StructArrayNet/StructArrayNet.log index 28a25e2cc2..26ecf9460c 100644 --- a/tests/StructArrayNet/StructArrayNet.log +++ b/tests/StructArrayNet/StructArrayNet.log @@ -377,6 +377,8 @@ design: (work@dut) |vpiSigned:1 |vpiRefModule: \_ref_module: work@mod (m), line:12:8, endln:12:9 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructArrayNet/dut.sv, line:9:1, endln:13:10 |vpiName:m |vpiDefName:work@mod |vpiActual: diff --git a/tests/StructUnsizedVal/StructUnsizedVal.log b/tests/StructUnsizedVal/StructUnsizedVal.log index c463337d2a..846bd25c89 100644 --- a/tests/StructUnsizedVal/StructUnsizedVal.log +++ b/tests/StructUnsizedVal/StructUnsizedVal.log @@ -947,6 +947,8 @@ design: (work@top) |vpiDefName:work@dut |vpiRefModule: \_ref_module: work@foo (f), line:18:32, endln:18:33 + |vpiParent: + \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/StructUnsizedVal/dut.sv, line:17:1, endln:19:10 |vpiName:f |vpiDefName:work@foo |vpiActual: @@ -1002,6 +1004,8 @@ design: (work@top) |vpiDefName:work@foo |vpiRefModule: \_ref_module: work@foo2 (f), line:14:35, endln:14:36 + |vpiParent: + \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/StructUnsizedVal/dut.sv, line:13:1, endln:15:10 |vpiName:f |vpiDefName:work@foo2 |vpiActual: @@ -1063,6 +1067,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@dut (d), line:22:7, endln:22:8 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructUnsizedVal/dut.sv, line:21:1, endln:23:10 |vpiName:d |vpiDefName:work@dut |vpiActual: diff --git a/tests/StructVar/StructVar.log b/tests/StructVar/StructVar.log index 18a4f2a717..91d32e2915 100644 --- a/tests/StructVar/StructVar.log +++ b/tests/StructVar/StructVar.log @@ -562,18 +562,24 @@ design: (work@test) |vpiName:$vpi_decompiler |vpiRefModule: \_ref_module: work@dut1 (u1), line:70:8, endln:70:10 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:u1 |vpiDefName:work@dut1 |vpiActual: \_module_inst: work@dut1 (work@dut1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:1:1, endln:31:10 |vpiRefModule: \_ref_module: work@dut2 (u2), line:71:8, endln:71:10 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:u2 |vpiDefName:work@dut2 |vpiActual: \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:34:1, endln:44:10 |vpiRefModule: \_ref_module: work@prim_generic_ram_1 (u3), line:72:22, endln:72:24 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:69:1, endln:76:10 |vpiName:u3 |vpiDefName:work@prim_generic_ram_1 |vpiActual: diff --git a/tests/TaggedParam/TaggedParam.log b/tests/TaggedParam/TaggedParam.log index 28034d49b6..646054b4d6 100644 --- a/tests/TaggedParam/TaggedParam.log +++ b/tests/TaggedParam/TaggedParam.log @@ -371,6 +371,8 @@ design: (work@fpu_wrap) |vpiDefName:work@fpu_wrap |vpiRefModule: \_ref_module: work@fpnew_top (i_fpnew_bulk), line:25:8, endln:25:20 + |vpiParent: + \_module_inst: work@fpu_wrap (work@fpu_wrap), file:${SURELOG_DIR}/tests/TaggedParam/dut.sv, line:16:1, endln:27:10 |vpiName:i_fpnew_bulk |vpiDefName:work@fpnew_top |vpiActual: diff --git a/tests/TestSepCompNoHash/TestSepCompNoHash.log b/tests/TestSepCompNoHash/TestSepCompNoHash.log index 2c3f8d74a7..a5790f032e 100644 --- a/tests/TestSepCompNoHash/TestSepCompNoHash.log +++ b/tests/TestSepCompNoHash/TestSepCompNoHash.log @@ -27,18 +27,18 @@ [ NOTE] : 0 [INF:CM0023] Creating log file ${SURELOG_DIR}/tests/TestSepCompNoHash/slpp_all/surelog.log. -PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv -PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv +PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv -[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv:1:1: No timescale set for "top". - +PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv [WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv:1:1: No timescale set for "pkg1". [WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv:1:1: No timescale set for "pkg2". +[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv:1:1: No timescale set for "top". + [INF:CP0300] Compilation... [INF:CP0301] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv:1:1: Compile package "pkg1". diff --git a/tests/TimeUnit/TimeUnit.log b/tests/TimeUnit/TimeUnit.log index f99c99c684..c2603ae409 100644 --- a/tests/TimeUnit/TimeUnit.log +++ b/tests/TimeUnit/TimeUnit.log @@ -112,7 +112,7 @@ enum_typespec 1 enum_var 1 event_control 1 function 9 -gate 1 +gate 2 int_typespec 9 int_var 4 interface_inst 3 diff --git a/tests/TypeParam/TypeParam.log b/tests/TypeParam/TypeParam.log index 273ccc5a0e..733e370d7d 100644 --- a/tests/TypeParam/TypeParam.log +++ b/tests/TypeParam/TypeParam.log @@ -169,12 +169,16 @@ design: (work@top) |vpiFullName:work@mid.DATA0 |vpiRefModule: \_ref_module: work@bottom (u1), line:12:22, endln:12:24 + |vpiParent: + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 |vpiName:u1 |vpiDefName:work@bottom |vpiActual: \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:17:1, endln:21:10 |vpiRefModule: \_ref_module: work@bottom (u2), line:13:33, endln:13:35 + |vpiParent: + \_module_inst: work@mid (work@mid), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:10:1, endln:15:10 |vpiName:u2 |vpiDefName:work@bottom |vpiActual: @@ -204,6 +208,8 @@ design: (work@top) |vpiFullName:work@top.DATATOP |vpiRefModule: \_ref_module: work@mid (u0), line:6:22, endln:6:24 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam/dut.sv, line:1:1, endln:8:10 |vpiName:u0 |vpiDefName:work@mid |vpiActual: diff --git a/tests/TypeParam2/TypeParam2.log b/tests/TypeParam2/TypeParam2.log index de9ecef8e1..ec5ac2ac58 100644 --- a/tests/TypeParam2/TypeParam2.log +++ b/tests/TypeParam2/TypeParam2.log @@ -197,6 +197,8 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@rr_arb_tree (i_arbiter), line:17:5, endln:17:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TypeParam2/dut.sv, line:8:1, endln:20:10 |vpiName:i_arbiter |vpiDefName:work@rr_arb_tree |vpiActual: diff --git a/tests/TypeParamElab/TypeParamElab.log b/tests/TypeParamElab/TypeParamElab.log index c848f50574..e38011720f 100644 --- a/tests/TypeParamElab/TypeParamElab.log +++ b/tests/TypeParamElab/TypeParamElab.log @@ -551,6 +551,8 @@ design: (work@axi_node_arbiter) |vpiDefName:work@axi_node_arbiter |vpiRefModule: \_ref_module: work@stream_arbiter (i_arb_inp), line:35:5, endln:35:14 + |vpiParent: + \_module_inst: work@axi_node_arbiter (work@axi_node_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:22:1, endln:37:10 |vpiName:i_arb_inp |vpiDefName:work@stream_arbiter |vpiActual: @@ -623,6 +625,8 @@ design: (work@axi_node_arbiter) |vpiDefName:work@stream_arbiter |vpiRefModule: \_ref_module: work@stream_arbiter_flushable (i_arb), line:18:5, endln:18:10 + |vpiParent: + \_module_inst: work@stream_arbiter (work@stream_arbiter), file:${SURELOG_DIR}/tests/TypeParamElab/dut.sv, line:9:1, endln:20:10 |vpiName:i_arb |vpiDefName:work@stream_arbiter_flushable |vpiActual: diff --git a/tests/TypeParamOverride/TypeParamOverride.log b/tests/TypeParamOverride/TypeParamOverride.log index c52e716516..3b52843971 100644 --- a/tests/TypeParamOverride/TypeParamOverride.log +++ b/tests/TypeParamOverride/TypeParamOverride.log @@ -302,6 +302,8 @@ design: (work@ariane_testharness) |vpiDefName:work@ariane_testharness |vpiRefModule: \_ref_module: work@axi_err_slv (i_gpio_err_slv), line:27:3, endln:27:17 + |vpiParent: + \_module_inst: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 |vpiName:i_gpio_err_slv |vpiDefName:work@axi_err_slv |vpiActual: diff --git a/tests/TypespecExpr/TypespecExpr.log b/tests/TypespecExpr/TypespecExpr.log index bc46f512f4..0981131184 100644 --- a/tests/TypespecExpr/TypespecExpr.log +++ b/tests/TypespecExpr/TypespecExpr.log @@ -448,6 +448,8 @@ design: (work@Mod2) |vpiNetType:36 |vpiRefModule: \_ref_module: work@Mod1 (mod1), line:9:27, endln:9:31 + |vpiParent: + \_module_inst: work@Mod2 (work@Mod2), file:${SURELOG_DIR}/tests/TypespecExpr/dut.sv, line:5:1, endln:10:10 |vpiName:mod1 |vpiDefName:work@Mod1 |vpiActual: diff --git a/tests/Udp/Udp.log b/tests/Udp/Udp.log index 8cceddeeec..2a609fb267 100644 --- a/tests/Udp/Udp.log +++ b/tests/Udp/Udp.log @@ -1012,7 +1012,7 @@ ref_obj 27 sys_func_call 4 table_entry 18 task 18 -udp 1 +udp 2 udp_defn 4 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/Udp/slpp_all/surelog.uhdm ... diff --git a/tests/UhdmCoverage/UhdmCoverage.log b/tests/UhdmCoverage/UhdmCoverage.log index d3154374a7..f4e903660f 100644 --- a/tests/UhdmCoverage/UhdmCoverage.log +++ b/tests/UhdmCoverage/UhdmCoverage.log @@ -1576,6 +1576,8 @@ design: (work@divSqrtRecFNToRaw_small) \_logic_net: (lce_resp_link_cast_o) |vpiRefModule: \_ref_module: work@MOD (u1), line:110:5, endln:110:7 + |vpiParent: + \_module_inst: work@e (work@e), file:${SURELOG_DIR}/tests/UhdmCoverage/dut.sv, line:99:1, endln:115:10 |vpiName:u1 |vpiDefName:work@MOD |vpiActual: diff --git a/tests/UnitDefParam/UnitDefParam.log b/tests/UnitDefParam/UnitDefParam.log index 0e1291d41e..1b02b23fa9 100644 --- a/tests/UnitDefParam/UnitDefParam.log +++ b/tests/UnitDefParam/UnitDefParam.log @@ -1694,24 +1694,32 @@ design: (work@top_def) |vpiDefName:work@defparam_example |vpiRefModule: \_ref_module: work@secret_number (U0), line:19:17, endln:19:19 + |vpiParent: + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U0 |vpiDefName:work@secret_number |vpiActual: \_module_inst: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 |vpiRefModule: \_ref_module: work@secret_number (U1), line:20:17, endln:20:19 + |vpiParent: + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U1 |vpiDefName:work@secret_number |vpiActual: \_module_inst: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 |vpiRefModule: \_ref_module: work@secret_number (U2), line:21:17, endln:21:19 + |vpiParent: + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U2 |vpiDefName:work@secret_number |vpiActual: \_module_inst: work@secret_number (work@secret_number), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:2:1, endln:12:10 |vpiRefModule: \_ref_module: work@secret_number (U3), line:22:17, endln:22:19 + |vpiParent: + \_module_inst: work@defparam_example (work@defparam_example), file:${SURELOG_DIR}/tests/UnitDefParam/small.v, line:14:1, endln:27:10 |vpiName:U3 |vpiDefName:work@secret_number |vpiActual: @@ -1857,6 +1865,8 @@ design: (work@top_def) |vpiDefName:work@small_top |vpiRefModule: \_ref_module: work@small_test (u1), line:8:24, endln:8:26 + |vpiParent: + \_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:7:1, endln:9:10 |vpiName:u1 |vpiDefName:work@small_test |vpiActual: @@ -1869,6 +1879,8 @@ design: (work@top_def) |vpiDefName:work@top_def |vpiRefModule: \_ref_module: work@def (u1), line:3:14, endln:3:16 + |vpiParent: + \_module_inst: work@top_def (work@top_def), file:${SURELOG_DIR}/tests/UnitDefParam/top.v, line:1:1, endln:5:10 |vpiName:u1 |vpiDefName:work@def |vpiActual: diff --git a/tests/UnitElab/UnitElab.log b/tests/UnitElab/UnitElab.log index 9dbfab6118..c4b020f741 100644 --- a/tests/UnitElab/UnitElab.log +++ b/tests/UnitElab/UnitElab.log @@ -13591,7 +13591,7 @@ enum_const 5 enum_typespec 1 enum_var 1 function 9 -gate 5 +gate 10 gen_scope 2426 gen_scope_array 2426 int_typespec 1219 @@ -14408,6 +14408,8 @@ design: (work@bottom1) |vpiDefName:work@small_top |vpiRefModule: \_ref_module: work@small_test (u1), line:2:24, endln:2:26 + |vpiParent: + \_module_inst: work@small_top (work@small_top), file:${SURELOG_DIR}/tests/UnitElab/small.v, line:1:1, endln:3:10 |vpiName:u1 |vpiDefName:work@small_test |vpiActual: @@ -14496,6 +14498,20 @@ design: (work@bottom1) \_ref_obj: |vpiActual: \_logic_net: (work@test.b), line:35:16, endln:35:17 + |vpiPrimitive: + \_gate: (work@test.u0), line:39:7, endln:39:14 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + |vpiName:u0 + |vpiFullName:work@test.u0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@test.u4), line:58:6, endln:58:13 + |vpiParent: + \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:35:1, endln:76:10 + |vpiName:u4 + |vpiFullName:work@test.u4 + |vpiPrimType:1 |uhdmallModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnitElab/top.v, line:26:1, endln:31:10 |vpiParent: diff --git a/tests/UnitElabExternNested/UnitElabExternNested.log b/tests/UnitElabExternNested/UnitElabExternNested.log index e227044549..3911b53baa 100644 --- a/tests/UnitElabExternNested/UnitElabExternNested.log +++ b/tests/UnitElabExternNested/UnitElabExternNested.log @@ -80,7 +80,7 @@ enum_const 5 enum_typespec 1 enum_var 1 function 9 -gate 6 +gate 12 int_typespec 11 int_var 4 io_decl 11 diff --git a/tests/UnitLibrary/UnitLibrary.log b/tests/UnitLibrary/UnitLibrary.log index 0785de92d4..35e397c2dc 100644 --- a/tests/UnitLibrary/UnitLibrary.log +++ b/tests/UnitLibrary/UnitLibrary.log @@ -29,8 +29,8 @@ LIB: lib1 ${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv LIB: lib2 - ${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv ${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v + ${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv LIB: lib3 ${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v @@ -66,10 +66,10 @@ LIB: libw [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv". - [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv". + [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw1/wsub.v". @@ -90,10 +90,10 @@ LIB: libw [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv". - [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv". + [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw1/wsub.v". diff --git a/tests/UnsizedConstInst/UnsizedConstInst.log b/tests/UnsizedConstInst/UnsizedConstInst.log index 6d72593a24..ba0c918568 100644 --- a/tests/UnsizedConstInst/UnsizedConstInst.log +++ b/tests/UnsizedConstInst/UnsizedConstInst.log @@ -303,12 +303,16 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@bottom (u1), line:10:19, endln:10:21 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiName:u1 |vpiDefName:work@bottom |vpiActual: \_module_inst: work@bottom (work@bottom), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:1:1, endln:7:10 |vpiRefModule: \_ref_module: work@bottom (u2), line:11:19, endln:11:21 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedConstInst/dut.sv, line:9:1, endln:12:10 |vpiName:u2 |vpiDefName:work@bottom |vpiActual: diff --git a/tests/UnsizedParam/UnsizedParam.log b/tests/UnsizedParam/UnsizedParam.log index 135fb4eb07..f8b8d51fa4 100644 --- a/tests/UnsizedParam/UnsizedParam.log +++ b/tests/UnsizedParam/UnsizedParam.log @@ -377,12 +377,16 @@ design: (work@top) |vpiDefName:work@top |vpiRefModule: \_ref_module: work@submodule (u_sub_default), line:9:14, endln:9:27 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiName:u_sub_default |vpiDefName:work@submodule |vpiActual: \_module_inst: work@submodule (work@submodule), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:1:1, endln:6:10 |vpiRefModule: \_ref_module: work@submodule (u_sub_5), line:10:23, endln:10:30 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/UnsizedParam/dut.sv, line:8:1, endln:11:10 |vpiName:u_sub_5 |vpiDefName:work@submodule |vpiActual: diff --git a/tests/WildConn/WildConn.log b/tests/WildConn/WildConn.log index 2f1fc0be70..ccb761d710 100644 --- a/tests/WildConn/WildConn.log +++ b/tests/WildConn/WildConn.log @@ -967,6 +967,8 @@ design: (work@top) \_logic_typespec: , line:7:18, endln:7:23 |vpiRefModule: \_ref_module: work@MOD (u1), line:12:7, endln:12:9 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/WildConn/dut.sv, line:7:1, endln:17:10 |vpiName:u1 |vpiDefName:work@MOD |vpiActual: diff --git a/third_party/UHDM b/third_party/UHDM index 24ac1c3504..a017e19c0e 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 24ac1c3504b5923dd2846480097baf82823d623a +Subproject commit a017e19c0eeaa8dbdc064c204214ded130a65a66 diff --git a/third_party/antlr4 b/third_party/antlr4 index 6e89287582..3aff09a030 160000 --- a/third_party/antlr4 +++ b/third_party/antlr4 @@ -1 +1 @@ -Subproject commit 6e89287582c0c86407688aabbffda9f63bc7dc41 +Subproject commit 3aff09a030f63d23adaaf4bfeb2b01f1cc369c0f diff --git a/third_party/googletest b/third_party/googletest index 12a5852e45..d25e625364 160000 --- a/third_party/googletest +++ b/third_party/googletest @@ -1 +1 @@ -Subproject commit 12a5852e451baabc79c63a86c634912c563d57bc +Subproject commit d25e625364a2078c940da2cb1fcf098aa184fd9f diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 9ecca37345..92e7b12d5a 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -2,20 +2,12 @@ [WRN:CM0010] Command line argument "-Wno-UNOPTFLAT" ignored. -Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 12 --- Configuring done --- Generating done +Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 16 +-- Configuring done (0.1s) +-- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser -make[1]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' -make[2]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' -make[3]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' -make[3]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' -make[3]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' -[100%] Generating preprocessing -make[3]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' +[100%] Generating preprocessing [100%] Built target Parse -make[2]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' -make[1]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser' Surelog preproc status: 0 [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv". @@ -122,31 +114,27 @@ PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv". -Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 12 --- Configuring done --- Generating done +Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16 +-- Configuring done (0.0s) +-- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -make[1]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' -make[2]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' -make[3]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' -make[3]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' -make[3]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' -[ 16%] Generating 11_axi4_to_ahb.sv -[ 16%] Generating 10_dec_tlu_ctl.sv -[ 25%] Generating 12_tb_top.sv -[ 33%] Generating 1_ifu_mem_ctl.sv -[ 41%] Generating 2_dec_decode_ctl.sv -[ 50%] Generating 3_mem_lib.sv -[ 66%] Generating 5_beh_lib.sv -[ 66%] Generating 4_lsu_bus_buffer.sv -[ 75%] Generating 6_dbg.sv -[ 83%] Generating 8_ahb_to_axi4.sv -[ 91%] Generating 7_lsu_bus_intf.sv -[100%] Generating 9_exu.sv -make[3]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' +[ 6%] Generating 10_lsu_bus_intf.sv +[ 12%] Generating 13_ifu_mem_ctl.sv +[ 18%] Generating 12_beh_lib.sv +[ 25%] Generating 11_ifu_bp_ctl.sv +[ 31%] Generating 14_mem_lib.sv +[ 37%] Generating 15_exu.sv +[ 43%] Generating 16_dec_decode_ctl.sv +[ 50%] Generating 1_lsu_stbuf.sv +[ 56%] Generating 2_ahb_to_axi4.sv +[ 62%] Generating 3_rvjtag_tap.sv +[ 68%] Generating 4_dec_tlu_ctl.sv +[ 75%] Generating 5_lsu_bus_buffer.sv +[ 81%] Generating 6_dbg.sv +[ 87%] Generating 7_axi4_to_ahb.sv +[ 93%] Generating 8_ifu_aln_ctl.sv +[100%] Generating 9_tb_top.sv [100%] Built target Parse -make[2]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' -make[1]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess' Surelog parsing status: 0 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv". diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index 53055ae88a..0c603500f7 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -22,125 +22,125 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_sdram.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv". @@ -159,125 +159,125 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/ [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_sdram.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". [INF:CM0029] Using global timescale: "10ps/10ps". @@ -536,142 +536,142 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/trace_logger.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv:22:1: previous definition. - -[ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv:22:1: previous definition. +[ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv:22:1: previous definition. + [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv:22:1: previous definition. [ERR:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines", - ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv:22:1: previous definition. + ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv:22:1: previous definition. [NTE:CP0309] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:37:29: Implicit port type (wire) for "read_data". diff --git a/third_party/tests/SimpleParserTest/SimpleParserTest.log b/third_party/tests/SimpleParserTest/SimpleParserTest.log index da575c40a3..df4c7be45a 100644 --- a/third_party/tests/SimpleParserTest/SimpleParserTest.log +++ b/third_party/tests/SimpleParserTest/SimpleParserTest.log @@ -129,7 +129,7 @@ event_control 32 for_stmt 11 func_call 2 function 9 -gate 5 +gate 10 if_else 16 if_stmt 21 include_file_info 1 @@ -7273,6 +7273,41 @@ design: (work@dff_async_reset) \_logic_net: (work@full_adder_gates.carry), line:7:35, endln:7:40 |vpiTypedef: \_logic_typespec: , line:9:8, endln:9:8 + |vpiPrimitive: + \_gate: (work@full_adder_gates.U_and1), line:12:5, endln:12:22 + |vpiParent: + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + |vpiName:U_and1 + |vpiFullName:work@full_adder_gates.U_and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@full_adder_gates.U_and2), line:13:5, endln:13:22 + |vpiParent: + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + |vpiName:U_and2 + |vpiFullName:work@full_adder_gates.U_and2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@full_adder_gates.U_and3), line:14:5, endln:14:22 + |vpiParent: + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + |vpiName:U_and3 + |vpiFullName:work@full_adder_gates.U_and3 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@full_adder_gates.U_or), line:15:5, endln:15:34 + |vpiParent: + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + |vpiName:U_or + |vpiFullName:work@full_adder_gates.U_or + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@full_adder_gates.U_sum), line:16:5, endln:16:22 + |vpiParent: + \_module_inst: work@full_adder_gates (work@full_adder_gates), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/full_adder.v, line:7:1, endln:18:10 + |vpiName:U_sum + |vpiFullName:work@full_adder_gates.U_sum + |vpiPrimType:5 |uhdmallModules: \_module_inst: work@mux21_switch (work@mux21_switch), file:${SURELOG_DIR}/third_party/tests/SimpleParserTest/mux21.v, line:7:1, endln:22:10 |vpiParent: diff --git a/third_party/tests/Sky130Cell/Sky130Cell.log b/third_party/tests/Sky130Cell/Sky130Cell.log index c111ec0c5b..852758f64f 100644 --- a/third_party/tests/Sky130Cell/Sky130Cell.log +++ b/third_party/tests/Sky130Cell/Sky130Cell.log @@ -3319,6 +3319,20 @@ design: (work@sky130_fd_sc_hd__dfrtp) \_logic_net: (work@sky130_fd_sc_hd__dfrtp.RESET_B), line:40:5, endln:40:12 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrtp.not0), line:54:45, endln:54:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfrtp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrtp.buf0), line:56:45, endln:56:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfrtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfrtp (work@sky130_fd_sc_hd__dfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtp.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__dfrtp @@ -3838,6 +3852,20 @@ design: (work@sky130_fd_sc_hd__sdfxbp) \_logic_net: (work@sky130_fd_sc_hd__sdfxbp.SCE), line:43:5, endln:43:8 |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfxbp.buf0), line:61:47, endln:61:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfxbp.not0), line:62:47, endln:62:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfxbp.not0 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfxbp (work@sky130_fd_sc_hd__sdfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxbp.functional.v, line:37:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__sdfxbp @@ -4242,6 +4270,27 @@ design: (work@sky130_fd_sc_hd__o41ai) \_logic_net: (work@sky130_fd_sc_hd__o41ai.B1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o41ai.or0), line:57:10, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o41ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o41ai.nand0), line:58:10, endln:58:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o41ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o41ai.buf0), line:59:10, endln:59:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o41ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o41ai (work@sky130_fd_sc_hd__o41ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o41ai @@ -4618,6 +4667,20 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s15) \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s15.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s15.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s15.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s15.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s15 (work@sky130_fd_sc_hd__clkdlybuf4s15), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s15.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s15 @@ -5082,6 +5145,13 @@ design: (work@sky130_fd_sc_hd__sedfxtp) \_logic_net: (work@sky130_fd_sc_hd__sedfxtp.SCE), line:44:5, endln:44:8 |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sedfxtp.buf0), line:64:47, endln:64:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sedfxtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sedfxtp (work@sky130_fd_sc_hd__sedfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxtp.functional.v, line:38:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__sedfxtp @@ -5386,6 +5456,20 @@ design: (work@sky130_fd_sc_hd__xor2) \_logic_net: (work@sky130_fd_sc_hd__xor2.B), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xor2.xor0), line:50:9, endln:50:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + |vpiName:xor0 + |vpiFullName:work@sky130_fd_sc_hd__xor2.xor0 + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xor2.buf0), line:51:9, endln:51:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__xor2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__xor2 (work@sky130_fd_sc_hd__xor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor2.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__xor2 @@ -5679,6 +5763,13 @@ design: (work@sky130_fd_sc_hd__macro_sparecell) \_logic_net: (work@sky130_fd_sc_hd__macro_sparecell.LO), line:42:5, endln:42:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__macro_sparecell.buf0), line:66:30, endln:66:81 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__macro_sparecell.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__macro_sparecell (work@sky130_fd_sc_hd__macro_sparecell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__macro_sparecell.functional.v, line:41:1, endln:68:10 |vpiName:work@sky130_fd_sc_hd__macro_sparecell @@ -6156,6 +6247,20 @@ design: (work@sky130_fd_sc_hd__inv) \_logic_net: (work@sky130_fd_sc_hd__inv.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__inv.not0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__inv.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__inv.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__inv.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__inv (work@sky130_fd_sc_hd__inv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__inv.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__inv @@ -6369,6 +6474,27 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrc) \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrc.A), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_isobufsrc.not0), line:51:9, endln:51:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_isobufsrc.and0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_isobufsrc.buf0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrc.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrc (work@sky130_fd_sc_hd__lpflow_isobufsrc), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrc.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__lpflow_isobufsrc @@ -6637,6 +6763,20 @@ design: (work@sky130_fd_sc_hd__clkinvlp) \_logic_net: (work@sky130_fd_sc_hd__clkinvlp.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkinvlp.not0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkinvlp.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkinvlp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkinvlp (work@sky130_fd_sc_hd__clkinvlp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinvlp.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__clkinvlp @@ -6825,6 +6965,20 @@ design: (work@sky130_fd_sc_hd__bufinv) \_logic_net: (work@sky130_fd_sc_hd__bufinv.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__bufinv.not0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__bufinv.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__bufinv.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__bufinv.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__bufinv (work@sky130_fd_sc_hd__bufinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufinv.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__bufinv @@ -7099,6 +7253,34 @@ design: (work@sky130_fd_sc_hd__a32o) \_logic_net: (work@sky130_fd_sc_hd__a32o.B2), line:42:5, endln:42:7 |vpiTypedef: \_logic_typespec: , line:51:12, endln:51:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32o.and0), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a32o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32o.and1), line:60:9, endln:60:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__a32o.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32o.or0), line:61:9, endln:61:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a32o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32o.buf0), line:62:9, endln:62:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a32o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a32o (work@sky130_fd_sc_hd__a32o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32o.functional.v, line:36:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__a32o @@ -7601,6 +7783,55 @@ design: (work@sky130_fd_sc_hd__fahcon) \_logic_net: (work@sky130_fd_sc_hd__fahcon.CI), line:38:5, endln:38:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.xor0), line:56:9, endln:56:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:xor0 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.xor0 + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.buf0), line:57:9, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.nor0), line:58:9, endln:58:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.nor1), line:59:9, endln:59:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:nor1 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.nor1 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.nor2), line:60:9, endln:60:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:nor2 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.nor2 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.or0), line:61:9, endln:61:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcon.buf1), line:62:9, endln:62:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__fahcon.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__fahcon (work@sky130_fd_sc_hd__fahcon), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcon.functional.v, line:33:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__fahcon @@ -8164,6 +8395,20 @@ design: (work@sky130_fd_sc_hd__dlymetal6s2s) \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s2s.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlymetal6s2s.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlymetal6s2s.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s2s.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlymetal6s2s (work@sky130_fd_sc_hd__dlymetal6s2s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s2s.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__dlymetal6s2s @@ -8438,6 +8683,34 @@ design: (work@sky130_fd_sc_hd__o32a) \_logic_net: (work@sky130_fd_sc_hd__o32a.B2), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32a.or0), line:58:9, endln:58:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o32a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32a.or1), line:59:9, endln:59:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + |vpiName:or1 + |vpiFullName:work@sky130_fd_sc_hd__o32a.or1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32a.and0), line:60:9, endln:60:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o32a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32a.buf0), line:61:9, endln:61:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o32a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o32a (work@sky130_fd_sc_hd__o32a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32a.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o32a @@ -9214,6 +9487,41 @@ design: (work@sky130_fd_sc_hd__sdfbbn) \_logic_net: (work@sky130_fd_sc_hd__sdfbbn.RESET_B), line:46:5, endln:46:12 |vpiTypedef: \_logic_typespec: , line:57:12, endln:57:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbn.not0), line:67:47, endln:67:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbn.not1), line:68:47, endln:68:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbn.not2), line:69:47, endln:69:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + |vpiName:not2 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not2 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbn.buf0), line:72:47, endln:72:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbn.not3), line:73:47, endln:73:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 + |vpiName:not3 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbn.not3 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfbbn (work@sky130_fd_sc_hd__sdfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbn.functional.v, line:38:1, endln:75:10 |vpiName:work@sky130_fd_sc_hd__sdfbbn @@ -9827,6 +10135,20 @@ design: (work@sky130_fd_sc_hd__dfxbp) \_logic_net: (work@sky130_fd_sc_hd__dfxbp.D), line:40:5, endln:40:6 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfxbp.buf0), line:54:44, endln:54:74 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfxbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfxbp.not0), line:55:44, endln:55:74 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfxbp.not0 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfxbp (work@sky130_fd_sc_hd__dfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxbp.functional.v, line:36:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__dfxbp @@ -10228,6 +10550,27 @@ design: (work@sky130_fd_sc_hd__dlrtn) \_logic_net: (work@sky130_fd_sc_hd__dlrtn.GATE_N), line:40:5, endln:40:11 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrtn.not0), line:55:48, endln:55:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlrtn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrtn.not1), line:56:48, endln:56:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dlrtn.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrtn.buf0), line:58:48, endln:58:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlrtn.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlrtn (work@sky130_fd_sc_hd__dlrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtn.functional.v, line:36:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__dlrtn @@ -10650,6 +10993,13 @@ design: (work@sky130_fd_sc_hd__mux2i) \_logic_net: (work@sky130_fd_sc_hd__mux2i.S), line:40:5, endln:40:6 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__mux2i.buf0), line:54:37, endln:54:87 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__mux2i.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__mux2i (work@sky130_fd_sc_hd__mux2i), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2i.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__mux2i @@ -10935,6 +11285,27 @@ design: (work@sky130_fd_sc_hd__o2111ai) \_logic_net: (work@sky130_fd_sc_hd__o2111ai.D1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2111ai.or0), line:57:10, endln:57:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o2111ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2111ai.nand0), line:58:10, endln:58:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o2111ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2111ai.buf0), line:59:10, endln:59:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o2111ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o2111ai (work@sky130_fd_sc_hd__o2111ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2111ai @@ -11422,6 +11793,41 @@ design: (work@sky130_fd_sc_hd__a222oi) \_logic_net: (work@sky130_fd_sc_hd__a222oi.C2), line:42:5, endln:42:7 |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a222oi.nand0), line:61:10, endln:61:61 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a222oi.nand1), line:62:10, endln:62:61 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + |vpiName:nand1 + |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a222oi.nand2), line:63:10, endln:63:61 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + |vpiName:nand2 + |vpiFullName:work@sky130_fd_sc_hd__a222oi.nand2 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a222oi.and0), line:64:10, endln:64:61 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a222oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a222oi.buf0), line:65:10, endln:65:61 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a222oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a222oi (work@sky130_fd_sc_hd__a222oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a222oi.functional.v, line:35:1, endln:67:10 |vpiName:work@sky130_fd_sc_hd__a222oi @@ -11922,6 +12328,20 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s25) \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s25.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s25.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s25.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s25.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s25 (work@sky130_fd_sc_hd__clkdlybuf4s25), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s25.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s25 @@ -12171,6 +12591,27 @@ design: (work@sky130_fd_sc_hd__or4bb) \_logic_net: (work@sky130_fd_sc_hd__or4bb.D_N), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4bb.nand0), line:53:10, endln:53:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__or4bb.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4bb.or0), line:54:10, endln:54:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or4bb.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4bb.buf0), line:55:10, endln:55:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or4bb.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or4bb (work@sky130_fd_sc_hd__or4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__or4bb @@ -12504,6 +12945,13 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap) \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.A), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:43:12, endln:43:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.buf0), line:46:9, endln:46:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v, line:36:1, endln:48:10 |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap @@ -12709,6 +13157,27 @@ design: (work@sky130_fd_sc_hd__nor4bb) \_logic_net: (work@sky130_fd_sc_hd__nor4bb.D_N), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4bb.nor0), line:53:9, endln:53:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__nor4bb.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4bb.and0), line:54:9, endln:54:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__nor4bb.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4bb.buf0), line:55:9, endln:55:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor4bb.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor4bb (work@sky130_fd_sc_hd__nor4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor4bb @@ -13085,6 +13554,20 @@ design: (work@sky130_fd_sc_hd__nand3) \_logic_net: (work@sky130_fd_sc_hd__nand3.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand3.nand0), line:50:10, endln:50:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__nand3.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand3.buf0), line:51:10, endln:51:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand3 (work@sky130_fd_sc_hd__nand3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__nand3 @@ -13566,6 +14049,41 @@ design: (work@sky130_fd_sc_hd__dfbbn) \_logic_net: (work@sky130_fd_sc_hd__dfbbn.RESET_B), line:43:5, endln:43:12 |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbn.not0), line:61:46, endln:61:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbn.not1), line:62:46, endln:62:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbn.not2), line:63:46, endln:63:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + |vpiName:not2 + |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not2 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbn.buf0), line:65:46, endln:65:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfbbn.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbn.not3), line:66:46, endln:66:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 + |vpiName:not3 + |vpiFullName:work@sky130_fd_sc_hd__dfbbn.not3 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfbbn (work@sky130_fd_sc_hd__dfbbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbn.functional.v, line:37:1, endln:68:10 |vpiName:work@sky130_fd_sc_hd__dfbbn @@ -14277,6 +14795,20 @@ design: (work@sky130_fd_sc_hd__sedfxbp) \_logic_net: (work@sky130_fd_sc_hd__sedfxbp.SCE), line:45:5, endln:45:8 |vpiTypedef: \_logic_typespec: , line:55:12, endln:55:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sedfxbp.buf0), line:66:47, endln:66:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sedfxbp.not0), line:67:47, endln:67:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sedfxbp.not0 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sedfxbp (work@sky130_fd_sc_hd__sedfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sedfxbp.functional.v, line:38:1, endln:69:10 |vpiName:work@sky130_fd_sc_hd__sedfxbp @@ -14933,6 +15465,13 @@ design: (work@sky130_fd_sc_hd__sdfxtp) \_logic_net: (work@sky130_fd_sc_hd__sdfxtp.SCE), line:42:5, endln:42:8 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfxtp.buf0), line:59:47, endln:59:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfxtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfxtp (work@sky130_fd_sc_hd__sdfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfxtp.functional.v, line:37:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__sdfxtp @@ -15179,6 +15718,20 @@ design: (work@sky130_fd_sc_hd__probec_p) \_logic_net: (work@sky130_fd_sc_hd__probec_p.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__probec_p.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__probec_p.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__probec_p.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__probec_p.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__probec_p (work@sky130_fd_sc_hd__probec_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probec_p.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__probec_p @@ -15428,6 +15981,27 @@ design: (work@sky130_fd_sc_hd__a211oi) \_logic_net: (work@sky130_fd_sc_hd__a211oi.C1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a211oi.and0), line:55:9, endln:55:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a211oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a211oi.nor0), line:56:9, endln:56:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a211oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a211oi.buf0), line:57:9, endln:57:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a211oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a211oi (work@sky130_fd_sc_hd__a211oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211oi.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a211oi @@ -15836,6 +16410,34 @@ design: (work@sky130_fd_sc_hd__o22a) \_logic_net: (work@sky130_fd_sc_hd__o22a.B2), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22a.or0), line:56:9, endln:56:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o22a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22a.or1), line:57:9, endln:57:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + |vpiName:or1 + |vpiFullName:work@sky130_fd_sc_hd__o22a.or1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22a.and0), line:58:9, endln:58:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o22a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22a.buf0), line:59:9, endln:59:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o22a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o22a (work@sky130_fd_sc_hd__o22a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o22a @@ -16336,6 +16938,13 @@ design: (work@sky130_fd_sc_hd__dfxtp) \_logic_net: (work@sky130_fd_sc_hd__dfxtp.D), line:39:5, endln:39:6 |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfxtp.buf0), line:52:44, endln:52:74 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfxtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfxtp (work@sky130_fd_sc_hd__dfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfxtp.functional.v, line:36:1, endln:54:10 |vpiName:work@sky130_fd_sc_hd__dfxtp @@ -16563,6 +17172,27 @@ design: (work@sky130_fd_sc_hd__a21oi) \_logic_net: (work@sky130_fd_sc_hd__a21oi.B1), line:39:5, endln:39:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21oi.and0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a21oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21oi.nor0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a21oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21oi.buf0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a21oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a21oi (work@sky130_fd_sc_hd__a21oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21oi.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__a21oi @@ -16935,6 +17565,34 @@ design: (work@sky130_fd_sc_hd__a22oi) \_logic_net: (work@sky130_fd_sc_hd__a22oi.B2), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22oi.nand0), line:56:10, endln:56:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__a22oi.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22oi.nand1), line:57:10, endln:57:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + |vpiName:nand1 + |vpiFullName:work@sky130_fd_sc_hd__a22oi.nand1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22oi.and0), line:58:10, endln:58:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a22oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22oi.buf0), line:59:10, endln:59:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a22oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a22oi (work@sky130_fd_sc_hd__a22oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a22oi @@ -17319,6 +17977,20 @@ design: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr) \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_clkinvkapwr.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_clkinvkapwr (work@sky130_fd_sc_hd__lpflow_clkinvkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkinvkapwr.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_clkinvkapwr @@ -17565,6 +18237,20 @@ design: (work@sky130_fd_sc_hd__and3) \_logic_net: (work@sky130_fd_sc_hd__and3.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and3.and0), line:50:9, endln:50:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and3.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and3.buf0), line:51:9, endln:51:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and3 (work@sky130_fd_sc_hd__and3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__and3 @@ -17886,6 +18572,27 @@ design: (work@sky130_fd_sc_hd__o211ai) \_logic_net: (work@sky130_fd_sc_hd__o211ai.C1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o211ai.or0), line:55:10, endln:55:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o211ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o211ai.nand0), line:56:10, endln:56:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o211ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o211ai.buf0), line:57:10, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o211ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o211ai (work@sky130_fd_sc_hd__o211ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211ai.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o211ai @@ -18226,6 +18933,20 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s18) \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s18.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s18.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s18.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s18.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s18 (work@sky130_fd_sc_hd__clkdlybuf4s18), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s18.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s18 @@ -18439,6 +19160,27 @@ design: (work@sky130_fd_sc_hd__or2b) \_logic_net: (work@sky130_fd_sc_hd__or2b.B_N), line:36:5, endln:36:8 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or2b.not0), line:49:9, endln:49:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__or2b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or2b.or0), line:50:9, endln:50:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or2b.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or2b.buf0), line:51:9, endln:51:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or2b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or2b (work@sky130_fd_sc_hd__or2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2b.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__or2b @@ -19025,6 +19767,27 @@ design: (work@sky130_fd_sc_hd__sdfrbp) \_logic_net: (work@sky130_fd_sc_hd__sdfrbp.RESET_B), line:45:5, endln:45:12 |vpiTypedef: \_logic_typespec: , line:55:12, endln:55:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrbp.not0), line:63:47, endln:63:87 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrbp.buf0), line:66:47, endln:66:87 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrbp.not1), line:67:47, endln:67:87 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__sdfrbp.not1 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfrbp (work@sky130_fd_sc_hd__sdfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrbp.functional.v, line:38:1, endln:69:10 |vpiName:work@sky130_fd_sc_hd__sdfrbp @@ -19493,6 +20256,20 @@ design: (work@sky130_fd_sc_hd__dlclkp) \_logic_net: (work@sky130_fd_sc_hd__dlclkp.CLK), line:39:5, endln:39:8 |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlclkp.not0), line:52:35, endln:52:68 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlclkp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlclkp.and0), line:54:35, endln:54:68 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__dlclkp.and0 + |vpiPrimType:1 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlclkp (work@sky130_fd_sc_hd__dlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlclkp.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__dlclkp @@ -19735,6 +20512,20 @@ design: (work@sky130_fd_sc_hd__clkinv) \_logic_net: (work@sky130_fd_sc_hd__clkinv.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkinv.not0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__clkinv.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkinv.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkinv.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkinv (work@sky130_fd_sc_hd__clkinv), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkinv.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__clkinv @@ -20213,6 +21004,13 @@ design: (work@sky130_fd_sc_hd__mux4) \_logic_net: (work@sky130_fd_sc_hd__mux4.S1), line:43:5, endln:43:7 |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__mux4.buf0), line:60:35, endln:60:86 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__mux4.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__mux4 (work@sky130_fd_sc_hd__mux4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux4.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__mux4 @@ -20528,6 +21326,27 @@ design: (work@sky130_fd_sc_hd__a21o) \_logic_net: (work@sky130_fd_sc_hd__a21o.B1), line:39:5, endln:39:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21o.and0), line:53:9, endln:53:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a21o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21o.or0), line:54:9, endln:54:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a21o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21o.buf0), line:55:9, endln:55:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a21o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a21o (work@sky130_fd_sc_hd__a21o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21o.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__a21o @@ -20886,6 +21705,20 @@ design: (work@sky130_fd_sc_hd__or4) \_logic_net: (work@sky130_fd_sc_hd__or4.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4.or0), line:52:9, endln:52:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or4.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4.buf0), line:53:9, endln:53:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or4.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or4 (work@sky130_fd_sc_hd__or4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__or4 @@ -21182,6 +22015,20 @@ design: (work@sky130_fd_sc_hd__dlygate4sd2) \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd2.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlygate4sd2.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlygate4sd2.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd2.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlygate4sd2 (work@sky130_fd_sc_hd__dlygate4sd2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd2.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__dlygate4sd2 @@ -21406,6 +22253,20 @@ design: (work@sky130_fd_sc_hd__or3) \_logic_net: (work@sky130_fd_sc_hd__or3.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or3.or0), line:50:9, endln:50:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or3.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or3.buf0), line:51:9, endln:51:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or3 (work@sky130_fd_sc_hd__or3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__or3 @@ -21666,6 +22527,20 @@ design: (work@sky130_fd_sc_hd__probe_p) \_logic_net: (work@sky130_fd_sc_hd__probe_p.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__probe_p.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__probe_p.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__probe_p.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__probe_p.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__probe_p (work@sky130_fd_sc_hd__probe_p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__probe_p.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__probe_p @@ -21943,6 +22818,62 @@ design: (work@sky130_fd_sc_hd__fahcin) \_logic_net: (work@sky130_fd_sc_hd__fahcin.CIN), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.not0), line:57:9, endln:57:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.xor0), line:58:9, endln:58:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:xor0 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.xor0 + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.buf0), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.and0), line:60:9, endln:60:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.and1), line:61:9, endln:61:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.and2), line:62:9, endln:62:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:and2 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.and2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.or0), line:63:9, endln:63:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fahcin.buf1), line:64:9, endln:64:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__fahcin.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__fahcin (work@sky130_fd_sc_hd__fahcin), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fahcin.functional.v, line:33:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__fahcin @@ -22629,6 +23560,27 @@ design: (work@sky130_fd_sc_hd__a2111oi) \_logic_net: (work@sky130_fd_sc_hd__a2111oi.D1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2111oi.and0), line:57:9, endln:57:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a2111oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2111oi.nor0), line:58:9, endln:58:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a2111oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2111oi.buf0), line:59:9, endln:59:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a2111oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a2111oi (work@sky130_fd_sc_hd__a2111oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a2111oi @@ -23048,6 +24000,27 @@ design: (work@sky130_fd_sc_hd__o21ba) \_logic_net: (work@sky130_fd_sc_hd__o21ba.B1_N), line:40:5, endln:40:9 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21ba.nor0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__o21ba.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21ba.nor1), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + |vpiName:nor1 + |vpiFullName:work@sky130_fd_sc_hd__o21ba.nor1 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21ba.buf0), line:56:9, endln:56:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o21ba.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o21ba (work@sky130_fd_sc_hd__o21ba), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ba.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__o21ba @@ -23395,6 +24368,27 @@ design: (work@sky130_fd_sc_hd__nand3b) \_logic_net: (work@sky130_fd_sc_hd__nand3b.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand3b.not0), line:51:10, endln:51:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__nand3b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand3b.nand0), line:52:10, endln:52:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__nand3b.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand3b.buf0), line:53:10, endln:53:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand3b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand3b (work@sky130_fd_sc_hd__nand3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand3b.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nand3b @@ -23699,6 +24693,20 @@ design: (work@sky130_fd_sc_hd__clkbuf) \_logic_net: (work@sky130_fd_sc_hd__clkbuf.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkbuf.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkbuf.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkbuf.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__clkbuf.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkbuf (work@sky130_fd_sc_hd__clkbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkbuf.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__clkbuf @@ -23973,6 +24981,34 @@ design: (work@sky130_fd_sc_hd__o221a) \_logic_net: (work@sky130_fd_sc_hd__o221a.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221a.or0), line:58:9, endln:58:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o221a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221a.or1), line:59:9, endln:59:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + |vpiName:or1 + |vpiFullName:work@sky130_fd_sc_hd__o221a.or1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221a.and0), line:60:9, endln:60:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o221a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221a.buf0), line:61:9, endln:61:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o221a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o221a (work@sky130_fd_sc_hd__o221a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221a.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o221a @@ -24479,6 +25515,34 @@ design: (work@sky130_fd_sc_hd__o32ai) \_logic_net: (work@sky130_fd_sc_hd__o32ai.B2), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32ai.nor0), line:58:9, endln:58:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__o32ai.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32ai.nor1), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + |vpiName:nor1 + |vpiFullName:work@sky130_fd_sc_hd__o32ai.nor1 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32ai.or0), line:60:9, endln:60:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o32ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o32ai.buf0), line:61:9, endln:61:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o32ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o32ai (work@sky130_fd_sc_hd__o32ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o32ai.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o32ai @@ -24917,6 +25981,20 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1n) \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1n.SLEEP_B), line:38:5, endln:38:12 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputiso1n.not0), line:50:9, endln:50:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputiso1n.or0), line:51:9, endln:51:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1n.or0 + |vpiPrimType:4 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1n (work@sky130_fd_sc_hd__lpflow_inputiso1n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1n.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso1n @@ -25448,6 +26526,27 @@ design: (work@sky130_fd_sc_hd__sdfrtn) \_logic_net: (work@sky130_fd_sc_hd__sdfrtn.RESET_B), line:44:5, endln:44:12 |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrtn.not0), line:62:47, endln:62:90 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrtn.not1), line:63:47, endln:63:90 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrtn.buf0), line:66:47, endln:66:90 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfrtn.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfrtn (work@sky130_fd_sc_hd__sdfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtn.functional.v, line:38:1, endln:68:10 |vpiName:work@sky130_fd_sc_hd__sdfrtn @@ -25865,6 +26964,27 @@ design: (work@sky130_fd_sc_hd__nor4b) \_logic_net: (work@sky130_fd_sc_hd__nor4b.D_N), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4b.not0), line:53:9, endln:53:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__nor4b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4b.nor0), line:54:9, endln:54:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__nor4b.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4b.buf0), line:55:9, endln:55:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor4b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor4b (work@sky130_fd_sc_hd__nor4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor4b @@ -26284,6 +27404,27 @@ design: (work@sky130_fd_sc_hd__a2111o) \_logic_net: (work@sky130_fd_sc_hd__a2111o.D1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2111o.and0), line:57:9, endln:57:47 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a2111o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2111o.or0), line:58:9, endln:58:47 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a2111o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2111o.buf0), line:59:9, endln:59:47 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a2111o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a2111o (work@sky130_fd_sc_hd__a2111o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2111o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a2111o @@ -26714,6 +27855,20 @@ design: (work@sky130_fd_sc_hd__nand4) \_logic_net: (work@sky130_fd_sc_hd__nand4.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4.nand0), line:52:10, endln:52:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__nand4.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4.buf0), line:53:10, endln:53:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand4.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand4 (work@sky130_fd_sc_hd__nand4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nand4 @@ -27138,6 +28293,13 @@ design: (work@sky130_fd_sc_hd__mux2) \_logic_net: (work@sky130_fd_sc_hd__mux2.S), line:40:5, endln:40:6 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__mux2.buf0), line:54:35, endln:54:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__mux2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__mux2 (work@sky130_fd_sc_hd__mux2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__mux2.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__mux2 @@ -27362,6 +28524,20 @@ design: (work@sky130_fd_sc_hd__nand2) \_logic_net: (work@sky130_fd_sc_hd__nand2.B), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand2.nand0), line:48:10, endln:48:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__nand2.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand2.buf0), line:49:10, endln:49:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand2 (work@sky130_fd_sc_hd__nand2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__nand2 @@ -27757,6 +28933,27 @@ design: (work@sky130_fd_sc_hd__dlrbp) \_logic_net: (work@sky130_fd_sc_hd__dlrbp.GATE), line:42:5, endln:42:9 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbp.not0), line:57:48, endln:57:81 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlrbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbp.buf0), line:59:48, endln:59:81 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlrbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbp.not1), line:60:48, endln:60:81 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dlrbp.not1 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlrbp (work@sky130_fd_sc_hd__dlrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbp.functional.v, line:37:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__dlrbp @@ -28132,6 +29329,34 @@ design: (work@sky130_fd_sc_hd__o2bb2a) \_logic_net: (work@sky130_fd_sc_hd__o2bb2a.B2), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2a.nand0), line:56:10, endln:56:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2a.or0), line:57:10, endln:57:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2a.and0), line:58:10, endln:58:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2a.buf0), line:59:10, endln:59:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o2bb2a (work@sky130_fd_sc_hd__o2bb2a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2bb2a @@ -28749,6 +29974,13 @@ design: (work@sky130_fd_sc_hd__edfxtp) \_logic_net: (work@sky130_fd_sc_hd__edfxtp.DE), line:42:5, endln:42:7 |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__edfxtp.buf0), line:58:47, endln:58:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__edfxtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__edfxtp (work@sky130_fd_sc_hd__edfxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxtp.functional.v, line:38:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__edfxtp @@ -29322,6 +30554,34 @@ design: (work@sky130_fd_sc_hd__sdfbbp) \_logic_net: (work@sky130_fd_sc_hd__sdfbbp.RESET_B), line:46:5, endln:46:12 |vpiTypedef: \_logic_typespec: , line:57:12, endln:57:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbp.not0), line:66:47, endln:66:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbp.not1), line:67:47, endln:67:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbp.buf0), line:70:47, endln:70:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfbbp.not2), line:71:47, endln:71:92 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 + |vpiName:not2 + |vpiFullName:work@sky130_fd_sc_hd__sdfbbp.not2 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfbbp (work@sky130_fd_sc_hd__sdfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfbbp.functional.v, line:38:1, endln:73:10 |vpiName:work@sky130_fd_sc_hd__sdfbbp @@ -30057,6 +31317,20 @@ design: (work@sky130_fd_sc_hd__sdfrtp) \_logic_net: (work@sky130_fd_sc_hd__sdfrtp.RESET_B), line:44:5, endln:44:12 |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrtp.not0), line:61:47, endln:61:87 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfrtp.buf0), line:64:47, endln:64:87 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfrtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfrtp (work@sky130_fd_sc_hd__sdfrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfrtp.functional.v, line:38:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__sdfrtp @@ -30691,6 +31965,20 @@ design: (work@sky130_fd_sc_hd__sdfstp) \_logic_net: (work@sky130_fd_sc_hd__sdfstp.SET_B), line:44:5, endln:44:10 |vpiTypedef: \_logic_typespec: , line:53:12, endln:53:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfstp.not0), line:61:47, endln:61:85 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfstp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfstp.buf0), line:64:47, endln:64:85 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfstp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfstp (work@sky130_fd_sc_hd__sdfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfstp.functional.v, line:38:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__sdfstp @@ -31071,6 +32359,34 @@ design: (work@sky130_fd_sc_hd__a22o) \_logic_net: (work@sky130_fd_sc_hd__a22o.B2), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22o.and0), line:56:9, endln:56:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a22o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22o.and1), line:57:9, endln:57:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__a22o.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22o.or0), line:58:9, endln:58:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a22o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a22o.buf0), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a22o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a22o (work@sky130_fd_sc_hd__a22o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a22o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a22o @@ -31538,6 +32854,27 @@ design: (work@sky130_fd_sc_hd__o31a) \_logic_net: (work@sky130_fd_sc_hd__o31a.B1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o31a.or0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o31a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o31a.and0), line:56:9, endln:56:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o31a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o31a.buf0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o31a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o31a (work@sky130_fd_sc_hd__o31a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31a.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o31a @@ -31878,6 +33215,20 @@ design: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr) \_logic_net: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_clkbufkapwr (work@sky130_fd_sc_hd__lpflow_clkbufkapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_clkbufkapwr.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_clkbufkapwr @@ -32077,6 +33428,13 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0n) \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0n.SLEEP_B), line:38:5, endln:38:12 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputiso0n.and0), line:47:9, endln:47:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0n.and0 + |vpiPrimType:1 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0n (work@sky130_fd_sc_hd__lpflow_inputiso0n), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0n.functional.v, line:35:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso0n @@ -32361,6 +33719,20 @@ design: (work@sky130_fd_sc_hd__or2) \_logic_net: (work@sky130_fd_sc_hd__or2.B), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or2.or0), line:48:9, endln:48:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or2.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or2.buf0), line:49:9, endln:49:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or2 (work@sky130_fd_sc_hd__or2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__or2 @@ -32671,6 +34043,34 @@ design: (work@sky130_fd_sc_hd__a221o) \_logic_net: (work@sky130_fd_sc_hd__a221o.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221o.and0), line:58:9, endln:58:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a221o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221o.and1), line:59:9, endln:59:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__a221o.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221o.or0), line:60:9, endln:60:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a221o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221o.buf0), line:61:9, endln:61:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a221o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a221o (work@sky130_fd_sc_hd__a221o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221o.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__a221o @@ -33145,6 +34545,20 @@ design: (work@sky130_fd_sc_hd__and4) \_logic_net: (work@sky130_fd_sc_hd__and4.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4.and0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and4.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4.buf0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and4.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and4 (work@sky130_fd_sc_hd__and4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__and4 @@ -33459,6 +34873,20 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso0p) \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso0p.SLEEP), line:38:5, endln:38:10 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputiso0p.not0), line:50:9, endln:50:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputiso0p.and0), line:51:9, endln:51:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso0p.and0 + |vpiPrimType:1 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso0p (work@sky130_fd_sc_hd__lpflow_inputiso0p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso0p @@ -33683,6 +35111,20 @@ design: (work@sky130_fd_sc_hd__buf) \_logic_net: (work@sky130_fd_sc_hd__buf.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__buf.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__buf.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__buf.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__buf.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__buf (work@sky130_fd_sc_hd__buf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__buf.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__buf @@ -33914,6 +35356,27 @@ design: (work@sky130_fd_sc_hd__o21a) \_logic_net: (work@sky130_fd_sc_hd__o21a.B1), line:39:5, endln:39:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21a.or0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o21a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21a.and0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o21a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21a.buf0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o21a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o21a (work@sky130_fd_sc_hd__o21a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21a.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__o21a @@ -34254,6 +35717,20 @@ design: (work@sky130_fd_sc_hd__xnor3) \_logic_net: (work@sky130_fd_sc_hd__xnor3.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xnor3.xnor0), line:50:10, endln:50:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + |vpiName:xnor0 + |vpiFullName:work@sky130_fd_sc_hd__xnor3.xnor0 + |vpiPrimType:6 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xnor3.buf0), line:51:10, endln:51:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__xnor3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__xnor3 (work@sky130_fd_sc_hd__xnor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor3.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__xnor3 @@ -34557,6 +36034,27 @@ design: (work@sky130_fd_sc_hd__and3b) \_logic_net: (work@sky130_fd_sc_hd__and3b.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and3b.not0), line:51:9, endln:51:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__and3b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and3b.and0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and3b.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and3b.buf0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and3b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and3b (work@sky130_fd_sc_hd__and3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and3b.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__and3b @@ -34929,6 +36427,34 @@ design: (work@sky130_fd_sc_hd__o22ai) \_logic_net: (work@sky130_fd_sc_hd__o22ai.B2), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22ai.nor0), line:56:9, endln:56:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__o22ai.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22ai.nor1), line:57:9, endln:57:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + |vpiName:nor1 + |vpiFullName:work@sky130_fd_sc_hd__o22ai.nor1 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22ai.or0), line:58:9, endln:58:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o22ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o22ai.buf0), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o22ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o22ai (work@sky130_fd_sc_hd__o22ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o22ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o22ai @@ -35356,6 +36882,27 @@ design: (work@sky130_fd_sc_hd__o21ai) \_logic_net: (work@sky130_fd_sc_hd__o21ai.B1), line:39:5, endln:39:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21ai.or0), line:53:10, endln:53:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o21ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21ai.nand0), line:54:10, endln:54:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o21ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21ai.buf0), line:55:10, endln:55:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o21ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o21ai (work@sky130_fd_sc_hd__o21ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21ai.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__o21ai @@ -35739,6 +37286,27 @@ design: (work@sky130_fd_sc_hd__o41a) \_logic_net: (work@sky130_fd_sc_hd__o41a.B1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o41a.or0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o41a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o41a.and0), line:58:9, endln:58:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o41a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o41a.buf0), line:59:9, endln:59:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o41a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o41a (work@sky130_fd_sc_hd__o41a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o41a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o41a @@ -36306,6 +37874,20 @@ design: (work@sky130_fd_sc_hd__clkdlybuf4s50) \_logic_net: (work@sky130_fd_sc_hd__clkdlybuf4s50.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s50.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__clkdlybuf4s50.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__clkdlybuf4s50.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__clkdlybuf4s50 (work@sky130_fd_sc_hd__clkdlybuf4s50), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__clkdlybuf4s50.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__clkdlybuf4s50 @@ -36555,6 +38137,27 @@ design: (work@sky130_fd_sc_hd__or4b) \_logic_net: (work@sky130_fd_sc_hd__or4b.D_N), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4b.not0), line:53:9, endln:53:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__or4b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4b.or0), line:54:9, endln:54:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or4b.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or4b.buf0), line:55:9, endln:55:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or4b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or4b (work@sky130_fd_sc_hd__or4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__or4b @@ -36895,6 +38498,20 @@ design: (work@sky130_fd_sc_hd__dlymetal6s4s) \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s4s.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlymetal6s4s.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlymetal6s4s.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s4s.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlymetal6s4s (work@sky130_fd_sc_hd__dlymetal6s4s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s4s.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__dlymetal6s4s @@ -37161,6 +38778,34 @@ design: (work@sky130_fd_sc_hd__a2bb2o) \_logic_net: (work@sky130_fd_sc_hd__a2bb2o.B2), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2o.and0), line:57:9, endln:57:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2o.nor0), line:58:9, endln:58:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2o.or0), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2o.buf0), line:60:9, endln:60:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a2bb2o (work@sky130_fd_sc_hd__a2bb2o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2o.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__a2bb2o @@ -37796,6 +39441,20 @@ design: (work@sky130_fd_sc_hd__edfxbp) \_logic_net: (work@sky130_fd_sc_hd__edfxbp.DE), line:43:5, endln:43:7 |vpiTypedef: \_logic_typespec: , line:51:12, endln:51:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__edfxbp.buf0), line:60:47, endln:60:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__edfxbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__edfxbp.not0), line:61:47, endln:61:83 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__edfxbp.not0 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__edfxbp (work@sky130_fd_sc_hd__edfxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__edfxbp.functional.v, line:38:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__edfxbp @@ -38260,6 +39919,27 @@ design: (work@sky130_fd_sc_hd__dfrbp) \_logic_net: (work@sky130_fd_sc_hd__dfrbp.RESET_B), line:41:5, endln:41:12 |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrbp.not0), line:56:45, endln:56:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfrbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrbp.buf0), line:58:45, endln:58:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfrbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrbp.not1), line:59:45, endln:59:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dfrbp.not1 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfrbp (work@sky130_fd_sc_hd__dfrbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrbp.functional.v, line:36:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__dfrbp @@ -38698,6 +40378,34 @@ design: (work@sky130_fd_sc_hd__sdlclkp) \_logic_net: (work@sky130_fd_sc_hd__sdlclkp.CLK), line:40:5, endln:40:8 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdlclkp.not0), line:56:35, endln:56:70 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdlclkp.not1), line:57:35, endln:57:70 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdlclkp.nor0), line:58:35, endln:58:70 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdlclkp.and0), line:60:35, endln:60:70 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__sdlclkp.and0 + |vpiPrimType:1 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdlclkp (work@sky130_fd_sc_hd__sdlclkp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdlclkp.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__sdlclkp @@ -39143,6 +40851,27 @@ design: (work@sky130_fd_sc_hd__o311ai) \_logic_net: (work@sky130_fd_sc_hd__o311ai.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o311ai.or0), line:57:10, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o311ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o311ai.nand0), line:58:10, endln:58:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o311ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o311ai.buf0), line:59:10, endln:59:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o311ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o311ai (work@sky130_fd_sc_hd__o311ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o311ai @@ -39601,6 +41330,55 @@ design: (work@sky130_fd_sc_hd__fah) \_logic_net: (work@sky130_fd_sc_hd__fah.CI), line:38:5, endln:38:7 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.xor0), line:56:9, endln:56:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:xor0 + |vpiFullName:work@sky130_fd_sc_hd__fah.xor0 + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.buf0), line:57:9, endln:57:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__fah.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.and0), line:58:9, endln:58:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__fah.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.and1), line:59:9, endln:59:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__fah.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.and2), line:60:9, endln:60:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:and2 + |vpiFullName:work@sky130_fd_sc_hd__fah.and2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.or0), line:61:9, endln:61:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__fah.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fah.buf1), line:62:9, endln:62:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__fah.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__fah (work@sky130_fd_sc_hd__fah), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fah.functional.v, line:33:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__fah @@ -40225,6 +42003,27 @@ design: (work@sky130_fd_sc_hd__nand4bb) \_logic_net: (work@sky130_fd_sc_hd__nand4bb.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4bb.nand0), line:53:10, endln:53:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__nand4bb.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4bb.or0), line:54:10, endln:54:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__nand4bb.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4bb.buf0), line:55:10, endln:55:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand4bb.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand4bb (work@sky130_fd_sc_hd__nand4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nand4bb @@ -40590,6 +42389,27 @@ design: (work@sky130_fd_sc_hd__nand2b) \_logic_net: (work@sky130_fd_sc_hd__nand2b.B), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand2b.not0), line:49:9, endln:49:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__nand2b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand2b.or0), line:50:9, endln:50:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__nand2b.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand2b.buf0), line:51:9, endln:51:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand2b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand2b (work@sky130_fd_sc_hd__nand2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand2b.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__nand2b @@ -40894,6 +42714,20 @@ design: (work@sky130_fd_sc_hd__nor3) \_logic_net: (work@sky130_fd_sc_hd__nor3.C), line:39:5, endln:39:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor3.nor0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__nor3.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor3.buf0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor3 (work@sky130_fd_sc_hd__nor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nor3 @@ -41215,6 +43049,27 @@ design: (work@sky130_fd_sc_hd__a211o) \_logic_net: (work@sky130_fd_sc_hd__a211o.C1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a211o.and0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a211o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a211o.or0), line:56:9, endln:56:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a211o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a211o.buf0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a211o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a211o (work@sky130_fd_sc_hd__a211o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a211o.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a211o @@ -41672,6 +43527,27 @@ design: (work@sky130_fd_sc_hd__dlxbn) \_logic_net: (work@sky130_fd_sc_hd__dlxbn.GATE_N), line:40:5, endln:40:11 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxbn.not0), line:54:47, endln:54:80 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlxbn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxbn.buf0), line:56:47, endln:56:80 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlxbn.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxbn.not1), line:57:47, endln:57:80 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dlxbn.not1 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlxbn (work@sky130_fd_sc_hd__dlxbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbn.functional.v, line:36:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__dlxbn @@ -42014,6 +43890,41 @@ design: (work@sky130_fd_sc_hd__maj3) \_logic_net: (work@sky130_fd_sc_hd__maj3.C), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__maj3.or0), line:53:9, endln:53:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__maj3.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__maj3.and0), line:54:9, endln:54:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__maj3.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__maj3.and1), line:55:9, endln:55:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__maj3.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__maj3.or1), line:56:9, endln:56:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + |vpiName:or1 + |vpiFullName:work@sky130_fd_sc_hd__maj3.or1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__maj3.buf0), line:57:9, endln:57:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__maj3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__maj3 (work@sky130_fd_sc_hd__maj3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__maj3.functional.v, line:33:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__maj3 @@ -42477,6 +44388,27 @@ design: (work@sky130_fd_sc_hd__a21bo) \_logic_net: (work@sky130_fd_sc_hd__a21bo.B1_N), line:40:5, endln:40:9 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21bo.nand0), line:54:10, endln:54:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__a21bo.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21bo.nand1), line:55:10, endln:55:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + |vpiName:nand1 + |vpiFullName:work@sky130_fd_sc_hd__a21bo.nand1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21bo.buf0), line:56:10, endln:56:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a21bo.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a21bo (work@sky130_fd_sc_hd__a21bo), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21bo.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__a21bo @@ -42959,6 +44891,34 @@ design: (work@sky130_fd_sc_hd__dlrbn) \_logic_net: (work@sky130_fd_sc_hd__dlrbn.GATE_N), line:42:5, endln:42:11 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbn.not0), line:58:48, endln:58:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlrbn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbn.not1), line:59:48, endln:59:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dlrbn.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbn.buf0), line:61:48, endln:61:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlrbn.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrbn.not2), line:62:48, endln:62:84 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 + |vpiName:not2 + |vpiFullName:work@sky130_fd_sc_hd__dlrbn.not2 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlrbn (work@sky130_fd_sc_hd__dlrbn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrbn.functional.v, line:37:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__dlrbn @@ -43402,6 +45362,13 @@ design: (work@sky130_fd_sc_hd__lpflow_inputisolatch) \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputisolatch.SLEEP_B), line:39:5, endln:39:12 |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputisolatch.buf0), line:52:36, endln:52:69 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputisolatch.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_inputisolatch (work@sky130_fd_sc_hd__lpflow_inputisolatch), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputisolatch.functional.v, line:36:1, endln:54:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputisolatch @@ -43672,6 +45639,34 @@ design: (work@sky130_fd_sc_hd__o221ai) \_logic_net: (work@sky130_fd_sc_hd__o221ai.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221ai.or0), line:58:10, endln:58:51 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o221ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221ai.or1), line:59:10, endln:59:51 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + |vpiName:or1 + |vpiFullName:work@sky130_fd_sc_hd__o221ai.or1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221ai.nand0), line:60:10, endln:60:51 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o221ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o221ai.buf0), line:61:10, endln:61:51 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o221ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o221ai (work@sky130_fd_sc_hd__o221ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o221ai.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__o221ai @@ -44171,6 +46166,27 @@ design: (work@sky130_fd_sc_hd__o2111a) \_logic_net: (work@sky130_fd_sc_hd__o2111a.D1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2111a.or0), line:57:9, endln:57:47 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o2111a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2111a.and0), line:58:9, endln:58:47 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o2111a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2111a.buf0), line:59:9, endln:59:47 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o2111a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o2111a (work@sky130_fd_sc_hd__o2111a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2111a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2111a @@ -44608,6 +46624,27 @@ design: (work@sky130_fd_sc_hd__and4b) \_logic_net: (work@sky130_fd_sc_hd__and4b.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4b.not0), line:53:9, endln:53:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__and4b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4b.and0), line:54:9, endln:54:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and4b.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4b.buf0), line:55:9, endln:55:45 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and4b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and4b (work@sky130_fd_sc_hd__and4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__and4b @@ -44966,6 +47003,20 @@ design: (work@sky130_fd_sc_hd__and2) \_logic_net: (work@sky130_fd_sc_hd__and2.B), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and2.and0), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and2.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and2.buf0), line:49:9, endln:49:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and2 (work@sky130_fd_sc_hd__and2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__and2 @@ -45240,6 +47291,34 @@ design: (work@sky130_fd_sc_hd__o21bai) \_logic_net: (work@sky130_fd_sc_hd__o21bai.B1_N), line:40:5, endln:40:9 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21bai.not0), line:55:10, endln:55:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__o21bai.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21bai.or0), line:56:10, endln:56:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o21bai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21bai.nand0), line:57:10, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o21bai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o21bai.buf0), line:58:10, endln:58:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o21bai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o21bai (work@sky130_fd_sc_hd__o21bai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o21bai.functional.v, line:36:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__o21bai @@ -45691,6 +47770,76 @@ design: (work@sky130_fd_sc_hd__fa) \_logic_net: (work@sky130_fd_sc_hd__fa.CIN), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.or0), line:59:9, endln:59:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__fa.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.and0), line:60:9, endln:60:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__fa.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.and1), line:61:9, endln:61:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__fa.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.or1), line:62:9, endln:62:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:or1 + |vpiFullName:work@sky130_fd_sc_hd__fa.or1 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.buf0), line:63:9, endln:63:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__fa.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.and2), line:64:9, endln:64:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:and2 + |vpiFullName:work@sky130_fd_sc_hd__fa.and2 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.nor0), line:65:9, endln:65:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__fa.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.nor1), line:66:9, endln:66:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:nor1 + |vpiFullName:work@sky130_fd_sc_hd__fa.nor1 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.or2), line:67:9, endln:67:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:or2 + |vpiFullName:work@sky130_fd_sc_hd__fa.or2 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__fa.buf1), line:68:9, endln:68:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__fa.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__fa (work@sky130_fd_sc_hd__fa), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__fa.functional.v, line:33:1, endln:70:10 |vpiName:work@sky130_fd_sc_hd__fa @@ -46475,6 +48624,27 @@ design: (work@sky130_fd_sc_hd__a31oi) \_logic_net: (work@sky130_fd_sc_hd__a31oi.B1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a31oi.and0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a31oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a31oi.nor0), line:56:9, endln:56:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a31oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a31oi.buf0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a31oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a31oi (work@sky130_fd_sc_hd__a31oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31oi.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a31oi @@ -46840,6 +49010,27 @@ design: (work@sky130_fd_sc_hd__nor2b) \_logic_net: (work@sky130_fd_sc_hd__nor2b.B_N), line:38:5, endln:38:8 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor2b.not0), line:51:9, endln:51:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__nor2b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor2b.and0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__nor2b.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor2b.buf0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor2b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor2b (work@sky130_fd_sc_hd__nor2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2b.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__nor2b @@ -47482,6 +49673,27 @@ design: (work@sky130_fd_sc_hd__dfsbp) \_logic_net: (work@sky130_fd_sc_hd__dfsbp.SET_B), line:41:5, endln:41:10 |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfsbp.not0), line:56:45, endln:56:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfsbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfsbp.buf0), line:58:45, endln:58:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfsbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfsbp.not1), line:59:45, endln:59:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dfsbp.not1 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfsbp (work@sky130_fd_sc_hd__dfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfsbp.functional.v, line:36:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__dfsbp @@ -47857,6 +50069,34 @@ design: (work@sky130_fd_sc_hd__a2bb2oi) \_logic_net: (work@sky130_fd_sc_hd__a2bb2oi.B2), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:49:12, endln:49:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2oi.and0), line:57:9, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2oi.nor0), line:58:9, endln:58:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2oi.nor1), line:59:9, endln:59:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + |vpiName:nor1 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.nor1 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a2bb2oi.buf0), line:60:9, endln:60:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a2bb2oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a2bb2oi (work@sky130_fd_sc_hd__a2bb2oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a2bb2oi.functional.v, line:36:1, endln:62:10 |vpiName:work@sky130_fd_sc_hd__a2bb2oi @@ -48413,6 +50653,27 @@ design: (work@sky130_fd_sc_hd__dfrtn) \_logic_net: (work@sky130_fd_sc_hd__dfrtn.RESET_B), line:41:5, endln:41:12 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrtn.not0), line:56:45, endln:56:76 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfrtn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrtn.not1), line:57:45, endln:57:76 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dfrtn.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfrtn.buf0), line:59:45, endln:59:76 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfrtn.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfrtn (work@sky130_fd_sc_hd__dfrtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfrtn.functional.v, line:37:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__dfrtn @@ -48860,6 +51121,20 @@ design: (work@sky130_fd_sc_hd__dlrtp) \_logic_net: (work@sky130_fd_sc_hd__dlrtp.GATE), line:41:5, endln:41:9 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrtp.not0), line:55:48, endln:55:81 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlrtp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlrtp.buf0), line:57:48, endln:57:81 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlrtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlrtp (work@sky130_fd_sc_hd__dlrtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlrtp.functional.v, line:37:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__dlrtp @@ -49171,6 +51446,27 @@ design: (work@sky130_fd_sc_hd__and4bb) \_logic_net: (work@sky130_fd_sc_hd__and4bb.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4bb.nor0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__and4bb.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4bb.and0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and4bb.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and4bb.buf0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and4bb.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and4bb (work@sky130_fd_sc_hd__and4bb), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and4bb.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__and4bb @@ -49590,6 +51886,27 @@ design: (work@sky130_fd_sc_hd__a41o) \_logic_net: (work@sky130_fd_sc_hd__a41o.B1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a41o.and0), line:57:9, endln:57:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a41o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a41o.or0), line:58:9, endln:58:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a41o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a41o.buf0), line:59:9, endln:59:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a41o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a41o (work@sky130_fd_sc_hd__a41o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a41o @@ -50009,6 +52326,34 @@ design: (work@sky130_fd_sc_hd__ha) \_logic_net: (work@sky130_fd_sc_hd__ha.B), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__ha.and0), line:51:9, endln:51:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__ha.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__ha.buf0), line:52:9, endln:52:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__ha.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__ha.xor0), line:53:9, endln:53:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + |vpiName:xor0 + |vpiFullName:work@sky130_fd_sc_hd__ha.xor0 + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__ha.buf1), line:54:9, endln:54:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__ha.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__ha (work@sky130_fd_sc_hd__ha), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__ha.functional.v, line:33:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__ha @@ -50562,6 +52907,34 @@ design: (work@sky130_fd_sc_hd__dfbbp) \_logic_net: (work@sky130_fd_sc_hd__dfbbp.RESET_B), line:43:5, endln:43:12 |vpiTypedef: \_logic_typespec: , line:52:12, endln:52:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbp.not0), line:60:46, endln:60:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfbbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbp.not1), line:61:46, endln:61:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__dfbbp.not1 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbp.buf0), line:63:46, endln:63:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfbbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfbbp.not2), line:64:46, endln:64:79 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 + |vpiName:not2 + |vpiFullName:work@sky130_fd_sc_hd__dfbbp.not2 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfbbp (work@sky130_fd_sc_hd__dfbbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfbbp.functional.v, line:37:1, endln:66:10 |vpiName:work@sky130_fd_sc_hd__dfbbp @@ -50946,6 +53319,13 @@ design: (work@sky130_fd_sc_hd__lpflow_inputiso1p) \_logic_net: (work@sky130_fd_sc_hd__lpflow_inputiso1p.SLEEP), line:38:5, endln:38:10 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_inputiso1p.or0), line:47:9, endln:47:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_inputiso1p.or0 + |vpiPrimType:4 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_inputiso1p (work@sky130_fd_sc_hd__lpflow_inputiso1p), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_inputiso1p.functional.v, line:35:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__lpflow_inputiso1p @@ -51205,6 +53585,27 @@ design: (work@sky130_fd_sc_hd__a311o) \_logic_net: (work@sky130_fd_sc_hd__a311o.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a311o.and0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a311o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a311o.or0), line:58:9, endln:58:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a311o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a311o.buf0), line:59:9, endln:59:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a311o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a311o (work@sky130_fd_sc_hd__a311o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311o.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a311o @@ -51680,6 +54081,20 @@ design: (work@sky130_fd_sc_hd__dlxtn) \_logic_net: (work@sky130_fd_sc_hd__dlxtn.GATE_N), line:39:5, endln:39:11 |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxtn.not0), line:52:35, endln:52:68 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlxtn.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxtn.buf0), line:54:35, endln:54:68 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlxtn.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlxtn (work@sky130_fd_sc_hd__dlxtn), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtn.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__dlxtn @@ -51987,6 +54402,27 @@ design: (work@sky130_fd_sc_hd__a41oi) \_logic_net: (work@sky130_fd_sc_hd__a41oi.B1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a41oi.and0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a41oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a41oi.nor0), line:58:9, endln:58:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a41oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a41oi.buf0), line:59:9, endln:59:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a41oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a41oi (work@sky130_fd_sc_hd__a41oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a41oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a41oi @@ -52681,6 +55117,27 @@ design: (work@sky130_fd_sc_hd__sdfsbp) \_logic_net: (work@sky130_fd_sc_hd__sdfsbp.SET_B), line:45:5, endln:45:10 |vpiTypedef: \_logic_typespec: , line:55:12, endln:55:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfsbp.not0), line:63:47, endln:63:85 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfsbp.buf0), line:66:47, endln:66:85 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__sdfsbp.not1), line:67:47, endln:67:85 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 + |vpiName:not1 + |vpiFullName:work@sky130_fd_sc_hd__sdfsbp.not1 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__sdfsbp (work@sky130_fd_sc_hd__sdfsbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__sdfsbp.functional.v, line:38:1, endln:69:10 |vpiName:work@sky130_fd_sc_hd__sdfsbp @@ -53234,6 +55691,13 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell) \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.A), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.buf0), line:45:9, endln:45:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.v, line:35:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell @@ -53378,6 +55842,20 @@ design: (work@sky130_fd_sc_hd__bufbuf) \_logic_net: (work@sky130_fd_sc_hd__bufbuf.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__bufbuf.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__bufbuf.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__bufbuf.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__bufbuf.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__bufbuf (work@sky130_fd_sc_hd__bufbuf), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__bufbuf.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__bufbuf @@ -53602,6 +56080,20 @@ design: (work@sky130_fd_sc_hd__xor3) \_logic_net: (work@sky130_fd_sc_hd__xor3.C), line:39:5, endln:39:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xor3.xor0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + |vpiName:xor0 + |vpiFullName:work@sky130_fd_sc_hd__xor3.xor0 + |vpiPrimType:5 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xor3.buf0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__xor3.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__xor3 (work@sky130_fd_sc_hd__xor3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xor3.functional.v, line:35:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__xor3 @@ -53930,6 +56422,34 @@ design: (work@sky130_fd_sc_hd__o2bb2ai) \_logic_net: (work@sky130_fd_sc_hd__o2bb2ai.B2), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2ai.nand0), line:56:10, endln:56:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2ai.or0), line:57:10, endln:57:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2ai.nand1), line:58:10, endln:58:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + |vpiName:nand1 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.nand1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o2bb2ai.buf0), line:59:10, endln:59:49 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o2bb2ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o2bb2ai (work@sky130_fd_sc_hd__o2bb2ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o2bb2ai.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o2bb2ai @@ -54332,6 +56852,20 @@ design: (work@sky130_fd_sc_hd__nor2) \_logic_net: (work@sky130_fd_sc_hd__nor2.B), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor2.nor0), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__nor2.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor2.buf0), line:49:9, endln:49:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor2 (work@sky130_fd_sc_hd__nor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor2.functional.v, line:33:1, endln:51:10 |vpiName:work@sky130_fd_sc_hd__nor2 @@ -54666,6 +57200,20 @@ design: (work@sky130_fd_sc_hd__dlxbp) \_logic_net: (work@sky130_fd_sc_hd__dlxbp.GATE), line:40:5, endln:40:9 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxbp.buf0), line:54:47, endln:54:80 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlxbp.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxbp.not0), line:55:47, endln:55:80 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dlxbp.not0 + |vpiPrimType:8 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlxbp (work@sky130_fd_sc_hd__dlxbp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxbp.functional.v, line:36:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__dlxbp @@ -54900,6 +57448,13 @@ design: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap) \_logic_net: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.A), line:37:5, endln:37:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.buf0), line:45:9, endln:45:39 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.v, line:35:1, endln:47:10 |vpiName:work@sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap @@ -55087,6 +57642,27 @@ design: (work@sky130_fd_sc_hd__or3b) \_logic_net: (work@sky130_fd_sc_hd__or3b.C_N), line:37:5, endln:37:8 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or3b.not0), line:51:9, endln:51:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__or3b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or3b.or0), line:52:9, endln:52:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__or3b.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__or3b.buf0), line:53:9, endln:53:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__or3b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__or3b (work@sky130_fd_sc_hd__or3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__or3b.functional.v, line:33:1, endln:55:10 |vpiName:work@sky130_fd_sc_hd__or3b @@ -55409,6 +57985,20 @@ design: (work@sky130_fd_sc_hd__xnor2) \_logic_net: (work@sky130_fd_sc_hd__xnor2.B), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:44:12, endln:44:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xnor2.xnor0), line:50:10, endln:50:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + |vpiName:xnor0 + |vpiFullName:work@sky130_fd_sc_hd__xnor2.xnor0 + |vpiPrimType:6 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__xnor2.buf0), line:51:10, endln:51:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__xnor2.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__xnor2 (work@sky130_fd_sc_hd__xnor2), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__xnor2.functional.v, line:35:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__xnor2 @@ -55694,6 +58284,27 @@ design: (work@sky130_fd_sc_hd__o211a) \_logic_net: (work@sky130_fd_sc_hd__o211a.C1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o211a.or0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o211a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o211a.and0), line:56:9, endln:56:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o211a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o211a.buf0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o211a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o211a (work@sky130_fd_sc_hd__o211a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o211a.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o211a @@ -56077,6 +58688,27 @@ design: (work@sky130_fd_sc_hd__nor3b) \_logic_net: (work@sky130_fd_sc_hd__nor3b.C_N), line:39:5, endln:39:8 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor3b.nor0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__nor3b.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor3b.and0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__nor3b.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor3b.buf0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor3b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor3b (work@sky130_fd_sc_hd__nor3b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor3b.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor3b @@ -56442,6 +59074,27 @@ design: (work@sky130_fd_sc_hd__o31ai) \_logic_net: (work@sky130_fd_sc_hd__o31ai.B1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o31ai.or0), line:55:10, endln:55:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o31ai.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o31ai.nand0), line:56:10, endln:56:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__o31ai.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o31ai.buf0), line:57:10, endln:57:46 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o31ai.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o31ai (work@sky130_fd_sc_hd__o31ai), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o31ai.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__o31ai @@ -56782,6 +59435,20 @@ design: (work@sky130_fd_sc_hd__dlymetal6s6s) \_logic_net: (work@sky130_fd_sc_hd__dlymetal6s6s.A), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:41:12, endln:41:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlymetal6s6s.buf0), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlymetal6s6s.buf1), line:48:9, endln:48:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__dlymetal6s6s.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlymetal6s6s (work@sky130_fd_sc_hd__dlymetal6s6s), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlymetal6s6s.functional.v, line:34:1, endln:50:10 |vpiName:work@sky130_fd_sc_hd__dlymetal6s6s @@ -57049,6 +59716,27 @@ design: (work@sky130_fd_sc_hd__a311oi) \_logic_net: (work@sky130_fd_sc_hd__a311oi.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a311oi.and0), line:57:9, endln:57:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a311oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a311oi.nor0), line:58:9, endln:58:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a311oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a311oi.buf0), line:59:9, endln:59:44 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a311oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a311oi (work@sky130_fd_sc_hd__a311oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a311oi.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__a311oi @@ -57486,6 +60174,27 @@ design: (work@sky130_fd_sc_hd__a31o) \_logic_net: (work@sky130_fd_sc_hd__a31o.B1), line:40:5, endln:40:7 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a31o.and0), line:55:9, endln:55:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a31o.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a31o.or0), line:56:9, endln:56:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__a31o.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a31o.buf0), line:57:9, endln:57:42 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a31o.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a31o (work@sky130_fd_sc_hd__a31o), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a31o.functional.v, line:35:1, endln:59:10 |vpiName:work@sky130_fd_sc_hd__a31o @@ -57887,6 +60596,27 @@ design: (work@sky130_fd_sc_hd__nand4b) \_logic_net: (work@sky130_fd_sc_hd__nand4b.D), line:38:5, endln:38:6 |vpiTypedef: \_logic_typespec: , line:46:12, endln:46:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4b.not0), line:53:10, endln:53:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__nand4b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4b.nand0), line:54:10, endln:54:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__nand4b.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nand4b.buf0), line:55:10, endln:55:48 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nand4b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nand4b (work@sky130_fd_sc_hd__nand4b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nand4b.functional.v, line:33:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nand4b @@ -58252,6 +60982,27 @@ design: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr) \_logic_net: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.A), line:39:5, endln:39:6 |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0), line:52:9, endln:52:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0), line:53:9, endln:53:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.buf0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__lpflow_isobufsrckapwr (work@sky130_fd_sc_hd__lpflow_isobufsrckapwr), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.v, line:36:1, endln:56:10 |vpiName:work@sky130_fd_sc_hd__lpflow_isobufsrckapwr @@ -58570,6 +61321,34 @@ design: (work@sky130_fd_sc_hd__a21boi) \_logic_net: (work@sky130_fd_sc_hd__a21boi.B1_N), line:40:5, endln:40:9 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21boi.not0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__a21boi.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21boi.and0), line:56:9, endln:56:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a21boi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21boi.nor0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a21boi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a21boi.buf0), line:58:9, endln:58:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a21boi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a21boi (work@sky130_fd_sc_hd__a21boi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a21boi.functional.v, line:36:1, endln:60:10 |vpiName:work@sky130_fd_sc_hd__a21boi @@ -58918,6 +61697,20 @@ design: (work@sky130_fd_sc_hd__dlygate4sd1) \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd1.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlygate4sd1.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlygate4sd1.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd1.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlygate4sd1 (work@sky130_fd_sc_hd__dlygate4sd1), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd1.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__dlygate4sd1 @@ -59192,6 +61985,34 @@ design: (work@sky130_fd_sc_hd__a32oi) \_logic_net: (work@sky130_fd_sc_hd__a32oi.B2), line:42:5, endln:42:7 |vpiTypedef: \_logic_typespec: , line:51:12, endln:51:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32oi.nand0), line:59:10, endln:59:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + |vpiName:nand0 + |vpiFullName:work@sky130_fd_sc_hd__a32oi.nand0 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32oi.nand1), line:60:10, endln:60:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + |vpiName:nand1 + |vpiFullName:work@sky130_fd_sc_hd__a32oi.nand1 + |vpiPrimType:2 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32oi.and0), line:61:10, endln:61:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a32oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a32oi.buf0), line:62:10, endln:62:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a32oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a32oi (work@sky130_fd_sc_hd__a32oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a32oi.functional.v, line:36:1, endln:64:10 |vpiName:work@sky130_fd_sc_hd__a32oi @@ -59691,6 +62512,27 @@ design: (work@sky130_fd_sc_hd__o311a) \_logic_net: (work@sky130_fd_sc_hd__o311a.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o311a.or0), line:57:9, endln:57:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + |vpiName:or0 + |vpiFullName:work@sky130_fd_sc_hd__o311a.or0 + |vpiPrimType:4 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o311a.and0), line:58:9, endln:58:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__o311a.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__o311a.buf0), line:59:9, endln:59:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__o311a.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__o311a (work@sky130_fd_sc_hd__o311a), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__o311a.functional.v, line:35:1, endln:61:10 |vpiName:work@sky130_fd_sc_hd__o311a @@ -60092,6 +62934,27 @@ design: (work@sky130_fd_sc_hd__and2b) \_logic_net: (work@sky130_fd_sc_hd__and2b.B), line:36:5, endln:36:6 |vpiTypedef: \_logic_typespec: , line:42:12, endln:42:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and2b.not0), line:49:9, endln:49:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__and2b.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and2b.and0), line:50:9, endln:50:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__and2b.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__and2b.buf0), line:51:9, endln:51:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__and2b.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__and2b (work@sky130_fd_sc_hd__and2b), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__and2b.functional.v, line:33:1, endln:53:10 |vpiName:work@sky130_fd_sc_hd__and2b @@ -60446,6 +63309,34 @@ design: (work@sky130_fd_sc_hd__a221oi) \_logic_net: (work@sky130_fd_sc_hd__a221oi.C1), line:41:5, endln:41:7 |vpiTypedef: \_logic_typespec: , line:50:12, endln:50:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221oi.and0), line:58:9, endln:58:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + |vpiName:and0 + |vpiFullName:work@sky130_fd_sc_hd__a221oi.and0 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221oi.and1), line:59:9, endln:59:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + |vpiName:and1 + |vpiFullName:work@sky130_fd_sc_hd__a221oi.and1 + |vpiPrimType:1 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221oi.nor0), line:60:9, endln:60:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__a221oi.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__a221oi.buf0), line:61:9, endln:61:50 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__a221oi.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__a221oi (work@sky130_fd_sc_hd__a221oi), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__a221oi.functional.v, line:35:1, endln:63:10 |vpiName:work@sky130_fd_sc_hd__a221oi @@ -60958,6 +63849,13 @@ design: (work@sky130_fd_sc_hd__dlxtp) \_logic_net: (work@sky130_fd_sc_hd__dlxtp.GATE), line:39:5, endln:39:9 |vpiTypedef: \_logic_typespec: , line:45:12, endln:45:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlxtp.buf0), line:52:35, endln:52:68 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlxtp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlxtp (work@sky130_fd_sc_hd__dlxtp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlxtp.functional.v, line:36:1, endln:54:10 |vpiName:work@sky130_fd_sc_hd__dlxtp @@ -61307,6 +64205,20 @@ design: (work@sky130_fd_sc_hd__dfstp) \_logic_net: (work@sky130_fd_sc_hd__dfstp.SET_B), line:40:5, endln:40:10 |vpiTypedef: \_logic_typespec: , line:47:12, endln:47:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfstp.not0), line:54:45, endln:54:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + |vpiName:not0 + |vpiFullName:work@sky130_fd_sc_hd__dfstp.not0 + |vpiPrimType:8 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dfstp.buf0), line:56:45, endln:56:75 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dfstp.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dfstp (work@sky130_fd_sc_hd__dfstp), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dfstp.functional.v, line:36:1, endln:58:10 |vpiName:work@sky130_fd_sc_hd__dfstp @@ -61755,6 +64667,20 @@ design: (work@sky130_fd_sc_hd__nor4) \_logic_net: (work@sky130_fd_sc_hd__nor4.D), line:40:5, endln:40:6 |vpiTypedef: \_logic_typespec: , line:48:12, endln:48:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4.nor0), line:54:9, endln:54:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + |vpiName:nor0 + |vpiFullName:work@sky130_fd_sc_hd__nor4.nor0 + |vpiPrimType:3 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__nor4.buf0), line:55:9, endln:55:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__nor4.buf0 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__nor4 (work@sky130_fd_sc_hd__nor4), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__nor4.functional.v, line:35:1, endln:57:10 |vpiName:work@sky130_fd_sc_hd__nor4 @@ -62051,6 +64977,20 @@ design: (work@sky130_fd_sc_hd__dlygate4sd3) \_logic_net: (work@sky130_fd_sc_hd__dlygate4sd3.A), line:35:5, endln:35:6 |vpiTypedef: \_logic_typespec: , line:40:12, endln:40:12 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlygate4sd3.buf0), line:46:9, endln:46:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + |vpiName:buf0 + |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.buf0 + |vpiPrimType:7 + |vpiPrimitive: + \_gate: (work@sky130_fd_sc_hd__dlygate4sd3.buf1), line:47:9, endln:47:43 + |vpiParent: + \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 + |vpiName:buf1 + |vpiFullName:work@sky130_fd_sc_hd__dlygate4sd3.buf1 + |vpiPrimType:7 |uhdmtopModules: \_module_inst: work@sky130_fd_sc_hd__dlygate4sd3 (work@sky130_fd_sc_hd__dlygate4sd3), file:${SURELOG_DIR}/third_party/tests/Sky130Cell/cells/cells/sky130_fd_sc_hd__dlygate4sd3.functional.v, line:33:1, endln:49:10 |vpiName:work@sky130_fd_sc_hd__dlygate4sd3 diff --git a/third_party/tests/ariane/Ariane.log b/third_party/tests/ariane/Ariane.log index 5fd182c16c..db5a8a431d 100644 --- a/third_party/tests/ariane/Ariane.log +++ b/third_party/tests/ariane/Ariane.log @@ -1,4 +1,3 @@ -make[1]: Entering directory '${SURELOG_DIR}/third_party/tests/ariane' Makefile:139: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM [Verilator] Building Model ${SURELOG_DIR}/build/bin/surelog -DVERILATOR=1 -sverilog -parse -d coveruhdm -verbose -timescale=1ps/1ps ${SURELOG_DIR}/third_party/tests/ariane/include/riscv_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/ariane_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/std_cache_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/wt_cache_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/register_interface/src/reg_intf.sv ${SURELOG_DIR}/third_party/tests/ariane/src/register_interface/src/reg_intf_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/axi_intf.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_soc_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_axi_soc_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/ariane_axi_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/alu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/amo_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ariane_regfile_ff.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ariane.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_adapter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_shim.sv ${SURELOG_DIR}/third_party/tests/ariane/src/branch_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/commit_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/compressed_decoder.sv ${SURELOG_DIR}/third_party/tests/ariane/src/controller.sv ${SURELOG_DIR}/third_party/tests/ariane/src/csr_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/csr_regfile.sv ${SURELOG_DIR}/third_party/tests/ariane/src/decoder.sv ${SURELOG_DIR}/third_party/tests/ariane/src/dromajo_ram.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ex_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/id_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/instr_realign.sv ${SURELOG_DIR}/third_party/tests/ariane/src/issue_read_operands.sv ${SURELOG_DIR}/third_party/tests/ariane/src/issue_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/load_store_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/load_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/mmu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/multiplier.sv ${SURELOG_DIR}/third_party/tests/ariane/src/mult.sv ${SURELOG_DIR}/third_party/tests/ariane/src/perf_counters.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ptw.sv ${SURELOG_DIR}/third_party/tests/ariane/src/re_name.sv ${SURELOG_DIR}/third_party/tests/ariane/src/scoreboard.sv ${SURELOG_DIR}/third_party/tests/ariane/src/serdiv.sv ${SURELOG_DIR}/third_party/tests/ariane/src/store_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/store_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tlb.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_cast_multi.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_classifier.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_divsqrt_multi.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_fma_multi.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_fma.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_noncomp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_opgroup_block.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_opgroup_fmt_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_opgroup_multifmt_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_rounding.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/bht.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/btb.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/frontend.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/instr_queue.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/instr_scan.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/ras.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/amo_alu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/cache_ctrl.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/cva6_icache_axi_wrapper.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/cva6_icache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/miss_handler.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/std_cache_subsystem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/std_icache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/std_nbdcache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/tag_cmp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_axi_adapter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_cache_subsystem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_ctrl.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_mem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_missunit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_wbuffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_icache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_l15_adapter.sv ${SURELOG_DIR}/third_party/tests/ariane/bootrom/bootrom.sv ${SURELOG_DIR}/third_party/tests/ariane/src/clint/axi_lite_interface.sv ${SURELOG_DIR}/third_party/tests/ariane/src/clint/clint.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi2apb/src/axi2apb_64_32.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi2apb/src/axi2apb.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi2apb/src/axi2apb_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/apb_timer/apb_timer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/apb_timer/timer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_ar_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_aw_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_b_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_r_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_single_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_slice_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_w_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/apb_regs_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_AR.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_AW.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_BR.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_BW.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_DW.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_AR_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_AW_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_BR_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_BW_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_DW_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_multiplexer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_arbiter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_wrap_with_slices.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_regs_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_request_block.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_response_block.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_res_tbl.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_amos.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_atomics.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_mem_if/src/axi2mem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/pmp/src/pmp_entry.sv ${SURELOG_DIR}/third_party/tests/ariane/src/pmp/src/pmp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/rv_plic_target.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/rv_plic_gateway.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/plic_regmap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/plic_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dmi_cdc.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dmi_jtag.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dmi_jtag_tap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_csrs.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_mem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_sba.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/debug_rom/debug_rom.sv ${SURELOG_DIR}/third_party/tests/ariane/src/register_interface/src/apb_to_reg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_multicut.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/generic_fifo.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/pulp_sync.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/find_first_one.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/rstgen_bypass.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/rstgen.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_mux.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_demux.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/exp_backoff.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_master_connect.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_slave_connect.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_master_connect_rev.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_slave_connect_rev.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_cut.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_join.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_delayer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_to_axi_lite.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpga-support/rtl/SyncSpRamBeNx64.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/unread.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/sync.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/cdc_2phase.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/spill_register.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/sync_wedge.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/edge_detect.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_arbiter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_arbiter_flushable.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/fifo_v1.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/fifo_v2.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/fifo_v3.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/lzc.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/popcount.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/rr_arb_tree.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/rrarbiter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_delay.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/lfsr_8bit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/lfsr_16bit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/delta_counter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/counter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/shift_reg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tech_cells_generic/src/pulp_clock_gating.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tech_cells_generic/src/cluster_clock_inverter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tech_cells_generic/src/pulp_clock_mux2.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_testharness.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_peripherals.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/common/uart.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/common/SimDTM.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/common/SimJTAG.sv +define+WT_DCACHE src/util/sram.sv tb/common/mock_uart.sv +incdir+src/axi_node --unroll-count 256 -Werror-PINMISSING -Werror-IMPLICIT -Wno-fatal -Wno-PINCONNECTEMPTY -Wno-ASSIGNDLY -Wno-DECLFILENAME -Wno-UNUSED -Wno-UNOPTFLAT -Wno-BLKANDNBLK -Wno-style -LDFLAGS "-Lblah/lib -Lblah/lib -Wl,-rpath,blah/lib -Wl,-rpath,blah/lib -lfesvr -lpthread" -CFLAGS " -DVL_DEBUG" -Wall --cc --vpi +incdir+src/common_cells/include/ --top-module ariane_testharness --Mdir work-ver -O3 --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc @@ -25432,9 +25431,8 @@ there are 1 more instances of this message. [WARNING] : 19 [ NOTE] : 55 cd work-ver && make -j -f Variane_testharness.mk -make[2]: Entering directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver' -make[2]: Variane_testharness.mk: No such file or directory -make[2]: *** No rule to make target 'Variane_testharness.mk'. Stop. -make[2]: Leaving directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver' -make[1]: *** [Makefile:634: verilate] Error 2 -make[1]: Leaving directory '${SURELOG_DIR}/third_party/tests/ariane' +make[1]: Entering directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver' +make[1]: Variane_testharness.mk: No such file or directory +make[1]: *** No rule to make target 'Variane_testharness.mk'. Stop. +make[1]: Leaving directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver' +make: *** [Makefile:634: verilate] Error 2 diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log index 8a037df1e3..92b32e39f8 100644 --- a/third_party/tests/oh/BasicOh.log +++ b/third_party/tests/oh/BasicOh.log @@ -2,563 +2,563 @@ [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". [INF:CM0029] Using global timescale: "1ns/1ns". @@ -13884,6 +13884,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_lat0 (oh_lat0), line:105:4, endln:105:11 + |vpiParent: + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:oh_lat0 |vpiDefName:work@oh_lat0 |vpiActual: @@ -13940,6 +13942,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_clockmux2 (oh_clockmux2), line:112:4, endln:112:16 + |vpiParent: + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:oh_clockmux2 |vpiDefName:work@oh_clockmux2 |vpiActual: @@ -13998,6 +14002,8 @@ design: (work@oh_fifo_async) |vpiName:clk |vpiRefModule: \_ref_module: work@oh_lat0 (latch_clk1), line:144:4, endln:144:14 + |vpiParent: + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:latch_clk1 |vpiDefName:work@oh_lat0 |vpiActual: @@ -14054,6 +14060,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_clockmux4 (mux_clk1), line:157:4, endln:157:12 + |vpiParent: + \_module_inst: work@oh_clockdiv (work@oh_clockdiv), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v, line:9:1, endln:167:10 |vpiName:mux_clk1 |vpiDefName:work@oh_clockmux4 |vpiActual: @@ -17691,6 +17699,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa32 (csa32_0), line:35:4, endln:35:11 + |vpiParent: + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:csa32_0 |vpiDefName:work@oh_csa32 |vpiActual: @@ -17857,6 +17867,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa32 (csa32_1), line:44:4, endln:44:11 + |vpiParent: + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:csa32_1 |vpiDefName:work@oh_csa32 |vpiActual: @@ -18023,6 +18035,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa42 (csa42), line:53:4, endln:53:9 + |vpiParent: + \_module_inst: work@oh_csa62 (work@oh_csa62), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v, line:8:1, endln:62:10 |vpiName:csa42 |vpiDefName:work@oh_csa42 |vpiActual: @@ -19440,6 +19454,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa32 (csa32_0), line:46:4, endln:46:11 + |vpiParent: + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:csa32_0 |vpiDefName:work@oh_csa32 |vpiActual: @@ -19606,6 +19622,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa32 (csa32_1), line:55:4, endln:55:11 + |vpiParent: + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:csa32_1 |vpiDefName:work@oh_csa32 |vpiActual: @@ -19772,6 +19790,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa32 (csa32_2), line:64:4, endln:64:11 + |vpiParent: + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:csa32_2 |vpiDefName:work@oh_csa32 |vpiActual: @@ -19938,6 +19958,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_csa62 (csa62), line:73:4, endln:73:9 + |vpiParent: + \_module_inst: work@oh_csa92 (work@oh_csa92), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v, line:8:1, endln:88:10 |vpiName:csa62 |vpiDefName:work@oh_csa62 |vpiActual: @@ -21031,6 +21053,8 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_debouncer.clean_out |vpiRefModule: \_ref_module: work@oh_dsync (dsync), line:30:4, endln:30:9 + |vpiParent: + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:dsync |vpiDefName:work@oh_dsync |vpiActual: @@ -21061,6 +21085,8 @@ design: (work@oh_fifo_async) |vpiName:noisy_in |vpiRefModule: \_ref_module: work@oh_rsync (rsync), line:38:4, endln:38:9 + |vpiParent: + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:rsync |vpiDefName:work@oh_rsync |vpiActual: @@ -21085,6 +21111,8 @@ design: (work@oh_fifo_async) |vpiName:nreset |vpiRefModule: \_ref_module: work@oh_counter (oh_counter), line:55:4, endln:55:14 + |vpiParent: + \_module_inst: work@oh_debouncer (work@oh_debouncer), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v, line:8:1, endln:77:10 |vpiName:oh_counter |vpiDefName:work@oh_counter |vpiActual: @@ -26274,6 +26302,8 @@ design: (work@oh_fifo_async) \_logic_net: (work@oh_fifo_async.wr_full), line:28:17, endln:28:24 |vpiRefModule: \_ref_module: work@oh_rsync (wr_rsync), line:74:4, endln:74:12 + |vpiParent: + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_rsync |vpiDefName:work@oh_rsync |vpiActual: @@ -26304,6 +26334,8 @@ design: (work@oh_fifo_async) \_logic_net: (work@oh_fifo_async.nreset), line:23:16, endln:23:22 |vpiRefModule: \_ref_module: work@oh_rsync (rd_rsync), line:80:4, endln:80:12 + |vpiParent: + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_rsync |vpiDefName:work@oh_rsync |vpiActual: @@ -26334,6 +26366,8 @@ design: (work@oh_fifo_async) \_logic_net: (work@oh_fifo_async.nreset), line:23:16, endln:23:22 |vpiRefModule: \_ref_module: work@oh_bin2gray (wr_bin2gray), line:115:4, endln:115:15 + |vpiParent: + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:wr_bin2gray |vpiDefName:work@oh_bin2gray |vpiActual: @@ -26378,6 +26412,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_bin2gray (rd_bin2gray), line:131:4, endln:131:15 + |vpiParent: + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:rd_bin2gray |vpiDefName:work@oh_bin2gray |vpiActual: @@ -26422,6 +26458,8 @@ design: (work@oh_fifo_async) |vpiConstType:9 |vpiRefModule: \_ref_module: work@oh_memory_dp (oh_memory_dp), line:162:4, endln:162:16 + |vpiParent: + \_module_inst: work@oh_fifo_async (work@oh_fifo_async), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 |vpiName:oh_memory_dp |vpiDefName:work@oh_memory_dp |vpiActual: @@ -27372,6 +27410,8 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_cdc.ready_out |vpiRefModule: \_ref_module: work@oh_rsync (sync_reset), line:41:4, endln:41:14 + |vpiParent: + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:sync_reset |vpiDefName:work@oh_rsync |vpiActual: @@ -27396,6 +27436,8 @@ design: (work@oh_fifo_async) |vpiName:nreset |vpiRefModule: \_ref_module: work@oh_fifo_async (oh_fifo_async), line:56:4, endln:56:17 + |vpiParent: + \_module_inst: work@oh_fifo_cdc (work@oh_fifo_cdc), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v, line:8:1, endln:86:10 |vpiName:oh_fifo_async |vpiDefName:work@oh_fifo_async |vpiActual: @@ -29804,6 +29846,8 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_fifo_sync.empty |vpiRefModule: \_ref_module: work@oh_memory_dp (oh_memory_dp), line:120:4, endln:120:16 + |vpiParent: + \_module_inst: work@oh_fifo_sync (work@oh_fifo_sync), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v, line:8:1, endln:144:10 |vpiName:oh_memory_dp |vpiDefName:work@oh_memory_dp |vpiActual: @@ -55722,6 +55766,8 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_pulse2pulse.dout |vpiRefModule: \_ref_module: work@oh_dsync (sync), line:39:4, endln:39:8 + |vpiParent: + \_module_inst: work@oh_pulse2pulse (work@oh_pulse2pulse), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v, line:9:1, endln:53:10 |vpiName:sync |vpiDefName:work@oh_dsync |vpiActual: @@ -60882,6 +60928,8 @@ design: (work@oh_fifo_async) |vpiFullName:work@oh_standby.clk_en |vpiRefModule: \_ref_module: work@oh_dsync (oh_dsync), line:43:4, endln:43:12 + |vpiParent: + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:oh_dsync |vpiDefName:work@oh_dsync |vpiActual: @@ -60912,6 +60960,8 @@ design: (work@oh_fifo_async) |vpiName:clkin |vpiRefModule: \_ref_module: work@oh_edge2pulse (oh_edge2pulse), line:52:18, endln:52:31 + |vpiParent: + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:oh_edge2pulse |vpiDefName:work@oh_edge2pulse |vpiActual: @@ -60942,6 +60992,8 @@ design: (work@oh_fifo_async) |vpiName:sync_reset |vpiRefModule: \_ref_module: work@oh_delay (oh_delay), line:63:4, endln:63:12 + |vpiParent: + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:oh_delay |vpiDefName:work@oh_delay |vpiActual: @@ -60972,6 +61024,8 @@ design: (work@oh_fifo_async) |vpiName:clkin |vpiRefModule: \_ref_module: work@oh_clockgate (oh_clockgate), line:91:17, endln:91:29 + |vpiParent: + \_module_inst: work@oh_standby (work@oh_standby), file:${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v, line:8:1, endln:96:10 |vpiName:oh_clockgate |vpiDefName:work@oh_clockgate |vpiActual: From bfddb1a42704f177af31e17c92bc77f7247d29bb Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 18 Apr 2023 11:18:49 -0700 Subject: [PATCH 2/2] wip non-elab primitive instances --- src/DesignCompile/CompileHelper.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index 1bd9b0a059..a46bf9eecb 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -2460,7 +2460,6 @@ void CompileHelper::compileInstantiation(ModuleDefinition* mod, } } - uint32_t CompileHelper::getBuiltinType(VObjectType type) { switch (type) { case VObjectType::slNInpGate_And: