diff --git a/.vscode/launch.json b/.vscode/launch.json
index 6c1b221017..4ed69db88d 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -1857,6 +1857,25 @@
                     "ignoreFailures": true
                 }
             ]
+        }, 
+        {
+            "name": "YosysVerx",
+            "type": "cppdbg",
+            "request": "launch",
+            "program": "${workspaceFolder}/dbuild/bin/surelog",
+            "args": ["-f", "YosysVerx.sl"],
+            "stopAtEntry": false,
+            "cwd": "${workspaceFolder}/third_party/tests/YosysVerx",
+            "environment": [],
+            "externalConsole": false,
+            "MIMode": "gdb",
+            "setupCommands": [
+                {
+                    "description": "Enable pretty-printing for gdb",
+                    "text": "-enable-pretty-printing",
+                    "ignoreFailures": true
+                }
+            ]
         }
     ]
 }
\ No newline at end of file
diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp
index 0c68a5bb19..bf597195c6 100644
--- a/src/DesignCompile/UhdmWriter.cpp
+++ b/src/DesignCompile/UhdmWriter.cpp
@@ -1932,11 +1932,6 @@ bool UhdmWriter::writeElabGenScope(Serializer& s, ModuleInstance* instance,
     }
   }
 
-  if (mod) {
-    lateTypedefBinding(s, mod, m, componentMap);
-    lateBinding(s, mod, m, componentMap);
-  }
-
   return true;
 }
 
@@ -2893,7 +2888,27 @@ void UhdmWriter::lateBinding(UHDM::Serializer& s, DesignComponent* mod,
       parent = parent->VpiParent();
     }
     if (ref->Actual_group()) continue;
-
+    if (m->UhdmType() == uhdmmodule_inst) {
+      module_inst* minst = (module_inst*)m;
+      if (minst->Interfaces()) {
+        for (auto n : *minst->Interfaces()) {
+          if (n->VpiName() == name) {
+            ref->Actual_group(n);
+            break;
+          }
+        }
+        if (ref->Actual_group()) continue;
+      }
+      if (minst->Interface_arrays()) {
+        for (auto n : *minst->Interface_arrays()) {
+          if (n->VpiName() == name) {
+            ref->Actual_group(n);
+            break;
+          }
+        }
+        if (ref->Actual_group()) continue;
+      }
+    }
     if (m->UhdmType() == uhdmmodule_inst ||
         m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram) {
       instance* inst = (instance*)m;
@@ -3200,13 +3215,6 @@ bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance,
       }
     }
   }
-
-  if (mod) {
-    lateTypedefBinding(s, mod, m, componentMap);
-    lateBinding(s, mod, m, componentMap);
-    lateTypedefBinding(s, mod, m, componentMap);
-  }
-
   return true;
 }
 
@@ -3379,12 +3387,6 @@ bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance,
       }
     }
   }
-
-  if (mod) {
-    lateTypedefBinding(s, mod, m, componentMap);
-    lateBinding(s, mod, m, componentMap);
-  }
-
   return true;
 }
 
@@ -3452,7 +3454,6 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance,
   VectorOfprimitive* subPrimitives = nullptr;
   VectorOfprimitive_array* subPrimitiveArrays = nullptr;
   VectorOfgen_scope_array* subGenScopeArrays = nullptr;
-
   if (m->UhdmType() == uhdmmodule_inst) {
     writeElabModule(s, instance, (module_inst*)m, exprBuilder);
   } else if (m->UhdmType() == uhdmgen_scope) {
@@ -3796,6 +3797,15 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance,
       }
     }
   }
+
+  if (mod && netlist) {
+    scope* sc = dynamic_cast<scope*>(m);
+    if (sc) {
+      lateTypedefBinding(s, mod, sc, componentMap);
+      lateBinding(s, mod, sc, componentMap);
+      lateTypedefBinding(s, mod, sc, componentMap);
+    }
+  }
 }
 
 vpiHandle UhdmWriter::write(PathId uhdmFileId) {
diff --git a/tests/InterfInst/InterfInst.log b/tests/InterfInst/InterfInst.log
new file mode 100644
index 0000000000..5d9106440d
--- /dev/null
+++ b/tests/InterfInst/InterfInst.log
@@ -0,0 +1,574 @@
+[INF:CM0023] Creating log file ${SURELOG_DIR}/build/regression/InterfInst/slpp_all/surelog.log.
+
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/InterfInst/dut.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<126> s<125> l<2:1> el<1:2>
+n<> u<2> t<Interface> p<5> s<4> l<2:1> el<2:10>
+n<sim_sram_if> u<3> t<StringConst> p<4> l<2:11> el<2:22>
+n<> u<4> t<Interface_identifier> p<5> c<3> l<2:11> el<2:22>
+n<> u<5> t<Interface_ansi_header> p<19> c<2> s<17> l<2:1> el<2:23>
+n<> u<6> t<IntegerAtomType_Int> p<7> l<3:4> el<3:7>
+n<> u<7> t<Data_type> p<11> c<6> s<10> l<3:4> el<3:7>
+n<start_addr> u<8> t<StringConst> p<9> l<3:8> el<3:18>
+n<> u<9> t<Variable_decl_assignment> p<10> c<8> l<3:8> el<3:18>
+n<> u<10> t<List_of_variable_decl_assignments> p<11> c<9> l<3:8> el<3:18>
+n<> u<11> t<Variable_declaration> p<12> c<7> l<3:4> el<3:19>
+n<> u<12> t<Data_declaration> p<13> c<11> l<3:4> el<3:19>
+n<> u<13> t<Package_or_generate_item_declaration> p<14> c<12> l<3:4> el<3:19>
+n<> u<14> t<Module_or_generate_item_declaration> p<15> c<13> l<3:4> el<3:19>
+n<> u<15> t<Module_common_item> p<16> c<14> l<3:4> el<3:19>
+n<> u<16> t<Interface_or_generate_item> p<17> c<15> l<3:4> el<3:19>
+n<> u<17> t<Non_port_interface_item> p<19> c<16> s<18> l<3:4> el<3:19>
+n<> u<18> t<Endinterface> p<19> l<4:1> el<4:13>
+n<> u<19> t<Interface_declaration> p<20> c<5> l<2:1> el<4:13>
+n<> u<20> t<Description> p<125> c<19> s<60> l<2:1> el<4:13>
+n<module> u<21> t<Module_keyword> p<39> s<22> l<6:1> el<6:7>
+n<dut> u<22> t<StringConst> p<39> s<38> l<6:8> el<6:11>
+n<sim_sram_if> u<23> t<StringConst> p<24> l<6:12> el<6:23>
+n<> u<24> t<Data_type> p<25> c<23> l<6:12> el<6:23>
+n<> u<25> t<Data_type_or_implicit> p<26> c<24> l<6:12> el<6:23>
+n<> u<26> t<Net_port_type> p<27> c<25> l<6:12> el<6:23>
+n<> u<27> t<Net_port_header> p<29> c<26> s<28> l<6:12> el<6:23>
+n<ss_if> u<28> t<StringConst> p<29> l<6:24> el<6:29>
+n<> u<29> t<Ansi_port_declaration> p<38> c<27> s<37> l<6:12> el<6:29>
+n<> u<30> t<PortDir_Out> p<35> s<34> l<6:31> el<6:37>
+n<> u<31> t<IntegerAtomType_Int> p<32> l<6:38> el<6:41>
+n<> u<32> t<Data_type> p<33> c<31> l<6:38> el<6:41>
+n<> u<33> t<Data_type_or_implicit> p<34> c<32> l<6:38> el<6:41>
+n<> u<34> t<Net_port_type> p<35> c<33> l<6:38> el<6:41>
+n<> u<35> t<Net_port_header> p<37> c<30> s<36> l<6:31> el<6:41>
+n<a> u<36> t<StringConst> p<37> l<6:42> el<6:43>
+n<> u<37> t<Ansi_port_declaration> p<38> c<35> l<6:31> el<6:43>
+n<> u<38> t<List_of_port_declarations> p<39> c<29> l<6:11> el<6:44>
+n<> u<39> t<Module_ansi_header> p<59> c<21> s<57> l<6:1> el<6:45>
+n<a> u<40> t<StringConst> p<41> l<7:11> el<7:12>
+n<> u<41> t<Ps_or_hierarchical_identifier> p<44> c<40> s<43> l<7:11> el<7:12>
+n<> u<42> t<Constant_bit_select> p<43> l<7:13> el<7:13>
+n<> u<43> t<Constant_select> p<44> c<42> l<7:13> el<7:13>
+n<> u<44> t<Net_lvalue> p<52> c<41> s<51> l<7:11> el<7:12>
+n<ss_if> u<45> t<StringConst> p<49> s<46> l<7:15> el<7:20>
+n<start_addr> u<46> t<StringConst> p<49> s<48> l<7:21> el<7:31>
+n<> u<47> t<Bit_select> p<48> l<7:31> el<7:31>
+n<> u<48> t<Select> p<49> c<47> l<7:31> el<7:31>
+n<> u<49> t<Complex_func_call> p<50> c<45> l<7:15> el<7:31>
+n<> u<50> t<Primary> p<51> c<49> l<7:15> el<7:31>
+n<> u<51> t<Expression> p<52> c<50> l<7:15> el<7:31>
+n<> u<52> t<Net_assignment> p<53> c<44> l<7:11> el<7:31>
+n<> u<53> t<List_of_net_assignments> p<54> c<52> l<7:11> el<7:31>
+n<> u<54> t<Continuous_assign> p<55> c<53> l<7:4> el<7:32>
+n<> u<55> t<Module_common_item> p<56> c<54> l<7:4> el<7:32>
+n<> u<56> t<Module_or_generate_item> p<57> c<55> l<7:4> el<7:32>
+n<> u<57> t<Non_port_module_item> p<59> c<56> s<58> l<7:4> el<7:32>
+n<> u<58> t<Endmodule> p<59> l<8:1> el<8:10>
+n<> u<59> t<Module_declaration> p<60> c<39> l<6:1> el<8:10>
+n<> u<60> t<Description> p<125> c<59> s<124> l<6:1> el<8:10>
+n<module> u<61> t<Module_keyword> p<72> s<62> l<10:1> el<10:7>
+n<top> u<62> t<StringConst> p<72> s<71> l<10:8> el<10:11>
+n<> u<63> t<PortDir_Out> p<68> s<67> l<10:12> el<10:18>
+n<> u<64> t<IntegerAtomType_Int> p<65> l<10:19> el<10:22>
+n<> u<65> t<Data_type> p<66> c<64> l<10:19> el<10:22>
+n<> u<66> t<Data_type_or_implicit> p<67> c<65> l<10:19> el<10:22>
+n<> u<67> t<Net_port_type> p<68> c<66> l<10:19> el<10:22>
+n<> u<68> t<Net_port_header> p<70> c<63> s<69> l<10:12> el<10:22>
+n<o> u<69> t<StringConst> p<70> l<10:23> el<10:24>
+n<> u<70> t<Ansi_port_declaration> p<71> c<68> l<10:12> el<10:24>
+n<> u<71> t<List_of_port_declarations> p<72> c<70> l<10:11> el<10:25>
+n<> u<72> t<Module_ansi_header> p<123> c<61> s<81> l<10:1> el<10:26>
+n<sim_sram_if> u<73> t<StringConst> p<79> s<78> l<11:4> el<11:15>
+n<u_sim_sram_if> u<74> t<StringConst> p<75> l<11:16> el<11:29>
+n<> u<75> t<Name_of_instance> p<78> c<74> s<77> l<11:16> el<11:29>
+n<> u<76> t<Ordered_port_connection> p<77> l<11:30> el<11:30>
+n<> u<77> t<List_of_port_connections> p<78> c<76> l<11:30> el<11:30>
+n<> u<78> t<Hierarchical_instance> p<79> c<75> l<11:16> el<11:31>
+n<> u<79> t<Module_instantiation> p<80> c<73> l<11:4> el<11:32>
+n<> u<80> t<Module_or_generate_item> p<81> c<79> l<11:4> el<11:32>
+n<> u<81> t<Non_port_module_item> p<123> c<80> s<97> l<11:4> el<11:32>
+n<u_sim_sram_if> u<82> t<StringConst> p<83> l<12:11> el<12:24>
+n<> u<83> t<Ps_or_hierarchical_identifier> p<87> c<82> s<86> l<12:11> el<12:24>
+n<start_addr> u<84> t<StringConst> p<86> s<85> l<12:25> el<12:35>
+n<> u<85> t<Constant_bit_select> p<86> l<12:36> el<12:36>
+n<> u<86> t<Constant_select> p<87> c<84> l<12:24> el<12:35>
+n<> u<87> t<Net_lvalue> p<92> c<83> s<91> l<12:11> el<12:35>
+n<32'h1234> u<88> t<IntConst> p<89> l<12:38> el<12:46>
+n<> u<89> t<Primary_literal> p<90> c<88> l<12:38> el<12:46>
+n<> u<90> t<Primary> p<91> c<89> l<12:38> el<12:46>
+n<> u<91> t<Expression> p<92> c<90> l<12:38> el<12:46>
+n<> u<92> t<Net_assignment> p<93> c<87> l<12:11> el<12:46>
+n<> u<93> t<List_of_net_assignments> p<94> c<92> l<12:11> el<12:46>
+n<> u<94> t<Continuous_assign> p<95> c<93> l<12:4> el<12:47>
+n<> u<95> t<Module_common_item> p<96> c<94> l<12:4> el<12:47>
+n<> u<96> t<Module_or_generate_item> p<97> c<95> l<12:4> el<12:47>
+n<> u<97> t<Non_port_module_item> p<123> c<96> s<121> l<12:4> el<12:47>
+n<dut> u<98> t<StringConst> p<119> s<118> l<13:4> el<13:7>
+n<u_dut> u<99> t<StringConst> p<100> l<13:8> el<13:13>
+n<> u<100> t<Name_of_instance> p<118> c<99> s<117> l<13:8> el<13:13>
+n<ss_if> u<101> t<StringConst> p<108> s<106> l<13:15> el<13:20>
+n<u_sim_sram_if> u<102> t<StringConst> p<103> l<13:21> el<13:34>
+n<> u<103> t<Primary_literal> p<104> c<102> l<13:21> el<13:34>
+n<> u<104> t<Primary> p<105> c<103> l<13:21> el<13:34>
+n<> u<105> t<Expression> p<108> c<104> s<107> l<13:21> el<13:34>
+n<> u<106> t<OpenParens> p<108> s<105> l<13:20> el<13:21>
+n<> u<107> t<CloseParens> p<108> l<13:34> el<13:35>
+n<> u<108> t<Named_port_connection> p<117> c<101> s<116> l<13:14> el<13:35>
+n<a> u<109> t<StringConst> p<116> s<114> l<13:38> el<13:39>
+n<o> u<110> t<StringConst> p<111> l<13:40> el<13:41>
+n<> u<111> t<Primary_literal> p<112> c<110> l<13:40> el<13:41>
+n<> u<112> t<Primary> p<113> c<111> l<13:40> el<13:41>
+n<> u<113> t<Expression> p<116> c<112> s<115> l<13:40> el<13:41>
+n<> u<114> t<OpenParens> p<116> s<113> l<13:39> el<13:40>
+n<> u<115> t<CloseParens> p<116> l<13:41> el<13:42>
+n<> u<116> t<Named_port_connection> p<117> c<109> l<13:37> el<13:42>
+n<> u<117> t<List_of_port_connections> p<118> c<108> l<13:14> el<13:42>
+n<> u<118> t<Hierarchical_instance> p<119> c<100> l<13:8> el<13:43>
+n<> u<119> t<Module_instantiation> p<120> c<98> l<13:4> el<13:44>
+n<> u<120> t<Module_or_generate_item> p<121> c<119> l<13:4> el<13:44>
+n<> u<121> t<Non_port_module_item> p<123> c<120> s<122> l<13:4> el<13:44>
+n<> u<122> t<Endmodule> p<123> l<14:1> el<14:10>
+n<> u<123> t<Module_declaration> p<124> c<72> l<10:1> el<14:10>
+n<> u<124> t<Description> p<125> c<123> l<10:1> el<14:10>
+n<> u<125> t<Source_text> p<126> c<20> l<2:1> el<14:10>
+n<> u<126> t<Top_level_rule> c<1> l<2:1> el<15:1>
+AST_DEBUG_END
+[WRN:PA0205] ${SURELOG_DIR}/tests/InterfInst/dut.sv:2:1: No timescale set for "sim_sram_if".
+
+[WRN:PA0205] ${SURELOG_DIR}/tests/InterfInst/dut.sv:6:1: No timescale set for "dut".
+
+[WRN:PA0205] ${SURELOG_DIR}/tests/InterfInst/dut.sv:10:1: No timescale set for "top".
+
+[INF:CP0300] Compilation...
+
+[INF:CP0303] ${SURELOG_DIR}/tests/InterfInst/dut.sv:6:1: Compile module "work@dut".
+
+[INF:CP0304] ${SURELOG_DIR}/tests/InterfInst/dut.sv:2:1: Compile interface "work@sim_sram_if".
+
+[INF:CP0303] ${SURELOG_DIR}/tests/InterfInst/dut.sv:10:1: Compile module "work@top".
+
+[INF:EL0526] Design Elaboration...
+
+[NTE:EL0503] ${SURELOG_DIR}/tests/InterfInst/dut.sv:10:1: Top level module "work@top".
+
+[NTE:EL0508] Nb Top level modules: 1.
+
+[NTE:EL0509] Max instance depth: 2.
+
+[NTE:EL0510] Nb instances: 2.
+
+[NTE:EL0511] Nb leaf instances: 1.
+
+[INF:UH0706] Creating UHDM Model...
+
+=== UHDM Object Stats Begin (Non-Elaborated Model) ===
+constant                                               2
+cont_assign                                            3
+design                                                 1
+hier_path                                              3
+int_typespec                                           8
+int_var                                                4
+interface_inst                                         4
+interface_typespec                                     3
+logic_net                                              4
+module_inst                                            6
+port                                                   8
+ref_module                                             2
+ref_obj                                               17
+=== UHDM Object Stats End ===
+[INF:UH0707] Elaborating UHDM...
+
+=== UHDM Object Stats Begin (Elaborated Model) ===
+constant                                               2
+cont_assign                                            5
+design                                                 1
+hier_path                                              5
+int_typespec                                           8
+int_var                                                4
+interface_inst                                         4
+interface_typespec                                     3
+logic_net                                              4
+module_inst                                            6
+port                                                  11
+ref_module                                             2
+ref_obj                                               27
+=== UHDM Object Stats End ===
+[ERR:UH0725] ${SURELOG_DIR}/tests/InterfInst/dut.sv:7:15: Unresolved hierarchical reference "ss_if.start_addr".
+
+[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/InterfInst/slpp_all/surelog.uhdm ...
+
+[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/InterfInst/slpp_all/checker/surelog.chk.html ...
+
+[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/InterfInst/slpp_all/surelog.uhdm ...
+
+[INF:UH0711] Decompiling UHDM...
+
+====== UHDM =======
+design: (work@top)
+|vpiElaborated:1
+|vpiName:work@top
+|uhdmallInterfaces:
+\_interface_inst: work@sim_sram_if (work@sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:2:1, endln:4:13
+  |vpiParent:
+  \_design: (work@top)
+  |vpiFullName:work@sim_sram_if
+  |vpiDefName:work@sim_sram_if
+  |vpiNet:
+  \_logic_net: (work@sim_sram_if.start_addr), line:3:8, endln:3:18
+    |vpiParent:
+    \_interface_inst: work@sim_sram_if (work@sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:2:1, endln:4:13
+    |vpiName:start_addr
+    |vpiFullName:work@sim_sram_if.start_addr
+|uhdmallModules:
+\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+  |vpiParent:
+  \_design: (work@top)
+  |vpiFullName:work@dut
+  |vpiDefName:work@dut
+  |vpiNet:
+  \_logic_net: (work@dut.a), line:6:42, endln:6:43
+    |vpiParent:
+    \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+    |vpiName:a
+    |vpiFullName:work@dut.a
+  |vpiNet:
+  \_logic_net: (work@dut.ss_if), line:6:24, endln:6:29
+    |vpiParent:
+    \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+    |vpiName:ss_if
+    |vpiFullName:work@dut.ss_if
+  |vpiPort:
+  \_port: (ss_if), line:6:24, endln:6:29
+    |vpiParent:
+    \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+    |vpiName:ss_if
+    |vpiDirection:3
+    |vpiLowConn:
+    \_ref_obj: 
+      |vpiActual:
+      \_interface_inst: work@sim_sram_if (work@sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:2:1, endln:4:13
+    |vpiTypedef:
+    \_interface_typespec: (sim_sram_if), line:6:12, endln:6:23
+      |vpiName:sim_sram_if
+  |vpiPort:
+  \_port: (a), line:6:42, endln:6:43
+    |vpiParent:
+    \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+    |vpiName:a
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: 
+      |vpiActual:
+      \_logic_net: (work@dut.a), line:6:42, endln:6:43
+    |vpiTypedef:
+    \_int_typespec: , line:6:38, endln:6:41
+      |vpiSigned:1
+  |vpiContAssign:
+  \_cont_assign: , line:7:11, endln:7:31
+    |vpiParent:
+    \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+    |vpiRhs:
+    \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31
+      |vpiParent:
+      \_cont_assign: , line:7:11, endln:7:31
+      |vpiName:ss_if.start_addr
+      |vpiActual:
+      \_ref_obj: (ss_if), line:7:15, endln:7:20
+        |vpiParent:
+        \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31
+        |vpiName:ss_if
+      |vpiActual:
+      \_ref_obj: (start_addr), line:7:21, endln:7:31
+        |vpiName:start_addr
+    |vpiLhs:
+    \_ref_obj: (work@dut.a), line:7:11, endln:7:12
+      |vpiParent:
+      \_cont_assign: , line:7:11, endln:7:31
+      |vpiName:a
+      |vpiFullName:work@dut.a
+      |vpiActual:
+      \_int_var: (work@top.u_dut.a), line:6:42, endln:6:43
+|uhdmallModules:
+\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+  |vpiParent:
+  \_design: (work@top)
+  |vpiFullName:work@top
+  |vpiDefName:work@top
+  |vpiNet:
+  \_logic_net: (work@top.o), line:10:23, endln:10:24
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:o
+    |vpiFullName:work@top.o
+  |vpiPort:
+  \_port: (o), line:10:23, endln:10:24
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:o
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: 
+      |vpiActual:
+      \_logic_net: (work@top.o), line:10:23, endln:10:24
+    |vpiTypedef:
+    \_int_typespec: , line:10:19, endln:10:22
+      |vpiSigned:1
+  |vpiContAssign:
+  \_cont_assign: , line:12:11, endln:12:46
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiRhs:
+    \_constant: , line:12:38, endln:12:46
+      |vpiParent:
+      \_cont_assign: , line:12:11, endln:12:46
+      |vpiDecompile:32'h1234
+      |vpiSize:32
+      |HEX:1234
+      |vpiConstType:5
+    |vpiLhs:
+    \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35
+      |vpiParent:
+      \_cont_assign: , line:12:11, endln:12:46
+      |vpiName:u_sim_sram_if.start_addr
+      |vpiActual:
+      \_ref_obj: (u_sim_sram_if)
+        |vpiParent:
+        \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35
+        |vpiName:u_sim_sram_if
+      |vpiActual:
+      \_ref_obj: (start_addr)
+        |vpiName:start_addr
+  |vpiRefModule:
+  \_ref_module: work@sim_sram_if (u_sim_sram_if), line:11:16, endln:11:29
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:u_sim_sram_if
+    |vpiDefName:work@sim_sram_if
+    |vpiActual:
+    \_interface_inst: work@sim_sram_if (work@sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:2:1, endln:4:13
+  |vpiRefModule:
+  \_ref_module: work@dut (u_dut), line:13:8, endln:13:13
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:u_dut
+    |vpiDefName:work@dut
+    |vpiActual:
+    \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:6:1, endln:8:10
+    |vpiPort:
+    \_port: (ss_if), line:13:14, endln:13:35
+      |vpiName:ss_if
+      |vpiHighConn:
+      \_ref_obj: (u_sim_sram_if), line:13:21, endln:13:34
+        |vpiName:u_sim_sram_if
+        |vpiActual:
+        \_interface_inst: work@sim_sram_if (work@top.u_sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:11:4, endln:11:32
+    |vpiPort:
+    \_port: (a), line:13:37, endln:13:42
+      |vpiName:a
+      |vpiHighConn:
+      \_ref_obj: (o), line:13:40, endln:13:41
+        |vpiName:o
+        |vpiActual:
+        \_int_var: (work@top.o), line:10:23, endln:10:24
+|uhdmtopModules:
+\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+  |vpiName:work@top
+  |vpiVariables:
+  \_int_var: (work@top.o), line:10:23, endln:10:24
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiTypespec:
+    \_int_typespec: , line:10:19, endln:10:22
+      |vpiSigned:1
+    |vpiName:o
+    |vpiFullName:work@top.o
+    |vpiSigned:1
+    |vpiVisibility:1
+  |vpiDefName:work@top
+  |vpiTop:1
+  |vpiTopModule:1
+  |vpiPort:
+  \_port: (o), line:10:23, endln:10:24
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:o
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@top.o), line:10:23, endln:10:24
+      |vpiParent:
+      \_port: (o), line:10:23, endln:10:24
+      |vpiName:o
+      |vpiFullName:work@top.o
+      |vpiActual:
+      \_int_var: (work@top.o), line:10:23, endln:10:24
+    |vpiTypedef:
+    \_int_typespec: , line:10:19, endln:10:22
+      |vpiSigned:1
+    |vpiInstance:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+  |vpiInterface:
+  \_interface_inst: work@sim_sram_if (work@top.u_sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:11:4, endln:11:32
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:u_sim_sram_if
+    |vpiFullName:work@top.u_sim_sram_if
+    |vpiVariables:
+    \_int_var: (work@top.u_sim_sram_if.start_addr), line:3:8, endln:3:18
+      |vpiParent:
+      \_interface_inst: work@sim_sram_if (work@top.u_sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:11:4, endln:11:32
+      |vpiTypespec:
+      \_int_typespec: , line:3:4, endln:3:7
+        |vpiSigned:1
+      |vpiName:start_addr
+      |vpiFullName:work@top.u_sim_sram_if.start_addr
+      |vpiVisibility:1
+    |vpiDefName:work@sim_sram_if
+    |vpiDefFile:${SURELOG_DIR}/tests/InterfInst/dut.sv
+    |vpiDefLineNo:2
+    |vpiInstance:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+  |vpiModule:
+  \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiName:u_dut
+    |vpiFullName:work@top.u_dut
+    |vpiVariables:
+    \_int_var: (work@top.u_dut.a), line:6:42, endln:6:43
+      |vpiParent:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+      |vpiTypespec:
+      \_int_typespec: , line:6:38, endln:6:41
+        |vpiSigned:1
+      |vpiName:a
+      |vpiFullName:work@top.u_dut.a
+      |vpiSigned:1
+      |vpiVisibility:1
+    |vpiDefName:work@dut
+    |vpiDefFile:${SURELOG_DIR}/tests/InterfInst/dut.sv
+    |vpiDefLineNo:6
+    |vpiInstance:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiPort:
+    \_port: (ss_if), line:6:24, endln:6:29
+      |vpiParent:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+      |vpiName:ss_if
+      |vpiDirection:3
+      |vpiHighConn:
+      \_ref_obj: (work@top.u_sim_sram_if), line:13:21, endln:13:34
+        |vpiParent:
+        \_port: (ss_if), line:6:24, endln:6:29
+        |vpiName:u_sim_sram_if
+        |vpiFullName:work@top.u_sim_sram_if
+        |vpiActual:
+        \_interface_inst: work@sim_sram_if (work@top.u_sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:11:4, endln:11:32
+      |vpiLowConn:
+      \_ref_obj: (work@top.u_dut.ss_if), line:13:15, endln:13:20
+        |vpiParent:
+        \_port: (ss_if), line:6:24, endln:6:29
+        |vpiFullName:work@top.u_dut.ss_if
+        |vpiActual:
+        \_interface_inst: work@sim_sram_if (work@top.u_dut.ss_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:0
+      |vpiTypedef:
+      \_interface_typespec: (sim_sram_if), line:6:12, endln:6:23
+        |vpiName:sim_sram_if
+      |vpiInstance:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+    |vpiPort:
+    \_port: (a), line:6:42, endln:6:43
+      |vpiParent:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+      |vpiName:a
+      |vpiDirection:2
+      |vpiHighConn:
+      \_ref_obj: (work@top.o), line:13:40, endln:13:41
+        |vpiParent:
+        \_port: (a), line:6:42, endln:6:43
+        |vpiName:o
+        |vpiFullName:work@top.o
+        |vpiActual:
+        \_int_var: (work@top.o), line:10:23, endln:10:24
+      |vpiLowConn:
+      \_ref_obj: (work@top.u_dut.a), line:13:38, endln:13:39
+        |vpiParent:
+        \_port: (a), line:6:42, endln:6:43
+        |vpiName:a
+        |vpiFullName:work@top.u_dut.a
+        |vpiActual:
+        \_int_var: (work@top.u_dut.a), line:6:42, endln:6:43
+      |vpiTypedef:
+      \_int_typespec: , line:6:38, endln:6:41
+        |vpiSigned:1
+      |vpiInstance:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+    |vpiInterface:
+    \_interface_inst: work@sim_sram_if (work@top.u_dut.ss_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:0
+      |vpiParent:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+      |vpiName:ss_if
+      |vpiFullName:work@top.u_dut.ss_if
+      |vpiDefName:work@sim_sram_if
+    |vpiInterface:
+    \_interface_inst: work@sim_sram_if (work@top.u_dut.ss_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:0
+    |vpiContAssign:
+    \_cont_assign: , line:7:11, endln:7:31
+      |vpiParent:
+      \_module_inst: work@dut (work@top.u_dut), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:4, endln:13:44
+      |vpiRhs:
+      \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31
+        |vpiParent:
+        \_cont_assign: , line:7:11, endln:7:31
+        |vpiName:ss_if.start_addr
+        |vpiActual:
+        \_ref_obj: (ss_if), line:7:15, endln:7:20
+          |vpiParent:
+          \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31
+          |vpiName:ss_if
+          |vpiActual:
+          \_interface_inst: work@sim_sram_if (work@top.u_dut.ss_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:13:0
+        |vpiActual:
+        \_ref_obj: (start_addr), line:7:21, endln:7:31
+          |vpiParent:
+          \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31
+          |vpiName:start_addr
+      |vpiLhs:
+      \_ref_obj: (work@top.u_dut.a), line:7:11, endln:7:12
+        |vpiParent:
+        \_cont_assign: , line:7:11, endln:7:31
+        |vpiName:a
+        |vpiFullName:work@top.u_dut.a
+        |vpiActual:
+        \_int_var: (work@top.u_dut.a), line:6:42, endln:6:43
+  |vpiContAssign:
+  \_cont_assign: , line:12:11, endln:12:46
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:10:1, endln:14:10
+    |vpiRhs:
+    \_constant: , line:12:38, endln:12:46
+    |vpiLhs:
+    \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35
+      |vpiParent:
+      \_cont_assign: , line:12:11, endln:12:46
+      |vpiName:u_sim_sram_if.start_addr
+      |vpiActual:
+      \_ref_obj: (u_sim_sram_if)
+        |vpiParent:
+        \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35
+        |vpiName:u_sim_sram_if
+        |vpiActual:
+        \_interface_inst: work@sim_sram_if (work@top.u_sim_sram_if), file:${SURELOG_DIR}/tests/InterfInst/dut.sv, line:11:4, endln:11:32
+      |vpiActual:
+      \_ref_obj: (start_addr)
+        |vpiParent:
+        \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35
+        |vpiName:start_addr
+        |vpiActual:
+        \_int_var: (work@top.u_sim_sram_if.start_addr), line:3:8, endln:3:18
+===================
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 1
+[WARNING] : 3
+[   NOTE] : 5
+
+
+[roundtrip]: ${SURELOG_DIR}/tests/InterfInst/dut.sv | ${SURELOG_DIR}/build/regression/InterfInst/roundtrip/dut_000.sv | 6 | 14 |
\ No newline at end of file
diff --git a/tests/InterfInst/InterfInst.sl b/tests/InterfInst/InterfInst.sl
new file mode 100644
index 0000000000..b461620aca
--- /dev/null
+++ b/tests/InterfInst/InterfInst.sl
@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
diff --git a/tests/InterfInst/dut.sv b/tests/InterfInst/dut.sv
new file mode 100644
index 0000000000..f601fb4f7b
--- /dev/null
+++ b/tests/InterfInst/dut.sv
@@ -0,0 +1,14 @@
+
+interface sim_sram_if;   
+   int start_addr;
+endinterface // sim_sram_if
+
+module dut(sim_sram_if ss_if, output int a);
+   assign a = ss_if.start_addr;
+endmodule // dut
+
+module top(output int o);
+   sim_sram_if u_sim_sram_if();
+   assign u_sim_sram_if.start_addr = 32'h1234;
+   dut u_dut(.ss_if(u_sim_sram_if), .a(o));
+endmodule // top
diff --git a/tests/InterfType/InterfType.log b/tests/InterfType/InterfType.log
index e3f816eeac..542c0b87e1 100644
--- a/tests/InterfType/InterfType.log
+++ b/tests/InterfType/InterfType.log
@@ -120,7 +120,7 @@ design                                                 1
 int_typespec                                           2
 interface_inst                                         7
 interface_typespec                                     2
-logic_net                                              2
+logic_net                                              1
 module_inst                                            6
 param_assign                                           2
 parameter                                              2
@@ -136,7 +136,7 @@ design                                                 1
 int_typespec                                           2
 interface_inst                                         7
 interface_typespec                                     2
-logic_net                                              2
+logic_net                                              1
 module_inst                                            6
 param_assign                                           2
 parameter                                              2
@@ -239,16 +239,12 @@ design: (work@dut)
       \_ref_obj: (i_types), line:16:20, endln:16:27
         |vpiName:i_types
         |vpiActual:
-        \_logic_net: (i_types)
+        \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26
 |uhdmtopModules:
 \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10
   |vpiName:work@dut
   |vpiDefName:work@dut
   |vpiTop:1
-  |vpiNet:
-  \_logic_net: (i_types)
-    |vpiName:i_types
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiInterface:
   \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26
diff --git a/tests/InterfaceElab/InterfaceElab.log b/tests/InterfaceElab/InterfaceElab.log
index 6a8a202c3b..03eddab379 100644
--- a/tests/InterfaceElab/InterfaceElab.log
+++ b/tests/InterfaceElab/InterfaceElab.log
@@ -196,7 +196,7 @@ int_typespec                                           2
 interface_inst                                         4
 interface_typespec                                     6
 io_decl                                                4
-logic_net                                              7
+logic_net                                              6
 logic_typespec                                         6
 logic_var                                              2
 modport                                                4
@@ -218,7 +218,7 @@ int_typespec                                           2
 interface_inst                                         4
 interface_typespec                                     6
 io_decl                                                4
-logic_net                                              7
+logic_net                                              6
 logic_typespec                                         6
 logic_var                                              2
 modport                                                4
@@ -373,7 +373,7 @@ design: (work@testharness)
       \_ref_obj: (reg_bus), line:27:34, endln:27:41
         |vpiName:reg_bus
         |vpiActual:
-        \_logic_net: (reg_bus)
+        \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23
 |uhdmallModules:
 \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10
   |vpiParent:
@@ -410,10 +410,6 @@ design: (work@testharness)
       |vpiName:clk_i
       |vpiFullName:work@testharness.i_peripherals.clk_i
       |vpiNetType:1
-    |vpiNet:
-    \_logic_net: (reg_bus)
-      |vpiName:reg_bus
-      |vpiNetType:1
     |vpiInstance:
     \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10
     |vpiInterface:
@@ -565,7 +561,7 @@ design: (work@testharness)
           |vpiName:reg_bus
           |vpiFullName:work@testharness.i_peripherals.reg_bus
           |vpiActual:
-          \_logic_net: (reg_bus)
+          \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23
         |vpiLowConn:
         \_ref_obj: (work@testharness.i_peripherals.i_apb_to_reg.reg_o), line:27:27, endln:27:32
           |vpiParent:
diff --git a/tests/InterfaceModPort/InterfaceModPort.log b/tests/InterfaceModPort/InterfaceModPort.log
index c8342e6f7f..ceb818af8d 100644
--- a/tests/InterfaceModPort/InterfaceModPort.log
+++ b/tests/InterfaceModPort/InterfaceModPort.log
@@ -1215,7 +1215,7 @@ int_var                                                4
 interface_inst                                         7
 interface_typespec                                    14
 io_decl                                              116
-logic_net                                             27
+logic_net                                             26
 logic_typespec                                        54
 logic_var                                             47
 modport                                               13
@@ -2136,7 +2136,7 @@ design: (work@interface_modports)
       \_ref_obj: (miff), line:120:20, endln:120:24
         |vpiName:miff
         |vpiActual:
-        \_logic_net: (miff)
+        \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
   |vpiRefModule:
   \_ref_module: work@memory_model (U_model), line:121:14, endln:121:21
     |vpiParent:
@@ -2151,7 +2151,7 @@ design: (work@interface_modports)
       \_ref_obj: (miff), line:121:22, endln:121:26
         |vpiName:miff
         |vpiActual:
-        \_logic_net: (miff)
+        \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
   |vpiRefModule:
   \_ref_module: work@test (U_test), line:122:8, endln:122:14
     |vpiParent:
@@ -2166,7 +2166,7 @@ design: (work@interface_modports)
       \_ref_obj: (miff), line:122:15, endln:122:19
         |vpiName:miff
         |vpiActual:
-        \_logic_net: (miff)
+        \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
 |uhdmallModules:
 \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10
   |vpiParent:
@@ -2544,10 +2544,6 @@ design: (work@interface_modports)
         \_interface_typespec: (mem_if), line:99:14, endln:99:20
         |vpiName:tb
         |vpiIsModPort:1
-  |vpiNet:
-  \_logic_net: (miff)
-    |vpiName:miff
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiInterface:
   \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
diff --git a/tests/ModPortParam/ModPortParam.log b/tests/ModPortParam/ModPortParam.log
index 33de4d8c1a..0f89e0ae76 100644
--- a/tests/ModPortParam/ModPortParam.log
+++ b/tests/ModPortParam/ModPortParam.log
@@ -107,7 +107,7 @@ design                                                 1
 interface_inst                                         4
 interface_typespec                                     6
 io_decl                                                4
-logic_net                                              2
+logic_net                                              1
 modport                                                4
 module_inst                                            5
 port                                                   3
@@ -121,7 +121,7 @@ design                                                 1
 interface_inst                                         4
 interface_typespec                                     6
 io_decl                                                4
-logic_net                                              2
+logic_net                                              1
 modport                                                4
 module_inst                                            5
 port                                                   4
@@ -211,16 +211,12 @@ design: (work@Core)
       \_ref_obj: (perfCounterIF), line:16:19, endln:16:32
         |vpiName:perfCounterIF
         |vpiActual:
-        \_logic_net: (perfCounterIF)
+        \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40
 |uhdmtopModules:
 \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10
   |vpiName:work@Core
   |vpiDefName:work@Core
   |vpiTop:1
-  |vpiNet:
-  \_logic_net: (perfCounterIF)
-    |vpiName:perfCounterIF
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiInterface:
   \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40
@@ -270,7 +266,7 @@ design: (work@Core)
         |vpiName:perfCounterIF
         |vpiFullName:work@Core.perfCounterIF
         |vpiActual:
-        \_logic_net: (perfCounterIF)
+        \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40
       |vpiLowConn:
       \_ref_obj: (work@Core.csrUnit.perfCounter), line:16:19, endln:16:32
         |vpiParent:
diff --git a/tests/OneNetInterf/OneNetInterf.log b/tests/OneNetInterf/OneNetInterf.log
index de6259f4c6..8986a29d6e 100644
--- a/tests/OneNetInterf/OneNetInterf.log
+++ b/tests/OneNetInterf/OneNetInterf.log
@@ -60,7 +60,7 @@ immediate_assert                                       2
 initial                                                1
 interface_inst                                         7
 interface_typespec                                     5
-logic_net                                             31
+logic_net                                             29
 logic_typespec                                        37
 module_inst                                           18
 operation                                              2
@@ -555,7 +555,7 @@ design: (work@dut)
       \_ref_obj: (conntb), line:4:18, endln:4:24
         |vpiName:conntb
         |vpiActual:
-        \_logic_net: (conntb)
+        \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41
 |uhdmallModules:
 \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10
   |vpiParent:
@@ -675,7 +675,7 @@ design: (work@dut)
       \_ref_obj: (conntb), line:17:15, endln:17:21
         |vpiName:conntb
         |vpiActual:
-        \_logic_net: (conntb)
+        \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41
   |vpiRefModule:
   \_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15
     |vpiParent:
@@ -735,10 +735,6 @@ design: (work@dut)
     |vpiName:o
     |vpiFullName:work@dut.o
     |vpiNetType:48
-  |vpiNet:
-  \_logic_net: (conntb)
-    |vpiName:conntb
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiPort:
   \_port: (i), line:2:24, endln:2:25
@@ -1070,10 +1066,6 @@ design: (work@dut)
     |vpiName:o
     |vpiFullName:work@tb.o
     |vpiNetType:1
-  |vpiNet:
-  \_logic_net: (conntb)
-    |vpiName:conntb
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiInterface:
   \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41
diff --git a/tests/OneNetModPort/OneNetModPort.log b/tests/OneNetModPort/OneNetModPort.log
index 21ca16fc77..c13b51fe1c 100644
--- a/tests/OneNetModPort/OneNetModPort.log
+++ b/tests/OneNetModPort/OneNetModPort.log
@@ -57,7 +57,7 @@ initial                                                1
 interface_inst                                         7
 interface_typespec                                     8
 io_decl                                               24
-logic_net                                             13
+logic_net                                             11
 logic_typespec                                        20
 logic_var                                              8
 modport                                               12
@@ -520,7 +520,7 @@ design: (work@TOP)
       \_ref_obj: (conntb), line:18:16, endln:18:22
         |vpiName:conntb
         |vpiActual:
-        \_logic_net: (conntb)
+        \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22
 |uhdmallModules:
 \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10
   |vpiParent:
@@ -637,7 +637,7 @@ design: (work@TOP)
       \_ref_obj: (conntb), line:6:18, endln:6:24
         |vpiName:conntb
         |vpiActual:
-        \_logic_net: (conntb)
+        \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22
 |uhdmallModules:
 \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10
   |vpiParent:
@@ -743,10 +743,6 @@ design: (work@TOP)
         \_interface_typespec: (ConnectTB), line:1:21, endln:1:30
         |vpiName:tb
         |vpiIsModPort:1
-  |vpiNet:
-  \_logic_net: (conntb)
-    |vpiName:conntb
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiInterface:
   \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22
@@ -842,10 +838,6 @@ design: (work@TOP)
       |vpiName:o
       |vpiFullName:work@TOP.dut1.o
       |vpiNetType:48
-    |vpiNet:
-    \_logic_net: (conntb)
-      |vpiName:conntb
-      |vpiNetType:1
     |vpiInstance:
     \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10
     |vpiPort:
diff --git a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log
index a43c27fc2c..a910dd2836 100644
--- a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log
+++ b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log
@@ -64,7 +64,7 @@ immediate_assert                                       2
 initial                                                1
 interface_inst                                         8
 io_decl                                               28
-logic_net                                             18
+logic_net                                             17
 logic_typespec                                        22
 logic_var                                             10
 modport                                               14
@@ -645,7 +645,7 @@ design: (work@TOP)
       \_ref_obj: (conntb), line:19:22, endln:19:28
         |vpiName:conntb
         |vpiActual:
-        \_logic_net: (conntb)
+        \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22
 |uhdmallModules:
 \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10
   |vpiParent:
@@ -882,10 +882,6 @@ design: (work@TOP)
       |vpiTypedef:
       \_unsupported_typespec: (intf), line:1:31, endln:1:35
         |vpiName:intf
-  |vpiNet:
-  \_logic_net: (conntb)
-    |vpiName:conntb
-    |vpiNetType:1
   |vpiTopModule:1
   |vpiInterface:
   \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22
diff --git a/tests/OneNetRange/OneNetRange.log b/tests/OneNetRange/OneNetRange.log
index dd4039cddb..50d882f183 100644
--- a/tests/OneNetRange/OneNetRange.log
+++ b/tests/OneNetRange/OneNetRange.log
@@ -57,7 +57,7 @@ initial                                                1
 int_typespec                                          12
 interface_inst                                         6
 interface_typespec                                     3
-logic_net                                             26
+logic_net                                             25
 logic_typespec                                        30
 module_inst                                           23
 operation                                             46
@@ -898,7 +898,7 @@ design: (work@TOP)
       \_ref_obj: (conntb), line:4:35, endln:4:41
         |vpiName:conntb
         |vpiActual:
-        \_logic_net: (conntb)
+        \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58
 |uhdmallModules:
 \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10
   |vpiParent:
@@ -1485,10 +1485,6 @@ design: (work@TOP)
       |vpiName:o
       |vpiFullName:work@TOP.dut1.o
       |vpiNetType:48
-    |vpiNet:
-    \_logic_net: (conntb)
-      |vpiName:conntb
-      |vpiNetType:1
     |vpiInstance:
     \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10
     |vpiPort:
diff --git a/tests/SimpleInterface/SimpleInterface.log b/tests/SimpleInterface/SimpleInterface.log
index b21c5e4952..f12b3de864 100644
--- a/tests/SimpleInterface/SimpleInterface.log
+++ b/tests/SimpleInterface/SimpleInterface.log
@@ -2217,7 +2217,7 @@ forever_stmt                                          11
 fork_stmt                                             31
 func_call                                           5081
 function                                            4692
-hier_path                                           8228
+hier_path                                           8249
 if_else                                              812
 if_stmt                                             4422
 include_file_info                                    166
@@ -2228,7 +2228,7 @@ int_var                                             1171
 interface_inst                                         5
 interface_typespec                                     3
 io_decl                                             6913
-logic_net                                            475
+logic_net                                            474
 logic_typespec                                       106
 logic_var                                             42
 long_int_typespec                                     99
@@ -2250,7 +2250,7 @@ range                                               3225
 real_typespec                                         33
 real_var                                               8
 ref_module                                             2
-ref_obj                                            44205
+ref_obj                                            44226
 ref_var                                             1788
 repeat                                                26
 return_stmt                                         3272
diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
index 9a4512a71d..3cd1bb3fb5 100644
--- a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
+++ b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
@@ -912,7 +912,7 @@ func_call                                          13654
 function                                            8542
 gen_scope                                              2
 gen_scope_array                                        2
-hier_path                                          20160
+hier_path                                          20349
 if_else                                             1972
 if_stmt                                            10918
 immediate_assert                                       9
@@ -925,7 +925,7 @@ int_var                                             2733
 interface_inst                                        14
 interface_typespec                                     3
 io_decl                                            13135
-logic_net                                            734
+logic_net                                            733
 logic_typespec                                       229
 logic_var                                             92
 long_int_typespec                                    179
@@ -947,7 +947,7 @@ range                                              13788
 real_typespec                                         41
 real_var                                               8
 ref_module                                             5
-ref_obj                                           109662
+ref_obj                                           109851
 ref_var                                             4624
 repeat                                                76
 return_stmt                                         6963
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index f7b440b33c..8dcd5b665d 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -3,7 +3,7 @@
 [WRN:CM0010] Command line argument "-Wno-UNOPTFLAT" ignored.
 
 Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 16
--- Configuring done (0.1s)
+-- Configuring done (0.0s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser
 [100%] Generating preprocessing
@@ -115,7 +115,7 @@ PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv
 [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv".
 
 Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16
--- Configuring done (0.1s)
+-- Configuring done (0.0s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
@@ -127,8 +127,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
-[ 62%] Generating 3_rvjtag_tap.sv
-[ 68%] Generating 4_dec_tlu_ctl.sv
+[ 62%] Generating 4_dec_tlu_ctl.sv
+[ 68%] Generating 3_rvjtag_tap.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
 [ 87%] Generating 7_axi4_to_ahb.sv
diff --git a/third_party/tests/Driver/Driver.log b/third_party/tests/Driver/Driver.log
index 01a1bd0ac4..7d618ff246 100644
--- a/third_party/tests/Driver/Driver.log
+++ b/third_party/tests/Driver/Driver.log
@@ -834,7 +834,7 @@ forever_stmt                                          12
 fork_stmt                                             35
 func_call                                           5086
 function                                            4766
-hier_path                                           8142
+hier_path                                           8163
 if_else                                              824
 if_stmt                                             4452
 include_file_info                                    175
@@ -868,7 +868,7 @@ range                                               3066
 real_typespec                                         33
 real_var                                               8
 ref_module                                             1
-ref_obj                                            44351
+ref_obj                                            44372
 ref_var                                             1795
 repeat                                                30
 return_stmt                                         3301
diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log
index 1ea4fbabb8..0ddf483e02 100644
--- a/third_party/tests/Ibex/Ibex.log
+++ b/third_party/tests/Ibex/Ibex.log
@@ -1607,7 +1607,7 @@ func_call                                          30003
 function                                           15514
 gen_scope                                            328
 gen_scope_array                                      328
-hier_path                                          43056
+hier_path                                          43077
 if_else                                             4404
 if_stmt                                            23958
 immediate_assert                                       5
@@ -1643,7 +1643,7 @@ range                                              62338
 real_typespec                                         58
 real_var                                               9
 ref_module                                            31
-ref_obj                                           251121
+ref_obj                                           251142
 ref_var                                             9759
 repeat                                               158
 return_stmt                                        14240
diff --git a/third_party/tests/Monitor/Monitor.log b/third_party/tests/Monitor/Monitor.log
index 4cd1087d9b..a6040e61ed 100644
--- a/third_party/tests/Monitor/Monitor.log
+++ b/third_party/tests/Monitor/Monitor.log
@@ -902,7 +902,7 @@ forever_stmt                                          18
 fork_stmt                                             69
 func_call                                           9554
 function                                            6840
-hier_path                                          14014
+hier_path                                          14035
 if_else                                             1428
 if_stmt                                             7721
 immediate_assert                                       9
@@ -938,7 +938,7 @@ range                                               7715
 real_typespec                                         37
 real_var                                               8
 ref_module                                             1
-ref_obj                                            77506
+ref_obj                                            77527
 ref_var                                             3307
 repeat                                                50
 return_stmt                                         5220
diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log
index 0c603500f7..3cbad0e25a 100644
--- a/third_party/tests/NyuziProcessor/NyuziProcessor.log
+++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log
@@ -1760,7 +1760,7 @@ interface_array                                        4
 interface_inst                                        48
 interface_typespec                                   118
 io_decl                                              831
-logic_net                                           3878
+logic_net                                           3873
 logic_typespec                                     19346
 logic_var                                           2684
 modport                                               77
@@ -1835,7 +1835,7 @@ interface_array                                        4
 interface_inst                                        48
 interface_typespec                                   118
 io_decl                                              845
-logic_net                                           3878
+logic_net                                           3873
 logic_typespec                                     19346
 logic_var                                           6026
 modport                                               77
@@ -1864,57 +1864,13 @@ task_call                                             22
 typespec_member                                     7574
 var_select                                           953
 === UHDM Object Stats End ===
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:299:17: Unresolved hierarchical reference "nyuzi_io_bus.write_en".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:301:23: Unresolved hierarchical reference "nyuzi_io_bus.address".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:305:38: Unresolved hierarchical reference "nyuzi_io_bus.write_data[7:0]".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:310:49: Unresolved hierarchical reference "nyuzi_io_bus.write_data[0]".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:313:51: Unresolved hierarchical reference "nyuzi_io_bus.write_data".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:317:17: Unresolved hierarchical reference "nyuzi_io_bus.read_en".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:319:24: Unresolved hierarchical reference "nyuzi_io_bus.address[15:0]".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:262:57: Unresolved hierarchical reference "nyuzi_io_bus.write_en".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:263:56: Unresolved hierarchical reference "nyuzi_io_bus.read_en".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:264:56: Unresolved hierarchical reference "nyuzi_io_bus.address".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:265:59: Unresolved hierarchical reference "nyuzi_io_bus.write_data".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:222:12: Unresolved hierarchical reference "host_jtag.tdi".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:222:28: Unresolved hierarchical reference "target_jtag.tdo".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:223:12: Unresolved hierarchical reference "target_jtag.tdi".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:223:30: Unresolved hierarchical reference "host_jtag.tdo".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:224:12: Unresolved hierarchical reference "target_jtag.tck".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:224:30: Unresolved hierarchical reference "host_jtag.tck".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:225:12: Unresolved hierarchical reference "target_jtag.trst_n".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:225:33: Unresolved hierarchical reference "host_jtag.trst_n".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:226:12: Unresolved hierarchical reference "target_jtag.tms".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:226:30: Unresolved hierarchical reference "host_jtag.tms".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:256:12: Unresolved hierarchical reference "nyuzi_io_bus.read_data".
-
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/NyuziProcessor/slpp_unit/surelog.uhdm ...
 
 [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/NyuziProcessor/slpp_unit/checker/surelog.chk.html ...
 
 [  FATAL] : 0
 [ SYNTAX] : 0
-[  ERROR] : 70
+[  ERROR] : 48
 [WARNING] : 0
 [   NOTE] : 12
 
diff --git a/third_party/tests/OVMSwitch/OVMSwitch.log b/third_party/tests/OVMSwitch/OVMSwitch.log
index 29840f26da..0319106b63 100644
--- a/third_party/tests/OVMSwitch/OVMSwitch.log
+++ b/third_party/tests/OVMSwitch/OVMSwitch.log
@@ -773,7 +773,7 @@ integer_var                                           75
 interface_inst                                        17
 interface_typespec                                     6
 io_decl                                             3594
-logic_net                                            483
+logic_net                                            481
 logic_typespec                                       255
 logic_var                                             39
 method_func_call                                    3512
diff --git a/third_party/tests/Rp32/rp32.log b/third_party/tests/Rp32/rp32.log
index 629628a13d..c196fa61fe 100644
--- a/third_party/tests/Rp32/rp32.log
+++ b/third_party/tests/Rp32/rp32.log
@@ -431,7 +431,7 @@ interface_array                                        2
 interface_inst                                        13
 interface_typespec                                    21
 io_decl                                              235
-logic_net                                            418
+logic_net                                            417
 logic_typespec                                      1102
 logic_var                                            203
 modport                                               22
@@ -499,7 +499,7 @@ interface_array                                        2
 interface_inst                                        13
 interface_typespec                                    21
 io_decl                                              428
-logic_net                                            418
+logic_net                                            417
 logic_typespec                                      1102
 logic_var                                            207
 modport                                               22
@@ -529,26 +529,12 @@ typespec_member                                     6883
 union_typespec                                         6
 union_var                                              1
 === UHDM Object Stats End ===
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:110:13: Unresolved hierarchical reference "bus_ls.vld".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:111:13: Unresolved hierarchical reference "bus_ls.wen".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:112:13: Unresolved hierarchical reference "bus_ls.adr".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:113:13: Unresolved hierarchical reference "bus_ls.ben".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:114:13: Unresolved hierarchical reference "bus_ls.wdt".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:115:13: Unresolved hierarchical reference "bus_ls.rdt".
-
-[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:116:13: Unresolved hierarchical reference "bus_ls.rdy".
-
 [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/rp32/slpp_all/surelog.uhdm ...
 
 [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/rp32/slpp_all/checker/surelog.chk.html ...
 
 [  FATAL] : 0
 [ SYNTAX] : 0
-[  ERROR] : 7
+[  ERROR] : 0
 [WARNING] : 20
 [   NOTE] : 76
diff --git a/third_party/tests/Tnoc/Tnoc.log b/third_party/tests/Tnoc/Tnoc.log
index 9455c36fec..b1b77c7a0c 100644
--- a/third_party/tests/Tnoc/Tnoc.log
+++ b/third_party/tests/Tnoc/Tnoc.log
@@ -24159,7 +24159,7 @@ interface_array                                      989
 interface_inst                                     24779
 interface_typespec                                 40659
 io_decl                                            97940
-logic_net                                           9528
+logic_net                                           9519
 logic_typespec                                     71267
 logic_var                                          49617
 method_func_call                                    2197
diff --git a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log
index 62a084399a..9a574abc3e 100644
--- a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log
+++ b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log
@@ -910,7 +910,7 @@ int_var                                             4059
 interface_inst                                         4
 interface_typespec                                     7
 io_decl                                            18988
-logic_net                                            353
+logic_net                                            352
 logic_typespec                                       334
 logic_var                                            116
 long_int_typespec                                    259
diff --git a/third_party/tests/UVMSwitch/UVMSwitch.log b/third_party/tests/UVMSwitch/UVMSwitch.log
index 74bcd01ea6..23e0e51d8f 100644
--- a/third_party/tests/UVMSwitch/UVMSwitch.log
+++ b/third_party/tests/UVMSwitch/UVMSwitch.log
@@ -6970,7 +6970,7 @@ integer_var                                            9
 interface_inst                                        17
 interface_typespec                                     6
 io_decl                                             6968
-logic_net                                            564
+logic_net                                            562
 logic_typespec                                       250
 logic_var                                             44
 long_int_typespec                                     99
diff --git a/third_party/tests/YosysVerx/YosysVerx.sl b/third_party/tests/YosysVerx/YosysVerx.sl
index 646c5ffdc5..feb3b98089 100644
--- a/third_party/tests/YosysVerx/YosysVerx.sl
+++ b/third_party/tests/YosysVerx/YosysVerx.sl
@@ -1 +1 @@
- +incdir+.+../../../UVM/uvm-1.2/src/        -writepp -parse   -mt max  -nopython -fileunit *.v
+ +incdir+.+../../../UVM/uvm-1.2/src/        -writepp -parse   -mt max  -nopython -fileunit vexriscv.demo.GenFull.v