From ec4f3c4ca4f68b955179a6873d195011c892b1eb Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Sun, 23 Apr 2023 11:13:07 -0700 Subject: [PATCH 1/2] interface binding --- .vscode/launch.json | 19 +++++++ src/DesignCompile/UhdmWriter.cpp | 50 +++++++++++-------- tests/InterfType/InterfType.log | 10 ++-- tests/InterfaceElab/InterfaceElab.log | 12 ++--- tests/InterfaceModPort/InterfaceModPort.log | 12 ++--- tests/ModPortParam/ModPortParam.log | 12 ++--- tests/OneNetInterf/OneNetInterf.log | 14 ++---- tests/OneNetModPort/OneNetModPort.log | 14 ++---- .../OneNetModPortGeneric.log | 8 +-- tests/OneNetRange/OneNetRange.log | 8 +-- tests/SimpleInterface/SimpleInterface.log | 6 +-- .../AmiqSimpleTestSuite.log | 6 +-- .../tests/CoresSweRVMP/CoresSweRVMP.log | 8 +-- third_party/tests/Driver/Driver.log | 4 +- third_party/tests/Ibex/Ibex.log | 4 +- third_party/tests/Monitor/Monitor.log | 4 +- .../tests/NyuziProcessor/NyuziProcessor.log | 50 ++----------------- third_party/tests/OVMSwitch/OVMSwitch.log | 2 +- third_party/tests/Rp32/rp32.log | 20 ++------ third_party/tests/Tnoc/Tnoc.log | 2 +- .../tests/UVMNestedSeq/UVMNestedSeq.log | 2 +- third_party/tests/UVMSwitch/UVMSwitch.log | 2 +- third_party/tests/YosysVerx/YosysVerx.sl | 2 +- 23 files changed, 101 insertions(+), 170 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index 6c1b221017..4ed69db88d 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -1857,6 +1857,25 @@ "ignoreFailures": true } ] + }, + { + "name": "YosysVerx", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/dbuild/bin/surelog", + "args": ["-f", "YosysVerx.sl"], + "stopAtEntry": false, + "cwd": "${workspaceFolder}/third_party/tests/YosysVerx", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] } ] } \ No newline at end of file diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index 0c68a5bb19..bf597195c6 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -1932,11 +1932,6 @@ bool UhdmWriter::writeElabGenScope(Serializer& s, ModuleInstance* instance, } } - if (mod) { - lateTypedefBinding(s, mod, m, componentMap); - lateBinding(s, mod, m, componentMap); - } - return true; } @@ -2893,7 +2888,27 @@ void UhdmWriter::lateBinding(UHDM::Serializer& s, DesignComponent* mod, parent = parent->VpiParent(); } if (ref->Actual_group()) continue; - + if (m->UhdmType() == uhdmmodule_inst) { + module_inst* minst = (module_inst*)m; + if (minst->Interfaces()) { + for (auto n : *minst->Interfaces()) { + if (n->VpiName() == name) { + ref->Actual_group(n); + break; + } + } + if (ref->Actual_group()) continue; + } + if (minst->Interface_arrays()) { + for (auto n : *minst->Interface_arrays()) { + if (n->VpiName() == name) { + ref->Actual_group(n); + break; + } + } + if (ref->Actual_group()) continue; + } + } if (m->UhdmType() == uhdmmodule_inst || m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram) { instance* inst = (instance*)m; @@ -3200,13 +3215,6 @@ bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance, } } } - - if (mod) { - lateTypedefBinding(s, mod, m, componentMap); - lateBinding(s, mod, m, componentMap); - lateTypedefBinding(s, mod, m, componentMap); - } - return true; } @@ -3379,12 +3387,6 @@ bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance, } } } - - if (mod) { - lateTypedefBinding(s, mod, m, componentMap); - lateBinding(s, mod, m, componentMap); - } - return true; } @@ -3452,7 +3454,6 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, VectorOfprimitive* subPrimitives = nullptr; VectorOfprimitive_array* subPrimitiveArrays = nullptr; VectorOfgen_scope_array* subGenScopeArrays = nullptr; - if (m->UhdmType() == uhdmmodule_inst) { writeElabModule(s, instance, (module_inst*)m, exprBuilder); } else if (m->UhdmType() == uhdmgen_scope) { @@ -3796,6 +3797,15 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, } } } + + if (mod && netlist) { + scope* sc = dynamic_cast(m); + if (sc) { + lateTypedefBinding(s, mod, sc, componentMap); + lateBinding(s, mod, sc, componentMap); + lateTypedefBinding(s, mod, sc, componentMap); + } + } } vpiHandle UhdmWriter::write(PathId uhdmFileId) { diff --git a/tests/InterfType/InterfType.log b/tests/InterfType/InterfType.log index e3f816eeac..542c0b87e1 100644 --- a/tests/InterfType/InterfType.log +++ b/tests/InterfType/InterfType.log @@ -120,7 +120,7 @@ design 1 int_typespec 2 interface_inst 7 interface_typespec 2 -logic_net 2 +logic_net 1 module_inst 6 param_assign 2 parameter 2 @@ -136,7 +136,7 @@ design 1 int_typespec 2 interface_inst 7 interface_typespec 2 -logic_net 2 +logic_net 1 module_inst 6 param_assign 2 parameter 2 @@ -239,16 +239,12 @@ design: (work@dut) \_ref_obj: (i_types), line:16:20, endln:16:27 |vpiName:i_types |vpiActual: - \_logic_net: (i_types) + \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 |uhdmtopModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10 |vpiName:work@dut |vpiDefName:work@dut |vpiTop:1 - |vpiNet: - \_logic_net: (i_types) - |vpiName:i_types - |vpiNetType:1 |vpiTopModule:1 |vpiInterface: \_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26 diff --git a/tests/InterfaceElab/InterfaceElab.log b/tests/InterfaceElab/InterfaceElab.log index 6a8a202c3b..03eddab379 100644 --- a/tests/InterfaceElab/InterfaceElab.log +++ b/tests/InterfaceElab/InterfaceElab.log @@ -196,7 +196,7 @@ int_typespec 2 interface_inst 4 interface_typespec 6 io_decl 4 -logic_net 7 +logic_net 6 logic_typespec 6 logic_var 2 modport 4 @@ -218,7 +218,7 @@ int_typespec 2 interface_inst 4 interface_typespec 6 io_decl 4 -logic_net 7 +logic_net 6 logic_typespec 6 logic_var 2 modport 4 @@ -373,7 +373,7 @@ design: (work@testharness) \_ref_obj: (reg_bus), line:27:34, endln:27:41 |vpiName:reg_bus |vpiActual: - \_logic_net: (reg_bus) + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |uhdmallModules: \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 |vpiParent: @@ -410,10 +410,6 @@ design: (work@testharness) |vpiName:clk_i |vpiFullName:work@testharness.i_peripherals.clk_i |vpiNetType:1 - |vpiNet: - \_logic_net: (reg_bus) - |vpiName:reg_bus - |vpiNetType:1 |vpiInstance: \_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10 |vpiInterface: @@ -565,7 +561,7 @@ design: (work@testharness) |vpiName:reg_bus |vpiFullName:work@testharness.i_peripherals.reg_bus |vpiActual: - \_logic_net: (reg_bus) + \_interface_inst: work@REG_BUS (work@testharness.i_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23 |vpiLowConn: \_ref_obj: (work@testharness.i_peripherals.i_apb_to_reg.reg_o), line:27:27, endln:27:32 |vpiParent: diff --git a/tests/InterfaceModPort/InterfaceModPort.log b/tests/InterfaceModPort/InterfaceModPort.log index c8342e6f7f..ceb818af8d 100644 --- a/tests/InterfaceModPort/InterfaceModPort.log +++ b/tests/InterfaceModPort/InterfaceModPort.log @@ -1215,7 +1215,7 @@ int_var 4 interface_inst 7 interface_typespec 14 io_decl 116 -logic_net 27 +logic_net 26 logic_typespec 54 logic_var 47 modport 13 @@ -2136,7 +2136,7 @@ design: (work@interface_modports) \_ref_obj: (miff), line:120:20, endln:120:24 |vpiName:miff |vpiActual: - \_logic_net: (miff) + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiRefModule: \_ref_module: work@memory_model (U_model), line:121:14, endln:121:21 |vpiParent: @@ -2151,7 +2151,7 @@ design: (work@interface_modports) \_ref_obj: (miff), line:121:22, endln:121:26 |vpiName:miff |vpiActual: - \_logic_net: (miff) + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |vpiRefModule: \_ref_module: work@test (U_test), line:122:8, endln:122:14 |vpiParent: @@ -2166,7 +2166,7 @@ design: (work@interface_modports) \_ref_obj: (miff), line:122:15, endln:122:19 |vpiName:miff |vpiActual: - \_logic_net: (miff) + \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 |uhdmallModules: \_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10 |vpiParent: @@ -2544,10 +2544,6 @@ design: (work@interface_modports) \_interface_typespec: (mem_if), line:99:14, endln:99:20 |vpiName:tb |vpiIsModPort:1 - |vpiNet: - \_logic_net: (miff) - |vpiName:miff - |vpiNetType:1 |vpiTopModule:1 |vpiInterface: \_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18 diff --git a/tests/ModPortParam/ModPortParam.log b/tests/ModPortParam/ModPortParam.log index 33de4d8c1a..0f89e0ae76 100644 --- a/tests/ModPortParam/ModPortParam.log +++ b/tests/ModPortParam/ModPortParam.log @@ -107,7 +107,7 @@ design 1 interface_inst 4 interface_typespec 6 io_decl 4 -logic_net 2 +logic_net 1 modport 4 module_inst 5 port 3 @@ -121,7 +121,7 @@ design 1 interface_inst 4 interface_typespec 6 io_decl 4 -logic_net 2 +logic_net 1 modport 4 module_inst 5 port 4 @@ -211,16 +211,12 @@ design: (work@Core) \_ref_obj: (perfCounterIF), line:16:19, endln:16:32 |vpiName:perfCounterIF |vpiActual: - \_logic_net: (perfCounterIF) + \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 |uhdmtopModules: \_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10 |vpiName:work@Core |vpiDefName:work@Core |vpiTop:1 - |vpiNet: - \_logic_net: (perfCounterIF) - |vpiName:perfCounterIF - |vpiNetType:1 |vpiTopModule:1 |vpiInterface: \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 @@ -270,7 +266,7 @@ design: (work@Core) |vpiName:perfCounterIF |vpiFullName:work@Core.perfCounterIF |vpiActual: - \_logic_net: (perfCounterIF) + \_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40 |vpiLowConn: \_ref_obj: (work@Core.csrUnit.perfCounter), line:16:19, endln:16:32 |vpiParent: diff --git a/tests/OneNetInterf/OneNetInterf.log b/tests/OneNetInterf/OneNetInterf.log index de6259f4c6..8986a29d6e 100644 --- a/tests/OneNetInterf/OneNetInterf.log +++ b/tests/OneNetInterf/OneNetInterf.log @@ -60,7 +60,7 @@ immediate_assert 2 initial 1 interface_inst 7 interface_typespec 5 -logic_net 31 +logic_net 29 logic_typespec 37 module_inst 18 operation 2 @@ -555,7 +555,7 @@ design: (work@dut) \_ref_obj: (conntb), line:4:18, endln:4:24 |vpiName:conntb |vpiActual: - \_logic_net: (conntb) + \_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41 |uhdmallModules: \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10 |vpiParent: @@ -675,7 +675,7 @@ design: (work@dut) \_ref_obj: (conntb), line:17:15, endln:17:21 |vpiName:conntb |vpiActual: - \_logic_net: (conntb) + \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15 |vpiParent: @@ -735,10 +735,6 @@ design: (work@dut) |vpiName:o |vpiFullName:work@dut.o |vpiNetType:48 - |vpiNet: - \_logic_net: (conntb) - |vpiName:conntb - |vpiNetType:1 |vpiTopModule:1 |vpiPort: \_port: (i), line:2:24, endln:2:25 @@ -1070,10 +1066,6 @@ design: (work@dut) |vpiName:o |vpiFullName:work@tb.o |vpiNetType:1 - |vpiNet: - \_logic_net: (conntb) - |vpiName:conntb - |vpiNetType:1 |vpiTopModule:1 |vpiInterface: \_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41 diff --git a/tests/OneNetModPort/OneNetModPort.log b/tests/OneNetModPort/OneNetModPort.log index 21ca16fc77..c13b51fe1c 100644 --- a/tests/OneNetModPort/OneNetModPort.log +++ b/tests/OneNetModPort/OneNetModPort.log @@ -57,7 +57,7 @@ initial 1 interface_inst 7 interface_typespec 8 io_decl 24 -logic_net 13 +logic_net 11 logic_typespec 20 logic_var 8 modport 12 @@ -520,7 +520,7 @@ design: (work@TOP) \_ref_obj: (conntb), line:18:16, endln:18:22 |vpiName:conntb |vpiActual: - \_logic_net: (conntb) + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 |uhdmallModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10 |vpiParent: @@ -637,7 +637,7 @@ design: (work@TOP) \_ref_obj: (conntb), line:6:18, endln:6:24 |vpiName:conntb |vpiActual: - \_logic_net: (conntb) + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22 |uhdmallModules: \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10 |vpiParent: @@ -743,10 +743,6 @@ design: (work@TOP) \_interface_typespec: (ConnectTB), line:1:21, endln:1:30 |vpiName:tb |vpiIsModPort:1 - |vpiNet: - \_logic_net: (conntb) - |vpiName:conntb - |vpiNetType:1 |vpiTopModule:1 |vpiInterface: \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22 @@ -842,10 +838,6 @@ design: (work@TOP) |vpiName:o |vpiFullName:work@TOP.dut1.o |vpiNetType:48 - |vpiNet: - \_logic_net: (conntb) - |vpiName:conntb - |vpiNetType:1 |vpiInstance: \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiPort: diff --git a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log index a43c27fc2c..a910dd2836 100644 --- a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log +++ b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log @@ -64,7 +64,7 @@ immediate_assert 2 initial 1 interface_inst 8 io_decl 28 -logic_net 18 +logic_net 17 logic_typespec 22 logic_var 10 modport 14 @@ -645,7 +645,7 @@ design: (work@TOP) \_ref_obj: (conntb), line:19:22, endln:19:28 |vpiName:conntb |vpiActual: - \_logic_net: (conntb) + \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 |uhdmallModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:2:1, endln:7:10 |vpiParent: @@ -882,10 +882,6 @@ design: (work@TOP) |vpiTypedef: \_unsupported_typespec: (intf), line:1:31, endln:1:35 |vpiName:intf - |vpiNet: - \_logic_net: (conntb) - |vpiName:conntb - |vpiNetType:1 |vpiTopModule:1 |vpiInterface: \_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:16:3, endln:16:22 diff --git a/tests/OneNetRange/OneNetRange.log b/tests/OneNetRange/OneNetRange.log index dd4039cddb..50d882f183 100644 --- a/tests/OneNetRange/OneNetRange.log +++ b/tests/OneNetRange/OneNetRange.log @@ -57,7 +57,7 @@ initial 1 int_typespec 12 interface_inst 6 interface_typespec 3 -logic_net 26 +logic_net 25 logic_typespec 30 module_inst 23 operation 46 @@ -898,7 +898,7 @@ design: (work@TOP) \_ref_obj: (conntb), line:4:35, endln:4:41 |vpiName:conntb |vpiActual: - \_logic_net: (conntb) + \_interface_inst: work@ConnectTB (work@TOP.dut1.conntb), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:3:3, endln:3:58 |uhdmallModules: \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:11:1, endln:13:10 |vpiParent: @@ -1485,10 +1485,6 @@ design: (work@TOP) |vpiName:o |vpiFullName:work@TOP.dut1.o |vpiNetType:48 - |vpiNet: - \_logic_net: (conntb) - |vpiName:conntb - |vpiNetType:1 |vpiInstance: \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiPort: diff --git a/tests/SimpleInterface/SimpleInterface.log b/tests/SimpleInterface/SimpleInterface.log index b21c5e4952..f12b3de864 100644 --- a/tests/SimpleInterface/SimpleInterface.log +++ b/tests/SimpleInterface/SimpleInterface.log @@ -2217,7 +2217,7 @@ forever_stmt 11 fork_stmt 31 func_call 5081 function 4692 -hier_path 8228 +hier_path 8249 if_else 812 if_stmt 4422 include_file_info 166 @@ -2228,7 +2228,7 @@ int_var 1171 interface_inst 5 interface_typespec 3 io_decl 6913 -logic_net 475 +logic_net 474 logic_typespec 106 logic_var 42 long_int_typespec 99 @@ -2250,7 +2250,7 @@ range 3225 real_typespec 33 real_var 8 ref_module 2 -ref_obj 44205 +ref_obj 44226 ref_var 1788 repeat 26 return_stmt 3272 diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log index 9a4512a71d..3cd1bb3fb5 100644 --- a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log +++ b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log @@ -912,7 +912,7 @@ func_call 13654 function 8542 gen_scope 2 gen_scope_array 2 -hier_path 20160 +hier_path 20349 if_else 1972 if_stmt 10918 immediate_assert 9 @@ -925,7 +925,7 @@ int_var 2733 interface_inst 14 interface_typespec 3 io_decl 13135 -logic_net 734 +logic_net 733 logic_typespec 229 logic_var 92 long_int_typespec 179 @@ -947,7 +947,7 @@ range 13788 real_typespec 41 real_var 8 ref_module 5 -ref_obj 109662 +ref_obj 109851 ref_var 4624 repeat 76 return_stmt 6963 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index f7b440b33c..8dcd5b665d 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -3,7 +3,7 @@ [WRN:CM0010] Command line argument "-Wno-UNOPTFLAT" ignored. Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 16 --- Configuring done (0.1s) +-- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser [100%] Generating preprocessing @@ -115,7 +115,7 @@ PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv". Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16 --- Configuring done (0.1s) +-- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess [ 6%] Generating 10_lsu_bus_intf.sv @@ -127,8 +127,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; [ 43%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv -[ 62%] Generating 3_rvjtag_tap.sv -[ 68%] Generating 4_dec_tlu_ctl.sv +[ 62%] Generating 4_dec_tlu_ctl.sv +[ 68%] Generating 3_rvjtag_tap.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv diff --git a/third_party/tests/Driver/Driver.log b/third_party/tests/Driver/Driver.log index 01a1bd0ac4..7d618ff246 100644 --- a/third_party/tests/Driver/Driver.log +++ b/third_party/tests/Driver/Driver.log @@ -834,7 +834,7 @@ forever_stmt 12 fork_stmt 35 func_call 5086 function 4766 -hier_path 8142 +hier_path 8163 if_else 824 if_stmt 4452 include_file_info 175 @@ -868,7 +868,7 @@ range 3066 real_typespec 33 real_var 8 ref_module 1 -ref_obj 44351 +ref_obj 44372 ref_var 1795 repeat 30 return_stmt 3301 diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log index 1ea4fbabb8..0ddf483e02 100644 --- a/third_party/tests/Ibex/Ibex.log +++ b/third_party/tests/Ibex/Ibex.log @@ -1607,7 +1607,7 @@ func_call 30003 function 15514 gen_scope 328 gen_scope_array 328 -hier_path 43056 +hier_path 43077 if_else 4404 if_stmt 23958 immediate_assert 5 @@ -1643,7 +1643,7 @@ range 62338 real_typespec 58 real_var 9 ref_module 31 -ref_obj 251121 +ref_obj 251142 ref_var 9759 repeat 158 return_stmt 14240 diff --git a/third_party/tests/Monitor/Monitor.log b/third_party/tests/Monitor/Monitor.log index 4cd1087d9b..a6040e61ed 100644 --- a/third_party/tests/Monitor/Monitor.log +++ b/third_party/tests/Monitor/Monitor.log @@ -902,7 +902,7 @@ forever_stmt 18 fork_stmt 69 func_call 9554 function 6840 -hier_path 14014 +hier_path 14035 if_else 1428 if_stmt 7721 immediate_assert 9 @@ -938,7 +938,7 @@ range 7715 real_typespec 37 real_var 8 ref_module 1 -ref_obj 77506 +ref_obj 77527 ref_var 3307 repeat 50 return_stmt 5220 diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index 0c603500f7..3cbad0e25a 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -1760,7 +1760,7 @@ interface_array 4 interface_inst 48 interface_typespec 118 io_decl 831 -logic_net 3878 +logic_net 3873 logic_typespec 19346 logic_var 2684 modport 77 @@ -1835,7 +1835,7 @@ interface_array 4 interface_inst 48 interface_typespec 118 io_decl 845 -logic_net 3878 +logic_net 3873 logic_typespec 19346 logic_var 6026 modport 77 @@ -1864,57 +1864,13 @@ task_call 22 typespec_member 7574 var_select 953 === UHDM Object Stats End === -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:299:17: Unresolved hierarchical reference "nyuzi_io_bus.write_en". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:301:23: Unresolved hierarchical reference "nyuzi_io_bus.address". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:305:38: Unresolved hierarchical reference "nyuzi_io_bus.write_data[7:0]". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:310:49: Unresolved hierarchical reference "nyuzi_io_bus.write_data[0]". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:313:51: Unresolved hierarchical reference "nyuzi_io_bus.write_data". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:317:17: Unresolved hierarchical reference "nyuzi_io_bus.read_en". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:319:24: Unresolved hierarchical reference "nyuzi_io_bus.address[15:0]". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:262:57: Unresolved hierarchical reference "nyuzi_io_bus.write_en". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:263:56: Unresolved hierarchical reference "nyuzi_io_bus.read_en". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:264:56: Unresolved hierarchical reference "nyuzi_io_bus.address". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:265:59: Unresolved hierarchical reference "nyuzi_io_bus.write_data". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:222:12: Unresolved hierarchical reference "host_jtag.tdi". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:222:28: Unresolved hierarchical reference "target_jtag.tdo". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:223:12: Unresolved hierarchical reference "target_jtag.tdi". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:223:30: Unresolved hierarchical reference "host_jtag.tdo". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:224:12: Unresolved hierarchical reference "target_jtag.tck". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:224:30: Unresolved hierarchical reference "host_jtag.tck". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:225:12: Unresolved hierarchical reference "target_jtag.trst_n". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:225:33: Unresolved hierarchical reference "host_jtag.trst_n". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:226:12: Unresolved hierarchical reference "target_jtag.tms". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:226:30: Unresolved hierarchical reference "host_jtag.tms". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:256:12: Unresolved hierarchical reference "nyuzi_io_bus.read_data". - [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/NyuziProcessor/slpp_unit/surelog.uhdm ... [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/NyuziProcessor/slpp_unit/checker/surelog.chk.html ... [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 70 +[ ERROR] : 48 [WARNING] : 0 [ NOTE] : 12 diff --git a/third_party/tests/OVMSwitch/OVMSwitch.log b/third_party/tests/OVMSwitch/OVMSwitch.log index 29840f26da..0319106b63 100644 --- a/third_party/tests/OVMSwitch/OVMSwitch.log +++ b/third_party/tests/OVMSwitch/OVMSwitch.log @@ -773,7 +773,7 @@ integer_var 75 interface_inst 17 interface_typespec 6 io_decl 3594 -logic_net 483 +logic_net 481 logic_typespec 255 logic_var 39 method_func_call 3512 diff --git a/third_party/tests/Rp32/rp32.log b/third_party/tests/Rp32/rp32.log index 629628a13d..c196fa61fe 100644 --- a/third_party/tests/Rp32/rp32.log +++ b/third_party/tests/Rp32/rp32.log @@ -431,7 +431,7 @@ interface_array 2 interface_inst 13 interface_typespec 21 io_decl 235 -logic_net 418 +logic_net 417 logic_typespec 1102 logic_var 203 modport 22 @@ -499,7 +499,7 @@ interface_array 2 interface_inst 13 interface_typespec 21 io_decl 428 -logic_net 418 +logic_net 417 logic_typespec 1102 logic_var 207 modport 22 @@ -529,26 +529,12 @@ typespec_member 6883 union_typespec 6 union_var 1 === UHDM Object Stats End === -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:110:13: Unresolved hierarchical reference "bus_ls.vld". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:111:13: Unresolved hierarchical reference "bus_ls.wen". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:112:13: Unresolved hierarchical reference "bus_ls.adr". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:113:13: Unresolved hierarchical reference "bus_ls.ben". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:114:13: Unresolved hierarchical reference "bus_ls.wdt". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:115:13: Unresolved hierarchical reference "bus_ls.rdt". - -[ERR:UH0725] ${SURELOG_DIR}/third_party/tests/Rp32/hdl/rtl/soc/r5p_soc_top.sv:116:13: Unresolved hierarchical reference "bus_ls.rdy". - [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/rp32/slpp_all/surelog.uhdm ... [INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/rp32/slpp_all/checker/surelog.chk.html ... [ FATAL] : 0 [ SYNTAX] : 0 -[ ERROR] : 7 +[ ERROR] : 0 [WARNING] : 20 [ NOTE] : 76 diff --git a/third_party/tests/Tnoc/Tnoc.log b/third_party/tests/Tnoc/Tnoc.log index 9455c36fec..b1b77c7a0c 100644 --- a/third_party/tests/Tnoc/Tnoc.log +++ b/third_party/tests/Tnoc/Tnoc.log @@ -24159,7 +24159,7 @@ interface_array 989 interface_inst 24779 interface_typespec 40659 io_decl 97940 -logic_net 9528 +logic_net 9519 logic_typespec 71267 logic_var 49617 method_func_call 2197 diff --git a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log index 62a084399a..9a574abc3e 100644 --- a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log +++ b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log @@ -910,7 +910,7 @@ int_var 4059 interface_inst 4 interface_typespec 7 io_decl 18988 -logic_net 353 +logic_net 352 logic_typespec 334 logic_var 116 long_int_typespec 259 diff --git a/third_party/tests/UVMSwitch/UVMSwitch.log b/third_party/tests/UVMSwitch/UVMSwitch.log index 74bcd01ea6..23e0e51d8f 100644 --- a/third_party/tests/UVMSwitch/UVMSwitch.log +++ b/third_party/tests/UVMSwitch/UVMSwitch.log @@ -6970,7 +6970,7 @@ integer_var 9 interface_inst 17 interface_typespec 6 io_decl 6968 -logic_net 564 +logic_net 562 logic_typespec 250 logic_var 44 long_int_typespec 99 diff --git a/third_party/tests/YosysVerx/YosysVerx.sl b/third_party/tests/YosysVerx/YosysVerx.sl index 646c5ffdc5..feb3b98089 100644 --- a/third_party/tests/YosysVerx/YosysVerx.sl +++ b/third_party/tests/YosysVerx/YosysVerx.sl @@ -1 +1 @@ - +incdir+.+../../../UVM/uvm-1.2/src/ -writepp -parse -mt max -nopython -fileunit *.v + +incdir+.+../../../UVM/uvm-1.2/src/ -writepp -parse -mt max -nopython -fileunit vexriscv.demo.GenFull.v From 7bff6de41c6428c3a961fd14d0160a7f64ef8690 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Sun, 23 Apr 2023 11:20:13 -0700 Subject: [PATCH 2/2] interface binding --- tests/InterfInst/InterfInst.log | 574 ++++++++++++++++++++++++++++++++ tests/InterfInst/InterfInst.sl | 1 + tests/InterfInst/dut.sv | 14 + 3 files changed, 589 insertions(+) create mode 100644 tests/InterfInst/InterfInst.log create mode 100644 tests/InterfInst/InterfInst.sl create mode 100644 tests/InterfInst/dut.sv diff --git a/tests/InterfInst/InterfInst.log b/tests/InterfInst/InterfInst.log new file mode 100644 index 0000000000..5d9106440d --- /dev/null +++ b/tests/InterfInst/InterfInst.log @@ -0,0 +1,574 @@ +[INF:CM0023] Creating log file ${SURELOG_DIR}/build/regression/InterfInst/slpp_all/surelog.log. + +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/InterfInst/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<126> s<125> l<2:1> el<1:2> +n<> u<2> t p<5> s<4> l<2:1> el<2:10> +n u<3> t p<4> l<2:11> el<2:22> +n<> u<4> t p<5> c<3> l<2:11> el<2:22> +n<> u<5> t p<19> c<2> s<17> l<2:1> el<2:23> +n<> u<6> t p<7> l<3:4> el<3:7> +n<> u<7> t p<11> c<6> s<10> l<3:4> el<3:7> +n u<8> t p<9> l<3:8> el<3:18> +n<> u<9> t p<10> c<8> l<3:8> el<3:18> +n<> u<10> t p<11> c<9> l<3:8> el<3:18> +n<> u<11> t p<12> c<7> l<3:4> el<3:19> +n<> u<12> t p<13> c<11> l<3:4> el<3:19> +n<> u<13> t p<14> c<12> l<3:4> el<3:19> +n<> u<14> t p<15> c<13> l<3:4> el<3:19> +n<> u<15> t p<16> c<14> l<3:4> el<3:19> +n<> u<16> t p<17> c<15> l<3:4> el<3:19> +n<> u<17> t p<19> c<16> s<18> l<3:4> el<3:19> +n<> u<18> t p<19> l<4:1> el<4:13> +n<> u<19> t p<20> c<5> l<2:1> el<4:13> +n<> u<20> t p<125> c<19> s<60> l<2:1> el<4:13> +n u<21> t p<39> s<22> l<6:1> el<6:7> +n u<22> t p<39> s<38> l<6:8> el<6:11> +n u<23> t p<24> l<6:12> el<6:23> +n<> u<24> t p<25> c<23> l<6:12> el<6:23> +n<> u<25> t p<26> c<24> l<6:12> el<6:23> +n<> u<26> t p<27> c<25> l<6:12> el<6:23> +n<> u<27> t p<29> c<26> s<28> l<6:12> el<6:23> +n u<28> t p<29> l<6:24> el<6:29> +n<> u<29> t p<38> c<27> s<37> l<6:12> el<6:29> +n<> u<30> t p<35> s<34> l<6:31> el<6:37> +n<> u<31> t p<32> l<6:38> el<6:41> +n<> u<32> t p<33> c<31> l<6:38> el<6:41> +n<> u<33> t p<34> c<32> l<6:38> el<6:41> +n<> u<34> t p<35> c<33> l<6:38> el<6:41> +n<> u<35> t p<37> c<30> s<36> l<6:31> el<6:41> +n u<36> t p<37> l<6:42> el<6:43> +n<> u<37> t p<38> c<35> l<6:31> el<6:43> +n<> u<38> t p<39> c<29> l<6:11> el<6:44> +n<> u<39> t p<59> c<21> s<57> l<6:1> el<6:45> +n u<40> t p<41> l<7:11> el<7:12> +n<> u<41> t p<44> c<40> s<43> l<7:11> el<7:12> +n<> u<42> t p<43> l<7:13> el<7:13> +n<> u<43> t p<44> c<42> l<7:13> el<7:13> +n<> u<44> t p<52> c<41> s<51> l<7:11> el<7:12> +n u<45> t p<49> s<46> l<7:15> el<7:20> +n u<46> t p<49> s<48> l<7:21> el<7:31> +n<> u<47> t p<48> l<7:31> el<7:31> +n<> u<48> t