diff --git a/src/DesignCompile/CompileExpression.cpp b/src/DesignCompile/CompileExpression.cpp index d66a8df0f8..30b929d882 100644 --- a/src/DesignCompile/CompileExpression.cpp +++ b/src/DesignCompile/CompileExpression.cpp @@ -4774,6 +4774,31 @@ UHDM::any *CompileHelper::compileComplexFuncCall( result->VpiParent(param); else result = param; + } else if ((fC->Type(List_of_arguments) == + VObjectType::slStringConst)) { + hier_path *path = s.MakeHier_path(); + VectorOfany *elems = s.MakeAnyVec(); + path->Path_elems(elems); + ref_obj *ref = s.MakeRef_obj(); + ref->VpiName(StrCat(packagename, "::", functionname)); + ref->VpiFullName(StrCat(packagename, "::", functionname)); + ref->Actual_group(param); + ref->VpiParent(pexpr); + fC->populateCoreMembers(name, name, ref); + elems->push_back(ref); + while (List_of_arguments) { + if ((fC->Type(List_of_arguments) == + VObjectType::slStringConst)) { + ref_obj *ref = s.MakeRef_obj(); + ref->VpiName(fC->SymName(List_of_arguments)); + ref->VpiParent(pexpr); + fC->populateCoreMembers(List_of_arguments, List_of_arguments, + ref); + elems->push_back(ref); + } + List_of_arguments = fC->Sibling(List_of_arguments); + } + result = path; } else { ref_obj *ref = s.MakeRef_obj(); ref->VpiName(StrCat(packagename, "::", functionname)); diff --git a/tests/PackStructField/PackStructField.log b/tests/PackStructField/PackStructField.log new file mode 100644 index 0000000000..d07dd64d6e --- /dev/null +++ b/tests/PackStructField/PackStructField.log @@ -0,0 +1,596 @@ +[INF:CM0023] Creating log file ${SURELOG_DIR}/build/regression/PackStructField/slpp_all/surelog.log. + +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/PackStructField/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<135> s<134> l<2:1> el<1:2> +n<> u<2> t p<60> s<3> l<2:1> el<2:8> +n u<3> t p<60> s<26> l<2:9> el<2:19> +n<> u<4> t p<5> l<4:11> el<4:17> +n<> u<5> t p<21> c<4> s<6> l<4:11> el<4:17> +n<> u<6> t p<21> s<13> l<4:18> el<4:24> +n<> u<7> t p<8> l<5:5> el<5:10> +n<> u<8> t p<9> c<7> l<5:5> el<5:10> +n<> u<9> t p<13> c<8> s<12> l<5:5> el<5:10> +n u<10> t p<11> l<5:11> el<5:12> +n<> u<11> t p<12> c<10> l<5:11> el<5:12> +n<> u<12> t p<13> c<11> l<5:11> el<5:12> +n<> u<13> t p<21> c<9> s<20> l<5:5> el<5:13> +n<> u<14> t p<15> l<6:5> el<6:10> +n<> u<15> t p<16> c<14> l<6:5> el<6:10> +n<> u<16> t p<20> c<15> s<19> l<6:5> el<6:10> +n u<17> t p<18> l<6:11> el<6:12> +n<> u<18> t p<19> c<17> l<6:11> el<6:12> +n<> u<19> t p<20> c<18> l<6:11> el<6:12> +n<> u<20> t p<21> c<16> l<6:5> el<6:13> +n<> u<21> t p<23> c<5> s<22> l<4:11> el<7:4> +n u<22> t p<23> l<7:5> el<7:14> +n<> u<23> t p<24> c<21> l<4:3> el<7:15> +n<> u<24> t p<25> c<23> l<4:3> el<7:15> +n<> u<25> t p<26> c<24> l<4:3> el<7:15> +n<> u<26> t p<60> c<25> s<57> l<4:3> el<7:15> +n u<27> t p<28> l<9:13> el<9:23> +n<> u<28> t p<29> c<27> l<9:13> el<9:23> +n<> u<29> t p<31> c<28> s<30> l<9:13> el<9:25> +n u<30> t p<31> l<9:25> el<9:34> +n<> u<31> t p<32> c<29> l<9:13> el<9:34> +n<> u<32> t p<55> c<31> s<54> l<9:13> el<9:34> +n u<33> t p<53> s<52> l<9:35> el<9:47> +n u<34> t p<35> l<10:5> el<10:6> +n<> u<35> t p<46> c<34> s<39> l<10:5> el<10:6> +n<> u<36> t p<37> l<10:8> el<10:12> +n<> u<37> t p<38> c<36> l<10:8> el<10:12> +n<> u<38> t p<39> c<37> l<10:8> el<10:12> +n<> u<39> t p<46> c<38> s<41> l<10:8> el<10:12> +n u<40> t p<41> l<11:5> el<11:6> +n<> u<41> t p<46> c<40> s<45> l<11:5> el<11:6> +n<> u<42> t p<43> l<11:8> el<11:12> +n<> u<43> t p<44> c<42> l<11:8> el<11:12> +n<> u<44> t p<45> c<43> l<11:8> el<11:12> +n<> u<45> t p<46> c<44> l<11:8> el<11:12> +n<> u<46> t p<47> c<35> l<9:50> el<12:4> +n<> u<47> t p<48> c<46> l<9:50> el<12:4> +n<> u<48> t p<49> c<47> l<9:50> el<12:4> +n<> u<49> t p<50> c<48> l<9:50> el<12:4> +n<> u<50> t p<51> c<49> l<9:50> el<12:4> +n<> u<51> t p<52> c<50> l<9:50> el<12:4> +n<> u<52> t p<53> c<51> l<9:50> el<12:4> +n<> u<53> t p<54> c<33> l<9:35> el<12:4> +n<> u<54> t p<55> c<53> l<9:35> el<12:4> +n<> u<55> t p<56> c<32> l<9:3> el<12:4> +n<> u<56> t p<57> c<55> l<9:3> el<12:5> +n<> u<57> t p<60> c<56> s<59> l<9:3> el<12:5> +n u<58> t p<60> l<14:14> el<14:24> +n<> u<59> t p<60> s<58> l<14:1> el<14:11> +n<> u<60> t p<61> c<2> l<2:1> el<14:24> +n<> u<61> t p<134> c<60> s<133> l<2:1> el<14:24> +n u<62> t p<87> s<63> l<16:1> el<16:7> +n u<63> t p<87> s<86> l<16:8> el<16:17> +n<> u<64> t p<72> s<71> l<17:5> el<17:11> +n u<65> t p<66> l<17:12> el<17:22> +n<> u<66> t p<67> c<65> l<17:12> el<17:22> +n<> u<67> t p<69> c<66> s<68> l<17:12> el<17:24> +n u<68> t p<69> l<17:24> el<17:33> +n<> u<69> t p<70> c<67> l<17:12> el<17:33> +n<> u<70> t p<71> c<69> l<17:12> el<17:33> +n<> u<71> t p<72> c<70> l<17:12> el<17:33> +n<> u<72> t p<74> c<64> s<73> l<17:5> el<17:33> +n u<73> t p<74> l<17:34> el<17:35> +n<> u<74> t p<86> c<72> s<85> l<17:5> el<17:35> +n<> u<75> t p<83> s<82> l<18:5> el<18:11> +n u<76> t p<77> l<18:12> el<18:22> +n<> u<77> t p<78> c<76> l<18:12> el<18:22> +n<> u<78> t p<80> c<77> s<79> l<18:12> el<18:24> +n u<79> t p<80> l<18:24> el<18:33> +n<> u<80> t p<81> c<78> l<18:12> el<18:33> +n<> u<81> t p<82> c<80> l<18:12> el<18:33> +n<> u<82> t p<83> c<81> l<18:12> el<18:33> +n<> u<83> t p<85> c<75> s<84> l<18:5> el<18:33> +n u<84> t p<85> l<18:34> el<18:35> +n<> u<85> t p<86> c<83> l<18:5> el<18:35> +n<> u<86> t p<87> c<74> l<16:18> el<19:2> +n<> u<87> t p<132> c<62> s<108> l<16:1> el<19:3> +n u<88> t p<89> l<21:8> el<21:9> +n<> u<89> t p<92> c<88> s<91> l<21:8> el<21:9> +n<> u<90> t p<91> l<21:10> el<21:10> +n<> u<91> t p<92> c<90> l<21:10> el<21:10> +n<> u<92> t p<103> c<89> s<102> l<21:8> el<21:9> +n u<93> t p<94> l<21:12> el<21:22> +n<> u<94> t p<95> c<93> l<21:12> el<21:22> +n<> u<95> t p<100> c<94> s<96> l<21:12> el<21:24> +n u<96> t p<100> s<97> l<21:24> el<21:36> +n u<97> t p<100> s<99> l<21:37> el<21:38> +n<> u<98> t p<99> l<21:38> el<21:38> +n<> u<99> t p<121> c<119> l<22:38> el<22:38> +n<> u<121> t p<122> c<116> l<22:12> el<22:38> +n<> u<122> t p<123> c<121> l<22:12> el<22:38> +n<> u<123> t p<124> c<122> l<22:12> el<22:38> +n<> u<124> t p<125> c<113> l<22:8> el<22:38> +n<> u<125> t p<126> c<124> l<22:8> el<22:38> +n<> u<126> t p<127> c<125> l<22:1> el<22:39> +n<> u<127> t p<128> c<126> l<22:1> el<22:39> +n<> u<128> t p<129> c<127> l<22:1> el<22:39> +n<> u<129> t p<132> c<128> s<131> l<22:1> el<22:39> +n u<130> t p<132> l<24:13> el<24:22> +n<> u<131> t p<132> s<130> l<24:1> el<24:10> +n<> u<132> t p<133> c<87> l<16:1> el<24:22> +n<> u<133> t p<134> c<132> l<16:1> el<24:22> +n<> u<134> t p<135> c<61> l<2:1> el<24:22> +n<> u<135> t c<1> l<2:1> el<24:22> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/PackStructField/dut.sv:2:1: No timescale set for "my_package". + +[WRN:PA0205] ${SURELOG_DIR}/tests/PackStructField/dut.sv:16:1: No timescale set for "my_module". + +[INF:CP0300] Compilation... + +[INF:CP0301] ${SURELOG_DIR}/tests/PackStructField/dut.sv:2:1: Compile package "my_package". + +[INF:CP0303] ${SURELOG_DIR}/tests/PackStructField/dut.sv:16:1: Compile module "work@my_module". + +[INF:EL0526] Design Elaboration... + +[NTE:EL0503] ${SURELOG_DIR}/tests/PackStructField/dut.sv:16:1: Top level module "work@my_module". + +[NTE:EL0508] Nb Top level modules: 1. + +[NTE:EL0509] Max instance depth: 1. + +[NTE:EL0510] Nb instances: 1. + +[NTE:EL0511] Nb leaf instances: 1. + +[INF:UH0706] Creating UHDM Model... + +=== UHDM Object Stats Begin (Non-Elaborated Model) === +constant 20 +cont_assign 4 +design 1 +hier_path 4 +logic_net 2 +logic_typespec 16 +module_inst 5 +operation 10 +package 3 +param_assign 4 +parameter 4 +port 4 +ref_obj 16 +string_typespec 14 +struct_net 2 +struct_typespec 8 +tagged_pattern 14 +typespec_member 16 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... + +=== UHDM Object Stats Begin (Elaborated Model) === +constant 20 +cont_assign 6 +design 1 +hier_path 4 +logic_net 2 +logic_typespec 16 +module_inst 5 +operation 10 +package 3 +param_assign 4 +parameter 4 +port 6 +ref_obj 20 +string_typespec 14 +struct_net 2 +struct_typespec 8 +tagged_pattern 14 +typespec_member 16 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/PackStructField/slpp_all/surelog.uhdm ... + +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/PackStructField/slpp_all/checker/surelog.chk.html ... + +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/PackStructField/slpp_all/surelog.uhdm ... + +[INF:UH0711] Decompiling UHDM... + +====== UHDM ======= +design: (work@my_module) +|vpiElaborated:1 +|vpiName:work@my_module +|uhdmallPackages: +\_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiParent: + \_design: (work@my_module) + |vpiName:my_package + |vpiFullName:my_package:: + |vpiParameter: + \_parameter: (my_package::my_parameter), line:9:35, endln:9:47 + |vpiParent: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiTypespec: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiParent: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiName:my_package::my_struct + |vpiInstance: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiPacked:1 + |vpiTypespecMember: + \_typespec_member: (a), line:5:11, endln:5:12 + |vpiParent: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:a + |vpiTypespec: + \_logic_typespec: , line:5:5, endln:5:10 + |vpiParent: + \_typespec_member: (a), line:5:11, endln:5:12 + |vpiInstance: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiRefFile:${SURELOG_DIR}/tests/PackStructField/dut.sv + |vpiRefLineNo:5 + |vpiRefColumnNo:5 + |vpiRefEndLineNo:5 + |vpiRefEndColumnNo:10 + |vpiTypespecMember: + \_typespec_member: (b), line:6:11, endln:6:12 + |vpiParent: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:b + |vpiTypespec: + \_logic_typespec: , line:6:5, endln:6:10 + |vpiParent: + \_typespec_member: (b), line:6:11, endln:6:12 + |vpiInstance: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiRefFile:${SURELOG_DIR}/tests/PackStructField/dut.sv + |vpiRefLineNo:6 + |vpiRefColumnNo:5 + |vpiRefEndLineNo:6 + |vpiRefEndColumnNo:10 + |vpiName:my_parameter + |vpiFullName:my_package::my_parameter + |vpiParamAssign: + \_param_assign: , line:9:35, endln:12:4 + |vpiParent: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiRhs: + \_operation: , line:9:50, endln:12:4 + |vpiOpType:75 + |vpiOperand: + \_tagged_pattern: , line:10:8, endln:10:12 + |vpiPattern: + \_constant: , line:10:8, endln:10:12 + |vpiDecompile:1'b1 + |vpiSize:1 + |BIN:1 + |vpiConstType:3 + |vpiTypespec: + \_string_typespec: (a), line:10:5, endln:10:6 + |vpiName:a + |vpiOperand: + \_tagged_pattern: , line:11:8, endln:11:12 + |vpiPattern: + \_constant: , line:11:8, endln:11:12 + |vpiDecompile:1'b0 + |vpiSize:1 + |BIN:0 + |vpiConstType:3 + |vpiTypespec: + \_string_typespec: (b), line:11:5, endln:11:6 + |vpiName:b + |vpiLhs: + \_parameter: (my_package::my_parameter), line:9:35, endln:9:47 + |vpiTypedef: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiParent: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiName:my_package::my_struct + |vpiInstance: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiPacked:1 + |vpiTypespecMember: + \_typespec_member: (a), line:5:11, endln:5:12 + |vpiParent: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:a + |vpiTypespec: + \_logic_typespec: , line:5:5, endln:5:10 + |vpiParent: + \_typespec_member: (a), line:5:11, endln:5:12 + |vpiInstance: + \_package: (my_package) + |vpiRefFile:${SURELOG_DIR}/tests/PackStructField/dut.sv + |vpiRefLineNo:5 + |vpiRefColumnNo:5 + |vpiRefEndLineNo:5 + |vpiRefEndColumnNo:10 + |vpiTypespecMember: + \_typespec_member: (b), line:6:11, endln:6:12 + |vpiParent: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:b + |vpiTypespec: + \_logic_typespec: , line:6:5, endln:6:10 + |vpiParent: + \_typespec_member: (b), line:6:11, endln:6:12 + |vpiInstance: + \_package: (my_package) + |vpiRefFile:${SURELOG_DIR}/tests/PackStructField/dut.sv + |vpiRefLineNo:6 + |vpiRefColumnNo:5 + |vpiRefEndLineNo:6 + |vpiRefEndColumnNo:10 + |vpiDefName:my_package +|uhdmtopPackages: +\_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiParent: + \_design: (work@my_module) + |vpiName:my_package + |vpiFullName:my_package:: + |vpiParameter: + \_parameter: (my_package::my_parameter), line:9:35, endln:9:47 + |vpiParent: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiTypespec: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:my_parameter + |vpiFullName:my_package::my_parameter + |vpiParamAssign: + \_param_assign: , line:9:35, endln:12:4 + |vpiParent: + \_package: my_package (my_package::), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:2:1, endln:14:24 + |vpiRhs: + \_operation: , line:9:50, endln:12:4 + |vpiOpType:75 + |vpiOperand: + \_tagged_pattern: , line:10:8, endln:10:12 + |vpiPattern: + \_constant: , line:10:8, endln:10:12 + |vpiDecompile:1'b1 + |vpiSize:1 + |BIN:1 + |vpiConstType:3 + |vpiTypespec: + \_string_typespec: (a), line:10:5, endln:10:6 + |vpiName:a + |vpiOperand: + \_tagged_pattern: , line:11:8, endln:11:12 + |vpiPattern: + \_constant: , line:11:8, endln:11:12 + |vpiDecompile:1'b0 + |vpiSize:1 + |BIN:0 + |vpiConstType:3 + |vpiTypespec: + \_string_typespec: (b), line:11:5, endln:11:6 + |vpiName:b + |vpiLhs: + \_parameter: (my_package::my_parameter), line:9:35, endln:9:47 + |vpiTypedef: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiDefName:my_package + |vpiTop:1 +|uhdmallModules: +\_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiParent: + \_design: (work@my_module) + |vpiFullName:work@my_module + |vpiDefName:work@my_module + |vpiNet: + \_logic_net: (work@my_module.x), line:17:34, endln:17:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:x + |vpiFullName:work@my_module.x + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@my_module.y), line:18:34, endln:18:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:y + |vpiFullName:work@my_module.y + |vpiNetType:1 + |vpiPort: + \_port: (x), line:17:34, endln:17:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:x + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: + |vpiActual: + \_logic_net: (work@my_module.x), line:17:34, endln:17:35 + |vpiTypedef: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiPort: + \_port: (y), line:18:34, endln:18:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:y + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: + |vpiActual: + \_logic_net: (work@my_module.y), line:18:34, endln:18:35 + |vpiTypedef: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiContAssign: + \_cont_assign: , line:21:8, endln:21:38 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiRhs: + \_hier_path: (work@my_module), line:21:12, endln:21:38 + |vpiParent: + \_cont_assign: , line:21:8, endln:21:38 + |vpiFullName:work@my_module + |vpiActual: + \_ref_obj: (my_package::my_parameter), line:21:12, endln:21:24 + |vpiName:my_package::my_parameter + |vpiActual: + \_parameter: (my_package::my_parameter), line:9:35, endln:9:47 + |vpiActual: + \_ref_obj: (a), line:21:37, endln:21:38 + |vpiName:a + |vpiLhs: + \_ref_obj: (work@my_module.x), line:21:8, endln:21:9 + |vpiParent: + \_cont_assign: , line:21:8, endln:21:38 + |vpiName:x + |vpiFullName:work@my_module.x + |vpiActual: + \_struct_net: (work@my_module.x), line:17:34, endln:17:35 + |vpiContAssign: + \_cont_assign: , line:22:8, endln:22:38 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiRhs: + \_hier_path: (work@my_module), line:22:12, endln:22:38 + |vpiParent: + \_cont_assign: , line:22:8, endln:22:38 + |vpiFullName:work@my_module + |vpiActual: + \_ref_obj: (my_package::my_parameter), line:22:12, endln:22:24 + |vpiName:my_package::my_parameter + |vpiActual: + \_parameter: (my_package::my_parameter), line:9:35, endln:9:47 + |vpiActual: + \_ref_obj: (b), line:22:37, endln:22:38 + |vpiName:b + |vpiLhs: + \_ref_obj: (work@my_module.y), line:22:8, endln:22:9 + |vpiParent: + \_cont_assign: , line:22:8, endln:22:38 + |vpiName:y + |vpiFullName:work@my_module.y + |vpiActual: + \_struct_net: (work@my_module.y), line:18:34, endln:18:35 +|uhdmtopModules: +\_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:work@my_module + |vpiDefName:work@my_module + |vpiTop:1 + |vpiNet: + \_struct_net: (work@my_module.x), line:17:34, endln:17:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiTypespec: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:x + |vpiFullName:work@my_module.x + |vpiNetType:1 + |vpiNet: + \_struct_net: (work@my_module.y), line:18:34, endln:18:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiTypespec: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiName:y + |vpiFullName:work@my_module.y + |vpiNetType:1 + |vpiTopModule:1 + |vpiPort: + \_port: (x), line:17:34, endln:17:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:x + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@my_module.x), line:17:34, endln:17:35 + |vpiParent: + \_port: (x), line:17:34, endln:17:35 + |vpiName:x + |vpiFullName:work@my_module.x + |vpiActual: + \_struct_net: (work@my_module.x), line:17:34, endln:17:35 + |vpiTypedef: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiInstance: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiPort: + \_port: (y), line:18:34, endln:18:35 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiName:y + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@my_module.y), line:18:34, endln:18:35 + |vpiParent: + \_port: (y), line:18:34, endln:18:35 + |vpiName:y + |vpiFullName:work@my_module.y + |vpiActual: + \_struct_net: (work@my_module.y), line:18:34, endln:18:35 + |vpiTypedef: + \_struct_typespec: (my_package::my_struct), line:4:11, endln:4:17 + |vpiInstance: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiContAssign: + \_cont_assign: , line:21:8, endln:21:38 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiRhs: + \_constant: , line:10:8, endln:10:12 + |vpiParent: + \_cont_assign: , line:21:8, endln:21:38 + |vpiDecompile:1'b1 + |vpiSize:1 + |BIN:1 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@my_module.x), line:21:8, endln:21:9 + |vpiParent: + \_cont_assign: , line:21:8, endln:21:38 + |vpiName:x + |vpiFullName:work@my_module.x + |vpiActual: + \_struct_net: (work@my_module.x), line:17:34, endln:17:35 + |vpiContAssign: + \_cont_assign: , line:22:8, endln:22:38 + |vpiParent: + \_module_inst: work@my_module (work@my_module), file:${SURELOG_DIR}/tests/PackStructField/dut.sv, line:16:1, endln:24:22 + |vpiRhs: + \_constant: , line:11:8, endln:11:12 + |vpiParent: + \_cont_assign: , line:22:8, endln:22:38 + |vpiDecompile:1'b0 + |vpiSize:1 + |BIN:0 + |vpiConstType:3 + |vpiLhs: + \_ref_obj: (work@my_module.y), line:22:8, endln:22:9 + |vpiParent: + \_cont_assign: , line:22:8, endln:22:38 + |vpiName:y + |vpiFullName:work@my_module.y + |vpiActual: + \_struct_net: (work@my_module.y), line:18:34, endln:18:35 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 2 +[ NOTE] : 5 + + +[roundtrip]: ${SURELOG_DIR}/tests/PackStructField/dut.sv | ${SURELOG_DIR}/build/regression/PackStructField/roundtrip/dut_000.sv | 8 | 24 | \ No newline at end of file diff --git a/tests/PackStructField/PackStructField.sl b/tests/PackStructField/PackStructField.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/PackStructField/PackStructField.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/PackStructField/dut.sv b/tests/PackStructField/dut.sv new file mode 100644 index 0000000000..5e8034e43b --- /dev/null +++ b/tests/PackStructField/dut.sv @@ -0,0 +1,24 @@ + +package my_package; + + typedef struct packed { + logic a; + logic b; + } my_struct; + + parameter my_package::my_struct my_parameter = '{ + a: 1'b1, + b: 1'b0 + }; + +endpackage : my_package + +module my_module ( + output my_package::my_struct x, + output my_package::my_struct y +); + +assign x = my_package::my_parameter.a; +assign y = my_package::my_parameter.b; + +endmodule : my_module \ No newline at end of file diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 8dcd5b665d..7221e0b70c 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -3,7 +3,7 @@ [WRN:CM0010] Command line argument "-Wno-UNOPTFLAT" ignored. Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 16 --- Configuring done (0.0s) +-- Configuring done (0.1s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser [100%] Generating preprocessing @@ -118,20 +118,20 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 10_lsu_bus_intf.sv -[ 12%] Generating 11_ifu_bp_ctl.sv -[ 18%] Generating 12_beh_lib.sv +[ 6%] Generating 12_beh_lib.sv +[ 12%] Generating 10_lsu_bus_intf.sv +[ 18%] Generating 11_ifu_bp_ctl.sv [ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv -[ 62%] Generating 4_dec_tlu_ctl.sv -[ 68%] Generating 3_rvjtag_tap.sv +[ 62%] Generating 3_rvjtag_tap.sv +[ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv -[ 81%] Generating 6_dbg.sv -[ 87%] Generating 7_axi4_to_ahb.sv +[ 81%] Generating 7_axi4_to_ahb.sv +[ 87%] Generating 6_dbg.sv [ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse