From c66a6a7753dcc7a7ed5c85fbbe7be77d54aaf2c4 Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain.dargelas@gmail.com>
Date: Fri, 15 Dec 2023 18:19:17 -0800
Subject: [PATCH] Unbound for loop support

---
 src/DesignCompile/UhdmWriter.cpp              |  12 +-
 tests/ConstCapital/ConstCapital.log           |   4 +-
 tests/UnboundForLoop/UnboundForLoop.log       | 873 ++++++++++++++++++
 tests/UnboundForLoop/UnboundForLoop.sl        |   1 +
 tests/UnboundForLoop/dut.sv                   |   9 +
 third_party/UHDM                              |   2 +-
 .../tests/CoresSweRVMP/CoresSweRVMP.log       |   8 +-
 third_party/tests/Scr1/Scr1.log               |   2 +-
 third_party/tests/Scr1SvTests/Scr1SvTests.log |   2 +-
 9 files changed, 903 insertions(+), 10 deletions(-)
 create mode 100644 tests/UnboundForLoop/UnboundForLoop.log
 create mode 100644 tests/UnboundForLoop/UnboundForLoop.sl
 create mode 100644 tests/UnboundForLoop/dut.sv

diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp
index 7e70ce6b56..1f9c459c95 100644
--- a/src/DesignCompile/UhdmWriter.cpp
+++ b/src/DesignCompile/UhdmWriter.cpp
@@ -3163,7 +3163,17 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
 
     const any* parent = ref->VpiParent();
     while (parent) {
-      if (parent->UhdmType() == uhdmfunction) {
+      if (parent->UhdmType() == uhdmdesign) {
+        design* d = (design*) parent;
+        if (auto params = d->Parameters()) {
+          for (auto decl : *params) {
+            if (decl->VpiName() == name) {
+              ref->Actual_group(decl);
+              break;
+            }
+          }
+        }
+      } else if (parent->UhdmType() == uhdmfunction) {
         function* func = (function*)parent;
         if (parent->VpiName() == name) {
           if (const any* ret = func->Return()) {
diff --git a/tests/ConstCapital/ConstCapital.log b/tests/ConstCapital/ConstCapital.log
index b155155191..5e7f0438e6 100644
--- a/tests/ConstCapital/ConstCapital.log
+++ b/tests/ConstCapital/ConstCapital.log
@@ -208,7 +208,7 @@ design: (work@test)
         |vpiName:foo
         |vpiFullName:work@test.foo
         |vpiActual:
-        \_logic_net: (work@test.foo), line:10:5, endln:10:8
+        \_parameter: (foo), line:1:15, endln:1:18
       |vpiOperand:
       \_constant: , line:10:12, endln:10:20
         |vpiParent:
@@ -244,7 +244,7 @@ design: (work@test)
         |vpiName:foo2
         |vpiFullName:work@test.foo2
         |vpiActual:
-        \_logic_net: (work@test.foo2), line:15:5, endln:15:9
+        \_parameter: (foo2), line:2:15, endln:2:19
       |vpiOperand:
       \_constant: , line:15:13, endln:15:18
         |vpiParent:
diff --git a/tests/UnboundForLoop/UnboundForLoop.log b/tests/UnboundForLoop/UnboundForLoop.log
new file mode 100644
index 0000000000..86ad711f0c
--- /dev/null
+++ b/tests/UnboundForLoop/UnboundForLoop.log
@@ -0,0 +1,873 @@
+[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/UnboundForLoop/slpp_all/surelog.log".
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<134> s<133> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<41> s<3> l<1:1> el<1:7>
+n<signed_shifter> u<3> t<StringConst> p<41> s<40> l<1:8> el<1:22>
+n<> u<4> t<PortDir_Inp> p<18> s<17> l<2:3> el<2:8>
+n<> u<5> t<NetType_Wire> p<17> s<16> l<2:9> el<2:13>
+n<1> u<6> t<IntConst> p<7> l<2:15> el<2:16>
+n<> u<7> t<Primary_literal> p<8> c<6> l<2:15> el<2:16>
+n<> u<8> t<Constant_primary> p<9> c<7> l<2:15> el<2:16>
+n<> u<9> t<Constant_expression> p<14> c<8> s<13> l<2:15> el<2:16>
+n<0> u<10> t<IntConst> p<11> l<2:17> el<2:18>
+n<> u<11> t<Primary_literal> p<12> c<10> l<2:17> el<2:18>
+n<> u<12> t<Constant_primary> p<13> c<11> l<2:17> el<2:18>
+n<> u<13> t<Constant_expression> p<14> c<12> l<2:17> el<2:18>
+n<> u<14> t<Constant_range> p<15> c<9> l<2:15> el<2:18>
+n<> u<15> t<Packed_dimension> p<16> c<14> l<2:14> el<2:19>
+n<> u<16> t<Data_type_or_implicit> p<17> c<15> l<2:14> el<2:19>
+n<> u<17> t<Net_port_type> p<18> c<5> l<2:9> el<2:19>
+n<> u<18> t<Net_port_header> p<20> c<4> s<19> l<2:3> el<2:19>
+n<i> u<19> t<StringConst> p<20> l<2:20> el<2:21>
+n<> u<20> t<Ansi_port_declaration> p<40> c<18> s<39> l<2:3> el<2:21>
+n<> u<21> t<PortDir_Out> p<37> s<36> l<3:3> el<3:9>
+n<> u<22> t<IntVec_TypeReg> p<34> s<23> l<3:10> el<3:13>
+n<> u<23> t<Signing_Signed> p<34> s<33> l<3:14> el<3:20>
+n<3> u<24> t<IntConst> p<25> l<3:22> el<3:23>
+n<> u<25> t<Primary_literal> p<26> c<24> l<3:22> el<3:23>
+n<> u<26> t<Constant_primary> p<27> c<25> l<3:22> el<3:23>
+n<> u<27> t<Constant_expression> p<32> c<26> s<31> l<3:22> el<3:23>
+n<0> u<28> t<IntConst> p<29> l<3:24> el<3:25>
+n<> u<29> t<Primary_literal> p<30> c<28> l<3:24> el<3:25>
+n<> u<30> t<Constant_primary> p<31> c<29> l<3:24> el<3:25>
+n<> u<31> t<Constant_expression> p<32> c<30> l<3:24> el<3:25>
+n<> u<32> t<Constant_range> p<33> c<27> l<3:22> el<3:25>
+n<> u<33> t<Packed_dimension> p<34> c<32> l<3:21> el<3:26>
+n<> u<34> t<Data_type> p<35> c<22> l<3:10> el<3:26>
+n<> u<35> t<Data_type_or_implicit> p<36> c<34> l<3:10> el<3:26>
+n<> u<36> t<Net_port_type> p<37> c<35> l<3:10> el<3:26>
+n<> u<37> t<Net_port_header> p<39> c<21> s<38> l<3:3> el<3:26>
+n<Q> u<38> t<StringConst> p<39> l<3:27> el<3:28>
+n<> u<39> t<Ansi_port_declaration> p<40> c<37> l<3:3> el<3:28>
+n<> u<40> t<List_of_port_declarations> p<41> c<20> l<1:23> el<3:30>
+n<> u<41> t<Module_ansi_header> p<131> c<2> s<53> l<1:1> el<3:31>
+n<> u<42> t<IntegerAtomType_Integer> p<43> l<4:3> el<4:10>
+n<> u<43> t<Data_type> p<47> c<42> s<46> l<4:3> el<4:10>
+n<j> u<44> t<StringConst> p<45> l<4:11> el<4:12>
+n<> u<45> t<Variable_decl_assignment> p<46> c<44> l<4:11> el<4:12>
+n<> u<46> t<List_of_variable_decl_assignments> p<47> c<45> l<4:11> el<4:12>
+n<> u<47> t<Variable_declaration> p<48> c<43> l<4:3> el<4:13>
+n<> u<48> t<Data_declaration> p<49> c<47> l<4:3> el<4:13>
+n<> u<49> t<Package_or_generate_item_declaration> p<50> c<48> l<4:3> el<4:13>
+n<> u<50> t<Module_or_generate_item_declaration> p<51> c<49> l<4:3> el<4:13>
+n<> u<51> t<Module_common_item> p<52> c<50> l<4:3> el<4:13>
+n<> u<52> t<Module_or_generate_item> p<53> c<51> l<4:3> el<4:13>
+n<> u<53> t<Non_port_module_item> p<131> c<52> s<129> l<4:3> el<4:13>
+n<> u<54> t<ALWAYS> p<126> s<125> l<5:3> el<5:9>
+n<> u<55> t<Event_control> p<56> l<5:10> el<5:13>
+n<> u<56> t<Procedural_timing_control> p<123> c<55> s<122> l<5:10> el<5:13>
+n<j> u<57> t<StringConst> p<58> l<6:9> el<6:10>
+n<> u<58> t<Ps_or_hierarchical_identifier> p<61> c<57> s<60> l<6:9> el<6:10>
+n<> u<59> t<Bit_select> p<60> l<6:10> el<6:10>
+n<> u<60> t<Select> p<61> c<59> l<6:10> el<6:10>
+n<> u<61> t<Variable_lvalue> p<66> c<58> s<65> l<6:9> el<6:10>
+n<0> u<62> t<IntConst> p<63> l<6:11> el<6:12>
+n<> u<63> t<Primary_literal> p<64> c<62> l<6:11> el<6:12>
+n<> u<64> t<Primary> p<65> c<63> l<6:11> el<6:12>
+n<> u<65> t<Expression> p<66> c<64> l<6:11> el<6:12>
+n<> u<66> t<Variable_assignment> p<67> c<61> l<6:9> el<6:12>
+n<> u<67> t<List_of_variable_assignments> p<68> c<66> l<6:9> el<6:12>
+n<> u<68> t<For_initialization> p<114> c<67> s<78> l<6:9> el<6:12>
+n<j> u<69> t<StringConst> p<70> l<6:13> el<6:14>
+n<> u<70> t<Primary_literal> p<71> c<69> l<6:13> el<6:14>
+n<> u<71> t<Primary> p<72> c<70> l<6:13> el<6:14>
+n<> u<72> t<Expression> p<78> c<71> s<77> l<6:13> el<6:14>
+n<i> u<73> t<StringConst> p<74> l<6:15> el<6:16>
+n<> u<74> t<Primary_literal> p<75> c<73> l<6:15> el<6:16>
+n<> u<75> t<Primary> p<76> c<74> l<6:15> el<6:16>
+n<> u<76> t<Expression> p<78> c<75> l<6:15> el<6:16>
+n<> u<77> t<BinOp_Less> p<78> s<76> l<6:14> el<6:15>
+n<> u<78> t<Expression> p<114> c<72> s<97> l<6:13> el<6:16>
+n<j> u<79> t<StringConst> p<80> l<6:17> el<6:18>
+n<> u<80> t<Ps_or_hierarchical_identifier> p<83> c<79> s<82> l<6:17> el<6:18>
+n<> u<81> t<Bit_select> p<82> l<6:18> el<6:18>
+n<> u<82> t<Select> p<83> c<81> l<6:18> el<6:18>
+n<> u<83> t<Variable_lvalue> p<95> c<80> s<84> l<6:17> el<6:18>
+n<> u<84> t<AssignOp_Assign> p<95> s<94> l<6:18> el<6:19>
+n<j> u<85> t<StringConst> p<86> l<6:19> el<6:20>
+n<> u<86> t<Primary_literal> p<87> c<85> l<6:19> el<6:20>
+n<> u<87> t<Primary> p<88> c<86> l<6:19> el<6:20>
+n<> u<88> t<Expression> p<94> c<87> s<93> l<6:19> el<6:20>
+n<1> u<89> t<IntConst> p<90> l<6:21> el<6:22>
+n<> u<90> t<Primary_literal> p<91> c<89> l<6:21> el<6:22>
+n<> u<91> t<Primary> p<92> c<90> l<6:21> el<6:22>
+n<> u<92> t<Expression> p<94> c<91> l<6:21> el<6:22>
+n<> u<93> t<BinOp_Plus> p<94> s<92> l<6:20> el<6:21>
+n<> u<94> t<Expression> p<95> c<88> l<6:19> el<6:22>
+n<> u<95> t<Operator_assignment> p<96> c<83> l<6:17> el<6:22>
+n<> u<96> t<For_step_assignment> p<97> c<95> l<6:17> el<6:22>
+n<> u<97> t<For_step> p<114> c<96> s<112> l<6:17> el<6:22>
+n<Q> u<98> t<StringConst> p<99> l<6:24> el<6:25>
+n<> u<99> t<Ps_or_hierarchical_identifier> p<102> c<98> s<101> l<6:24> el<6:25>
+n<> u<100> t<Bit_select> p<101> l<6:26> el<6:26>
+n<> u<101> t<Select> p<102> c<100> l<6:26> el<6:26>
+n<> u<102> t<Variable_lvalue> p<108> c<99> s<103> l<6:24> el<6:25>
+n<> u<103> t<AssignOp_Assign> p<108> s<107> l<6:26> el<6:27>
+n<> u<104> t<Number_1Tickb1> p<105> l<6:28> el<6:32>
+n<> u<105> t<Primary_literal> p<106> c<104> l<6:28> el<6:32>
+n<> u<106> t<Primary> p<107> c<105> l<6:28> el<6:32>
+n<> u<107> t<Expression> p<108> c<106> l<6:28> el<6:32>
+n<> u<108> t<Operator_assignment> p<109> c<102> l<6:24> el<6:32>
+n<> u<109> t<Blocking_assignment> p<110> c<108> l<6:24> el<6:32>
+n<> u<110> t<Statement_item> p<111> c<109> l<6:24> el<6:33>
+n<> u<111> t<Statement> p<112> c<110> l<6:24> el<6:33>
+n<> u<112> t<Statement_or_null> p<114> c<111> l<6:24> el<6:33>
+n<> u<113> t<FOR> p<114> s<68> l<6:5> el<6:8>
+n<> u<114> t<Loop_statement> p<115> c<113> l<6:5> el<6:33>
+n<> u<115> t<Statement_item> p<116> c<114> l<6:5> el<6:33>
+n<> u<116> t<Statement> p<117> c<115> l<6:5> el<6:33>
+n<> u<117> t<Statement_or_null> p<119> c<116> s<118> l<6:5> el<6:33>
+n<> u<118> t<END> p<119> l<7:3> el<7:6>
+n<> u<119> t<Seq_block> p<120> c<117> l<5:14> el<7:6>
+n<> u<120> t<Statement_item> p<121> c<119> l<5:14> el<7:6>
+n<> u<121> t<Statement> p<122> c<120> l<5:14> el<7:6>
+n<> u<122> t<Statement_or_null> p<123> c<121> l<5:14> el<7:6>
+n<> u<123> t<Procedural_timing_control_statement> p<124> c<56> l<5:10> el<7:6>
+n<> u<124> t<Statement_item> p<125> c<123> l<5:10> el<7:6>
+n<> u<125> t<Statement> p<126> c<124> l<5:10> el<7:6>
+n<> u<126> t<Always_construct> p<127> c<54> l<5:3> el<7:6>
+n<> u<127> t<Module_common_item> p<128> c<126> l<5:3> el<7:6>
+n<> u<128> t<Module_or_generate_item> p<129> c<127> l<5:3> el<7:6>
+n<> u<129> t<Non_port_module_item> p<131> c<128> s<130> l<5:3> el<7:6>
+n<> u<130> t<ENDMODULE> p<131> l<8:1> el<8:10>
+n<> u<131> t<Module_declaration> p<132> c<41> l<1:1> el<8:10>
+n<> u<132> t<Description> p<133> c<131> l<1:1> el<8:10>
+n<> u<133> t<Source_text> p<134> c<132> l<1:1> el<8:10>
+n<> u<134> t<Top_level_rule> c<1> l<1:1> el<10:1>
+AST_DEBUG_END
+[INF:CP0300] Compilation...
+[INF:CP0303] ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv:1:1: Compile module "work@signed_shifter".
+[INF:EL0526] Design Elaboration...
+[NTE:EL0503] ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv:1:1: Top level module "work@signed_shifter".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 1.
+[NTE:EL0510] Nb instances: 1.
+[NTE:EL0511] Nb leaf instances: 0.
+[INF:UH0706] Creating UHDM Model...
+=== UHDM Object Stats Begin (Non-Elaborated Model) ===
+always                                                 1
+assignment                                             3
+begin                                                  1
+constant                                              19
+design                                                 1
+event_control                                          1
+for_stmt                                               1
+integer_typespec                                       2
+integer_var                                            1
+logic_net                                              5
+logic_typespec                                         6
+module_inst                                            3
+operation                                              2
+port                                                   4
+range                                                  8
+ref_obj                                                9
+ref_typespec                                           8
+ref_var                                                1
+=== UHDM Object Stats End ===
+[INF:UH0707] Elaborating UHDM...
+=== UHDM Object Stats Begin (Elaborated Model) ===
+always                                                 2
+assignment                                             6
+begin                                                  2
+constant                                              19
+design                                                 1
+event_control                                          2
+for_stmt                                               2
+integer_typespec                                       2
+integer_var                                            1
+logic_net                                              5
+logic_typespec                                         6
+module_inst                                            3
+operation                                              4
+port                                                   6
+range                                                  8
+ref_obj                                               16
+ref_typespec                                          10
+ref_var                                                2
+=== UHDM Object Stats End ===
+[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/UnboundForLoop/slpp_all/surelog.uhdm ...
+[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/UnboundForLoop/slpp_all/checker/surelog.chk.html ...
+[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/UnboundForLoop/slpp_all/surelog.uhdm ...
+[INF:UH0711] Decompiling UHDM...
+====== UHDM =======
+design: (work@signed_shifter)
+|vpiElaborated:1
+|vpiName:work@signed_shifter
+|uhdmallModules:
+\_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+  |vpiParent:
+  \_design: (work@signed_shifter)
+  |vpiFullName:work@signed_shifter
+  |vpiDefName:work@signed_shifter
+  |vpiNet:
+  \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiName:i
+    |vpiFullName:work@signed_shifter.i
+    |vpiNetType:1
+  |vpiNet:
+  \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiName:Q
+    |vpiFullName:work@signed_shifter.Q
+    |vpiNetType:48
+  |vpiNet:
+  \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiTypespec:
+    \_ref_typespec: (work@signed_shifter.j)
+      |vpiParent:
+      \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
+      |vpiFullName:work@signed_shifter.j
+      |vpiActual:
+      \_integer_typespec: , line:4:3, endln:4:10
+    |vpiName:j
+    |vpiFullName:work@signed_shifter.j
+  |vpiPort:
+  \_port: (i), line:2:20, endln:2:21
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiName:i
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@signed_shifter.i.i), line:2:20, endln:2:21
+      |vpiParent:
+      \_port: (i), line:2:20, endln:2:21
+      |vpiName:i
+      |vpiFullName:work@signed_shifter.i.i
+      |vpiActual:
+      \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+    |vpiTypedef:
+    \_ref_typespec: (work@signed_shifter.i)
+      |vpiParent:
+      \_port: (i), line:2:20, endln:2:21
+      |vpiFullName:work@signed_shifter.i
+      |vpiActual:
+      \_logic_typespec: , line:2:9, endln:2:19
+  |vpiPort:
+  \_port: (Q), line:3:27, endln:3:28
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiName:Q
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@signed_shifter.Q.Q), line:3:27, endln:3:28
+      |vpiParent:
+      \_port: (Q), line:3:27, endln:3:28
+      |vpiName:Q
+      |vpiFullName:work@signed_shifter.Q.Q
+      |vpiActual:
+      \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+    |vpiTypedef:
+    \_ref_typespec: (work@signed_shifter.Q)
+      |vpiParent:
+      \_port: (Q), line:3:27, endln:3:28
+      |vpiFullName:work@signed_shifter.Q
+      |vpiActual:
+      \_logic_typespec: , line:3:10, endln:3:26
+  |vpiProcess:
+  \_always: , line:5:3, endln:7:6
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiStmt:
+    \_event_control: , line:5:10, endln:5:13
+      |vpiParent:
+      \_always: , line:5:3, endln:7:6
+      |vpiStmt:
+      \_begin: (work@signed_shifter), line:5:14, endln:7:6
+        |vpiParent:
+        \_event_control: , line:5:10, endln:5:13
+        |vpiFullName:work@signed_shifter
+        |vpiStmt:
+        \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+          |vpiParent:
+          \_begin: (work@signed_shifter), line:5:14, endln:7:6
+          |vpiFullName:work@signed_shifter
+          |vpiForInitStmt:
+          \_assignment: , line:6:9, endln:6:12
+            |vpiParent:
+            \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+            |vpiRhs:
+            \_constant: , line:6:11, endln:6:12
+              |vpiParent:
+              \_assignment: , line:6:9, endln:6:12
+              |vpiDecompile:0
+              |vpiSize:64
+              |UINT:0
+              |vpiConstType:9
+            |vpiLhs:
+            \_ref_var: (work@signed_shifter.j), line:6:9, endln:6:10
+              |vpiParent:
+              \_assignment: , line:6:9, endln:6:12
+              |vpiName:j
+              |vpiFullName:work@signed_shifter.j
+          |vpiForIncStmt:
+          \_assignment: , line:6:17, endln:6:22
+            |vpiParent:
+            \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_operation: , line:6:19, endln:6:22
+              |vpiParent:
+              \_assignment: , line:6:17, endln:6:22
+              |vpiOpType:24
+              |vpiOperand:
+              \_ref_obj: (work@signed_shifter.j), line:6:19, endln:6:20
+                |vpiParent:
+                \_operation: , line:6:19, endln:6:22
+                |vpiName:j
+                |vpiFullName:work@signed_shifter.j
+                |vpiActual:
+                \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
+              |vpiOperand:
+              \_constant: , line:6:21, endln:6:22
+                |vpiParent:
+                \_operation: , line:6:19, endln:6:22
+                |vpiDecompile:1
+                |vpiSize:64
+                |UINT:1
+                |vpiConstType:9
+            |vpiLhs:
+            \_ref_obj: (work@signed_shifter.j), line:6:17, endln:6:18
+              |vpiParent:
+              \_assignment: , line:6:17, endln:6:22
+              |vpiName:j
+              |vpiFullName:work@signed_shifter.j
+              |vpiActual:
+              \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
+          |vpiCondition:
+          \_operation: , line:6:13, endln:6:16
+            |vpiParent:
+            \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+            |vpiOpType:20
+            |vpiOperand:
+            \_ref_obj: (work@signed_shifter.j), line:6:13, endln:6:14
+              |vpiParent:
+              \_operation: , line:6:13, endln:6:16
+              |vpiName:j
+              |vpiFullName:work@signed_shifter.j
+              |vpiActual:
+              \_logic_net: (work@signed_shifter.j), line:4:11, endln:4:12
+            |vpiOperand:
+            \_ref_obj: (work@signed_shifter.i), line:6:15, endln:6:16
+              |vpiParent:
+              \_operation: , line:6:13, endln:6:16
+              |vpiName:i
+              |vpiFullName:work@signed_shifter.i
+              |vpiActual:
+              \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+          |vpiStmt:
+          \_assignment: , line:6:24, endln:6:32
+            |vpiParent:
+            \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+            |vpiOpType:82
+            |vpiBlocking:1
+            |vpiRhs:
+            \_constant: , line:6:28, endln:6:32
+              |vpiDecompile:1'b1
+              |vpiSize:1
+              |BIN:1
+              |vpiConstType:3
+            |vpiLhs:
+            \_ref_obj: (work@signed_shifter.Q), line:6:24, endln:6:25
+              |vpiParent:
+              \_assignment: , line:6:24, endln:6:32
+              |vpiName:Q
+              |vpiFullName:work@signed_shifter.Q
+              |vpiActual:
+              \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+    |vpiAlwaysType:1
+|uhdmtopModules:
+\_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+  |vpiName:work@signed_shifter
+  |vpiVariables:
+  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiTypespec:
+    \_ref_typespec: (work@signed_shifter.j)
+      |vpiParent:
+      \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+      |vpiFullName:work@signed_shifter.j
+      |vpiActual:
+      \_integer_typespec: , line:4:3, endln:4:10
+    |vpiName:j
+    |vpiFullName:work@signed_shifter.j
+    |vpiVisibility:1
+  |vpiDefName:work@signed_shifter
+  |vpiTop:1
+  |vpiNet:
+  \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiTypespec:
+    \_ref_typespec: (work@signed_shifter.i)
+      |vpiParent:
+      \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+      |vpiFullName:work@signed_shifter.i
+      |vpiActual:
+      \_logic_typespec: , line:2:9, endln:2:19
+    |vpiName:i
+    |vpiFullName:work@signed_shifter.i
+    |vpiNetType:1
+  |vpiNet:
+  \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiTypespec:
+    \_ref_typespec: (work@signed_shifter.Q)
+      |vpiParent:
+      \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+      |vpiFullName:work@signed_shifter.Q
+      |vpiActual:
+      \_logic_typespec: , line:3:10, endln:3:26
+    |vpiName:Q
+    |vpiFullName:work@signed_shifter.Q
+    |vpiNetType:48
+    |vpiSigned:1
+  |vpiTopModule:1
+  |vpiPort:
+  \_port: (i), line:2:20, endln:2:21
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiName:i
+    |vpiDirection:1
+    |vpiLowConn:
+    \_ref_obj: (work@signed_shifter.i), line:2:20, endln:2:21
+      |vpiParent:
+      \_port: (i), line:2:20, endln:2:21
+      |vpiName:i
+      |vpiFullName:work@signed_shifter.i
+      |vpiActual:
+      \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+    |vpiTypedef:
+    \_ref_typespec: (work@signed_shifter.i)
+      |vpiParent:
+      \_port: (i), line:2:20, endln:2:21
+      |vpiFullName:work@signed_shifter.i
+      |vpiActual:
+      \_logic_typespec: , line:2:9, endln:2:19
+    |vpiInstance:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+  |vpiPort:
+  \_port: (Q), line:3:27, endln:3:28
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiName:Q
+    |vpiDirection:2
+    |vpiLowConn:
+    \_ref_obj: (work@signed_shifter.Q), line:3:27, endln:3:28
+      |vpiParent:
+      \_port: (Q), line:3:27, endln:3:28
+      |vpiName:Q
+      |vpiFullName:work@signed_shifter.Q
+      |vpiActual:
+      \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+    |vpiTypedef:
+    \_ref_typespec: (work@signed_shifter.Q)
+      |vpiParent:
+      \_port: (Q), line:3:27, endln:3:28
+      |vpiFullName:work@signed_shifter.Q
+      |vpiActual:
+      \_logic_typespec: , line:3:10, endln:3:26
+    |vpiInstance:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+  |vpiProcess:
+  \_always: , line:5:3, endln:7:6
+    |vpiParent:
+    \_module_inst: work@signed_shifter (work@signed_shifter), file:${SURELOG_DIR}/tests/UnboundForLoop/dut.sv, line:1:1, endln:8:10
+    |vpiStmt:
+    \_event_control: , line:5:10, endln:5:13
+      |vpiParent:
+      \_always: , line:5:3, endln:7:6
+      |vpiStmt:
+      \_begin: (work@signed_shifter), line:5:14, endln:7:6
+        |vpiParent:
+        \_event_control: , line:5:10, endln:5:13
+        |vpiFullName:work@signed_shifter
+        |vpiStmt:
+        \_case_stmt: 
+          |vpiParent:
+          \_begin: (work@signed_shifter), line:5:14, endln:7:6
+          |vpiCondition:
+          \_ref_obj: (work@signed_shifter.i)
+            |vpiParent:
+            \_case_stmt: 
+            |vpiName:i
+            |vpiFullName:work@signed_shifter.i
+            |vpiActual:
+            \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+          |vpiCaseItem:
+          \_case_item: 
+            |vpiParent:
+            \_case_stmt: 
+            |vpiExpr:
+            \_constant: 
+              |vpiParent:
+              \_case_item: 
+              |vpiDecompile:0
+              |UINT:0
+              |vpiConstType:9
+            |vpiStmt:
+            \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+              |vpiParent:
+              \_case_item: 
+              |vpiFullName:work@signed_shifter
+              |vpiForInitStmt:
+              \_assignment: , line:6:9, endln:6:12
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiRhs:
+                \_constant: , line:6:11, endln:6:12
+                  |vpiParent:
+                  \_assignment: , line:6:9, endln:6:12
+                  |vpiDecompile:0
+                  |vpiSize:64
+                  |UINT:0
+                  |vpiConstType:9
+                |vpiLhs:
+                \_ref_var: (work@signed_shifter.j), line:6:9, endln:6:10
+                  |vpiParent:
+                  \_assignment: , line:6:9, endln:6:12
+                  |vpiName:j
+                  |vpiFullName:work@signed_shifter.j
+                  |vpiActual:
+                  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+              |vpiForIncStmt:
+              \_assignment: , line:6:17, endln:6:22
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiOpType:82
+                |vpiBlocking:1
+                |vpiRhs:
+                \_operation: , line:6:19, endln:6:22
+                  |vpiParent:
+                  \_assignment: , line:6:17, endln:6:22
+                  |vpiOpType:24
+                  |vpiOperand:
+                  \_ref_obj: (work@signed_shifter.j), line:6:19, endln:6:20
+                    |vpiParent:
+                    \_operation: , line:6:19, endln:6:22
+                    |vpiName:j
+                    |vpiFullName:work@signed_shifter.j
+                    |vpiActual:
+                    \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+                  |vpiOperand:
+                  \_constant: , line:6:21, endln:6:22
+                    |vpiParent:
+                    \_operation: , line:6:19, endln:6:22
+                    |vpiDecompile:1
+                    |vpiSize:64
+                    |UINT:1
+                    |vpiConstType:9
+                |vpiLhs:
+                \_ref_obj: (work@signed_shifter.j), line:6:17, endln:6:18
+                  |vpiParent:
+                  \_assignment: , line:6:17, endln:6:22
+                  |vpiName:j
+                  |vpiFullName:work@signed_shifter.j
+                  |vpiActual:
+                  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+              |vpiCondition:
+              \_operation: , line:6:13, endln:6:16
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiOpType:20
+                |vpiOperand:
+                \_ref_obj: (work@signed_shifter.j), line:6:13, endln:6:14
+                  |vpiParent:
+                  \_operation: , line:6:13, endln:6:16
+                  |vpiName:j
+                  |vpiFullName:work@signed_shifter.j
+                  |vpiActual:
+                  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+                |vpiOperand:
+                \_constant: 
+              |vpiStmt:
+              \_assignment: , line:6:24, endln:6:32
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiOpType:82
+                |vpiBlocking:1
+                |vpiRhs:
+                \_constant: , line:6:28, endln:6:32
+                  |vpiParent:
+                  \_assignment: , line:6:24, endln:6:32
+                  |vpiDecompile:1'b1
+                  |vpiSize:1
+                  |BIN:1
+                  |vpiConstType:3
+                |vpiLhs:
+                \_ref_obj: (work@signed_shifter.Q), line:6:24, endln:6:25
+                  |vpiParent:
+                  \_assignment: , line:6:24, endln:6:32
+                  |vpiName:Q
+                  |vpiFullName:work@signed_shifter.Q
+                  |vpiActual:
+                  \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+          |vpiCaseItem:
+          \_case_item: 
+            |vpiParent:
+            \_case_stmt: 
+            |vpiExpr:
+            \_constant: 
+              |vpiParent:
+              \_case_item: 
+              |vpiDecompile:1
+              |UINT:1
+              |vpiConstType:9
+            |vpiStmt:
+            \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+              |vpiParent:
+              \_case_item: 
+              |vpiFullName:work@signed_shifter
+              |vpiForInitStmt:
+              \_assignment: , line:6:9, endln:6:12
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiRhs:
+                \_constant: , line:6:11, endln:6:12
+                  |vpiParent:
+                  \_assignment: , line:6:9, endln:6:12
+                  |vpiDecompile:0
+                  |vpiSize:64
+                  |UINT:0
+                  |vpiConstType:9
+                |vpiLhs:
+                \_ref_var: (work@signed_shifter.j), line:6:9, endln:6:10
+                  |vpiParent:
+                  \_assignment: , line:6:9, endln:6:12
+                  |vpiName:j
+                  |vpiFullName:work@signed_shifter.j
+                  |vpiActual:
+                  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+              |vpiForIncStmt:
+              \_assignment: , line:6:17, endln:6:22
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiOpType:82
+                |vpiBlocking:1
+                |vpiRhs:
+                \_operation: , line:6:19, endln:6:22
+                  |vpiParent:
+                  \_assignment: , line:6:17, endln:6:22
+                  |vpiOpType:24
+                  |vpiOperand:
+                  \_ref_obj: (work@signed_shifter.j), line:6:19, endln:6:20
+                    |vpiParent:
+                    \_operation: , line:6:19, endln:6:22
+                    |vpiName:j
+                    |vpiFullName:work@signed_shifter.j
+                    |vpiActual:
+                    \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+                  |vpiOperand:
+                  \_constant: , line:6:21, endln:6:22
+                    |vpiParent:
+                    \_operation: , line:6:19, endln:6:22
+                    |vpiDecompile:1
+                    |vpiSize:64
+                    |UINT:1
+                    |vpiConstType:9
+                |vpiLhs:
+                \_ref_obj: (work@signed_shifter.j), line:6:17, endln:6:18
+                  |vpiParent:
+                  \_assignment: , line:6:17, endln:6:22
+                  |vpiName:j
+                  |vpiFullName:work@signed_shifter.j
+                  |vpiActual:
+                  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+              |vpiCondition:
+              \_operation: , line:6:13, endln:6:16
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiOpType:20
+                |vpiOperand:
+                \_ref_obj: (work@signed_shifter.j), line:6:13, endln:6:14
+                  |vpiParent:
+                  \_operation: , line:6:13, endln:6:16
+                  |vpiName:j
+                  |vpiFullName:work@signed_shifter.j
+                  |vpiActual:
+                  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+                |vpiOperand:
+                \_constant: 
+              |vpiStmt:
+              \_assignment: , line:6:24, endln:6:32
+                |vpiParent:
+                \_for_stmt: (work@signed_shifter), line:6:5, endln:6:8
+                |vpiOpType:82
+                |vpiBlocking:1
+                |vpiRhs:
+                \_constant: , line:6:28, endln:6:32
+                  |vpiParent:
+                  \_assignment: , line:6:24, endln:6:32
+                  |vpiDecompile:1'b1
+                  |vpiSize:1
+                  |BIN:1
+                  |vpiConstType:3
+                |vpiLhs:
+                \_ref_obj: (work@signed_shifter.Q), line:6:24, endln:6:25
+                  |vpiParent:
+                  \_assignment: , line:6:24, endln:6:32
+                  |vpiName:Q
+                  |vpiFullName:work@signed_shifter.Q
+                  |vpiActual:
+                  \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+    |vpiAlwaysType:1
+\_weaklyReferenced:
+\_logic_typespec: , line:2:9, endln:2:19
+  |vpiRange:
+  \_range: , line:2:14, endln:2:19
+    |vpiParent:
+    \_logic_typespec: , line:2:9, endln:2:19
+    |vpiLeftRange:
+    \_constant: , line:2:15, endln:2:16
+      |vpiParent:
+      \_range: , line:2:14, endln:2:19
+      |vpiDecompile:1
+      |vpiSize:64
+      |UINT:1
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:2:17, endln:2:18
+      |vpiParent:
+      \_range: , line:2:14, endln:2:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:3:10, endln:3:26
+  |vpiRange:
+  \_range: , line:3:21, endln:3:26
+    |vpiParent:
+    \_logic_typespec: , line:3:10, endln:3:26
+    |vpiLeftRange:
+    \_constant: , line:3:22, endln:3:23
+      |vpiParent:
+      \_range: , line:3:21, endln:3:26
+      |vpiDecompile:3
+      |vpiSize:64
+      |UINT:3
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:3:24, endln:3:25
+      |vpiParent:
+      \_range: , line:3:21, endln:3:26
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+  |vpiSigned:1
+\_logic_typespec: , line:2:9, endln:2:19
+  |vpiParent:
+  \_logic_net: (work@signed_shifter.i), line:2:20, endln:2:21
+  |vpiRange:
+  \_range: , line:2:14, endln:2:19
+    |vpiParent:
+    \_logic_typespec: , line:2:9, endln:2:19
+    |vpiLeftRange:
+    \_constant: , line:2:15, endln:2:16
+      |vpiParent:
+      \_range: , line:2:14, endln:2:19
+      |vpiDecompile:1
+      |vpiSize:64
+      |UINT:1
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:2:17, endln:2:18
+      |vpiParent:
+      \_range: , line:2:14, endln:2:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:3:10, endln:3:26
+  |vpiParent:
+  \_logic_net: (work@signed_shifter.Q), line:3:27, endln:3:28
+  |vpiRange:
+  \_range: , line:3:21, endln:3:26
+    |vpiParent:
+    \_logic_typespec: , line:3:10, endln:3:26
+    |vpiLeftRange:
+    \_constant: , line:3:22, endln:3:23
+      |vpiParent:
+      \_range: , line:3:21, endln:3:26
+      |vpiDecompile:3
+      |vpiSize:64
+      |UINT:3
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:3:24, endln:3:25
+      |vpiParent:
+      \_range: , line:3:21, endln:3:26
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+  |vpiSigned:1
+\_integer_typespec: , line:4:3, endln:4:10
+  |vpiParent:
+  \_integer_var: (work@signed_shifter.j), line:4:11, endln:4:12
+  |vpiSigned:1
+\_logic_typespec: , line:2:9, endln:2:19
+  |vpiRange:
+  \_range: , line:2:14, endln:2:19
+    |vpiParent:
+    \_logic_typespec: , line:2:9, endln:2:19
+    |vpiLeftRange:
+    \_constant: , line:2:15, endln:2:16
+      |vpiParent:
+      \_range: , line:2:14, endln:2:19
+      |vpiDecompile:1
+      |vpiSize:64
+      |UINT:1
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:2:17, endln:2:18
+      |vpiParent:
+      \_range: , line:2:14, endln:2:19
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+\_logic_typespec: , line:3:10, endln:3:26
+  |vpiRange:
+  \_range: , line:3:21, endln:3:26
+    |vpiParent:
+    \_logic_typespec: , line:3:10, endln:3:26
+    |vpiLeftRange:
+    \_constant: , line:3:22, endln:3:23
+      |vpiParent:
+      \_range: , line:3:21, endln:3:26
+      |vpiDecompile:3
+      |vpiSize:64
+      |UINT:3
+      |vpiConstType:9
+    |vpiRightRange:
+    \_constant: , line:3:24, endln:3:25
+      |vpiParent:
+      \_range: , line:3:21, endln:3:26
+      |vpiDecompile:0
+      |vpiSize:64
+      |UINT:0
+      |vpiConstType:9
+  |vpiSigned:1
+\_integer_typespec: , line:4:3, endln:4:10
+  |vpiSigned:1
+===================
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 0
+[   NOTE] : 5
+
+============================== Begin RoundTrip Results ==============================
+[roundtrip]: ${SURELOG_DIR}/tests/UnboundForLoop/dut.sv | ${SURELOG_DIR}/build/regression/UnboundForLoop/roundtrip/dut_000.sv | 4 | 8 |
+============================== End RoundTrip Results ==============================
diff --git a/tests/UnboundForLoop/UnboundForLoop.sl b/tests/UnboundForLoop/UnboundForLoop.sl
new file mode 100644
index 0000000000..4f4ff0c0f5
--- /dev/null
+++ b/tests/UnboundForLoop/UnboundForLoop.sl
@@ -0,0 +1 @@
+-parse -d uhdm -synth -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
diff --git a/tests/UnboundForLoop/dut.sv b/tests/UnboundForLoop/dut.sv
new file mode 100644
index 0000000000..563f0ae114
--- /dev/null
+++ b/tests/UnboundForLoop/dut.sv
@@ -0,0 +1,9 @@
+module signed_shifter (
+  input wire [1:0] i,
+  output reg signed [3:0] Q );
+  integer j;
+  always @ * begin
+    for(j=0;j<i;j=j+1) Q = 1'b1;
+  end
+endmodule
+
diff --git a/third_party/UHDM b/third_party/UHDM
index 8f8b824fb7..8a62e0f686 160000
--- a/third_party/UHDM
+++ b/third_party/UHDM
@@ -1 +1 @@
-Subproject commit 8f8b824fb737537025cbb59eb0b2c7b188affb34
+Subproject commit 8a62e0f686c15cd4f1c69190a82f989035bcfd75
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index 2785cb420f..324c64fb23 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -65,11 +65,11 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 -- Generating done
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 12_beh_lib.sv
-[ 18%] Generating 11_ifu_bp_ctl.sv
+[ 12%] Generating 11_ifu_bp_ctl.sv
+[ 18%] Generating 12_beh_lib.sv
 [ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 15_exu.sv
-[ 37%] Generating 14_mem_lib.sv
+[ 31%] Generating 14_mem_lib.sv
+[ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log
index d45fd37dfd..827e1abc6c 100644
--- a/third_party/tests/Scr1/Scr1.log
+++ b/third_party/tests/Scr1/Scr1.log
@@ -259,7 +259,7 @@ int_var                                               40
 integer_typespec                                      59
 integer_var                                            3
 io_decl                                               27
-logic_net                                           2985
+logic_net                                           2757
 logic_typespec                                      4195
 logic_var                                            828
 method_func_call                                       5
diff --git a/third_party/tests/Scr1SvTests/Scr1SvTests.log b/third_party/tests/Scr1SvTests/Scr1SvTests.log
index c742b6ff29..40dd7fcf08 100644
--- a/third_party/tests/Scr1SvTests/Scr1SvTests.log
+++ b/third_party/tests/Scr1SvTests/Scr1SvTests.log
@@ -191,7 +191,7 @@ int_var                                               32
 integer_typespec                                      74
 integer_var                                            3
 io_decl                                               27
-logic_net                                           3237
+logic_net                                           3006
 logic_typespec                                      4682
 logic_var                                           1058
 method_func_call                                       4