diff --git a/.vscode/launch.json b/.vscode/launch.json index 22576f8ab1..edbf06c49e 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -369,6 +369,25 @@ } ] }, + { + "name": "Rggen", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/dbuild/bin/surelog", + "args": ["-f", "Rggen.sl"], + "stopAtEntry": false, + "cwd": "${workspaceFolder}/third_party/tests/rggen", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + }, { "name": "BlackParrotOOB", "type": "cppdbg", diff --git a/tests/BitsInGenBlock/BitsInGenBlock.log b/tests/BitsInGenBlock/BitsInGenBlock.log new file mode 100644 index 0000000000..997072f7b9 --- /dev/null +++ b/tests/BitsInGenBlock/BitsInGenBlock.log @@ -0,0 +1,704 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/BitsInGenBlock/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<124> s<123> l<1:1> el<1:0> +n u<2> t p<6> s<3> l<1:1> el<1:7> +n u<3> t p<6> s<5> l<1:8> el<1:12> +n<> u<4> t p<5> l<1:13> el<1:13> +n<> u<5> t p<6> c<4> l<1:12> el<1:14> +n<> u<6> t p<8> c<2> s<7> l<1:1> el<1:15> +n<> u<7> t p<8> l<3:1> el<3:10> +n<> u<8> t p<9> c<6> l<1:1> el<3:10> +n<> u<9> t p<123> c<8> s<12> l<1:1> el<3:10> +n<> u<10> t p<11> l<3:10> el<3:11> +n<> u<11> t p<12> c<10> l<3:10> el<3:11> +n<> u<12> t p<123> c<11> s<122> l<3:10> el<3:11> +n u<13> t p<40> s<14> l<5:1> el<5:7> +n u<14> t p<40> s<39> l<5:8> el<5:16> +n<> u<15> t p<20> s<19> l<7:3> el<7:9> +n<> u<16> t p<17> l<7:10> el<7:15> +n<> u<17> t p<18> c<16> l<7:10> el<7:15> +n<> u<18> t p<19> c<17> l<7:10> el<7:15> +n<> u<19> t p<20> c<18> l<7:10> el<7:15> +n<> u<20> t p<22> c<15> s<21> l<7:3> el<7:15> +n u<21> t p<22> l<7:40> el<7:51> +n<> u<22> t p<39> c<20> s<30> l<7:3> el<7:51> +n<> u<23> t p<28> s<27> l<8:3> el<8:8> +n<> u<24> t p<25> l<8:10> el<8:15> +n<> u<25> t p<26> c<24> l<8:10> el<8:15> +n<> u<26> t p<27> c<25> l<8:10> el<8:15> +n<> u<27> t p<28> c<26> l<8:10> el<8:15> +n<> u<28> t p<30> c<23> s<29> l<8:3> el<8:15> +n u<29> t p<30> l<8:40> el<8:51> +n<> u<30> t p<39> c<28> s<38> l<8:3> el<8:51> +n<> u<31> t p<36> s<35> l<9:3> el<9:9> +n<> u<32> t p<33> l<9:10> el<9:14> +n<> u<33> t p<34> c<32> l<9:10> el<9:14> +n<> u<34> t p<35> c<33> l<9:10> el<9:14> +n<> u<35> t p<36> c<34> l<9:10> el<9:14> +n<> u<36> t p<38> c<31> s<37> l<9:3> el<9:14> +n u<37> t p<38> l<9:15> el<9:16> +n<> u<38> t p<39> c<36> l<9:3> el<9:16> +n<> u<39> t p<40> c<22> l<5:18> el<10:2> +n<> u<40> t p<121> c<13> s<119> l<5:1> el<10:3> +n<1> u<41> t p<42> l<15:7> el<15:8> +n<> u<42> t p<43> c<41> l<15:7> el<15:8> +n<> u<43> t p<44> c<42> l<15:7> el<15:8> +n<> u<44> t p<112> c<43> s<110> l<15:7> el<15:8> +n<> u<45> t p<46> l<17:16> el<17:19> +n<> u<46> t p<47> c<45> l<17:16> el<17:19> +n<> u<47> t p<74> c<46> s<73> l<17:16> el<17:19> +n u<48> t p<72> s<71> l<17:20> el<17:33> +n<> u<49> t p<67> s<50> l<17:36> el<17:37> +n u<50> t p<67> s<66> l<17:37> el<17:41> +n u<51> t p<52> l<19:7> el<19:18> +n<> u<52> t p<53> c<51> l<19:7> el<19:18> +n<> u<53> t p<54> c<52> l<19:7> el<19:18> +n<> u<54> t p<63> c<53> s<58> l<19:7> el<19:18> +n u<55> t p<56> l<20:7> el<20:18> +n<> u<56> t p<57> c<55> l<20:7> el<20:18> +n<> u<57> t p<58> c<56> l<20:7> el<20:18> +n<> u<58> t p<63> c<57> s<62> l<20:7> el<20:18> +n u<59> t p<60> l<21:7> el<21:8> +n<> u<60> t p<61> c<59> l<21:7> el<21:8> +n<> u<61> t p<62> c<60> l<21:7> el<21:8> +n<> u<62> t p<63> c<61> l<21:7> el<21:8> +n<> u<63> t p<64> c<54> l<17:42> el<22:6> +n<> u<64> t p<65> c<63> l<17:42> el<22:6> +n<> u<65> t p<66> c<64> l<17:42> el<22:6> +n<> u<66> t p<67> c<65> l<17:42> el<22:6> +n<> u<67> t p<68> c<49> l<17:36> el<22:7> +n<> u<68> t p<69> c<67> l<17:36> el<22:7> +n<> u<69> t p<70> c<68> l<17:36> el<22:7> +n<> u<70> t p<71> c<69> l<17:36> el<22:7> +n<> u<71> t p<72> c<70> l<17:36> el<22:7> +n<> u<72> t p<73> c<48> l<17:20> el<22:7> +n<> u<73> t p<74> c<72> l<17:20> el<22:7> +n<> u<74> t p<75> c<47> l<17:5> el<22:7> +n<> u<75> t p<76> c<74> l<17:5> el<22:8> +n<> u<76> t p<77> c<75> l<17:5> el<22:8> +n<> u<77> t p<78> c<76> l<17:5> el<22:8> +n<> u<78> t p<79> c<77> l<17:5> el<22:8> +n<> u<79> t p<109> c<78> s<107> l<17:5> el<22:8> +n u<80> t p<81> l<24:7> el<24:20> +n<> u<81> t p<82> c<80> l<24:7> el<24:20> +n<> u<82> t p<83> c<81> l<24:7> el<24:20> +n<> u<83> t p<89> c<82> s<88> l<24:7> el<24:20> +n<10> u<84> t p<85> l<24:24> el<24:26> +n<> u<85> t p<86> c<84> l<24:24> el<24:26> +n<> u<86> t p<87> c<85> l<24:24> el<24:26> +n<> u<87> t p<89> c<86> l<24:24> el<24:26> +n<> u<88> t p<89> s<87> l<24:21> el<24:23> +n<> u<89> t p<103> c<83> s<101> l<24:7> el<24:26> +n u<90> t p<96> s<95> l<25:6> el<25:10> +n u<91> t p<92> l<25:11> el<25:15> +n<> u<92> t p<95> c<91> s<94> l<25:11> el<25:15> +n<> u<93> t p<94> l<25:16> el<25:16> +n<> u<94> t p<95> c<93> l<25:16> el<25:16> +n<> u<95> t p<96> c<92> l<25:11> el<25:17> +n<> u<96> t p<97> c<90> l<25:6> el<25:18> +n<> u<97> t p<98> c<96> l<25:6> el<25:18> +n<> u<98> t p<100> c<97> s<99> l<25:6> el<25:18> +n<> u<99> t p<100> l<26:3> el<26:6> +n<> u<100> t p<101> c<98> l<24:28> el<26:6> +n<> u<101> t p<103> c<100> l<24:28> el<26:6> +n<> u<102> t p<103> s<89> l<24:3> el<24:5> +n<> u<103> t p<104> c<102> l<24:3> el<26:6> +n<> u<104> t p<105> c<103> l<24:3> el<26:6> +n<> u<105> t p<106> c<104> l<24:3> el<26:6> +n<> u<106> t p<107> c<105> l<24:3> el<26:6> +n<> u<107> t p<109> c<106> s<108> l<24:3> el<26:6> +n<> u<108> t p<109> l<28:1> el<28:4> +n<> u<109> t p<110> c<79> l<15:10> el<28:4> +n<> u<110> t p<112> c<109> l<15:10> el<28:4> +n<> u<111> t p<112> s<44> l<15:3> el<15:5> +n<> u<112> t p<113> c<111> l<15:3> el<28:4> +n<> u<113> t p<114> c<112> l<15:3> el<28:4> +n<> u<114> t p<115> c<113> l<15:3> el<28:4> +n<> u<115> t p<116> c<114> l<15:3> el<28:4> +n<> u<116> t p<118> c<115> s<117> l<15:3> el<28:4> +n<> u<117> t p<118> l<29:1> el<29:12> +n<> u<118> t p<119> c<116> l<14:1> el<29:12> +n<> u<119> t p<121> c<118> s<120> l<14:1> el<29:12> +n<> u<120> t p<121> l<31:1> el<31:10> +n<> u<121> t p<122> c<40> l<5:1> el<31:10> +n<> u<122> t p<123> c<121> l<5:1> el<31:10> +n<> u<123> t p<124> c<9> l<1:1> el<31:10> +n<> u<124> t c<1> l<1:1> el<32:1> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:1:1: No timescale set for "GOOD". +[WRN:PA0205] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:5:1: No timescale set for "ibex_top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:1:1: Compile module "work@GOOD". +[INF:CP0303] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:5:1: Compile module "work@ibex_top". +[INF:EL0526] Design Elaboration... +[INF:CP0335] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:17:5: Compile generate block "work@ibex_top.genblk1". +[INF:CP0335] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:25:6: Compile generate block "work@ibex_top.genblk1.genblk1". +[NTE:EL0503] ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv:5:1: Top level module "work@ibex_top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 4. +[NTE:EL0510] Nb instances: 2. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +begin 3 +byte_typespec 3 +byte_var 1 +constant 10 +design 1 +gen_if 2 +gen_region 1 +gen_scope 4 +gen_scope_array 4 +int_typespec 4 +logic_net 5 +logic_typespec 6 +module_inst 7 +operation 6 +param_assign 3 +parameter 3 +port 6 +ref_module 2 +ref_obj 19 +ref_typespec 17 +sys_func_call 1 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +begin 3 +byte_typespec 3 +byte_var 1 +constant 10 +design 1 +gen_if 2 +gen_region 1 +gen_scope 6 +gen_scope_array 6 +int_typespec 4 +logic_net 5 +logic_typespec 6 +module_inst 8 +operation 6 +param_assign 4 +parameter 3 +port 9 +ref_module 2 +ref_obj 22 +ref_typespec 22 +sys_func_call 1 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/BitsInGenBlock/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/BitsInGenBlock/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/BitsInGenBlock/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@ibex_top) +|vpiElaborated:1 +|vpiName:work@ibex_top +|uhdmallModules: +\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:1:1, endln:3:10 + |vpiParent: + \_design: (work@ibex_top) + |vpiFullName:work@GOOD + |vpiDefName:work@GOOD +|uhdmallModules: +\_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiParent: + \_design: (work@ibex_top) + |vpiFullName:work@ibex_top + |vpiDefName:work@ibex_top + |vpiNet: + \_logic_net: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:instr_req_o + |vpiFullName:work@ibex_top.instr_req_o + |vpiNetType:36 + |vpiNet: + \_logic_net: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:instr_gnt_i + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiNetType:36 + |vpiNet: + \_logic_net: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:b + |vpiFullName:work@ibex_top.b + |vpiPort: + \_port: (instr_req_o), line:7:40, endln:7:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:instr_req_o + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@ibex_top.instr_req_o.instr_req_o), line:7:40, endln:7:51 + |vpiParent: + \_port: (instr_req_o), line:7:40, endln:7:51 + |vpiName:instr_req_o + |vpiFullName:work@ibex_top.instr_req_o.instr_req_o + |vpiActual: + \_logic_net: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 + |vpiTypedef: + \_ref_typespec: (work@ibex_top.instr_req_o) + |vpiParent: + \_port: (instr_req_o), line:7:40, endln:7:51 + |vpiFullName:work@ibex_top.instr_req_o + |vpiActual: + \_logic_typespec: , line:7:10, endln:7:15 + |vpiPort: + \_port: (instr_gnt_i), line:8:40, endln:8:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:instr_gnt_i + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ibex_top.instr_gnt_i.instr_gnt_i), line:8:40, endln:8:51 + |vpiParent: + \_port: (instr_gnt_i), line:8:40, endln:8:51 + |vpiName:instr_gnt_i + |vpiFullName:work@ibex_top.instr_gnt_i.instr_gnt_i + |vpiActual: + \_logic_net: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 + |vpiTypedef: + \_ref_typespec: (work@ibex_top.instr_gnt_i) + |vpiParent: + \_port: (instr_gnt_i), line:8:40, endln:8:51 + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiActual: + \_logic_typespec: , line:8:10, endln:8:15 + |vpiPort: + \_port: (b), line:9:15, endln:9:16 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:b + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@ibex_top.b.b), line:9:15, endln:9:16 + |vpiParent: + \_port: (b), line:9:15, endln:9:16 + |vpiName:b + |vpiFullName:work@ibex_top.b.b + |vpiActual: + \_logic_net: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiTypedef: + \_ref_typespec: (work@ibex_top.b) + |vpiParent: + \_port: (b), line:9:15, endln:9:16 + |vpiFullName:work@ibex_top.b + |vpiActual: + \_byte_typespec: , line:9:10, endln:9:14 + |vpiGenStmt: + \_gen_region: + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiStmt: + \_begin: (work@ibex_top) + |vpiParent: + \_gen_region: + |vpiFullName:work@ibex_top + |vpiStmt: + \_gen_if: , line:15:3, endln:15:5 + |vpiParent: + \_begin: (work@ibex_top) + |vpiCondition: + \_constant: , line:15:7, endln:15:8 + |vpiParent: + \_gen_if: , line:15:3, endln:15:5 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiStmt: + \_begin: (work@ibex_top) + |vpiParent: + \_gen_if: , line:15:3, endln:15:5 + |vpiFullName:work@ibex_top + |vpiStmt: + \_param_assign: , line:17:20, endln:22:7 + |vpiParent: + \_begin: (work@ibex_top) + |vpiRhs: + \_sys_func_call: ($bits), line:17:36, endln:22:7 + |vpiParent: + \_param_assign: , line:17:20, endln:22:7 + |vpiArgument: + \_operation: , line:17:42, endln:22:6 + |vpiParent: + \_sys_func_call: ($bits), line:17:36, endln:22:7 + |vpiOpType:33 + |vpiOperand: + \_ref_obj: (work@ibex_top.instr_req_o), line:19:7, endln:19:18 + |vpiParent: + \_operation: , line:17:42, endln:22:6 + |vpiName:instr_req_o + |vpiFullName:work@ibex_top.instr_req_o + |vpiOperand: + \_ref_obj: (work@ibex_top.instr_gnt_i), line:20:7, endln:20:18 + |vpiParent: + \_operation: , line:17:42, endln:22:6 + |vpiName:instr_gnt_i + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiOperand: + \_ref_obj: (work@ibex_top.b), line:21:7, endln:21:8 + |vpiParent: + \_operation: , line:17:42, endln:22:6 + |vpiName:b + |vpiFullName:work@ibex_top.b + |vpiName:$bits + |vpiLhs: + \_parameter: (work@ibex_top.NumBufferBits), line:17:20, endln:22:7 + |vpiParent: + \_param_assign: , line:17:20, endln:22:7 + |vpiTypespec: + \_ref_typespec: (work@ibex_top.NumBufferBits) + |vpiParent: + \_parameter: (work@ibex_top.NumBufferBits), line:17:20, endln:22:7 + |vpiFullName:work@ibex_top.NumBufferBits + |vpiActual: + \_int_typespec: , line:17:16, endln:17:19 + |vpiLocalParam:1 + |vpiName:NumBufferBits + |vpiFullName:work@ibex_top.NumBufferBits + |vpiStmt: + \_gen_if: , line:24:3, endln:24:5 + |vpiParent: + \_begin: (work@ibex_top) + |vpiCondition: + \_operation: , line:24:7, endln:24:26 + |vpiParent: + \_gen_if: , line:24:3, endln:24:5 + |vpiOpType:14 + |vpiOperand: + \_ref_obj: (work@ibex_top.NumBufferBits), line:24:7, endln:24:20 + |vpiParent: + \_operation: , line:24:7, endln:24:26 + |vpiName:NumBufferBits + |vpiFullName:work@ibex_top.NumBufferBits + |vpiOperand: + \_constant: , line:24:24, endln:24:26 + |vpiParent: + \_operation: , line:24:7, endln:24:26 + |vpiDecompile:10 + |vpiSize:64 + |UINT:10 + |vpiConstType:9 + |vpiStmt: + \_begin: (work@ibex_top) + |vpiParent: + \_gen_if: , line:24:3, endln:24:5 + |vpiFullName:work@ibex_top + |vpiStmt: + \_ref_module: work@GOOD (good), line:25:11, endln:25:15 + |vpiParent: + \_begin: (work@ibex_top) + |vpiName:good + |vpiDefName:work@GOOD +|uhdmtopModules: +\_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:work@ibex_top + |vpiVariables: + \_byte_var: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiTypespec: + \_ref_typespec: (work@ibex_top.b) + |vpiParent: + \_byte_var: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiFullName:work@ibex_top.b + |vpiActual: + \_byte_typespec: , line:9:10, endln:9:14 + |vpiName:b + |vpiFullName:work@ibex_top.b + |vpiSigned:1 + |vpiVisibility:1 + |vpiDefName:work@ibex_top + |vpiTop:1 + |vpiNet: + \_logic_net: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiTypespec: + \_ref_typespec: (work@ibex_top.instr_req_o) + |vpiParent: + \_logic_net: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 + |vpiFullName:work@ibex_top.instr_req_o + |vpiActual: + \_logic_typespec: , line:7:10, endln:7:15 + |vpiName:instr_req_o + |vpiFullName:work@ibex_top.instr_req_o + |vpiNetType:36 + |vpiNet: + \_logic_net: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiTypespec: + \_ref_typespec: (work@ibex_top.instr_gnt_i) + |vpiParent: + \_logic_net: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiActual: + \_logic_typespec: , line:8:10, endln:8:15 + |vpiName:instr_gnt_i + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiNetType:36 + |vpiTopModule:1 + |vpiPort: + \_port: (instr_req_o), line:7:40, endln:7:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:instr_req_o + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 + |vpiParent: + \_port: (instr_req_o), line:7:40, endln:7:51 + |vpiName:instr_req_o + |vpiFullName:work@ibex_top.instr_req_o + |vpiActual: + \_logic_net: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 + |vpiTypedef: + \_ref_typespec: (work@ibex_top.instr_req_o) + |vpiParent: + \_port: (instr_req_o), line:7:40, endln:7:51 + |vpiFullName:work@ibex_top.instr_req_o + |vpiActual: + \_logic_typespec: , line:7:10, endln:7:15 + |vpiInstance: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiPort: + \_port: (instr_gnt_i), line:8:40, endln:8:51 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:instr_gnt_i + |vpiDirection:1 + |vpiLowConn: + \_ref_obj: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 + |vpiParent: + \_port: (instr_gnt_i), line:8:40, endln:8:51 + |vpiName:instr_gnt_i + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiActual: + \_logic_net: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 + |vpiTypedef: + \_ref_typespec: (work@ibex_top.instr_gnt_i) + |vpiParent: + \_port: (instr_gnt_i), line:8:40, endln:8:51 + |vpiFullName:work@ibex_top.instr_gnt_i + |vpiActual: + \_logic_typespec: , line:8:10, endln:8:15 + |vpiInstance: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiPort: + \_port: (b), line:9:15, endln:9:16 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:b + |vpiDirection:2 + |vpiLowConn: + \_ref_obj: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiParent: + \_port: (b), line:9:15, endln:9:16 + |vpiName:b + |vpiFullName:work@ibex_top.b + |vpiActual: + \_byte_var: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiTypedef: + \_ref_typespec: (work@ibex_top.b) + |vpiParent: + \_port: (b), line:9:15, endln:9:16 + |vpiFullName:work@ibex_top.b + |vpiActual: + \_byte_typespec: , line:9:10, endln:9:14 + |vpiInstance: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiGenScopeArray: + \_gen_scope_array: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:genblk1 + |vpiFullName:work@ibex_top.genblk1 + |vpiGenScope: + \_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiParent: + \_gen_scope_array: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiFullName:work@ibex_top.genblk1 + |vpiParameter: + \_parameter: (work@ibex_top.genblk1.NumBufferBits), line:17:20, endln:17:33 + |vpiParent: + \_param_assign: , line:17:20, endln:22:7 + |UINT:10 + |vpiTypespec: + \_ref_typespec: (work@ibex_top.genblk1.NumBufferBits) + |vpiParent: + \_parameter: (work@ibex_top.genblk1.NumBufferBits), line:17:20, endln:17:33 + |vpiFullName:work@ibex_top.genblk1.NumBufferBits + |vpiActual: + \_int_typespec: , line:17:16, endln:17:19 + |vpiSigned:1 + |vpiLocalParam:1 + |vpiName:NumBufferBits + |vpiFullName:work@ibex_top.genblk1.NumBufferBits + |vpiParamAssign: + \_param_assign: , line:17:20, endln:22:7 + |vpiParent: + \_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiRhs: + \_constant: , line:17:36, endln:22:7 + |vpiParent: + \_param_assign: , line:17:20, endln:22:7 + |vpiDecompile:10 + |vpiSize:32 + |UINT:10 + |vpiTypespec: + \_ref_typespec: (work@ibex_top.genblk1) + |vpiParent: + \_constant: , line:17:36, endln:22:7 + |vpiFullName:work@ibex_top.genblk1 + |vpiActual: + \_int_typespec: , line:17:16, endln:17:19 + |vpiConstType:9 + |vpiLhs: + \_parameter: (work@ibex_top.genblk1.NumBufferBits), line:17:20, endln:17:33 + |vpiGenScopeArray: + \_gen_scope_array: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiParent: + \_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiName:genblk1 + |vpiFullName:work@ibex_top.genblk1.genblk1 + |vpiGenScope: + \_gen_scope: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiParent: + \_gen_scope_array: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiFullName:work@ibex_top.genblk1.genblk1 + |vpiModule: + \_module_inst: work@GOOD (work@ibex_top.genblk1.genblk1.good), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:25:6, endln:25:18 + |vpiParent: + \_gen_scope: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiName:good + |vpiFullName:work@ibex_top.genblk1.genblk1.good + |vpiDefName:work@GOOD + |vpiDefFile:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv + |vpiDefLineNo:1 +\_weaklyReferenced: +\_int_typespec: , line:17:16, endln:17:19 + |vpiSigned:1 +\_logic_typespec: , line:7:10, endln:7:15 +\_logic_typespec: , line:8:10, endln:8:15 +\_byte_typespec: , line:9:10, endln:9:14 + |vpiSigned:1 +\_logic_typespec: , line:7:10, endln:7:15 + |vpiParent: + \_logic_net: (work@ibex_top.instr_req_o), line:7:40, endln:7:51 +\_logic_typespec: , line:8:10, endln:8:15 + |vpiParent: + \_logic_net: (work@ibex_top.instr_gnt_i), line:8:40, endln:8:51 +\_byte_typespec: , line:9:10, endln:9:14 + |vpiParent: + \_byte_var: (work@ibex_top.b), line:9:15, endln:9:16 + |vpiSigned:1 +\_int_typespec: , line:17:16, endln:17:19 + |vpiParent: + \_parameter: (NumBufferBits), line:17:20, endln:17:33 + |vpiSigned:1 +\_parameter: (NumBufferBits), line:17:20, endln:17:33 + |vpiParent: + \_param_assign: , line:17:20, endln:22:7 + |UINT:10 + |vpiTypespec: + \_ref_typespec: (NumBufferBits) + |vpiParent: + \_parameter: (NumBufferBits), line:17:20, endln:17:33 + |vpiFullName:NumBufferBits + |vpiActual: + \_int_typespec: , line:17:16, endln:17:19 + |vpiSigned:1 + |vpiLocalParam:1 + |vpiName:NumBufferBits +\_param_assign: , line:17:20, endln:22:7 + |vpiRhs: + \_constant: , line:17:36, endln:22:7 + |vpiParent: + \_param_assign: , line:17:20, endln:22:7 + |vpiDecompile:10 + |vpiSize:32 + |UINT:10 + |vpiTypespec: + \_ref_typespec: + |vpiParent: + \_constant: , line:17:36, endln:22:7 + |vpiActual: + \_int_typespec: , line:17:16, endln:17:19 + |vpiConstType:9 + |vpiLhs: + \_parameter: (NumBufferBits), line:17:20, endln:17:33 +\_param_assign: , line:17:20, endln:22:7 + |vpiParent: + \_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiRhs: + \_constant: , line:17:36, endln:22:7 + |vpiLhs: + \_parameter: (work@ibex_top.genblk1.NumBufferBits), line:17:20, endln:17:33 +\_logic_typespec: , line:7:10, endln:7:15 +\_logic_typespec: , line:8:10, endln:8:15 +\_byte_typespec: , line:9:10, endln:9:14 + |vpiSigned:1 +\_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiParent: + \_gen_scope_array: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiFullName:work@ibex_top.genblk1 + |vpiParameter: + \_parameter: (work@ibex_top.genblk1.NumBufferBits), line:17:20, endln:17:33 + |vpiParamAssign: + \_param_assign: , line:17:20, endln:22:7 + |vpiGenScopeArray: + \_gen_scope_array: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiParent: + \_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiName:genblk1 + |vpiFullName:work@ibex_top.genblk1.genblk1 + |vpiGenScope: + \_gen_scope: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiParent: + \_gen_scope_array: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiFullName:work@ibex_top.genblk1.genblk1 + |vpiModule: + \_module_inst: work@GOOD (work@ibex_top.genblk1.genblk1.good), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:25:6, endln:25:18 + |vpiParent: + \_gen_scope: (work@ibex_top.genblk1.genblk1), line:25:6, endln:25:18 + |vpiName:good + |vpiFullName:work@ibex_top.genblk1.genblk1.good + |vpiDefName:work@GOOD + |vpiDefFile:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv + |vpiDefLineNo:1 +\_gen_scope_array: (work@ibex_top.genblk1), line:17:5, endln:22:8 + |vpiParent: + \_module_inst: work@ibex_top (work@ibex_top), file:${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv, line:5:1, endln:31:10 + |vpiName:genblk1 + |vpiFullName:work@ibex_top.genblk1 + |vpiGenScope: + \_gen_scope: (work@ibex_top.genblk1), line:17:5, endln:22:8 +\_int_typespec: , line:17:16, endln:17:19 + |vpiParent: + \_ref_typespec: (work@ibex_top.genblk1.NumBufferBits) + |vpiSigned:1 +\_ref_typespec: (work@ibex_top.genblk1.NumBufferBits) + |vpiParent: + \_parameter: (work@ibex_top.genblk1.NumBufferBits), line:17:20, endln:17:33 + |vpiFullName:work@ibex_top.genblk1.NumBufferBits + |vpiActual: + \_int_typespec: , line:17:16, endln:17:19 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 2 +[ NOTE] : 5 + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/BitsInGenBlock/dut.sv | ${SURELOG_DIR}/build/regression/BitsInGenBlock/roundtrip/dut_000.sv | 11 | 31 | +============================== End RoundTrip Results ============================== diff --git a/tests/BitsInGenBlock/BitsInGenBlock.sl b/tests/BitsInGenBlock/BitsInGenBlock.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/BitsInGenBlock/BitsInGenBlock.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/BitsInGenBlock/dut.sv b/tests/BitsInGenBlock/dut.sv new file mode 100644 index 0000000000..09eeb3de66 --- /dev/null +++ b/tests/BitsInGenBlock/dut.sv @@ -0,0 +1,31 @@ +module GOOD(); + +endmodule; // GOOD + +module ibex_top ( + + output logic instr_req_o, + input logic instr_gnt_i, + output byte b +); + + + +generate + if (1) begin + + localparam int NumBufferBits = $bits({ + + instr_req_o, // 1 bit + instr_gnt_i, // 1 bit + b // 8 bits + }); + + if (NumBufferBits == 10) begin + GOOD good(); + end + +end +endgenerate + +endmodule diff --git a/tests/HighLow/HighLow.log b/tests/HighLow/HighLow.log index 7fbabb2ed3..cc4aac4022 100644 --- a/tests/HighLow/HighLow.log +++ b/tests/HighLow/HighLow.log @@ -298,7 +298,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === begin 4 -constant 42 +constant 41 cont_assign 2 design 1 gen_if 4 @@ -320,7 +320,7 @@ sys_func_call 10 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === begin 4 -constant 42 +constant 41 cont_assign 3 design 1 gen_if 4 @@ -866,10 +866,7 @@ design: (work@top) \_constant: |vpiParent: \_cont_assign: , line:12:10, endln:12:24 - |vpiDecompile:2 - |vpiSize:64 |UINT:2 - |vpiConstType:9 |vpiLhs: \_ref_obj: (work@top.ccc), line:12:10, endln:12:13 |vpiParent: @@ -1064,7 +1061,6 @@ design: (work@top) \_logic_typespec: |vpiLeftRange: \_constant: - |UINT:2 |vpiRightRange: \_constant: |UINT:1 diff --git a/third_party/UHDM b/third_party/UHDM index af8bb5e7b4..e86ba8acac 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit af8bb5e7b456811d64a7bc647d52410b66a953ca +Subproject commit e86ba8acac8e3053e1238560c56dc62299956303 diff --git a/third_party/tests/AzadiRTL/AzadiRTL.log b/third_party/tests/AzadiRTL/AzadiRTL.log index 23700df356..6cb2ff3e0f 100644 --- a/third_party/tests/AzadiRTL/AzadiRTL.log +++ b/third_party/tests/AzadiRTL/AzadiRTL.log @@ -13904,7 +13904,7 @@ case_stmt 316 class_defn 8 class_typespec 4 class_var 3 -constant 275929 +constant 275928 cont_assign 15432 delay_control 8 design 1 diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 324c64fb23..f1702aa3c1 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -64,20 +64,20 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 10_lsu_bus_intf.sv -[ 12%] Generating 11_ifu_bp_ctl.sv +[ 6%] Generating 15_exu.sv +[ 12%] Generating 14_mem_lib.sv [ 18%] Generating 12_beh_lib.sv [ 25%] Generating 13_ifu_mem_ctl.sv -[ 31%] Generating 14_mem_lib.sv -[ 37%] Generating 15_exu.sv +[ 31%] Generating 1_lsu_stbuf.sv +[ 37%] Generating 11_ifu_bp_ctl.sv [ 43%] Generating 16_dec_decode_ctl.sv -[ 50%] Generating 1_lsu_stbuf.sv +[ 50%] Generating 10_lsu_bus_intf.sv [ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv [ 68%] Generating 4_dec_tlu_ctl.sv [ 75%] Generating 5_lsu_bus_buffer.sv -[ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv +[ 87%] Generating 6_dbg.sv [ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse diff --git a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log index cf7e82c869..c8c9895386 100644 --- a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log +++ b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log @@ -6244,7 +6244,7 @@ case_stmt 614 class_defn 8 class_typespec 4 class_var 3 -constant 348744 +constant 348743 cont_assign 47364 design 1 enum_const 2553 diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log index 4057564df7..206b4a86d6 100644 --- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log +++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log @@ -14390,7 +14390,7 @@ part_select 4960 port 91788 range 167931 ref_module 5040 -ref_obj 332702 +ref_obj 332695 ref_typespec 453726 ref_var 174 return_stmt 429 @@ -14399,7 +14399,7 @@ string_var 19 struct_net 571 struct_typespec 24138 struct_var 1840 -sys_func_call 500 +sys_func_call 493 tagged_pattern 33133 task 9 typespec_member 68262 @@ -14427,7 +14427,7 @@ chandle_var 14 class_defn 8 class_typespec 4 class_var 3 -constant 936087 +constant 936086 cont_assign 147474 design 1 enum_const 31258 @@ -14475,7 +14475,7 @@ part_select 22451 port 224742 range 171087 ref_module 5040 -ref_obj 1087996 +ref_obj 1087989 ref_typespec 796720 ref_var 176 return_stmt 15514 @@ -14484,7 +14484,7 @@ string_var 36 struct_net 571 struct_typespec 24138 struct_var 2418 -sys_func_call 2410 +sys_func_call 2403 tagged_pattern 33523 task 18 typespec_member 68262 diff --git a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log index 5fe26ff5bf..a8ebeb92f7 100644 --- a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log +++ b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log @@ -5905,7 +5905,7 @@ chandle_var 11 class_defn 8 class_typespec 4 class_var 3 -constant 325988 +constant 325987 cont_assign 43470 design 1 enum_const 2451 diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log index 79f7f48a05..de9629d9f1 100644 --- a/third_party/tests/IncompTitan/IncompTitan.log +++ b/third_party/tests/IncompTitan/IncompTitan.log @@ -5386,7 +5386,7 @@ property_inst 4 property_spec 479 range 75232 ref_module 2376 -ref_obj 166321 +ref_obj 166320 ref_typespec 167850 ref_var 74 return_stmt 137 @@ -5395,7 +5395,7 @@ string_typespec 10655 struct_net 147 struct_typespec 5521 struct_var 1295 -sys_func_call 2746 +sys_func_call 2745 tagged_pattern 7929 task 9 typespec_member 17886 diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index a45c208b05..b3de0063d2 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -943,14 +943,14 @@ part_select 435 port 3875 range 18477 ref_module 187 -ref_obj 33534 +ref_obj 33530 ref_typespec 138196 string_typespec 84 string_var 1 struct_net 81 struct_typespec 1093 struct_var 77 -sys_func_call 2609 +sys_func_call 2605 task 13 task_call 11 typespec_member 7460 @@ -1023,14 +1023,14 @@ part_select 1179 port 7457 range 18627 ref_module 187 -ref_obj 90442 +ref_obj 90438 ref_typespec 203147 string_typespec 84 string_var 1 struct_net 81 struct_typespec 1093 struct_var 135 -sys_func_call 3571 +sys_func_call 3567 task 26 task_call 22 typespec_member 7460 diff --git a/third_party/tests/Opentitan/Earlgrey.log b/third_party/tests/Opentitan/Earlgrey.log index 7a751ab1b1..af0ebb9d55 100644 --- a/third_party/tests/Opentitan/Earlgrey.log +++ b/third_party/tests/Opentitan/Earlgrey.log @@ -25248,7 +25248,7 @@ case_stmt 336 class_defn 8 class_typespec 4 class_var 3 -constant 217425 +constant 217424 cont_assign 30746 design 1 enum_const 2021 diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log index 6237eab598..af910a861b 100644 --- a/third_party/tests/Opentitan/Opentitan.log +++ b/third_party/tests/Opentitan/Opentitan.log @@ -4307,7 +4307,7 @@ chandle_var 2 class_defn 613 class_typespec 8828 class_var 22226 -constant 252355 +constant 252354 constraint 10 cont_assign 30814 continue_stmt 173