From 82890582b9080214c7434105088278acdb407ef7 Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain.dargelas@gmail.com>
Date: Fri, 12 Jan 2024 20:30:58 -0800
Subject: [PATCH] file and package level const pushing in synth mode

---
 src/DesignCompile/CompileHelper.cpp             |  7 ++++++-
 third_party/tests/CoresSweRVMP/CoresSweRVMP.log | 12 ++++++------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp
index acd8e2930c..94ff787376 100644
--- a/src/DesignCompile/CompileHelper.cpp
+++ b/src/DesignCompile/CompileHelper.cpp
@@ -3554,7 +3554,12 @@ bool CompileHelper::compileParameterDeclaration(
           NodeId pattAssign = fC->sl_collect(
               actual_value, VObjectType::paConstant_concatenation);
           if (pattAssign != InvalidNodeId) {
-            isMultiDimension = true;
+            if (!compileDesign->getCompiler()
+                     ->getCommandLineParser()
+                     ->reportNonSynthesizable()) {
+              // More constant pushing with Synth option on
+              isMultiDimension = true;
+            }
           }
         }
         UHDM::any* expr = compileExpression(
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index a764175951..41e3c4fafd 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -69,17 +69,17 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 [ 18%] Generating 12_beh_lib.sv
 [ 25%] Generating 13_ifu_mem_ctl.sv
 [ 31%] Generating 14_mem_lib.sv
-[ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
+[ 43%] Generating 15_exu.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
-[ 62%] Generating 4_dec_tlu_ctl.sv
-[ 68%] Generating 3_rvjtag_tap.sv
+[ 62%] Generating 3_rvjtag_tap.sv
+[ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
-[ 81%] Generating 6_dbg.sv
-[ 87%] Generating 7_axi4_to_ahb.sv
-[ 93%] Generating 8_ifu_aln_ctl.sv
+[ 81%] Generating 7_axi4_to_ahb.sv
+[ 87%] Generating 6_dbg.sv
 [100%] Generating 9_tb_top.sv
+[100%] Generating 8_ifu_aln_ctl.sv
 [100%] Built target Parse
 Surelog parsing status: 0
 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".