diff --git a/.github/workflows/non_vendored.yml b/.github/workflows/non_vendored.yml index fdbf73e66c..e1dfaad3c1 100644 --- a/.github/workflows/non_vendored.yml +++ b/.github/workflows/non_vendored.yml @@ -58,7 +58,7 @@ jobs: cmake -B build -DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_STANDARD=17 -DCMAKE_POSITION_INDEPENDENT_CODE=ON -DJSON_BuildTests=OFF . && cmake --build build && sudo cmake --install build popd - git clone --depth 1 --branch v1.78 https://github.com/chipsalliance/UHDM.git + git clone --depth 1 --branch v1.79 https://github.com/chipsalliance/UHDM.git pushd UHDM cmake -B build -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DUHDM_USE_HOST_GTEST=ON -DUHDM_USE_HOST_CAPNP=ON . && cmake --build build && sudo cmake --install build popd diff --git a/.gitmodules b/.gitmodules index b7a7bc3508..0c36456336 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,7 +7,7 @@ [submodule "third_party/UHDM"] path = third_party/UHDM url = https://github.com/chipsalliance/UHDM.git - branch = v1.78 + branch = v1.79 [submodule "third_party/antlr4"] path = third_party/antlr4 url = https://github.com/antlr/antlr4.git diff --git a/.vscode/launch.json b/.vscode/launch.json index 3f2be90596..22576f8ab1 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -545,6 +545,25 @@ } ] }, + { + "name": "SimpleVMM", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/dbuild/bin/surelog", + "args": ["top.v", "-parse", "-sverilog", "-verbose", "-fileunit", "+incdir+../../UVM/ovm-2.1.2/src/", "+incdir+../../UVM/vmm-1.1.1a/sv"], + "stopAtEntry": false, + "cwd": "${workspaceFolder}/third_party/tests/SimpleVMM/", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + }, { "name": "TestBatchMode", "type": "cppdbg", diff --git a/CMakeLists.txt b/CMakeLists.txt index 034eb1ae33..fa509fbe66 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR) # Version changes whenever some new features accumulated, or the # grammar or the cache format changes to make sure caches # are invalidated. -project(SURELOG VERSION 1.78) +project(SURELOG VERSION 1.79) # Detect build type, fallback to release and throw a warning if use didn't # specify any diff --git a/src/DesignCompile/CompileAssertion.cpp b/src/DesignCompile/CompileAssertion.cpp index 0f049858be..82a03f8484 100644 --- a/src/DesignCompile/CompileAssertion.cpp +++ b/src/DesignCompile/CompileAssertion.cpp @@ -475,7 +475,7 @@ UHDM::property_decl* CompileHelper::compilePropertyDeclaration( compileDesign, Reduce::No, pstmt, instance); if (varst) { for (auto v : *varst) { - if (UHDM::assign_stmt* vast = any_cast(v)) { + if (UHDM::assignment* vast = any_cast(v)) { if (UHDM::variables* va = any_cast(vast->Lhs())) { vars->push_back(va); } diff --git a/src/DesignCompile/CompileGenStmt.cpp b/src/DesignCompile/CompileGenStmt.cpp index 04a3491608..0d8c65175d 100644 --- a/src/DesignCompile/CompileGenStmt.cpp +++ b/src/DesignCompile/CompileGenStmt.cpp @@ -308,7 +308,7 @@ UHDM::VectorOfgen_stmt* CompileHelper::compileGenStmt( NodeId Var = fC->Child(varInit); NodeId Expression = fC->Sibling(Var); - assign_stmt* assign_stmt = s.MakeAssign_stmt(); + assignment* assign_stmt = s.MakeAssignment(); assign_stmt->VpiParent(genfor); fC->populateCoreMembers(varInit, varInit, assign_stmt); if (variables* varb = (variables*)compileVariable( diff --git a/src/DesignCompile/CompileModule.cpp b/src/DesignCompile/CompileModule.cpp index 1119b4c400..6e2f97292b 100644 --- a/src/DesignCompile/CompileModule.cpp +++ b/src/DesignCompile/CompileModule.cpp @@ -37,6 +37,7 @@ // UHDM #include #include +#include #include #include #include @@ -468,7 +469,7 @@ bool CompileModule::collectUdpObjects_() { fC->populateCoreMembers(id, id, init); init->VpiParent(defn); defn->Initial(init); - UHDM::assign_stmt* assign_stmt = s.MakeAssign_stmt(); + UHDM::assignment* assign_stmt = s.MakeAssignment(); init->Stmt(assign_stmt); UHDM::ref_obj* ref = s.MakeRef_obj(); ref->VpiName(fC->SymName(Identifier)); diff --git a/src/DesignCompile/CompileStmt.cpp b/src/DesignCompile/CompileStmt.cpp index 8b6ef72b5a..42fc47d5a5 100644 --- a/src/DesignCompile/CompileStmt.cpp +++ b/src/DesignCompile/CompileStmt.cpp @@ -336,11 +336,11 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component, stmt, instance, muteErrors)) { for (any* cstmt : *cstmts) { bool isDecl = false; - if (cstmt->UhdmType() == uhdmassign_stmt) { - assign_stmt* assign = (assign_stmt*)cstmt; + if (cstmt->UhdmType() == uhdmassignment) { + assignment* assign = (assignment*)cstmt; if (assign->Rhs() == nullptr) { isDecl = true; - ((variables*)assign->Lhs())->VpiParent(stmt); + if (assign->Lhs()) ((variables*)assign->Lhs())->VpiParent(stmt); } } else if (cstmt->UhdmType() == uhdmsequence_decl) { VectorOfsequence_decl* decls = scope->Sequence_decls(); @@ -418,8 +418,8 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component, stmt, instance, muteErrors)) { for (any* cstmt : *cstmts) { bool isDecl = false; - if (cstmt->UhdmType() == uhdmassign_stmt) { - assign_stmt* assign = (assign_stmt*)cstmt; + if (cstmt->UhdmType() == uhdmassignment) { + assignment* assign = (assignment*)cstmt; if (assign->Rhs() == nullptr) { VectorOfvariables* vars = scope->Variables(); if (vars == nullptr) { @@ -427,8 +427,10 @@ VectorOfany* CompileHelper::compileStmt(DesignComponent* component, vars = s.MakeVariablesVec(); scope->Variables(vars); } - vars->push_back((UHDM::variables*)assign->Lhs()); - ((variables*)assign->Lhs())->VpiParent(stmt); + if (assign->Lhs()) { + vars->push_back((UHDM::variables*)assign->Lhs()); + ((variables*)assign->Lhs())->VpiParent(stmt); + } } } if (!isDecl) { @@ -1241,7 +1243,9 @@ VectorOfany* CompileHelper::compileDataDeclaration( if (results == nullptr) { results = s.MakeAnyVec(); } - assign_stmt* assign_stmt = s.MakeAssign_stmt(); + assignment* assign_stmt = s.MakeAssignment(); + assign_stmt->VpiOpType(vpiAssignmentOp); + assign_stmt->VpiBlocking(true); if (var) { var->VpiParent(assign_stmt); assign_stmt->Lhs(var); @@ -2064,8 +2068,9 @@ bool CompileHelper::compileTask(DesignComponent* component, } if (param_assign* pst = any_cast(st)) param_assigns->push_back(pst); - } else if (stmt_type == uhdmassign_stmt) { - assign_stmt* stmt = (assign_stmt*)st; + } + if (stmt_type == uhdmassignment) { + assignment* stmt = (assignment*)st; if (stmt->Rhs() == nullptr || any_cast((expr*)stmt->Lhs())) { // Declaration @@ -2074,11 +2079,12 @@ bool CompileHelper::compileTask(DesignComponent* component, task->Variables(s.MakeVariablesVec()); vars = task->Variables(); } - vars->push_back((variables*)stmt->Lhs()); + if (stmt->Lhs()) vars->push_back((variables*)stmt->Lhs()); if (stmt->Rhs() != nullptr) { stmts->push_back(st); } else { - any_cast((expr*)stmt->Lhs())->VpiParent(begin); + if (variables* var = any_cast((expr*)stmt->Lhs())) + var->VpiParent(begin); // s.Erase(stmt); } } else { @@ -2110,8 +2116,8 @@ bool CompileHelper::compileTask(DesignComponent* component, } if (param_assign* pst = any_cast(st)) param_assigns->push_back(pst); - } else if (stmt_type == uhdmassign_stmt) { - assign_stmt* stmt = (assign_stmt*)st; + } else if (stmt_type == uhdmassignment) { + assignment* stmt = (assignment*)st; if (stmt->Rhs() == nullptr || any_cast((expr*)stmt->Lhs())) { // Declaration @@ -2120,11 +2126,12 @@ bool CompileHelper::compileTask(DesignComponent* component, task->Variables(s.MakeVariablesVec()); vars = task->Variables(); } - vars->push_back((variables*)stmt->Lhs()); + if (stmt->Lhs()) vars->push_back((variables*)stmt->Lhs()); if (stmt->Rhs() != nullptr) { task->Stmt(st); } else { - any_cast((expr*)stmt->Lhs())->VpiParent(task); + if (variables* var = any_cast((expr*)stmt->Lhs())) + var->VpiParent(task); // s.Erase(stmt); } } else { @@ -2481,8 +2488,8 @@ bool CompileHelper::compileFunction(DesignComponent* component, } if (param_assign* pst = any_cast(st)) param_assigns->push_back(pst); - } else if (stmt_type == uhdmassign_stmt) { - assign_stmt* stmt = (assign_stmt*)st; + } else if (stmt_type == uhdmassignment) { + assignment* stmt = (assignment*)st; if (stmt->Rhs() == nullptr || any_cast((expr*)stmt->Lhs())) { // Declaration @@ -2491,11 +2498,12 @@ bool CompileHelper::compileFunction(DesignComponent* component, func->Variables(s.MakeVariablesVec()); vars = func->Variables(); } - vars->push_back((variables*)stmt->Lhs()); + if (stmt->Lhs()) vars->push_back((variables*)stmt->Lhs()); if (stmt->Rhs() != nullptr) { stmts->push_back(st); } else { - any_cast((expr*)stmt->Lhs())->VpiParent(begin); + if (variables* var = any_cast((expr*)stmt->Lhs())) + var->VpiParent(begin); // s.Erase(stmt); } } else { @@ -2527,8 +2535,8 @@ bool CompileHelper::compileFunction(DesignComponent* component, } if (param_assign* pst = any_cast(st)) param_assigns->push_back(pst); - } else if (stmt_type == uhdmassign_stmt) { - assign_stmt* stmt = (assign_stmt*)st; + } else if (stmt_type == uhdmassignment) { + assignment* stmt = (assignment*)st; if (stmt->Rhs() == nullptr || any_cast((expr*)stmt->Lhs())) { // Declaration @@ -2537,11 +2545,12 @@ bool CompileHelper::compileFunction(DesignComponent* component, func->Variables(s.MakeVariablesVec()); vars = func->Variables(); } - vars->push_back((variables*)stmt->Lhs()); + if (stmt->Lhs()) vars->push_back((variables*)stmt->Lhs()); if (stmt->Rhs() != nullptr) { func->Stmt(st); } else { - any_cast((expr*)stmt->Lhs())->VpiParent(func); + if (variables* var = any_cast((expr*)stmt->Lhs())) + var->VpiParent(func); // s.Erase(stmt); } } else { @@ -2837,7 +2846,7 @@ UHDM::any* CompileHelper::compileForLoop(DesignComponent* component, NodeId Data_type = fC->Child(For_variable_declaration); NodeId Var = fC->Sibling(Data_type); NodeId Expression = fC->Sibling(Var); - assign_stmt* assign_stmt = s.MakeAssign_stmt(); + assignment* assign_stmt = s.MakeAssignment(); assign_stmt->VpiParent(for_stmt); fC->populateCoreMembers(For_variable_declaration, For_variable_declaration, assign_stmt); @@ -2884,7 +2893,7 @@ UHDM::any* CompileHelper::compileForLoop(DesignComponent* component, stmts = for_stmt->VpiForInitStmts(); } - assign_stmt* assign_stmt = s.MakeAssign_stmt(); + assignment* assign_stmt = s.MakeAssignment(); assign_stmt->VpiParent(for_stmt); fC->populateCoreMembers(Variable_assignment, Variable_assignment, assign_stmt); diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index 0666e806c5..26b04ea716 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -2592,10 +2592,10 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, VectorOfany* inits = f->VpiForInitStmts(); if (inits) { for (auto init : *inits) { - if (init->UhdmType() == uhdmassign_stmt) { - assign_stmt* as = (assign_stmt*)init; + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; const expr* lhs = as->Lhs(); - if (lhs->VpiName() == name) { + if (lhs && lhs->VpiName() == name) { if (lhs->UhdmType() == uhdmref_var) continue; if (lhs->UhdmType() == uhdmref_obj) continue; found = true; @@ -2734,10 +2734,10 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, VectorOfany* stmts = b->Stmts(); if (stmts) { for (auto init : *stmts) { - if (init->UhdmType() == uhdmassign_stmt) { - assign_stmt* as = (assign_stmt*)init; + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; const expr* lhs = as->Lhs(); - if (lhs->VpiName() == name) { + if (lhs && lhs->VpiName() == name) { if (lhs->UhdmType() == uhdmref_var) continue; if (lhs->UhdmType() == uhdmref_obj) continue; found = true; @@ -2786,10 +2786,10 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, VectorOfany* stmts = b->Stmts(); if (stmts) { for (auto init : *stmts) { - if (init->UhdmType() == uhdmassign_stmt) { - assign_stmt* as = (assign_stmt*)init; + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; const expr* lhs = as->Lhs(); - if (lhs->VpiName() == name) { + if (lhs && lhs->VpiName() == name) { if (lhs->UhdmType() == uhdmref_var) continue; if (lhs->UhdmType() == uhdmref_obj) continue; found = true; @@ -2839,10 +2839,10 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, VectorOfany* stmts = b->Stmts(); if (stmts) { for (auto init : *stmts) { - if (init->UhdmType() == uhdmassign_stmt) { - assign_stmt* as = (assign_stmt*)init; + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; const expr* lhs = as->Lhs(); - if (lhs->VpiName() == name) { + if (lhs && lhs->VpiName() == name) { if (lhs->UhdmType() == uhdmref_var) continue; if (lhs->UhdmType() == uhdmref_obj) continue; found = true; @@ -2892,9 +2892,10 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, VectorOfany* stmts = b->Stmts(); if (stmts) { for (auto init : *stmts) { - if (init->UhdmType() == uhdmassign_stmt) { - assign_stmt* as = (assign_stmt*)init; + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; const expr* lhs = as->Lhs(); + if (!lhs) continue; if (lhs->UhdmType() == uhdmref_var) continue; if (lhs->UhdmType() == uhdmref_obj) continue; if (lhs->VpiName() == name) { @@ -2952,15 +2953,15 @@ void UhdmWriter::lateTypedefBinding(UHDM::Serializer& s, DesignComponent* mod, parent); } } - } else if (parent->UhdmType() == uhdmassign_stmt) { + } else if (parent->UhdmType() == uhdmassignment) { parent = var->VpiParent()->VpiParent(); // gen_for loop, implicit loop var declaration fixup if (parent->UhdmType() == uhdmgen_for) { gen_for* for_stmt = (gen_for*)parent; if (for_stmt->VpiForInitStmts()) { any* stmt = for_stmt->VpiForInitStmts()->at(0); - if (stmt->UhdmType() == uhdmassign_stmt) { - assign_stmt* st = (assign_stmt*)stmt; + if (stmt->UhdmType() == uhdmassignment) { + assignment* st = (assignment*)stmt; st->Lhs((expr*)swapForSpecifiedVar( s, mod, st->Lhs(), nullptr, nullptr, name, var, parent)); } @@ -3280,10 +3281,10 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { VectorOfany* inits = f->VpiForInitStmts(); if (inits) { for (auto init : *inits) { - if (init->UhdmType() == uhdmassign_stmt) { - assign_stmt* as = (assign_stmt*)init; + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; const expr* lhs = as->Lhs(); - if (lhs->VpiName() == name) { + if (lhs && lhs->VpiName() == name) { if (lhs->UhdmType() == uhdmref_var) continue; if (lhs->UhdmType() == uhdmref_obj) continue; ref->Actual_group((expr*)lhs); @@ -3330,7 +3331,16 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { VectorOfany* stmts = b->Stmts(); if (stmts) { for (auto init : *stmts) { - if (init->UhdmType() == uhdmassign_stmt) { + if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; + const expr* lhs = as->Lhs(); + if (lhs && lhs->VpiName() == name) { + if (lhs->UhdmType() == uhdmref_var) continue; + if (lhs->UhdmType() == uhdmref_obj) continue; + ref->Actual_group((expr*)lhs); + break; + } + } else if (init->UhdmType() == uhdmassign_stmt) { assign_stmt* as = (assign_stmt*)init; const expr* lhs = as->Lhs(); if (lhs->VpiName() == name) { @@ -3376,6 +3386,15 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { ref->Actual_group((expr*)lhs); break; } + } else if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; + const expr* lhs = as->Lhs(); + if (lhs->VpiName() == name) { + if (lhs->UhdmType() == uhdmref_var) continue; + if (lhs->UhdmType() == uhdmref_obj) continue; + ref->Actual_group((expr*)lhs); + break; + } } } } @@ -3413,6 +3432,15 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { ref->Actual_group((expr*)lhs); break; } + } else if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; + const expr* lhs = as->Lhs(); + if (lhs->VpiName() == name) { + if (lhs->UhdmType() == uhdmref_var) continue; + if (lhs->UhdmType() == uhdmref_obj) continue; + ref->Actual_group((expr*)lhs); + break; + } } } } @@ -3450,6 +3478,15 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { ref->Actual_group((expr*)lhs); break; } + } else if (init->UhdmType() == uhdmassignment) { + assignment* as = (assignment*)init; + const expr* lhs = as->Lhs(); + if (lhs->VpiName() == name) { + if (lhs->UhdmType() == uhdmref_var) continue; + if (lhs->UhdmType() == uhdmref_obj) continue; + ref->Actual_group((expr*)lhs); + break; + } } } } diff --git a/tests/AllPackageSignal/AllPackageSignal.log b/tests/AllPackageSignal/AllPackageSignal.log index 965aade615..10e91c50dd 100644 --- a/tests/AllPackageSignal/AllPackageSignal.log +++ b/tests/AllPackageSignal/AllPackageSignal.log @@ -343,8 +343,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 6 array_var 6 -assign_stmt 6 -assignment 6 +assignment 12 begin 6 bit_select 6 bit_typespec 12 @@ -370,8 +369,7 @@ tagged_pattern 6 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 6 array_var 18 -assign_stmt 6 -assignment 12 +assignment 18 begin 12 bit_select 12 bit_typespec 12 diff --git a/tests/ArianeElab/ArianeElab.log b/tests/ArianeElab/ArianeElab.log index 2e99be02e8..78b5d9d3cc 100644 --- a/tests/ArianeElab/ArianeElab.log +++ b/tests/ArianeElab/ArianeElab.log @@ -20169,8 +20169,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 73 -assignment 66 +assignment 139 begin 83 bit_select 103 bit_typespec 377 @@ -20233,8 +20232,7 @@ var_select 48 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 146 -assignment 202 +assignment 348 begin 265 bit_select 295 bit_typespec 377 @@ -31223,13 +31221,15 @@ design: (work@top) |vpiFullName:riscv::spikeCommitLog::rf_s |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -31258,7 +31258,7 @@ design: (work@top) |vpiLhs: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -38687,7 +38687,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -38703,6 +38702,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiParent: @@ -38741,7 +38741,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -38757,12 +38756,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -38778,6 +38777,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -38808,7 +38808,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -38824,12 +38823,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -38845,6 +38844,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -38858,7 +38858,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -38874,6 +38873,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -38895,7 +38895,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -38911,6 +38910,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -38932,7 +38932,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -38948,6 +38947,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -38969,7 +38969,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -38985,6 +38984,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiParent: @@ -39225,13 +39225,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: \_constant: , line:753:29, endln:753:30 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -39239,7 +39239,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -39279,7 +39279,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -39295,6 +39294,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -39314,7 +39314,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -39338,11 +39337,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -39366,6 +39365,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -39517,13 +39517,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: \_constant: , line:763:29, endln:763:30 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -39531,7 +39531,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -39571,7 +39571,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -39587,6 +39586,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -39606,7 +39606,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -39630,11 +39629,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -39658,6 +39657,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -39811,13 +39811,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: \_constant: , line:772:29, endln:772:30 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -39825,7 +39825,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -39865,7 +39865,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -39881,6 +39880,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -39900,7 +39900,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -39924,11 +39923,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -39952,6 +39951,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -41850,13 +41850,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:ariane_pkg::data_align::data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -41912,7 +41914,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -41923,13 +41925,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:ariane_pkg::data_align::addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -41951,7 +41955,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -46878,7 +46882,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -46903,11 +46906,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -46932,6 +46935,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiParent: @@ -47009,9 +47013,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiDecompile:0 @@ -47021,7 +47027,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -47038,13 +47044,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: \_constant: , line:1771:27, endln:1771:28 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -47052,7 +47058,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -47258,13 +47264,15 @@ design: (work@top) |vpiFullName:fpnew_pkg::min_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -47279,7 +47287,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -47296,13 +47304,13 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: \_constant: , line:1780:27, endln:1780:28 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -47310,7 +47318,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -47490,7 +47498,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -47515,6 +47522,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -47558,7 +47566,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -47583,6 +47590,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -47653,7 +47661,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -47678,6 +47685,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::bias::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiParent: @@ -47791,13 +47799,13 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: \_constant: , line:1804:29, endln:1804:30 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -47805,7 +47813,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -47892,7 +47900,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -47908,6 +47915,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -47943,7 +47951,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -47958,6 +47965,7 @@ design: (work@top) |vpiName:exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -47976,7 +47984,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -47992,6 +47999,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -48027,7 +48035,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -48042,6 +48049,7 @@ design: (work@top) |vpiName:man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -48123,9 +48131,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_int_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiDecompile:0 @@ -48135,7 +48145,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -48152,13 +48162,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: \_constant: , line:1818:21, endln:1818:22 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -48166,7 +48176,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -49032,13 +49042,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: \_constant: , line:1864:29, endln:1864:30 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -49046,7 +49056,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -49406,13 +49416,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: \_constant: , line:1880:30, endln:1880:31 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -49420,7 +49430,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -49470,13 +49480,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: \_constant: , line:1881:31, endln:1881:32 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -49484,7 +49494,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -49762,13 +49772,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: \_constant: , line:1893:29, endln:1893:30 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -49776,7 +49786,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -50183,13 +50193,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: \_constant: , line:1910:30, endln:1910:31 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50197,7 +50207,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -50247,13 +50257,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: \_constant: , line:1911:31, endln:1911:32 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50261,7 +50271,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -50499,13 +50509,13 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: \_constant: , line:1920:27, endln:1920:28 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50513,7 +50523,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -50703,13 +50713,13 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: \_constant: , line:1930:27, endln:1930:28 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50717,7 +50727,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -50926,13 +50936,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: \_constant: , line:1938:27, endln:1938:28 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50940,7 +50950,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -51181,9 +51191,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::get_num_regs_multi::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiDecompile:0 @@ -51193,7 +51205,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -51210,13 +51222,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: \_constant: , line:1949:27, endln:1949:28 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -51224,7 +51236,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -61874,13 +61886,15 @@ design: (work@top) |vpiFullName:riscv::spikeCommitLog::rf_s |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -61909,7 +61923,7 @@ design: (work@top) |vpiLhs: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -68529,7 +68543,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -68545,6 +68558,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiParent: @@ -68583,7 +68597,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -68599,12 +68612,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -68620,6 +68633,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -68650,7 +68664,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -68666,12 +68679,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -68687,6 +68700,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -68700,7 +68714,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -68716,6 +68729,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -68737,7 +68751,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -68753,6 +68766,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -68774,7 +68788,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -68790,6 +68803,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -68811,7 +68825,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -68827,6 +68840,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiParent: @@ -69067,13 +69081,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: \_constant: , line:753:29, endln:753:30 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -69081,7 +69095,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -69121,7 +69135,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -69137,6 +69150,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -69156,7 +69170,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -69180,11 +69193,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -69208,6 +69221,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -69359,13 +69373,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: \_constant: , line:763:29, endln:763:30 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -69373,7 +69387,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -69413,7 +69427,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -69429,6 +69442,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -69448,7 +69462,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -69472,11 +69485,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -69500,6 +69513,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -69653,13 +69667,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: \_constant: , line:772:29, endln:772:30 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -69667,7 +69681,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -69707,7 +69721,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -69723,6 +69736,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -69742,7 +69756,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -69766,11 +69779,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -69794,6 +69807,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -71593,13 +71607,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:ariane_pkg::data_align::data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -71655,7 +71671,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -71666,13 +71682,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:ariane_pkg::data_align::addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -71694,7 +71712,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -76480,7 +76498,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -76505,11 +76522,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -76534,6 +76551,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiParent: @@ -76611,9 +76629,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiDecompile:0 @@ -76623,7 +76643,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -76640,13 +76660,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: \_constant: , line:1771:27, endln:1771:28 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -76654,7 +76674,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -76860,13 +76880,15 @@ design: (work@top) |vpiFullName:fpnew_pkg::min_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -76881,7 +76903,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -76898,13 +76920,13 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: \_constant: , line:1780:27, endln:1780:28 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -76912,7 +76934,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -77092,7 +77114,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -77117,6 +77138,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -77160,7 +77182,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -77185,6 +77206,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -77255,7 +77277,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -77280,6 +77301,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::bias::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiParent: @@ -77393,13 +77415,13 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: \_constant: , line:1804:29, endln:1804:30 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -77407,7 +77429,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -77494,7 +77516,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -77510,6 +77531,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -77545,7 +77567,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -77560,6 +77581,7 @@ design: (work@top) |vpiName:exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -77578,7 +77600,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -77594,6 +77615,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -77629,7 +77651,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -77644,6 +77665,7 @@ design: (work@top) |vpiName:man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -77725,9 +77747,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_int_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiDecompile:0 @@ -77737,7 +77761,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -77754,13 +77778,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: \_constant: , line:1818:21, endln:1818:22 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -77768,7 +77792,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -78648,13 +78672,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: \_constant: , line:1864:29, endln:1864:30 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -78662,7 +78686,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -79022,13 +79046,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: \_constant: , line:1880:30, endln:1880:31 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79036,7 +79060,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -79086,13 +79110,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: \_constant: , line:1881:31, endln:1881:32 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79100,7 +79124,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -79378,13 +79402,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: \_constant: , line:1893:29, endln:1893:30 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79392,7 +79416,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -79799,13 +79823,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: \_constant: , line:1910:30, endln:1910:31 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79813,7 +79837,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -79863,13 +79887,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: \_constant: , line:1911:31, endln:1911:32 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79877,7 +79901,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -80115,13 +80139,13 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: \_constant: , line:1920:27, endln:1920:28 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80129,7 +80153,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -80319,13 +80343,13 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: \_constant: , line:1930:27, endln:1930:28 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80333,7 +80357,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -80542,13 +80566,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: \_constant: , line:1938:27, endln:1938:28 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80556,7 +80580,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -80782,9 +80806,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::get_num_regs_multi::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiDecompile:0 @@ -80794,7 +80820,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -80811,13 +80837,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: \_constant: , line:1949:27, endln:1949:28 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80825,7 +80851,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -85137,7 +85163,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -85151,6 +85176,7 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiName:RASDepth |vpiFullName:ariane_pkg::check_cfg::RASDepth + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -85177,7 +85203,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -85191,12 +85216,12 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -85210,6 +85235,7 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -85234,7 +85260,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -85248,12 +85273,12 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -85267,6 +85292,7 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -85280,7 +85306,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -85294,6 +85319,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -85315,7 +85341,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -85329,6 +85354,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -85350,7 +85376,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -85364,6 +85389,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -85385,7 +85411,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -85399,6 +85424,7 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiName:NrPMPEntries |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -85600,7 +85626,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -85608,7 +85634,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -85648,7 +85674,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -85662,6 +85687,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -85681,7 +85707,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -85703,11 +85728,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -85729,6 +85754,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -85857,7 +85883,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -85865,7 +85891,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -85905,7 +85931,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -85919,6 +85944,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -85938,7 +85964,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -85960,11 +85985,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -85986,6 +86011,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -86115,7 +86141,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -86123,7 +86149,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -86163,7 +86189,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -86177,6 +86202,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -86196,7 +86222,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -86218,11 +86243,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -86244,6 +86269,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -87670,7 +87696,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -87683,7 +87709,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -87733,13 +87759,15 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -87775,13 +87803,15 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -94203,7 +94233,6 @@ design: (work@top) \_hier_path: (Features.Width), line:1964:42, endln:1964:56 |vpiParent: \_param_assign: , line:1964:27, endln:1964:56 - |vpiName:Features.Width |vpiActual: \_ref_obj: (Features), line:1964:51, endln:1964:56 |vpiParent: @@ -94214,6 +94243,7 @@ design: (work@top) |vpiParent: \_hier_path: (Features.Width), line:1964:42, endln:1964:56 |vpiName:Width + |vpiName:Features.Width |vpiLhs: \_parameter: (work@fpnew_top.WIDTH), line:1964:27, endln:1964:32 |vpiParamAssign: @@ -94271,7 +94301,7 @@ design: (work@top) |vpiParent: \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10 |vpiForInitStmt: - \_assign_stmt: , line:1971:8, endln:1971:22 + \_assignment: , line:1971:8, endln:1971:22 |vpiParent: \_gen_for: |vpiRhs: @@ -94283,7 +94313,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@fpnew_top.fmt), line:1971:15, endln:1971:18 |vpiParent: - \_assign_stmt: , line:1971:8, endln:1971:22 + \_assignment: , line:1971:8, endln:1971:22 |vpiTypespec: \_ref_typespec: (work@fpnew_top.fmt) |vpiParent: @@ -94399,7 +94429,6 @@ design: (work@top) \_hier_path: (Features.EnableNanBox), line:1974:9, endln:1974:30 |vpiParent: \_operation: , line:1974:9, endln:1974:52 - |vpiName:Features.EnableNanBox |vpiActual: \_ref_obj: (Features), line:1974:18, endln:1974:30 |vpiParent: @@ -94410,6 +94439,7 @@ design: (work@top) |vpiParent: \_hier_path: (Features.EnableNanBox), line:1974:9, endln:1974:30 |vpiName:EnableNanBox + |vpiName:Features.EnableNanBox |vpiOperand: \_operation: , line:1974:35, endln:1974:51 |vpiParent: @@ -101574,7 +101604,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -101590,6 +101619,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -101616,7 +101646,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -101632,12 +101661,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -101653,6 +101682,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -101677,7 +101707,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -101693,12 +101722,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -101714,6 +101743,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -101727,7 +101757,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -101743,6 +101772,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (work@top.i_ariane.check_cfg.NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -101764,7 +101794,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -101780,6 +101809,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.check_cfg.NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -101801,7 +101831,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -101817,6 +101846,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.check_cfg.NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -101838,7 +101868,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -101854,6 +101883,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -102068,7 +102098,7 @@ design: (work@top) \_begin: (work@top.i_ariane.is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (work@top.i_ariane.is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -102076,7 +102106,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.is_inside_nonidempotent_regions.k) |vpiParent: @@ -102116,7 +102146,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -102132,6 +102161,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (work@top.i_ariane.is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -102151,7 +102181,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -102175,11 +102204,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions.Cfg.NonIdempotentAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -102203,6 +102232,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions.Cfg.NonIdempotentLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.is_inside_nonidempotent_regions.address), line:754:89, endln:754:96 |vpiParent: @@ -102344,7 +102374,7 @@ design: (work@top) \_begin: (work@top.i_ariane.is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:work@top.i_ariane.is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (work@top.i_ariane.is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -102352,7 +102382,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.is_inside_execute_regions.k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.is_inside_execute_regions.k) |vpiParent: @@ -102392,7 +102422,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -102408,6 +102437,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_execute_regions.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (work@top.i_ariane.is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -102427,7 +102457,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -102451,11 +102480,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_execute_regions.Cfg.ExecuteRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -102479,6 +102508,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_execute_regions.Cfg.ExecuteRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.is_inside_execute_regions.address), line:764:89, endln:764:96 |vpiParent: @@ -102622,7 +102652,7 @@ design: (work@top) \_begin: (work@top.i_ariane.is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (work@top.i_ariane.is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -102630,7 +102660,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.is_inside_cacheable_regions.k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.is_inside_cacheable_regions.k) |vpiParent: @@ -102670,7 +102700,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -102686,6 +102715,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (work@top.i_ariane.is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -102705,7 +102735,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -102729,11 +102758,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions.Cfg.CachedRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -102757,6 +102786,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions.Cfg.CachedRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.is_inside_cacheable_regions.address), line:773:87, endln:773:94 |vpiParent: @@ -104268,13 +104298,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:work@top.i_ariane.data_align.data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (work@top.i_ariane.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -104310,7 +104342,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.data_align.addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.data_align.addr_tmp) |vpiParent: @@ -104321,13 +104353,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:work@top.i_ariane.data_align.addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (work@top.i_ariane.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -104341,7 +104375,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.data_align.data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.data_align.data_tmp) |vpiParent: @@ -108540,7 +108574,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -108556,6 +108589,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -108582,7 +108616,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -108598,12 +108631,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -108619,6 +108652,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -108643,7 +108677,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -108659,12 +108692,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -108680,6 +108713,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -108693,7 +108727,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -108709,6 +108742,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.check_cfg.NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -108730,7 +108764,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -108746,6 +108779,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.check_cfg.NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -108767,7 +108801,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -108783,6 +108816,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.check_cfg.NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -108804,7 +108838,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -108820,6 +108853,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -109034,7 +109068,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -109042,7 +109076,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k) |vpiParent: @@ -109082,7 +109116,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -109098,6 +109131,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -109117,7 +109151,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -109141,11 +109174,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -109169,6 +109202,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.address), line:754:89, endln:754:96 |vpiParent: @@ -109310,7 +109344,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -109318,7 +109352,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k) |vpiParent: @@ -109358,7 +109392,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -109374,6 +109407,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -109393,7 +109427,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -109417,11 +109450,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions.Cfg.ExecuteRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -109445,6 +109478,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions.Cfg.ExecuteRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.address), line:764:89, endln:764:96 |vpiParent: @@ -109588,7 +109622,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -109596,7 +109630,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k) |vpiParent: @@ -109636,7 +109670,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -109652,6 +109685,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -109671,7 +109705,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -109695,11 +109728,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.Cfg.CachedRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -109723,6 +109756,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.Cfg.CachedRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.address), line:773:87, endln:773:94 |vpiParent: @@ -111234,13 +111268,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.data_align.data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -111276,7 +111312,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.data_align.addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.data_align.addr_tmp) |vpiParent: @@ -111287,13 +111323,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.data_align.addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -111307,7 +111345,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.data_align.data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.data_align.data_tmp) |vpiParent: @@ -115589,7 +115627,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -115605,6 +115642,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -115631,7 +115669,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -115647,12 +115684,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -115668,6 +115705,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -115692,7 +115730,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -115708,12 +115745,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -115729,6 +115766,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -115742,7 +115780,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -115758,6 +115795,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -115779,7 +115817,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -115795,6 +115832,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -115816,7 +115854,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -115832,6 +115869,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -115853,7 +115891,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -115869,6 +115906,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -116083,7 +116121,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -116091,7 +116129,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k) |vpiParent: @@ -116131,7 +116169,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -116147,6 +116184,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -116166,7 +116204,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -116190,11 +116227,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -116218,6 +116255,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.address), line:754:89, endln:754:96 |vpiParent: @@ -116359,7 +116397,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -116367,7 +116405,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k) |vpiParent: @@ -116407,7 +116445,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -116423,6 +116460,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -116442,7 +116480,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -116466,11 +116503,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.Cfg.ExecuteRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -116494,6 +116531,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.Cfg.ExecuteRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.address), line:764:89, endln:764:96 |vpiParent: @@ -116637,7 +116675,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -116645,7 +116683,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k) |vpiParent: @@ -116685,7 +116723,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -116701,6 +116738,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -116720,7 +116758,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -116744,11 +116781,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.Cfg.CachedRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -116772,6 +116809,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.Cfg.CachedRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.address), line:773:87, endln:773:94 |vpiParent: @@ -118283,13 +118321,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -118325,7 +118365,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.addr_tmp) |vpiParent: @@ -118336,13 +118376,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -118356,7 +118398,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.data_tmp) |vpiParent: @@ -123990,7 +124032,7 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -124094,13 +124136,15 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -131246,7 +131290,7 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -131350,13 +131394,15 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -140524,7 +140570,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -140532,7 +140578,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -140572,7 +140618,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -140586,6 +140631,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -140605,7 +140651,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -140627,11 +140672,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -140653,6 +140698,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -140780,7 +140826,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -140788,7 +140834,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -140828,7 +140874,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -140842,6 +140887,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -140861,7 +140907,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -140883,11 +140928,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -140909,6 +140954,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -141037,7 +141083,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -141045,7 +141091,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -141085,7 +141131,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -141099,6 +141144,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -141118,7 +141164,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -141140,11 +141185,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -141166,6 +141211,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -142630,7 +142676,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -142643,7 +142689,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -142693,13 +142739,15 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -142735,13 +142783,15 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -144743,7 +144793,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -144757,6 +144806,7 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiName:RASDepth |vpiFullName:ariane_pkg::check_cfg::RASDepth + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 \_io_decl: (Cfg), line:731:53, endln:731:56 @@ -144815,7 +144865,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -144829,12 +144878,12 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -144848,6 +144897,7 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -144872,7 +144922,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -144886,12 +144935,12 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -144905,6 +144954,7 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -144918,7 +144968,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -144932,6 +144981,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -144953,7 +145003,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -144967,6 +145016,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -144988,7 +145038,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -145002,6 +145051,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -145023,7 +145073,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -145037,6 +145086,7 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiName:NrPMPEntries |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -147906,7 +147956,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -147929,11 +147978,11 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiName:exp_bits |vpiFullName:fpnew_pkg::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -147956,6 +148005,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiName:man_bits |vpiFullName:fpnew_pkg::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiInstance: @@ -147968,7 +148018,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -148004,9 +148054,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiLhs: @@ -148017,7 +148069,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: @@ -148025,7 +148077,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -148172,7 +148224,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -148208,13 +148260,15 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -148234,7 +148288,7 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: @@ -148242,7 +148296,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -148411,7 +148465,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -148436,6 +148489,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_int_var: (fpnew_pkg::exp_bits), line:1787:22, endln:1787:34 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::man_bits), line:1792:3, endln:1794:14 @@ -148468,7 +148522,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -148493,6 +148546,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_int_var: (fpnew_pkg::man_bits), line:1792:22, endln:1792:34 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::bias), line:1797:3, endln:1799:14 @@ -148546,7 +148600,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -148569,6 +148622,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiName:exp_bits |vpiFullName:fpnew_pkg::bias::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiOperand: @@ -148645,7 +148699,7 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: @@ -148653,7 +148707,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -148740,7 +148794,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -148754,6 +148807,7 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiName:exp_bits |vpiFullName:fpnew_pkg::super_format::exp_bits + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -148789,7 +148843,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -148802,6 +148855,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiName:exp_bits + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -148820,7 +148874,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -148834,6 +148887,7 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiName:man_bits |vpiFullName:fpnew_pkg::super_format::man_bits + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -148869,7 +148923,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -148882,6 +148935,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiName:man_bits + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -148904,7 +148958,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -148940,9 +148994,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiLhs: @@ -148953,7 +149009,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: @@ -148961,7 +149017,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -149742,7 +149798,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: @@ -149750,7 +149806,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -150073,7 +150129,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: @@ -150081,7 +150137,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -150131,7 +150187,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: @@ -150139,7 +150195,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -150394,7 +150450,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: @@ -150402,7 +150458,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -150766,7 +150822,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: @@ -150774,7 +150830,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -150824,7 +150880,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: @@ -150832,7 +150888,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -151059,7 +151115,7 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: @@ -151067,7 +151123,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -151238,7 +151294,7 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: @@ -151246,7 +151302,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -151440,7 +151496,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: @@ -151448,7 +151504,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -151586,7 +151642,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -151648,9 +151704,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiLhs: @@ -151661,7 +151719,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: @@ -151669,7 +151727,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -154287,7 +154345,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -154310,11 +154367,11 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiName:exp_bits |vpiFullName:fpnew_pkg::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -154337,6 +154394,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiName:man_bits |vpiFullName:fpnew_pkg::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiInstance: @@ -154349,7 +154407,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -154385,9 +154443,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiLhs: @@ -154398,7 +154458,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: @@ -154406,7 +154466,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -154553,7 +154613,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -154589,13 +154649,15 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -154615,7 +154677,7 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: @@ -154623,7 +154685,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -154792,7 +154854,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -154817,6 +154878,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_int_var: (fpnew_pkg::exp_bits), line:1787:22, endln:1787:34 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::man_bits), line:1792:3, endln:1794:14 @@ -154849,7 +154911,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -154874,6 +154935,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_int_var: (fpnew_pkg::man_bits), line:1792:22, endln:1792:34 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::bias), line:1797:3, endln:1799:14 @@ -154927,7 +154989,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -154950,6 +155011,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiName:exp_bits |vpiFullName:fpnew_pkg::bias::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiOperand: @@ -155026,7 +155088,7 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: @@ -155034,7 +155096,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -155121,7 +155183,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -155135,6 +155196,7 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiName:exp_bits |vpiFullName:fpnew_pkg::super_format::exp_bits + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -155170,7 +155232,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -155183,6 +155244,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiName:exp_bits + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -155201,7 +155263,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -155215,6 +155276,7 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiName:man_bits |vpiFullName:fpnew_pkg::super_format::man_bits + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -155250,7 +155312,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -155263,6 +155324,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiName:man_bits + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -155285,7 +155347,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -155321,9 +155383,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiLhs: @@ -155334,7 +155398,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: @@ -155342,7 +155406,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -156109,7 +156173,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: @@ -156117,7 +156181,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -156440,7 +156504,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: @@ -156448,7 +156512,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -156498,7 +156562,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: @@ -156506,7 +156570,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -156761,7 +156825,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: @@ -156769,7 +156833,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -157133,7 +157197,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: @@ -157141,7 +157205,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -157191,7 +157255,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: @@ -157199,7 +157263,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -157426,7 +157490,7 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: @@ -157434,7 +157498,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -157605,7 +157669,7 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: @@ -157613,7 +157677,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -157807,7 +157871,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: @@ -157815,7 +157879,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -157965,7 +158029,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -158027,9 +158091,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiLhs: @@ -158040,7 +158106,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: @@ -158048,7 +158114,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: diff --git a/tests/ArianeElab2/ArianeElab2.log b/tests/ArianeElab2/ArianeElab2.log index e5db5bec2a..87487b577a 100644 --- a/tests/ArianeElab2/ArianeElab2.log +++ b/tests/ArianeElab2/ArianeElab2.log @@ -20780,8 +20780,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 75 -assignment 66 +assignment 141 begin 83 bit_select 390 bit_typespec 377 @@ -20842,8 +20841,7 @@ unsupported_typespec 28 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 148 -assignment 202 +assignment 350 begin 265 bit_select 1859 bit_typespec 377 @@ -31830,13 +31828,15 @@ design: (work@top) |vpiFullName:riscv::spikeCommitLog::rf_s |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -31865,7 +31865,7 @@ design: (work@top) |vpiLhs: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -39294,7 +39294,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -39310,6 +39309,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiParent: @@ -39348,7 +39348,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -39364,12 +39363,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -39385,6 +39384,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -39415,7 +39415,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -39431,12 +39430,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -39452,6 +39451,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -39465,7 +39465,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -39481,6 +39480,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -39502,7 +39502,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -39518,6 +39517,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -39539,7 +39539,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -39555,6 +39554,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -39576,7 +39576,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -39592,6 +39591,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiParent: @@ -39832,13 +39832,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: \_constant: , line:753:29, endln:753:30 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -39846,7 +39846,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -39886,7 +39886,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -39902,6 +39901,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -39921,7 +39921,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -39945,11 +39944,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -39973,6 +39972,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -40124,13 +40124,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: \_constant: , line:763:29, endln:763:30 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -40138,7 +40138,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -40178,7 +40178,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -40194,6 +40193,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -40213,7 +40213,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -40237,11 +40236,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -40265,6 +40264,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -40418,13 +40418,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: \_constant: , line:772:29, endln:772:30 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -40432,7 +40432,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -40472,7 +40472,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -40488,6 +40487,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -40507,7 +40507,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -40531,11 +40530,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -40559,6 +40558,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -42457,13 +42457,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:ariane_pkg::data_align::data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -42519,7 +42521,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -42530,13 +42532,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:ariane_pkg::data_align::addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -42558,7 +42562,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -47485,7 +47489,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -47510,11 +47513,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -47539,6 +47542,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiParent: @@ -47616,9 +47620,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiDecompile:0 @@ -47628,7 +47634,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -47645,13 +47651,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: \_constant: , line:1771:27, endln:1771:28 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -47659,7 +47665,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -47865,13 +47871,15 @@ design: (work@top) |vpiFullName:fpnew_pkg::min_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -47886,7 +47894,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -47903,13 +47911,13 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: \_constant: , line:1780:27, endln:1780:28 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -47917,7 +47925,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -48097,7 +48105,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -48122,6 +48129,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -48165,7 +48173,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -48190,6 +48197,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -48260,7 +48268,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -48285,6 +48292,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::bias::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiParent: @@ -48398,13 +48406,13 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: \_constant: , line:1804:29, endln:1804:30 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -48412,7 +48420,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -48499,7 +48507,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -48515,6 +48522,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -48550,7 +48558,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -48565,6 +48572,7 @@ design: (work@top) |vpiName:exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -48583,7 +48591,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -48599,6 +48606,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -48634,7 +48642,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -48649,6 +48656,7 @@ design: (work@top) |vpiName:man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -48730,9 +48738,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_int_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiDecompile:0 @@ -48742,7 +48752,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -48759,13 +48769,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: \_constant: , line:1818:21, endln:1818:22 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -48773,7 +48783,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -49639,13 +49649,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: \_constant: , line:1864:29, endln:1864:30 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -49653,7 +49663,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -50013,13 +50023,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: \_constant: , line:1880:30, endln:1880:31 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50027,7 +50037,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -50077,13 +50087,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: \_constant: , line:1881:31, endln:1881:32 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50091,7 +50101,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -50369,13 +50379,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: \_constant: , line:1893:29, endln:1893:30 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50383,7 +50393,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -50790,13 +50800,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: \_constant: , line:1910:30, endln:1910:31 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50804,7 +50814,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -50854,13 +50864,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: \_constant: , line:1911:31, endln:1911:32 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -50868,7 +50878,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -51106,13 +51116,13 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: \_constant: , line:1920:27, endln:1920:28 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -51120,7 +51130,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -51310,13 +51320,13 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: \_constant: , line:1930:27, endln:1930:28 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -51324,7 +51334,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -51533,13 +51543,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: \_constant: , line:1938:27, endln:1938:28 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -51547,7 +51557,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -51788,9 +51798,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::get_num_regs_multi::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiDecompile:0 @@ -51800,7 +51812,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -51817,13 +51829,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: \_constant: , line:1949:27, endln:1949:28 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -51831,7 +51843,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -62481,13 +62493,15 @@ design: (work@top) |vpiFullName:riscv::spikeCommitLog::rf_s |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -62516,7 +62530,7 @@ design: (work@top) |vpiLhs: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -69136,7 +69150,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -69152,6 +69165,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiParent: @@ -69190,7 +69204,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -69206,12 +69219,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -69227,6 +69240,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -69257,7 +69271,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -69273,12 +69286,12 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -69294,6 +69307,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -69307,7 +69321,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -69323,6 +69336,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -69344,7 +69358,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -69360,6 +69373,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -69381,7 +69395,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -69397,6 +69410,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -69418,7 +69432,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -69434,6 +69447,7 @@ design: (work@top) |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiParent: @@ -69674,13 +69688,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: \_constant: , line:753:29, endln:753:30 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -69688,7 +69702,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -69728,7 +69742,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -69744,6 +69757,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -69763,7 +69777,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -69787,11 +69800,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -69815,6 +69828,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -69966,13 +69980,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: \_constant: , line:763:29, endln:763:30 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -69980,7 +69994,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -70020,7 +70034,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -70036,6 +70049,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -70055,7 +70069,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -70079,11 +70092,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -70107,6 +70120,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -70260,13 +70274,13 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: \_constant: , line:772:29, endln:772:30 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -70274,7 +70288,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -70314,7 +70328,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -70330,6 +70343,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -70349,7 +70363,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -70373,11 +70386,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -70401,6 +70414,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -72200,13 +72214,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:ariane_pkg::data_align::data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -72262,7 +72278,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -72273,13 +72289,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:ariane_pkg::data_align::addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -72301,7 +72319,7 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -77087,7 +77105,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -77112,11 +77129,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -77141,6 +77158,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiParent: @@ -77218,9 +77236,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiDecompile:0 @@ -77230,7 +77250,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -77247,13 +77267,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: \_constant: , line:1771:27, endln:1771:28 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -77261,7 +77281,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -77467,13 +77487,15 @@ design: (work@top) |vpiFullName:fpnew_pkg::min_fp_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -77488,7 +77510,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -77505,13 +77527,13 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: \_constant: , line:1780:27, endln:1780:28 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -77519,7 +77541,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -77699,7 +77721,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -77724,6 +77745,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -77767,7 +77789,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -77792,6 +77813,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 |vpiTaskFunc: @@ -77862,7 +77884,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -77887,6 +77908,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::bias::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiParent: @@ -78000,13 +78022,13 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: \_constant: , line:1804:29, endln:1804:30 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -78014,7 +78036,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -78101,7 +78123,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -78117,6 +78138,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -78152,7 +78174,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -78167,6 +78188,7 @@ design: (work@top) |vpiName:exp_bits |vpiActual: \_typespec_member: (exp_bits), line:1501:18, endln:1501:26 + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -78185,7 +78207,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -78201,6 +78222,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::super_format::man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -78236,7 +78258,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -78251,6 +78272,7 @@ design: (work@top) |vpiName:man_bits |vpiActual: \_typespec_member: (man_bits), line:1502:18, endln:1502:26 + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -78332,9 +78354,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::max_int_width::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiDecompile:0 @@ -78344,7 +78368,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -78361,13 +78385,13 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: \_constant: , line:1818:21, endln:1818:22 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -78375,7 +78399,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -79287,13 +79311,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: \_constant: , line:1864:29, endln:1864:30 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79301,7 +79325,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -79661,13 +79685,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: \_constant: , line:1880:30, endln:1880:31 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79675,7 +79699,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -79725,13 +79749,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: \_constant: , line:1881:31, endln:1881:32 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -79739,7 +79763,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -80017,13 +80041,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: \_constant: , line:1893:29, endln:1893:30 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80031,7 +80055,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -80438,13 +80462,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: \_constant: , line:1910:30, endln:1910:31 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80452,7 +80476,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -80502,13 +80526,13 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: \_constant: , line:1911:31, endln:1911:32 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80516,7 +80540,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -80754,13 +80778,13 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: \_constant: , line:1920:27, endln:1920:28 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80768,7 +80792,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -80958,13 +80982,13 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: \_constant: , line:1930:27, endln:1930:28 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -80972,7 +80996,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -81181,13 +81205,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: \_constant: , line:1938:27, endln:1938:28 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -81195,7 +81219,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -81421,9 +81445,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::get_num_regs_multi::res |vpiAutomatic:1 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiDecompile:0 @@ -81433,7 +81459,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -81450,13 +81476,13 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: \_constant: , line:1949:27, endln:1949:28 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -81464,7 +81490,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -85776,7 +85802,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -85790,6 +85815,7 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiName:RASDepth |vpiFullName:ariane_pkg::check_cfg::RASDepth + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -85816,7 +85842,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -85830,12 +85855,12 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -85849,6 +85874,7 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -85873,7 +85899,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -85887,12 +85912,12 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -85906,6 +85931,7 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -85919,7 +85945,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -85933,6 +85958,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -85954,7 +85980,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -85968,6 +85993,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -85989,7 +86015,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -86003,6 +86028,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -86024,7 +86050,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -86038,6 +86063,7 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiName:NrPMPEntries |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -86239,7 +86265,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -86247,7 +86273,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -86287,7 +86313,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -86301,6 +86326,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -86320,7 +86346,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -86342,11 +86367,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -86368,6 +86393,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -86496,7 +86522,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -86504,7 +86530,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -86544,7 +86570,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -86558,6 +86583,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -86577,7 +86603,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -86599,11 +86624,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -86625,6 +86650,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -86754,7 +86780,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -86762,7 +86788,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -86802,7 +86828,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -86816,6 +86841,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -86835,7 +86861,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -86857,11 +86882,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -86883,6 +86908,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -88309,7 +88335,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -88322,7 +88348,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -88372,13 +88398,15 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -88414,13 +88442,15 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -94855,7 +94885,7 @@ design: (work@top) |vpiParent: \_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10 |vpiForInitStmt: - \_assign_stmt: , line:1974:7, endln:1974:21 + \_assignment: , line:1974:7, endln:1974:21 |vpiParent: \_gen_for: |vpiRhs: @@ -94867,7 +94897,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@fpnew_opgroup_block.fmt), line:1974:14, endln:1974:17 |vpiParent: - \_assign_stmt: , line:1974:7, endln:1974:21 + \_assignment: , line:1974:7, endln:1974:21 |vpiTypespec: \_ref_typespec: (work@fpnew_opgroup_block.fmt) |vpiParent: @@ -95171,13 +95201,15 @@ design: (work@top) |vpiName:active_format |vpiFullName:work@fpnew_opgroup_block.gen_parallel_slices.active_format |vpiStmt: - \_assign_stmt: , line:1985:13, endln:1985:21 + \_assignment: , line:1985:13, endln:1985:21 |vpiParent: \_named_begin: (work@fpnew_opgroup_block.gen_parallel_slices.active_format) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@fpnew_opgroup_block.gen_parallel_slices.active_format.in_valid), line:1985:13, endln:1985:21 |vpiParent: - \_assign_stmt: , line:1985:13, endln:1985:21 + \_assignment: , line:1985:13, endln:1985:21 |vpiTypespec: \_ref_typespec: (work@fpnew_opgroup_block.gen_parallel_slices.active_format.in_valid) |vpiParent: @@ -95625,7 +95657,6 @@ design: (work@top) \_hier_path: (Features.Width), line:2012:42, endln:2012:56 |vpiParent: \_param_assign: , line:2012:27, endln:2012:56 - |vpiName:Features.Width |vpiActual: \_ref_obj: (Features), line:2012:51, endln:2012:56 |vpiParent: @@ -95636,6 +95667,7 @@ design: (work@top) |vpiParent: \_hier_path: (Features.Width), line:2012:42, endln:2012:56 |vpiName:Width + |vpiName:Features.Width |vpiLhs: \_parameter: (work@fpnew_top.WIDTH), line:2012:27, endln:2012:32 |vpiParamAssign: @@ -95714,7 +95746,7 @@ design: (work@top) |vpiParent: \_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10 |vpiForInitStmt: - \_assign_stmt: , line:2019:9, endln:2019:25 + \_assignment: , line:2019:9, endln:2019:25 |vpiParent: \_gen_for: |vpiRhs: @@ -95726,7 +95758,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@fpnew_top.opgrp), line:2019:16, endln:2019:21 |vpiParent: - \_assign_stmt: , line:2019:9, endln:2019:25 + \_assignment: , line:2019:9, endln:2019:25 |vpiTypespec: \_ref_typespec: (work@fpnew_top.opgrp) |vpiParent: @@ -95837,7 +95869,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[opgrp]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[opgrp] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -95855,6 +95886,7 @@ design: (work@top) \_bit_select: (work@fpnew_top.gen_operation_groups.Implementation.UnitTypes[opgrp].UnitTypes), line:2021:54, endln:2021:59 |vpiName:opgrp |vpiFullName:work@fpnew_top.gen_operation_groups.Implementation.UnitTypes[opgrp].opgrp + |vpiName:Implementation.UnitTypes[opgrp] |vpiLhs: \_parameter: (work@fpnew_top.gen_operation_groups.DEBUGYOU), line:2021:18, endln:2021:60 |vpiParent: @@ -100180,7 +100212,6 @@ design: (work@top) \_hier_path: (FPU_IMPLEMENTATION.UnitTypes[1]), line:2066:28, endln:2066:59 |vpiParent: \_param_assign: , line:2066:17, endln:2066:59 - |vpiName:FPU_IMPLEMENTATION.UnitTypes[1] |vpiActual: \_ref_obj: (FPU_IMPLEMENTATION), line:2066:47, endln:2066:56 |vpiParent: @@ -100200,6 +100231,7 @@ design: (work@top) |vpiSize:64 |UINT:1 |vpiConstType:9 + |vpiName:FPU_IMPLEMENTATION.UnitTypes[1] |vpiLhs: \_parameter: (work@fpu_wrap.fpu_gen.DEBUGMOI), line:2066:17, endln:2066:59 |vpiParent: @@ -103014,7 +103046,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -103030,6 +103061,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -103056,7 +103088,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -103072,12 +103103,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -103093,6 +103124,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -103117,7 +103149,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -103133,12 +103164,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -103154,6 +103185,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -103167,7 +103199,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -103183,6 +103214,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (work@top.i_ariane.check_cfg.NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -103204,7 +103236,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -103220,6 +103251,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.check_cfg.NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -103241,7 +103273,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -103257,6 +103288,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.check_cfg.NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -103278,7 +103310,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -103294,6 +103325,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.check_cfg.NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -103508,7 +103540,7 @@ design: (work@top) \_begin: (work@top.i_ariane.is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (work@top.i_ariane.is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -103516,7 +103548,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.is_inside_nonidempotent_regions.k) |vpiParent: @@ -103556,7 +103588,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -103572,6 +103603,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (work@top.i_ariane.is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -103591,7 +103623,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -103615,11 +103646,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions.Cfg.NonIdempotentAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -103643,6 +103674,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_nonidempotent_regions.Cfg.NonIdempotentLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.is_inside_nonidempotent_regions.address), line:754:89, endln:754:96 |vpiParent: @@ -103784,7 +103816,7 @@ design: (work@top) \_begin: (work@top.i_ariane.is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:work@top.i_ariane.is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (work@top.i_ariane.is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -103792,7 +103824,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.is_inside_execute_regions.k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.is_inside_execute_regions.k) |vpiParent: @@ -103832,7 +103864,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -103848,6 +103879,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_execute_regions.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (work@top.i_ariane.is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -103867,7 +103899,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -103891,11 +103922,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_execute_regions.Cfg.ExecuteRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -103919,6 +103950,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_execute_regions.Cfg.ExecuteRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.is_inside_execute_regions.address), line:764:89, endln:764:96 |vpiParent: @@ -104062,7 +104094,7 @@ design: (work@top) \_begin: (work@top.i_ariane.is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (work@top.i_ariane.is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -104070,7 +104102,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.is_inside_cacheable_regions.k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.is_inside_cacheable_regions.k) |vpiParent: @@ -104110,7 +104142,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -104126,6 +104157,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (work@top.i_ariane.is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -104145,7 +104177,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -104169,11 +104200,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions.Cfg.CachedRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -104197,6 +104228,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.is_inside_cacheable_regions.Cfg.CachedRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.is_inside_cacheable_regions.address), line:773:87, endln:773:94 |vpiParent: @@ -105708,13 +105740,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:work@top.i_ariane.data_align.data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (work@top.i_ariane.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -105750,7 +105784,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.data_align.addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.data_align.addr_tmp) |vpiParent: @@ -105761,13 +105795,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:work@top.i_ariane.data_align.addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (work@top.i_ariane.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -105781,7 +105817,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.data_align.data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.data_align.data_tmp) |vpiParent: @@ -109980,7 +110016,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -109996,6 +110031,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -110022,7 +110058,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -110038,12 +110073,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -110059,6 +110094,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -110083,7 +110119,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -110099,12 +110134,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -110120,6 +110155,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -110133,7 +110169,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -110149,6 +110184,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.check_cfg.NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -110170,7 +110206,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -110186,6 +110221,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.check_cfg.NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -110207,7 +110243,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -110223,6 +110258,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.check_cfg.NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -110244,7 +110280,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -110260,6 +110295,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.check_cfg.NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -110474,7 +110510,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -110482,7 +110518,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k) |vpiParent: @@ -110522,7 +110558,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -110538,6 +110573,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -110557,7 +110593,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -110581,11 +110616,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -110609,6 +110644,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.is_inside_nonidempotent_regions.address), line:754:89, endln:754:96 |vpiParent: @@ -110750,7 +110786,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -110758,7 +110794,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k) |vpiParent: @@ -110798,7 +110834,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -110814,6 +110849,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -110833,7 +110869,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -110857,11 +110892,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions.Cfg.ExecuteRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -110885,6 +110920,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_execute_regions.Cfg.ExecuteRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.is_inside_execute_regions.address), line:764:89, endln:764:96 |vpiParent: @@ -111028,7 +111064,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -111036,7 +111072,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k) |vpiParent: @@ -111076,7 +111112,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -111092,6 +111127,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -111111,7 +111147,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -111135,11 +111170,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.Cfg.CachedRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -111163,6 +111198,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.Cfg.CachedRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.is_inside_cacheable_regions.address), line:773:87, endln:773:94 |vpiParent: @@ -112674,13 +112710,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.data_align.data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -112716,7 +112754,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.data_align.addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.data_align.addr_tmp) |vpiParent: @@ -112727,13 +112765,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.data_align.addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -112747,7 +112787,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.data_align.data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.data_align.data_tmp) |vpiParent: @@ -117029,7 +117069,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -117045,6 +117084,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.RASDepth |vpiActual: \_typespec_member: (RASDepth), line:685:41, endln:685:49 + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 |vpiStmt: @@ -117071,7 +117111,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -117087,12 +117126,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -117108,6 +117147,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BTBEntries |vpiActual: \_typespec_member: (BTBEntries), line:686:41, endln:686:51 + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -117132,7 +117172,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -117148,12 +117187,12 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -117169,6 +117208,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.BHTEntries |vpiActual: \_typespec_member: (BHTEntries), line:687:41, endln:687:51 + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -117182,7 +117222,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -117198,6 +117237,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -117219,7 +117259,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -117235,6 +117274,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -117256,7 +117296,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -117272,6 +117311,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -117293,7 +117333,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -117309,6 +117348,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.check_cfg.NrPMPEntries |vpiActual: \_typespec_member: (NrPMPEntries), line:703:41, endln:703:53 + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -117523,7 +117563,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -117531,7 +117571,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k) |vpiParent: @@ -117571,7 +117611,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -117587,6 +117626,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.NrNonIdempotentRules |vpiActual: \_typespec_member: (NrNonIdempotentRules), line:689:41, endln:689:61 + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -117606,7 +117646,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -117630,11 +117669,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -117658,6 +117697,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.Cfg.NonIdempotentLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_nonidempotent_regions.address), line:754:89, endln:754:96 |vpiParent: @@ -117799,7 +117839,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -117807,7 +117847,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k) |vpiParent: @@ -117847,7 +117887,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -117863,6 +117902,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.NrExecuteRegionRules |vpiActual: \_typespec_member: (NrExecuteRegionRules), line:692:41, endln:692:61 + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -117882,7 +117922,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -117906,11 +117945,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.Cfg.ExecuteRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -117934,6 +117973,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.Cfg.ExecuteRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_execute_regions.address), line:764:89, endln:764:96 |vpiParent: @@ -118077,7 +118117,7 @@ design: (work@top) \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -118085,7 +118125,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k) |vpiParent: @@ -118125,7 +118165,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -118141,6 +118180,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.NrCachedRegionRules |vpiActual: \_typespec_member: (NrCachedRegionRules), line:695:41, endln:695:60 + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -118160,7 +118200,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -118184,11 +118223,11 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.Cfg.CachedRegionAddrBase[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -118212,6 +118251,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.Cfg.CachedRegionLength[k].k |vpiActual: \_int_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.is_inside_cacheable_regions.address), line:773:87, endln:773:94 |vpiParent: @@ -119723,13 +119763,15 @@ design: (work@top) |vpiName:data_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.data_tmp |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -119765,7 +119807,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.addr_tmp) |vpiParent: @@ -119776,13 +119818,15 @@ design: (work@top) |vpiName:addr_tmp |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.addr_tmp |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -119796,7 +119840,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.data_align.data_tmp) |vpiParent: @@ -122407,7 +122451,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[0]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[0] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -122431,6 +122474,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:Implementation.UnitTypes[0] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].DEBUGYOU), line:2021:18, endln:2021:26 |vpiModule: @@ -122697,7 +122741,21 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask + |vpiActual: + \_ref_obj: (Features), line:2028:24, endln:2028:32 + |vpiParent: + \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 + |vpiName:Features + |vpiActual: + \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.Features), line:2008:45, endln:2008:53 + |vpiActual: + \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask), line:2028:33, endln:2028:43 + |vpiParent: + \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 + |vpiName:IntFmtMask + |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask + |vpiActual: + \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiExpr: \_operation: , line:2071:25, endln:2071:37 |vpiParent: @@ -122732,23 +122790,7 @@ design: (work@top) \_constant: , line:2050:65, endln:2050:69 |vpiOperand: \_constant: , line:2050:71, endln:2050:75 - |vpiActual: - \_ref_obj: (Features), line:2028:24, endln:2028:32 - |vpiParent: - \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 - |vpiName:Features - |vpiActual: - \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.Features), line:2008:45, endln:2008:53 - |vpiActual: - \_ref_obj: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask), line:2028:33, endln:2028:43 - |vpiParent: - \_hier_path: (Features.IntFmtMask), line:2028:24, endln:2028:43 - |vpiName:IntFmtMask - |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask - |vpiActual: - \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -122767,7 +122809,29 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[0] + |vpiActual: + \_ref_obj: (Implementation), line:2029:24, endln:2029:38 + |vpiParent: + \_hier_path: (Implementation.PipeRegs[0]), line:2029:24, endln:2029:54 + |vpiName:Implementation + |vpiActual: + \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.Implementation), line:2009:45, endln:2009:59 + |vpiActual: + \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs), line:2029:48, endln:2029:53 + |vpiParent: + \_hier_path: (Implementation.PipeRegs[0]), line:2029:24, endln:2029:54 + |vpiName:PipeRegs + |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs + |vpiActual: + \_typespec_member: (PipeRegs), line:1721:28, endln:1721:36 + |vpiIndex: + \_constant: , line:2029:48, endln:2029:53 + |vpiParent: + \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs), line:2029:48, endln:2029:53 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 |vpiParent: @@ -122857,31 +122921,7 @@ design: (work@top) \_tagged_pattern: , line:2062:31, endln:2062:48 |vpiOperand: \_constant: , line:2063:19, endln:2063:41 - |vpiActual: - \_ref_obj: (Implementation), line:2029:24, endln:2029:38 - |vpiParent: - \_hier_path: (Implementation.PipeRegs[0]), line:2029:24, endln:2029:54 - |vpiName:Implementation - |vpiActual: - \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.Implementation), line:2009:45, endln:2009:59 - |vpiActual: - \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs), line:2029:48, endln:2029:53 - |vpiParent: - \_hier_path: (Implementation.PipeRegs[0]), line:2029:24, endln:2029:54 - |vpiName:PipeRegs - |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs - |vpiActual: - \_typespec_member: (PipeRegs), line:1721:28, endln:1721:36 - |vpiIndex: - \_constant: , line:2029:48, endln:2029:53 - |vpiParent: - \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs), line:2029:48, endln:2029:53 - |vpiDecompile:0 - |vpiSize:64 - |UINT:0 - |vpiConstType:9 - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[0] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.FmtPipeRegs), line:1965:41, endln:1965:52 |vpiParamAssign: @@ -122900,9 +122940,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -122928,6 +122965,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.FmtUnitTypes), line:1966:41, endln:1966:53 |vpiParamAssign: @@ -123099,9 +123137,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -123121,6 +123156,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -123174,9 +123210,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -123196,6 +123229,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -123409,9 +123443,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -123431,6 +123462,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -123484,9 +123516,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -123506,6 +123535,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -123719,9 +123749,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -123741,6 +123768,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -123794,9 +123822,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -123816,6 +123841,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -124029,9 +124055,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -124051,6 +124074,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -124104,9 +124128,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -124126,6 +124147,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -124339,9 +124361,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -124361,6 +124380,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -124414,9 +124434,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -124436,6 +124453,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -124624,7 +124642,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[1]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[1] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -124648,6 +124665,7 @@ design: (work@top) |vpiSize:64 |UINT:1 |vpiConstType:9 + |vpiName:Implementation.UnitTypes[1] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].DEBUGYOU), line:2021:18, endln:2021:26 |vpiModule: @@ -124914,9 +124932,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -124934,6 +124949,7 @@ design: (work@top) \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -124952,9 +124968,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.PipeRegs[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -124980,6 +124993,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[1] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.FmtPipeRegs), line:1965:41, endln:1965:52 |vpiParamAssign: @@ -124998,9 +125012,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125026,6 +125037,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.FmtUnitTypes), line:1966:41, endln:1966:53 |vpiParamAssign: @@ -125197,9 +125209,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125219,6 +125228,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -125272,9 +125282,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125294,6 +125301,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -125507,9 +125515,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125529,6 +125534,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -125582,9 +125588,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125604,6 +125607,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -125817,9 +125821,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125839,6 +125840,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -125892,9 +125894,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -125914,6 +125913,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -126127,9 +126127,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -126149,6 +126146,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -126202,9 +126200,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -126224,6 +126219,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -126437,9 +126433,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -126459,6 +126452,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -126512,9 +126506,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -126534,6 +126525,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -126722,7 +126714,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[2]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[2] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -126746,6 +126737,7 @@ design: (work@top) |vpiSize:64 |UINT:2 |vpiConstType:9 + |vpiName:Implementation.UnitTypes[2] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].DEBUGYOU), line:2021:18, endln:2021:26 |vpiModule: @@ -127012,9 +127004,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -127032,6 +127021,7 @@ design: (work@top) \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -127050,9 +127040,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.PipeRegs[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -127078,6 +127065,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[2] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.FmtPipeRegs), line:1965:41, endln:1965:52 |vpiParamAssign: @@ -127096,9 +127084,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -127124,6 +127109,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.FmtUnitTypes), line:1966:41, endln:1966:53 |vpiParamAssign: @@ -127295,9 +127281,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -127317,6 +127300,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -127370,9 +127354,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -127392,6 +127373,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -127605,9 +127587,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -127627,6 +127606,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -127680,9 +127660,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -127702,6 +127679,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -127915,9 +127893,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -127937,6 +127912,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -127990,9 +127966,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -128012,6 +127985,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -128225,9 +128199,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -128247,6 +128218,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -128300,9 +128272,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -128322,6 +128291,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -128535,9 +128505,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -128557,6 +128524,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -128610,9 +128578,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -128632,6 +128597,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -128820,7 +128786,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[3]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[3] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -128844,6 +128809,7 @@ design: (work@top) |vpiSize:64 |UINT:3 |vpiConstType:9 + |vpiName:Implementation.UnitTypes[3] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].DEBUGYOU), line:2021:18, endln:2021:26 |vpiModule: @@ -129110,9 +129076,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -129130,6 +129093,7 @@ design: (work@top) \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -129148,9 +129112,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.PipeRegs[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -129176,6 +129137,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[3] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.FmtPipeRegs), line:1965:41, endln:1965:52 |vpiParamAssign: @@ -129194,9 +129156,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -129222,6 +129181,7 @@ design: (work@top) |vpiConstType:9 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.FmtUnitTypes), line:1966:41, endln:1966:53 |vpiParamAssign: @@ -129393,9 +129353,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -129415,6 +129372,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -129468,9 +129426,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[0].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -129490,6 +129445,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -129703,9 +129659,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -129725,6 +129678,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -129778,9 +129732,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[1].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -129800,6 +129751,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -130013,9 +129965,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -130035,6 +129984,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -130088,9 +130038,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[2].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -130110,6 +130057,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -130323,9 +130271,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -130345,6 +130290,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -130398,9 +130344,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[3].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -130420,6 +130363,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -130633,9 +130577,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -130655,6 +130596,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1976:78, endln:1976:87 |vpiParent: @@ -130708,9 +130650,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.gen_parallel_slices[4].Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -130730,6 +130669,7 @@ design: (work@top) \_constant: , line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] |vpiArgument: \_constant: , line:1978:87, endln:1978:96 |vpiParent: @@ -132123,7 +132063,7 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -132227,13 +132167,15 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -139379,7 +139321,7 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiTypespec: \_ref_typespec: (riscv::spikeCommitLog::rf_s) |vpiParent: @@ -139483,13 +139425,15 @@ design: (work@top) |vpiVariables: \_string_var: (riscv::spikeCommitLog::rf_s), line:640:26, endln:640:30 |vpiStmt: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiParent: \_begin: (riscv::spikeCommitLog), line:638:9, endln:638:27 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:640:33, endln:640:51 |vpiParent: - \_assign_stmt: , line:640:26, endln:640:51 + \_assignment: , line:640:26, endln:640:51 |vpiOpType:32 |vpiOperand: \_ref_obj: (riscv::spikeCommitLog::rd_fpr), line:640:33, endln:640:39 @@ -148657,7 +148601,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:752:7, endln:752:17 |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions |vpiForInitStmt: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_nonidempotent_regions), line:753:7, endln:753:10 |vpiRhs: @@ -148665,7 +148609,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 |vpiParent: - \_assign_stmt: , line:753:12, endln:753:30 + \_assignment: , line:753:12, endln:753:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_nonidempotent_regions::k) |vpiParent: @@ -148705,7 +148649,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiParent: \_operation: , line:753:32, endln:753:60 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:753:36, endln:753:39 |vpiParent: @@ -148719,6 +148662,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:753:36, endln:753:60 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiStmt: \_begin: (ariane_pkg::is_inside_nonidempotent_regions), line:753:67, endln:755:10 |vpiParent: @@ -148738,7 +148682,6 @@ design: (work@top) \_hier_path: (Cfg.NonIdempotentAddrBase[k]), line:754:31, endln:754:59 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:754:31, endln:754:34 |vpiParent: @@ -148760,11 +148703,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentAddrBase[k] |vpiArgument: \_hier_path: (Cfg.NonIdempotentLength[k]), line:754:61, endln:754:87 |vpiParent: \_func_call: (range_check), line:754:19, endln:754:97 - |vpiName:Cfg.NonIdempotentLength[k] |vpiActual: \_ref_obj: (Cfg), line:754:61, endln:754:64 |vpiParent: @@ -148786,6 +148729,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_nonidempotent_regions::Cfg.NonIdempotentLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_nonidempotent_regions::k), line:753:25, endln:753:26 + |vpiName:Cfg.NonIdempotentLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_nonidempotent_regions::address), line:754:89, endln:754:96 |vpiParent: @@ -148913,7 +148857,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_execute_regions), line:762:7, endln:762:17 |vpiFullName:ariane_pkg::is_inside_execute_regions |vpiForInitStmt: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_execute_regions), line:763:7, endln:763:10 |vpiRhs: @@ -148921,7 +148865,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 |vpiParent: - \_assign_stmt: , line:763:12, endln:763:30 + \_assignment: , line:763:12, endln:763:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_execute_regions::k) |vpiParent: @@ -148961,7 +148905,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiParent: \_operation: , line:763:32, endln:763:60 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:763:36, endln:763:39 |vpiParent: @@ -148975,6 +148918,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:763:36, endln:763:60 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::is_inside_execute_regions::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_execute_regions), line:763:67, endln:765:10 |vpiParent: @@ -148994,7 +148938,6 @@ design: (work@top) \_hier_path: (Cfg.ExecuteRegionAddrBase[k]), line:764:31, endln:764:59 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:764:31, endln:764:34 |vpiParent: @@ -149016,11 +148959,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.ExecuteRegionLength[k]), line:764:61, endln:764:87 |vpiParent: \_func_call: (range_check), line:764:19, endln:764:97 - |vpiName:Cfg.ExecuteRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:764:61, endln:764:64 |vpiParent: @@ -149042,6 +148985,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_execute_regions::Cfg.ExecuteRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_execute_regions::k), line:763:25, endln:763:26 + |vpiName:Cfg.ExecuteRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_execute_regions::address), line:764:89, endln:764:96 |vpiParent: @@ -149170,7 +149114,7 @@ design: (work@top) \_begin: (ariane_pkg::is_inside_cacheable_regions), line:771:7, endln:771:17 |vpiFullName:ariane_pkg::is_inside_cacheable_regions |vpiForInitStmt: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiParent: \_for_stmt: (ariane_pkg::is_inside_cacheable_regions), line:772:7, endln:772:10 |vpiRhs: @@ -149178,7 +149122,7 @@ design: (work@top) |vpiLhs: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 |vpiParent: - \_assign_stmt: , line:772:12, endln:772:30 + \_assignment: , line:772:12, endln:772:30 |vpiTypespec: \_ref_typespec: (ariane_pkg::is_inside_cacheable_regions::k) |vpiParent: @@ -149218,7 +149162,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiParent: \_operation: , line:772:32, endln:772:59 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:772:36, endln:772:39 |vpiParent: @@ -149232,6 +149175,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:772:36, endln:772:59 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::is_inside_cacheable_regions::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiStmt: \_begin: (ariane_pkg::is_inside_cacheable_regions), line:772:66, endln:774:10 |vpiParent: @@ -149251,7 +149195,6 @@ design: (work@top) \_hier_path: (Cfg.CachedRegionAddrBase[k]), line:773:31, endln:773:58 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionAddrBase[k] |vpiActual: \_ref_obj: (Cfg), line:773:31, endln:773:34 |vpiParent: @@ -149273,11 +149216,11 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionAddrBase[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionAddrBase[k] |vpiArgument: \_hier_path: (Cfg.CachedRegionLength[k]), line:773:60, endln:773:85 |vpiParent: \_func_call: (range_check), line:773:19, endln:773:95 - |vpiName:Cfg.CachedRegionLength[k] |vpiActual: \_ref_obj: (Cfg), line:773:60, endln:773:63 |vpiParent: @@ -149299,6 +149242,7 @@ design: (work@top) |vpiFullName:ariane_pkg::is_inside_cacheable_regions::Cfg.CachedRegionLength[k]::k |vpiActual: \_int_var: (ariane_pkg::is_inside_cacheable_regions::k), line:772:25, endln:772:26 + |vpiName:Cfg.CachedRegionLength[k] |vpiArgument: \_ref_obj: (ariane_pkg::is_inside_cacheable_regions::address), line:773:87, endln:773:94 |vpiParent: @@ -150763,7 +150707,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::addr_tmp) |vpiParent: @@ -150776,7 +150720,7 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiTypespec: \_ref_typespec: (ariane_pkg::data_align::data_tmp) |vpiParent: @@ -150826,13 +150770,15 @@ design: (work@top) |vpiVariables: \_logic_var: (ariane_pkg::data_align::data_tmp), line:1399:22, endln:1399:30 |vpiStmt: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1398:32, endln:1398:74 |vpiParent: - \_assign_stmt: , line:1398:21, endln:1398:74 + \_assignment: , line:1398:21, endln:1398:74 |vpiOpType:33 |vpiOperand: \_operation: , line:1398:34, endln:1398:61 @@ -150868,13 +150814,15 @@ design: (work@top) |vpiLhs: \_logic_var: (ariane_pkg::data_align::addr_tmp), line:1398:21, endln:1398:29 |vpiStmt: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiParent: \_begin: (ariane_pkg::data_align), line:1399:9, endln:1399:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:1399:33, endln:1399:43 |vpiParent: - \_assign_stmt: , line:1399:22, endln:1399:43 + \_assignment: , line:1399:22, endln:1399:43 |vpiOpType:34 |vpiOperand: \_constant: , line:1399:34, endln:1399:36 @@ -152876,7 +152824,6 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiParent: \_operation: , line:734:16, endln:734:32 - |vpiName:Cfg.RASDepth |vpiActual: \_ref_obj: (Cfg), line:734:16, endln:734:19 |vpiParent: @@ -152890,6 +152837,7 @@ design: (work@top) \_hier_path: (Cfg.RASDepth), line:734:16, endln:734:28 |vpiName:RASDepth |vpiFullName:ariane_pkg::check_cfg::RASDepth + |vpiName:Cfg.RASDepth |vpiOperand: \_constant: , line:734:31, endln:734:32 \_io_decl: (Cfg), line:731:53, endln:731:56 @@ -152948,7 +152896,6 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiParent: \_sys_func_call: ($clog2), line:735:19, endln:735:41 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:26, endln:735:29 |vpiParent: @@ -152962,12 +152909,12 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:26, endln:735:40 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiParent: \_operation: , line:735:16, endln:735:60 - |vpiName:Cfg.BTBEntries |vpiActual: \_ref_obj: (Cfg), line:735:46, endln:735:49 |vpiParent: @@ -152981,6 +152928,7 @@ design: (work@top) \_hier_path: (Cfg.BTBEntries), line:735:46, endln:735:60 |vpiName:BTBEntries |vpiFullName:ariane_pkg::check_cfg::BTBEntries + |vpiName:Cfg.BTBEntries |vpiStmt: \_immediate_assert: , line:736:9, endln:736:62 |vpiParent: @@ -153005,7 +152953,6 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiParent: \_sys_func_call: ($clog2), line:736:19, endln:736:41 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:26, endln:736:29 |vpiParent: @@ -153019,12 +152966,12 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:26, endln:736:40 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiName:$clog2 |vpiOperand: \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiParent: \_operation: , line:736:16, endln:736:60 - |vpiName:Cfg.BHTEntries |vpiActual: \_ref_obj: (Cfg), line:736:46, endln:736:49 |vpiParent: @@ -153038,6 +152985,7 @@ design: (work@top) \_hier_path: (Cfg.BHTEntries), line:736:46, endln:736:60 |vpiName:BHTEntries |vpiFullName:ariane_pkg::check_cfg::BHTEntries + |vpiName:Cfg.BHTEntries |vpiStmt: \_immediate_assert: , line:737:9, endln:737:56 |vpiParent: @@ -153051,7 +152999,6 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiParent: \_operation: , line:737:16, endln:737:54 - |vpiName:Cfg.NrNonIdempotentRules |vpiActual: \_ref_obj: (Cfg), line:737:16, endln:737:19 |vpiParent: @@ -153065,6 +153012,7 @@ design: (work@top) \_hier_path: (Cfg.NrNonIdempotentRules), line:737:16, endln:737:40 |vpiName:NrNonIdempotentRules |vpiFullName:ariane_pkg::check_cfg::NrNonIdempotentRules + |vpiName:Cfg.NrNonIdempotentRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:737:44, endln:737:54 |vpiParent: @@ -153086,7 +153034,6 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiParent: \_operation: , line:738:16, endln:738:54 - |vpiName:Cfg.NrExecuteRegionRules |vpiActual: \_ref_obj: (Cfg), line:738:16, endln:738:19 |vpiParent: @@ -153100,6 +153047,7 @@ design: (work@top) \_hier_path: (Cfg.NrExecuteRegionRules), line:738:16, endln:738:40 |vpiName:NrExecuteRegionRules |vpiFullName:ariane_pkg::check_cfg::NrExecuteRegionRules + |vpiName:Cfg.NrExecuteRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:738:44, endln:738:54 |vpiParent: @@ -153121,7 +153069,6 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiParent: \_operation: , line:739:16, endln:739:54 - |vpiName:Cfg.NrCachedRegionRules |vpiActual: \_ref_obj: (Cfg), line:739:16, endln:739:19 |vpiParent: @@ -153135,6 +153082,7 @@ design: (work@top) \_hier_path: (Cfg.NrCachedRegionRules), line:739:16, endln:739:39 |vpiName:NrCachedRegionRules |vpiFullName:ariane_pkg::check_cfg::NrCachedRegionRules + |vpiName:Cfg.NrCachedRegionRules |vpiOperand: \_ref_obj: (ariane_pkg::check_cfg::NrMaxRules), line:739:44, endln:739:54 |vpiParent: @@ -153156,7 +153104,6 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiParent: \_operation: , line:740:16, endln:740:38 - |vpiName:Cfg.NrPMPEntries |vpiActual: \_ref_obj: (Cfg), line:740:16, endln:740:19 |vpiParent: @@ -153170,6 +153117,7 @@ design: (work@top) \_hier_path: (Cfg.NrPMPEntries), line:740:16, endln:740:32 |vpiName:NrPMPEntries |vpiFullName:ariane_pkg::check_cfg::NrPMPEntries + |vpiName:Cfg.NrPMPEntries |vpiOperand: \_constant: , line:740:36, endln:740:38 |vpiInstance: @@ -156039,7 +155987,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -156062,11 +156009,11 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiName:exp_bits |vpiFullName:fpnew_pkg::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -156089,6 +156036,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiName:man_bits |vpiFullName:fpnew_pkg::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiInstance: @@ -156101,7 +156049,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -156137,9 +156085,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiLhs: @@ -156150,7 +156100,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: @@ -156158,7 +156108,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -156305,7 +156255,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -156341,13 +156291,15 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -156367,7 +156319,7 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: @@ -156375,7 +156327,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -156544,7 +156496,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -156569,6 +156520,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_int_var: (fpnew_pkg::exp_bits), line:1787:22, endln:1787:34 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::man_bits), line:1792:3, endln:1794:14 @@ -156601,7 +156553,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -156626,6 +156577,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_int_var: (fpnew_pkg::man_bits), line:1792:22, endln:1792:34 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::bias), line:1797:3, endln:1799:14 @@ -156679,7 +156631,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -156702,6 +156653,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiName:exp_bits |vpiFullName:fpnew_pkg::bias::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiOperand: @@ -156778,7 +156730,7 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: @@ -156786,7 +156738,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -156873,7 +156825,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -156887,6 +156838,7 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiName:exp_bits |vpiFullName:fpnew_pkg::super_format::exp_bits + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -156922,7 +156874,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -156935,6 +156886,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiName:exp_bits + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -156953,7 +156905,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -156967,6 +156918,7 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiName:man_bits |vpiFullName:fpnew_pkg::super_format::man_bits + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -157002,7 +156954,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -157015,6 +156966,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiName:man_bits + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -157037,7 +156989,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -157073,9 +157025,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiLhs: @@ -157086,7 +157040,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: @@ -157094,7 +157048,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -157875,7 +157829,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: @@ -157883,7 +157837,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -158206,7 +158160,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: @@ -158214,7 +158168,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -158264,7 +158218,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: @@ -158272,7 +158226,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -158527,7 +158481,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: @@ -158535,7 +158489,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -158899,7 +158853,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: @@ -158907,7 +158861,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -158957,7 +158911,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: @@ -158965,7 +158919,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -159192,7 +159146,7 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: @@ -159200,7 +159154,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -159371,7 +159325,7 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: @@ -159379,7 +159333,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -159573,7 +159527,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: @@ -159581,7 +159535,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -159719,7 +159673,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -159781,9 +159735,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiLhs: @@ -159794,7 +159750,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: @@ -159802,7 +159758,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -162420,7 +162376,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:12, endln:1765:24 |vpiParent: @@ -162443,11 +162398,11 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1765:12, endln:1765:38 |vpiName:exp_bits |vpiFullName:fpnew_pkg::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiParent: \_operation: , line:1765:12, endln:1765:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1765:41, endln:1765:53 |vpiParent: @@ -162470,6 +162425,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1765:41, endln:1765:67 |vpiName:man_bits |vpiFullName:fpnew_pkg::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:1765:70, endln:1765:71 |vpiInstance: @@ -162482,7 +162438,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiParent: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::res) |vpiParent: @@ -162518,9 +162474,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_fp_width::res), line:1770:28, endln:1770:31 |vpiStmt: - \_assign_stmt: , line:1770:28, endln:1770:35 + \_assignment: , line:1770:28, endln:1770:35 |vpiParent: \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1770:34, endln:1770:35 |vpiLhs: @@ -162531,7 +162489,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_fp_width), line:1771:5, endln:1773:66 |vpiFullName:fpnew_pkg::max_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiParent: \_for_stmt: (fpnew_pkg::max_fp_width), line:1771:5, endln:1771:8 |vpiRhs: @@ -162539,7 +162497,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_fp_width::i), line:1771:23, endln:1771:24 |vpiParent: - \_assign_stmt: , line:1771:10, endln:1771:28 + \_assignment: , line:1771:10, endln:1771:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_fp_width::i) |vpiParent: @@ -162686,7 +162644,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::res) |vpiParent: @@ -162722,13 +162680,15 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::min_fp_width::res), line:1779:28, endln:1779:31 |vpiStmt: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiParent: \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_func_call: (max_fp_width), line:1779:34, endln:1779:51 |vpiParent: - \_assign_stmt: , line:1779:28, endln:1779:51 + \_assignment: , line:1779:28, endln:1779:51 |vpiArgument: \_ref_obj: (fpnew_pkg::min_fp_width::cfg), line:1779:47, endln:1779:50 |vpiParent: @@ -162748,7 +162708,7 @@ design: (work@top) \_begin: (fpnew_pkg::min_fp_width), line:1780:5, endln:1782:66 |vpiFullName:fpnew_pkg::min_fp_width |vpiForInitStmt: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiParent: \_for_stmt: (fpnew_pkg::min_fp_width), line:1780:5, endln:1780:8 |vpiRhs: @@ -162756,7 +162716,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::min_fp_width::i), line:1780:23, endln:1780:24 |vpiParent: - \_assign_stmt: , line:1780:10, endln:1780:28 + \_assignment: , line:1780:10, endln:1780:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::min_fp_width::i) |vpiParent: @@ -162925,7 +162885,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1788:12, endln:1788:38 |vpiParent: \_return_stmt: , line:1788:5, endln:1788:11 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1788:12, endln:1788:24 |vpiParent: @@ -162950,6 +162909,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::exp_bits::exp_bits |vpiActual: \_int_var: (fpnew_pkg::exp_bits), line:1787:22, endln:1787:34 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::man_bits), line:1792:3, endln:1794:14 @@ -162982,7 +162942,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:1793:12, endln:1793:38 |vpiParent: \_return_stmt: , line:1793:5, endln:1793:11 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1793:12, endln:1793:24 |vpiParent: @@ -163007,6 +162966,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::man_bits::man_bits |vpiActual: \_int_var: (fpnew_pkg::man_bits), line:1792:22, endln:1792:34 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiInstance: \_package: fpnew_pkg (fpnew_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1485:1, endln:1955:11 \_function: (fpnew_pkg::bias), line:1797:3, endln:1799:14 @@ -163060,7 +163020,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiParent: \_operation: , line:1798:26, endln:1798:54 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:1798:26, endln:1798:38 |vpiParent: @@ -163083,6 +163042,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:1798:26, endln:1798:52 |vpiName:exp_bits |vpiFullName:fpnew_pkg::bias::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_constant: , line:1798:53, endln:1798:54 |vpiOperand: @@ -163159,7 +163119,7 @@ design: (work@top) \_begin: (fpnew_pkg::super_format), line:1803:5, endln:1803:14 |vpiFullName:fpnew_pkg::super_format |vpiForInitStmt: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiParent: \_for_stmt: (fpnew_pkg::super_format), line:1804:5, endln:1804:8 |vpiRhs: @@ -163167,7 +163127,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::super_format::fmt), line:1804:23, endln:1804:26 |vpiParent: - \_assign_stmt: , line:1804:10, endln:1804:30 + \_assignment: , line:1804:10, endln:1804:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::super_format::fmt) |vpiParent: @@ -163254,7 +163214,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiParent: \_func_call: (maximum), line:1806:34, endln:1806:84 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:42, endln:1806:45 |vpiParent: @@ -163268,6 +163227,7 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:42, endln:1806:54 |vpiName:exp_bits |vpiFullName:fpnew_pkg::super_format::exp_bits + |vpiName:res.exp_bits |vpiArgument: \_func_call: (exp_bits), line:1806:56, endln:1806:83 |vpiParent: @@ -163303,7 +163263,6 @@ design: (work@top) \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiParent: \_assignment: , line:1806:9, endln:1806:85 - |vpiName:res.exp_bits |vpiActual: \_ref_obj: (res), line:1806:13, endln:1806:21 |vpiParent: @@ -163316,6 +163275,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.exp_bits), line:1806:9, endln:1806:21 |vpiName:exp_bits + |vpiName:res.exp_bits |vpiStmt: \_assignment: , line:1807:9, endln:1807:85 |vpiParent: @@ -163334,7 +163294,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiParent: \_func_call: (maximum), line:1807:34, endln:1807:84 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:42, endln:1807:45 |vpiParent: @@ -163348,6 +163307,7 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:42, endln:1807:54 |vpiName:man_bits |vpiFullName:fpnew_pkg::super_format::man_bits + |vpiName:res.man_bits |vpiArgument: \_func_call: (man_bits), line:1807:56, endln:1807:83 |vpiParent: @@ -163383,7 +163343,6 @@ design: (work@top) \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiParent: \_assignment: , line:1807:9, endln:1807:85 - |vpiName:res.man_bits |vpiActual: \_ref_obj: (res), line:1807:13, endln:1807:21 |vpiParent: @@ -163396,6 +163355,7 @@ design: (work@top) |vpiParent: \_hier_path: (res.man_bits), line:1807:9, endln:1807:21 |vpiName:man_bits + |vpiName:res.man_bits |vpiStmt: \_return_stmt: , line:1809:5, endln:1809:11 |vpiParent: @@ -163418,7 +163378,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiParent: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::res) |vpiParent: @@ -163454,9 +163414,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::max_int_width::res), line:1817:28, endln:1817:31 |vpiStmt: - \_assign_stmt: , line:1817:28, endln:1817:35 + \_assignment: , line:1817:28, endln:1817:35 |vpiParent: \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1817:34, endln:1817:35 |vpiLhs: @@ -163467,7 +163429,7 @@ design: (work@top) \_begin: (fpnew_pkg::max_int_width), line:1818:5, endln:1820:8 |vpiFullName:fpnew_pkg::max_int_width |vpiForInitStmt: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiParent: \_for_stmt: (fpnew_pkg::max_int_width), line:1818:5, endln:1818:8 |vpiRhs: @@ -163475,7 +163437,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::max_int_width::ifmt), line:1818:14, endln:1818:18 |vpiParent: - \_assign_stmt: , line:1818:10, endln:1818:22 + \_assignment: , line:1818:10, endln:1818:22 |vpiTypespec: \_ref_typespec: (fpnew_pkg::max_int_width::ifmt) |vpiParent: @@ -164242,7 +164204,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1866:77 |vpiFullName:fpnew_pkg::get_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_formats), line:1864:5, endln:1864:8 |vpiRhs: @@ -164250,7 +164212,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_formats::fmt), line:1864:23, endln:1864:26 |vpiParent: - \_assign_stmt: , line:1864:10, endln:1864:30 + \_assignment: , line:1864:10, endln:1864:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_formats::fmt) |vpiParent: @@ -164573,7 +164535,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_lane_int_formats), line:1876:5, endln:1876:36 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiRhs: @@ -164581,7 +164543,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::ifmt), line:1880:23, endln:1880:27 |vpiParent: - \_assign_stmt: , line:1880:10, endln:1880:31 + \_assignment: , line:1880:10, endln:1880:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::ifmt) |vpiParent: @@ -164631,7 +164593,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1880:5, endln:1880:8 |vpiFullName:fpnew_pkg::get_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_lane_int_formats), line:1881:7, endln:1881:10 |vpiRhs: @@ -164639,7 +164601,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_lane_int_formats::fmt), line:1881:25, endln:1881:28 |vpiParent: - \_assign_stmt: , line:1881:12, endln:1881:32 + \_assignment: , line:1881:12, endln:1881:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_lane_int_formats::fmt) |vpiParent: @@ -164894,7 +164856,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1896:67 |vpiFullName:fpnew_pkg::get_conv_lane_formats |vpiForInitStmt: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_formats), line:1893:5, endln:1893:8 |vpiRhs: @@ -164902,7 +164864,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_formats::fmt), line:1893:23, endln:1893:26 |vpiParent: - \_assign_stmt: , line:1893:10, endln:1893:30 + \_assignment: , line:1893:10, endln:1893:30 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_formats::fmt) |vpiParent: @@ -165266,7 +165228,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_conv_lane_int_formats), line:1906:5, endln:1906:36 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiRhs: @@ -165274,7 +165236,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::ifmt), line:1910:23, endln:1910:27 |vpiParent: - \_assign_stmt: , line:1910:10, endln:1910:31 + \_assignment: , line:1910:10, endln:1910:31 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::ifmt) |vpiParent: @@ -165324,7 +165286,7 @@ design: (work@top) \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1910:5, endln:1910:8 |vpiFullName:fpnew_pkg::get_conv_lane_int_formats |vpiForInitStmt: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiParent: \_for_stmt: (fpnew_pkg::get_conv_lane_int_formats), line:1911:7, endln:1911:10 |vpiRhs: @@ -165332,7 +165294,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_conv_lane_int_formats::fmt), line:1911:25, endln:1911:28 |vpiParent: - \_assign_stmt: , line:1911:12, endln:1911:32 + \_assignment: , line:1911:12, endln:1911:32 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_conv_lane_int_formats::fmt) |vpiParent: @@ -165559,7 +165521,7 @@ design: (work@top) \_begin: (fpnew_pkg::any_enabled_multi), line:1923:7, endln:1923:19 |vpiFullName:fpnew_pkg::any_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiParent: \_for_stmt: (fpnew_pkg::any_enabled_multi), line:1920:5, endln:1920:8 |vpiRhs: @@ -165567,7 +165529,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::any_enabled_multi::i), line:1920:23, endln:1920:24 |vpiParent: - \_assign_stmt: , line:1920:10, endln:1920:28 + \_assignment: , line:1920:10, endln:1920:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::any_enabled_multi::i) |vpiParent: @@ -165738,7 +165700,7 @@ design: (work@top) \_begin: (fpnew_pkg::is_first_enabled_multi), line:1933:5, endln:1933:17 |vpiFullName:fpnew_pkg::is_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiParent: \_for_stmt: (fpnew_pkg::is_first_enabled_multi), line:1930:5, endln:1930:8 |vpiRhs: @@ -165746,7 +165708,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::is_first_enabled_multi::i), line:1930:23, endln:1930:24 |vpiParent: - \_assign_stmt: , line:1930:10, endln:1930:28 + \_assignment: , line:1930:10, endln:1930:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::is_first_enabled_multi::i) |vpiParent: @@ -165940,7 +165902,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_first_enabled_multi), line:1941:7, endln:1941:30 |vpiFullName:fpnew_pkg::get_first_enabled_multi |vpiForInitStmt: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_first_enabled_multi), line:1938:5, endln:1938:8 |vpiRhs: @@ -165948,7 +165910,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_first_enabled_multi::i), line:1938:23, endln:1938:24 |vpiParent: - \_assign_stmt: , line:1938:10, endln:1938:28 + \_assignment: , line:1938:10, endln:1938:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_first_enabled_multi::i) |vpiParent: @@ -166098,7 +166060,7 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiParent: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::res) |vpiParent: @@ -166160,9 +166122,11 @@ design: (work@top) |vpiVariables: \_int_var: (fpnew_pkg::get_num_regs_multi::res), line:1948:28, endln:1948:31 |vpiStmt: - \_assign_stmt: , line:1948:28, endln:1948:35 + \_assignment: , line:1948:28, endln:1948:35 |vpiParent: \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:1948:34, endln:1948:35 |vpiLhs: @@ -166173,7 +166137,7 @@ design: (work@top) \_begin: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1951:8 |vpiFullName:fpnew_pkg::get_num_regs_multi |vpiForInitStmt: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiParent: \_for_stmt: (fpnew_pkg::get_num_regs_multi), line:1949:5, endln:1949:8 |vpiRhs: @@ -166181,7 +166145,7 @@ design: (work@top) |vpiLhs: \_int_var: (fpnew_pkg::get_num_regs_multi::i), line:1949:23, endln:1949:24 |vpiParent: - \_assign_stmt: , line:1949:10, endln:1949:28 + \_assignment: , line:1949:10, endln:1949:28 |vpiTypespec: \_ref_typespec: (fpnew_pkg::get_num_regs_multi::i) |vpiParent: @@ -184423,7 +184387,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[0]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[0] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -184431,6 +184394,7 @@ design: (work@top) |vpiName:Implementation |vpiActual: \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].Implementation.UnitTypes[0].UnitTypes), line:2021:54, endln:2021:59 + |vpiName:Implementation.UnitTypes[0] \_param_assign: , line:2021:18, endln:2021:60 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0]), line:2019:64, endln:2035:6 @@ -184455,9 +184419,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -184467,6 +184428,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.PipeRegs[0].PipeRegs), line:2029:48, endln:2029:53 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[0] \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.UnitTypes[0].UnitTypes), line:2030:49, endln:2030:54 |vpiParent: \_hier_path: (Implementation.UnitTypes[0]), line:2030:24, endln:2030:55 @@ -184484,9 +184446,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.UnitTypes[0] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[0] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -184496,6 +184455,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Implementation.UnitTypes[0].UnitTypes), line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[0] \_int_typespec: , line:1505:14, endln:1505:26 |vpiParent: \_ref_typespec: @@ -185124,7 +185084,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[1]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[1] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -185132,6 +185091,7 @@ design: (work@top) |vpiName:Implementation |vpiActual: \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].Implementation.UnitTypes[1].UnitTypes), line:2021:54, endln:2021:59 + |vpiName:Implementation.UnitTypes[1] \_param_assign: , line:2021:18, endln:2021:60 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1]), line:2019:64, endln:2035:6 @@ -185156,9 +185116,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.PipeRegs[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -185168,6 +185125,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.PipeRegs[1].PipeRegs), line:2029:48, endln:2029:53 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[1] \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.UnitTypes[1].UnitTypes), line:2030:49, endln:2030:54 |vpiParent: \_hier_path: (Implementation.UnitTypes[1]), line:2030:24, endln:2030:55 @@ -185185,9 +185143,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.UnitTypes[1] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[1] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -185197,6 +185152,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Implementation.UnitTypes[1].UnitTypes), line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[1] \_int_typespec: , line:1505:14, endln:1505:26 |vpiParent: \_ref_typespec: @@ -185825,7 +185781,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[2]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[2] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -185833,6 +185788,7 @@ design: (work@top) |vpiName:Implementation |vpiActual: \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].Implementation.UnitTypes[2].UnitTypes), line:2021:54, endln:2021:59 + |vpiName:Implementation.UnitTypes[2] \_param_assign: , line:2021:18, endln:2021:60 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2]), line:2019:64, endln:2035:6 @@ -185857,9 +185813,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.PipeRegs[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -185869,6 +185822,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.PipeRegs[2].PipeRegs), line:2029:48, endln:2029:53 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[2] \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.UnitTypes[2].UnitTypes), line:2030:49, endln:2030:54 |vpiParent: \_hier_path: (Implementation.UnitTypes[2]), line:2030:24, endln:2030:55 @@ -185886,9 +185840,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.UnitTypes[2] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[2] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -185898,6 +185849,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Implementation.UnitTypes[2].UnitTypes), line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[2] \_int_typespec: , line:1505:14, endln:1505:26 |vpiParent: \_ref_typespec: @@ -186526,7 +186478,6 @@ design: (work@top) \_hier_path: (Implementation.UnitTypes[3]), line:2021:29, endln:2021:60 |vpiParent: \_param_assign: , line:2021:18, endln:2021:60 - |vpiName:Implementation.UnitTypes[3] |vpiActual: \_ref_obj: (Implementation), line:2021:44, endln:2021:53 |vpiParent: @@ -186534,6 +186485,7 @@ design: (work@top) |vpiName:Implementation |vpiActual: \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].Implementation.UnitTypes[3].UnitTypes), line:2021:54, endln:2021:59 + |vpiName:Implementation.UnitTypes[3] \_param_assign: , line:2021:18, endln:2021:60 |vpiParent: \_gen_scope: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3]), line:2019:64, endln:2035:6 @@ -186558,9 +186510,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.PipeRegs[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.PipeRegs[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2029:24, endln:2029:38 |vpiParent: @@ -186570,6 +186519,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.PipeRegs[3].PipeRegs), line:2029:48, endln:2029:53 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.PipeRegs[3] \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.UnitTypes[3].UnitTypes), line:2030:49, endln:2030:54 |vpiParent: \_hier_path: (Implementation.UnitTypes[3]), line:2030:24, endln:2030:55 @@ -186587,9 +186537,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.UnitTypes[3] |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_implementation_t), line:1720:11, endln:1724:4 - |vpiName:Implementation.UnitTypes[3] - |vpiExpr: - \_operation: , line:2072:25, endln:2072:43 |vpiActual: \_ref_obj: (Implementation), line:2030:24, endln:2030:38 |vpiParent: @@ -186599,6 +186546,7 @@ design: (work@top) \_bit_select: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Implementation.UnitTypes[3].UnitTypes), line:2030:49, endln:2030:54 |vpiExpr: \_operation: , line:2072:25, endln:2072:43 + |vpiName:Implementation.UnitTypes[3] \_int_typespec: , line:1505:14, endln:1505:26 |vpiParent: \_ref_typespec: @@ -191223,9 +191171,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -191239,6 +191184,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[0].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -191492,9 +191438,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -191508,6 +191451,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.IntFmtMask |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[1].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -191761,9 +191705,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -191777,6 +191718,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.IntFmtMask |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[2].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: @@ -192030,9 +191972,6 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.Features.IntFmtMask |vpiActual: \_struct_typespec: (fpnew_pkg::fpu_features_t), line:1662:11, endln:1668:4 - |vpiName:Features.IntFmtMask - |vpiExpr: - \_operation: , line:2071:25, endln:2071:37 |vpiActual: \_ref_obj: (Features), line:2028:24, endln:2028:32 |vpiParent: @@ -192046,6 +191985,7 @@ design: (work@top) |vpiFullName:work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.IntFmtMask |vpiExpr: \_operation: , line:2071:25, endln:2071:37 + |vpiName:Features.IntFmtMask |vpiLhs: \_parameter: (work@top.i_ariane.ex_stage_i.fpu_gen.fpu_i.fpu_gen.i_fpnew_bulk.gen_operation_groups[3].i_opgroup_block.IntFmtMask), line:1964:41, endln:1964:51 |vpiParamAssign: diff --git a/tests/ArrayExprFuncArg/ArrayExprFuncArg.log b/tests/ArrayExprFuncArg/ArrayExprFuncArg.log index 74f4d02405..ebaac73185 100644 --- a/tests/ArrayExprFuncArg/ArrayExprFuncArg.log +++ b/tests/ArrayExprFuncArg/ArrayExprFuncArg.log @@ -561,8 +561,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 9 array_var 1 -assign_stmt 2 -assignment 3 +assignment 5 begin 9 bit_select 8 constant 148 @@ -592,8 +591,7 @@ sys_task_call 4 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 9 array_var 1 -assign_stmt 4 -assignment 6 +assignment 10 begin 13 bit_select 12 constant 148 @@ -919,13 +917,13 @@ design: (work@main) \_function: (work@top.ASSIGN_VADDR), line:10:1, endln:14:12 |vpiFullName:work@top.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:11:9, endln:11:18 + \_assignment: , line:11:9, endln:11:18 |vpiParent: \_for_stmt: (work@top.ASSIGN_VADDR), line:11:4, endln:11:7 |vpiRhs: \_constant: , line:11:17, endln:11:18 |vpiParent: - \_assign_stmt: , line:11:9, endln:11:18 + \_assignment: , line:11:9, endln:11:18 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -933,7 +931,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@top.ASSIGN_VADDR.i), line:11:13, endln:11:14 |vpiParent: - \_assign_stmt: , line:11:9, endln:11:18 + \_assignment: , line:11:9, endln:11:18 |vpiTypespec: \_ref_typespec: (work@top.ASSIGN_VADDR.i) |vpiParent: @@ -1123,13 +1121,13 @@ design: (work@main) \_begin: (work@top.MAX_VADDR_CNT), line:27:5, endln:31:8 |vpiFullName:work@top.MAX_VADDR_CNT |vpiForInitStmt: - \_assign_stmt: , line:27:10, endln:27:19 + \_assignment: , line:27:10, endln:27:19 |vpiParent: \_for_stmt: (work@top.MAX_VADDR_CNT), line:27:5, endln:27:8 |vpiRhs: \_constant: , line:27:18, endln:27:19 |vpiParent: - \_assign_stmt: , line:27:10, endln:27:19 + \_assignment: , line:27:10, endln:27:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1137,7 +1135,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@top.MAX_VADDR_CNT.i), line:27:14, endln:27:15 |vpiParent: - \_assign_stmt: , line:27:10, endln:27:19 + \_assignment: , line:27:10, endln:27:19 |vpiTypespec: \_ref_typespec: (work@top.MAX_VADDR_CNT.i) |vpiParent: @@ -1665,7 +1663,7 @@ design: (work@main) \_function: (work@main.top1.ASSIGN_VADDR), line:10:1, endln:14:12 |vpiFullName:work@main.top1.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:11:9, endln:11:18 + \_assignment: , line:11:9, endln:11:18 |vpiParent: \_for_stmt: (work@main.top1.ASSIGN_VADDR), line:11:4, endln:11:7 |vpiRhs: @@ -1673,7 +1671,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@main.top1.ASSIGN_VADDR.i), line:11:13, endln:11:14 |vpiParent: - \_assign_stmt: , line:11:9, endln:11:18 + \_assignment: , line:11:9, endln:11:18 |vpiTypespec: \_ref_typespec: (work@main.top1.ASSIGN_VADDR.i) |vpiParent: @@ -1846,7 +1844,7 @@ design: (work@main) \_begin: (work@main.top1.MAX_VADDR_CNT), line:27:5, endln:31:8 |vpiFullName:work@main.top1.MAX_VADDR_CNT |vpiForInitStmt: - \_assign_stmt: , line:27:10, endln:27:19 + \_assignment: , line:27:10, endln:27:19 |vpiParent: \_for_stmt: (work@main.top1.MAX_VADDR_CNT), line:27:5, endln:27:8 |vpiRhs: @@ -1854,7 +1852,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@main.top1.MAX_VADDR_CNT.i), line:27:14, endln:27:15 |vpiParent: - \_assign_stmt: , line:27:10, endln:27:19 + \_assignment: , line:27:10, endln:27:19 |vpiTypespec: \_ref_typespec: (work@main.top1.MAX_VADDR_CNT.i) |vpiParent: diff --git a/tests/ArrayMethodIterator/ArrayMethodIterator.log b/tests/ArrayMethodIterator/ArrayMethodIterator.log index 8f6de5cd66..3d281514aa 100644 --- a/tests/ArrayMethodIterator/ArrayMethodIterator.log +++ b/tests/ArrayMethodIterator/ArrayMethodIterator.log @@ -168,8 +168,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 3 -assignment 1 +assignment 4 begin 1 class_defn 3 class_typespec 4 @@ -193,8 +192,7 @@ type_parameter 2 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 6 -assign_stmt 3 -assignment 2 +assignment 5 begin 2 class_defn 3 class_typespec 4 @@ -467,7 +465,6 @@ design: (work@top) \_hier_path: (callbacks_to_append), line:19:32, endln:19:90 |vpiParent: \_assignment: , line:19:3, endln:19:90 - |vpiName:callbacks_to_append |vpiActual: \_ref_obj: (pkg::uvm_callbacks::get_all::callbacks_to_append), line:19:32, endln:19:51 |vpiParent: @@ -493,7 +490,6 @@ design: (work@top) \_hier_path: (cb_.get_inst_id), line:19:73, endln:19:88 |vpiParent: \_method_func_call: (unique), line:19:52, endln:19:58 - |vpiName:cb_.get_inst_id |vpiActual: \_ref_obj: (cb_), line:19:73, endln:19:76 |vpiParent: @@ -509,6 +505,8 @@ design: (work@top) |vpiFullName:pkg::uvm_callbacks::get_all::callbacks_to_append::get_inst_id |vpiActual: \_int_var: (pkg::uvm_callback::get_inst_id), line:7:8, endln:7:19 + |vpiName:cb_.get_inst_id + |vpiName:callbacks_to_append |vpiLhs: \_ref_obj: (pkg::uvm_callbacks::get_all::unique_callbacks_to_append), line:19:3, endln:19:29 |vpiParent: @@ -681,7 +679,6 @@ design: (work@top) \_hier_path: (cb_.get_inst_id), line:19:73, endln:19:88 |vpiParent: \_assignment: , line:19:3, endln:19:90 - |vpiName:cb_.get_inst_id |vpiActual: \_ref_obj: (cb_), line:19:73, endln:19:76 |vpiParent: @@ -693,6 +690,7 @@ design: (work@top) \_hier_path: (cb_.get_inst_id), line:19:73, endln:19:88 |vpiName:get_inst_id |vpiFullName:pkg::uvm_callbacks::get_all::get_inst_id + |vpiName:cb_.get_inst_id \_assignment: , line:19:3, endln:19:90 |vpiParent: \_begin: (pkg::uvm_callbacks::get_all), line:15:3, endln:15:29 @@ -702,7 +700,6 @@ design: (work@top) \_hier_path: (callbacks_to_append), line:19:32, endln:19:90 |vpiParent: \_assignment: , line:19:3, endln:19:90 - |vpiName:callbacks_to_append |vpiActual: \_ref_obj: (pkg::uvm_callbacks::get_all::callbacks_to_append), line:19:32, endln:19:51 |vpiParent: @@ -711,6 +708,7 @@ design: (work@top) |vpiFullName:pkg::uvm_callbacks::get_all::callbacks_to_append |vpiActual: \_method_func_call: (unique), line:19:52, endln:19:58 + |vpiName:callbacks_to_append |vpiLhs: \_ref_obj: (pkg::uvm_callbacks::get_all::unique_callbacks_to_append), line:19:3, endln:19:29 |vpiParent: diff --git a/tests/ArrayVarName/ArrayVarName.log b/tests/ArrayVarName/ArrayVarName.log index 7b8074b8b3..c81eca474f 100644 --- a/tests/ArrayVarName/ArrayVarName.log +++ b/tests/ArrayVarName/ArrayVarName.log @@ -106,7 +106,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1 array_var 1 -assign_stmt 1 +assignment 1 begin 1 bit_select 1 constant 7 @@ -132,7 +132,7 @@ return_stmt 1 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 1 array_var 4 -assign_stmt 2 +assignment 2 begin 2 bit_select 2 constant 7 @@ -177,7 +177,7 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.get_a1.a), line:5:11, endln:5:12 |vpiParent: - \_assign_stmt: , line:5:11, endln:5:26 + \_assignment: , line:5:11, endln:5:26 |vpiTypespec: \_ref_typespec: (work@top.get_a1.a) |vpiParent: @@ -226,13 +226,15 @@ design: (work@top) |vpiVariables: \_array_var: (work@top.get_a1.a), line:5:11, endln:5:12 |vpiStmt: - \_assign_stmt: , line:5:11, endln:5:26 + \_assignment: , line:5:11, endln:5:26 |vpiParent: \_begin: (work@top.get_a1), line:6:7, endln:6:19 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:5:19, endln:5:26 |vpiParent: - \_assign_stmt: , line:5:11, endln:5:26 + \_assignment: , line:5:11, endln:5:26 |vpiOpType:75 |vpiOperand: \_constant: , line:5:21, endln:5:22 @@ -419,13 +421,15 @@ design: (work@top) |vpiFullName:work@top.get_a1.a |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:5:11, endln:5:26 + \_assignment: , line:5:11, endln:5:26 |vpiParent: \_begin: (work@top.get_a1), line:6:7, endln:6:19 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:5:19, endln:5:26 |vpiParent: - \_assign_stmt: , line:5:11, endln:5:26 + \_assignment: , line:5:11, endln:5:26 |vpiOpType:75 |vpiOperand: \_constant: , line:5:21, endln:5:22 @@ -434,7 +438,7 @@ design: (work@top) |vpiLhs: \_array_var: (work@top.get_a1.a), line:5:11, endln:5:12 |vpiParent: - \_assign_stmt: , line:5:11, endln:5:26 + \_assignment: , line:5:11, endln:5:26 |vpiTypespec: \_ref_typespec: (work@top.get_a1.a) |vpiParent: diff --git a/tests/AssignPlus/AssignPlus.log b/tests/AssignPlus/AssignPlus.log index 16e8bf7cc1..3146d9a54c 100644 --- a/tests/AssignPlus/AssignPlus.log +++ b/tests/AssignPlus/AssignPlus.log @@ -191,8 +191,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 bit_select 36 constant 48 cont_assign 12 @@ -215,8 +214,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 bit_select 66 constant 48 cont_assign 22 @@ -298,7 +296,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignPlus/dut.sv, line:1:1, endln:11:10 |vpiForInitStmt: - \_assign_stmt: , line:5:10, endln:5:22 + \_assignment: , line:5:10, endln:5:22 |vpiParent: \_gen_for: |vpiRhs: @@ -310,7 +308,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:5:17, endln:5:18 |vpiParent: - \_assign_stmt: , line:5:10, endln:5:22 + \_assignment: , line:5:10, endln:5:22 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: diff --git a/tests/AssignSubs/AssignSubs.log b/tests/AssignSubs/AssignSubs.log index b123c1d5db..ab5fdc317c 100644 --- a/tests/AssignSubs/AssignSubs.log +++ b/tests/AssignSubs/AssignSubs.log @@ -182,8 +182,7 @@ AST_DEBUG_END always 2 array_typespec 1 array_var 1 -assign_stmt 1 -assignment 2 +assignment 3 begin 3 bit_select 2 constant 27 @@ -216,8 +215,7 @@ unsupported_typespec 1 always 3 array_typespec 1 array_var 1 -assign_stmt 1 -assignment 3 +assignment 4 begin 4 bit_select 3 constant 27 @@ -375,7 +373,7 @@ design: (work@dut) |vpiParent: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/AssignSubs/dut.sv, line:7:1, endln:19:10 |vpiForInitStmt: - \_assign_stmt: , line:14:7, endln:14:19 + \_assignment: , line:14:7, endln:14:19 |vpiParent: \_gen_for: |vpiRhs: @@ -387,7 +385,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.i), line:14:14, endln:14:15 |vpiParent: - \_assign_stmt: , line:14:7, endln:14:19 + \_assignment: , line:14:7, endln:14:19 |vpiTypespec: \_ref_typespec: (work@dut.i) |vpiParent: diff --git a/tests/Assignments/Assignments.log b/tests/Assignments/Assignments.log index 69eed84521..646215d6c1 100644 --- a/tests/Assignments/Assignments.log +++ b/tests/Assignments/Assignments.log @@ -588,8 +588,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 1 -assignment 10 +assignment 11 begin 2 bit_select 2 bit_typespec 1 @@ -626,8 +625,7 @@ task 9 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 2 -assignment 20 +assignment 22 begin 4 bit_select 4 bit_typespec 1 @@ -1222,7 +1220,6 @@ design: (work@dut) \_hier_path: (cover_info.size), line:6:22, endln:6:39 |vpiParent: \_operation: , line:6:22, endln:6:43 - |vpiName:cover_info.size |vpiActual: \_ref_obj: (cover_info), line:6:22, endln:6:32 |vpiParent: @@ -1235,6 +1232,7 @@ design: (work@dut) |vpiParent: \_hier_path: (cover_info.size), line:6:22, endln:6:39 |vpiName:size + |vpiName:cover_info.size |vpiOperand: \_constant: , line:6:42, endln:6:43 |vpiParent: @@ -1357,13 +1355,13 @@ design: (work@dut) \_begin: (work@dut.uvm_packer::get_packed_bits), line:7:5, endln:7:38 |vpiFullName:work@dut.uvm_packer::get_packed_bits |vpiForInitStmt: - \_assign_stmt: , line:10:10, endln:10:17 + \_assignment: , line:10:10, endln:10:17 |vpiParent: \_for_stmt: (work@dut.uvm_packer::get_packed_bits), line:10:5, endln:10:8 |vpiRhs: \_constant: , line:10:16, endln:10:17 |vpiParent: - \_assign_stmt: , line:10:10, endln:10:17 + \_assignment: , line:10:10, endln:10:17 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1371,7 +1369,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.uvm_packer::get_packed_bits.i), line:10:14, endln:10:15 |vpiParent: - \_assign_stmt: , line:10:10, endln:10:17 + \_assignment: , line:10:10, endln:10:17 |vpiTypespec: \_ref_typespec: (work@dut.uvm_packer::get_packed_bits.i) |vpiParent: @@ -1783,7 +1781,6 @@ design: (work@dut) \_hier_path: (cover_info.size), line:6:22, endln:6:39 |vpiParent: \_operation: , line:6:22, endln:6:43 - |vpiName:cover_info.size |vpiActual: \_ref_obj: (cover_info), line:6:22, endln:6:32 |vpiParent: @@ -1796,6 +1793,7 @@ design: (work@dut) |vpiParent: \_hier_path: (cover_info.size), line:6:22, endln:6:39 |vpiName:size + |vpiName:cover_info.size |vpiOperand: \_constant: , line:6:42, endln:6:43 |vpiArgument: @@ -1900,7 +1898,7 @@ design: (work@dut) \_begin: (work@dut.uvm_packer::get_packed_bits), line:7:5, endln:7:38 |vpiFullName:work@dut.uvm_packer::get_packed_bits |vpiForInitStmt: - \_assign_stmt: , line:10:10, endln:10:17 + \_assignment: , line:10:10, endln:10:17 |vpiParent: \_for_stmt: (work@dut.uvm_packer::get_packed_bits), line:10:5, endln:10:8 |vpiRhs: @@ -1908,7 +1906,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.uvm_packer::get_packed_bits.i), line:10:14, endln:10:15 |vpiParent: - \_assign_stmt: , line:10:10, endln:10:17 + \_assignment: , line:10:10, endln:10:17 |vpiTypespec: \_ref_typespec: (work@dut.uvm_packer::get_packed_bits.i) |vpiParent: diff --git a/tests/AssumeProp/AssumeProp.log b/tests/AssumeProp/AssumeProp.log index d38bb6b146..28065c1002 100644 --- a/tests/AssumeProp/AssumeProp.log +++ b/tests/AssumeProp/AssumeProp.log @@ -230,7 +230,6 @@ design: (work@dut) \_hier_path: (slv_req_i.aw_valid), line:4:51, endln:4:69 |vpiParent: \_operation: , line:4:51, endln:5:80 - |vpiName:slv_req_i.aw_valid |vpiActual: \_ref_obj: (slv_req_i), line:4:51, endln:4:60 |vpiParent: @@ -242,6 +241,7 @@ design: (work@dut) \_hier_path: (slv_req_i.aw_valid), line:4:51, endln:4:69 |vpiName:aw_valid |vpiFullName:work@dut.aw_select.aw_valid + |vpiName:slv_req_i.aw_valid |vpiOperand: \_operation: , line:5:51, endln:5:79 |vpiParent: @@ -325,7 +325,6 @@ design: (work@dut) \_hier_path: (slv_req_i.aw_valid), line:4:51, endln:4:69 |vpiParent: \_operation: , line:4:51, endln:5:80 - |vpiName:slv_req_i.aw_valid |vpiActual: \_ref_obj: (slv_req_i), line:4:51, endln:4:60 |vpiParent: @@ -337,6 +336,7 @@ design: (work@dut) \_hier_path: (slv_req_i.aw_valid), line:4:51, endln:4:69 |vpiName:aw_valid |vpiFullName:work@dut.aw_select.aw_valid + |vpiName:slv_req_i.aw_valid |vpiOperand: \_operation: , line:5:51, endln:5:79 |vpiParent: diff --git a/tests/BindMethod/BindMethod.log b/tests/BindMethod/BindMethod.log index 39b5f4e390..f4d25b3804 100644 --- a/tests/BindMethod/BindMethod.log +++ b/tests/BindMethod/BindMethod.log @@ -107,8 +107,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 2 class_defn 4 class_typespec 5 @@ -127,8 +126,7 @@ task 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 4 +assignment 6 begin 4 class_defn 4 class_typespec 5 @@ -208,7 +206,6 @@ design: (unnamed) \_hier_path: (cbs.first), line:20:15, endln:20:26 |vpiParent: \_assignment: , line:20:3, endln:20:26 - |vpiName:cbs.first |vpiActual: \_ref_obj: (cbs), line:20:15, endln:20:18 |vpiParent: @@ -223,11 +220,11 @@ design: (unnamed) |vpiName:first |vpiFunction: \_function: (uvm::uvm_vreg_field_cb_iter::first), line:5:1, endln:5:7 + |vpiName:cbs.first |vpiLhs: \_hier_path: (cbs.fname), line:20:3, endln:20:12 |vpiParent: \_assignment: , line:20:3, endln:20:26 - |vpiName:cbs.fname |vpiActual: \_ref_obj: (cbs), line:20:7, endln:20:12 |vpiParent: @@ -242,6 +239,7 @@ design: (unnamed) |vpiName:fname |vpiActual: \_int_var: (uvm::uvm_vreg_field_cbs::fname), line:10:7, endln:10:12 + |vpiName:cbs.fname |vpiInstance: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/BindMethod/dut.sv, line:1:1, endln:23:11 |uhdmtopPackages: @@ -315,7 +313,6 @@ design: (unnamed) \_hier_path: (cbs.first), line:20:15, endln:20:26 |vpiParent: \_assignment: , line:20:3, endln:20:26 - |vpiName:cbs.first |vpiActual: \_ref_obj: (cbs), line:20:15, endln:20:18 |vpiParent: @@ -330,11 +327,11 @@ design: (unnamed) |vpiName:first |vpiFunction: \_function: (uvm::uvm_vreg_field_cb_iter::first), line:5:1, endln:5:7 + |vpiName:cbs.first |vpiLhs: \_hier_path: (cbs.fname), line:20:3, endln:20:12 |vpiParent: \_assignment: , line:20:3, endln:20:26 - |vpiName:cbs.fname |vpiActual: \_ref_obj: (cbs), line:20:7, endln:20:12 |vpiParent: @@ -349,6 +346,7 @@ design: (unnamed) |vpiName:fname |vpiActual: \_int_var: (uvm::uvm_vreg_field_cbs::fname), line:10:7, endln:10:12 + |vpiName:cbs.fname |vpiInstance: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/BindMethod/dut.sv, line:1:1, endln:23:11 |vpiClassDefn: @@ -446,7 +444,6 @@ design: (unnamed) \_hier_path: (cbs.first), line:20:15, endln:20:26 |vpiParent: \_assignment: , line:20:3, endln:20:26 - |vpiName:cbs.first |vpiActual: \_ref_obj: (cbs), line:20:15, endln:20:18 |vpiParent: @@ -459,11 +456,11 @@ design: (unnamed) |vpiParent: \_hier_path: (cbs.first), line:20:15, endln:20:26 |vpiName:first + |vpiName:cbs.first |vpiLhs: \_hier_path: (cbs.fname), line:20:3, endln:20:12 |vpiParent: \_assignment: , line:20:3, endln:20:26 - |vpiName:cbs.fname |vpiActual: \_ref_obj: (cbs), line:20:7, endln:20:12 |vpiParent: @@ -476,6 +473,7 @@ design: (unnamed) |vpiParent: \_hier_path: (cbs.fname), line:20:3, endln:20:12 |vpiName:fname + |vpiName:cbs.fname \_task: (uvm::uvm_vreg::write), line:18:1, endln:21:8 |vpiParent: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/BindMethod/dut.sv, line:1:1, endln:23:11 diff --git a/tests/BindStmt2/BindStmt2.log b/tests/BindStmt2/BindStmt2.log index 5e6e89c636..8f6689176e 100644 --- a/tests/BindStmt2/BindStmt2.log +++ b/tests/BindStmt2/BindStmt2.log @@ -2581,7 +2581,6 @@ design: (work@rv_dm) \_hier_path: (dmi_req.addr), line:62:22, endln:62:34 |vpiParent: \_port: (dmi_req_addr), line:45:21, endln:45:33 - |vpiName:dmi_req.addr |vpiActual: \_ref_obj: (dmi_req), line:62:22, endln:62:29 |vpiParent: @@ -2595,6 +2594,7 @@ design: (work@rv_dm) \_hier_path: (dmi_req.addr), line:62:22, endln:62:34 |vpiName:addr |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_addr.addr + |vpiName:dmi_req.addr |vpiLowConn: \_ref_obj: (u_dmidpi.dmi_req_addr), line:62:6, endln:62:18 |vpiParent: @@ -2622,7 +2622,6 @@ design: (work@rv_dm) \_hier_path: (dmi_req.op), line:63:22, endln:63:32 |vpiParent: \_port: (dmi_req_op), line:46:21, endln:46:31 - |vpiName:dmi_req.op |vpiActual: \_ref_obj: (dmi_req), line:63:22, endln:63:29 |vpiParent: @@ -2636,6 +2635,7 @@ design: (work@rv_dm) \_hier_path: (dmi_req.op), line:63:22, endln:63:32 |vpiName:op |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_op.op + |vpiName:dmi_req.op |vpiLowConn: \_ref_obj: (u_dmidpi.dmi_req_op), line:63:6, endln:63:16 |vpiParent: @@ -2663,7 +2663,6 @@ design: (work@rv_dm) \_hier_path: (dmi_req.data), line:64:22, endln:64:34 |vpiParent: \_port: (dmi_req_data), line:47:21, endln:47:33 - |vpiName:dmi_req.data |vpiActual: \_ref_obj: (dmi_req), line:64:22, endln:64:29 |vpiParent: @@ -2677,6 +2676,7 @@ design: (work@rv_dm) \_hier_path: (dmi_req.data), line:64:22, endln:64:34 |vpiName:data |vpiFullName:work@rv_dm.u_dmidpi.dmi_req_data.data + |vpiName:dmi_req.data |vpiLowConn: \_ref_obj: (u_dmidpi.dmi_req_data), line:64:6, endln:64:18 |vpiParent: @@ -2750,7 +2750,6 @@ design: (work@rv_dm) \_hier_path: (dmi_rsp.data), line:67:22, endln:67:34 |vpiParent: \_port: (dmi_rsp_data), line:50:21, endln:50:33 - |vpiName:dmi_rsp.data |vpiActual: \_ref_obj: (dmi_rsp), line:67:22, endln:67:29 |vpiParent: @@ -2764,6 +2763,7 @@ design: (work@rv_dm) \_hier_path: (dmi_rsp.data), line:67:22, endln:67:34 |vpiName:data |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_data.data + |vpiName:dmi_rsp.data |vpiLowConn: \_ref_obj: (u_dmidpi.dmi_rsp_data), line:67:6, endln:67:18 |vpiParent: @@ -2791,7 +2791,6 @@ design: (work@rv_dm) \_hier_path: (dmi_rsp.resp), line:68:22, endln:68:34 |vpiParent: \_port: (dmi_rsp_resp), line:51:21, endln:51:33 - |vpiName:dmi_rsp.resp |vpiActual: \_ref_obj: (dmi_rsp), line:68:22, endln:68:29 |vpiParent: @@ -2805,6 +2804,7 @@ design: (work@rv_dm) \_hier_path: (dmi_rsp.resp), line:68:22, endln:68:34 |vpiName:resp |vpiFullName:work@rv_dm.u_dmidpi.dmi_rsp_resp.resp + |vpiName:dmi_rsp.resp |vpiLowConn: \_ref_obj: (u_dmidpi.dmi_rsp_resp), line:68:6, endln:68:18 |vpiParent: diff --git a/tests/BitSelect/BitSelect.log b/tests/BitSelect/BitSelect.log index a133cfd2f6..c8df928e15 100644 --- a/tests/BitSelect/BitSelect.log +++ b/tests/BitSelect/BitSelect.log @@ -191,7 +191,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 3. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 5 bit_typespec 4 constant 57 @@ -217,7 +217,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 5 bit_typespec 4 constant 57 @@ -411,7 +411,7 @@ design: (work@dut) |vpiParent: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/BitSelect/dut.sv, line:6:1, endln:15:10 |vpiForInitStmt: - \_assign_stmt: , line:10:6, endln:10:18 + \_assignment: , line:10:6, endln:10:18 |vpiParent: \_gen_for: |vpiRhs: @@ -423,7 +423,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.i), line:10:13, endln:10:14 |vpiParent: - \_assign_stmt: , line:10:6, endln:10:18 + \_assignment: , line:10:6, endln:10:18 |vpiTypespec: \_ref_typespec: (work@dut.i) |vpiParent: diff --git a/tests/BitSelectExpr/BitSelectExpr.log b/tests/BitSelectExpr/BitSelectExpr.log index cc2d486565..08aca8dab6 100644 --- a/tests/BitSelectExpr/BitSelectExpr.log +++ b/tests/BitSelectExpr/BitSelectExpr.log @@ -238,7 +238,6 @@ design: (work@top) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:9:11, endln:9:25 |vpiParent: \_cont_assign: , line:9:11, endln:9:40 - |vpiName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_bit_select: (sram_otp_key_o[2 - 2]), line:9:11, endln:9:25 |vpiParent: @@ -272,6 +271,7 @@ design: (work@top) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:9:11, endln:9:25 |vpiName:nonce |vpiFullName:sram_otp_key_o[2 - 2].nonce + |vpiName:sram_otp_key_o[2 - 2].nonce |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectExpr/dut.sv, line:1:1, endln:12:10 |vpiName:work@top @@ -367,7 +367,6 @@ design: (work@top) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:9:11, endln:9:25 |vpiParent: \_cont_assign: , line:9:11, endln:9:40 - |vpiName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_bit_select: (sram_otp_key_o[2 - 2]), line:9:11, endln:9:25 |vpiParent: @@ -390,6 +389,7 @@ design: (work@top) |vpiFullName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_typespec_member: (nonce), line:4:14, endln:4:19 + |vpiName:sram_otp_key_o[2 - 2].nonce \_weaklyReferenced: \_int_typespec: , line:4:7, endln:4:10 |vpiParent: @@ -439,7 +439,6 @@ design: (work@top) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:9:11, endln:9:25 |vpiParent: \_cont_assign: , line:9:11, endln:9:40 - |vpiName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_bit_select: (sram_otp_key_o[2 - 2]), line:9:11, endln:9:25 |vpiParent: @@ -473,6 +472,7 @@ design: (work@top) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:9:11, endln:9:25 |vpiName:nonce |vpiFullName:sram_otp_key_o[2 - 2].nonce + |vpiName:sram_otp_key_o[2 - 2].nonce =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/BitSelectHier/BitSelectHier.log b/tests/BitSelectHier/BitSelectHier.log index 6fd2ebfe8f..69d4f33fe1 100644 --- a/tests/BitSelectHier/BitSelectHier.log +++ b/tests/BitSelectHier/BitSelectHier.log @@ -294,7 +294,6 @@ design: (unnamed) \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiParent: \_assignment: , line:43:4, endln:43:43 - |vpiName:this.in_use.get_start_offset |vpiActual: \_ref_obj: (this), line:43:15, endln:43:21 |vpiParent: @@ -310,6 +309,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiName:get_start_offset + |vpiName:this.in_use.get_start_offset |vpiLhs: \_ref_obj: (pack::uvm_mem_mam::reconfigure::top), line:43:4, endln:43:7 |vpiParent: @@ -438,7 +438,6 @@ design: (unnamed) \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiParent: \_assignment: , line:43:4, endln:43:43 - |vpiName:this.in_use.get_start_offset |vpiActual: \_ref_obj: (this), line:43:15, endln:43:21 |vpiParent: @@ -460,6 +459,7 @@ design: (unnamed) |vpiName:get_start_offset |vpiActual: \_function: (pack::uvm_mem_region::get_start_offset), line:16:4, endln:16:10 + |vpiName:this.in_use.get_start_offset |vpiLhs: \_ref_obj: (pack::uvm_mem_mam::reconfigure::top), line:43:4, endln:43:7 |vpiParent: @@ -578,7 +578,6 @@ design: (unnamed) \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiParent: \_assignment: , line:43:4, endln:43:43 - |vpiName:this.in_use.get_start_offset |vpiActual: \_ref_obj: (this), line:43:15, endln:43:21 |vpiParent: @@ -594,6 +593,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiName:get_start_offset + |vpiName:this.in_use.get_start_offset |vpiLhs: \_ref_obj: (pack::uvm_mem_mam::reconfigure::top), line:43:4, endln:43:7 |vpiParent: @@ -641,7 +641,6 @@ design: (unnamed) \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiParent: \_assignment: , line:43:4, endln:43:43 - |vpiName:this.in_use.get_start_offset |vpiActual: \_ref_obj: (this), line:43:15, endln:43:21 |vpiParent: @@ -657,6 +656,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.in_use.get_start_offset), line:43:10, endln:43:43 |vpiName:get_start_offset + |vpiName:this.in_use.get_start_offset |vpiLhs: \_ref_obj: (pack::uvm_mem_mam::reconfigure::top), line:43:4, endln:43:7 |vpiParent: diff --git a/tests/BitSelectPartSelectInFunction/BitSelectPartSelectInFunction.log b/tests/BitSelectPartSelectInFunction/BitSelectPartSelectInFunction.log index 860f77749b..6beb799f66 100644 --- a/tests/BitSelectPartSelectInFunction/BitSelectPartSelectInFunction.log +++ b/tests/BitSelectPartSelectInFunction/BitSelectPartSelectInFunction.log @@ -189,8 +189,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 bit_select 1 constant 33 @@ -219,8 +218,7 @@ var_select 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 2 +assignment 3 begin 2 bit_select 2 constant 33 diff --git a/tests/BitSelectSelect/BitSelectSelect.log b/tests/BitSelectSelect/BitSelectSelect.log index d3b479aaeb..bf7185b624 100644 --- a/tests/BitSelectSelect/BitSelectSelect.log +++ b/tests/BitSelectSelect/BitSelectSelect.log @@ -256,7 +256,6 @@ design: (work@top) \_hier_path: (a[0][0].min_v), line:8:11, endln:8:12 |vpiParent: \_cont_assign: , line:8:11, endln:8:29 - |vpiName:a[0][0].min_v |vpiActual: \_bit_select: (a[0]), line:8:11, endln:8:12 |vpiParent: @@ -286,6 +285,7 @@ design: (work@top) \_hier_path: (a[0][0].min_v), line:8:11, endln:8:12 |vpiName:min_v |vpiFullName:a[0][0].min_v + |vpiName:a[0][0].min_v |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitSelectSelect/dut.sv, line:2:1, endln:9:10 |vpiName:work@top @@ -405,7 +405,6 @@ design: (work@top) \_hier_path: (a[0][0].min_v), line:8:11, endln:8:12 |vpiParent: \_cont_assign: , line:8:11, endln:8:29 - |vpiName:a[0][0].min_v |vpiActual: \_bit_select: (a[0]), line:8:11, endln:8:12 |vpiParent: @@ -443,6 +442,7 @@ design: (work@top) |vpiFullName:a[0][0].min_v |vpiActual: \_typespec_member: (min_v), line:4:19, endln:4:24 + |vpiName:a[0][0].min_v \_weaklyReferenced: \_logic_typespec: , line:4:7, endln:4:18 |vpiParent: @@ -531,7 +531,6 @@ design: (work@top) \_hier_path: (a[0][0].min_v), line:8:11, endln:8:12 |vpiParent: \_cont_assign: , line:8:11, endln:8:29 - |vpiName:a[0][0].min_v |vpiActual: \_bit_select: (a[0]), line:8:11, endln:8:12 |vpiParent: @@ -555,6 +554,7 @@ design: (work@top) \_hier_path: (a[0][0].min_v), line:8:11, endln:8:12 |vpiName:min_v |vpiFullName:a[0][0].min_v + |vpiName:a[0][0].min_v =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/BitsOp/BitsOp.log b/tests/BitsOp/BitsOp.log index a34de88c0c..2e6115ae6f 100644 --- a/tests/BitsOp/BitsOp.log +++ b/tests/BitsOp/BitsOp.log @@ -4292,7 +4292,6 @@ design: (work@dut) \_hier_path: (tl_h_i.a_source), line:88:16, endln:88:31 |vpiParent: \_sys_func_call: ($bits), line:88:10, endln:88:32 - |vpiName:tl_h_i.a_source |vpiActual: \_ref_obj: (tl_h_i), line:88:16, endln:88:22 |vpiParent: @@ -4303,6 +4302,7 @@ design: (work@dut) |vpiParent: \_hier_path: (tl_h_i.a_source), line:88:16, endln:88:31 |vpiName:a_source + |vpiName:tl_h_i.a_source |vpiName:$bits |vpiOperand: \_constant: , line:88:33, endln:88:34 @@ -4338,7 +4338,6 @@ design: (work@dut) \_hier_path: (tl_h_i.a_size), line:89:16, endln:89:29 |vpiParent: \_sys_func_call: ($bits), line:89:10, endln:89:30 - |vpiName:tl_h_i.a_size |vpiActual: \_ref_obj: (tl_h_i), line:89:16, endln:89:22 |vpiParent: @@ -4349,6 +4348,7 @@ design: (work@dut) |vpiParent: \_hier_path: (tl_h_i.a_size), line:89:16, endln:89:29 |vpiName:a_size + |vpiName:tl_h_i.a_size |vpiName:$bits |vpiOperand: \_constant: , line:89:31, endln:89:32 diff --git a/tests/BitsStructMember/BitsStructMember.log b/tests/BitsStructMember/BitsStructMember.log index 970d97fce4..79b84124d3 100644 --- a/tests/BitsStructMember/BitsStructMember.log +++ b/tests/BitsStructMember/BitsStructMember.log @@ -13,8 +13,7 @@ [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 1 -assignment 1 +assignment 2 begin 3 bit_select 1 case_item 1 @@ -44,8 +43,7 @@ typespec_member 8 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 2 -assignment 2 +assignment 4 begin 6 bit_select 2 case_item 2 @@ -448,13 +446,13 @@ design: (work@top) \_begin: (work@top), line:21:18, endln:25:10 |vpiFullName:work@top |vpiForInitStmt: - \_assign_stmt: , line:22:14, endln:22:23 + \_assignment: , line:22:14, endln:22:23 |vpiParent: \_for_stmt: (work@top), line:22:9, endln:22:12 |vpiRhs: \_constant: , line:22:22, endln:22:23 |vpiParent: - \_assign_stmt: , line:22:14, endln:22:23 + \_assignment: , line:22:14, endln:22:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -462,7 +460,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:22:18, endln:22:19 |vpiParent: - \_assign_stmt: , line:22:14, endln:22:23 + \_assignment: , line:22:14, endln:22:23 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -538,7 +536,6 @@ design: (work@top) \_hier_path: (keymgr_data_i.strb[i]), line:23:36, endln:23:57 |vpiParent: \_operation: , line:23:35, endln:23:58 - |vpiName:keymgr_data_i.strb[i] |vpiActual: \_ref_obj: (keymgr_data_i), line:23:36, endln:23:49 |vpiParent: @@ -558,6 +555,7 @@ design: (work@top) |vpiFullName:work@top.keymgr_data_i.strb[i].i |vpiActual: \_int_var: (work@top.i), line:22:18, endln:22:19 + |vpiName:keymgr_data_i.strb[i] |vpiLhs: \_indexed_part_select: kmac_mask_o (work@top.kmac_mask_o), line:23:11, endln:23:30 |vpiParent: @@ -721,7 +719,7 @@ design: (work@top) \_begin: (work@top), line:21:18, endln:25:10 |vpiFullName:work@top |vpiForInitStmt: - \_assign_stmt: , line:22:14, endln:22:23 + \_assignment: , line:22:14, endln:22:23 |vpiParent: \_for_stmt: (work@top), line:22:9, endln:22:12 |vpiRhs: @@ -729,7 +727,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:22:18, endln:22:19 |vpiParent: - \_assign_stmt: , line:22:14, endln:22:23 + \_assignment: , line:22:14, endln:22:23 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -795,7 +793,6 @@ design: (work@top) \_hier_path: (keymgr_data_i.strb[i]), line:23:36, endln:23:57 |vpiParent: \_operation: , line:23:35, endln:23:58 - |vpiName:keymgr_data_i.strb[i] |vpiActual: \_ref_obj: (keymgr_data_i), line:23:36, endln:23:49 |vpiParent: @@ -819,6 +816,7 @@ design: (work@top) |vpiFullName:work@top.keymgr_data_i.strb[i].i |vpiActual: \_int_var: (work@top.i), line:22:18, endln:22:19 + |vpiName:keymgr_data_i.strb[i] |vpiLhs: \_indexed_part_select: kmac_mask_o (work@top.kmac_mask_o), line:23:11, endln:23:30 |vpiParent: diff --git a/tests/BlackBox/BlackBox.log b/tests/BlackBox/BlackBox.log index ed3a5a0ad2..417b1a5bfc 100644 --- a/tests/BlackBox/BlackBox.log +++ b/tests/BlackBox/BlackBox.log @@ -246,7 +246,6 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: \_cont_assign: , line:31:12, endln:31:54 - |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiActual: \_ref_obj: (nyuzi), line:31:16, endln:31:21 |vpiParent: @@ -275,6 +274,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:wb_writeback_en |vpiFullName:work@top.wb_writeback_en + |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiLhs: \_ref_obj: (work@top.o), line:31:12, endln:31:13 |vpiParent: @@ -367,7 +367,6 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: \_cont_assign: , line:31:12, endln:31:54 - |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiActual: \_ref_obj: (nyuzi), line:31:16, endln:31:21 |vpiParent: @@ -400,6 +399,7 @@ design: (work@top) |vpiFullName:work@top.wb_writeback_en |vpiActual: \_int_var: (work@top.nyuzi.core_gen[0].core.wb_writeback_en), line:7:5, endln:7:20 + |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiLhs: \_ref_obj: (work@top.o), line:31:12, endln:31:13 |vpiParent: diff --git a/tests/BlackBox/BlackBoxInst.log b/tests/BlackBox/BlackBoxInst.log index 6630a2db17..d3a85566b5 100644 --- a/tests/BlackBox/BlackBoxInst.log +++ b/tests/BlackBox/BlackBoxInst.log @@ -244,7 +244,6 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: \_cont_assign: , line:31:12, endln:31:54 - |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiActual: \_ref_obj: (nyuzi), line:31:16, endln:31:21 |vpiParent: @@ -273,6 +272,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:wb_writeback_en |vpiFullName:work@top.wb_writeback_en + |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiLhs: \_ref_obj: (work@top.o), line:31:12, endln:31:13 |vpiParent: @@ -325,7 +325,6 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: \_cont_assign: , line:31:12, endln:31:54 - |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiActual: \_ref_obj: (nyuzi), line:31:16, endln:31:21 |vpiParent: @@ -354,6 +353,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:wb_writeback_en |vpiFullName:work@top.wb_writeback_en + |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiLhs: \_ref_obj: (work@top.o), line:31:12, endln:31:13 |vpiParent: diff --git a/tests/BlackBox/BlackBoxSubMod.log b/tests/BlackBox/BlackBoxSubMod.log index 2feab88c3c..549d0e3152 100644 --- a/tests/BlackBox/BlackBoxSubMod.log +++ b/tests/BlackBox/BlackBoxSubMod.log @@ -224,7 +224,6 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: \_cont_assign: , line:31:12, endln:31:54 - |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiActual: \_ref_obj: (nyuzi), line:31:16, endln:31:21 |vpiParent: @@ -253,6 +252,7 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:wb_writeback_en |vpiFullName:work@top.wb_writeback_en + |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiLhs: \_ref_obj: (work@top.o), line:31:12, endln:31:13 |vpiParent: @@ -294,7 +294,6 @@ design: (work@top) \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiParent: \_cont_assign: , line:31:12, endln:31:54 - |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiActual: \_ref_obj: (nyuzi), line:31:16, endln:31:21 |vpiParent: @@ -315,6 +314,7 @@ design: (work@top) |vpiParent: \_hier_path: (nyuzi.core_gen[0].core.wb_writeback_en), line:31:16, endln:31:54 |vpiName:core + |vpiName:nyuzi.core_gen[0].core.wb_writeback_en |vpiLhs: \_ref_obj: (work@top.o), line:31:12, endln:31:13 |vpiParent: diff --git a/tests/BlackParrotConf/BlackParrotConf.log b/tests/BlackParrotConf/BlackParrotConf.log index 82a5086062..684874f960 100644 --- a/tests/BlackParrotConf/BlackParrotConf.log +++ b/tests/BlackParrotConf/BlackParrotConf.log @@ -72094,7 +72094,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.multicore), line:5684:30, endln:5684:53 |vpiParent: \_param_assign: , line:5684:16, endln:5684:53 - |vpiName:proc_param_lp.multicore |vpiActual: \_ref_obj: (proc_param_lp), line:5684:44, endln:5684:53 |vpiParent: @@ -72105,6 +72104,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.multicore), line:5684:30, endln:5684:53 |vpiName:multicore + |vpiName:proc_param_lp.multicore |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.multicore_p), line:5684:16, endln:5684:27 |vpiParamAssign: @@ -72115,7 +72115,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:5686:30, endln:5686:52 |vpiParent: \_param_assign: , line:5686:16, endln:5686:52 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:5686:44, endln:5686:52 |vpiParent: @@ -72126,6 +72125,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:5686:30, endln:5686:52 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.cc_x_dim_p), line:5686:16, endln:5686:26 |vpiParamAssign: @@ -72136,7 +72136,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:5687:30, endln:5687:52 |vpiParent: \_param_assign: , line:5687:16, endln:5687:52 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:5687:44, endln:5687:52 |vpiParent: @@ -72147,6 +72146,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:5687:30, endln:5687:52 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.cc_y_dim_p), line:5687:16, endln:5687:26 |vpiParamAssign: @@ -72169,7 +72169,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:5690:29, endln:5690:51 |vpiParent: \_param_assign: , line:5690:16, endln:5690:51 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:5690:43, endln:5690:51 |vpiParent: @@ -72180,6 +72179,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:5690:29, endln:5690:51 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.ic_y_dim_p), line:5690:16, endln:5690:26 |vpiParamAssign: @@ -72202,7 +72202,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mc_y_dim), line:5692:29, endln:5692:51 |vpiParent: \_param_assign: , line:5692:16, endln:5692:51 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:5692:43, endln:5692:51 |vpiParent: @@ -72213,6 +72212,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:5692:29, endln:5692:51 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.mc_y_dim_p), line:5692:16, endln:5692:26 |vpiParamAssign: @@ -72223,7 +72223,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cac_x_dim), line:5693:30, endln:5693:53 |vpiParent: \_param_assign: , line:5693:16, endln:5693:53 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:5693:44, endln:5693:53 |vpiParent: @@ -72234,6 +72233,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:5693:30, endln:5693:53 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.cac_x_dim_p), line:5693:16, endln:5693:27 |vpiParamAssign: @@ -72256,7 +72256,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:5695:30, endln:5695:53 |vpiParent: \_param_assign: , line:5695:16, endln:5695:53 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:5695:44, endln:5695:53 |vpiParent: @@ -72267,6 +72266,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:5695:30, endln:5695:53 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.sac_x_dim_p), line:5695:16, endln:5695:27 |vpiParamAssign: @@ -72289,7 +72289,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cacc_type), line:5697:30, endln:5697:53 |vpiParent: \_param_assign: , line:5697:16, endln:5697:53 - |vpiName:proc_param_lp.cacc_type |vpiActual: \_ref_obj: (proc_param_lp), line:5697:44, endln:5697:53 |vpiParent: @@ -72300,6 +72299,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cacc_type), line:5697:30, endln:5697:53 |vpiName:cacc_type + |vpiName:proc_param_lp.cacc_type |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.cacc_type_p), line:5697:16, endln:5697:27 |vpiParamAssign: @@ -72310,7 +72310,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sacc_type), line:5698:30, endln:5698:53 |vpiParent: \_param_assign: , line:5698:16, endln:5698:53 - |vpiName:proc_param_lp.sacc_type |vpiActual: \_ref_obj: (proc_param_lp), line:5698:44, endln:5698:53 |vpiParent: @@ -72321,6 +72320,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sacc_type), line:5698:30, endln:5698:53 |vpiName:sacc_type + |vpiName:proc_param_lp.sacc_type |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.sacc_type_p), line:5698:16, endln:5698:27 |vpiParamAssign: @@ -72446,7 +72446,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.num_cce), line:5706:28, endln:5706:49 |vpiParent: \_param_assign: , line:5706:16, endln:5706:49 - |vpiName:proc_param_lp.num_cce |vpiActual: \_ref_obj: (proc_param_lp), line:5706:42, endln:5706:49 |vpiParent: @@ -72457,6 +72456,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.num_cce), line:5706:28, endln:5706:49 |vpiName:num_cce + |vpiName:proc_param_lp.num_cce |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_cce_p), line:5706:16, endln:5706:25 |vpiParamAssign: @@ -72467,7 +72467,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.num_lce), line:5707:28, endln:5707:49 |vpiParent: \_param_assign: , line:5707:16, endln:5707:49 - |vpiName:proc_param_lp.num_lce |vpiActual: \_ref_obj: (proc_param_lp), line:5707:42, endln:5707:49 |vpiParent: @@ -72478,6 +72477,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.num_lce), line:5707:28, endln:5707:49 |vpiName:num_lce + |vpiName:proc_param_lp.num_lce |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.num_lce_p), line:5707:16, endln:5707:25 |vpiParamAssign: @@ -72909,7 +72909,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:5713:32, endln:5713:57 |vpiParent: \_param_assign: , line:5713:16, endln:5713:57 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:5713:46, endln:5713:57 |vpiParent: @@ -72920,6 +72919,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:5713:32, endln:5713:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.vaddr_width_p), line:5713:16, endln:5713:29 |vpiParamAssign: @@ -72930,7 +72930,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:5714:32, endln:5714:57 |vpiParent: \_param_assign: , line:5714:16, endln:5714:57 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:5714:46, endln:5714:57 |vpiParent: @@ -72941,6 +72940,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:5714:32, endln:5714:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.paddr_width_p), line:5714:16, endln:5714:29 |vpiParamAssign: @@ -72951,7 +72951,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:5715:32, endln:5715:56 |vpiParent: \_param_assign: , line:5715:16, endln:5715:56 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:5715:46, endln:5715:56 |vpiParent: @@ -72962,6 +72961,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:5715:32, endln:5715:56 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.asid_width_p), line:5715:16, endln:5715:28 |vpiParamAssign: @@ -72972,7 +72972,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.boot_pc), line:5717:34, endln:5717:55 |vpiParent: \_param_assign: , line:5717:16, endln:5717:55 - |vpiName:proc_param_lp.boot_pc |vpiActual: \_ref_obj: (proc_param_lp), line:5717:48, endln:5717:55 |vpiParent: @@ -72983,6 +72982,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.boot_pc), line:5717:34, endln:5717:55 |vpiName:boot_pc + |vpiName:proc_param_lp.boot_pc |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.boot_pc_p), line:5717:16, endln:5717:25 |vpiParamAssign: @@ -72993,7 +72993,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.boot_in_debug), line:5718:34, endln:5718:61 |vpiParent: \_param_assign: , line:5718:16, endln:5718:61 - |vpiName:proc_param_lp.boot_in_debug |vpiActual: \_ref_obj: (proc_param_lp), line:5718:48, endln:5718:61 |vpiParent: @@ -73004,6 +73003,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.boot_in_debug), line:5718:34, endln:5718:61 |vpiName:boot_in_debug + |vpiName:proc_param_lp.boot_in_debug |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.boot_in_debug_p), line:5718:16, endln:5718:31 |vpiParamAssign: @@ -73014,7 +73014,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:5720:46, endln:5720:85 |vpiParent: \_param_assign: , line:5720:16, endln:5720:85 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:5720:60, endln:5720:85 |vpiParent: @@ -73025,6 +73024,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:5720:46, endln:5720:85 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.branch_metadata_fwd_width_p), line:5720:16, endln:5720:43 |vpiParamAssign: @@ -73035,7 +73035,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.btb_tag_width), line:5721:46, endln:5721:73 |vpiParent: \_param_assign: , line:5721:16, endln:5721:73 - |vpiName:proc_param_lp.btb_tag_width |vpiActual: \_ref_obj: (proc_param_lp), line:5721:60, endln:5721:73 |vpiParent: @@ -73046,6 +73045,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.btb_tag_width), line:5721:46, endln:5721:73 |vpiName:btb_tag_width + |vpiName:proc_param_lp.btb_tag_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.btb_tag_width_p), line:5721:16, endln:5721:31 |vpiParamAssign: @@ -73056,7 +73056,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.btb_idx_width), line:5722:46, endln:5722:73 |vpiParent: \_param_assign: , line:5722:16, endln:5722:73 - |vpiName:proc_param_lp.btb_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:5722:60, endln:5722:73 |vpiParent: @@ -73067,6 +73066,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.btb_idx_width), line:5722:46, endln:5722:73 |vpiName:btb_idx_width + |vpiName:proc_param_lp.btb_idx_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.btb_idx_width_p), line:5722:16, endln:5722:31 |vpiParamAssign: @@ -73077,7 +73077,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.bht_idx_width), line:5723:46, endln:5723:73 |vpiParent: \_param_assign: , line:5723:16, endln:5723:73 - |vpiName:proc_param_lp.bht_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:5723:60, endln:5723:73 |vpiParent: @@ -73088,6 +73087,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.bht_idx_width), line:5723:46, endln:5723:73 |vpiName:bht_idx_width + |vpiName:proc_param_lp.bht_idx_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.bht_idx_width_p), line:5723:16, endln:5723:31 |vpiParamAssign: @@ -73098,7 +73098,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ghist_width), line:5724:46, endln:5724:71 |vpiParent: \_param_assign: , line:5724:16, endln:5724:71 - |vpiName:proc_param_lp.ghist_width |vpiActual: \_ref_obj: (proc_param_lp), line:5724:60, endln:5724:71 |vpiParent: @@ -73109,6 +73108,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ghist_width), line:5724:46, endln:5724:71 |vpiName:ghist_width + |vpiName:proc_param_lp.ghist_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.ghist_width_p), line:5724:16, endln:5724:29 |vpiParamAssign: @@ -73119,7 +73119,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.itlb_els), line:5726:42, endln:5726:64 |vpiParent: \_param_assign: , line:5726:16, endln:5726:64 - |vpiName:proc_param_lp.itlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:5726:56, endln:5726:64 |vpiParent: @@ -73130,6 +73129,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.itlb_els), line:5726:42, endln:5726:64 |vpiName:itlb_els + |vpiName:proc_param_lp.itlb_els |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.itlb_els_p), line:5726:16, endln:5726:26 |vpiParamAssign: @@ -73140,7 +73140,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dtlb_els), line:5727:42, endln:5727:64 |vpiParent: \_param_assign: , line:5727:16, endln:5727:64 - |vpiName:proc_param_lp.dtlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:5727:56, endln:5727:64 |vpiParent: @@ -73151,6 +73150,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dtlb_els), line:5727:42, endln:5727:64 |vpiName:dtlb_els + |vpiName:proc_param_lp.dtlb_els |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.dtlb_els_p), line:5727:16, endln:5727:26 |vpiParamAssign: @@ -73161,7 +73161,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.lr_sc), line:5729:45, endln:5729:64 |vpiParent: \_param_assign: , line:5729:16, endln:5729:64 - |vpiName:proc_param_lp.lr_sc |vpiActual: \_ref_obj: (proc_param_lp), line:5729:59, endln:5729:64 |vpiParent: @@ -73172,6 +73171,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.lr_sc), line:5729:45, endln:5729:64 |vpiName:lr_sc + |vpiName:proc_param_lp.lr_sc |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.lr_sc_p), line:5729:16, endln:5729:23 |vpiParamAssign: @@ -73182,7 +73182,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_swap), line:5730:45, endln:5730:67 |vpiParent: \_param_assign: , line:5730:16, endln:5730:67 - |vpiName:proc_param_lp.amo_swap |vpiActual: \_ref_obj: (proc_param_lp), line:5730:59, endln:5730:67 |vpiParent: @@ -73193,6 +73192,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_swap), line:5730:45, endln:5730:67 |vpiName:amo_swap + |vpiName:proc_param_lp.amo_swap |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.amo_swap_p), line:5730:16, endln:5730:26 |vpiParamAssign: @@ -73203,7 +73203,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_fetch_logic), line:5731:45, endln:5731:74 |vpiParent: \_param_assign: , line:5731:16, endln:5731:74 - |vpiName:proc_param_lp.amo_fetch_logic |vpiActual: \_ref_obj: (proc_param_lp), line:5731:59, endln:5731:74 |vpiParent: @@ -73214,6 +73213,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_fetch_logic), line:5731:45, endln:5731:74 |vpiName:amo_fetch_logic + |vpiName:proc_param_lp.amo_fetch_logic |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.amo_fetch_logic_p), line:5731:16, endln:5731:33 |vpiParamAssign: @@ -73224,7 +73224,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:5732:45, endln:5732:79 |vpiParent: \_param_assign: , line:5732:16, endln:5732:79 - |vpiName:proc_param_lp.amo_fetch_arithmetic |vpiActual: \_ref_obj: (proc_param_lp), line:5732:59, endln:5732:79 |vpiParent: @@ -73235,6 +73234,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:5732:45, endln:5732:79 |vpiName:amo_fetch_arithmetic + |vpiName:proc_param_lp.amo_fetch_arithmetic |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.amo_fetch_arithmetic_p), line:5732:16, endln:5732:38 |vpiParamAssign: @@ -73245,7 +73245,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l1_coherent), line:5734:45, endln:5734:70 |vpiParent: \_param_assign: , line:5734:16, endln:5734:70 - |vpiName:proc_param_lp.l1_coherent |vpiActual: \_ref_obj: (proc_param_lp), line:5734:59, endln:5734:70 |vpiParent: @@ -73256,6 +73255,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l1_coherent), line:5734:45, endln:5734:70 |vpiName:l1_coherent + |vpiName:proc_param_lp.l1_coherent |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.l1_coherent_p), line:5734:16, endln:5734:29 |vpiParamAssign: @@ -73266,7 +73266,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l1_writethrough), line:5735:45, endln:5735:74 |vpiParent: \_param_assign: , line:5735:16, endln:5735:74 - |vpiName:proc_param_lp.l1_writethrough |vpiActual: \_ref_obj: (proc_param_lp), line:5735:59, endln:5735:74 |vpiParent: @@ -73277,6 +73276,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l1_writethrough), line:5735:45, endln:5735:74 |vpiName:l1_writethrough + |vpiName:proc_param_lp.l1_writethrough |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.l1_writethrough_p), line:5735:16, endln:5735:33 |vpiParamAssign: @@ -73287,7 +73287,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_sets), line:5736:45, endln:5736:70 |vpiParent: \_param_assign: , line:5736:16, endln:5736:70 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:5736:59, endln:5736:70 |vpiParent: @@ -73298,6 +73297,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:5736:45, endln:5736:70 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_sets_p), line:5736:16, endln:5736:29 |vpiParamAssign: @@ -73308,7 +73308,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_assoc), line:5737:45, endln:5737:71 |vpiParent: \_param_assign: , line:5737:16, endln:5737:71 - |vpiName:proc_param_lp.dcache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:5737:59, endln:5737:71 |vpiParent: @@ -73319,6 +73318,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_assoc), line:5737:45, endln:5737:71 |vpiName:dcache_assoc + |vpiName:proc_param_lp.dcache_assoc |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_assoc_p), line:5737:16, endln:5737:30 |vpiParamAssign: @@ -73329,7 +73329,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_block_width), line:5738:45, endln:5738:77 |vpiParent: \_param_assign: , line:5738:16, endln:5738:77 - |vpiName:proc_param_lp.dcache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:5738:59, endln:5738:77 |vpiParent: @@ -73340,6 +73339,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_block_width), line:5738:45, endln:5738:77 |vpiName:dcache_block_width + |vpiName:proc_param_lp.dcache_block_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_block_width_p), line:5738:16, endln:5738:36 |vpiParamAssign: @@ -73350,7 +73350,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_fill_width), line:5739:45, endln:5739:76 |vpiParent: \_param_assign: , line:5739:16, endln:5739:76 - |vpiName:proc_param_lp.dcache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:5739:59, endln:5739:76 |vpiParent: @@ -73361,6 +73360,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_fill_width), line:5739:45, endln:5739:76 |vpiName:dcache_fill_width + |vpiName:proc_param_lp.dcache_fill_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.dcache_fill_width_p), line:5739:16, endln:5739:35 |vpiParamAssign: @@ -73371,7 +73371,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_sets), line:5740:45, endln:5740:70 |vpiParent: \_param_assign: , line:5740:16, endln:5740:70 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:5740:59, endln:5740:70 |vpiParent: @@ -73382,6 +73381,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:5740:45, endln:5740:70 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_sets_p), line:5740:16, endln:5740:29 |vpiParamAssign: @@ -73392,7 +73392,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_assoc), line:5741:45, endln:5741:71 |vpiParent: \_param_assign: , line:5741:16, endln:5741:71 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:5741:59, endln:5741:71 |vpiParent: @@ -73403,6 +73402,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:5741:45, endln:5741:71 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_assoc_p), line:5741:16, endln:5741:30 |vpiParamAssign: @@ -73413,7 +73413,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_block_width), line:5742:45, endln:5742:77 |vpiParent: \_param_assign: , line:5742:16, endln:5742:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:5742:59, endln:5742:77 |vpiParent: @@ -73424,6 +73423,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:5742:45, endln:5742:77 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_block_width_p), line:5742:16, endln:5742:36 |vpiParamAssign: @@ -73434,7 +73434,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_fill_width), line:5743:45, endln:5743:76 |vpiParent: \_param_assign: , line:5743:16, endln:5743:76 - |vpiName:proc_param_lp.icache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:5743:59, endln:5743:76 |vpiParent: @@ -73445,6 +73444,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_fill_width), line:5743:45, endln:5743:76 |vpiName:icache_fill_width + |vpiName:proc_param_lp.icache_fill_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.icache_fill_width_p), line:5743:16, endln:5743:35 |vpiParamAssign: @@ -73455,7 +73455,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_sets), line:5744:45, endln:5744:70 |vpiParent: \_param_assign: , line:5744:16, endln:5744:70 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:5744:59, endln:5744:70 |vpiParent: @@ -73466,6 +73465,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:5744:45, endln:5744:70 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_sets_p), line:5744:16, endln:5744:29 |vpiParamAssign: @@ -73476,7 +73476,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_assoc), line:5745:45, endln:5745:71 |vpiParent: \_param_assign: , line:5745:16, endln:5745:71 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:5745:59, endln:5745:71 |vpiParent: @@ -73487,6 +73486,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:5745:45, endln:5745:71 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_assoc_p), line:5745:16, endln:5745:30 |vpiParamAssign: @@ -73497,7 +73497,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_block_width), line:5746:45, endln:5746:77 |vpiParent: \_param_assign: , line:5746:16, endln:5746:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:5746:59, endln:5746:77 |vpiParent: @@ -73508,6 +73507,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:5746:45, endln:5746:77 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_block_width_p), line:5746:16, endln:5746:36 |vpiParamAssign: @@ -73518,7 +73518,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_fill_width), line:5747:45, endln:5747:76 |vpiParent: \_param_assign: , line:5747:16, endln:5747:76 - |vpiName:proc_param_lp.acache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:5747:59, endln:5747:76 |vpiParent: @@ -73529,6 +73528,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_fill_width), line:5747:45, endln:5747:76 |vpiName:acache_fill_width + |vpiName:proc_param_lp.acache_fill_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.acache_fill_width_p), line:5747:16, endln:5747:35 |vpiParamAssign: @@ -73925,7 +73925,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_pc_width), line:5771:45, endln:5771:71 |vpiParent: \_param_assign: , line:5771:16, endln:5771:71 - |vpiName:proc_param_lp.cce_pc_width |vpiActual: \_ref_obj: (proc_param_lp), line:5771:59, endln:5771:71 |vpiParent: @@ -73936,6 +73935,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_pc_width), line:5771:45, endln:5771:71 |vpiName:cce_pc_width + |vpiName:proc_param_lp.cce_pc_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_pc_width_p), line:5771:16, endln:5771:30 |vpiParamAssign: @@ -74032,7 +74032,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_ucode), line:5775:45, endln:5775:68 |vpiParent: \_param_assign: , line:5775:16, endln:5775:68 - |vpiName:proc_param_lp.cce_ucode |vpiActual: \_ref_obj: (proc_param_lp), line:5775:59, endln:5775:68 |vpiParent: @@ -74043,6 +74042,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_ucode), line:5775:45, endln:5775:68 |vpiName:cce_ucode + |vpiName:proc_param_lp.cce_ucode |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.cce_ucode_p), line:5775:16, endln:5775:27 |vpiParamAssign: @@ -74053,7 +74053,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_en), line:5777:29, endln:5777:48 |vpiParent: \_param_assign: , line:5777:16, endln:5777:48 - |vpiName:proc_param_lp.l2_en |vpiActual: \_ref_obj: (proc_param_lp), line:5777:43, endln:5777:48 |vpiParent: @@ -74064,6 +74063,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_en), line:5777:29, endln:5777:48 |vpiName:l2_en + |vpiName:proc_param_lp.l2_en |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_en_p), line:5777:16, endln:5777:23 |vpiParamAssign: @@ -74074,7 +74074,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_sets), line:5778:29, endln:5778:50 |vpiParent: \_param_assign: , line:5778:16, endln:5778:50 - |vpiName:proc_param_lp.l2_sets |vpiActual: \_ref_obj: (proc_param_lp), line:5778:43, endln:5778:50 |vpiParent: @@ -74085,6 +74084,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_sets), line:5778:29, endln:5778:50 |vpiName:l2_sets + |vpiName:proc_param_lp.l2_sets |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_sets_p), line:5778:16, endln:5778:25 |vpiParamAssign: @@ -74095,7 +74095,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_assoc), line:5779:29, endln:5779:51 |vpiParent: \_param_assign: , line:5779:16, endln:5779:51 - |vpiName:proc_param_lp.l2_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:5779:43, endln:5779:51 |vpiParent: @@ -74106,6 +74105,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_assoc), line:5779:29, endln:5779:51 |vpiName:l2_assoc + |vpiName:proc_param_lp.l2_assoc |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_assoc_p), line:5779:16, endln:5779:26 |vpiParamAssign: @@ -74116,7 +74116,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:5780:40, endln:5780:73 |vpiParent: \_param_assign: , line:5780:16, endln:5780:73 - |vpiName:proc_param_lp.l2_outstanding_reqs |vpiActual: \_ref_obj: (proc_param_lp), line:5780:54, endln:5780:73 |vpiParent: @@ -74127,6 +74126,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:5780:40, endln:5780:73 |vpiName:l2_outstanding_reqs + |vpiName:proc_param_lp.l2_outstanding_reqs |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.l2_outstanding_reqs_p), line:5780:16, endln:5780:37 |vpiParamAssign: @@ -74137,7 +74137,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:5782:38, endln:5782:69 |vpiParent: \_param_assign: , line:5782:16, endln:5782:69 - |vpiName:proc_param_lp.fe_queue_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:5782:52, endln:5782:69 |vpiParent: @@ -74148,6 +74147,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:5782:38, endln:5782:69 |vpiName:fe_queue_fifo_els + |vpiName:proc_param_lp.fe_queue_fifo_els |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.fe_queue_fifo_els_p), line:5782:16, endln:5782:35 |vpiParamAssign: @@ -74158,7 +74158,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:5783:38, endln:5783:67 |vpiParent: \_param_assign: , line:5783:16, endln:5783:67 - |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:5783:52, endln:5783:67 |vpiParent: @@ -74169,6 +74168,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:5783:38, endln:5783:67 |vpiName:fe_cmd_fifo_els + |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.fe_cmd_fifo_els_p), line:5783:16, endln:5783:33 |vpiParamAssign: @@ -74179,7 +74179,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_coh_clk), line:5785:41, endln:5785:68 |vpiParent: \_param_assign: , line:5785:16, endln:5785:68 - |vpiName:proc_param_lp.async_coh_clk |vpiActual: \_ref_obj: (proc_param_lp), line:5785:55, endln:5785:68 |vpiParent: @@ -74190,6 +74189,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_coh_clk), line:5785:41, endln:5785:68 |vpiName:async_coh_clk + |vpiName:proc_param_lp.async_coh_clk |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.async_coh_clk_p), line:5785:16, endln:5785:31 |vpiParamAssign: @@ -74200,7 +74200,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_max_credits), line:5786:41, endln:5786:74 |vpiParent: \_param_assign: , line:5786:16, endln:5786:74 - |vpiName:proc_param_lp.coh_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:5786:55, endln:5786:74 |vpiParent: @@ -74211,6 +74210,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_max_credits), line:5786:41, endln:5786:74 |vpiName:coh_noc_max_credits + |vpiName:proc_param_lp.coh_noc_max_credits |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_max_credits_p), line:5786:16, endln:5786:37 |vpiParamAssign: @@ -74221,7 +74221,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_flit_width), line:5787:41, endln:5787:73 |vpiParent: \_param_assign: , line:5787:16, endln:5787:73 - |vpiName:proc_param_lp.coh_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:5787:55, endln:5787:73 |vpiParent: @@ -74232,6 +74231,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:5787:41, endln:5787:73 |vpiName:coh_noc_flit_width + |vpiName:proc_param_lp.coh_noc_flit_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_flit_width_p), line:5787:16, endln:5787:36 |vpiParamAssign: @@ -74242,7 +74242,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_cid_width), line:5788:41, endln:5788:72 |vpiParent: \_param_assign: , line:5788:16, endln:5788:72 - |vpiName:proc_param_lp.coh_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:5788:55, endln:5788:72 |vpiParent: @@ -74253,6 +74252,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:5788:41, endln:5788:72 |vpiName:coh_noc_cid_width + |vpiName:proc_param_lp.coh_noc_cid_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_cid_width_p), line:5788:16, endln:5788:35 |vpiParamAssign: @@ -74263,7 +74263,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_len_width), line:5789:41, endln:5789:72 |vpiParent: \_param_assign: , line:5789:16, endln:5789:72 - |vpiName:proc_param_lp.coh_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:5789:55, endln:5789:72 |vpiParent: @@ -74274,6 +74273,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_len_width), line:5789:41, endln:5789:72 |vpiName:coh_noc_len_width + |vpiName:proc_param_lp.coh_noc_len_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.coh_noc_len_width_p), line:5789:16, endln:5789:35 |vpiParamAssign: @@ -74705,7 +74705,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_mem_clk), line:5800:44, endln:5800:71 |vpiParent: \_param_assign: , line:5800:16, endln:5800:71 - |vpiName:proc_param_lp.async_mem_clk |vpiActual: \_ref_obj: (proc_param_lp), line:5800:58, endln:5800:71 |vpiParent: @@ -74716,6 +74715,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_mem_clk), line:5800:44, endln:5800:71 |vpiName:async_mem_clk + |vpiName:proc_param_lp.async_mem_clk |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.async_mem_clk_p), line:5800:16, endln:5800:31 |vpiParamAssign: @@ -74726,7 +74726,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_max_credits), line:5801:44, endln:5801:77 |vpiParent: \_param_assign: , line:5801:16, endln:5801:77 - |vpiName:proc_param_lp.mem_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:5801:58, endln:5801:77 |vpiParent: @@ -74737,6 +74736,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:5801:44, endln:5801:77 |vpiName:mem_noc_max_credits + |vpiName:proc_param_lp.mem_noc_max_credits |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_max_credits_p), line:5801:16, endln:5801:37 |vpiParamAssign: @@ -74747,7 +74747,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_flit_width), line:5802:44, endln:5802:76 |vpiParent: \_param_assign: , line:5802:16, endln:5802:76 - |vpiName:proc_param_lp.mem_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:5802:58, endln:5802:76 |vpiParent: @@ -74758,6 +74757,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:5802:44, endln:5802:76 |vpiName:mem_noc_flit_width + |vpiName:proc_param_lp.mem_noc_flit_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_flit_width_p), line:5802:16, endln:5802:36 |vpiParamAssign: @@ -74768,7 +74768,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_cid_width), line:5803:44, endln:5803:75 |vpiParent: \_param_assign: , line:5803:16, endln:5803:75 - |vpiName:proc_param_lp.mem_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:5803:58, endln:5803:75 |vpiParent: @@ -74779,6 +74778,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:5803:44, endln:5803:75 |vpiName:mem_noc_cid_width + |vpiName:proc_param_lp.mem_noc_cid_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_cid_width_p), line:5803:16, endln:5803:35 |vpiParamAssign: @@ -74789,7 +74789,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_len_width), line:5804:44, endln:5804:75 |vpiParent: \_param_assign: , line:5804:16, endln:5804:75 - |vpiName:proc_param_lp.mem_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:5804:58, endln:5804:75 |vpiParent: @@ -74800,6 +74799,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_len_width), line:5804:44, endln:5804:75 |vpiName:mem_noc_len_width + |vpiName:proc_param_lp.mem_noc_len_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.mem_noc_len_width_p), line:5804:16, endln:5804:35 |vpiParamAssign: @@ -75154,7 +75154,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_io_clk), line:5816:43, endln:5816:69 |vpiParent: \_param_assign: , line:5816:16, endln:5816:69 - |vpiName:proc_param_lp.async_io_clk |vpiActual: \_ref_obj: (proc_param_lp), line:5816:57, endln:5816:69 |vpiParent: @@ -75165,6 +75164,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_io_clk), line:5816:43, endln:5816:69 |vpiName:async_io_clk + |vpiName:proc_param_lp.async_io_clk |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.async_io_clk_p), line:5816:16, endln:5816:30 |vpiParamAssign: @@ -75175,7 +75175,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_max_credits), line:5817:43, endln:5817:75 |vpiParent: \_param_assign: , line:5817:16, endln:5817:75 - |vpiName:proc_param_lp.io_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:5817:57, endln:5817:75 |vpiParent: @@ -75186,6 +75185,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_max_credits), line:5817:43, endln:5817:75 |vpiName:io_noc_max_credits + |vpiName:proc_param_lp.io_noc_max_credits |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_max_credits_p), line:5817:16, endln:5817:36 |vpiParamAssign: @@ -75196,7 +75196,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_did_width), line:5818:43, endln:5818:73 |vpiParent: \_param_assign: , line:5818:16, endln:5818:73 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:5818:57, endln:5818:73 |vpiParent: @@ -75207,6 +75206,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:5818:43, endln:5818:73 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_did_width_p), line:5818:16, endln:5818:34 |vpiParamAssign: @@ -75217,7 +75217,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_flit_width), line:5819:43, endln:5819:74 |vpiParent: \_param_assign: , line:5819:16, endln:5819:74 - |vpiName:proc_param_lp.io_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:5819:57, endln:5819:74 |vpiParent: @@ -75228,6 +75227,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_flit_width), line:5819:43, endln:5819:74 |vpiName:io_noc_flit_width + |vpiName:proc_param_lp.io_noc_flit_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_flit_width_p), line:5819:16, endln:5819:35 |vpiParamAssign: @@ -75238,7 +75238,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_cid_width), line:5820:43, endln:5820:73 |vpiParent: \_param_assign: , line:5820:16, endln:5820:73 - |vpiName:proc_param_lp.io_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:5820:57, endln:5820:73 |vpiParent: @@ -75249,6 +75248,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_cid_width), line:5820:43, endln:5820:73 |vpiName:io_noc_cid_width + |vpiName:proc_param_lp.io_noc_cid_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_cid_width_p), line:5820:16, endln:5820:34 |vpiParamAssign: @@ -75259,7 +75259,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_len_width), line:5821:43, endln:5821:73 |vpiParent: \_param_assign: , line:5821:16, endln:5821:73 - |vpiName:proc_param_lp.io_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:5821:57, endln:5821:73 |vpiParent: @@ -75270,6 +75269,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_len_width), line:5821:43, endln:5821:73 |vpiName:io_noc_len_width + |vpiName:proc_param_lp.io_noc_len_width |vpiLhs: \_parameter: (work@bp_me_nonsynth_lce_tracer.io_noc_len_width_p), line:5821:16, endln:5821:34 |vpiParamAssign: @@ -75648,7 +75648,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:5840:32, endln:5840:57 |vpiParent: \_operation: , line:5840:32, endln:5840:79 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:5840:46, endln:5840:57 |vpiParent: @@ -75659,6 +75658,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:5840:32, endln:5840:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.page_offset_width_p), line:5840:60, endln:5840:79 |vpiParent: @@ -75680,7 +75680,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:5841:32, endln:5841:57 |vpiParent: \_operation: , line:5841:32, endln:5841:79 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:5841:46, endln:5841:57 |vpiParent: @@ -75691,6 +75690,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:5841:32, endln:5841:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.page_offset_width_p), line:5841:60, endln:5841:79 |vpiParent: @@ -78065,7 +78065,6 @@ design: (work@testbench) \_hier_path: (lce_req_payload.src_id), line:6045:16, endln:6045:38 |vpiParent: \_operation: , line:6045:16, endln:6045:50 - |vpiName:lce_req_payload.src_id |vpiActual: \_ref_obj: (lce_req_payload), line:6045:16, endln:6045:31 |vpiParent: @@ -78077,6 +78076,7 @@ design: (work@testbench) \_hier_path: (lce_req_payload.src_id), line:6045:16, endln:6045:38 |vpiName:src_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.src_id + |vpiName:lce_req_payload.src_id |vpiOperand: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_id_i), line:6045:42, endln:6045:50 |vpiParent: @@ -78127,7 +78127,6 @@ design: (work@testbench) \_hier_path: (lce_req_payload.src_id), line:6047:28, endln:6047:50 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req_payload.src_id |vpiActual: \_ref_obj: (lce_req_payload), line:6047:28, endln:6047:43 |vpiParent: @@ -78139,11 +78138,11 @@ design: (work@testbench) \_hier_path: (lce_req_payload.src_id), line:6047:28, endln:6047:50 |vpiName:src_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.src_id + |vpiName:lce_req_payload.src_id |vpiArgument: \_hier_path: (lce_req.header.addr), line:6047:52, endln:6047:71 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req.header.addr |vpiActual: \_ref_obj: (lce_req), line:6047:52, endln:6047:59 |vpiParent: @@ -78160,11 +78159,11 @@ design: (work@testbench) \_hier_path: (lce_req.header.addr), line:6047:52, endln:6047:71 |vpiName:addr |vpiFullName:work@bp_me_nonsynth_lce_tracer.addr + |vpiName:lce_req.header.addr |vpiArgument: \_hier_path: (lce_req_payload.dst_id), line:6047:73, endln:6047:95 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req_payload.dst_id |vpiActual: \_ref_obj: (lce_req_payload), line:6047:73, endln:6047:88 |vpiParent: @@ -78176,11 +78175,11 @@ design: (work@testbench) \_hier_path: (lce_req_payload.dst_id), line:6047:73, endln:6047:95 |vpiName:dst_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.dst_id + |vpiName:lce_req_payload.dst_id |vpiArgument: \_hier_path: (lce_req.header.msg_type), line:6047:97, endln:6047:120 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req.header.msg_type |vpiActual: \_ref_obj: (lce_req), line:6047:97, endln:6047:104 |vpiParent: @@ -78197,11 +78196,11 @@ design: (work@testbench) \_hier_path: (lce_req.header.msg_type), line:6047:97, endln:6047:120 |vpiName:msg_type |vpiFullName:work@bp_me_nonsynth_lce_tracer.msg_type + |vpiName:lce_req.header.msg_type |vpiArgument: \_hier_path: (lce_req_payload.non_exclusive), line:6048:21, endln:6048:50 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req_payload.non_exclusive |vpiActual: \_ref_obj: (lce_req_payload), line:6048:21, endln:6048:36 |vpiParent: @@ -78213,11 +78212,11 @@ design: (work@testbench) \_hier_path: (lce_req_payload.non_exclusive), line:6048:21, endln:6048:50 |vpiName:non_exclusive |vpiFullName:work@bp_me_nonsynth_lce_tracer.non_exclusive + |vpiName:lce_req_payload.non_exclusive |vpiArgument: \_hier_path: (lce_req_payload.lru_way_id), line:6048:52, endln:6048:78 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req_payload.lru_way_id |vpiActual: \_ref_obj: (lce_req_payload), line:6048:52, endln:6048:67 |vpiParent: @@ -78229,11 +78228,11 @@ design: (work@testbench) \_hier_path: (lce_req_payload.lru_way_id), line:6048:52, endln:6048:78 |vpiName:lru_way_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.lru_way_id + |vpiName:lce_req_payload.lru_way_id |vpiArgument: \_hier_path: (lce_req.header.size), line:6049:21, endln:6049:40 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req.header.size |vpiActual: \_ref_obj: (lce_req), line:6049:21, endln:6049:28 |vpiParent: @@ -78250,11 +78249,11 @@ design: (work@testbench) \_hier_path: (lce_req.header.size), line:6049:21, endln:6049:40 |vpiName:size |vpiFullName:work@bp_me_nonsynth_lce_tracer.size + |vpiName:lce_req.header.size |vpiArgument: \_hier_path: (lce_req.data), line:6049:42, endln:6049:54 |vpiParent: \_sys_func_call: ($fdisplay), line:6046:9, endln:6050:20 - |vpiName:lce_req.data |vpiActual: \_ref_obj: (lce_req), line:6049:42, endln:6049:49 |vpiParent: @@ -78266,6 +78265,7 @@ design: (work@testbench) \_hier_path: (lce_req.data), line:6049:42, endln:6049:54 |vpiName:data |vpiFullName:work@bp_me_nonsynth_lce_tracer.data + |vpiName:lce_req.data |vpiName:$fdisplay |vpiStmt: \_if_stmt: , line:6054:7, endln:6060:10 @@ -78310,7 +78310,6 @@ design: (work@testbench) \_hier_path: (lce_resp_payload.src_id), line:6055:16, endln:6055:39 |vpiParent: \_operation: , line:6055:16, endln:6055:51 - |vpiName:lce_resp_payload.src_id |vpiActual: \_ref_obj: (lce_resp_payload), line:6055:16, endln:6055:32 |vpiParent: @@ -78322,6 +78321,7 @@ design: (work@testbench) \_hier_path: (lce_resp_payload.src_id), line:6055:16, endln:6055:39 |vpiName:src_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.src_id + |vpiName:lce_resp_payload.src_id |vpiOperand: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_id_i), line:6055:43, endln:6055:51 |vpiParent: @@ -78372,7 +78372,6 @@ design: (work@testbench) \_hier_path: (lce_resp_payload.src_id), line:6057:28, endln:6057:51 |vpiParent: \_sys_func_call: ($fdisplay), line:6056:9, endln:6059:20 - |vpiName:lce_resp_payload.src_id |vpiActual: \_ref_obj: (lce_resp_payload), line:6057:28, endln:6057:44 |vpiParent: @@ -78384,11 +78383,11 @@ design: (work@testbench) \_hier_path: (lce_resp_payload.src_id), line:6057:28, endln:6057:51 |vpiName:src_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.src_id + |vpiName:lce_resp_payload.src_id |vpiArgument: \_hier_path: (lce_resp.header.addr), line:6057:53, endln:6057:73 |vpiParent: \_sys_func_call: ($fdisplay), line:6056:9, endln:6059:20 - |vpiName:lce_resp.header.addr |vpiActual: \_ref_obj: (lce_resp), line:6057:53, endln:6057:61 |vpiParent: @@ -78405,11 +78404,11 @@ design: (work@testbench) \_hier_path: (lce_resp.header.addr), line:6057:53, endln:6057:73 |vpiName:addr |vpiFullName:work@bp_me_nonsynth_lce_tracer.addr + |vpiName:lce_resp.header.addr |vpiArgument: \_hier_path: (lce_resp_payload.dst_id), line:6057:75, endln:6057:98 |vpiParent: \_sys_func_call: ($fdisplay), line:6056:9, endln:6059:20 - |vpiName:lce_resp_payload.dst_id |vpiActual: \_ref_obj: (lce_resp_payload), line:6057:75, endln:6057:91 |vpiParent: @@ -78421,11 +78420,11 @@ design: (work@testbench) \_hier_path: (lce_resp_payload.dst_id), line:6057:75, endln:6057:98 |vpiName:dst_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.dst_id + |vpiName:lce_resp_payload.dst_id |vpiArgument: \_hier_path: (lce_resp.header.msg_type), line:6057:100, endln:6057:124 |vpiParent: \_sys_func_call: ($fdisplay), line:6056:9, endln:6059:20 - |vpiName:lce_resp.header.msg_type |vpiActual: \_ref_obj: (lce_resp), line:6057:100, endln:6057:108 |vpiParent: @@ -78442,11 +78441,11 @@ design: (work@testbench) \_hier_path: (lce_resp.header.msg_type), line:6057:100, endln:6057:124 |vpiName:msg_type |vpiFullName:work@bp_me_nonsynth_lce_tracer.msg_type + |vpiName:lce_resp.header.msg_type |vpiArgument: \_hier_path: (lce_resp.header.size), line:6058:21, endln:6058:41 |vpiParent: \_sys_func_call: ($fdisplay), line:6056:9, endln:6059:20 - |vpiName:lce_resp.header.size |vpiActual: \_ref_obj: (lce_resp), line:6058:21, endln:6058:29 |vpiParent: @@ -78463,11 +78462,11 @@ design: (work@testbench) \_hier_path: (lce_resp.header.size), line:6058:21, endln:6058:41 |vpiName:size |vpiFullName:work@bp_me_nonsynth_lce_tracer.size + |vpiName:lce_resp.header.size |vpiArgument: \_hier_path: (lce_resp.data), line:6058:43, endln:6058:56 |vpiParent: \_sys_func_call: ($fdisplay), line:6056:9, endln:6059:20 - |vpiName:lce_resp.data |vpiActual: \_ref_obj: (lce_resp), line:6058:43, endln:6058:51 |vpiParent: @@ -78479,6 +78478,7 @@ design: (work@testbench) \_hier_path: (lce_resp.data), line:6058:43, endln:6058:56 |vpiName:data |vpiFullName:work@bp_me_nonsynth_lce_tracer.data + |vpiName:lce_resp.data |vpiName:$fdisplay |vpiStmt: \_if_stmt: , line:6063:7, endln:6070:10 @@ -78523,7 +78523,6 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.dst_id), line:6064:16, endln:6064:38 |vpiParent: \_operation: , line:6064:16, endln:6064:50 - |vpiName:lce_cmd_payload.dst_id |vpiActual: \_ref_obj: (lce_cmd_payload), line:6064:16, endln:6064:31 |vpiParent: @@ -78535,6 +78534,7 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.dst_id), line:6064:16, endln:6064:38 |vpiName:dst_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.dst_id + |vpiName:lce_cmd_payload.dst_id |vpiOperand: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_id_i), line:6064:42, endln:6064:50 |vpiParent: @@ -78585,7 +78585,6 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.dst_id), line:6066:28, endln:6066:50 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd_payload.dst_id |vpiActual: \_ref_obj: (lce_cmd_payload), line:6066:28, endln:6066:43 |vpiParent: @@ -78597,11 +78596,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.dst_id), line:6066:28, endln:6066:50 |vpiName:dst_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.dst_id + |vpiName:lce_cmd_payload.dst_id |vpiArgument: \_hier_path: (lce_cmd.header.addr), line:6066:52, endln:6066:71 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd.header.addr |vpiActual: \_ref_obj: (lce_cmd), line:6066:52, endln:6066:59 |vpiParent: @@ -78618,11 +78617,11 @@ design: (work@testbench) \_hier_path: (lce_cmd.header.addr), line:6066:52, endln:6066:71 |vpiName:addr |vpiFullName:work@bp_me_nonsynth_lce_tracer.addr + |vpiName:lce_cmd.header.addr |vpiArgument: \_hier_path: (lce_cmd_payload.src_id), line:6066:73, endln:6066:95 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd_payload.src_id |vpiActual: \_ref_obj: (lce_cmd_payload), line:6066:73, endln:6066:88 |vpiParent: @@ -78634,11 +78633,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.src_id), line:6066:73, endln:6066:95 |vpiName:src_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.src_id + |vpiName:lce_cmd_payload.src_id |vpiArgument: \_hier_path: (lce_cmd.header.msg_type), line:6066:97, endln:6066:120 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd.header.msg_type |vpiActual: \_ref_obj: (lce_cmd), line:6066:97, endln:6066:104 |vpiParent: @@ -78655,11 +78654,11 @@ design: (work@testbench) \_hier_path: (lce_cmd.header.msg_type), line:6066:97, endln:6066:120 |vpiName:msg_type |vpiFullName:work@bp_me_nonsynth_lce_tracer.msg_type + |vpiName:lce_cmd.header.msg_type |vpiArgument: \_hier_path: (lce_cmd.header.addr[block_offset_bits_lp+:lg_sets_lp]), line:6067:21, endln:6067:74 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd.header.addr[block_offset_bits_lp+:lg_sets_lp] |vpiActual: \_ref_obj: (lce_cmd), line:6067:21, endln:6067:28 |vpiParent: @@ -78690,11 +78689,11 @@ design: (work@testbench) \_indexed_part_select: (lce_cmd.header.addr[block_offset_bits_lp+:lg_sets_lp]), line:6067:36, endln:6067:73 |vpiName:lg_sets_lp |vpiFullName:work@bp_me_nonsynth_lce_tracer.lce_cmd.header.addr[block_offset_bits_lp+:lg_sets_lp].lg_sets_lp + |vpiName:lce_cmd.header.addr[block_offset_bits_lp+:lg_sets_lp] |vpiArgument: \_hier_path: (lce_cmd_payload.way_id), line:6067:76, endln:6067:98 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd_payload.way_id |vpiActual: \_ref_obj: (lce_cmd_payload), line:6067:76, endln:6067:91 |vpiParent: @@ -78706,11 +78705,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.way_id), line:6067:76, endln:6067:98 |vpiName:way_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.way_id + |vpiName:lce_cmd_payload.way_id |vpiArgument: \_hier_path: (lce_cmd_payload.state), line:6067:100, endln:6067:121 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd_payload.state |vpiActual: \_ref_obj: (lce_cmd_payload), line:6067:100, endln:6067:115 |vpiParent: @@ -78722,11 +78721,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.state), line:6067:100, endln:6067:121 |vpiName:state |vpiFullName:work@bp_me_nonsynth_lce_tracer.state + |vpiName:lce_cmd_payload.state |vpiArgument: \_hier_path: (lce_cmd_payload.target), line:6067:123, endln:6067:145 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd_payload.target |vpiActual: \_ref_obj: (lce_cmd_payload), line:6067:123, endln:6067:138 |vpiParent: @@ -78738,11 +78737,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.target), line:6067:123, endln:6067:145 |vpiName:target |vpiFullName:work@bp_me_nonsynth_lce_tracer.target + |vpiName:lce_cmd_payload.target |vpiArgument: \_hier_path: (lce_cmd_payload.target_way_id), line:6068:21, endln:6068:50 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd_payload.target_way_id |vpiActual: \_ref_obj: (lce_cmd_payload), line:6068:21, endln:6068:36 |vpiParent: @@ -78754,11 +78753,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_payload.target_way_id), line:6068:21, endln:6068:50 |vpiName:target_way_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.target_way_id + |vpiName:lce_cmd_payload.target_way_id |vpiArgument: \_hier_path: (lce_cmd.header.size), line:6068:52, endln:6068:71 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd.header.size |vpiActual: \_ref_obj: (lce_cmd), line:6068:52, endln:6068:59 |vpiParent: @@ -78775,11 +78774,11 @@ design: (work@testbench) \_hier_path: (lce_cmd.header.size), line:6068:52, endln:6068:71 |vpiName:size |vpiFullName:work@bp_me_nonsynth_lce_tracer.size + |vpiName:lce_cmd.header.size |vpiArgument: \_hier_path: (lce_cmd.data), line:6068:73, endln:6068:85 |vpiParent: \_sys_func_call: ($fdisplay), line:6065:9, endln:6069:20 - |vpiName:lce_cmd.data |vpiActual: \_ref_obj: (lce_cmd), line:6068:73, endln:6068:80 |vpiParent: @@ -78791,6 +78790,7 @@ design: (work@testbench) \_hier_path: (lce_cmd.data), line:6068:73, endln:6068:85 |vpiName:data |vpiFullName:work@bp_me_nonsynth_lce_tracer.data + |vpiName:lce_cmd.data |vpiName:$fdisplay |vpiStmt: \_if_stmt: , line:6073:7, endln:6079:10 @@ -78859,7 +78859,6 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.dst_id), line:6075:38, endln:6075:63 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo_payload.dst_id |vpiActual: \_ref_obj: (lce_cmd_lo_payload), line:6075:38, endln:6075:56 |vpiParent: @@ -78871,11 +78870,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.dst_id), line:6075:38, endln:6075:63 |vpiName:dst_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.dst_id + |vpiName:lce_cmd_lo_payload.dst_id |vpiArgument: \_hier_path: (lce_cmd_lo.header.addr), line:6075:65, endln:6075:87 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo.header.addr |vpiActual: \_ref_obj: (lce_cmd_lo), line:6075:65, endln:6075:75 |vpiParent: @@ -78892,11 +78891,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo.header.addr), line:6075:65, endln:6075:87 |vpiName:addr |vpiFullName:work@bp_me_nonsynth_lce_tracer.addr + |vpiName:lce_cmd_lo.header.addr |vpiArgument: \_hier_path: (lce_cmd_lo_payload.src_id), line:6075:89, endln:6075:114 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo_payload.src_id |vpiActual: \_ref_obj: (lce_cmd_lo_payload), line:6075:89, endln:6075:107 |vpiParent: @@ -78908,11 +78907,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.src_id), line:6075:89, endln:6075:114 |vpiName:src_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.src_id + |vpiName:lce_cmd_lo_payload.src_id |vpiArgument: \_hier_path: (lce_cmd_lo.header.msg_type), line:6075:116, endln:6075:142 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo.header.msg_type |vpiActual: \_ref_obj: (lce_cmd_lo), line:6075:116, endln:6075:126 |vpiParent: @@ -78929,11 +78928,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo.header.msg_type), line:6075:116, endln:6075:142 |vpiName:msg_type |vpiFullName:work@bp_me_nonsynth_lce_tracer.msg_type + |vpiName:lce_cmd_lo.header.msg_type |vpiArgument: \_hier_path: (lce_cmd_lo_payload.way_id), line:6076:21, endln:6076:46 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo_payload.way_id |vpiActual: \_ref_obj: (lce_cmd_lo_payload), line:6076:21, endln:6076:39 |vpiParent: @@ -78945,11 +78944,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.way_id), line:6076:21, endln:6076:46 |vpiName:way_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.way_id + |vpiName:lce_cmd_lo_payload.way_id |vpiArgument: \_hier_path: (lce_cmd_lo_payload.state), line:6076:48, endln:6076:72 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo_payload.state |vpiActual: \_ref_obj: (lce_cmd_lo_payload), line:6076:48, endln:6076:66 |vpiParent: @@ -78961,11 +78960,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.state), line:6076:48, endln:6076:72 |vpiName:state |vpiFullName:work@bp_me_nonsynth_lce_tracer.state + |vpiName:lce_cmd_lo_payload.state |vpiArgument: \_hier_path: (lce_cmd_lo_payload.target), line:6076:74, endln:6076:99 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo_payload.target |vpiActual: \_ref_obj: (lce_cmd_lo_payload), line:6076:74, endln:6076:92 |vpiParent: @@ -78977,11 +78976,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.target), line:6076:74, endln:6076:99 |vpiName:target |vpiFullName:work@bp_me_nonsynth_lce_tracer.target + |vpiName:lce_cmd_lo_payload.target |vpiArgument: \_hier_path: (lce_cmd_lo_payload.target_way_id), line:6076:101, endln:6076:133 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo_payload.target_way_id |vpiActual: \_ref_obj: (lce_cmd_lo_payload), line:6076:101, endln:6076:119 |vpiParent: @@ -78993,11 +78992,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo_payload.target_way_id), line:6076:101, endln:6076:133 |vpiName:target_way_id |vpiFullName:work@bp_me_nonsynth_lce_tracer.target_way_id + |vpiName:lce_cmd_lo_payload.target_way_id |vpiArgument: \_hier_path: (lce_cmd_lo.header.size), line:6077:21, endln:6077:43 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo.header.size |vpiActual: \_ref_obj: (lce_cmd_lo), line:6077:21, endln:6077:31 |vpiParent: @@ -79014,11 +79013,11 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo.header.size), line:6077:21, endln:6077:43 |vpiName:size |vpiFullName:work@bp_me_nonsynth_lce_tracer.size + |vpiName:lce_cmd_lo.header.size |vpiArgument: \_hier_path: (lce_cmd_lo.data), line:6077:45, endln:6077:60 |vpiParent: \_sys_func_call: ($fdisplay), line:6074:9, endln:6078:20 - |vpiName:lce_cmd_lo.data |vpiActual: \_ref_obj: (lce_cmd_lo), line:6077:45, endln:6077:55 |vpiParent: @@ -79030,6 +79029,7 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo.data), line:6077:45, endln:6077:60 |vpiName:data |vpiFullName:work@bp_me_nonsynth_lce_tracer.data + |vpiName:lce_cmd_lo.data |vpiName:$fdisplay |vpiAlwaysType:3 |vpiContAssign: @@ -79120,7 +79120,6 @@ design: (work@testbench) \_hier_path: (lce_req.header.payload), line:6025:28, endln:6025:50 |vpiParent: \_cont_assign: , line:6025:10, endln:6025:50 - |vpiName:lce_req.header.payload |vpiActual: \_ref_obj: (lce_req), line:6025:28, endln:6025:35 |vpiParent: @@ -79137,6 +79136,7 @@ design: (work@testbench) \_hier_path: (lce_req.header.payload), line:6025:28, endln:6025:50 |vpiName:payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.payload + |vpiName:lce_req.header.payload |vpiLhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_req_payload), line:6025:10, endln:6025:25 |vpiParent: @@ -79153,7 +79153,6 @@ design: (work@testbench) \_hier_path: (lce_resp.header.payload), line:6026:29, endln:6026:52 |vpiParent: \_cont_assign: , line:6026:10, endln:6026:52 - |vpiName:lce_resp.header.payload |vpiActual: \_ref_obj: (lce_resp), line:6026:29, endln:6026:37 |vpiParent: @@ -79170,6 +79169,7 @@ design: (work@testbench) \_hier_path: (lce_resp.header.payload), line:6026:29, endln:6026:52 |vpiName:payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.payload + |vpiName:lce_resp.header.payload |vpiLhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_resp_payload), line:6026:10, endln:6026:26 |vpiParent: @@ -79186,7 +79186,6 @@ design: (work@testbench) \_hier_path: (lce_cmd.header.payload), line:6027:28, endln:6027:50 |vpiParent: \_cont_assign: , line:6027:10, endln:6027:50 - |vpiName:lce_cmd.header.payload |vpiActual: \_ref_obj: (lce_cmd), line:6027:28, endln:6027:35 |vpiParent: @@ -79203,6 +79202,7 @@ design: (work@testbench) \_hier_path: (lce_cmd.header.payload), line:6027:28, endln:6027:50 |vpiName:payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.payload + |vpiName:lce_cmd.header.payload |vpiLhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_cmd_payload), line:6027:10, endln:6027:25 |vpiParent: @@ -79219,7 +79219,6 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo.header.payload), line:6028:31, endln:6028:56 |vpiParent: \_cont_assign: , line:6028:10, endln:6028:56 - |vpiName:lce_cmd_lo.header.payload |vpiActual: \_ref_obj: (lce_cmd_lo), line:6028:31, endln:6028:41 |vpiParent: @@ -79236,6 +79235,7 @@ design: (work@testbench) \_hier_path: (lce_cmd_lo.header.payload), line:6028:31, endln:6028:56 |vpiName:payload |vpiFullName:work@bp_me_nonsynth_lce_tracer.payload + |vpiName:lce_cmd_lo.header.payload |vpiLhs: \_ref_obj: (work@bp_me_nonsynth_lce_tracer.lce_cmd_lo_payload), line:6028:10, endln:6028:28 |vpiParent: @@ -90339,7 +90339,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.multicore), line:6096:30, endln:6096:53 |vpiParent: \_param_assign: , line:6096:16, endln:6096:53 - |vpiName:proc_param_lp.multicore |vpiActual: \_ref_obj: (proc_param_lp), line:6096:44, endln:6096:53 |vpiParent: @@ -90350,6 +90349,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.multicore), line:6096:30, endln:6096:53 |vpiName:multicore + |vpiName:proc_param_lp.multicore |vpiLhs: \_parameter: (work@testbench.multicore_p), line:6096:16, endln:6096:27 |vpiParamAssign: @@ -90360,7 +90360,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiParent: \_param_assign: , line:6098:16, endln:6098:52 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -90371,6 +90370,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiLhs: \_parameter: (work@testbench.cc_x_dim_p), line:6098:16, endln:6098:26 |vpiParamAssign: @@ -90381,7 +90381,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiParent: \_param_assign: , line:6099:16, endln:6099:52 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -90392,6 +90391,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.cc_y_dim_p), line:6099:16, endln:6099:26 |vpiParamAssign: @@ -90414,7 +90414,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6102:29, endln:6102:51 |vpiParent: \_param_assign: , line:6102:16, endln:6102:51 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -90425,6 +90424,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6102:29, endln:6102:51 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiLhs: \_parameter: (work@testbench.ic_y_dim_p), line:6102:16, endln:6102:26 |vpiParamAssign: @@ -90447,7 +90447,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mc_y_dim), line:6104:29, endln:6104:51 |vpiParent: \_param_assign: , line:6104:16, endln:6104:51 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -90458,6 +90457,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6104:29, endln:6104:51 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiLhs: \_parameter: (work@testbench.mc_y_dim_p), line:6104:16, endln:6104:26 |vpiParamAssign: @@ -90468,7 +90468,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cac_x_dim), line:6105:30, endln:6105:53 |vpiParent: \_param_assign: , line:6105:16, endln:6105:53 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -90479,6 +90478,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6105:30, endln:6105:53 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiLhs: \_parameter: (work@testbench.cac_x_dim_p), line:6105:16, endln:6105:27 |vpiParamAssign: @@ -90501,7 +90501,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6107:30, endln:6107:53 |vpiParent: \_param_assign: , line:6107:16, endln:6107:53 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -90512,6 +90511,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6107:30, endln:6107:53 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiLhs: \_parameter: (work@testbench.sac_x_dim_p), line:6107:16, endln:6107:27 |vpiParamAssign: @@ -90534,7 +90534,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cacc_type), line:6109:30, endln:6109:53 |vpiParent: \_param_assign: , line:6109:16, endln:6109:53 - |vpiName:proc_param_lp.cacc_type |vpiActual: \_ref_obj: (proc_param_lp), line:6109:44, endln:6109:53 |vpiParent: @@ -90545,6 +90544,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cacc_type), line:6109:30, endln:6109:53 |vpiName:cacc_type + |vpiName:proc_param_lp.cacc_type |vpiLhs: \_parameter: (work@testbench.cacc_type_p), line:6109:16, endln:6109:27 |vpiParamAssign: @@ -90555,7 +90555,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sacc_type), line:6110:30, endln:6110:53 |vpiParent: \_param_assign: , line:6110:16, endln:6110:53 - |vpiName:proc_param_lp.sacc_type |vpiActual: \_ref_obj: (proc_param_lp), line:6110:44, endln:6110:53 |vpiParent: @@ -90566,6 +90565,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sacc_type), line:6110:30, endln:6110:53 |vpiName:sacc_type + |vpiName:proc_param_lp.sacc_type |vpiLhs: \_parameter: (work@testbench.sacc_type_p), line:6110:16, endln:6110:27 |vpiParamAssign: @@ -90691,7 +90691,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.num_cce), line:6118:28, endln:6118:49 |vpiParent: \_param_assign: , line:6118:16, endln:6118:49 - |vpiName:proc_param_lp.num_cce |vpiActual: \_ref_obj: (proc_param_lp), line:6118:42, endln:6118:49 |vpiParent: @@ -90702,6 +90701,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.num_cce), line:6118:28, endln:6118:49 |vpiName:num_cce + |vpiName:proc_param_lp.num_cce |vpiLhs: \_parameter: (work@testbench.num_cce_p), line:6118:16, endln:6118:25 |vpiParamAssign: @@ -90712,7 +90712,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.num_lce), line:6119:28, endln:6119:49 |vpiParent: \_param_assign: , line:6119:16, endln:6119:49 - |vpiName:proc_param_lp.num_lce |vpiActual: \_ref_obj: (proc_param_lp), line:6119:42, endln:6119:49 |vpiParent: @@ -90723,6 +90722,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.num_lce), line:6119:28, endln:6119:49 |vpiName:num_lce + |vpiName:proc_param_lp.num_lce |vpiLhs: \_parameter: (work@testbench.num_lce_p), line:6119:16, endln:6119:25 |vpiParamAssign: @@ -91154,7 +91154,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6125:32, endln:6125:57 |vpiParent: \_param_assign: , line:6125:16, endln:6125:57 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -91165,6 +91164,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6125:32, endln:6125:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiLhs: \_parameter: (work@testbench.vaddr_width_p), line:6125:16, endln:6125:29 |vpiParamAssign: @@ -91175,7 +91175,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6126:32, endln:6126:57 |vpiParent: \_param_assign: , line:6126:16, endln:6126:57 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -91186,6 +91185,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6126:32, endln:6126:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiLhs: \_parameter: (work@testbench.paddr_width_p), line:6126:16, endln:6126:29 |vpiParamAssign: @@ -91196,7 +91196,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6127:32, endln:6127:56 |vpiParent: \_param_assign: , line:6127:16, endln:6127:56 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -91207,6 +91206,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6127:32, endln:6127:56 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiLhs: \_parameter: (work@testbench.asid_width_p), line:6127:16, endln:6127:28 |vpiParamAssign: @@ -91217,7 +91217,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.boot_pc), line:6129:34, endln:6129:55 |vpiParent: \_param_assign: , line:6129:16, endln:6129:55 - |vpiName:proc_param_lp.boot_pc |vpiActual: \_ref_obj: (proc_param_lp), line:6129:48, endln:6129:55 |vpiParent: @@ -91228,6 +91227,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.boot_pc), line:6129:34, endln:6129:55 |vpiName:boot_pc + |vpiName:proc_param_lp.boot_pc |vpiLhs: \_parameter: (work@testbench.boot_pc_p), line:6129:16, endln:6129:25 |vpiParamAssign: @@ -91238,7 +91238,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.boot_in_debug), line:6130:34, endln:6130:61 |vpiParent: \_param_assign: , line:6130:16, endln:6130:61 - |vpiName:proc_param_lp.boot_in_debug |vpiActual: \_ref_obj: (proc_param_lp), line:6130:48, endln:6130:61 |vpiParent: @@ -91249,6 +91248,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.boot_in_debug), line:6130:34, endln:6130:61 |vpiName:boot_in_debug + |vpiName:proc_param_lp.boot_in_debug |vpiLhs: \_parameter: (work@testbench.boot_in_debug_p), line:6130:16, endln:6130:31 |vpiParamAssign: @@ -91259,7 +91259,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6132:46, endln:6132:85 |vpiParent: \_param_assign: , line:6132:16, endln:6132:85 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -91270,6 +91269,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6132:46, endln:6132:85 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiLhs: \_parameter: (work@testbench.branch_metadata_fwd_width_p), line:6132:16, endln:6132:43 |vpiParamAssign: @@ -91280,7 +91280,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.btb_tag_width), line:6133:46, endln:6133:73 |vpiParent: \_param_assign: , line:6133:16, endln:6133:73 - |vpiName:proc_param_lp.btb_tag_width |vpiActual: \_ref_obj: (proc_param_lp), line:6133:60, endln:6133:73 |vpiParent: @@ -91291,6 +91290,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.btb_tag_width), line:6133:46, endln:6133:73 |vpiName:btb_tag_width + |vpiName:proc_param_lp.btb_tag_width |vpiLhs: \_parameter: (work@testbench.btb_tag_width_p), line:6133:16, endln:6133:31 |vpiParamAssign: @@ -91301,7 +91301,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.btb_idx_width), line:6134:46, endln:6134:73 |vpiParent: \_param_assign: , line:6134:16, endln:6134:73 - |vpiName:proc_param_lp.btb_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:6134:60, endln:6134:73 |vpiParent: @@ -91312,6 +91311,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.btb_idx_width), line:6134:46, endln:6134:73 |vpiName:btb_idx_width + |vpiName:proc_param_lp.btb_idx_width |vpiLhs: \_parameter: (work@testbench.btb_idx_width_p), line:6134:16, endln:6134:31 |vpiParamAssign: @@ -91322,7 +91322,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.bht_idx_width), line:6135:46, endln:6135:73 |vpiParent: \_param_assign: , line:6135:16, endln:6135:73 - |vpiName:proc_param_lp.bht_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:6135:60, endln:6135:73 |vpiParent: @@ -91333,6 +91332,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.bht_idx_width), line:6135:46, endln:6135:73 |vpiName:bht_idx_width + |vpiName:proc_param_lp.bht_idx_width |vpiLhs: \_parameter: (work@testbench.bht_idx_width_p), line:6135:16, endln:6135:31 |vpiParamAssign: @@ -91343,7 +91343,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ghist_width), line:6136:46, endln:6136:71 |vpiParent: \_param_assign: , line:6136:16, endln:6136:71 - |vpiName:proc_param_lp.ghist_width |vpiActual: \_ref_obj: (proc_param_lp), line:6136:60, endln:6136:71 |vpiParent: @@ -91354,6 +91353,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ghist_width), line:6136:46, endln:6136:71 |vpiName:ghist_width + |vpiName:proc_param_lp.ghist_width |vpiLhs: \_parameter: (work@testbench.ghist_width_p), line:6136:16, endln:6136:29 |vpiParamAssign: @@ -91364,7 +91364,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.itlb_els), line:6138:42, endln:6138:64 |vpiParent: \_param_assign: , line:6138:16, endln:6138:64 - |vpiName:proc_param_lp.itlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:6138:56, endln:6138:64 |vpiParent: @@ -91375,6 +91374,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.itlb_els), line:6138:42, endln:6138:64 |vpiName:itlb_els + |vpiName:proc_param_lp.itlb_els |vpiLhs: \_parameter: (work@testbench.itlb_els_p), line:6138:16, endln:6138:26 |vpiParamAssign: @@ -91385,7 +91385,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dtlb_els), line:6139:42, endln:6139:64 |vpiParent: \_param_assign: , line:6139:16, endln:6139:64 - |vpiName:proc_param_lp.dtlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:6139:56, endln:6139:64 |vpiParent: @@ -91396,6 +91395,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dtlb_els), line:6139:42, endln:6139:64 |vpiName:dtlb_els + |vpiName:proc_param_lp.dtlb_els |vpiLhs: \_parameter: (work@testbench.dtlb_els_p), line:6139:16, endln:6139:26 |vpiParamAssign: @@ -91406,7 +91406,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.lr_sc), line:6141:45, endln:6141:64 |vpiParent: \_param_assign: , line:6141:16, endln:6141:64 - |vpiName:proc_param_lp.lr_sc |vpiActual: \_ref_obj: (proc_param_lp), line:6141:59, endln:6141:64 |vpiParent: @@ -91417,6 +91416,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.lr_sc), line:6141:45, endln:6141:64 |vpiName:lr_sc + |vpiName:proc_param_lp.lr_sc |vpiLhs: \_parameter: (work@testbench.lr_sc_p), line:6141:16, endln:6141:23 |vpiParamAssign: @@ -91427,7 +91427,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_swap), line:6142:45, endln:6142:67 |vpiParent: \_param_assign: , line:6142:16, endln:6142:67 - |vpiName:proc_param_lp.amo_swap |vpiActual: \_ref_obj: (proc_param_lp), line:6142:59, endln:6142:67 |vpiParent: @@ -91438,6 +91437,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_swap), line:6142:45, endln:6142:67 |vpiName:amo_swap + |vpiName:proc_param_lp.amo_swap |vpiLhs: \_parameter: (work@testbench.amo_swap_p), line:6142:16, endln:6142:26 |vpiParamAssign: @@ -91448,7 +91448,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_fetch_logic), line:6143:45, endln:6143:74 |vpiParent: \_param_assign: , line:6143:16, endln:6143:74 - |vpiName:proc_param_lp.amo_fetch_logic |vpiActual: \_ref_obj: (proc_param_lp), line:6143:59, endln:6143:74 |vpiParent: @@ -91459,6 +91458,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_fetch_logic), line:6143:45, endln:6143:74 |vpiName:amo_fetch_logic + |vpiName:proc_param_lp.amo_fetch_logic |vpiLhs: \_parameter: (work@testbench.amo_fetch_logic_p), line:6143:16, endln:6143:33 |vpiParamAssign: @@ -91469,7 +91469,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:6144:45, endln:6144:79 |vpiParent: \_param_assign: , line:6144:16, endln:6144:79 - |vpiName:proc_param_lp.amo_fetch_arithmetic |vpiActual: \_ref_obj: (proc_param_lp), line:6144:59, endln:6144:79 |vpiParent: @@ -91480,6 +91479,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:6144:45, endln:6144:79 |vpiName:amo_fetch_arithmetic + |vpiName:proc_param_lp.amo_fetch_arithmetic |vpiLhs: \_parameter: (work@testbench.amo_fetch_arithmetic_p), line:6144:16, endln:6144:38 |vpiParamAssign: @@ -91490,7 +91490,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l1_coherent), line:6146:45, endln:6146:70 |vpiParent: \_param_assign: , line:6146:16, endln:6146:70 - |vpiName:proc_param_lp.l1_coherent |vpiActual: \_ref_obj: (proc_param_lp), line:6146:59, endln:6146:70 |vpiParent: @@ -91501,6 +91500,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l1_coherent), line:6146:45, endln:6146:70 |vpiName:l1_coherent + |vpiName:proc_param_lp.l1_coherent |vpiLhs: \_parameter: (work@testbench.l1_coherent_p), line:6146:16, endln:6146:29 |vpiParamAssign: @@ -91511,7 +91511,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l1_writethrough), line:6147:45, endln:6147:74 |vpiParent: \_param_assign: , line:6147:16, endln:6147:74 - |vpiName:proc_param_lp.l1_writethrough |vpiActual: \_ref_obj: (proc_param_lp), line:6147:59, endln:6147:74 |vpiParent: @@ -91522,6 +91521,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l1_writethrough), line:6147:45, endln:6147:74 |vpiName:l1_writethrough + |vpiName:proc_param_lp.l1_writethrough |vpiLhs: \_parameter: (work@testbench.l1_writethrough_p), line:6147:16, endln:6147:33 |vpiParamAssign: @@ -91532,7 +91532,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_sets), line:6148:45, endln:6148:70 |vpiParent: \_param_assign: , line:6148:16, endln:6148:70 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6148:59, endln:6148:70 |vpiParent: @@ -91543,6 +91542,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:6148:45, endln:6148:70 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiLhs: \_parameter: (work@testbench.dcache_sets_p), line:6148:16, endln:6148:29 |vpiParamAssign: @@ -91553,7 +91553,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_assoc), line:6149:45, endln:6149:71 |vpiParent: \_param_assign: , line:6149:16, endln:6149:71 - |vpiName:proc_param_lp.dcache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6149:59, endln:6149:71 |vpiParent: @@ -91564,6 +91563,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_assoc), line:6149:45, endln:6149:71 |vpiName:dcache_assoc + |vpiName:proc_param_lp.dcache_assoc |vpiLhs: \_parameter: (work@testbench.dcache_assoc_p), line:6149:16, endln:6149:30 |vpiParamAssign: @@ -91574,7 +91574,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_block_width), line:6150:45, endln:6150:77 |vpiParent: \_param_assign: , line:6150:16, endln:6150:77 - |vpiName:proc_param_lp.dcache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6150:59, endln:6150:77 |vpiParent: @@ -91585,6 +91584,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_block_width), line:6150:45, endln:6150:77 |vpiName:dcache_block_width + |vpiName:proc_param_lp.dcache_block_width |vpiLhs: \_parameter: (work@testbench.dcache_block_width_p), line:6150:16, endln:6150:36 |vpiParamAssign: @@ -91595,7 +91595,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_fill_width), line:6151:45, endln:6151:76 |vpiParent: \_param_assign: , line:6151:16, endln:6151:76 - |vpiName:proc_param_lp.dcache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:6151:59, endln:6151:76 |vpiParent: @@ -91606,6 +91605,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_fill_width), line:6151:45, endln:6151:76 |vpiName:dcache_fill_width + |vpiName:proc_param_lp.dcache_fill_width |vpiLhs: \_parameter: (work@testbench.dcache_fill_width_p), line:6151:16, endln:6151:35 |vpiParamAssign: @@ -91616,7 +91616,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_sets), line:6152:45, endln:6152:70 |vpiParent: \_param_assign: , line:6152:16, endln:6152:70 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -91627,6 +91626,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6152:45, endln:6152:70 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiLhs: \_parameter: (work@testbench.icache_sets_p), line:6152:16, endln:6152:29 |vpiParamAssign: @@ -91637,7 +91637,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_assoc), line:6153:45, endln:6153:71 |vpiParent: \_param_assign: , line:6153:16, endln:6153:71 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6153:59, endln:6153:71 |vpiParent: @@ -91648,6 +91647,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:6153:45, endln:6153:71 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiLhs: \_parameter: (work@testbench.icache_assoc_p), line:6153:16, endln:6153:30 |vpiParamAssign: @@ -91658,7 +91658,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_block_width), line:6154:45, endln:6154:77 |vpiParent: \_param_assign: , line:6154:16, endln:6154:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6154:59, endln:6154:77 |vpiParent: @@ -91669,6 +91668,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:6154:45, endln:6154:77 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiLhs: \_parameter: (work@testbench.icache_block_width_p), line:6154:16, endln:6154:36 |vpiParamAssign: @@ -91679,7 +91679,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_fill_width), line:6155:45, endln:6155:76 |vpiParent: \_param_assign: , line:6155:16, endln:6155:76 - |vpiName:proc_param_lp.icache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:6155:59, endln:6155:76 |vpiParent: @@ -91690,6 +91689,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_fill_width), line:6155:45, endln:6155:76 |vpiName:icache_fill_width + |vpiName:proc_param_lp.icache_fill_width |vpiLhs: \_parameter: (work@testbench.icache_fill_width_p), line:6155:16, endln:6155:35 |vpiParamAssign: @@ -91700,7 +91700,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_sets), line:6156:45, endln:6156:70 |vpiParent: \_param_assign: , line:6156:16, endln:6156:70 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6156:59, endln:6156:70 |vpiParent: @@ -91711,6 +91710,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:6156:45, endln:6156:70 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiLhs: \_parameter: (work@testbench.acache_sets_p), line:6156:16, endln:6156:29 |vpiParamAssign: @@ -91721,7 +91721,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_assoc), line:6157:45, endln:6157:71 |vpiParent: \_param_assign: , line:6157:16, endln:6157:71 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6157:59, endln:6157:71 |vpiParent: @@ -91732,6 +91731,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:6157:45, endln:6157:71 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiLhs: \_parameter: (work@testbench.acache_assoc_p), line:6157:16, endln:6157:30 |vpiParamAssign: @@ -91742,7 +91742,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_block_width), line:6158:45, endln:6158:77 |vpiParent: \_param_assign: , line:6158:16, endln:6158:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6158:59, endln:6158:77 |vpiParent: @@ -91753,6 +91752,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:6158:45, endln:6158:77 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiLhs: \_parameter: (work@testbench.acache_block_width_p), line:6158:16, endln:6158:36 |vpiParamAssign: @@ -91763,7 +91763,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_fill_width), line:6159:45, endln:6159:76 |vpiParent: \_param_assign: , line:6159:16, endln:6159:76 - |vpiName:proc_param_lp.acache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:6159:59, endln:6159:76 |vpiParent: @@ -91774,6 +91773,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_fill_width), line:6159:45, endln:6159:76 |vpiName:acache_fill_width + |vpiName:proc_param_lp.acache_fill_width |vpiLhs: \_parameter: (work@testbench.acache_fill_width_p), line:6159:16, endln:6159:35 |vpiParamAssign: @@ -92170,7 +92170,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_pc_width), line:6183:45, endln:6183:71 |vpiParent: \_param_assign: , line:6183:16, endln:6183:71 - |vpiName:proc_param_lp.cce_pc_width |vpiActual: \_ref_obj: (proc_param_lp), line:6183:59, endln:6183:71 |vpiParent: @@ -92181,6 +92180,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_pc_width), line:6183:45, endln:6183:71 |vpiName:cce_pc_width + |vpiName:proc_param_lp.cce_pc_width |vpiLhs: \_parameter: (work@testbench.cce_pc_width_p), line:6183:16, endln:6183:30 |vpiParamAssign: @@ -92277,7 +92277,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_ucode), line:6187:45, endln:6187:68 |vpiParent: \_param_assign: , line:6187:16, endln:6187:68 - |vpiName:proc_param_lp.cce_ucode |vpiActual: \_ref_obj: (proc_param_lp), line:6187:59, endln:6187:68 |vpiParent: @@ -92288,6 +92287,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_ucode), line:6187:45, endln:6187:68 |vpiName:cce_ucode + |vpiName:proc_param_lp.cce_ucode |vpiLhs: \_parameter: (work@testbench.cce_ucode_p), line:6187:16, endln:6187:27 |vpiParamAssign: @@ -92298,7 +92298,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_en), line:6189:29, endln:6189:48 |vpiParent: \_param_assign: , line:6189:16, endln:6189:48 - |vpiName:proc_param_lp.l2_en |vpiActual: \_ref_obj: (proc_param_lp), line:6189:43, endln:6189:48 |vpiParent: @@ -92309,6 +92308,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_en), line:6189:29, endln:6189:48 |vpiName:l2_en + |vpiName:proc_param_lp.l2_en |vpiLhs: \_parameter: (work@testbench.l2_en_p), line:6189:16, endln:6189:23 |vpiParamAssign: @@ -92319,7 +92319,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_sets), line:6190:29, endln:6190:50 |vpiParent: \_param_assign: , line:6190:16, endln:6190:50 - |vpiName:proc_param_lp.l2_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6190:43, endln:6190:50 |vpiParent: @@ -92330,6 +92329,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_sets), line:6190:29, endln:6190:50 |vpiName:l2_sets + |vpiName:proc_param_lp.l2_sets |vpiLhs: \_parameter: (work@testbench.l2_sets_p), line:6190:16, endln:6190:25 |vpiParamAssign: @@ -92340,7 +92340,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_assoc), line:6191:29, endln:6191:51 |vpiParent: \_param_assign: , line:6191:16, endln:6191:51 - |vpiName:proc_param_lp.l2_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6191:43, endln:6191:51 |vpiParent: @@ -92351,6 +92350,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_assoc), line:6191:29, endln:6191:51 |vpiName:l2_assoc + |vpiName:proc_param_lp.l2_assoc |vpiLhs: \_parameter: (work@testbench.l2_assoc_p), line:6191:16, endln:6191:26 |vpiParamAssign: @@ -92361,7 +92361,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:6192:40, endln:6192:73 |vpiParent: \_param_assign: , line:6192:16, endln:6192:73 - |vpiName:proc_param_lp.l2_outstanding_reqs |vpiActual: \_ref_obj: (proc_param_lp), line:6192:54, endln:6192:73 |vpiParent: @@ -92372,6 +92371,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:6192:40, endln:6192:73 |vpiName:l2_outstanding_reqs + |vpiName:proc_param_lp.l2_outstanding_reqs |vpiLhs: \_parameter: (work@testbench.l2_outstanding_reqs_p), line:6192:16, endln:6192:37 |vpiParamAssign: @@ -92382,7 +92382,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:6194:38, endln:6194:69 |vpiParent: \_param_assign: , line:6194:16, endln:6194:69 - |vpiName:proc_param_lp.fe_queue_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:6194:52, endln:6194:69 |vpiParent: @@ -92393,6 +92392,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:6194:38, endln:6194:69 |vpiName:fe_queue_fifo_els + |vpiName:proc_param_lp.fe_queue_fifo_els |vpiLhs: \_parameter: (work@testbench.fe_queue_fifo_els_p), line:6194:16, endln:6194:35 |vpiParamAssign: @@ -92403,7 +92403,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:6195:38, endln:6195:67 |vpiParent: \_param_assign: , line:6195:16, endln:6195:67 - |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:6195:52, endln:6195:67 |vpiParent: @@ -92414,6 +92413,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:6195:38, endln:6195:67 |vpiName:fe_cmd_fifo_els + |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiLhs: \_parameter: (work@testbench.fe_cmd_fifo_els_p), line:6195:16, endln:6195:33 |vpiParamAssign: @@ -92424,7 +92424,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_coh_clk), line:6197:41, endln:6197:68 |vpiParent: \_param_assign: , line:6197:16, endln:6197:68 - |vpiName:proc_param_lp.async_coh_clk |vpiActual: \_ref_obj: (proc_param_lp), line:6197:55, endln:6197:68 |vpiParent: @@ -92435,6 +92434,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_coh_clk), line:6197:41, endln:6197:68 |vpiName:async_coh_clk + |vpiName:proc_param_lp.async_coh_clk |vpiLhs: \_parameter: (work@testbench.async_coh_clk_p), line:6197:16, endln:6197:31 |vpiParamAssign: @@ -92445,7 +92445,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_max_credits), line:6198:41, endln:6198:74 |vpiParent: \_param_assign: , line:6198:16, endln:6198:74 - |vpiName:proc_param_lp.coh_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:6198:55, endln:6198:74 |vpiParent: @@ -92456,6 +92455,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_max_credits), line:6198:41, endln:6198:74 |vpiName:coh_noc_max_credits + |vpiName:proc_param_lp.coh_noc_max_credits |vpiLhs: \_parameter: (work@testbench.coh_noc_max_credits_p), line:6198:16, endln:6198:37 |vpiParamAssign: @@ -92466,7 +92466,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_flit_width), line:6199:41, endln:6199:73 |vpiParent: \_param_assign: , line:6199:16, endln:6199:73 - |vpiName:proc_param_lp.coh_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:6199:55, endln:6199:73 |vpiParent: @@ -92477,6 +92476,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:6199:41, endln:6199:73 |vpiName:coh_noc_flit_width + |vpiName:proc_param_lp.coh_noc_flit_width |vpiLhs: \_parameter: (work@testbench.coh_noc_flit_width_p), line:6199:16, endln:6199:36 |vpiParamAssign: @@ -92487,7 +92487,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_cid_width), line:6200:41, endln:6200:72 |vpiParent: \_param_assign: , line:6200:16, endln:6200:72 - |vpiName:proc_param_lp.coh_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6200:55, endln:6200:72 |vpiParent: @@ -92498,6 +92497,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:6200:41, endln:6200:72 |vpiName:coh_noc_cid_width + |vpiName:proc_param_lp.coh_noc_cid_width |vpiLhs: \_parameter: (work@testbench.coh_noc_cid_width_p), line:6200:16, endln:6200:35 |vpiParamAssign: @@ -92508,7 +92508,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_len_width), line:6201:41, endln:6201:72 |vpiParent: \_param_assign: , line:6201:16, endln:6201:72 - |vpiName:proc_param_lp.coh_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:6201:55, endln:6201:72 |vpiParent: @@ -92519,6 +92518,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_len_width), line:6201:41, endln:6201:72 |vpiName:coh_noc_len_width + |vpiName:proc_param_lp.coh_noc_len_width |vpiLhs: \_parameter: (work@testbench.coh_noc_len_width_p), line:6201:16, endln:6201:35 |vpiParamAssign: @@ -92950,7 +92950,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_mem_clk), line:6212:44, endln:6212:71 |vpiParent: \_param_assign: , line:6212:16, endln:6212:71 - |vpiName:proc_param_lp.async_mem_clk |vpiActual: \_ref_obj: (proc_param_lp), line:6212:58, endln:6212:71 |vpiParent: @@ -92961,6 +92960,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_mem_clk), line:6212:44, endln:6212:71 |vpiName:async_mem_clk + |vpiName:proc_param_lp.async_mem_clk |vpiLhs: \_parameter: (work@testbench.async_mem_clk_p), line:6212:16, endln:6212:31 |vpiParamAssign: @@ -92971,7 +92971,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_max_credits), line:6213:44, endln:6213:77 |vpiParent: \_param_assign: , line:6213:16, endln:6213:77 - |vpiName:proc_param_lp.mem_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:6213:58, endln:6213:77 |vpiParent: @@ -92982,6 +92981,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:6213:44, endln:6213:77 |vpiName:mem_noc_max_credits + |vpiName:proc_param_lp.mem_noc_max_credits |vpiLhs: \_parameter: (work@testbench.mem_noc_max_credits_p), line:6213:16, endln:6213:37 |vpiParamAssign: @@ -92992,7 +92992,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_flit_width), line:6214:44, endln:6214:76 |vpiParent: \_param_assign: , line:6214:16, endln:6214:76 - |vpiName:proc_param_lp.mem_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:6214:58, endln:6214:76 |vpiParent: @@ -93003,6 +93002,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:6214:44, endln:6214:76 |vpiName:mem_noc_flit_width + |vpiName:proc_param_lp.mem_noc_flit_width |vpiLhs: \_parameter: (work@testbench.mem_noc_flit_width_p), line:6214:16, endln:6214:36 |vpiParamAssign: @@ -93013,7 +93013,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_cid_width), line:6215:44, endln:6215:75 |vpiParent: \_param_assign: , line:6215:16, endln:6215:75 - |vpiName:proc_param_lp.mem_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6215:58, endln:6215:75 |vpiParent: @@ -93024,6 +93023,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:6215:44, endln:6215:75 |vpiName:mem_noc_cid_width + |vpiName:proc_param_lp.mem_noc_cid_width |vpiLhs: \_parameter: (work@testbench.mem_noc_cid_width_p), line:6215:16, endln:6215:35 |vpiParamAssign: @@ -93034,7 +93034,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_len_width), line:6216:44, endln:6216:75 |vpiParent: \_param_assign: , line:6216:16, endln:6216:75 - |vpiName:proc_param_lp.mem_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:6216:58, endln:6216:75 |vpiParent: @@ -93045,6 +93044,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_len_width), line:6216:44, endln:6216:75 |vpiName:mem_noc_len_width + |vpiName:proc_param_lp.mem_noc_len_width |vpiLhs: \_parameter: (work@testbench.mem_noc_len_width_p), line:6216:16, endln:6216:35 |vpiParamAssign: @@ -93399,7 +93399,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_io_clk), line:6228:43, endln:6228:69 |vpiParent: \_param_assign: , line:6228:16, endln:6228:69 - |vpiName:proc_param_lp.async_io_clk |vpiActual: \_ref_obj: (proc_param_lp), line:6228:57, endln:6228:69 |vpiParent: @@ -93410,6 +93409,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_io_clk), line:6228:43, endln:6228:69 |vpiName:async_io_clk + |vpiName:proc_param_lp.async_io_clk |vpiLhs: \_parameter: (work@testbench.async_io_clk_p), line:6228:16, endln:6228:30 |vpiParamAssign: @@ -93420,7 +93420,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_max_credits), line:6229:43, endln:6229:75 |vpiParent: \_param_assign: , line:6229:16, endln:6229:75 - |vpiName:proc_param_lp.io_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:6229:57, endln:6229:75 |vpiParent: @@ -93431,6 +93430,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_max_credits), line:6229:43, endln:6229:75 |vpiName:io_noc_max_credits + |vpiName:proc_param_lp.io_noc_max_credits |vpiLhs: \_parameter: (work@testbench.io_noc_max_credits_p), line:6229:16, endln:6229:36 |vpiParamAssign: @@ -93441,7 +93441,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiParent: \_param_assign: , line:6230:16, endln:6230:73 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:6230:57, endln:6230:73 |vpiParent: @@ -93452,6 +93451,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiLhs: \_parameter: (work@testbench.io_noc_did_width_p), line:6230:16, endln:6230:34 |vpiParamAssign: @@ -93462,7 +93462,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_flit_width), line:6231:43, endln:6231:74 |vpiParent: \_param_assign: , line:6231:16, endln:6231:74 - |vpiName:proc_param_lp.io_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:6231:57, endln:6231:74 |vpiParent: @@ -93473,6 +93472,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_flit_width), line:6231:43, endln:6231:74 |vpiName:io_noc_flit_width + |vpiName:proc_param_lp.io_noc_flit_width |vpiLhs: \_parameter: (work@testbench.io_noc_flit_width_p), line:6231:16, endln:6231:35 |vpiParamAssign: @@ -93483,7 +93483,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_cid_width), line:6232:43, endln:6232:73 |vpiParent: \_param_assign: , line:6232:16, endln:6232:73 - |vpiName:proc_param_lp.io_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6232:57, endln:6232:73 |vpiParent: @@ -93494,6 +93493,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_cid_width), line:6232:43, endln:6232:73 |vpiName:io_noc_cid_width + |vpiName:proc_param_lp.io_noc_cid_width |vpiLhs: \_parameter: (work@testbench.io_noc_cid_width_p), line:6232:16, endln:6232:34 |vpiParamAssign: @@ -93504,7 +93504,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_len_width), line:6233:43, endln:6233:73 |vpiParent: \_param_assign: , line:6233:16, endln:6233:73 - |vpiName:proc_param_lp.io_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:6233:57, endln:6233:73 |vpiParent: @@ -93515,6 +93514,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_len_width), line:6233:43, endln:6233:73 |vpiName:io_noc_len_width + |vpiName:proc_param_lp.io_noc_len_width |vpiLhs: \_parameter: (work@testbench.io_noc_len_width_p), line:6233:16, endln:6233:34 |vpiParamAssign: @@ -93893,7 +93893,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6252:32, endln:6252:57 |vpiParent: \_operation: , line:6252:32, endln:6252:79 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6252:46, endln:6252:57 |vpiParent: @@ -93904,6 +93903,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6252:32, endln:6252:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_ref_obj: (work@testbench.page_offset_width_p), line:6252:60, endln:6252:79 |vpiParent: @@ -93925,7 +93925,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6253:32, endln:6253:57 |vpiParent: \_operation: , line:6253:32, endln:6253:79 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6253:46, endln:6253:57 |vpiParent: @@ -93936,6 +93935,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6253:32, endln:6253:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_ref_obj: (work@testbench.page_offset_width_p), line:6253:60, endln:6253:79 |vpiParent: @@ -99014,7 +99014,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.multicore), line:6096:30, endln:6096:53 |vpiParent: \_param_assign: , line:6096:16, endln:6096:53 - |vpiName:proc_param_lp.multicore |vpiActual: \_ref_obj: (proc_param_lp), line:6096:44, endln:6096:53 |vpiParent: @@ -99027,6 +99026,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.multicore), line:6096:30, endln:6096:53 |vpiName:multicore + |vpiName:proc_param_lp.multicore |vpiLhs: \_parameter: (work@testbench.multicore_p), line:6096:16, endln:6096:27 |vpiParamAssign: @@ -99037,7 +99037,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiParent: \_param_assign: , line:6098:16, endln:6098:52 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99050,6 +99049,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiLhs: \_parameter: (work@testbench.cc_x_dim_p), line:6098:16, endln:6098:26 |vpiParamAssign: @@ -99060,7 +99060,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiParent: \_param_assign: , line:6099:16, endln:6099:52 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99073,6 +99072,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.cc_y_dim_p), line:6099:16, endln:6099:26 |vpiParamAssign: @@ -99083,7 +99083,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6101:29, endln:6101:39 |vpiParent: \_param_assign: , line:6098:16, endln:6098:52 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99096,6 +99095,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6101:29, endln:6101:39 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiLhs: \_parameter: (work@testbench.ic_x_dim_p), line:6101:16, endln:6101:26 |vpiParamAssign: @@ -99106,7 +99106,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6102:29, endln:6102:51 |vpiParent: \_param_assign: , line:6102:16, endln:6102:51 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -99119,6 +99118,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6102:29, endln:6102:51 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiLhs: \_parameter: (work@testbench.ic_y_dim_p), line:6102:16, endln:6102:26 |vpiParamAssign: @@ -99129,7 +99129,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6103:29, endln:6103:39 |vpiParent: \_param_assign: , line:6098:16, endln:6098:52 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99142,6 +99141,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6103:29, endln:6103:39 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiLhs: \_parameter: (work@testbench.mc_x_dim_p), line:6103:16, endln:6103:26 |vpiParamAssign: @@ -99152,7 +99152,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mc_y_dim), line:6104:29, endln:6104:51 |vpiParent: \_param_assign: , line:6104:16, endln:6104:51 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -99165,6 +99164,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6104:29, endln:6104:51 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiLhs: \_parameter: (work@testbench.mc_y_dim_p), line:6104:16, endln:6104:26 |vpiParamAssign: @@ -99175,7 +99175,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cac_x_dim), line:6105:30, endln:6105:53 |vpiParent: \_param_assign: , line:6105:16, endln:6105:53 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -99188,6 +99187,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6105:30, endln:6105:53 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiLhs: \_parameter: (work@testbench.cac_x_dim_p), line:6105:16, endln:6105:27 |vpiParamAssign: @@ -99198,7 +99198,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6106:30, endln:6106:40 |vpiParent: \_param_assign: , line:6099:16, endln:6099:52 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99211,6 +99210,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6106:30, endln:6106:40 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.cac_y_dim_p), line:6106:16, endln:6106:27 |vpiParamAssign: @@ -99221,7 +99221,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6107:30, endln:6107:53 |vpiParent: \_param_assign: , line:6107:16, endln:6107:53 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -99234,6 +99233,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6107:30, endln:6107:53 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiLhs: \_parameter: (work@testbench.sac_x_dim_p), line:6107:16, endln:6107:27 |vpiParamAssign: @@ -99244,7 +99244,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6108:30, endln:6108:40 |vpiParent: \_param_assign: , line:6099:16, endln:6099:52 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99257,6 +99256,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6108:30, endln:6108:40 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.sac_y_dim_p), line:6108:16, endln:6108:27 |vpiParamAssign: @@ -99267,7 +99267,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cacc_type), line:6109:30, endln:6109:53 |vpiParent: \_param_assign: , line:6109:16, endln:6109:53 - |vpiName:proc_param_lp.cacc_type |vpiActual: \_ref_obj: (proc_param_lp), line:6109:44, endln:6109:53 |vpiParent: @@ -99280,6 +99279,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cacc_type), line:6109:30, endln:6109:53 |vpiName:cacc_type + |vpiName:proc_param_lp.cacc_type |vpiLhs: \_parameter: (work@testbench.cacc_type_p), line:6109:16, endln:6109:27 |vpiParamAssign: @@ -99290,7 +99290,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sacc_type), line:6110:30, endln:6110:53 |vpiParent: \_param_assign: , line:6110:16, endln:6110:53 - |vpiName:proc_param_lp.sacc_type |vpiActual: \_ref_obj: (proc_param_lp), line:6110:44, endln:6110:53 |vpiParent: @@ -99303,6 +99302,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sacc_type), line:6110:30, endln:6110:53 |vpiName:sacc_type + |vpiName:proc_param_lp.sacc_type |vpiLhs: \_parameter: (work@testbench.sacc_type_p), line:6110:16, endln:6110:27 |vpiParamAssign: @@ -99318,7 +99318,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6112:30, endln:6112:40 |vpiParent: \_operation: , line:6112:30, endln:6112:53 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99331,11 +99330,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6112:30, endln:6112:40 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6112:43, endln:6112:53 |vpiParent: \_operation: , line:6112:30, endln:6112:53 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99348,6 +99347,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6112:43, endln:6112:53 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.num_core_p), line:6112:16, endln:6112:26 |vpiParamAssign: @@ -99363,7 +99363,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiParent: \_operation: , line:6113:30, endln:6113:53 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99376,11 +99375,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.ic_y_dim), line:6113:43, endln:6113:53 |vpiParent: \_operation: , line:6113:30, endln:6113:53 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -99393,6 +99392,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6113:43, endln:6113:53 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiLhs: \_parameter: (work@testbench.num_io_p), line:6113:16, endln:6113:24 |vpiParamAssign: @@ -99408,7 +99408,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiParent: \_operation: , line:6114:30, endln:6114:53 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99421,11 +99420,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6098:30, endln:6098:52 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6114:43, endln:6114:53 |vpiParent: \_operation: , line:6114:30, endln:6114:53 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -99438,6 +99437,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6114:43, endln:6114:53 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiLhs: \_parameter: (work@testbench.num_l2e_p), line:6114:16, endln:6114:25 |vpiParamAssign: @@ -99453,7 +99453,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cac_x_dim), line:6115:30, endln:6115:41 |vpiParent: \_operation: , line:6115:30, endln:6115:55 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -99466,11 +99465,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6115:30, endln:6115:41 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiParent: \_operation: , line:6115:30, endln:6115:55 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99483,6 +99482,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.num_cacc_p), line:6115:16, endln:6115:26 |vpiParamAssign: @@ -99498,7 +99498,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6116:30, endln:6116:41 |vpiParent: \_operation: , line:6116:30, endln:6116:55 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -99511,11 +99510,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6116:30, endln:6116:41 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiParent: \_operation: , line:6116:30, endln:6116:55 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99528,6 +99527,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6099:30, endln:6099:52 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiLhs: \_parameter: (work@testbench.num_sacc_p), line:6116:16, endln:6116:26 |vpiParamAssign: @@ -99538,7 +99538,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.num_cce), line:6118:28, endln:6118:49 |vpiParent: \_param_assign: , line:6118:16, endln:6118:49 - |vpiName:proc_param_lp.num_cce |vpiActual: \_ref_obj: (proc_param_lp), line:6118:42, endln:6118:49 |vpiParent: @@ -99551,6 +99550,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.num_cce), line:6118:28, endln:6118:49 |vpiName:num_cce + |vpiName:proc_param_lp.num_cce |vpiLhs: \_parameter: (work@testbench.num_cce_p), line:6118:16, endln:6118:25 |vpiParamAssign: @@ -99561,7 +99561,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.num_lce), line:6119:28, endln:6119:49 |vpiParent: \_param_assign: , line:6119:16, endln:6119:49 - |vpiName:proc_param_lp.num_lce |vpiActual: \_ref_obj: (proc_param_lp), line:6119:42, endln:6119:49 |vpiParent: @@ -99574,6 +99573,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.num_lce), line:6119:28, endln:6119:49 |vpiName:num_lce + |vpiName:proc_param_lp.num_lce |vpiLhs: \_parameter: (work@testbench.num_lce_p), line:6119:16, endln:6119:25 |vpiParamAssign: @@ -99599,7 +99599,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6121:38, endln:6121:48 |vpiParent: \_operation: , line:6121:38, endln:6121:59 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99612,11 +99611,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6121:38, endln:6121:48 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6121:49, endln:6121:59 |vpiParent: \_operation: , line:6121:38, endln:6121:59 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99629,6 +99628,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6121:49, endln:6121:59 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_constant: , line:6121:62, endln:6121:63 |vpiParent: @@ -99658,7 +99658,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6121:79, endln:6121:89 |vpiParent: \_operation: , line:6121:79, endln:6121:100 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99671,11 +99670,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6121:79, endln:6121:89 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6121:90, endln:6121:100 |vpiParent: \_operation: , line:6121:79, endln:6121:100 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99688,6 +99687,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6121:90, endln:6121:100 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiName:$clog2 |vpiLhs: \_parameter: (work@testbench.core_id_width_p), line:6121:16, endln:6121:31 @@ -99724,7 +99724,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6122:39, endln:6122:49 |vpiParent: \_operation: , line:6122:39, endln:6122:51 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99737,6 +99736,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6122:39, endln:6122:49 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_constant: , line:6122:50, endln:6122:51 |vpiParent: @@ -99767,7 +99767,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6122:56, endln:6122:66 |vpiParent: \_operation: , line:6122:56, endln:6122:68 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99780,6 +99779,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6122:56, endln:6122:66 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_constant: , line:6122:67, endln:6122:68 |vpiParent: @@ -99835,7 +99835,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6122:92, endln:6122:102 |vpiParent: \_operation: , line:6122:92, endln:6122:104 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99848,6 +99847,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6122:92, endln:6122:102 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_constant: , line:6122:103, endln:6122:104 |vpiParent: @@ -99878,7 +99878,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6122:109, endln:6122:119 |vpiParent: \_operation: , line:6122:109, endln:6122:121 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99891,6 +99890,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6122:109, endln:6122:119 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_constant: , line:6122:120, endln:6122:121 |vpiParent: @@ -99943,7 +99943,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6123:39, endln:6123:49 |vpiParent: \_operation: , line:6123:39, endln:6123:51 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -99956,6 +99955,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6123:39, endln:6123:49 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_constant: , line:6123:50, endln:6123:51 |vpiParent: @@ -99986,7 +99986,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6123:56, endln:6123:66 |vpiParent: \_operation: , line:6123:56, endln:6123:68 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -99999,6 +99998,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6123:56, endln:6123:66 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_constant: , line:6123:67, endln:6123:68 |vpiParent: @@ -100054,7 +100054,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_x_dim), line:6123:92, endln:6123:102 |vpiParent: \_operation: , line:6123:92, endln:6123:104 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -100067,6 +100066,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6123:92, endln:6123:102 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_constant: , line:6123:103, endln:6123:104 |vpiParent: @@ -100097,7 +100097,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cc_y_dim), line:6123:109, endln:6123:119 |vpiParent: \_operation: , line:6123:109, endln:6123:121 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -100110,6 +100109,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6123:109, endln:6123:119 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_constant: , line:6123:120, endln:6123:121 |vpiParent: @@ -100137,7 +100137,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6125:32, endln:6125:57 |vpiParent: \_param_assign: , line:6125:16, endln:6125:57 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -100150,6 +100149,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6125:32, endln:6125:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiLhs: \_parameter: (work@testbench.vaddr_width_p), line:6125:16, endln:6125:29 |vpiParamAssign: @@ -100160,7 +100160,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6126:32, endln:6126:57 |vpiParent: \_param_assign: , line:6126:16, endln:6126:57 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -100173,6 +100172,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6126:32, endln:6126:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiLhs: \_parameter: (work@testbench.paddr_width_p), line:6126:16, endln:6126:29 |vpiParamAssign: @@ -100183,7 +100183,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6127:32, endln:6127:56 |vpiParent: \_param_assign: , line:6127:16, endln:6127:56 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -100196,6 +100195,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6127:32, endln:6127:56 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiLhs: \_parameter: (work@testbench.asid_width_p), line:6127:16, endln:6127:28 |vpiParamAssign: @@ -100206,7 +100206,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.boot_pc), line:6129:34, endln:6129:55 |vpiParent: \_param_assign: , line:6129:16, endln:6129:55 - |vpiName:proc_param_lp.boot_pc |vpiActual: \_ref_obj: (proc_param_lp), line:6129:48, endln:6129:55 |vpiParent: @@ -100219,6 +100218,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.boot_pc), line:6129:34, endln:6129:55 |vpiName:boot_pc + |vpiName:proc_param_lp.boot_pc |vpiLhs: \_parameter: (work@testbench.boot_pc_p), line:6129:16, endln:6129:25 |vpiParamAssign: @@ -100229,7 +100229,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.boot_in_debug), line:6130:34, endln:6130:61 |vpiParent: \_param_assign: , line:6130:16, endln:6130:61 - |vpiName:proc_param_lp.boot_in_debug |vpiActual: \_ref_obj: (proc_param_lp), line:6130:48, endln:6130:61 |vpiParent: @@ -100242,6 +100241,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.boot_in_debug), line:6130:34, endln:6130:61 |vpiName:boot_in_debug + |vpiName:proc_param_lp.boot_in_debug |vpiLhs: \_parameter: (work@testbench.boot_in_debug_p), line:6130:16, endln:6130:31 |vpiParamAssign: @@ -100252,7 +100252,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6132:46, endln:6132:85 |vpiParent: \_param_assign: , line:6132:16, endln:6132:85 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -100265,6 +100264,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6132:46, endln:6132:85 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiLhs: \_parameter: (work@testbench.branch_metadata_fwd_width_p), line:6132:16, endln:6132:43 |vpiParamAssign: @@ -100275,7 +100275,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.btb_tag_width), line:6133:46, endln:6133:73 |vpiParent: \_param_assign: , line:6133:16, endln:6133:73 - |vpiName:proc_param_lp.btb_tag_width |vpiActual: \_ref_obj: (proc_param_lp), line:6133:60, endln:6133:73 |vpiParent: @@ -100288,6 +100287,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.btb_tag_width), line:6133:46, endln:6133:73 |vpiName:btb_tag_width + |vpiName:proc_param_lp.btb_tag_width |vpiLhs: \_parameter: (work@testbench.btb_tag_width_p), line:6133:16, endln:6133:31 |vpiParamAssign: @@ -100298,7 +100298,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.btb_idx_width), line:6134:46, endln:6134:73 |vpiParent: \_param_assign: , line:6134:16, endln:6134:73 - |vpiName:proc_param_lp.btb_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:6134:60, endln:6134:73 |vpiParent: @@ -100311,6 +100310,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.btb_idx_width), line:6134:46, endln:6134:73 |vpiName:btb_idx_width + |vpiName:proc_param_lp.btb_idx_width |vpiLhs: \_parameter: (work@testbench.btb_idx_width_p), line:6134:16, endln:6134:31 |vpiParamAssign: @@ -100321,7 +100321,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.bht_idx_width), line:6135:46, endln:6135:73 |vpiParent: \_param_assign: , line:6135:16, endln:6135:73 - |vpiName:proc_param_lp.bht_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:6135:60, endln:6135:73 |vpiParent: @@ -100334,6 +100333,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.bht_idx_width), line:6135:46, endln:6135:73 |vpiName:bht_idx_width + |vpiName:proc_param_lp.bht_idx_width |vpiLhs: \_parameter: (work@testbench.bht_idx_width_p), line:6135:16, endln:6135:31 |vpiParamAssign: @@ -100344,7 +100344,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ghist_width), line:6136:46, endln:6136:71 |vpiParent: \_param_assign: , line:6136:16, endln:6136:71 - |vpiName:proc_param_lp.ghist_width |vpiActual: \_ref_obj: (proc_param_lp), line:6136:60, endln:6136:71 |vpiParent: @@ -100357,6 +100356,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ghist_width), line:6136:46, endln:6136:71 |vpiName:ghist_width + |vpiName:proc_param_lp.ghist_width |vpiLhs: \_parameter: (work@testbench.ghist_width_p), line:6136:16, endln:6136:29 |vpiParamAssign: @@ -100367,7 +100367,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.itlb_els), line:6138:42, endln:6138:64 |vpiParent: \_param_assign: , line:6138:16, endln:6138:64 - |vpiName:proc_param_lp.itlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:6138:56, endln:6138:64 |vpiParent: @@ -100380,6 +100379,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.itlb_els), line:6138:42, endln:6138:64 |vpiName:itlb_els + |vpiName:proc_param_lp.itlb_els |vpiLhs: \_parameter: (work@testbench.itlb_els_p), line:6138:16, endln:6138:26 |vpiParamAssign: @@ -100390,7 +100390,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dtlb_els), line:6139:42, endln:6139:64 |vpiParent: \_param_assign: , line:6139:16, endln:6139:64 - |vpiName:proc_param_lp.dtlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:6139:56, endln:6139:64 |vpiParent: @@ -100403,6 +100402,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dtlb_els), line:6139:42, endln:6139:64 |vpiName:dtlb_els + |vpiName:proc_param_lp.dtlb_els |vpiLhs: \_parameter: (work@testbench.dtlb_els_p), line:6139:16, endln:6139:26 |vpiParamAssign: @@ -100413,7 +100413,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.lr_sc), line:6141:45, endln:6141:64 |vpiParent: \_param_assign: , line:6141:16, endln:6141:64 - |vpiName:proc_param_lp.lr_sc |vpiActual: \_ref_obj: (proc_param_lp), line:6141:59, endln:6141:64 |vpiParent: @@ -100426,6 +100425,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.lr_sc), line:6141:45, endln:6141:64 |vpiName:lr_sc + |vpiName:proc_param_lp.lr_sc |vpiLhs: \_parameter: (work@testbench.lr_sc_p), line:6141:16, endln:6141:23 |vpiParamAssign: @@ -100436,7 +100436,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_swap), line:6142:45, endln:6142:67 |vpiParent: \_param_assign: , line:6142:16, endln:6142:67 - |vpiName:proc_param_lp.amo_swap |vpiActual: \_ref_obj: (proc_param_lp), line:6142:59, endln:6142:67 |vpiParent: @@ -100449,6 +100448,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_swap), line:6142:45, endln:6142:67 |vpiName:amo_swap + |vpiName:proc_param_lp.amo_swap |vpiLhs: \_parameter: (work@testbench.amo_swap_p), line:6142:16, endln:6142:26 |vpiParamAssign: @@ -100459,7 +100459,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_fetch_logic), line:6143:45, endln:6143:74 |vpiParent: \_param_assign: , line:6143:16, endln:6143:74 - |vpiName:proc_param_lp.amo_fetch_logic |vpiActual: \_ref_obj: (proc_param_lp), line:6143:59, endln:6143:74 |vpiParent: @@ -100472,6 +100471,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_fetch_logic), line:6143:45, endln:6143:74 |vpiName:amo_fetch_logic + |vpiName:proc_param_lp.amo_fetch_logic |vpiLhs: \_parameter: (work@testbench.amo_fetch_logic_p), line:6143:16, endln:6143:33 |vpiParamAssign: @@ -100482,7 +100482,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:6144:45, endln:6144:79 |vpiParent: \_param_assign: , line:6144:16, endln:6144:79 - |vpiName:proc_param_lp.amo_fetch_arithmetic |vpiActual: \_ref_obj: (proc_param_lp), line:6144:59, endln:6144:79 |vpiParent: @@ -100495,6 +100494,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.amo_fetch_arithmetic), line:6144:45, endln:6144:79 |vpiName:amo_fetch_arithmetic + |vpiName:proc_param_lp.amo_fetch_arithmetic |vpiLhs: \_parameter: (work@testbench.amo_fetch_arithmetic_p), line:6144:16, endln:6144:38 |vpiParamAssign: @@ -100505,7 +100505,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l1_coherent), line:6146:45, endln:6146:70 |vpiParent: \_param_assign: , line:6146:16, endln:6146:70 - |vpiName:proc_param_lp.l1_coherent |vpiActual: \_ref_obj: (proc_param_lp), line:6146:59, endln:6146:70 |vpiParent: @@ -100518,6 +100517,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l1_coherent), line:6146:45, endln:6146:70 |vpiName:l1_coherent + |vpiName:proc_param_lp.l1_coherent |vpiLhs: \_parameter: (work@testbench.l1_coherent_p), line:6146:16, endln:6146:29 |vpiParamAssign: @@ -100528,7 +100528,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l1_writethrough), line:6147:45, endln:6147:74 |vpiParent: \_param_assign: , line:6147:16, endln:6147:74 - |vpiName:proc_param_lp.l1_writethrough |vpiActual: \_ref_obj: (proc_param_lp), line:6147:59, endln:6147:74 |vpiParent: @@ -100541,6 +100540,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l1_writethrough), line:6147:45, endln:6147:74 |vpiName:l1_writethrough + |vpiName:proc_param_lp.l1_writethrough |vpiLhs: \_parameter: (work@testbench.l1_writethrough_p), line:6147:16, endln:6147:33 |vpiParamAssign: @@ -100551,7 +100551,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_sets), line:6148:45, endln:6148:70 |vpiParent: \_param_assign: , line:6148:16, endln:6148:70 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6148:59, endln:6148:70 |vpiParent: @@ -100564,6 +100563,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:6148:45, endln:6148:70 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiLhs: \_parameter: (work@testbench.dcache_sets_p), line:6148:16, endln:6148:29 |vpiParamAssign: @@ -100574,7 +100574,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_assoc), line:6149:45, endln:6149:71 |vpiParent: \_param_assign: , line:6149:16, endln:6149:71 - |vpiName:proc_param_lp.dcache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6149:59, endln:6149:71 |vpiParent: @@ -100587,6 +100586,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_assoc), line:6149:45, endln:6149:71 |vpiName:dcache_assoc + |vpiName:proc_param_lp.dcache_assoc |vpiLhs: \_parameter: (work@testbench.dcache_assoc_p), line:6149:16, endln:6149:30 |vpiParamAssign: @@ -100597,7 +100597,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_block_width), line:6150:45, endln:6150:77 |vpiParent: \_param_assign: , line:6150:16, endln:6150:77 - |vpiName:proc_param_lp.dcache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6150:59, endln:6150:77 |vpiParent: @@ -100610,6 +100609,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_block_width), line:6150:45, endln:6150:77 |vpiName:dcache_block_width + |vpiName:proc_param_lp.dcache_block_width |vpiLhs: \_parameter: (work@testbench.dcache_block_width_p), line:6150:16, endln:6150:36 |vpiParamAssign: @@ -100620,7 +100620,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_fill_width), line:6151:45, endln:6151:76 |vpiParent: \_param_assign: , line:6151:16, endln:6151:76 - |vpiName:proc_param_lp.dcache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:6151:59, endln:6151:76 |vpiParent: @@ -100633,6 +100632,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_fill_width), line:6151:45, endln:6151:76 |vpiName:dcache_fill_width + |vpiName:proc_param_lp.dcache_fill_width |vpiLhs: \_parameter: (work@testbench.dcache_fill_width_p), line:6151:16, endln:6151:35 |vpiParamAssign: @@ -100643,7 +100643,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_sets), line:6152:45, endln:6152:70 |vpiParent: \_param_assign: , line:6152:16, endln:6152:70 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -100656,6 +100655,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6152:45, endln:6152:70 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiLhs: \_parameter: (work@testbench.icache_sets_p), line:6152:16, endln:6152:29 |vpiParamAssign: @@ -100666,7 +100666,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_assoc), line:6153:45, endln:6153:71 |vpiParent: \_param_assign: , line:6153:16, endln:6153:71 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6153:59, endln:6153:71 |vpiParent: @@ -100679,6 +100678,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:6153:45, endln:6153:71 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiLhs: \_parameter: (work@testbench.icache_assoc_p), line:6153:16, endln:6153:30 |vpiParamAssign: @@ -100689,7 +100689,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_block_width), line:6154:45, endln:6154:77 |vpiParent: \_param_assign: , line:6154:16, endln:6154:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6154:59, endln:6154:77 |vpiParent: @@ -100702,6 +100701,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:6154:45, endln:6154:77 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiLhs: \_parameter: (work@testbench.icache_block_width_p), line:6154:16, endln:6154:36 |vpiParamAssign: @@ -100712,7 +100712,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_fill_width), line:6155:45, endln:6155:76 |vpiParent: \_param_assign: , line:6155:16, endln:6155:76 - |vpiName:proc_param_lp.icache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:6155:59, endln:6155:76 |vpiParent: @@ -100725,6 +100724,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_fill_width), line:6155:45, endln:6155:76 |vpiName:icache_fill_width + |vpiName:proc_param_lp.icache_fill_width |vpiLhs: \_parameter: (work@testbench.icache_fill_width_p), line:6155:16, endln:6155:35 |vpiParamAssign: @@ -100735,7 +100735,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_sets), line:6156:45, endln:6156:70 |vpiParent: \_param_assign: , line:6156:16, endln:6156:70 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6156:59, endln:6156:70 |vpiParent: @@ -100748,6 +100747,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:6156:45, endln:6156:70 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiLhs: \_parameter: (work@testbench.acache_sets_p), line:6156:16, endln:6156:29 |vpiParamAssign: @@ -100758,7 +100758,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_assoc), line:6157:45, endln:6157:71 |vpiParent: \_param_assign: , line:6157:16, endln:6157:71 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6157:59, endln:6157:71 |vpiParent: @@ -100771,6 +100770,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:6157:45, endln:6157:71 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiLhs: \_parameter: (work@testbench.acache_assoc_p), line:6157:16, endln:6157:30 |vpiParamAssign: @@ -100781,7 +100781,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_block_width), line:6158:45, endln:6158:77 |vpiParent: \_param_assign: , line:6158:16, endln:6158:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6158:59, endln:6158:77 |vpiParent: @@ -100794,6 +100793,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:6158:45, endln:6158:77 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiLhs: \_parameter: (work@testbench.acache_block_width_p), line:6158:16, endln:6158:36 |vpiParamAssign: @@ -100804,7 +100804,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.acache_fill_width), line:6159:45, endln:6159:76 |vpiParent: \_param_assign: , line:6159:16, endln:6159:76 - |vpiName:proc_param_lp.acache_fill_width |vpiActual: \_ref_obj: (proc_param_lp), line:6159:59, endln:6159:76 |vpiParent: @@ -100817,6 +100816,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_fill_width), line:6159:45, endln:6159:76 |vpiName:acache_fill_width + |vpiName:proc_param_lp.acache_fill_width |vpiLhs: \_parameter: (work@testbench.acache_fill_width_p), line:6159:16, endln:6159:35 |vpiParamAssign: @@ -100837,7 +100837,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_assoc), line:6160:48, endln:6160:62 |vpiParent: \_operation: , line:6160:47, endln:6161:130 - |vpiName:proc_param_lp.dcache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6149:59, endln:6149:71 |vpiParent: @@ -100850,6 +100849,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_assoc), line:6160:48, endln:6160:62 |vpiName:dcache_assoc + |vpiName:proc_param_lp.dcache_assoc |vpiOperand: \_operation: , line:6161:55, endln:6161:128 |vpiParent: @@ -100864,7 +100864,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_assoc), line:6161:57, endln:6161:71 |vpiParent: \_operation: , line:6161:56, endln:6161:89 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6153:59, endln:6153:71 |vpiParent: @@ -100877,11 +100876,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:6161:57, endln:6161:71 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiOperand: \_hier_path: (proc_param_lp.acache_assoc), line:6161:74, endln:6161:88 |vpiParent: \_operation: , line:6161:56, endln:6161:89 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6157:59, endln:6157:71 |vpiParent: @@ -100894,11 +100893,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:6161:74, endln:6161:88 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiOperand: \_hier_path: (proc_param_lp.icache_assoc), line:6161:94, endln:6161:108 |vpiParent: \_operation: , line:6161:55, endln:6161:128 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6153:59, endln:6153:71 |vpiParent: @@ -100911,11 +100910,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:6161:94, endln:6161:108 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiOperand: \_hier_path: (proc_param_lp.acache_assoc), line:6161:113, endln:6161:127 |vpiParent: \_operation: , line:6161:55, endln:6161:128 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6157:59, endln:6157:71 |vpiParent: @@ -100928,11 +100927,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:6161:113, endln:6161:127 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiOperand: \_hier_path: (proc_param_lp.dcache_assoc), line:6161:135, endln:6161:149 |vpiParent: \_operation: , line:6160:46, endln:6162:130 - |vpiName:proc_param_lp.dcache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6149:59, endln:6149:71 |vpiParent: @@ -100945,6 +100944,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_assoc), line:6161:135, endln:6161:149 |vpiName:dcache_assoc + |vpiName:proc_param_lp.dcache_assoc |vpiOperand: \_operation: , line:6162:55, endln:6162:128 |vpiParent: @@ -100959,7 +100959,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_assoc), line:6162:57, endln:6162:71 |vpiParent: \_operation: , line:6162:56, endln:6162:89 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6153:59, endln:6153:71 |vpiParent: @@ -100972,11 +100971,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:6162:57, endln:6162:71 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiOperand: \_hier_path: (proc_param_lp.acache_assoc), line:6162:74, endln:6162:88 |vpiParent: \_operation: , line:6162:56, endln:6162:89 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6157:59, endln:6157:71 |vpiParent: @@ -100989,11 +100988,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:6162:74, endln:6162:88 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiOperand: \_hier_path: (proc_param_lp.icache_assoc), line:6162:94, endln:6162:108 |vpiParent: \_operation: , line:6162:55, endln:6162:128 - |vpiName:proc_param_lp.icache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6153:59, endln:6153:71 |vpiParent: @@ -101006,11 +101005,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_assoc), line:6162:94, endln:6162:108 |vpiName:icache_assoc + |vpiName:proc_param_lp.icache_assoc |vpiOperand: \_hier_path: (proc_param_lp.acache_assoc), line:6162:113, endln:6162:127 |vpiParent: \_operation: , line:6162:55, endln:6162:128 - |vpiName:proc_param_lp.acache_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6157:59, endln:6157:71 |vpiParent: @@ -101023,6 +101022,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_assoc), line:6162:113, endln:6162:127 |vpiName:acache_assoc + |vpiName:proc_param_lp.acache_assoc |vpiLhs: \_parameter: (work@testbench.lce_assoc_p), line:6160:16, endln:6160:27 |vpiParamAssign: @@ -101084,7 +101084,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_sets), line:6165:48, endln:6165:61 |vpiParent: \_operation: , line:6165:47, endln:6166:126 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6148:59, endln:6148:70 |vpiParent: @@ -101097,6 +101096,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:6165:48, endln:6165:61 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiOperand: \_operation: , line:6166:55, endln:6166:124 |vpiParent: @@ -101111,7 +101111,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_sets), line:6166:57, endln:6166:70 |vpiParent: \_operation: , line:6166:56, endln:6166:87 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -101124,11 +101123,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6166:57, endln:6166:70 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiOperand: \_hier_path: (proc_param_lp.acache_sets), line:6166:73, endln:6166:86 |vpiParent: \_operation: , line:6166:56, endln:6166:87 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6156:59, endln:6156:70 |vpiParent: @@ -101141,11 +101140,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:6166:73, endln:6166:86 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiOperand: \_hier_path: (proc_param_lp.icache_sets), line:6166:92, endln:6166:105 |vpiParent: \_operation: , line:6166:55, endln:6166:124 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -101158,11 +101157,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6166:92, endln:6166:105 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiOperand: \_hier_path: (proc_param_lp.acache_sets), line:6166:110, endln:6166:123 |vpiParent: \_operation: , line:6166:55, endln:6166:124 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6156:59, endln:6156:70 |vpiParent: @@ -101175,11 +101174,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:6166:110, endln:6166:123 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiOperand: \_hier_path: (proc_param_lp.dcache_sets), line:6166:131, endln:6166:144 |vpiParent: \_operation: , line:6165:46, endln:6167:126 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6148:59, endln:6148:70 |vpiParent: @@ -101192,6 +101191,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:6166:131, endln:6166:144 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiOperand: \_operation: , line:6167:55, endln:6167:124 |vpiParent: @@ -101206,7 +101206,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_sets), line:6167:57, endln:6167:70 |vpiParent: \_operation: , line:6167:56, endln:6167:87 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -101219,11 +101218,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6167:57, endln:6167:70 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiOperand: \_hier_path: (proc_param_lp.acache_sets), line:6167:73, endln:6167:86 |vpiParent: \_operation: , line:6167:56, endln:6167:87 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6156:59, endln:6156:70 |vpiParent: @@ -101236,11 +101235,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:6167:73, endln:6167:86 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiOperand: \_hier_path: (proc_param_lp.icache_sets), line:6167:92, endln:6167:105 |vpiParent: \_operation: , line:6167:55, endln:6167:124 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -101253,11 +101252,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6167:92, endln:6167:105 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiOperand: \_hier_path: (proc_param_lp.acache_sets), line:6167:110, endln:6167:123 |vpiParent: \_operation: , line:6167:55, endln:6167:124 - |vpiName:proc_param_lp.acache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6156:59, endln:6156:70 |vpiParent: @@ -101270,6 +101269,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_sets), line:6167:110, endln:6167:123 |vpiName:acache_sets + |vpiName:proc_param_lp.acache_sets |vpiLhs: \_parameter: (work@testbench.lce_sets_p), line:6165:16, endln:6165:26 |vpiParamAssign: @@ -101331,7 +101331,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_block_width), line:6171:49, endln:6171:69 |vpiParent: \_operation: , line:6171:48, endln:6175:2 - |vpiName:proc_param_lp.dcache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6150:59, endln:6150:77 |vpiParent: @@ -101344,6 +101343,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_block_width), line:6171:49, endln:6171:69 |vpiName:dcache_block_width + |vpiName:proc_param_lp.dcache_block_width |vpiOperand: \_operation: , line:6172:55, endln:6174:77 |vpiParent: @@ -101358,7 +101358,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_block_width), line:6172:57, endln:6172:77 |vpiParent: \_operation: , line:6172:56, endln:6173:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6154:59, endln:6154:77 |vpiParent: @@ -101371,11 +101370,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:6172:57, endln:6172:77 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiOperand: \_hier_path: (proc_param_lp.acache_block_width), line:6173:56, endln:6173:76 |vpiParent: \_operation: , line:6172:56, endln:6173:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6158:59, endln:6158:77 |vpiParent: @@ -101388,11 +101387,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:6173:56, endln:6173:76 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiOperand: \_hier_path: (proc_param_lp.icache_block_width), line:6173:82, endln:6173:102 |vpiParent: \_operation: , line:6172:55, endln:6174:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6154:59, endln:6154:77 |vpiParent: @@ -101405,11 +101404,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:6173:82, endln:6173:102 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiOperand: \_hier_path: (proc_param_lp.acache_block_width), line:6174:56, endln:6174:76 |vpiParent: \_operation: , line:6172:55, endln:6174:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6158:59, endln:6158:77 |vpiParent: @@ -101422,11 +101421,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:6174:56, endln:6174:76 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiOperand: \_hier_path: (proc_param_lp.dcache_block_width), line:6175:7, endln:6175:27 |vpiParent: \_operation: , line:6171:47, endln:6179:2 - |vpiName:proc_param_lp.dcache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6150:59, endln:6150:77 |vpiParent: @@ -101439,6 +101438,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_block_width), line:6175:7, endln:6175:27 |vpiName:dcache_block_width + |vpiName:proc_param_lp.dcache_block_width |vpiOperand: \_operation: , line:6176:55, endln:6178:77 |vpiParent: @@ -101453,7 +101453,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.icache_block_width), line:6176:57, endln:6176:77 |vpiParent: \_operation: , line:6176:56, endln:6177:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6154:59, endln:6154:77 |vpiParent: @@ -101466,11 +101465,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:6176:57, endln:6176:77 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiOperand: \_hier_path: (proc_param_lp.acache_block_width), line:6177:56, endln:6177:76 |vpiParent: \_operation: , line:6176:56, endln:6177:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6158:59, endln:6158:77 |vpiParent: @@ -101483,11 +101482,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:6177:56, endln:6177:76 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiOperand: \_hier_path: (proc_param_lp.icache_block_width), line:6177:82, endln:6177:102 |vpiParent: \_operation: , line:6176:55, endln:6178:77 - |vpiName:proc_param_lp.icache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6154:59, endln:6154:77 |vpiParent: @@ -101500,11 +101499,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_block_width), line:6177:82, endln:6177:102 |vpiName:icache_block_width + |vpiName:proc_param_lp.icache_block_width |vpiOperand: \_hier_path: (proc_param_lp.acache_block_width), line:6178:56, endln:6178:76 |vpiParent: \_operation: , line:6176:55, endln:6178:77 - |vpiName:proc_param_lp.acache_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:6158:59, endln:6158:77 |vpiParent: @@ -101517,6 +101516,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.acache_block_width), line:6178:56, endln:6178:76 |vpiName:acache_block_width + |vpiName:proc_param_lp.acache_block_width |vpiLhs: \_parameter: (work@testbench.cce_block_width_p), line:6171:16, endln:6171:33 |vpiParamAssign: @@ -101527,7 +101527,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_pc_width), line:6183:45, endln:6183:71 |vpiParent: \_param_assign: , line:6183:16, endln:6183:71 - |vpiName:proc_param_lp.cce_pc_width |vpiActual: \_ref_obj: (proc_param_lp), line:6183:59, endln:6183:71 |vpiParent: @@ -101540,6 +101539,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_pc_width), line:6183:45, endln:6183:71 |vpiName:cce_pc_width + |vpiName:proc_param_lp.cce_pc_width |vpiLhs: \_parameter: (work@testbench.cce_pc_width_p), line:6183:16, endln:6183:30 |vpiParamAssign: @@ -101563,7 +101563,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_pc_width), line:6184:48, endln:6184:62 |vpiParent: \_operation: , line:6184:45, endln:6184:62 - |vpiName:proc_param_lp.cce_pc_width |vpiActual: \_ref_obj: (proc_param_lp), line:6183:59, endln:6183:71 |vpiParent: @@ -101576,6 +101575,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_pc_width), line:6184:48, endln:6184:62 |vpiName:cce_pc_width + |vpiName:proc_param_lp.cce_pc_width |vpiLhs: \_parameter: (work@testbench.num_cce_instr_ram_els_p), line:6184:16, endln:6184:39 |vpiParamAssign: @@ -101596,7 +101596,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.dcache_sets), line:6185:48, endln:6185:61 |vpiParent: \_operation: , line:6185:47, endln:6185:78 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6148:59, endln:6148:70 |vpiParent: @@ -101609,11 +101608,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:6185:48, endln:6185:61 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiOperand: \_hier_path: (proc_param_lp.icache_sets), line:6185:64, endln:6185:77 |vpiParent: \_operation: , line:6185:47, endln:6185:78 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -101626,11 +101625,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6185:64, endln:6185:77 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiOperand: \_hier_path: (proc_param_lp.dcache_sets), line:6185:83, endln:6185:96 |vpiParent: \_operation: , line:6185:46, endln:6185:115 - |vpiName:proc_param_lp.dcache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6148:59, endln:6148:70 |vpiParent: @@ -101643,11 +101642,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.dcache_sets), line:6185:83, endln:6185:96 |vpiName:dcache_sets + |vpiName:proc_param_lp.dcache_sets |vpiOperand: \_hier_path: (proc_param_lp.icache_sets), line:6185:101, endln:6185:114 |vpiParent: \_operation: , line:6185:46, endln:6185:115 - |vpiName:proc_param_lp.icache_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6152:59, endln:6152:70 |vpiParent: @@ -101660,6 +101659,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.icache_sets), line:6185:101, endln:6185:114 |vpiName:icache_sets + |vpiName:proc_param_lp.icache_sets |vpiLhs: \_parameter: (work@testbench.cce_way_groups_p), line:6185:16, endln:6185:32 |vpiParamAssign: @@ -101691,7 +101691,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_ucode), line:6187:45, endln:6187:68 |vpiParent: \_param_assign: , line:6187:16, endln:6187:68 - |vpiName:proc_param_lp.cce_ucode |vpiActual: \_ref_obj: (proc_param_lp), line:6187:59, endln:6187:68 |vpiParent: @@ -101704,6 +101703,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_ucode), line:6187:45, endln:6187:68 |vpiName:cce_ucode + |vpiName:proc_param_lp.cce_ucode |vpiLhs: \_parameter: (work@testbench.cce_ucode_p), line:6187:16, endln:6187:27 |vpiParamAssign: @@ -101714,7 +101714,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_en), line:6189:29, endln:6189:48 |vpiParent: \_param_assign: , line:6189:16, endln:6189:48 - |vpiName:proc_param_lp.l2_en |vpiActual: \_ref_obj: (proc_param_lp), line:6189:43, endln:6189:48 |vpiParent: @@ -101727,6 +101726,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_en), line:6189:29, endln:6189:48 |vpiName:l2_en + |vpiName:proc_param_lp.l2_en |vpiLhs: \_parameter: (work@testbench.l2_en_p), line:6189:16, endln:6189:23 |vpiParamAssign: @@ -101737,7 +101737,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_sets), line:6190:29, endln:6190:50 |vpiParent: \_param_assign: , line:6190:16, endln:6190:50 - |vpiName:proc_param_lp.l2_sets |vpiActual: \_ref_obj: (proc_param_lp), line:6190:43, endln:6190:50 |vpiParent: @@ -101750,6 +101749,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_sets), line:6190:29, endln:6190:50 |vpiName:l2_sets + |vpiName:proc_param_lp.l2_sets |vpiLhs: \_parameter: (work@testbench.l2_sets_p), line:6190:16, endln:6190:25 |vpiParamAssign: @@ -101760,7 +101760,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_assoc), line:6191:29, endln:6191:51 |vpiParent: \_param_assign: , line:6191:16, endln:6191:51 - |vpiName:proc_param_lp.l2_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:6191:43, endln:6191:51 |vpiParent: @@ -101773,6 +101772,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_assoc), line:6191:29, endln:6191:51 |vpiName:l2_assoc + |vpiName:proc_param_lp.l2_assoc |vpiLhs: \_parameter: (work@testbench.l2_assoc_p), line:6191:16, endln:6191:26 |vpiParamAssign: @@ -101783,7 +101783,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:6192:40, endln:6192:73 |vpiParent: \_param_assign: , line:6192:16, endln:6192:73 - |vpiName:proc_param_lp.l2_outstanding_reqs |vpiActual: \_ref_obj: (proc_param_lp), line:6192:54, endln:6192:73 |vpiParent: @@ -101796,6 +101795,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.l2_outstanding_reqs), line:6192:40, endln:6192:73 |vpiName:l2_outstanding_reqs + |vpiName:proc_param_lp.l2_outstanding_reqs |vpiLhs: \_parameter: (work@testbench.l2_outstanding_reqs_p), line:6192:16, endln:6192:37 |vpiParamAssign: @@ -101806,7 +101806,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:6194:38, endln:6194:69 |vpiParent: \_param_assign: , line:6194:16, endln:6194:69 - |vpiName:proc_param_lp.fe_queue_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:6194:52, endln:6194:69 |vpiParent: @@ -101819,6 +101818,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:6194:38, endln:6194:69 |vpiName:fe_queue_fifo_els + |vpiName:proc_param_lp.fe_queue_fifo_els |vpiLhs: \_parameter: (work@testbench.fe_queue_fifo_els_p), line:6194:16, endln:6194:35 |vpiParamAssign: @@ -101829,7 +101829,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:6195:38, endln:6195:67 |vpiParent: \_param_assign: , line:6195:16, endln:6195:67 - |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:6195:52, endln:6195:67 |vpiParent: @@ -101842,6 +101841,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:6195:38, endln:6195:67 |vpiName:fe_cmd_fifo_els + |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiLhs: \_parameter: (work@testbench.fe_cmd_fifo_els_p), line:6195:16, endln:6195:33 |vpiParamAssign: @@ -101852,7 +101852,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_coh_clk), line:6197:41, endln:6197:68 |vpiParent: \_param_assign: , line:6197:16, endln:6197:68 - |vpiName:proc_param_lp.async_coh_clk |vpiActual: \_ref_obj: (proc_param_lp), line:6197:55, endln:6197:68 |vpiParent: @@ -101865,6 +101864,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_coh_clk), line:6197:41, endln:6197:68 |vpiName:async_coh_clk + |vpiName:proc_param_lp.async_coh_clk |vpiLhs: \_parameter: (work@testbench.async_coh_clk_p), line:6197:16, endln:6197:31 |vpiParamAssign: @@ -101875,7 +101875,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_max_credits), line:6198:41, endln:6198:74 |vpiParent: \_param_assign: , line:6198:16, endln:6198:74 - |vpiName:proc_param_lp.coh_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:6198:55, endln:6198:74 |vpiParent: @@ -101888,6 +101887,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_max_credits), line:6198:41, endln:6198:74 |vpiName:coh_noc_max_credits + |vpiName:proc_param_lp.coh_noc_max_credits |vpiLhs: \_parameter: (work@testbench.coh_noc_max_credits_p), line:6198:16, endln:6198:37 |vpiParamAssign: @@ -101898,7 +101898,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_flit_width), line:6199:41, endln:6199:73 |vpiParent: \_param_assign: , line:6199:16, endln:6199:73 - |vpiName:proc_param_lp.coh_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:6199:55, endln:6199:73 |vpiParent: @@ -101911,6 +101910,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:6199:41, endln:6199:73 |vpiName:coh_noc_flit_width + |vpiName:proc_param_lp.coh_noc_flit_width |vpiLhs: \_parameter: (work@testbench.coh_noc_flit_width_p), line:6199:16, endln:6199:36 |vpiParamAssign: @@ -101921,7 +101921,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_cid_width), line:6200:41, endln:6200:72 |vpiParent: \_param_assign: , line:6200:16, endln:6200:72 - |vpiName:proc_param_lp.coh_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6200:55, endln:6200:72 |vpiParent: @@ -101934,6 +101933,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:6200:41, endln:6200:72 |vpiName:coh_noc_cid_width + |vpiName:proc_param_lp.coh_noc_cid_width |vpiLhs: \_parameter: (work@testbench.coh_noc_cid_width_p), line:6200:16, endln:6200:35 |vpiParamAssign: @@ -101944,7 +101944,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.coh_noc_len_width), line:6201:41, endln:6201:72 |vpiParent: \_param_assign: , line:6201:16, endln:6201:72 - |vpiName:proc_param_lp.coh_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:6201:55, endln:6201:72 |vpiParent: @@ -101957,6 +101956,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_len_width), line:6201:41, endln:6201:72 |vpiName:coh_noc_len_width + |vpiName:proc_param_lp.coh_noc_len_width |vpiLhs: \_parameter: (work@testbench.coh_noc_len_width_p), line:6201:16, endln:6201:35 |vpiParamAssign: @@ -101992,7 +101992,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6202:45, endln:6202:55 |vpiParent: \_operation: , line:6202:45, endln:6202:66 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -102005,11 +102004,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6202:45, endln:6202:55 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:56, endln:6202:66 |vpiParent: \_operation: , line:6202:45, endln:6202:66 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -102022,11 +102021,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:56, endln:6202:66 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:67, endln:6202:77 |vpiParent: \_operation: , line:6202:45, endln:6202:77 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -102039,6 +102038,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:67, endln:6202:77 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6202:78, endln:6202:79 |vpiParent: @@ -102086,7 +102086,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6202:99, endln:6202:109 |vpiParent: \_operation: , line:6202:99, endln:6202:120 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -102099,11 +102098,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6202:99, endln:6202:109 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:110, endln:6202:120 |vpiParent: \_operation: , line:6202:99, endln:6202:120 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -102116,11 +102115,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:110, endln:6202:120 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:121, endln:6202:131 |vpiParent: \_operation: , line:6202:99, endln:6202:131 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -102133,6 +102132,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:121, endln:6202:131 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6202:132, endln:6202:133 |vpiParent: @@ -102177,7 +102177,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6203:45, endln:6203:56 |vpiParent: \_operation: , line:6203:45, endln:6203:67 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -102190,11 +102189,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6203:45, endln:6203:56 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:57, endln:6203:67 |vpiParent: \_operation: , line:6203:45, endln:6203:67 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -102207,11 +102206,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:57, endln:6203:67 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:68, endln:6203:79 |vpiParent: \_operation: , line:6203:45, endln:6203:79 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -102224,6 +102223,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:68, endln:6203:79 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_constant: , line:6203:80, endln:6203:81 |vpiParent: @@ -102271,7 +102271,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6203:101, endln:6203:112 |vpiParent: \_operation: , line:6203:101, endln:6203:123 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -102284,11 +102283,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6203:101, endln:6203:112 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:113, endln:6203:123 |vpiParent: \_operation: , line:6203:101, endln:6203:123 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -102301,11 +102300,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:113, endln:6203:123 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:124, endln:6203:135 |vpiParent: \_operation: , line:6203:101, endln:6203:135 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -102318,6 +102317,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:124, endln:6203:135 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_constant: , line:6203:136, endln:6203:137 |vpiParent: @@ -102433,7 +102433,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6203:45, endln:6203:56 |vpiParent: \_operation: , line:6203:45, endln:6203:67 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -102446,11 +102445,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6203:45, endln:6203:56 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:57, endln:6203:67 |vpiParent: \_operation: , line:6203:45, endln:6203:67 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -102463,11 +102462,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:57, endln:6203:67 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:68, endln:6203:79 |vpiParent: \_operation: , line:6203:45, endln:6203:79 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -102480,6 +102479,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:68, endln:6203:79 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_constant: , line:6203:80, endln:6203:81 |vpiParent: @@ -102527,7 +102527,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6203:101, endln:6203:112 |vpiParent: \_operation: , line:6203:101, endln:6203:123 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -102540,11 +102539,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6203:101, endln:6203:112 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:113, endln:6203:123 |vpiParent: \_operation: , line:6203:101, endln:6203:123 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -102557,11 +102556,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:113, endln:6203:123 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:124, endln:6203:135 |vpiParent: \_operation: , line:6203:101, endln:6203:135 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -102574,6 +102573,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:124, endln:6203:135 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_constant: , line:6203:136, endln:6203:137 |vpiParent: @@ -102617,7 +102617,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6202:45, endln:6202:55 |vpiParent: \_operation: , line:6202:45, endln:6202:66 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -102630,11 +102629,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6202:45, endln:6202:55 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:56, endln:6202:66 |vpiParent: \_operation: , line:6202:45, endln:6202:66 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -102647,11 +102646,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:56, endln:6202:66 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:67, endln:6202:77 |vpiParent: \_operation: , line:6202:45, endln:6202:77 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -102664,6 +102663,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:67, endln:6202:77 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6202:78, endln:6202:79 |vpiParent: @@ -102711,7 +102711,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6202:99, endln:6202:109 |vpiParent: \_operation: , line:6202:99, endln:6202:120 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -102724,11 +102723,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6202:99, endln:6202:109 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:110, endln:6202:120 |vpiParent: \_operation: , line:6202:99, endln:6202:120 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -102741,11 +102740,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6202:110, endln:6202:120 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:121, endln:6202:131 |vpiParent: \_operation: , line:6202:99, endln:6202:131 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -102758,6 +102757,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6202:121, endln:6202:131 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6202:132, endln:6202:133 |vpiParent: @@ -102796,7 +102796,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6203:45, endln:6203:56 |vpiParent: \_operation: , line:6203:45, endln:6203:67 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -102809,11 +102808,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6203:45, endln:6203:56 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:57, endln:6203:67 |vpiParent: \_operation: , line:6203:45, endln:6203:67 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -102826,11 +102825,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:57, endln:6203:67 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:68, endln:6203:79 |vpiParent: \_operation: , line:6203:45, endln:6203:79 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -102843,6 +102842,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:68, endln:6203:79 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_constant: , line:6203:80, endln:6203:81 |vpiParent: @@ -102890,7 +102890,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.sac_x_dim), line:6203:101, endln:6203:112 |vpiParent: \_operation: , line:6203:101, endln:6203:123 - |vpiName:proc_param_lp.sac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6107:44, endln:6107:53 |vpiParent: @@ -102903,11 +102902,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.sac_x_dim), line:6203:101, endln:6203:112 |vpiName:sac_x_dim + |vpiName:proc_param_lp.sac_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:113, endln:6203:123 |vpiParent: \_operation: , line:6203:101, endln:6203:123 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6098:44, endln:6098:52 |vpiParent: @@ -102920,11 +102919,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:6203:113, endln:6203:123 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiOperand: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:124, endln:6203:135 |vpiParent: \_operation: , line:6203:101, endln:6203:135 - |vpiName:proc_param_lp.cac_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6105:44, endln:6105:53 |vpiParent: @@ -102937,6 +102936,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cac_x_dim), line:6203:124, endln:6203:135 |vpiName:cac_x_dim + |vpiName:proc_param_lp.cac_x_dim |vpiOperand: \_constant: , line:6203:136, endln:6203:137 |vpiParent: @@ -102971,7 +102971,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_mem_clk), line:6212:44, endln:6212:71 |vpiParent: \_param_assign: , line:6212:16, endln:6212:71 - |vpiName:proc_param_lp.async_mem_clk |vpiActual: \_ref_obj: (proc_param_lp), line:6212:58, endln:6212:71 |vpiParent: @@ -102984,6 +102983,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_mem_clk), line:6212:44, endln:6212:71 |vpiName:async_mem_clk + |vpiName:proc_param_lp.async_mem_clk |vpiLhs: \_parameter: (work@testbench.async_mem_clk_p), line:6212:16, endln:6212:31 |vpiParamAssign: @@ -102994,7 +102994,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_max_credits), line:6213:44, endln:6213:77 |vpiParent: \_param_assign: , line:6213:16, endln:6213:77 - |vpiName:proc_param_lp.mem_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:6213:58, endln:6213:77 |vpiParent: @@ -103007,6 +103006,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:6213:44, endln:6213:77 |vpiName:mem_noc_max_credits + |vpiName:proc_param_lp.mem_noc_max_credits |vpiLhs: \_parameter: (work@testbench.mem_noc_max_credits_p), line:6213:16, endln:6213:37 |vpiParamAssign: @@ -103017,7 +103017,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_flit_width), line:6214:44, endln:6214:76 |vpiParent: \_param_assign: , line:6214:16, endln:6214:76 - |vpiName:proc_param_lp.mem_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:6214:58, endln:6214:76 |vpiParent: @@ -103030,6 +103029,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:6214:44, endln:6214:76 |vpiName:mem_noc_flit_width + |vpiName:proc_param_lp.mem_noc_flit_width |vpiLhs: \_parameter: (work@testbench.mem_noc_flit_width_p), line:6214:16, endln:6214:36 |vpiParamAssign: @@ -103040,7 +103040,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_cid_width), line:6215:44, endln:6215:75 |vpiParent: \_param_assign: , line:6215:16, endln:6215:75 - |vpiName:proc_param_lp.mem_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6215:58, endln:6215:75 |vpiParent: @@ -103053,6 +103052,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:6215:44, endln:6215:75 |vpiName:mem_noc_cid_width + |vpiName:proc_param_lp.mem_noc_cid_width |vpiLhs: \_parameter: (work@testbench.mem_noc_cid_width_p), line:6215:16, endln:6215:35 |vpiParamAssign: @@ -103063,7 +103063,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.mem_noc_len_width), line:6216:44, endln:6216:75 |vpiParent: \_param_assign: , line:6216:16, endln:6216:75 - |vpiName:proc_param_lp.mem_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:6216:58, endln:6216:75 |vpiParent: @@ -103076,6 +103075,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_len_width), line:6216:44, endln:6216:75 |vpiName:mem_noc_len_width + |vpiName:proc_param_lp.mem_noc_len_width |vpiLhs: \_parameter: (work@testbench.mem_noc_len_width_p), line:6216:16, endln:6216:35 |vpiParamAssign: @@ -103111,7 +103111,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6217:48, endln:6217:58 |vpiParent: \_operation: , line:6217:48, endln:6217:69 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -103124,11 +103123,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6217:48, endln:6217:58 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:59, endln:6217:69 |vpiParent: \_operation: , line:6217:48, endln:6217:69 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -103141,11 +103140,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:59, endln:6217:69 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:70, endln:6217:80 |vpiParent: \_operation: , line:6217:48, endln:6217:80 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -103158,6 +103157,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:70, endln:6217:80 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6217:81, endln:6217:82 |vpiParent: @@ -103205,7 +103205,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6217:102, endln:6217:112 |vpiParent: \_operation: , line:6217:102, endln:6217:123 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -103218,11 +103217,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6217:102, endln:6217:112 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:113, endln:6217:123 |vpiParent: \_operation: , line:6217:102, endln:6217:123 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -103235,11 +103234,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:113, endln:6217:123 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:124, endln:6217:134 |vpiParent: \_operation: , line:6217:102, endln:6217:134 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -103252,6 +103251,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:124, endln:6217:134 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6217:135, endln:6217:136 |vpiParent: @@ -103409,7 +103409,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6217:48, endln:6217:58 |vpiParent: \_operation: , line:6217:48, endln:6217:69 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -103422,11 +103421,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6217:48, endln:6217:58 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:59, endln:6217:69 |vpiParent: \_operation: , line:6217:48, endln:6217:69 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -103439,11 +103438,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:59, endln:6217:69 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:70, endln:6217:80 |vpiParent: \_operation: , line:6217:48, endln:6217:80 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -103456,6 +103455,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:70, endln:6217:80 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6217:81, endln:6217:82 |vpiParent: @@ -103503,7 +103503,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6217:102, endln:6217:112 |vpiParent: \_operation: , line:6217:102, endln:6217:123 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -103516,11 +103515,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6217:102, endln:6217:112 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:113, endln:6217:123 |vpiParent: \_operation: , line:6217:102, endln:6217:123 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -103533,11 +103532,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:113, endln:6217:123 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:124, endln:6217:134 |vpiParent: \_operation: , line:6217:102, endln:6217:134 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -103550,6 +103549,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:124, endln:6217:134 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6217:135, endln:6217:136 |vpiParent: @@ -103601,7 +103601,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6217:48, endln:6217:58 |vpiParent: \_operation: , line:6217:48, endln:6217:69 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -103614,11 +103613,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6217:48, endln:6217:58 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:59, endln:6217:69 |vpiParent: \_operation: , line:6217:48, endln:6217:69 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -103631,11 +103630,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:59, endln:6217:69 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:70, endln:6217:80 |vpiParent: \_operation: , line:6217:48, endln:6217:80 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -103648,6 +103647,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:70, endln:6217:80 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6217:81, endln:6217:82 |vpiParent: @@ -103695,7 +103695,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.ic_y_dim), line:6217:102, endln:6217:112 |vpiParent: \_operation: , line:6217:102, endln:6217:123 - |vpiName:proc_param_lp.ic_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6102:43, endln:6102:51 |vpiParent: @@ -103708,11 +103707,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.ic_y_dim), line:6217:102, endln:6217:112 |vpiName:ic_y_dim + |vpiName:proc_param_lp.ic_y_dim |vpiOperand: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:113, endln:6217:123 |vpiParent: \_operation: , line:6217:102, endln:6217:123 - |vpiName:proc_param_lp.cc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6099:44, endln:6099:52 |vpiParent: @@ -103725,11 +103724,11 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cc_y_dim), line:6217:113, endln:6217:123 |vpiName:cc_y_dim + |vpiName:proc_param_lp.cc_y_dim |vpiOperand: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:124, endln:6217:134 |vpiParent: \_operation: , line:6217:102, endln:6217:134 - |vpiName:proc_param_lp.mc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:6104:43, endln:6104:51 |vpiParent: @@ -103742,6 +103741,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.mc_y_dim), line:6217:124, endln:6217:134 |vpiName:mc_y_dim + |vpiName:proc_param_lp.mc_y_dim |vpiOperand: \_constant: , line:6217:135, endln:6217:136 |vpiParent: @@ -103769,7 +103769,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.async_io_clk), line:6228:43, endln:6228:69 |vpiParent: \_param_assign: , line:6228:16, endln:6228:69 - |vpiName:proc_param_lp.async_io_clk |vpiActual: \_ref_obj: (proc_param_lp), line:6228:57, endln:6228:69 |vpiParent: @@ -103782,6 +103781,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.async_io_clk), line:6228:43, endln:6228:69 |vpiName:async_io_clk + |vpiName:proc_param_lp.async_io_clk |vpiLhs: \_parameter: (work@testbench.async_io_clk_p), line:6228:16, endln:6228:30 |vpiParamAssign: @@ -103792,7 +103792,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_max_credits), line:6229:43, endln:6229:75 |vpiParent: \_param_assign: , line:6229:16, endln:6229:75 - |vpiName:proc_param_lp.io_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:6229:57, endln:6229:75 |vpiParent: @@ -103805,6 +103804,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_max_credits), line:6229:43, endln:6229:75 |vpiName:io_noc_max_credits + |vpiName:proc_param_lp.io_noc_max_credits |vpiLhs: \_parameter: (work@testbench.io_noc_max_credits_p), line:6229:16, endln:6229:36 |vpiParamAssign: @@ -103815,7 +103815,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiParent: \_param_assign: , line:6230:16, endln:6230:73 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:6230:57, endln:6230:73 |vpiParent: @@ -103828,6 +103827,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiLhs: \_parameter: (work@testbench.io_noc_did_width_p), line:6230:16, endln:6230:34 |vpiParamAssign: @@ -103838,7 +103838,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_flit_width), line:6231:43, endln:6231:74 |vpiParent: \_param_assign: , line:6231:16, endln:6231:74 - |vpiName:proc_param_lp.io_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:6231:57, endln:6231:74 |vpiParent: @@ -103851,6 +103850,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_flit_width), line:6231:43, endln:6231:74 |vpiName:io_noc_flit_width + |vpiName:proc_param_lp.io_noc_flit_width |vpiLhs: \_parameter: (work@testbench.io_noc_flit_width_p), line:6231:16, endln:6231:35 |vpiParamAssign: @@ -103861,7 +103861,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_cid_width), line:6232:43, endln:6232:73 |vpiParent: \_param_assign: , line:6232:16, endln:6232:73 - |vpiName:proc_param_lp.io_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6232:57, endln:6232:73 |vpiParent: @@ -103874,6 +103873,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_cid_width), line:6232:43, endln:6232:73 |vpiName:io_noc_cid_width + |vpiName:proc_param_lp.io_noc_cid_width |vpiLhs: \_parameter: (work@testbench.io_noc_cid_width_p), line:6232:16, endln:6232:34 |vpiParamAssign: @@ -103884,7 +103884,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_len_width), line:6233:43, endln:6233:73 |vpiParent: \_param_assign: , line:6233:16, endln:6233:73 - |vpiName:proc_param_lp.io_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:6233:57, endln:6233:73 |vpiParent: @@ -103897,6 +103896,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_len_width), line:6233:43, endln:6233:73 |vpiName:io_noc_len_width + |vpiName:proc_param_lp.io_noc_len_width |vpiLhs: \_parameter: (work@testbench.io_noc_len_width_p), line:6233:16, endln:6233:34 |vpiParamAssign: @@ -103928,7 +103928,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_did_width), line:6235:43, endln:6235:61 |vpiParent: \_param_assign: , line:6230:16, endln:6230:73 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:6230:57, endln:6230:73 |vpiParent: @@ -103941,6 +103940,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:6235:43, endln:6235:61 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiLhs: \_parameter: (work@testbench.io_noc_x_cord_width_p), line:6235:16, endln:6235:37 |vpiParamAssign: @@ -104043,7 +104043,6 @@ design: (work@testbench) |vpiParent: \_operation: , line:6242:9, endln:6242:81 |vpiSize:32 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:6230:57, endln:6230:73 |vpiParent: @@ -104056,6 +104055,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiOperand: \_operation: , line:6242:11, endln:6242:54 |vpiParent: @@ -104073,7 +104073,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiParent: \_operation: , line:6242:11, endln:6242:54 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:6230:57, endln:6230:73 |vpiParent: @@ -104086,6 +104085,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiLhs: \_parameter: (work@testbench.io_noc_cord_markers_pos_p), line:6240:20, endln:6240:45 |vpiParamAssign: @@ -104096,7 +104096,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiParent: \_param_assign: , line:6230:16, endln:6230:73 - |vpiName:proc_param_lp.io_noc_did_width |vpiActual: \_ref_obj: (proc_param_lp), line:6230:57, endln:6230:73 |vpiParent: @@ -104109,6 +104108,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.io_noc_did_width), line:6230:43, endln:6230:73 |vpiName:io_noc_did_width + |vpiName:proc_param_lp.io_noc_did_width |vpiLhs: \_parameter: (work@testbench.io_noc_cord_width_p), line:6243:16, endln:6243:35 |vpiParamAssign: @@ -104250,7 +104250,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6252:32, endln:6252:57 |vpiParent: \_operation: , line:6252:32, endln:6252:79 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6252:46, endln:6252:57 |vpiParent: @@ -104263,6 +104262,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6252:32, endln:6252:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_constant: , line:6252:60, endln:6252:79 |vpiParent: @@ -104286,7 +104286,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6253:32, endln:6253:57 |vpiParent: \_operation: , line:6253:32, endln:6253:79 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6253:46, endln:6253:57 |vpiParent: @@ -104299,6 +104298,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6253:32, endln:6253:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6253:60, endln:6253:79 |vpiParent: @@ -104363,7 +104363,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6260:4, endln:6260:17 |vpiParent: \_operation: , line:6260:4, endln:6260:33 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -104376,6 +104375,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6260:4, endln:6260:17 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_constant: , line:6260:20, endln:6260:33 |vpiParent: @@ -104388,7 +104388,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6260:36, endln:6260:63 |vpiParent: \_operation: , line:6260:4, endln:6260:63 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -104401,6 +104400,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6260:36, endln:6260:63 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_operation: , line:6263:4, endln:6263:49 |vpiParent: @@ -104410,7 +104410,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6263:4, endln:6263:17 |vpiParent: \_operation: , line:6263:4, endln:6263:49 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -104423,6 +104422,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6263:4, endln:6263:17 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_constant: , line:6263:20, endln:6263:49 |vpiParent: @@ -104445,7 +104445,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6266:4, endln:6266:17 |vpiParent: \_operation: , line:6266:4, endln:6266:33 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -104458,6 +104457,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6266:4, endln:6266:17 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_constant: , line:6266:20, endln:6266:33 |vpiParent: @@ -104470,7 +104470,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6266:36, endln:6266:63 |vpiParent: \_operation: , line:6266:4, endln:6266:63 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -104483,6 +104482,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6266:36, endln:6266:63 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_operation: , line:6269:4, endln:6269:49 |vpiParent: @@ -104492,7 +104492,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6269:4, endln:6269:17 |vpiParent: \_operation: , line:6269:4, endln:6269:49 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -104505,6 +104504,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6269:4, endln:6269:17 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_constant: , line:6269:20, endln:6269:49 |vpiParent: @@ -104533,7 +104533,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.vaddr_width), line:6278:4, endln:6278:17 |vpiParent: \_operation: , line:6278:4, endln:6279:42 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6125:46, endln:6125:57 |vpiParent: @@ -104546,6 +104545,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:6278:4, endln:6278:17 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_constant: , line:6279:6, endln:6279:42 |vpiParent: @@ -104604,7 +104604,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6283:6, endln:6283:33 |vpiParent: \_operation: , line:6282:4, endln:6283:33 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -104617,6 +104616,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6283:6, endln:6283:33 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_constant: , line:6283:36, endln:6283:71 |vpiParent: @@ -104660,7 +104660,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6286:6, endln:6286:33 |vpiParent: \_operation: , line:6286:4, endln:6286:33 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -104673,6 +104672,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6286:6, endln:6286:33 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_operation: , line:6288:29, endln:6304:36 |vpiParent: @@ -104697,7 +104697,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6290:4, endln:6290:17 |vpiParent: \_operation: , line:6290:4, endln:6290:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -104710,6 +104709,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6290:4, endln:6290:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6290:20, endln:6290:43 |vpiParent: @@ -104735,7 +104735,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6294:4, endln:6294:16 |vpiParent: \_operation: , line:6294:4, endln:6294:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -104748,6 +104747,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6294:4, endln:6294:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6294:19, endln:6294:20 |vpiParent: @@ -104770,7 +104770,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6298:4, endln:6298:17 |vpiParent: \_operation: , line:6298:4, endln:6298:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -104783,6 +104782,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6298:4, endln:6298:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6298:20, endln:6298:43 |vpiParent: @@ -104808,7 +104808,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6302:4, endln:6302:16 |vpiParent: \_operation: , line:6302:4, endln:6302:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -104821,6 +104820,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6302:4, endln:6302:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6302:19, endln:6302:20 |vpiParent: @@ -104846,7 +104846,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6307:6, endln:6307:33 |vpiParent: \_operation: , line:6307:4, endln:6307:33 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -104859,6 +104858,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6307:6, endln:6307:33 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_operation: , line:6309:31, endln:6325:36 |vpiParent: @@ -104883,7 +104883,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6311:4, endln:6311:17 |vpiParent: \_operation: , line:6311:4, endln:6311:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -104896,6 +104895,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6311:4, endln:6311:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6311:20, endln:6311:43 |vpiParent: @@ -104921,7 +104921,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6315:4, endln:6315:16 |vpiParent: \_operation: , line:6315:4, endln:6315:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -104934,6 +104933,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6315:4, endln:6315:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6315:19, endln:6315:20 |vpiParent: @@ -104956,7 +104956,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6319:4, endln:6319:17 |vpiParent: \_operation: , line:6319:4, endln:6319:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -104969,6 +104968,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6319:4, endln:6319:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6319:20, endln:6319:43 |vpiParent: @@ -104994,7 +104994,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6323:4, endln:6323:16 |vpiParent: \_operation: , line:6323:4, endln:6323:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -105007,6 +105006,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6323:4, endln:6323:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6323:19, endln:6323:20 |vpiParent: @@ -105042,7 +105042,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6331:6, endln:6331:33 |vpiParent: \_operation: , line:6330:4, endln:6331:33 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -105055,6 +105054,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6331:6, endln:6331:33 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_constant: , line:6331:36, endln:6331:71 |vpiParent: @@ -105098,7 +105098,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6334:6, endln:6334:33 |vpiParent: \_operation: , line:6334:4, endln:6334:33 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -105111,6 +105110,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6334:6, endln:6334:33 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_operation: , line:6336:29, endln:6352:36 |vpiParent: @@ -105135,7 +105135,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6338:4, endln:6338:17 |vpiParent: \_operation: , line:6338:4, endln:6338:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -105148,6 +105147,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6338:4, endln:6338:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6338:20, endln:6338:43 |vpiParent: @@ -105173,7 +105173,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6342:4, endln:6342:16 |vpiParent: \_operation: , line:6342:4, endln:6342:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -105186,6 +105185,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6342:4, endln:6342:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6342:19, endln:6342:20 |vpiParent: @@ -105208,7 +105208,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6346:4, endln:6346:17 |vpiParent: \_operation: , line:6346:4, endln:6346:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -105221,6 +105220,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6346:4, endln:6346:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6346:20, endln:6346:43 |vpiParent: @@ -105246,7 +105246,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6350:4, endln:6350:16 |vpiParent: \_operation: , line:6350:4, endln:6350:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -105259,6 +105258,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6350:4, endln:6350:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6350:19, endln:6350:20 |vpiParent: @@ -105284,7 +105284,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6355:6, endln:6355:33 |vpiParent: \_operation: , line:6355:4, endln:6355:33 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:6132:60, endln:6132:85 |vpiParent: @@ -105297,6 +105296,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:6355:6, endln:6355:33 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiOperand: \_operation: , line:6357:31, endln:6373:36 |vpiParent: @@ -105321,7 +105321,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6359:4, endln:6359:17 |vpiParent: \_operation: , line:6359:4, endln:6359:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -105334,6 +105333,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6359:4, endln:6359:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6359:20, endln:6359:43 |vpiParent: @@ -105359,7 +105359,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6363:4, endln:6363:16 |vpiParent: \_operation: , line:6363:4, endln:6363:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -105372,6 +105371,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6363:4, endln:6363:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6363:19, endln:6363:20 |vpiParent: @@ -105394,7 +105394,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6367:4, endln:6367:17 |vpiParent: \_operation: , line:6367:4, endln:6367:43 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -105407,6 +105406,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6367:4, endln:6367:17 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_constant: , line:6367:20, endln:6367:43 |vpiParent: @@ -105432,7 +105432,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.asid_width), line:6371:4, endln:6371:16 |vpiParent: \_operation: , line:6371:4, endln:6371:20 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:6127:46, endln:6127:56 |vpiParent: @@ -105445,6 +105444,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:6371:4, endln:6371:16 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiOperand: \_constant: , line:6371:19, endln:6371:20 |vpiParent: @@ -105565,7 +105565,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6392:28, endln:6392:41 |vpiParent: \_operation: , line:6392:4, endln:6392:41 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -105578,6 +105577,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6392:28, endln:6392:41 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_sys_func_call: ($bits), line:6392:42, endln:6392:70 |vpiParent: @@ -105636,7 +105636,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.paddr_width), line:6398:28, endln:6398:41 |vpiParent: \_operation: , line:6398:4, endln:6398:41 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:6126:46, endln:6126:57 |vpiParent: @@ -105649,6 +105648,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:6398:28, endln:6398:41 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_sys_func_call: ($bits), line:6398:42, endln:6398:70 |vpiParent: diff --git a/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log b/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log index 8c52dd7d50..8a8cf2fa33 100644 --- a/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log +++ b/tests/BlackParrotMuteErrors/BlackParrotMuteErrors.log @@ -6608,8 +6608,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 77 -assign_stmt 5 -assignment 6 +assignment 11 begin 4 bit_select 24 class_defn 8 @@ -6662,8 +6661,7 @@ unsupported_typespec 378 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === array_typespec 77 -assign_stmt 7 -assignment 12 +assignment 19 begin 8 bit_select 28 class_defn 8 @@ -6843,13 +6841,13 @@ design: (work@otp_ctrl) \_begin: (prim_util_pkg::_clog2), line:7:5, endln:7:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:8:5, endln:8:8 |vpiRhs: \_constant: , line:8:19, endln:8:20 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -6857,7 +6855,7 @@ design: (work@otp_ctrl) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:8:10, endln:8:16 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -39444,13 +39442,13 @@ design: (work@otp_ctrl) \_begin: (prim_util_pkg::_clog2), line:7:5, endln:7:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:8:5, endln:8:8 |vpiRhs: \_constant: , line:8:19, endln:8:20 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -39458,7 +39456,7 @@ design: (work@otp_ctrl) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:8:10, endln:8:16 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -91288,7 +91286,7 @@ design: (work@otp_ctrl) |vpiParent: \_module_inst: work@otp_ctrl (work@otp_ctrl), file:${SURELOG_DIR}/tests/BlackParrotMuteErrors/dut.sv, line:877:1, endln:893:10 |vpiForInitStmt: - \_assign_stmt: , line:882:6, endln:882:18 + \_assignment: , line:882:6, endln:882:18 |vpiParent: \_gen_for: |vpiRhs: @@ -91300,7 +91298,7 @@ design: (work@otp_ctrl) |vpiLhs: \_int_var: (work@otp_ctrl.k), line:882:13, endln:882:14 |vpiParent: - \_assign_stmt: , line:882:6, endln:882:18 + \_assignment: , line:882:6, endln:882:18 |vpiTypespec: \_ref_typespec: (work@otp_ctrl.k) |vpiParent: @@ -91370,7 +91368,6 @@ design: (work@otp_ctrl) \_hier_path: (PartInfo[k].variant), line:884:5, endln:884:13 |vpiParent: \_operation: , line:884:5, endln:884:36 - |vpiName:PartInfo[k].variant |vpiActual: \_bit_select: (PartInfo[k]), line:884:5, endln:884:13 |vpiParent: @@ -91389,6 +91386,7 @@ design: (work@otp_ctrl) \_hier_path: (PartInfo[k].variant), line:884:5, endln:884:13 |vpiName:variant |vpiFullName:work@otp_ctrl.gen_partitions.variant + |vpiName:PartInfo[k].variant |vpiOperand: \_ref_obj: (work@otp_ctrl.gen_partitions.Buffered), line:884:28, endln:884:36 |vpiParent: @@ -104481,7 +104479,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -104492,11 +104489,11 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiName:offset + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -104507,6 +104504,7 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiName:size + |vpiName:Info.size |vpiOperand: \_operation: , line:786:59, endln:786:77 |vpiParent: @@ -125972,7 +125970,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -125987,11 +125984,11 @@ design: (work@otp_ctrl) |vpiName:offset |vpiActual: \_typespec_member: (offset), line:558:34, endln:558:40 + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -126006,6 +126003,7 @@ design: (work@otp_ctrl) |vpiName:size |vpiActual: \_typespec_member: (size), line:559:34, endln:559:38 + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 |vpiParent: @@ -134473,7 +134471,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -134488,11 +134485,11 @@ design: (work@otp_ctrl) |vpiName:offset |vpiActual: \_typespec_member: (offset), line:558:34, endln:558:40 + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -134507,6 +134504,7 @@ design: (work@otp_ctrl) |vpiName:size |vpiActual: \_typespec_member: (size), line:559:34, endln:559:38 + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 |vpiParent: @@ -142974,7 +142972,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -142989,11 +142986,11 @@ design: (work@otp_ctrl) |vpiName:offset |vpiActual: \_typespec_member: (offset), line:558:34, endln:558:40 + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -143008,6 +143005,7 @@ design: (work@otp_ctrl) |vpiName:size |vpiActual: \_typespec_member: (size), line:559:34, endln:559:38 + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 |vpiParent: @@ -151475,7 +151473,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -151490,11 +151487,11 @@ design: (work@otp_ctrl) |vpiName:offset |vpiActual: \_typespec_member: (offset), line:558:34, endln:558:40 + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -151509,6 +151506,7 @@ design: (work@otp_ctrl) |vpiName:size |vpiActual: \_typespec_member: (size), line:559:34, endln:559:38 + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 |vpiParent: @@ -157570,7 +157568,7 @@ design: (work@otp_ctrl) \_begin: (prim_util_pkg::_clog2), line:7:5, endln:7:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:8:5, endln:8:8 |vpiRhs: @@ -157578,7 +157576,7 @@ design: (work@otp_ctrl) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:8:10, endln:8:16 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: @@ -157843,7 +157841,7 @@ design: (work@otp_ctrl) \_begin: (prim_util_pkg::_clog2), line:7:5, endln:7:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:8:5, endln:8:8 |vpiRhs: @@ -157851,7 +157849,7 @@ design: (work@otp_ctrl) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:8:10, endln:8:16 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:20 + \_assignment: , line:8:10, endln:8:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: @@ -232211,7 +232209,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -232222,11 +232219,11 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiName:offset + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -232237,6 +232234,7 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiName:size + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 \_param_assign: , line:786:18, endln:786:77 @@ -235648,7 +235646,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -235659,11 +235656,11 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiName:offset + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -235674,6 +235671,7 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiName:size + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 \_param_assign: , line:786:18, endln:786:77 @@ -239085,7 +239083,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -239096,11 +239093,11 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiName:offset + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -239111,6 +239108,7 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiName:size + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 \_param_assign: , line:786:18, endln:786:77 @@ -242522,7 +242520,6 @@ design: (work@otp_ctrl) \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.offset |vpiActual: \_ref_obj: (Info), line:786:38, endln:786:44 |vpiParent: @@ -242533,11 +242530,11 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.offset), line:786:33, endln:786:44 |vpiName:offset + |vpiName:Info.offset |vpiOperand: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiParent: \_operation: , line:786:33, endln:786:56 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:786:52, endln:786:56 |vpiParent: @@ -242548,6 +242545,7 @@ design: (work@otp_ctrl) |vpiParent: \_hier_path: (Info.size), line:786:47, endln:786:56 |vpiName:size + |vpiName:Info.size |vpiOperand: \_constant: , line:786:59, endln:786:75 \_param_assign: , line:786:18, endln:786:77 diff --git a/tests/BlackParrotParam/BlackParrotParam.log b/tests/BlackParrotParam/BlackParrotParam.log index 4ac44694ba..ac1fc80f64 100644 --- a/tests/BlackParrotParam/BlackParrotParam.log +++ b/tests/BlackParrotParam/BlackParrotParam.log @@ -49912,7 +49912,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.num_core), line:4381:29, endln:4381:51 |vpiParent: \_param_assign: , line:4381:16, endln:4381:51 - |vpiName:proc_param_lp.num_core |vpiActual: \_ref_obj: (proc_param_lp), line:4381:43, endln:4381:51 |vpiParent: @@ -49923,6 +49922,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.num_core), line:4381:29, endln:4381:51 |vpiName:num_core + |vpiName:proc_param_lp.num_core |vpiLhs: \_parameter: (work@bp_be_ptw.num_core_p), line:4381:16, endln:4381:26 |vpiParamAssign: @@ -49933,7 +49933,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.num_cce), line:4382:29, endln:4382:50 |vpiParent: \_param_assign: , line:4382:16, endln:4382:50 - |vpiName:proc_param_lp.num_cce |vpiActual: \_ref_obj: (proc_param_lp), line:4382:43, endln:4382:50 |vpiParent: @@ -49944,6 +49943,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.num_cce), line:4382:29, endln:4382:50 |vpiName:num_cce + |vpiName:proc_param_lp.num_cce |vpiLhs: \_parameter: (work@bp_be_ptw.num_cce_p), line:4382:16, endln:4382:25 |vpiParamAssign: @@ -49954,7 +49954,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.num_lce), line:4383:29, endln:4383:50 |vpiParent: \_param_assign: , line:4383:16, endln:4383:50 - |vpiName:proc_param_lp.num_lce |vpiActual: \_ref_obj: (proc_param_lp), line:4383:43, endln:4383:50 |vpiParent: @@ -49965,6 +49964,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.num_lce), line:4383:29, endln:4383:50 |vpiName:num_lce + |vpiName:proc_param_lp.num_lce |vpiLhs: \_parameter: (work@bp_be_ptw.num_lce_p), line:4383:16, endln:4383:25 |vpiParamAssign: @@ -49975,7 +49975,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.vaddr_width), line:4385:32, endln:4385:57 |vpiParent: \_param_assign: , line:4385:16, endln:4385:57 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:4385:46, endln:4385:57 |vpiParent: @@ -49986,6 +49985,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:4385:32, endln:4385:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiLhs: \_parameter: (work@bp_be_ptw.vaddr_width_p), line:4385:16, endln:4385:29 |vpiParamAssign: @@ -49996,7 +49996,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.paddr_width), line:4386:32, endln:4386:57 |vpiParent: \_param_assign: , line:4386:16, endln:4386:57 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:4386:46, endln:4386:57 |vpiParent: @@ -50007,6 +50006,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:4386:32, endln:4386:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiLhs: \_parameter: (work@bp_be_ptw.paddr_width_p), line:4386:16, endln:4386:29 |vpiParamAssign: @@ -50017,7 +50017,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.asid_width), line:4387:32, endln:4387:56 |vpiParent: \_param_assign: , line:4387:16, endln:4387:56 - |vpiName:proc_param_lp.asid_width |vpiActual: \_ref_obj: (proc_param_lp), line:4387:46, endln:4387:56 |vpiParent: @@ -50028,6 +50027,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.asid_width), line:4387:32, endln:4387:56 |vpiName:asid_width + |vpiName:proc_param_lp.asid_width |vpiLhs: \_parameter: (work@bp_be_ptw.asid_width_p), line:4387:16, endln:4387:28 |vpiParamAssign: @@ -50038,7 +50038,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:4389:46, endln:4389:85 |vpiParent: \_param_assign: , line:4389:16, endln:4389:85 - |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiActual: \_ref_obj: (proc_param_lp), line:4389:60, endln:4389:85 |vpiParent: @@ -50049,6 +50048,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.branch_metadata_fwd_width), line:4389:46, endln:4389:85 |vpiName:branch_metadata_fwd_width + |vpiName:proc_param_lp.branch_metadata_fwd_width |vpiLhs: \_parameter: (work@bp_be_ptw.branch_metadata_fwd_width_p), line:4389:16, endln:4389:43 |vpiParamAssign: @@ -50059,7 +50059,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.btb_tag_width), line:4390:46, endln:4390:73 |vpiParent: \_param_assign: , line:4390:16, endln:4390:73 - |vpiName:proc_param_lp.btb_tag_width |vpiActual: \_ref_obj: (proc_param_lp), line:4390:60, endln:4390:73 |vpiParent: @@ -50070,6 +50069,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.btb_tag_width), line:4390:46, endln:4390:73 |vpiName:btb_tag_width + |vpiName:proc_param_lp.btb_tag_width |vpiLhs: \_parameter: (work@bp_be_ptw.btb_tag_width_p), line:4390:16, endln:4390:31 |vpiParamAssign: @@ -50080,7 +50080,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.btb_idx_width), line:4391:46, endln:4391:73 |vpiParent: \_param_assign: , line:4391:16, endln:4391:73 - |vpiName:proc_param_lp.btb_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:4391:60, endln:4391:73 |vpiParent: @@ -50091,6 +50090,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.btb_idx_width), line:4391:46, endln:4391:73 |vpiName:btb_idx_width + |vpiName:proc_param_lp.btb_idx_width |vpiLhs: \_parameter: (work@bp_be_ptw.btb_idx_width_p), line:4391:16, endln:4391:31 |vpiParamAssign: @@ -50101,7 +50101,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.bht_idx_width), line:4392:46, endln:4392:73 |vpiParent: \_param_assign: , line:4392:16, endln:4392:73 - |vpiName:proc_param_lp.bht_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:4392:60, endln:4392:73 |vpiParent: @@ -50112,6 +50111,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.bht_idx_width), line:4392:46, endln:4392:73 |vpiName:bht_idx_width + |vpiName:proc_param_lp.bht_idx_width |vpiLhs: \_parameter: (work@bp_be_ptw.bht_idx_width_p), line:4392:16, endln:4392:31 |vpiParamAssign: @@ -50122,7 +50122,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.ras_idx_width), line:4393:46, endln:4393:73 |vpiParent: \_param_assign: , line:4393:16, endln:4393:73 - |vpiName:proc_param_lp.ras_idx_width |vpiActual: \_ref_obj: (proc_param_lp), line:4393:60, endln:4393:73 |vpiParent: @@ -50133,6 +50132,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.ras_idx_width), line:4393:46, endln:4393:73 |vpiName:ras_idx_width + |vpiName:proc_param_lp.ras_idx_width |vpiLhs: \_parameter: (work@bp_be_ptw.ras_idx_width_p), line:4393:16, endln:4393:31 |vpiParamAssign: @@ -50143,7 +50143,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.itlb_els), line:4395:42, endln:4395:64 |vpiParent: \_param_assign: , line:4395:16, endln:4395:64 - |vpiName:proc_param_lp.itlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:4395:56, endln:4395:64 |vpiParent: @@ -50154,6 +50153,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.itlb_els), line:4395:42, endln:4395:64 |vpiName:itlb_els + |vpiName:proc_param_lp.itlb_els |vpiLhs: \_parameter: (work@bp_be_ptw.itlb_els_p), line:4395:16, endln:4395:26 |vpiParamAssign: @@ -50164,7 +50164,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.dtlb_els), line:4396:42, endln:4396:64 |vpiParent: \_param_assign: , line:4396:16, endln:4396:64 - |vpiName:proc_param_lp.dtlb_els |vpiActual: \_ref_obj: (proc_param_lp), line:4396:56, endln:4396:64 |vpiParent: @@ -50175,6 +50174,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.dtlb_els), line:4396:42, endln:4396:64 |vpiName:dtlb_els + |vpiName:proc_param_lp.dtlb_els |vpiLhs: \_parameter: (work@bp_be_ptw.dtlb_els_p), line:4396:16, endln:4396:26 |vpiParamAssign: @@ -50185,7 +50185,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.lce_sets), line:4398:42, endln:4398:64 |vpiParent: \_param_assign: , line:4398:16, endln:4398:64 - |vpiName:proc_param_lp.lce_sets |vpiActual: \_ref_obj: (proc_param_lp), line:4398:56, endln:4398:64 |vpiParent: @@ -50196,6 +50195,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.lce_sets), line:4398:42, endln:4398:64 |vpiName:lce_sets + |vpiName:proc_param_lp.lce_sets |vpiLhs: \_parameter: (work@bp_be_ptw.lce_sets_p), line:4398:16, endln:4398:26 |vpiParamAssign: @@ -50206,7 +50206,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.lce_assoc), line:4399:42, endln:4399:65 |vpiParent: \_param_assign: , line:4399:16, endln:4399:65 - |vpiName:proc_param_lp.lce_assoc |vpiActual: \_ref_obj: (proc_param_lp), line:4399:56, endln:4399:65 |vpiParent: @@ -50217,6 +50216,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.lce_assoc), line:4399:42, endln:4399:65 |vpiName:lce_assoc + |vpiName:proc_param_lp.lce_assoc |vpiLhs: \_parameter: (work@bp_be_ptw.lce_assoc_p), line:4399:16, endln:4399:27 |vpiParamAssign: @@ -50227,7 +50227,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.cce_block_width), line:4400:42, endln:4400:71 |vpiParent: \_param_assign: , line:4400:16, endln:4400:71 - |vpiName:proc_param_lp.cce_block_width |vpiActual: \_ref_obj: (proc_param_lp), line:4400:56, endln:4400:71 |vpiParent: @@ -50238,6 +50237,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.cce_block_width), line:4400:42, endln:4400:71 |vpiName:cce_block_width + |vpiName:proc_param_lp.cce_block_width |vpiLhs: \_parameter: (work@bp_be_ptw.cce_block_width_p), line:4400:16, endln:4400:33 |vpiParamAssign: @@ -50248,7 +50248,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.num_cce_instr_ram_els), line:4401:42, endln:4401:77 |vpiParent: \_param_assign: , line:4401:16, endln:4401:77 - |vpiName:proc_param_lp.num_cce_instr_ram_els |vpiActual: \_ref_obj: (proc_param_lp), line:4401:56, endln:4401:77 |vpiParent: @@ -50259,6 +50258,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.num_cce_instr_ram_els), line:4401:42, endln:4401:77 |vpiName:num_cce_instr_ram_els + |vpiName:proc_param_lp.num_cce_instr_ram_els |vpiLhs: \_parameter: (work@bp_be_ptw.num_cce_instr_ram_els_p), line:4401:16, endln:4401:39 |vpiParamAssign: @@ -50269,7 +50269,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:4403:38, endln:4403:69 |vpiParent: \_param_assign: , line:4403:16, endln:4403:69 - |vpiName:proc_param_lp.fe_queue_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:4403:52, endln:4403:69 |vpiParent: @@ -50280,6 +50279,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.fe_queue_fifo_els), line:4403:38, endln:4403:69 |vpiName:fe_queue_fifo_els + |vpiName:proc_param_lp.fe_queue_fifo_els |vpiLhs: \_parameter: (work@bp_be_ptw.fe_queue_fifo_els_p), line:4403:16, endln:4403:35 |vpiParamAssign: @@ -50290,7 +50290,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:4404:38, endln:4404:67 |vpiParent: \_param_assign: , line:4404:16, endln:4404:67 - |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiActual: \_ref_obj: (proc_param_lp), line:4404:52, endln:4404:67 |vpiParent: @@ -50301,6 +50300,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.fe_cmd_fifo_els), line:4404:38, endln:4404:67 |vpiName:fe_cmd_fifo_els + |vpiName:proc_param_lp.fe_cmd_fifo_els |vpiLhs: \_parameter: (work@bp_be_ptw.fe_cmd_fifo_els_p), line:4404:16, endln:4404:33 |vpiParamAssign: @@ -50311,7 +50311,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.async_coh_clk), line:4406:41, endln:4406:68 |vpiParent: \_param_assign: , line:4406:16, endln:4406:68 - |vpiName:proc_param_lp.async_coh_clk |vpiActual: \_ref_obj: (proc_param_lp), line:4406:55, endln:4406:68 |vpiParent: @@ -50322,6 +50321,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.async_coh_clk), line:4406:41, endln:4406:68 |vpiName:async_coh_clk + |vpiName:proc_param_lp.async_coh_clk |vpiLhs: \_parameter: (work@bp_be_ptw.async_coh_clk_p), line:4406:16, endln:4406:31 |vpiParamAssign: @@ -50332,7 +50332,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_flit_width), line:4407:41, endln:4407:73 |vpiParent: \_param_assign: , line:4407:16, endln:4407:73 - |vpiName:proc_param_lp.coh_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:4407:55, endln:4407:73 |vpiParent: @@ -50343,6 +50342,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_flit_width), line:4407:41, endln:4407:73 |vpiName:coh_noc_flit_width + |vpiName:proc_param_lp.coh_noc_flit_width |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_flit_width_p), line:4407:16, endln:4407:36 |vpiParamAssign: @@ -50353,7 +50353,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_cid_width), line:4408:41, endln:4408:72 |vpiParent: \_param_assign: , line:4408:16, endln:4408:72 - |vpiName:proc_param_lp.coh_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:4408:55, endln:4408:72 |vpiParent: @@ -50364,6 +50363,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_cid_width), line:4408:41, endln:4408:72 |vpiName:coh_noc_cid_width + |vpiName:proc_param_lp.coh_noc_cid_width |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_cid_width_p), line:4408:16, endln:4408:35 |vpiParamAssign: @@ -50374,7 +50374,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_len_width), line:4409:41, endln:4409:72 |vpiParent: \_param_assign: , line:4409:16, endln:4409:72 - |vpiName:proc_param_lp.coh_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:4409:55, endln:4409:72 |vpiParent: @@ -50385,6 +50384,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_len_width), line:4409:41, endln:4409:72 |vpiName:coh_noc_len_width + |vpiName:proc_param_lp.coh_noc_len_width |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_len_width_p), line:4409:16, endln:4409:35 |vpiParamAssign: @@ -50395,7 +50395,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_y_cord_width), line:4410:41, endln:4410:75 |vpiParent: \_param_assign: , line:4410:16, endln:4410:75 - |vpiName:proc_param_lp.coh_noc_y_cord_width |vpiActual: \_ref_obj: (proc_param_lp), line:4410:55, endln:4410:75 |vpiParent: @@ -50406,6 +50405,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_y_cord_width), line:4410:41, endln:4410:75 |vpiName:coh_noc_y_cord_width + |vpiName:proc_param_lp.coh_noc_y_cord_width |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_y_cord_width_p), line:4410:16, endln:4410:38 |vpiParamAssign: @@ -50416,7 +50416,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_x_cord_width), line:4411:41, endln:4411:75 |vpiParent: \_param_assign: , line:4411:16, endln:4411:75 - |vpiName:proc_param_lp.coh_noc_x_cord_width |vpiActual: \_ref_obj: (proc_param_lp), line:4411:55, endln:4411:75 |vpiParent: @@ -50427,6 +50426,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_x_cord_width), line:4411:41, endln:4411:75 |vpiName:coh_noc_x_cord_width + |vpiName:proc_param_lp.coh_noc_x_cord_width |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_x_cord_width_p), line:4411:16, endln:4411:38 |vpiParamAssign: @@ -50437,7 +50437,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_y_dim), line:4412:41, endln:4412:68 |vpiParent: \_param_assign: , line:4412:16, endln:4412:68 - |vpiName:proc_param_lp.coh_noc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:4412:55, endln:4412:68 |vpiParent: @@ -50448,6 +50447,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_y_dim), line:4412:41, endln:4412:68 |vpiName:coh_noc_y_dim + |vpiName:proc_param_lp.coh_noc_y_dim |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_y_dim_p), line:4412:16, endln:4412:31 |vpiParamAssign: @@ -50458,7 +50458,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.coh_noc_x_dim), line:4413:41, endln:4413:68 |vpiParent: \_param_assign: , line:4413:16, endln:4413:68 - |vpiName:proc_param_lp.coh_noc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:4413:55, endln:4413:68 |vpiParent: @@ -50469,6 +50468,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.coh_noc_x_dim), line:4413:41, endln:4413:68 |vpiName:coh_noc_x_dim + |vpiName:proc_param_lp.coh_noc_x_dim |vpiLhs: \_parameter: (work@bp_be_ptw.coh_noc_x_dim_p), line:4413:16, endln:4413:31 |vpiParamAssign: @@ -50590,7 +50590,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.cfg_core_width), line:4420:35, endln:4420:63 |vpiParent: \_param_assign: , line:4420:16, endln:4420:63 - |vpiName:proc_param_lp.cfg_core_width |vpiActual: \_ref_obj: (proc_param_lp), line:4420:49, endln:4420:63 |vpiParent: @@ -50601,6 +50600,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.cfg_core_width), line:4420:35, endln:4420:63 |vpiName:cfg_core_width + |vpiName:proc_param_lp.cfg_core_width |vpiLhs: \_parameter: (work@bp_be_ptw.cfg_core_width_p), line:4420:16, endln:4420:32 |vpiParamAssign: @@ -50611,7 +50611,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.cfg_addr_width), line:4421:35, endln:4421:63 |vpiParent: \_param_assign: , line:4421:16, endln:4421:63 - |vpiName:proc_param_lp.cfg_addr_width |vpiActual: \_ref_obj: (proc_param_lp), line:4421:49, endln:4421:63 |vpiParent: @@ -50622,6 +50621,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.cfg_addr_width), line:4421:35, endln:4421:63 |vpiName:cfg_addr_width + |vpiName:proc_param_lp.cfg_addr_width |vpiLhs: \_parameter: (work@bp_be_ptw.cfg_addr_width_p), line:4421:16, endln:4421:32 |vpiParamAssign: @@ -50632,7 +50632,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.cfg_data_width), line:4422:35, endln:4422:63 |vpiParent: \_param_assign: , line:4422:16, endln:4422:63 - |vpiName:proc_param_lp.cfg_data_width |vpiActual: \_ref_obj: (proc_param_lp), line:4422:49, endln:4422:63 |vpiParent: @@ -50643,6 +50642,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.cfg_data_width), line:4422:35, endln:4422:63 |vpiName:cfg_data_width + |vpiName:proc_param_lp.cfg_data_width |vpiLhs: \_parameter: (work@bp_be_ptw.cfg_data_width_p), line:4422:16, endln:4422:32 |vpiParamAssign: @@ -50653,7 +50653,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.async_mem_clk), line:4424:44, endln:4424:71 |vpiParent: \_param_assign: , line:4424:16, endln:4424:71 - |vpiName:proc_param_lp.async_mem_clk |vpiActual: \_ref_obj: (proc_param_lp), line:4424:58, endln:4424:71 |vpiParent: @@ -50664,6 +50663,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.async_mem_clk), line:4424:44, endln:4424:71 |vpiName:async_mem_clk + |vpiName:proc_param_lp.async_mem_clk |vpiLhs: \_parameter: (work@bp_be_ptw.async_mem_clk_p), line:4424:16, endln:4424:31 |vpiParamAssign: @@ -50674,7 +50674,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_max_credits), line:4425:44, endln:4425:77 |vpiParent: \_param_assign: , line:4425:16, endln:4425:77 - |vpiName:proc_param_lp.mem_noc_max_credits |vpiActual: \_ref_obj: (proc_param_lp), line:4425:58, endln:4425:77 |vpiParent: @@ -50685,6 +50684,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_max_credits), line:4425:44, endln:4425:77 |vpiName:mem_noc_max_credits + |vpiName:proc_param_lp.mem_noc_max_credits |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_max_credits_p), line:4425:16, endln:4425:37 |vpiParamAssign: @@ -50695,7 +50695,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_flit_width), line:4426:44, endln:4426:76 |vpiParent: \_param_assign: , line:4426:16, endln:4426:76 - |vpiName:proc_param_lp.mem_noc_flit_width |vpiActual: \_ref_obj: (proc_param_lp), line:4426:58, endln:4426:76 |vpiParent: @@ -50706,6 +50705,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_flit_width), line:4426:44, endln:4426:76 |vpiName:mem_noc_flit_width + |vpiName:proc_param_lp.mem_noc_flit_width |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_flit_width_p), line:4426:16, endln:4426:36 |vpiParamAssign: @@ -50716,7 +50716,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_reserved_width), line:4427:44, endln:4427:80 |vpiParent: \_param_assign: , line:4427:16, endln:4427:80 - |vpiName:proc_param_lp.mem_noc_reserved_width |vpiActual: \_ref_obj: (proc_param_lp), line:4427:58, endln:4427:80 |vpiParent: @@ -50727,6 +50726,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_reserved_width), line:4427:44, endln:4427:80 |vpiName:mem_noc_reserved_width + |vpiName:proc_param_lp.mem_noc_reserved_width |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_reserved_width_p), line:4427:16, endln:4427:40 |vpiParamAssign: @@ -50737,7 +50737,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_cid_width), line:4428:44, endln:4428:75 |vpiParent: \_param_assign: , line:4428:16, endln:4428:75 - |vpiName:proc_param_lp.mem_noc_cid_width |vpiActual: \_ref_obj: (proc_param_lp), line:4428:58, endln:4428:75 |vpiParent: @@ -50748,6 +50747,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_cid_width), line:4428:44, endln:4428:75 |vpiName:mem_noc_cid_width + |vpiName:proc_param_lp.mem_noc_cid_width |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_cid_width_p), line:4428:16, endln:4428:35 |vpiParamAssign: @@ -50758,7 +50758,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_len_width), line:4429:44, endln:4429:75 |vpiParent: \_param_assign: , line:4429:16, endln:4429:75 - |vpiName:proc_param_lp.mem_noc_len_width |vpiActual: \_ref_obj: (proc_param_lp), line:4429:58, endln:4429:75 |vpiParent: @@ -50769,6 +50768,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_len_width), line:4429:44, endln:4429:75 |vpiName:mem_noc_len_width + |vpiName:proc_param_lp.mem_noc_len_width |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_len_width_p), line:4429:16, endln:4429:35 |vpiParamAssign: @@ -50779,7 +50779,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_y_cord_width), line:4430:44, endln:4430:78 |vpiParent: \_param_assign: , line:4430:16, endln:4430:78 - |vpiName:proc_param_lp.mem_noc_y_cord_width |vpiActual: \_ref_obj: (proc_param_lp), line:4430:58, endln:4430:78 |vpiParent: @@ -50790,6 +50789,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_y_cord_width), line:4430:44, endln:4430:78 |vpiName:mem_noc_y_cord_width + |vpiName:proc_param_lp.mem_noc_y_cord_width |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_y_cord_width_p), line:4430:16, endln:4430:38 |vpiParamAssign: @@ -50800,7 +50800,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_x_cord_width), line:4431:44, endln:4431:78 |vpiParent: \_param_assign: , line:4431:16, endln:4431:78 - |vpiName:proc_param_lp.mem_noc_x_cord_width |vpiActual: \_ref_obj: (proc_param_lp), line:4431:58, endln:4431:78 |vpiParent: @@ -50811,6 +50810,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_x_cord_width), line:4431:44, endln:4431:78 |vpiName:mem_noc_x_cord_width + |vpiName:proc_param_lp.mem_noc_x_cord_width |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_x_cord_width_p), line:4431:16, endln:4431:38 |vpiParamAssign: @@ -50821,7 +50821,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_y_dim), line:4432:44, endln:4432:71 |vpiParent: \_param_assign: , line:4432:16, endln:4432:71 - |vpiName:proc_param_lp.mem_noc_y_dim |vpiActual: \_ref_obj: (proc_param_lp), line:4432:58, endln:4432:71 |vpiParent: @@ -50832,6 +50831,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_y_dim), line:4432:44, endln:4432:71 |vpiName:mem_noc_y_dim + |vpiName:proc_param_lp.mem_noc_y_dim |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_y_dim_p), line:4432:16, endln:4432:31 |vpiParamAssign: @@ -50842,7 +50842,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.mem_noc_x_dim), line:4433:44, endln:4433:71 |vpiParent: \_param_assign: , line:4433:16, endln:4433:71 - |vpiName:proc_param_lp.mem_noc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:4433:58, endln:4433:71 |vpiParent: @@ -50853,6 +50852,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.mem_noc_x_dim), line:4433:44, endln:4433:71 |vpiName:mem_noc_x_dim + |vpiName:proc_param_lp.mem_noc_x_dim |vpiLhs: \_parameter: (work@bp_be_ptw.mem_noc_x_dim_p), line:4433:16, endln:4433:31 |vpiParamAssign: @@ -51126,7 +51126,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.vaddr_width), line:4448:32, endln:4448:57 |vpiParent: \_operation: , line:4448:32, endln:4448:79 - |vpiName:proc_param_lp.vaddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:4448:46, endln:4448:57 |vpiParent: @@ -51137,6 +51136,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.vaddr_width), line:4448:32, endln:4448:57 |vpiName:vaddr_width + |vpiName:proc_param_lp.vaddr_width |vpiOperand: \_ref_obj: (work@bp_be_ptw.page_offset_width_p), line:4448:60, endln:4448:79 |vpiParent: @@ -51158,7 +51158,6 @@ design: (work@bp_be_ptw) \_hier_path: (proc_param_lp.paddr_width), line:4449:32, endln:4449:57 |vpiParent: \_operation: , line:4449:32, endln:4449:79 - |vpiName:proc_param_lp.paddr_width |vpiActual: \_ref_obj: (proc_param_lp), line:4449:46, endln:4449:57 |vpiParent: @@ -51169,6 +51168,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (proc_param_lp.paddr_width), line:4449:32, endln:4449:57 |vpiName:paddr_width + |vpiName:proc_param_lp.paddr_width |vpiOperand: \_ref_obj: (work@bp_be_ptw.page_offset_width_p), line:4449:60, endln:4449:79 |vpiParent: @@ -52619,7 +52619,6 @@ design: (work@bp_be_ptw) \_hier_path: (tlb_w_entry.ptag), line:4625:10, endln:4625:26 |vpiParent: \_cont_assign: , line:4625:10, endln:4625:90 - |vpiName:tlb_w_entry.ptag |vpiActual: \_ref_obj: (tlb_w_entry), line:4625:22, endln:4625:26 |vpiParent: @@ -52630,6 +52629,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (tlb_w_entry.ptag), line:4625:10, endln:4625:26 |vpiName:ptag + |vpiName:tlb_w_entry.ptag |uhdmtopModules: \_module_inst: work@bp_be_ptw (work@bp_be_ptw), file:${SURELOG_DIR}/tests/BlackParrotParam/dut.sv, line:4371:1, endln:4628:10 |vpiName:work@bp_be_ptw @@ -60440,7 +60440,6 @@ design: (work@bp_be_ptw) \_hier_path: (tlb_w_entry.ptag), line:4625:10, endln:4625:26 |vpiParent: \_cont_assign: , line:4625:10, endln:4625:90 - |vpiName:tlb_w_entry.ptag |vpiActual: \_ref_obj: (tlb_w_entry), line:4625:22, endln:4625:26 |vpiParent: @@ -60451,6 +60450,7 @@ design: (work@bp_be_ptw) |vpiParent: \_hier_path: (tlb_w_entry.ptag), line:4625:10, endln:4625:26 |vpiName:ptag + |vpiName:tlb_w_entry.ptag \_weaklyReferenced: \_int_typespec: , line:78:1, endln:78:32 \_int_typespec: , line:79:1, endln:79:32 diff --git a/tests/BlackParrotStructParam/BlackParrotStructParam.log b/tests/BlackParrotStructParam/BlackParrotStructParam.log index c83ca84f75..975033232a 100644 --- a/tests/BlackParrotStructParam/BlackParrotStructParam.log +++ b/tests/BlackParrotStructParam/BlackParrotStructParam.log @@ -2288,7 +2288,6 @@ design: (work@top) \_hier_path: (proc_param_lp.cc_x_dim), line:58:28, endln:58:50 |vpiParent: \_param_assign: , line:58:14, endln:58:50 - |vpiName:proc_param_lp.cc_x_dim |vpiActual: \_ref_obj: (proc_param_lp), line:58:42, endln:58:50 |vpiParent: @@ -2299,6 +2298,7 @@ design: (work@top) |vpiParent: \_hier_path: (proc_param_lp.cc_x_dim), line:58:28, endln:58:50 |vpiName:cc_x_dim + |vpiName:proc_param_lp.cc_x_dim |vpiLhs: \_parameter: (work@top.cc_x_dim_p), line:58:14, endln:58:24 |vpiTypedef: diff --git a/tests/BuiltInMethod/BuiltInMethod.log b/tests/BuiltInMethod/BuiltInMethod.log index cd03c7039b..9e7504f677 100644 --- a/tests/BuiltInMethod/BuiltInMethod.log +++ b/tests/BuiltInMethod/BuiltInMethod.log @@ -331,7 +331,6 @@ design: (work@top) \_hier_path: (b), line:3:14, endln:3:19 |vpiParent: \_byte_var: (work@top.o), line:3:10, endln:3:19 - |vpiName:b |vpiActual: \_ref_obj: (work@top.o.b), line:3:14, endln:3:15 |vpiParent: @@ -345,6 +344,7 @@ design: (work@top) |vpiParent: \_hier_path: (b), line:3:14, endln:3:19 |vpiName:and + |vpiName:b |vpiVariables: \_byte_var: (work@top.o), line:4:10, endln:4:18 |vpiParent: @@ -363,7 +363,6 @@ design: (work@top) \_hier_path: (b), line:4:14, endln:4:18 |vpiParent: \_byte_var: (work@top.o), line:4:10, endln:4:18 - |vpiName:b |vpiActual: \_ref_obj: (work@top.o.b), line:4:14, endln:4:15 |vpiParent: @@ -377,6 +376,7 @@ design: (work@top) |vpiParent: \_hier_path: (b), line:4:14, endln:4:18 |vpiName:or + |vpiName:b |vpiVariables: \_byte_var: (work@top.o), line:5:10, endln:5:19 |vpiParent: @@ -395,7 +395,6 @@ design: (work@top) \_hier_path: (b), line:5:14, endln:5:19 |vpiParent: \_byte_var: (work@top.o), line:5:10, endln:5:19 - |vpiName:b |vpiActual: \_ref_obj: (work@top.o.b), line:5:14, endln:5:15 |vpiParent: @@ -409,6 +408,7 @@ design: (work@top) |vpiParent: \_hier_path: (b), line:5:14, endln:5:19 |vpiName:xor + |vpiName:b |vpiVariables: \_byte_var: (work@top.o), line:6:10, endln:6:22 |vpiParent: @@ -427,7 +427,6 @@ design: (work@top) \_hier_path: (b), line:6:14, endln:6:22 |vpiParent: \_byte_var: (work@top.o), line:6:10, endln:6:22 - |vpiName:b |vpiActual: \_ref_obj: (work@top.o.b), line:6:14, endln:6:15 |vpiParent: @@ -441,6 +440,7 @@ design: (work@top) |vpiParent: \_hier_path: (b), line:6:14, endln:6:22 |vpiName:unique + |vpiName:b |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 diff --git a/tests/CarryAdd/CarryAdd.log b/tests/CarryAdd/CarryAdd.log index 1357f47454..6465a8aa29 100644 --- a/tests/CarryAdd/CarryAdd.log +++ b/tests/CarryAdd/CarryAdd.log @@ -1162,7 +1162,6 @@ design: (work@carryadd) \_hier_path: (STAGE[i - 1].C), line:16:65, endln:16:77 |vpiParent: \_operation: , line:16:51, endln:16:77 - |vpiName:STAGE[i - 1].C |vpiActual: \_bit_select: (STAGE[i - 1]), line:16:65, endln:16:70 |vpiParent: @@ -1198,6 +1197,7 @@ design: (work@carryadd) |vpiFullName:work@carryadd.STAGE[1].genblk1.C |vpiActual: \_logic_net: (work@carryadd.STAGE[1].C), line:12:22, endln:12:23 + |vpiName:STAGE[i - 1].C |vpiLhs: \_ref_obj: (work@carryadd.STAGE[1].genblk1.C), line:16:32, endln:16:33 |vpiParent: @@ -1240,7 +1240,6 @@ design: (work@carryadd) \_hier_path: (STAGE[i - 1].C), line:17:48, endln:17:60 |vpiParent: \_operation: , line:17:36, endln:17:60 - |vpiName:STAGE[i - 1].C |vpiActual: \_bit_select: (STAGE[i - 1]), line:17:48, endln:17:53 |vpiParent: @@ -1276,6 +1275,7 @@ design: (work@carryadd) |vpiFullName:work@carryadd.STAGE[1].genblk1.C |vpiActual: \_logic_net: (work@carryadd.STAGE[1].C), line:12:22, endln:12:23 + |vpiName:STAGE[i - 1].C |vpiLhs: \_ref_obj: (work@carryadd.STAGE[1].genblk1.Y), line:17:32, endln:17:33 |vpiParent: @@ -1397,7 +1397,6 @@ design: (work@carryadd) \_hier_path: (STAGE[i - 1].C), line:16:65, endln:16:77 |vpiParent: \_operation: , line:16:51, endln:16:77 - |vpiName:STAGE[i - 1].C |vpiActual: \_bit_select: (STAGE[i - 1]), line:16:65, endln:16:70 |vpiParent: @@ -1412,6 +1411,7 @@ design: (work@carryadd) \_hier_path: (STAGE[i - 1].C), line:16:65, endln:16:77 |vpiName:C |vpiFullName:work@carryadd.STAGE[1].genblk1.C + |vpiName:STAGE[i - 1].C \_operation: , line:16:51, endln:16:77 |vpiParent: \_operation: , line:16:36, endln:16:78 @@ -1486,7 +1486,6 @@ design: (work@carryadd) \_hier_path: (STAGE[i - 1].C), line:17:48, endln:17:60 |vpiParent: \_operation: , line:17:36, endln:17:60 - |vpiName:STAGE[i - 1].C |vpiActual: \_bit_select: (STAGE[i - 1]), line:17:48, endln:17:53 |vpiParent: @@ -1501,6 +1500,7 @@ design: (work@carryadd) \_hier_path: (STAGE[i - 1].C), line:17:48, endln:17:60 |vpiName:C |vpiFullName:work@carryadd.STAGE[1].genblk1.C + |vpiName:STAGE[i - 1].C \_operation: , line:17:36, endln:17:60 |vpiParent: \_cont_assign: , line:16:32, endln:17:60 diff --git a/tests/CaseInside/CaseInside.log b/tests/CaseInside/CaseInside.log index 47608166af..d668348e92 100644 --- a/tests/CaseInside/CaseInside.log +++ b/tests/CaseInside/CaseInside.log @@ -1135,7 +1135,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr), line:15:27, endln:15:41 |vpiParent: \_operation: , line:15:20, endln:15:42 - |vpiName:dmi_req_i.addr |vpiActual: \_ref_obj: (dmi_req_i), line:15:27, endln:15:36 |vpiParent: @@ -1147,6 +1146,7 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr), line:15:27, endln:15:41 |vpiName:addr |vpiFullName:work@dm_csrs.csr_read_write.addr + |vpiName:dmi_req_i.addr |vpiCaseItem: \_case_item: , line:17:9, endln:21:12 |vpiParent: @@ -1279,7 +1279,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr), line:15:27, endln:15:41 |vpiParent: \_operation: , line:15:20, endln:15:42 - |vpiName:dmi_req_i.addr |vpiActual: \_ref_obj: (dmi_req_i), line:15:27, endln:15:36 |vpiParent: @@ -1291,6 +1290,7 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr), line:15:27, endln:15:41 |vpiName:addr |vpiFullName:work@dm_csrs.csr_read_write.addr + |vpiName:dmi_req_i.addr |vpiCaseItem: \_case_item: , line:17:9, endln:21:12 |vpiParent: diff --git a/tests/CastEnum/CastEnum.log b/tests/CastEnum/CastEnum.log index 772b7ad75d..36a276486c 100644 --- a/tests/CastEnum/CastEnum.log +++ b/tests/CastEnum/CastEnum.log @@ -1042,7 +1042,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.op), line:15:33, endln:15:45 |vpiParent: \_operation: , line:15:19, endln:15:46 - |vpiName:dmi_req_i.op |vpiActual: \_ref_obj: (dmi_req_i), line:15:33, endln:15:42 |vpiParent: @@ -1054,6 +1053,7 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.op), line:15:33, endln:15:45 |vpiName:op |vpiFullName:work@dm_csrs.op + |vpiName:dmi_req_i.op |vpiLhs: \_ref_obj: (work@dm_csrs.dtm_op), line:15:10, endln:15:16 |vpiParent: @@ -1102,7 +1102,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.op), line:15:33, endln:15:45 |vpiParent: \_operation: , line:15:19, endln:15:46 - |vpiName:dmi_req_i.op |vpiActual: \_ref_obj: (dmi_req_i), line:15:33, endln:15:42 |vpiParent: @@ -1114,6 +1113,7 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.op), line:15:33, endln:15:45 |vpiName:op |vpiFullName:work@dm_csrs.op + |vpiName:dmi_req_i.op |vpiLhs: \_ref_obj: (work@dm_csrs.dtm_op), line:15:10, endln:15:16 |vpiParent: @@ -1435,7 +1435,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.op), line:15:33, endln:15:45 |vpiParent: \_operation: , line:15:19, endln:15:46 - |vpiName:dmi_req_i.op |vpiActual: \_ref_obj: (dmi_req_i), line:15:33, endln:15:42 |vpiParent: @@ -1447,6 +1446,7 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.op), line:15:33, endln:15:45 |vpiName:op |vpiFullName:work@dm_csrs.op + |vpiName:dmi_req_i.op \_cont_assign: , line:15:10, endln:15:46 |vpiParent: \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/CastEnum/dut.sv, line:12:1, endln:17:10 diff --git a/tests/CastTypespec/CastTypespec.log b/tests/CastTypespec/CastTypespec.log index db0207fe3e..713629af2b 100644 --- a/tests/CastTypespec/CastTypespec.log +++ b/tests/CastTypespec/CastTypespec.log @@ -726,8 +726,7 @@ AST_DEBUG_END always 1 array_typespec 2 array_var 1 -assign_stmt 1 -assignment 2 +assignment 3 begin 2 class_defn 8 class_typespec 4 @@ -770,8 +769,7 @@ typespec_member 8 always 2 array_typespec 2 array_var 2 -assign_stmt 1 -assignment 4 +assignment 5 begin 4 class_defn 8 class_typespec 4 @@ -2286,7 +2284,6 @@ design: (work@tlul_adapter_host) \_hier_path: (dmcontrol_q.resumereq), line:38:20, endln:38:41 |vpiParent: \_assignment: , line:38:7, endln:38:41 - |vpiName:dmcontrol_q.resumereq |vpiActual: \_ref_obj: (dmcontrol_q), line:38:20, endln:38:31 |vpiParent: @@ -2298,6 +2295,7 @@ design: (work@tlul_adapter_host) \_hier_path: (dmcontrol_q.resumereq), line:38:20, endln:38:41 |vpiName:resumereq |vpiFullName:work@top.p_outmux.resumereq + |vpiName:dmcontrol_q.resumereq |vpiLhs: \_ref_obj: (work@top.p_outmux.resumereq_o), line:38:7, endln:38:18 |vpiParent: @@ -2644,7 +2642,6 @@ design: (work@tlul_adapter_host) \_hier_path: (dmcontrol_q.resumereq), line:38:20, endln:38:41 |vpiParent: \_assignment: , line:38:7, endln:38:41 - |vpiName:dmcontrol_q.resumereq |vpiActual: \_ref_obj: (dmcontrol_q), line:38:20, endln:38:31 |vpiParent: @@ -2656,6 +2653,7 @@ design: (work@tlul_adapter_host) \_hier_path: (dmcontrol_q.resumereq), line:38:20, endln:38:41 |vpiName:resumereq |vpiFullName:work@top.p_outmux.resumereq + |vpiName:dmcontrol_q.resumereq |vpiLhs: \_ref_obj: (work@top.p_outmux.resumereq_o), line:38:7, endln:38:18 |vpiParent: diff --git a/tests/CastUnsigned/CastUnsigned.log b/tests/CastUnsigned/CastUnsigned.log index 0730babfad..1ad8b2dc5d 100644 --- a/tests/CastUnsigned/CastUnsigned.log +++ b/tests/CastUnsigned/CastUnsigned.log @@ -1159,7 +1159,6 @@ design: (work@top) \_hier_path: (hw2reg.stall), line:9:9, endln:9:21 |vpiParent: \_assignment: , line:9:9, endln:9:36 - |vpiName:hw2reg.stall |vpiActual: \_ref_obj: (hw2reg), line:9:16, endln:9:21 |vpiParent: @@ -1170,6 +1169,7 @@ design: (work@top) |vpiParent: \_hier_path: (hw2reg.stall), line:9:9, endln:9:21 |vpiName:stall + |vpiName:hw2reg.stall |vpiAlwaysType:2 |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:2:1, endln:13:10 @@ -1289,7 +1289,6 @@ design: (work@top) \_hier_path: (hw2reg.stall), line:9:9, endln:9:21 |vpiParent: \_assignment: , line:9:9, endln:9:36 - |vpiName:hw2reg.stall |vpiActual: \_ref_obj: (hw2reg), line:9:16, endln:9:21 |vpiParent: @@ -1300,6 +1299,7 @@ design: (work@top) |vpiParent: \_hier_path: (hw2reg.stall), line:9:9, endln:9:21 |vpiName:stall + |vpiName:hw2reg.stall |vpiAlwaysType:2 |uhdmtopModules: \_module_inst: work@M (work@M), file:${SURELOG_DIR}/tests/CastUnsigned/dut.sv, line:15:1, endln:17:10 diff --git a/tests/ClassExtendParam/ClassExtendParam.log b/tests/ClassExtendParam/ClassExtendParam.log index 63c970c9ef..934e4d1365 100644 --- a/tests/ClassExtendParam/ClassExtendParam.log +++ b/tests/ClassExtendParam/ClassExtendParam.log @@ -332,7 +332,6 @@ design: (unnamed) \_hier_path: (m_sequencer.get_full_name), line:10:24, endln:10:51 |vpiParent: \_func_call: (uvm_report_warning), line:10:4, endln:10:52 - |vpiName:m_sequencer.get_full_name |vpiActual: \_ref_obj: (m_sequencer), line:10:24, endln:10:35 |vpiParent: @@ -347,6 +346,7 @@ design: (unnamed) |vpiName:get_full_name |vpiFunction: \_function: (uvm::uvm_sequence_item::get_full_name), line:28:1, endln:29:12 + |vpiName:m_sequencer.get_full_name |vpiName:uvm_report_warning |vpiClassDefn: \_class_defn: (uvm::uvm_sequence), file:${SURELOG_DIR}/tests/ClassExtendParam/dut.sv, line:3:9, endln:5:9 diff --git a/tests/ClassFuncProto/ClassFuncProto.log b/tests/ClassFuncProto/ClassFuncProto.log index 464ffab4ba..1819e6d88a 100644 --- a/tests/ClassFuncProto/ClassFuncProto.log +++ b/tests/ClassFuncProto/ClassFuncProto.log @@ -486,7 +486,7 @@ Instance tree: [ERR:CP0317] ${SURELOG_DIR}/tests/ClassFuncProto/top.v:41:71: Undefined type "uvm_reg". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_typespec 1 class_defn 13 class_typespec 7 @@ -513,7 +513,7 @@ unsupported_typespec 6 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_typespec 1 class_defn 16 class_typespec 7 diff --git a/tests/ClassMemberFunc/ClassMemberFunc.log b/tests/ClassMemberFunc/ClassMemberFunc.log index 56e489a118..ffac0bce7b 100644 --- a/tests/ClassMemberFunc/ClassMemberFunc.log +++ b/tests/ClassMemberFunc/ClassMemberFunc.log @@ -92,7 +92,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 +assignment 4 begin 2 class_defn 2 class_typespec 1 @@ -109,7 +109,7 @@ unsupported_typespec 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 6 +assignment 6 begin 4 class_defn 2 class_typespec 2 @@ -208,14 +208,15 @@ design: (unnamed) |vpiActual: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 |vpiStmt: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiParent: \_begin: (pkg::uvm_sequencer_base::start_phase_sequence), line:15:3, endln:15:38 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (rq.get), line:15:28, endln:15:37 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 - |vpiName:rq.get + \_assignment: , line:15:21, endln:15:37 |vpiActual: \_ref_obj: (rq), line:15:28, endln:15:30 |vpiParent: @@ -236,10 +237,11 @@ design: (unnamed) |vpiActual: \_class_var: (pkg::uvm_sequencer_base::start_phase_sequence::rq), line:13:30, endln:13:32 |vpiName:get + |vpiName:rq.get |vpiLhs: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiTypespec: \_ref_typespec: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc) |vpiParent: @@ -349,14 +351,15 @@ design: (unnamed) |vpiActual: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 |vpiStmt: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiParent: \_begin: (pkg::uvm_sequencer_base::start_phase_sequence), line:15:3, endln:15:38 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (rq.get), line:15:28, endln:15:37 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 - |vpiName:rq.get + \_assignment: , line:15:21, endln:15:37 |vpiActual: \_ref_obj: (rq), line:15:28, endln:15:30 |vpiParent: @@ -377,10 +380,11 @@ design: (unnamed) |vpiActual: \_class_var: (pkg::uvm_sequencer_base::start_phase_sequence::rq), line:13:30, endln:13:32 |vpiName:get + |vpiName:rq.get |vpiLhs: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiTypespec: \_ref_typespec: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc) |vpiParent: @@ -416,7 +420,7 @@ design: (unnamed) |vpiVariables: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiTypespec: \_ref_typespec: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc) |vpiParent: @@ -427,14 +431,15 @@ design: (unnamed) |vpiName:rsrc |vpiFullName:pkg::uvm_sequencer_base::start_phase_sequence::rsrc |vpiStmt: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiParent: \_begin: (pkg::uvm_sequencer_base::start_phase_sequence), line:15:3, endln:15:38 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (rq.get), line:15:28, endln:15:37 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 - |vpiName:rq.get + \_assignment: , line:15:21, endln:15:37 |vpiActual: \_ref_obj: (rq), line:15:28, endln:15:30 |vpiParent: @@ -453,6 +458,7 @@ design: (unnamed) |vpiName:i |vpiFullName:pkg::uvm_sequencer_base::start_phase_sequence::rq.get::i |vpiName:get + |vpiName:rq.get |vpiLhs: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 \_function: (pkg::uvm_sequencer_base::start_phase_sequence), line:12:1, endln:18:12 @@ -494,7 +500,7 @@ design: (unnamed) |vpiVariables: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiTypespec: \_ref_typespec: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc) |vpiParent: @@ -505,14 +511,15 @@ design: (unnamed) |vpiName:rsrc |vpiFullName:pkg::uvm_sequencer_base::start_phase_sequence::rsrc |vpiStmt: - \_assign_stmt: , line:15:21, endln:15:37 + \_assignment: , line:15:21, endln:15:37 |vpiParent: \_begin: (pkg::uvm_sequencer_base::start_phase_sequence), line:15:3, endln:15:38 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (rq.get), line:15:28, endln:15:37 |vpiParent: - \_assign_stmt: , line:15:21, endln:15:37 - |vpiName:rq.get + \_assignment: , line:15:21, endln:15:37 |vpiActual: \_ref_obj: (rq), line:15:28, endln:15:30 |vpiParent: @@ -531,6 +538,7 @@ design: (unnamed) |vpiName:i |vpiFullName:pkg::uvm_sequencer_base::start_phase_sequence::rq.get::i |vpiName:get + |vpiName:rq.get |vpiLhs: \_ref_var: (pkg::uvm_sequencer_base::start_phase_sequence::rsrc), line:15:21, endln:15:25 \_function: (pkg::uvm_sequencer_base::start_phase_sequence), line:12:1, endln:18:12 diff --git a/tests/ClassMemberRef/ClassMemberRef.log b/tests/ClassMemberRef/ClassMemberRef.log index cdb8136641..5b555cd187 100644 --- a/tests/ClassMemberRef/ClassMemberRef.log +++ b/tests/ClassMemberRef/ClassMemberRef.log @@ -259,7 +259,6 @@ design: (work@top) \_hier_path: (knobs.identifier), line:17:1, endln:17:17 |vpiParent: \_assignment: , line:17:1, endln:17:27 - |vpiName:knobs.identifier |vpiActual: \_ref_obj: (knobs), line:17:7, endln:17:17 |vpiParent: @@ -270,6 +269,7 @@ design: (work@top) |vpiParent: \_hier_path: (knobs.identifier), line:17:1, endln:17:17 |vpiName:identifier + |vpiName:knobs.identifier |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:1:1, endln:20:11 |uhdmtopPackages: @@ -391,7 +391,6 @@ design: (work@top) \_hier_path: (knobs.identifier), line:17:1, endln:17:17 |vpiParent: \_assignment: , line:17:1, endln:17:27 - |vpiName:knobs.identifier |vpiActual: \_ref_obj: (knobs), line:17:7, endln:17:17 |vpiParent: @@ -406,6 +405,7 @@ design: (work@top) |vpiName:identifier |vpiActual: \_bit_var: (pkg::m_uvm_printer_knobs::identifier), line:5:7, endln:5:17 + |vpiName:knobs.identifier |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ClassMemberRef/dut.sv, line:1:1, endln:20:11 |uhdmallModules: @@ -560,9 +560,9 @@ design: (work@top) \_hier_path: (printer) |vpiParent: \_assignment: , line:26:5, endln:26:18 - |vpiName:printer |vpiActual: \_ref_obj: (work@top.printer), line:26:5, endln:26:12 + |vpiName:printer \_bit_typespec: , line:11:50, endln:11:53 \_class_typespec: (pkg::uvm_printer), line:24:1, endln:24:6 |vpiName:pkg::uvm_printer diff --git a/tests/ClassMethodCall/ClassMethodCall.log b/tests/ClassMethodCall/ClassMethodCall.log index 6bf182a38b..b89c3c3951 100644 --- a/tests/ClassMethodCall/ClassMethodCall.log +++ b/tests/ClassMethodCall/ClassMethodCall.log @@ -636,9 +636,9 @@ design: (work@door_mod) \_hier_path: (open) |vpiParent: \_assignment: , line:47:9, endln:47:21 - |vpiName:open |vpiActual: \_ref_obj: (work@door_mod.open), line:47:9, endln:47:13 + |vpiName:open \_param_assign: , line:9:15, endln:9:32 |vpiParent: \_class_defn: (pack::door), file:${SURELOG_DIR}/tests/ClassMethodCall/dut.sv, line:4:9, endln:18:9 diff --git a/tests/ClassMini/ClassMini.log b/tests/ClassMini/ClassMini.log index f1e06712f8..0d1bf9c678 100644 --- a/tests/ClassMini/ClassMini.log +++ b/tests/ClassMini/ClassMini.log @@ -481,9 +481,9 @@ design: (work@door_mod) \_hier_path: (open) |vpiParent: \_assignment: , line:24:9, endln:24:21 - |vpiName:open |vpiActual: \_ref_obj: (work@door_mod.open), line:24:9, endln:24:13 + |vpiName:open \_param_assign: , line:7:15, endln:7:32 |vpiParent: \_class_defn: (pack::door), file:${SURELOG_DIR}/tests/ClassMini/dut.sv, line:3:9, endln:11:9 diff --git a/tests/ClassVar/ClassVar.log b/tests/ClassVar/ClassVar.log index 2a09cb7566..c17973699c 100644 --- a/tests/ClassVar/ClassVar.log +++ b/tests/ClassVar/ClassVar.log @@ -138,7 +138,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 3 +assignment 3 begin 2 bit_select 2 class_defn 2 @@ -165,7 +165,7 @@ unsupported_typespec 2 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 5 -assign_stmt 5 +assignment 5 begin 4 bit_select 4 class_defn 2 @@ -446,13 +446,15 @@ design: (unnamed) |vpiName:p_ |vpiFullName:pack::uvm_mem_mam::check_reg::p_ |vpiStmt: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:16:21, endln:22:6 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_bit_select: (pack::uvm_mem_mam::check_reg::paths), line:17:36, endln:17:37 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiName:paths |vpiFullName:pack::uvm_mem_mam::check_reg::paths |vpiActual: @@ -468,7 +470,7 @@ design: (unnamed) |vpiLhs: \_class_var: (pack::uvm_mem_mam::check_reg::path), line:17:25, endln:17:29 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::path) |vpiParent: @@ -479,14 +481,15 @@ design: (unnamed) |vpiName:path |vpiFullName:pack::uvm_mem_mam::check_reg::path |vpiStmt: - \_assign_stmt: , line:18:12, endln:18:37 + \_assignment: , line:18:12, endln:18:37 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:16:21, endln:22:6 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (path.slices[0].spath), line:18:17, endln:18:37 |vpiParent: - \_assign_stmt: , line:18:12, endln:18:37 - |vpiName:path.slices[0].spath + \_assignment: , line:18:12, endln:18:37 |vpiActual: \_ref_obj: (path), line:18:17, endln:18:21 |vpiParent: @@ -516,10 +519,11 @@ design: (unnamed) |vpiFullName:pack::uvm_mem_mam::check_reg::spath |vpiActual: \_typespec_member: (spath), line:4:11, endln:4:16 + |vpiName:path.slices[0].spath |vpiLhs: \_string_var: (pack::uvm_mem_mam::check_reg::p_), line:18:12, endln:18:14 |vpiParent: - \_assign_stmt: , line:18:12, endln:18:37 + \_assignment: , line:18:12, endln:18:37 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::p_) |vpiParent: @@ -615,7 +619,7 @@ design: (unnamed) |vpiVariables: \_class_var: (pack::uvm_mem_mam::check_reg::path), line:17:25, endln:17:29 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::path) |vpiParent: @@ -628,7 +632,7 @@ design: (unnamed) |vpiVariables: \_string_var: (pack::uvm_mem_mam::check_reg::p_), line:18:12, endln:18:14 |vpiParent: - \_assign_stmt: , line:18:12, endln:18:37 + \_assignment: , line:18:12, endln:18:37 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::p_) |vpiParent: @@ -639,13 +643,15 @@ design: (unnamed) |vpiName:p_ |vpiFullName:pack::uvm_mem_mam::check_reg::p_ |vpiStmt: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:16:21, endln:22:6 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_bit_select: (pack::uvm_mem_mam::check_reg::paths), line:17:36, endln:17:37 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiName:paths |vpiFullName:pack::uvm_mem_mam::check_reg::paths |vpiIndex: @@ -657,14 +663,15 @@ design: (unnamed) |vpiLhs: \_class_var: (pack::uvm_mem_mam::check_reg::path), line:17:25, endln:17:29 |vpiStmt: - \_assign_stmt: , line:18:12, endln:18:37 + \_assignment: , line:18:12, endln:18:37 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:16:21, endln:22:6 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (path.slices[0].spath), line:18:17, endln:18:37 |vpiParent: - \_assign_stmt: , line:18:12, endln:18:37 - |vpiName:path.slices[0].spath + \_assignment: , line:18:12, endln:18:37 |vpiActual: \_ref_obj: (path), line:18:17, endln:18:21 |vpiParent: @@ -684,6 +691,7 @@ design: (unnamed) \_hier_path: (path.slices[0].spath), line:18:17, endln:18:37 |vpiName:spath |vpiFullName:pack::uvm_mem_mam::check_reg::spath + |vpiName:path.slices[0].spath |vpiLhs: \_string_var: (pack::uvm_mem_mam::check_reg::p_), line:18:12, endln:18:14 \_function: (pack::uvm_mem_mam::check_reg), line:13:1, endln:13:10 diff --git a/tests/ClockingBlock/ClockingBlock.log b/tests/ClockingBlock/ClockingBlock.log index 585d43445f..3f1f5573b2 100644 --- a/tests/ClockingBlock/ClockingBlock.log +++ b/tests/ClockingBlock/ClockingBlock.log @@ -1061,7 +1061,6 @@ design: (work@top) \_hier_path: (top.to), line:14:29, endln:14:35 |vpiParent: \_clocking_io_decl: (to_Dut), line:14:20, endln:14:35 - |vpiName:top.to |vpiActual: \_ref_obj: (top), line:14:29, endln:14:32 |vpiParent: @@ -1073,6 +1072,7 @@ design: (work@top) \_hier_path: (top.to), line:14:29, endln:14:35 |vpiName:to |vpiFullName:work@top.cb1.to_Dut.to + |vpiName:top.to |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ClockingBlock/dut.sv, line:1:1, endln:17:10 |vpiName:work@top @@ -1228,7 +1228,6 @@ design: (work@top) \_hier_path: (top.to), line:14:29, endln:14:35 |vpiParent: \_clocking_io_decl: (to_Dut), line:14:20, endln:14:35 - |vpiName:top.to |vpiActual: \_ref_obj: (top), line:14:29, endln:14:32 |vpiParent: @@ -1242,6 +1241,7 @@ design: (work@top) \_hier_path: (top.to), line:14:29, endln:14:35 |vpiName:to |vpiFullName:work@top.cb1.to_Dut.to + |vpiName:top.to \_weaklyReferenced: \_function: (work@mailbox::new), line:3:5, endln:4:16 |vpiParent: diff --git a/tests/ClockingDrive/ClockingDrive.log b/tests/ClockingDrive/ClockingDrive.log index d94727a0aa..227d806518 100644 --- a/tests/ClockingDrive/ClockingDrive.log +++ b/tests/ClockingDrive/ClockingDrive.log @@ -529,7 +529,6 @@ design: (work@main) \_hier_path: (cb.v), line:10:4, endln:10:8 |vpiParent: \_assignment: , line:10:4, endln:10:17 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:10:7, endln:10:8 |vpiParent: @@ -540,6 +539,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.v), line:10:4, endln:10:8 |vpiName:v + |vpiName:cb.v |vpiProcess: \_initial: , line:12:1, endln:35:8 |vpiParent: @@ -566,7 +566,6 @@ design: (work@main) \_hier_path: (cb.a), line:13:5, endln:13:9 |vpiParent: \_assignment: , line:13:5, endln:13:14 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:13:8, endln:13:9 |vpiParent: @@ -577,6 +576,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.a), line:13:5, endln:13:9 |vpiName:a + |vpiName:cb.a |vpiStmt: \_assignment: , line:14:5, endln:14:17 |vpiParent: @@ -586,7 +586,6 @@ design: (work@main) \_hier_path: (cb.a), line:14:13, endln:14:17 |vpiParent: \_assignment: , line:14:5, endln:14:17 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:14:13, endln:14:15 |vpiParent: @@ -598,11 +597,11 @@ design: (work@main) \_hier_path: (cb.a), line:14:13, endln:14:17 |vpiName:a |vpiFullName:work@main.a + |vpiName:cb.a |vpiLhs: \_hier_path: (cb.b), line:14:5, endln:14:9 |vpiParent: \_assignment: , line:14:5, endln:14:17 - |vpiName:cb.b |vpiActual: \_ref_obj: (cb), line:14:8, endln:14:9 |vpiParent: @@ -613,6 +612,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.b), line:14:5, endln:14:9 |vpiName:b + |vpiName:cb.b |vpiStmt: \_assignment: , line:17:5, endln:17:26 |vpiParent: @@ -628,7 +628,6 @@ design: (work@main) \_hier_path: (bus.data), line:17:5, endln:17:18 |vpiParent: \_assignment: , line:17:5, endln:17:26 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:17:9, endln:17:13 |vpiParent: @@ -639,6 +638,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:17:5, endln:17:18 |vpiName:data + |vpiName:bus.data |vpiStmt: \_delay_control: , line:18:5, endln:18:8 |vpiParent: @@ -659,7 +659,6 @@ design: (work@main) \_hier_path: (bus.data), line:18:9, endln:18:17 |vpiParent: \_assignment: , line:18:9, endln:18:25 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:18:13, endln:18:17 |vpiParent: @@ -670,6 +669,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:18:9, endln:18:17 |vpiName:data + |vpiName:bus.data |vpiStmt: \_delay_control: , line:19:5, endln:19:8 |vpiParent: @@ -690,7 +690,6 @@ design: (work@main) \_hier_path: (bus.data), line:19:10, endln:19:18 |vpiParent: \_assignment: , line:19:10, endln:19:23 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:19:14, endln:19:18 |vpiParent: @@ -701,6 +700,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:19:10, endln:19:18 |vpiName:data + |vpiName:bus.data |vpiStmt: \_assignment: , line:20:5, endln:20:22 |vpiParent: @@ -718,7 +718,6 @@ design: (work@main) \_hier_path: (bus.data), line:20:5, endln:20:13 |vpiParent: \_assignment: , line:20:5, endln:20:22 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:20:9, endln:20:13 |vpiParent: @@ -729,6 +728,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:20:5, endln:20:13 |vpiName:data + |vpiName:bus.data |vpiDelayControl: \_delay_control: , line:20:17, endln:20:20 |vpiParent: @@ -751,7 +751,6 @@ design: (work@main) \_hier_path: (bus.data), line:22:5, endln:22:13 |vpiParent: \_assignment: , line:22:5, endln:22:21 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:22:9, endln:22:13 |vpiParent: @@ -762,6 +761,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:22:5, endln:22:13 |vpiName:data + |vpiName:bus.data |vpiDelayControl: \_delay_control: , line:22:17, endln:22:19 |vpiParent: @@ -789,7 +789,6 @@ design: (work@main) \_hier_path: (cb.v), line:25:5, endln:25:9 |vpiParent: \_assignment: , line:25:5, endln:25:18 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:25:8, endln:25:9 |vpiParent: @@ -800,6 +799,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.v), line:25:5, endln:25:9 |vpiName:v + |vpiName:cb.v |vpiStmt: \_assignment: , line:26:5, endln:26:22 |vpiParent: @@ -817,7 +817,6 @@ design: (work@main) \_hier_path: (cb.v), line:26:5, endln:26:9 |vpiParent: \_assignment: , line:26:5, endln:26:22 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:26:8, endln:26:9 |vpiParent: @@ -828,6 +827,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.v), line:26:5, endln:26:9 |vpiName:v + |vpiName:cb.v |vpiDelayControl: \_delay_control: , line:26:13, endln:26:16 |vpiParent: @@ -855,7 +855,6 @@ design: (work@main) \_hier_path: (cb.v), line:27:8, endln:27:12 |vpiParent: \_assignment: , line:27:8, endln:27:25 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:27:11, endln:27:12 |vpiParent: @@ -866,6 +865,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.v), line:27:8, endln:27:12 |vpiName:v + |vpiName:cb.v |vpiDelayControl: \_delay_control: , line:27:16, endln:27:19 |vpiParent: @@ -891,7 +891,6 @@ design: (work@main) \_hier_path: (cb.a), line:29:1, endln:29:5 |vpiParent: \_assignment: , line:29:1, endln:29:13 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:29:4, endln:29:5 |vpiParent: @@ -902,6 +901,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.a), line:29:1, endln:29:5 |vpiName:a + |vpiName:cb.a |vpiStmt: \_event_control: , line:30:1, endln:30:5 |vpiParent: @@ -929,7 +929,6 @@ design: (work@main) \_hier_path: (cb.a), line:31:1, endln:31:5 |vpiParent: \_assignment: , line:31:1, endln:31:13 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:31:4, endln:31:5 |vpiParent: @@ -940,6 +939,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.a), line:31:1, endln:31:5 |vpiName:a + |vpiName:cb.a |vpiStmt: \_delay_control: , line:32:1, endln:32:4 |vpiParent: @@ -960,7 +960,6 @@ design: (work@main) \_hier_path: (pe.nibble), line:33:1, endln:33:10 |vpiParent: \_assignment: , line:33:1, endln:33:21 - |vpiName:pe.nibble |vpiActual: \_ref_obj: (pe), line:33:4, endln:33:10 |vpiParent: @@ -971,6 +970,7 @@ design: (work@main) |vpiParent: \_hier_path: (pe.nibble), line:33:1, endln:33:10 |vpiName:nibble + |vpiName:pe.nibble |vpiStmt: \_assignment: , line:34:1, endln:34:21 |vpiParent: @@ -986,7 +986,6 @@ design: (work@main) \_hier_path: (pe.nibble), line:34:1, endln:34:10 |vpiParent: \_assignment: , line:34:1, endln:34:21 - |vpiName:pe.nibble |vpiActual: \_ref_obj: (pe), line:34:4, endln:34:10 |vpiParent: @@ -997,6 +996,7 @@ design: (work@main) |vpiParent: \_hier_path: (pe.nibble), line:34:1, endln:34:10 |vpiName:nibble + |vpiName:pe.nibble |uhdmtopModules: \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ClockingDrive/dut.sv, line:3:1, endln:36:10 |vpiName:work@main @@ -1065,7 +1065,6 @@ design: (work@main) \_hier_path: (cb.v), line:10:4, endln:10:8 |vpiParent: \_assignment: , line:10:4, endln:10:17 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:10:7, endln:10:8 |vpiParent: @@ -1080,6 +1079,7 @@ design: (work@main) |vpiName:v |vpiActual: \_clocking_io_decl: (v), line:7:8, endln:7:9 + |vpiName:cb.v |vpiProcess: \_initial: , line:12:1, endln:35:8 |vpiParent: @@ -1106,7 +1106,6 @@ design: (work@main) \_hier_path: (cb.a), line:13:5, endln:13:9 |vpiParent: \_assignment: , line:13:5, endln:13:14 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:13:8, endln:13:9 |vpiParent: @@ -1119,6 +1118,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.a), line:13:5, endln:13:9 |vpiName:a + |vpiName:cb.a |vpiStmt: \_assignment: , line:14:5, endln:14:17 |vpiParent: @@ -1128,7 +1128,6 @@ design: (work@main) \_hier_path: (cb.a), line:14:13, endln:14:17 |vpiParent: \_assignment: , line:14:5, endln:14:17 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:14:13, endln:14:15 |vpiParent: @@ -1142,11 +1141,11 @@ design: (work@main) \_hier_path: (cb.a), line:14:13, endln:14:17 |vpiName:a |vpiFullName:work@main.a + |vpiName:cb.a |vpiLhs: \_hier_path: (cb.b), line:14:5, endln:14:9 |vpiParent: \_assignment: , line:14:5, endln:14:17 - |vpiName:cb.b |vpiActual: \_ref_obj: (cb), line:14:8, endln:14:9 |vpiParent: @@ -1159,6 +1158,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.b), line:14:5, endln:14:9 |vpiName:b + |vpiName:cb.b |vpiStmt: \_assignment: , line:17:5, endln:17:26 |vpiParent: @@ -1170,7 +1170,6 @@ design: (work@main) \_hier_path: (bus.data), line:17:5, endln:17:18 |vpiParent: \_assignment: , line:17:5, endln:17:26 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:17:9, endln:17:13 |vpiParent: @@ -1181,6 +1180,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:17:5, endln:17:18 |vpiName:data + |vpiName:bus.data |vpiStmt: \_delay_control: , line:18:5, endln:18:8 |vpiParent: @@ -1197,7 +1197,6 @@ design: (work@main) \_hier_path: (bus.data), line:18:9, endln:18:17 |vpiParent: \_assignment: , line:18:9, endln:18:25 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:18:13, endln:18:17 |vpiParent: @@ -1208,6 +1207,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:18:9, endln:18:17 |vpiName:data + |vpiName:bus.data |vpiStmt: \_delay_control: , line:19:5, endln:19:8 |vpiParent: @@ -1224,7 +1224,6 @@ design: (work@main) \_hier_path: (bus.data), line:19:10, endln:19:18 |vpiParent: \_assignment: , line:19:10, endln:19:23 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:19:14, endln:19:18 |vpiParent: @@ -1235,6 +1234,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:19:10, endln:19:18 |vpiName:data + |vpiName:bus.data |vpiStmt: \_assignment: , line:20:5, endln:20:22 |vpiParent: @@ -1252,7 +1252,6 @@ design: (work@main) \_hier_path: (bus.data), line:20:5, endln:20:13 |vpiParent: \_assignment: , line:20:5, endln:20:22 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:20:9, endln:20:13 |vpiParent: @@ -1263,6 +1262,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:20:5, endln:20:13 |vpiName:data + |vpiName:bus.data |vpiDelayControl: \_delay_control: , line:20:17, endln:20:20 |vpiParent: @@ -1285,7 +1285,6 @@ design: (work@main) \_hier_path: (bus.data), line:22:5, endln:22:13 |vpiParent: \_assignment: , line:22:5, endln:22:21 - |vpiName:bus.data |vpiActual: \_ref_obj: (bus), line:22:9, endln:22:13 |vpiParent: @@ -1296,6 +1295,7 @@ design: (work@main) |vpiParent: \_hier_path: (bus.data), line:22:5, endln:22:13 |vpiName:data + |vpiName:bus.data |vpiDelayControl: \_delay_control: , line:22:17, endln:22:19 |vpiParent: @@ -1323,7 +1323,6 @@ design: (work@main) \_hier_path: (cb.v), line:25:5, endln:25:9 |vpiParent: \_assignment: , line:25:5, endln:25:18 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:25:8, endln:25:9 |vpiParent: @@ -1338,6 +1337,7 @@ design: (work@main) |vpiName:v |vpiActual: \_clocking_io_decl: (v), line:7:8, endln:7:9 + |vpiName:cb.v |vpiStmt: \_assignment: , line:26:5, endln:26:22 |vpiParent: @@ -1355,7 +1355,6 @@ design: (work@main) \_hier_path: (cb.v), line:26:5, endln:26:9 |vpiParent: \_assignment: , line:26:5, endln:26:22 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:26:8, endln:26:9 |vpiParent: @@ -1370,6 +1369,7 @@ design: (work@main) |vpiName:v |vpiActual: \_clocking_io_decl: (v), line:7:8, endln:7:9 + |vpiName:cb.v |vpiDelayControl: \_delay_control: , line:26:13, endln:26:16 |vpiParent: @@ -1397,7 +1397,6 @@ design: (work@main) \_hier_path: (cb.v), line:27:8, endln:27:12 |vpiParent: \_assignment: , line:27:8, endln:27:25 - |vpiName:cb.v |vpiActual: \_ref_obj: (cb), line:27:11, endln:27:12 |vpiParent: @@ -1412,6 +1411,7 @@ design: (work@main) |vpiName:v |vpiActual: \_clocking_io_decl: (v), line:7:8, endln:7:9 + |vpiName:cb.v |vpiDelayControl: \_delay_control: , line:27:16, endln:27:19 |vpiParent: @@ -1433,7 +1433,6 @@ design: (work@main) \_hier_path: (cb.a), line:29:1, endln:29:5 |vpiParent: \_assignment: , line:29:1, endln:29:13 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:29:4, endln:29:5 |vpiParent: @@ -1446,6 +1445,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.a), line:29:1, endln:29:5 |vpiName:a + |vpiName:cb.a |vpiStmt: \_event_control: , line:30:1, endln:30:5 |vpiParent: @@ -1469,7 +1469,6 @@ design: (work@main) \_hier_path: (cb.a), line:31:1, endln:31:5 |vpiParent: \_assignment: , line:31:1, endln:31:13 - |vpiName:cb.a |vpiActual: \_ref_obj: (cb), line:31:4, endln:31:5 |vpiParent: @@ -1482,6 +1481,7 @@ design: (work@main) |vpiParent: \_hier_path: (cb.a), line:31:1, endln:31:5 |vpiName:a + |vpiName:cb.a |vpiStmt: \_delay_control: , line:32:1, endln:32:4 |vpiParent: @@ -1498,7 +1498,6 @@ design: (work@main) \_hier_path: (pe.nibble), line:33:1, endln:33:10 |vpiParent: \_assignment: , line:33:1, endln:33:21 - |vpiName:pe.nibble |vpiActual: \_ref_obj: (pe), line:33:4, endln:33:10 |vpiParent: @@ -1509,6 +1508,7 @@ design: (work@main) |vpiParent: \_hier_path: (pe.nibble), line:33:1, endln:33:10 |vpiName:nibble + |vpiName:pe.nibble |vpiStmt: \_assignment: , line:34:1, endln:34:21 |vpiParent: @@ -1520,7 +1520,6 @@ design: (work@main) \_hier_path: (pe.nibble), line:34:1, endln:34:10 |vpiParent: \_assignment: , line:34:1, endln:34:21 - |vpiName:pe.nibble |vpiActual: \_ref_obj: (pe), line:34:4, endln:34:10 |vpiParent: @@ -1531,6 +1530,7 @@ design: (work@main) |vpiParent: \_hier_path: (pe.nibble), line:34:1, endln:34:10 |vpiName:nibble + |vpiName:pe.nibble \_weaklyReferenced: \_clocking_block: (work@main.cb), line:6:1, endln:8:12 |vpiParent: diff --git a/tests/ClockingSntx/ClockingSntx.log b/tests/ClockingSntx/ClockingSntx.log index 78c8fc6d99..b51b7e9e15 100644 --- a/tests/ClockingSntx/ClockingSntx.log +++ b/tests/ClockingSntx/ClockingSntx.log @@ -665,7 +665,6 @@ design: (work@top) \_hier_path: (top.cpu1.state), line:15:17, endln:15:31 |vpiParent: \_clocking_io_decl: (state), line:15:9, endln:15:31 - |vpiName:top.cpu1.state |vpiActual: \_ref_obj: (top), line:15:17, endln:15:20 |vpiParent: @@ -682,6 +681,7 @@ design: (work@top) \_hier_path: (top.cpu1.state), line:15:17, endln:15:31 |vpiName:state |vpiFullName:work@top.cd1.state.state + |vpiName:top.cpu1.state |vpiClockingBlock: \_clocking_block: (work@top.cd2), line:18:2, endln:21:13 |vpiParent: @@ -1118,7 +1118,6 @@ design: (work@top) \_hier_path: (top.cpu1.state), line:15:17, endln:15:31 |vpiParent: \_clocking_io_decl: (state), line:15:9, endln:15:31 - |vpiName:top.cpu1.state |vpiActual: \_ref_obj: (top), line:15:17, endln:15:20 |vpiParent: @@ -1137,6 +1136,7 @@ design: (work@top) \_hier_path: (top.cpu1.state), line:15:17, endln:15:31 |vpiName:state |vpiFullName:work@top.cd1.state.state + |vpiName:top.cpu1.state |vpiClockingBlock: \_clocking_block: (work@top.cd2), line:18:2, endln:21:13 |vpiParent: diff --git a/tests/ClogParam/ClogParam.log b/tests/ClogParam/ClogParam.log index aa9abc7c09..96ba6c3616 100644 --- a/tests/ClogParam/ClogParam.log +++ b/tests/ClogParam/ClogParam.log @@ -434,7 +434,6 @@ design: (work@top) \_hier_path: (Info.x), line:13:37, endln:13:43 |vpiParent: \_param_assign: , line:13:19, endln:13:43 - |vpiName:Info.x |vpiActual: \_ref_obj: (Info), line:13:42, endln:13:43 |vpiParent: @@ -445,6 +444,7 @@ design: (work@top) |vpiParent: \_hier_path: (Info.x), line:13:37, endln:13:43 |vpiName:x + |vpiName:Info.x |vpiLhs: \_parameter: (work@top.NumScrmblBlocks), line:13:19, endln:13:34 |vpiTypedef: @@ -602,7 +602,6 @@ design: (work@top) \_hier_path: (Info.x), line:13:37, endln:13:43 |vpiParent: \_param_assign: , line:13:19, endln:13:43 - |vpiName:Info.x |vpiActual: \_ref_obj: (Info), line:13:42, endln:13:43 |vpiParent: @@ -615,6 +614,7 @@ design: (work@top) |vpiParent: \_hier_path: (Info.x), line:13:37, endln:13:43 |vpiName:x + |vpiName:Info.x |vpiLhs: \_parameter: (work@top.NumScrmblBlocks), line:13:19, endln:13:34 |vpiTypedef: @@ -712,7 +712,6 @@ design: (work@top) |vpiFullName:work@top.Info.x |vpiActual: \_int_typespec: , line:13:15, endln:13:18 - |vpiName:Info.x |vpiActual: \_ref_obj: (Info), line:13:42, endln:13:43 |vpiParent: @@ -725,6 +724,7 @@ design: (work@top) |vpiParent: \_hier_path: (Info.x), line:16:15, endln:16:30 |vpiName:x + |vpiName:Info.x |vpiLhs: \_parameter: (work@top.u_otp_ctrl_ecc_reg.Depth), line:2:19, endln:2:24 |vpiParamAssign: @@ -746,7 +746,6 @@ design: (work@top) |vpiFullName:work@top.u_otp_ctrl_ecc_reg.Info.x |vpiActual: \_int_typespec: , line:13:15, endln:13:18 - |vpiName:Info.x |vpiActual: \_ref_obj: (Info), line:13:42, endln:13:43 |vpiParent: @@ -759,6 +758,7 @@ design: (work@top) |vpiParent: \_hier_path: (Info.x), line:3:31, endln:3:36 |vpiName:x + |vpiName:Info.x |vpiName:$clog2 |vpiLhs: \_parameter: (work@top.u_otp_ctrl_ecc_reg.Aw), line:3:19, endln:3:21 diff --git a/tests/ComplexBitSelect/ComplexBitSelect.log b/tests/ComplexBitSelect/ComplexBitSelect.log index 6c87ee4610..ee3073c9cc 100644 --- a/tests/ComplexBitSelect/ComplexBitSelect.log +++ b/tests/ComplexBitSelect/ComplexBitSelect.log @@ -465,7 +465,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 10 -assign_stmt 1 +assignment 1 bit_select 26 class_defn 8 class_typespec 4 @@ -503,7 +503,7 @@ unsupported_typespec 1 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === array_typespec 10 -assign_stmt 1 +assignment 1 bit_select 33 class_defn 8 class_typespec 4 @@ -1644,7 +1644,7 @@ design: (work@flash_ctrl_info_cfg) |vpiParent: \_module_inst: work@flash_ctrl_info_cfg (work@flash_ctrl_info_cfg), file:${SURELOG_DIR}/tests/ComplexBitSelect/dut.sv, line:12:1, endln:24:10 |vpiForInitStmt: - \_assign_stmt: , line:16:7, endln:16:19 + \_assignment: , line:16:7, endln:16:19 |vpiParent: \_gen_for: |vpiRhs: @@ -1656,7 +1656,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (work@flash_ctrl_info_cfg.i), line:16:14, endln:16:15 |vpiParent: - \_assign_stmt: , line:16:7, endln:16:19 + \_assignment: , line:16:7, endln:16:19 |vpiTypespec: \_ref_typespec: (work@flash_ctrl_info_cfg.i) |vpiParent: diff --git a/tests/ComplexHierPath/ComplexHierPath.log b/tests/ComplexHierPath/ComplexHierPath.log index edc455eaa4..630415ca68 100644 --- a/tests/ComplexHierPath/ComplexHierPath.log +++ b/tests/ComplexHierPath/ComplexHierPath.log @@ -315,7 +315,6 @@ design: (work@genblk_dive_top) \_hier_path: (Z.A.x), line:20:20, endln:20:25 |vpiParent: \_cont_assign: , line:20:16, endln:20:25 - |vpiName:Z.A.x |vpiActual: \_ref_obj: (Z), line:20:20, endln:20:21 |vpiParent: @@ -332,6 +331,7 @@ design: (work@genblk_dive_top) \_hier_path: (Z.A.x), line:20:20, endln:20:25 |vpiName:x |vpiFullName:work@genblk_dive_top.x + |vpiName:Z.A.x |vpiLhs: \_ref_obj: (work@genblk_dive_top.x), line:20:16, endln:20:17 |vpiParent: @@ -437,7 +437,6 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:11:56, endln:11:59 |vpiParent: \_cont_assign: , line:11:56, endln:11:63 - |vpiName:B.x |vpiActual: \_ref_obj: (B), line:11:58, endln:11:59 |vpiParent: @@ -450,6 +449,7 @@ design: (work@genblk_dive_top) |vpiParent: \_hier_path: (B.x), line:11:56, endln:11:59 |vpiName:x + |vpiName:B.x |vpiStmt: \_cont_assign: , line:14:48, endln:14:61 |vpiParent: @@ -458,7 +458,6 @@ design: (work@genblk_dive_top) \_hier_path: (A.B.C.x), line:14:54, endln:14:61 |vpiParent: \_cont_assign: , line:14:48, endln:14:61 - |vpiName:A.B.C.x |vpiActual: \_ref_obj: (A), line:14:54, endln:14:55 |vpiParent: @@ -486,11 +485,11 @@ design: (work@genblk_dive_top) \_hier_path: (A.B.C.x), line:14:54, endln:14:61 |vpiName:x |vpiFullName:work@genblk_dive_top.Z.A.B.x + |vpiName:A.B.C.x |vpiLhs: \_hier_path: (A.x), line:14:48, endln:14:51 |vpiParent: \_cont_assign: , line:14:48, endln:14:61 - |vpiName:A.x |vpiActual: \_ref_obj: (A), line:14:50, endln:14:51 |vpiParent: @@ -503,6 +502,7 @@ design: (work@genblk_dive_top) |vpiParent: \_hier_path: (A.x), line:14:48, endln:14:51 |vpiName:x + |vpiName:A.x |vpiStmt: \_cont_assign: , line:16:40, endln:16:51 |vpiParent: @@ -511,7 +511,6 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:16:48, endln:16:51 |vpiParent: \_cont_assign: , line:16:40, endln:16:51 - |vpiName:B.x |vpiActual: \_ref_obj: (B), line:16:48, endln:16:49 |vpiParent: @@ -525,11 +524,11 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:16:48, endln:16:51 |vpiName:x |vpiFullName:work@genblk_dive_top.Z.A.x + |vpiName:B.x |vpiLhs: \_hier_path: (B.C.x), line:16:40, endln:16:45 |vpiParent: \_cont_assign: , line:16:40, endln:16:51 - |vpiName:B.C.x |vpiActual: \_ref_obj: (B), line:16:42, endln:16:43 |vpiParent: @@ -547,6 +546,7 @@ design: (work@genblk_dive_top) |vpiParent: \_hier_path: (B.C.x), line:16:40, endln:16:45 |vpiName:x + |vpiName:B.C.x |uhdmtopModules: \_module_inst: work@genblk_dive_top (work@genblk_dive_top), file:${SURELOG_DIR}/tests/ComplexHierPath/dut.sv, line:2:1, endln:21:10 |vpiName:work@genblk_dive_top @@ -634,7 +634,6 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:16:48, endln:16:51 |vpiParent: \_cont_assign: , line:16:40, endln:16:51 - |vpiName:B.x |vpiActual: \_ref_obj: (B), line:16:48, endln:16:49 |vpiParent: @@ -650,11 +649,11 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.Z.A.x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39 + |vpiName:B.x |vpiLhs: \_hier_path: (B.C.x), line:16:40, endln:16:45 |vpiParent: \_cont_assign: , line:16:40, endln:16:51 - |vpiName:B.C.x |vpiActual: \_ref_obj: (B), line:16:42, endln:16:43 |vpiParent: @@ -676,6 +675,7 @@ design: (work@genblk_dive_top) |vpiName:x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39 + |vpiName:B.C.x |vpiGenScopeArray: \_gen_scope_array: (work@genblk_dive_top.Z.A.B), line:7:40, endln:15:36 |vpiParent: @@ -709,7 +709,6 @@ design: (work@genblk_dive_top) \_hier_path: (A.B.C.x), line:14:54, endln:14:61 |vpiParent: \_cont_assign: , line:14:48, endln:14:61 - |vpiName:A.B.C.x |vpiActual: \_ref_obj: (A), line:14:54, endln:14:55 |vpiParent: @@ -739,11 +738,11 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.Z.A.B.x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47 + |vpiName:A.B.C.x |vpiLhs: \_hier_path: (A.x), line:14:48, endln:14:51 |vpiParent: \_cont_assign: , line:14:48, endln:14:61 - |vpiName:A.x |vpiActual: \_ref_obj: (A), line:14:50, endln:14:51 |vpiParent: @@ -758,6 +757,7 @@ design: (work@genblk_dive_top) |vpiName:x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47 + |vpiName:A.x |vpiGenScopeArray: \_gen_scope_array: (work@genblk_dive_top.Z.A.B.C), line:9:48, endln:13:44 |vpiParent: @@ -806,7 +806,6 @@ design: (work@genblk_dive_top) \_hier_path: (A.B.C.x), line:12:58, endln:12:65 |vpiParent: \_cont_assign: , line:12:54, endln:12:55 - |vpiName:A.B.C.x |vpiActual: \_ref_obj: (A), line:12:58, endln:12:59 |vpiParent: @@ -836,6 +835,7 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.Z.A.B.C.x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.C.x), line:10:54, endln:10:55 + |vpiName:A.B.C.x |vpiLhs: \_logic_net: (work@genblk_dive_top.Z.A.B.C.z), line:12:54, endln:12:55 |vpiContAssign: @@ -854,7 +854,6 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:11:56, endln:11:59 |vpiParent: \_cont_assign: , line:11:56, endln:11:63 - |vpiName:B.x |vpiActual: \_ref_obj: (B), line:11:58, endln:11:59 |vpiParent: @@ -869,6 +868,7 @@ design: (work@genblk_dive_top) |vpiName:x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.C.x), line:10:54, endln:10:55 + |vpiName:B.x |vpiContAssign: \_cont_assign: , line:20:16, endln:20:25 |vpiParent: @@ -877,7 +877,6 @@ design: (work@genblk_dive_top) \_hier_path: (Z.A.x), line:20:20, endln:20:25 |vpiParent: \_cont_assign: , line:20:16, endln:20:25 - |vpiName:Z.A.x |vpiActual: \_ref_obj: (Z), line:20:20, endln:20:21 |vpiParent: @@ -900,6 +899,7 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.x |vpiActual: \_logic_net: (work@genblk_dive_top.x), line:2:36, endln:2:37 + |vpiName:Z.A.x |vpiLhs: \_ref_obj: (work@genblk_dive_top.x), line:20:16, endln:20:17 |vpiParent: @@ -947,7 +947,6 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:16:48, endln:16:51 |vpiParent: \_cont_assign: , line:16:40, endln:16:51 - |vpiName:B.x |vpiActual: \_ref_obj: (B), line:16:48, endln:16:49 |vpiParent: @@ -963,11 +962,11 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.Z.A.x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39 + |vpiName:B.x |vpiLhs: \_hier_path: (B.C.x), line:16:40, endln:16:45 |vpiParent: \_cont_assign: , line:16:40, endln:16:51 - |vpiName:B.C.x |vpiActual: \_ref_obj: (B), line:16:42, endln:16:43 |vpiParent: @@ -989,6 +988,7 @@ design: (work@genblk_dive_top) |vpiName:x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39 + |vpiName:B.C.x |vpiGenScopeArray: \_gen_scope_array: (work@genblk_dive_top.Z.A.B), line:7:40, endln:15:36 |vpiParent: @@ -1010,7 +1010,6 @@ design: (work@genblk_dive_top) \_hier_path: (A.B.C.x), line:14:54, endln:14:61 |vpiParent: \_cont_assign: , line:14:48, endln:14:61 - |vpiName:A.B.C.x |vpiActual: \_ref_obj: (A), line:14:54, endln:14:55 |vpiParent: @@ -1040,11 +1039,11 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.Z.A.B.x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47 + |vpiName:A.B.C.x |vpiLhs: \_hier_path: (A.x), line:14:48, endln:14:51 |vpiParent: \_cont_assign: , line:14:48, endln:14:61 - |vpiName:A.x |vpiActual: \_ref_obj: (A), line:14:50, endln:14:51 |vpiParent: @@ -1059,6 +1058,7 @@ design: (work@genblk_dive_top) |vpiName:x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47 + |vpiName:A.x |vpiGenScopeArray: \_gen_scope_array: (work@genblk_dive_top.Z.A.B.C), line:9:48, endln:13:44 |vpiParent: @@ -1083,7 +1083,6 @@ design: (work@genblk_dive_top) \_hier_path: (A.B.C.x), line:12:58, endln:12:65 |vpiParent: \_cont_assign: , line:12:54, endln:12:55 - |vpiName:A.B.C.x |vpiActual: \_ref_obj: (A), line:12:58, endln:12:59 |vpiParent: @@ -1113,6 +1112,7 @@ design: (work@genblk_dive_top) |vpiFullName:work@genblk_dive_top.Z.A.B.C.x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.C.x), line:10:54, endln:10:55 + |vpiName:A.B.C.x |vpiLhs: \_logic_net: (work@genblk_dive_top.Z.A.B.C.z), line:12:54, endln:12:55 |vpiContAssign: @@ -1125,7 +1125,6 @@ design: (work@genblk_dive_top) \_hier_path: (B.x), line:11:56, endln:11:59 |vpiParent: \_cont_assign: , line:11:56, endln:11:63 - |vpiName:B.x |vpiActual: \_ref_obj: (B), line:11:58, endln:11:59 |vpiParent: @@ -1140,6 +1139,7 @@ design: (work@genblk_dive_top) |vpiName:x |vpiActual: \_logic_net: (work@genblk_dive_top.Z.A.B.C.x), line:10:54, endln:10:55 + |vpiName:B.x \_gen_scope_array: (work@genblk_dive_top.Z), line:4:24, endln:18:20 |vpiParent: \_module_inst: work@genblk_dive_top (work@genblk_dive_top), file:${SURELOG_DIR}/tests/ComplexHierPath/dut.sv, line:2:1, endln:21:10 diff --git a/tests/ConcatOrder/ConcatOrder.log b/tests/ConcatOrder/ConcatOrder.log index b279c5c0d0..817ad1a2b2 100644 --- a/tests/ConcatOrder/ConcatOrder.log +++ b/tests/ConcatOrder/ConcatOrder.log @@ -1403,7 +1403,6 @@ design: (work@testbench) \_hier_path: (proc_param_lp.cce_ucode), line:44:47, endln:44:70 |vpiParent: \_param_assign: , line:44:18, endln:44:70 - |vpiName:proc_param_lp.cce_ucode |vpiActual: \_ref_obj: (proc_param_lp), line:44:61, endln:44:70 |vpiParent: @@ -1414,6 +1413,7 @@ design: (work@testbench) |vpiParent: \_hier_path: (proc_param_lp.cce_ucode), line:44:47, endln:44:70 |vpiName:cce_ucode + |vpiName:proc_param_lp.cce_ucode |vpiLhs: \_parameter: (work@testbench.cce_ucode_p), line:44:18, endln:44:29 |vpiTypedef: diff --git a/tests/ConstExpand/ConstExpand.log b/tests/ConstExpand/ConstExpand.log index 3f1e2ef60c..b00a12b7ae 100644 --- a/tests/ConstExpand/ConstExpand.log +++ b/tests/ConstExpand/ConstExpand.log @@ -346,7 +346,6 @@ design: (work@top) \_hier_path: (operation_i.operand_a[0+:32]), line:11:17, endln:11:45 |vpiParent: \_assignment: , line:11:13, endln:11:45 - |vpiName:operation_i.operand_a[0+:32] |vpiActual: \_ref_obj: (operation_i), line:11:17, endln:11:28 |vpiParent: @@ -372,6 +371,7 @@ design: (work@top) |vpiSize:64 |UINT:32 |vpiConstType:9 + |vpiName:operation_i.operand_a[0+:32] |vpiLhs: \_ref_obj: (work@top.o), line:11:13, endln:11:14 |vpiParent: @@ -519,7 +519,6 @@ design: (work@top) \_hier_path: (operation_i.operand_a[0+:32]), line:11:17, endln:11:45 |vpiParent: \_assignment: , line:11:13, endln:11:45 - |vpiName:operation_i.operand_a[0+:32] |vpiActual: \_ref_obj: (operation_i), line:11:17, endln:11:28 |vpiParent: @@ -541,6 +540,7 @@ design: (work@top) \_constant: , line:11:39, endln:11:40 |vpiWidthExpr: \_constant: , line:11:42, endln:11:44 + |vpiName:operation_i.operand_a[0+:32] |vpiLhs: \_ref_obj: (work@top.o), line:11:13, endln:11:14 |vpiParent: diff --git a/tests/ConstantRange/ConstantRange.log b/tests/ConstantRange/ConstantRange.log index 327e51c5ae..76205fbf06 100644 --- a/tests/ConstantRange/ConstantRange.log +++ b/tests/ConstantRange/ConstantRange.log @@ -233,7 +233,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 4. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 20 constant 139 @@ -260,7 +260,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 20 constant 139 @@ -423,7 +423,7 @@ design: (work@dut) |vpiParent: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ConstantRange/dut.sv, line:6:1, endln:21:10 |vpiForInitStmt: - \_assign_stmt: , line:11:6, endln:11:18 + \_assignment: , line:11:6, endln:11:18 |vpiParent: \_gen_for: |vpiRhs: @@ -435,7 +435,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.k), line:11:13, endln:11:14 |vpiParent: - \_assign_stmt: , line:11:6, endln:11:18 + \_assignment: , line:11:6, endln:11:18 |vpiTypespec: \_ref_typespec: (work@dut.k) |vpiParent: diff --git a/tests/CovMacro/CovMacro.log b/tests/CovMacro/CovMacro.log index f0f3445fe9..f0a382eda2 100644 --- a/tests/CovMacro/CovMacro.log +++ b/tests/CovMacro/CovMacro.log @@ -1332,8 +1332,6 @@ design: (work@top) \_hier_path: (work@top.$root.top), line:12:42, endln:12:51 |vpiParent: \_sys_func_call: ($coverage_control), line:12:13, endln:12:52 - |vpiName:$root.top - |vpiFullName:work@top.$root.top |vpiActual: \_ref_obj: ($root), line:12:48, endln:12:51 |vpiParent: @@ -1344,6 +1342,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@top.$root.top), line:12:42, endln:12:51 |vpiName:top + |vpiName:$root.top + |vpiFullName:work@top.$root.top |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:12:9, endln:12:10 @@ -1442,8 +1442,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit1), line:14:42, endln:14:57 |vpiParent: \_sys_func_call: ($coverage_control), line:14:13, endln:14:58 - |vpiName:$root.top.unit1 - |vpiFullName:work@top.$root.top.unit1 |vpiActual: \_ref_obj: ($root), line:14:48, endln:14:51 |vpiParent: @@ -1459,6 +1457,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@top.$root.top.unit1), line:14:42, endln:14:57 |vpiName:unit1 + |vpiName:$root.top.unit1 + |vpiFullName:work@top.$root.top.unit1 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:14:9, endln:14:10 @@ -1506,8 +1506,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit2), line:15:43, endln:15:58 |vpiParent: \_sys_func_call: ($coverage_control), line:15:13, endln:15:59 - |vpiName:$root.top.unit2 - |vpiFullName:work@top.$root.top.unit2 |vpiActual: \_ref_obj: ($root), line:15:49, endln:15:52 |vpiParent: @@ -1523,6 +1521,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@top.$root.top.unit2), line:15:43, endln:15:58 |vpiName:unit2 + |vpiName:$root.top.unit2 + |vpiFullName:work@top.$root.top.unit2 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:15:9, endln:15:10 @@ -1656,8 +1656,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit1), line:18:35, endln:18:50 |vpiParent: \_sys_func_call: ($coverage_get), line:18:13, endln:18:51 - |vpiName:$root.top.unit1 - |vpiFullName:work@top.$root.top.unit1 |vpiActual: \_ref_obj: ($root), line:18:41, endln:18:44 |vpiParent: @@ -1673,6 +1671,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@top.$root.top.unit1), line:18:35, endln:18:50 |vpiName:unit1 + |vpiName:$root.top.unit1 + |vpiFullName:work@top.$root.top.unit1 |vpiName:$coverage_get |vpiLhs: \_ref_obj: (work@top.r), line:18:9, endln:18:10 @@ -1876,8 +1876,6 @@ design: (work@top) \_hier_path: (work@top.$root.top), line:12:42, endln:12:51 |vpiParent: \_sys_func_call: ($coverage_control), line:12:13, endln:12:52 - |vpiName:$root.top - |vpiFullName:work@top.$root.top |vpiActual: \_ref_obj: ($root), line:12:48, endln:12:51 |vpiParent: @@ -1890,6 +1888,8 @@ design: (work@top) |vpiName:top |vpiActual: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:5:1, endln:25:10 + |vpiName:$root.top + |vpiFullName:work@top.$root.top |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:12:9, endln:12:10 @@ -1946,8 +1946,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit1), line:14:42, endln:14:57 |vpiParent: \_sys_func_call: ($coverage_control), line:14:13, endln:14:58 - |vpiName:$root.top.unit1 - |vpiFullName:work@top.$root.top.unit1 |vpiActual: \_ref_obj: ($root), line:14:48, endln:14:51 |vpiParent: @@ -1967,6 +1965,8 @@ design: (work@top) |vpiName:unit1 |vpiActual: \_module_inst: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 + |vpiName:$root.top.unit1 + |vpiFullName:work@top.$root.top.unit1 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:14:9, endln:14:10 @@ -1996,8 +1996,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit2), line:15:43, endln:15:58 |vpiParent: \_sys_func_call: ($coverage_control), line:15:13, endln:15:59 - |vpiName:$root.top.unit2 - |vpiFullName:work@top.$root.top.unit2 |vpiActual: \_ref_obj: ($root), line:15:49, endln:15:52 |vpiParent: @@ -2017,6 +2015,8 @@ design: (work@top) |vpiName:unit2 |vpiActual: \_module_inst: work@DUT (work@top.unit2), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:9:5, endln:9:17 + |vpiName:$root.top.unit2 + |vpiFullName:work@top.$root.top.unit2 |vpiName:$coverage_control |vpiLhs: \_ref_obj: (work@top.i), line:15:9, endln:15:10 @@ -2096,8 +2096,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.unit1), line:18:35, endln:18:50 |vpiParent: \_sys_func_call: ($coverage_get), line:18:13, endln:18:51 - |vpiName:$root.top.unit1 - |vpiFullName:work@top.$root.top.unit1 |vpiActual: \_ref_obj: ($root), line:18:41, endln:18:44 |vpiParent: @@ -2117,6 +2115,8 @@ design: (work@top) |vpiName:unit1 |vpiActual: \_module_inst: work@DUT (work@top.unit1), file:${SURELOG_DIR}/tests/CovMacro/dut.sv, line:8:5, endln:8:17 + |vpiName:$root.top.unit1 + |vpiFullName:work@top.$root.top.unit1 |vpiName:$coverage_get |vpiLhs: \_ref_obj: (work@top.r), line:18:9, endln:18:10 diff --git a/tests/CrossFunc/CrossFunc.log b/tests/CrossFunc/CrossFunc.log index 4ab9ca628b..ef8f23baae 100644 --- a/tests/CrossFunc/CrossFunc.log +++ b/tests/CrossFunc/CrossFunc.log @@ -347,7 +347,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 constant 21 design 1 for_stmt 2 @@ -370,7 +370,7 @@ unsupported_typespec 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 +assignment 4 constant 21 design 1 for_stmt 4 @@ -443,13 +443,13 @@ design: (work@mod_m) \_function: (work@mod_m.myFunc1), line:9:3, endln:12:14 |vpiFullName:work@mod_m.myFunc1 |vpiForInitStmt: - \_assign_stmt: , line:10:9, endln:10:18 + \_assignment: , line:10:9, endln:10:18 |vpiParent: \_for_stmt: (work@mod_m.myFunc1), line:10:4, endln:10:7 |vpiRhs: \_constant: , line:10:17, endln:10:18 |vpiParent: - \_assign_stmt: , line:10:9, endln:10:18 + \_assignment: , line:10:9, endln:10:18 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -457,7 +457,7 @@ design: (work@mod_m) |vpiLhs: \_int_var: (work@mod_m.myFunc1.i), line:10:13, endln:10:14 |vpiParent: - \_assign_stmt: , line:10:9, endln:10:18 + \_assignment: , line:10:9, endln:10:18 |vpiTypespec: \_ref_typespec: (work@mod_m.myFunc1.i) |vpiParent: @@ -570,13 +570,13 @@ design: (work@mod_m) \_function: (work@mod_m.myFunc2), line:17:3, endln:20:14 |vpiFullName:work@mod_m.myFunc2 |vpiForInitStmt: - \_assign_stmt: , line:18:9, endln:18:27 + \_assignment: , line:18:9, endln:18:27 |vpiParent: \_for_stmt: (work@mod_m.myFunc2), line:18:4, endln:18:7 |vpiRhs: \_constant: , line:18:26, endln:18:27 |vpiParent: - \_assign_stmt: , line:18:9, endln:18:27 + \_assignment: , line:18:9, endln:18:27 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -584,7 +584,7 @@ design: (work@mod_m) |vpiLhs: \_logic_var: (work@mod_m.myFunc2.i), line:18:22, endln:18:23 |vpiParent: - \_assign_stmt: , line:18:9, endln:18:27 + \_assignment: , line:18:9, endln:18:27 |vpiTypespec: \_ref_typespec: (work@mod_m.myFunc2.i) |vpiParent: @@ -804,7 +804,7 @@ design: (work@mod_m) \_function: (work@mod_m.myFunc1), line:9:3, endln:12:14 |vpiFullName:work@mod_m.myFunc1 |vpiForInitStmt: - \_assign_stmt: , line:10:9, endln:10:18 + \_assignment: , line:10:9, endln:10:18 |vpiParent: \_for_stmt: (work@mod_m.myFunc1), line:10:4, endln:10:7 |vpiRhs: @@ -812,7 +812,7 @@ design: (work@mod_m) |vpiLhs: \_int_var: (work@mod_m.myFunc1.i), line:10:13, endln:10:14 |vpiParent: - \_assign_stmt: , line:10:9, endln:10:18 + \_assignment: , line:10:9, endln:10:18 |vpiTypespec: \_ref_typespec: (work@mod_m.myFunc1.i) |vpiParent: @@ -915,7 +915,7 @@ design: (work@mod_m) \_function: (work@mod_m.myFunc2), line:17:3, endln:20:14 |vpiFullName:work@mod_m.myFunc2 |vpiForInitStmt: - \_assign_stmt: , line:18:9, endln:18:27 + \_assignment: , line:18:9, endln:18:27 |vpiParent: \_for_stmt: (work@mod_m.myFunc2), line:18:4, endln:18:7 |vpiRhs: @@ -923,7 +923,7 @@ design: (work@mod_m) |vpiLhs: \_logic_var: (work@mod_m.myFunc2.i), line:18:22, endln:18:23 |vpiParent: - \_assign_stmt: , line:18:9, endln:18:27 + \_assignment: , line:18:9, endln:18:27 |vpiTypespec: \_ref_typespec: (work@mod_m.myFunc2.i) |vpiParent: diff --git a/tests/DefaultPatternInt/DefaultPatternInt.log b/tests/DefaultPatternInt/DefaultPatternInt.log index 39c9d80898..95a684eca1 100644 --- a/tests/DefaultPatternInt/DefaultPatternInt.log +++ b/tests/DefaultPatternInt/DefaultPatternInt.log @@ -388,8 +388,7 @@ AST_DEBUG_END array_expr 7 array_typespec 12 array_var 1 -assign_stmt 1 -assignment 1 +assignment 2 begin 4 bit_select 8 constant 124 @@ -422,8 +421,7 @@ tagged_pattern 6 array_expr 7 array_typespec 12 array_var 1 -assign_stmt 2 -assignment 2 +assignment 4 begin 5 bit_select 10 constant 124 @@ -1037,13 +1035,13 @@ design: (work@main) \_function: (work@top.ASSIGN_VADDR), line:11:1, endln:15:12 |vpiFullName:work@top.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:12:10, endln:12:19 + \_assignment: , line:12:10, endln:12:19 |vpiParent: \_for_stmt: (work@top.ASSIGN_VADDR), line:12:5, endln:12:8 |vpiRhs: \_constant: , line:12:18, endln:12:19 |vpiParent: - \_assign_stmt: , line:12:10, endln:12:19 + \_assignment: , line:12:10, endln:12:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1051,7 +1049,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@top.ASSIGN_VADDR.i), line:12:14, endln:12:15 |vpiParent: - \_assign_stmt: , line:12:10, endln:12:19 + \_assignment: , line:12:10, endln:12:19 |vpiTypespec: \_ref_typespec: (work@top.ASSIGN_VADDR.i) |vpiParent: @@ -1473,7 +1471,7 @@ design: (work@main) \_function: (work@main.top1.ASSIGN_VADDR), line:11:1, endln:15:12 |vpiFullName:work@main.top1.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:12:10, endln:12:19 + \_assignment: , line:12:10, endln:12:19 |vpiParent: \_for_stmt: (work@main.top1.ASSIGN_VADDR), line:12:5, endln:12:8 |vpiRhs: @@ -1481,7 +1479,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@main.top1.ASSIGN_VADDR.i), line:12:14, endln:12:15 |vpiParent: - \_assign_stmt: , line:12:10, endln:12:19 + \_assignment: , line:12:10, endln:12:19 |vpiTypespec: \_ref_typespec: (work@main.top1.ASSIGN_VADDR.i) |vpiParent: diff --git a/tests/DefaultPatternModule/DefaultPatternModule.log b/tests/DefaultPatternModule/DefaultPatternModule.log index 728d0a8dd6..1ded5183d3 100644 --- a/tests/DefaultPatternModule/DefaultPatternModule.log +++ b/tests/DefaultPatternModule/DefaultPatternModule.log @@ -380,8 +380,7 @@ AST_DEBUG_END array_expr 1 array_typespec 7 array_var 1 -assign_stmt 1 -assignment 1 +assignment 2 begin 4 bit_select 8 constant 71 @@ -412,8 +411,7 @@ tagged_pattern 2 array_expr 1 array_typespec 7 array_var 1 -assign_stmt 2 -assignment 2 +assignment 4 begin 5 bit_select 10 constant 71 @@ -701,13 +699,13 @@ design: (work@main) \_function: (work@top.ASSIGN_VADDR), line:8:1, endln:12:12 |vpiFullName:work@top.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:9:10, endln:9:19 + \_assignment: , line:9:10, endln:9:19 |vpiParent: \_for_stmt: (work@top.ASSIGN_VADDR), line:9:5, endln:9:8 |vpiRhs: \_constant: , line:9:18, endln:9:19 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:19 + \_assignment: , line:9:10, endln:9:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -715,7 +713,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@top.ASSIGN_VADDR.i), line:9:14, endln:9:15 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:19 + \_assignment: , line:9:10, endln:9:19 |vpiTypespec: \_ref_typespec: (work@top.ASSIGN_VADDR.i) |vpiParent: @@ -1109,7 +1107,7 @@ design: (work@main) \_function: (work@main.top1.ASSIGN_VADDR), line:8:1, endln:12:12 |vpiFullName:work@main.top1.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:9:10, endln:9:19 + \_assignment: , line:9:10, endln:9:19 |vpiParent: \_for_stmt: (work@main.top1.ASSIGN_VADDR), line:9:5, endln:9:8 |vpiRhs: @@ -1117,7 +1115,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@main.top1.ASSIGN_VADDR.i), line:9:14, endln:9:15 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:19 + \_assignment: , line:9:10, endln:9:19 |vpiTypespec: \_ref_typespec: (work@main.top1.ASSIGN_VADDR.i) |vpiParent: diff --git a/tests/DoWhile/DoWhile.log b/tests/DoWhile/DoWhile.log index 4369f97152..cbcfc1cb4c 100644 --- a/tests/DoWhile/DoWhile.log +++ b/tests/DoWhile/DoWhile.log @@ -435,7 +435,6 @@ design: (unnamed) \_hier_path: (m_type_names.next), line:10:14, endln:10:36 |vpiParent: \_do_while: , line:6:3, endln:10:36 - |vpiName:m_type_names.next |vpiActual: \_ref_obj: (m_type_names), line:10:14, endln:10:26 |vpiParent: @@ -452,6 +451,7 @@ design: (unnamed) |vpiName:key |vpiFullName:toto::uvm_default_factory::print::m_type_names.next::key |vpiName:next + |vpiName:m_type_names.next |vpiStmt: \_begin: (toto::uvm_default_factory::print), line:6:6, endln:10:7 |vpiParent: @@ -470,7 +470,6 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiParent: \_operation: , line:7:11, endln:7:49 - |vpiName:m_sync[i].m_state |vpiActual: \_bit_select: (m_sync[i]), line:7:11, endln:7:17 |vpiParent: @@ -489,6 +488,7 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiName:m_state |vpiFullName:toto::uvm_default_factory::print::m_state + |vpiName:m_sync[i].m_state |vpiOperand: \_ref_obj: (toto::uvm_default_factory::print::UVM_PHASE_SYNCING), line:7:32, endln:7:49 |vpiParent: @@ -577,7 +577,6 @@ design: (unnamed) \_hier_path: (m_type_names.next), line:10:14, endln:10:36 |vpiParent: \_do_while: , line:6:3, endln:10:36 - |vpiName:m_type_names.next |vpiActual: \_ref_obj: (m_type_names), line:10:14, endln:10:26 |vpiParent: @@ -594,6 +593,7 @@ design: (unnamed) |vpiName:key |vpiFullName:toto::uvm_default_factory::print::m_type_names.next::key |vpiName:next + |vpiName:m_type_names.next |vpiStmt: \_begin: (toto::uvm_default_factory::print), line:6:6, endln:10:7 |vpiParent: @@ -612,7 +612,6 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiParent: \_operation: , line:7:11, endln:7:49 - |vpiName:m_sync[i].m_state |vpiActual: \_bit_select: (m_sync[i]), line:7:11, endln:7:17 |vpiParent: @@ -631,6 +630,7 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiName:m_state |vpiFullName:toto::uvm_default_factory::print::m_state + |vpiName:m_sync[i].m_state |vpiOperand: \_ref_obj: (toto::uvm_default_factory::print::UVM_PHASE_SYNCING), line:7:32, endln:7:49 |vpiParent: @@ -1126,7 +1126,6 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiParent: \_operation: , line:7:11, endln:7:49 - |vpiName:m_sync[i].m_state |vpiActual: \_bit_select: (m_sync[i]), line:7:11, endln:7:17 |vpiParent: @@ -1145,6 +1144,7 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiName:m_state |vpiFullName:toto::uvm_default_factory::print::m_state + |vpiName:m_sync[i].m_state |vpiOperand: \_ref_obj: (toto::uvm_default_factory::print::UVM_PHASE_SYNCING), line:7:32, endln:7:49 |vpiParent: @@ -1160,7 +1160,6 @@ design: (unnamed) \_hier_path: (m_type_names.next), line:10:14, endln:10:36 |vpiParent: \_do_while: , line:6:3, endln:10:36 - |vpiName:m_type_names.next |vpiActual: \_ref_obj: (m_type_names), line:10:14, endln:10:26 |vpiParent: @@ -1177,6 +1176,7 @@ design: (unnamed) |vpiName:key |vpiFullName:toto::uvm_default_factory::print::m_type_names.next::key |vpiName:next + |vpiName:m_type_names.next |vpiStmt: \_begin: (toto::uvm_default_factory::print), line:6:6, endln:10:7 \_function: (toto::uvm_default_factory::print), line:4:1, endln:12:12 @@ -1218,7 +1218,6 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiParent: \_operation: , line:7:11, endln:7:49 - |vpiName:m_sync[i].m_state |vpiActual: \_bit_select: (m_sync[i]), line:7:11, endln:7:17 |vpiParent: @@ -1237,6 +1236,7 @@ design: (unnamed) \_hier_path: (m_sync[i].m_state), line:7:11, endln:7:28 |vpiName:m_state |vpiFullName:toto::uvm_default_factory::print::m_state + |vpiName:m_sync[i].m_state |vpiOperand: \_ref_obj: (toto::uvm_default_factory::print::UVM_PHASE_SYNCING), line:7:32, endln:7:49 |vpiParent: @@ -1252,7 +1252,6 @@ design: (unnamed) \_hier_path: (m_type_names.next), line:10:14, endln:10:36 |vpiParent: \_do_while: , line:6:3, endln:10:36 - |vpiName:m_type_names.next |vpiActual: \_ref_obj: (m_type_names), line:10:14, endln:10:26 |vpiParent: @@ -1269,6 +1268,7 @@ design: (unnamed) |vpiName:key |vpiFullName:toto::uvm_default_factory::print::m_type_names.next::key |vpiName:next + |vpiName:m_type_names.next |vpiStmt: \_begin: (toto::uvm_default_factory::print), line:6:6, endln:10:7 \_function: (toto::uvm_default_factory::print), line:4:1, endln:12:12 diff --git a/tests/DollarRoot/DollarRoot.log b/tests/DollarRoot/DollarRoot.log index 847483f068..121151c68b 100644 --- a/tests/DollarRoot/DollarRoot.log +++ b/tests/DollarRoot/DollarRoot.log @@ -6733,8 +6733,7 @@ AST_DEBUG_END always 9 array_typespec 15 array_var 5 -assign_stmt 53 -assignment 65 +assignment 118 begin 84 bit_select 42 bit_typespec 7 @@ -6798,8 +6797,7 @@ wait_stmt 1 always 18 array_typespec 15 array_var 5 -assign_stmt 71 -assignment 130 +assignment 201 begin 168 bit_select 84 bit_typespec 7 @@ -8055,7 +8053,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:227:49, endln:227:57 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_address), line:227:7, endln:227:58 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:227:49, endln:227:52 |vpiParent: @@ -8069,6 +8066,7 @@ design: (work@top) \_hier_path: (cmd.addr), line:227:49, endln:227:57 |vpiName:addr |vpiFullName:work@test_program.configure_and_push_command_to_master_0.addr + |vpiName:cmd.addr |vpiName:$root.tb.dut.master_0.set_command_address |vpiStmt: \_func_call: ($root.tb.dut.master_0.set_command_burst_count), line:228:7, endln:228:68 @@ -8078,7 +8076,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:228:53, endln:228:67 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_burst_count), line:228:7, endln:228:68 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:228:53, endln:228:56 |vpiParent: @@ -8092,6 +8089,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:228:53, endln:228:67 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_command_to_master_0.burstcount + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_0.set_command_burst_count |vpiStmt: \_func_call: ($root.tb.dut.master_0.set_command_burst_size), line:229:7, endln:229:67 @@ -8101,7 +8099,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:229:52, endln:229:66 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_burst_size), line:229:7, endln:229:67 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:229:52, endln:229:55 |vpiParent: @@ -8115,6 +8112,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:229:52, endln:229:66 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_command_to_master_0.burstcount + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_0.set_command_burst_size |vpiStmt: \_func_call: ($root.tb.dut.master_0.set_command_init_latency), line:230:7, endln:230:68 @@ -8124,7 +8122,6 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:230:54, endln:230:67 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_init_latency), line:230:7, endln:230:68 - |vpiName:cmd.cmd_delay |vpiActual: \_ref_obj: (cmd), line:230:54, endln:230:57 |vpiParent: @@ -8138,6 +8135,7 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:230:54, endln:230:67 |vpiName:cmd_delay |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd_delay + |vpiName:cmd.cmd_delay |vpiName:$root.tb.dut.master_0.set_command_init_latency |vpiStmt: \_if_else: , line:232:7, endln:242:10 @@ -8152,7 +8150,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:232:11, endln:232:20 |vpiParent: \_operation: , line:232:11, endln:232:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:232:11, endln:232:14 |vpiParent: @@ -8166,6 +8163,7 @@ design: (work@top) \_hier_path: (cmd.trans), line:232:11, endln:232:20 |vpiName:trans |vpiFullName:work@test_program.configure_and_push_command_to_master_0.trans + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.WRITE), line:232:24, endln:232:29 |vpiParent: @@ -8198,13 +8196,13 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_0), line:232:31, endln:239:10 |vpiFullName:work@test_program.configure_and_push_command_to_master_0 |vpiForInitStmt: - \_assign_stmt: , line:234:15, endln:234:24 + \_assignment: , line:234:15, endln:234:24 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_command_to_master_0), line:234:10, endln:234:13 |vpiRhs: \_constant: , line:234:23, endln:234:24 |vpiParent: - \_assign_stmt: , line:234:15, endln:234:24 + \_assignment: , line:234:15, endln:234:24 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -8212,7 +8210,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 |vpiParent: - \_assign_stmt: , line:234:15, endln:234:24 + \_assignment: , line:234:15, endln:234:24 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_command_to_master_0.i) |vpiParent: @@ -8253,7 +8251,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:234:30, endln:234:44 |vpiParent: \_operation: , line:234:26, endln:234:44 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:234:30, endln:234:33 |vpiParent: @@ -8267,6 +8264,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:234:30, endln:234:44 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_command_to_master_0.burstcount + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_command_to_master_0), line:234:51, endln:238:13 |vpiParent: @@ -8280,7 +8278,6 @@ design: (work@top) \_hier_path: (cmd.data[i]), line:235:52, endln:235:63 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_data), line:235:13, endln:235:67 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:235:52, endln:235:55 |vpiParent: @@ -8302,6 +8299,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 + |vpiName:cmd.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.i), line:235:65, endln:235:66 |vpiParent: @@ -8319,7 +8317,6 @@ design: (work@top) \_hier_path: (cmd.byteenable[i]), line:236:59, endln:236:76 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_byte_enable), line:236:13, endln:236:80 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:236:59, endln:236:62 |vpiParent: @@ -8341,6 +8338,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 + |vpiName:cmd.byteenable[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.i), line:236:78, endln:236:79 |vpiParent: @@ -8358,7 +8356,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[i]), line:237:52, endln:237:69 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_idle), line:237:13, endln:237:73 - |vpiName:cmd.data_idles[i] |vpiActual: \_ref_obj: (cmd), line:237:52, endln:237:55 |vpiParent: @@ -8380,6 +8377,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd.data_idles[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 + |vpiName:cmd.data_idles[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.i), line:237:71, endln:237:72 |vpiParent: @@ -8415,7 +8413,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[0]), line:241:49, endln:241:66 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_idle), line:241:10, endln:241:70 - |vpiName:cmd.data_idles[0] |vpiActual: \_ref_obj: (cmd), line:241:49, endln:241:52 |vpiParent: @@ -8437,6 +8434,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:cmd.data_idles[0] |vpiArgument: \_constant: , line:241:68, endln:241:69 |vpiParent: @@ -8508,8 +8506,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size), line:271:27, endln:271:74 |vpiParent: \_assignment: , line:271:7, endln:271:74 - |vpiName:$root.tb.dut.master_0.get_response_burst_size - |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size |vpiActual: \_ref_obj: ($root), line:271:33, endln:271:35 |vpiParent: @@ -8535,11 +8531,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size), line:271:27, endln:271:74 |vpiName:get_response_burst_size + |vpiName:$root.tb.dut.master_0.get_response_burst_size + |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size |vpiLhs: \_hier_path: (rsp.burstcount), line:271:7, endln:271:21 |vpiParent: \_assignment: , line:271:7, endln:271:74 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:271:11, endln:271:21 |vpiParent: @@ -8552,19 +8549,20 @@ design: (work@top) |vpiParent: \_hier_path: (rsp.burstcount), line:271:7, endln:271:21 |vpiName:burstcount + |vpiName:rsp.burstcount |vpiStmt: \_for_stmt: (work@test_program.get_read_response_from_master_0), line:272:7, endln:272:10 |vpiParent: \_begin: (work@test_program.get_read_response_from_master_0), line:270:7, endln:270:44 |vpiFullName:work@test_program.get_read_response_from_master_0 |vpiForInitStmt: - \_assign_stmt: , line:272:12, endln:272:21 + \_assignment: , line:272:12, endln:272:21 |vpiParent: \_for_stmt: (work@test_program.get_read_response_from_master_0), line:272:7, endln:272:10 |vpiRhs: \_constant: , line:272:20, endln:272:21 |vpiParent: - \_assign_stmt: , line:272:12, endln:272:21 + \_assignment: , line:272:12, endln:272:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -8572,7 +8570,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_read_response_from_master_0.i), line:272:16, endln:272:17 |vpiParent: - \_assign_stmt: , line:272:12, endln:272:21 + \_assignment: , line:272:12, endln:272:21 |vpiTypespec: \_ref_typespec: (work@test_program.get_read_response_from_master_0.i) |vpiParent: @@ -8613,7 +8611,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:272:27, endln:272:41 |vpiParent: \_operation: , line:272:23, endln:272:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:272:27, endln:272:30 |vpiParent: @@ -8627,6 +8624,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:272:27, endln:272:41 |vpiName:burstcount |vpiFullName:work@test_program.get_read_response_from_master_0.burstcount + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_0), line:272:48, endln:274:10 |vpiParent: @@ -8642,8 +8640,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data), line:273:27, endln:273:69 |vpiParent: \_assignment: , line:273:10, endln:273:69 - |vpiName:$root.tb.dut.master_0.get_response_data - |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data |vpiActual: \_ref_obj: ($root), line:273:33, endln:273:35 |vpiParent: @@ -8669,11 +8665,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data), line:273:27, endln:273:69 |vpiName:get_response_data + |vpiName:$root.tb.dut.master_0.get_response_data + |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data |vpiLhs: \_hier_path: (rsp.data[i]), line:273:10, endln:273:21 |vpiParent: \_assignment: , line:273:10, endln:273:69 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:273:14, endln:273:18 |vpiParent: @@ -8695,6 +8692,7 @@ design: (work@top) |vpiFullName:work@test_program.get_read_response_from_master_0.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.get_read_response_from_master_0.i), line:272:16, endln:272:17 + |vpiName:rsp.data[i] |vpiStmt: \_return_stmt: , line:276:7, endln:276:13 |vpiParent: @@ -8764,8 +8762,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count), line:314:33, endln:314:79 |vpiParent: \_assignment: , line:314:7, endln:314:79 - |vpiName:$root.tb.dut.slave_0.get_command_burst_count - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count |vpiActual: \_ref_obj: ($root), line:314:39, endln:314:41 |vpiParent: @@ -8791,11 +8787,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count), line:314:33, endln:314:79 |vpiName:get_command_burst_count + |vpiName:$root.tb.dut.slave_0.get_command_burst_count + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count |vpiLhs: \_hier_path: (cmd.burstcount), line:314:7, endln:314:21 |vpiParent: \_assignment: , line:314:7, endln:314:79 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:314:11, endln:314:21 |vpiParent: @@ -8808,6 +8805,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.burstcount), line:314:7, endln:314:21 |vpiName:burstcount + |vpiName:cmd.burstcount |vpiStmt: \_assignment: , line:315:7, endln:315:75 |vpiParent: @@ -8818,8 +8816,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address), line:315:33, endln:315:75 |vpiParent: \_assignment: , line:315:7, endln:315:75 - |vpiName:$root.tb.dut.slave_0.get_command_address - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address |vpiActual: \_ref_obj: ($root), line:315:39, endln:315:41 |vpiParent: @@ -8845,11 +8841,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address), line:315:33, endln:315:75 |vpiName:get_command_address + |vpiName:$root.tb.dut.slave_0.get_command_address + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address |vpiLhs: \_hier_path: (cmd.addr), line:315:7, endln:315:15 |vpiParent: \_assignment: , line:315:7, endln:315:75 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:315:11, endln:315:15 |vpiParent: @@ -8862,6 +8859,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.addr), line:315:7, endln:315:15 |vpiName:addr + |vpiName:cmd.addr |vpiStmt: \_if_else: , line:317:7, endln:325:10 |vpiParent: @@ -8875,8 +8873,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request), line:317:11, endln:317:53 |vpiParent: \_operation: , line:317:11, endln:317:66 - |vpiName:$root.tb.dut.slave_0.get_command_request - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request |vpiActual: \_ref_obj: ($root), line:317:17, endln:317:19 |vpiParent: @@ -8902,6 +8898,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request), line:317:11, endln:317:53 |vpiName:get_command_request + |vpiName:$root.tb.dut.slave_0.get_command_request + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request |vpiOperand: \_ref_obj: (work@test_program.get_command_from_slave_0.REQ_WRITE), line:317:57, endln:317:66 |vpiParent: @@ -8933,7 +8931,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:318:10, endln:318:19 |vpiParent: \_assignment: , line:318:10, endln:318:27 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:318:14, endln:318:19 |vpiParent: @@ -8946,19 +8943,20 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.trans), line:318:10, endln:318:19 |vpiName:trans + |vpiName:cmd.trans |vpiStmt: \_for_stmt: (work@test_program.get_command_from_slave_0), line:319:10, endln:319:13 |vpiParent: \_begin: (work@test_program.get_command_from_slave_0), line:317:68, endln:323:10 |vpiFullName:work@test_program.get_command_from_slave_0 |vpiForInitStmt: - \_assign_stmt: , line:319:14, endln:319:23 + \_assignment: , line:319:14, endln:319:23 |vpiParent: \_for_stmt: (work@test_program.get_command_from_slave_0), line:319:10, endln:319:13 |vpiRhs: \_constant: , line:319:22, endln:319:23 |vpiParent: - \_assign_stmt: , line:319:14, endln:319:23 + \_assignment: , line:319:14, endln:319:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -8966,7 +8964,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_command_from_slave_0.i), line:319:18, endln:319:19 |vpiParent: - \_assign_stmt: , line:319:14, endln:319:23 + \_assignment: , line:319:14, endln:319:23 |vpiTypespec: \_ref_typespec: (work@test_program.get_command_from_slave_0.i) |vpiParent: @@ -9007,7 +9005,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:319:29, endln:319:43 |vpiParent: \_operation: , line:319:25, endln:319:43 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:319:29, endln:319:32 |vpiParent: @@ -9021,6 +9018,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:319:29, endln:319:43 |vpiName:burstcount |vpiFullName:work@test_program.get_command_from_slave_0.burstcount + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.get_command_from_slave_0), line:319:50, endln:322:13 |vpiParent: @@ -9036,8 +9034,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data), line:320:32, endln:320:72 |vpiParent: \_assignment: , line:320:13, endln:320:72 - |vpiName:$root.tb.dut.slave_0.get_command_data - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data |vpiActual: \_ref_obj: ($root), line:320:38, endln:320:40 |vpiParent: @@ -9063,11 +9059,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data), line:320:32, endln:320:72 |vpiName:get_command_data + |vpiName:$root.tb.dut.slave_0.get_command_data + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data |vpiLhs: \_hier_path: (cmd.data[i]), line:320:13, endln:320:24 |vpiParent: \_assignment: , line:320:13, endln:320:72 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:320:17, endln:320:21 |vpiParent: @@ -9089,6 +9086,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_0.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_0.i), line:319:18, endln:319:19 + |vpiName:cmd.data[i] |vpiStmt: \_assignment: , line:321:13, endln:321:79 |vpiParent: @@ -9099,8 +9097,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable), line:321:32, endln:321:79 |vpiParent: \_assignment: , line:321:13, endln:321:79 - |vpiName:$root.tb.dut.slave_0.get_command_byte_enable - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable |vpiActual: \_ref_obj: ($root), line:321:38, endln:321:40 |vpiParent: @@ -9126,11 +9122,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable), line:321:32, endln:321:79 |vpiName:get_command_byte_enable + |vpiName:$root.tb.dut.slave_0.get_command_byte_enable + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable |vpiLhs: \_hier_path: (cmd.byteenable[i]), line:321:13, endln:321:30 |vpiParent: \_assignment: , line:321:13, endln:321:79 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:321:17, endln:321:27 |vpiParent: @@ -9152,6 +9149,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_0.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_0.i), line:319:18, endln:319:19 + |vpiName:cmd.byteenable[i] |vpiElseStmt: \_begin: (work@test_program.get_command_from_slave_0), line:323:16, endln:325:10 |vpiParent: @@ -9175,7 +9173,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:324:10, endln:324:19 |vpiParent: \_assignment: , line:324:10, endln:324:26 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:324:14, endln:324:19 |vpiParent: @@ -9188,6 +9185,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.trans), line:324:10, endln:324:19 |vpiName:trans + |vpiName:cmd.trans |vpiStmt: \_return_stmt: , line:327:7, endln:327:13 |vpiParent: @@ -9265,7 +9263,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:347:52, endln:347:66 |vpiParent: \_func_call: ($root.tb.dut.slave_0.set_response_burst_size), line:347:7, endln:347:67 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:347:52, endln:347:55 |vpiParent: @@ -9279,6 +9276,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:347:52, endln:347:66 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.burstcount + |vpiName:rsp.burstcount |vpiName:$root.tb.dut.slave_0.set_response_burst_size |vpiStmt: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_0), line:348:7, endln:348:10 @@ -9286,13 +9284,13 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_response_to_slave_0), line:346:7, endln:346:59 |vpiFullName:work@test_program.configure_and_push_response_to_slave_0 |vpiForInitStmt: - \_assign_stmt: , line:348:12, endln:348:21 + \_assignment: , line:348:12, endln:348:21 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_0), line:348:7, endln:348:10 |vpiRhs: \_constant: , line:348:20, endln:348:21 |vpiParent: - \_assign_stmt: , line:348:12, endln:348:21 + \_assignment: , line:348:12, endln:348:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -9300,7 +9298,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 |vpiParent: - \_assign_stmt: , line:348:12, endln:348:21 + \_assignment: , line:348:12, endln:348:21 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_response_to_slave_0.i) |vpiParent: @@ -9341,7 +9339,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:348:27, endln:348:41 |vpiParent: \_operation: , line:348:23, endln:348:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:348:27, endln:348:30 |vpiParent: @@ -9355,6 +9352,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:348:27, endln:348:41 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.burstcount + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_response_to_slave_0), line:348:48, endln:359:10 |vpiParent: @@ -9368,7 +9366,6 @@ design: (work@top) \_hier_path: (rsp.data[i]), line:349:49, endln:349:60 |vpiParent: \_func_call: ($root.tb.dut.slave_0.set_response_data), line:349:10, endln:349:64 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:349:49, endln:349:52 |vpiParent: @@ -9390,6 +9387,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.i), line:349:62, endln:349:63 |vpiParent: @@ -9442,7 +9440,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:352:55, endln:352:69 |vpiParent: \_operation: , line:352:55, endln:352:99 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:352:55, endln:352:58 |vpiParent: @@ -9464,6 +9461,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.pending_read_cycles_slave_0), line:352:72, endln:352:99 |vpiParent: @@ -9491,7 +9489,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:353:37, endln:353:51 |vpiParent: \_assignment: , line:353:13, endln:353:51 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:353:37, endln:353:40 |vpiParent: @@ -9513,6 +9510,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiLhs: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.read_response_latency), line:353:13, endln:353:34 |vpiParent: @@ -9534,7 +9532,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:355:55, endln:355:69 |vpiParent: \_func_call: ($root.tb.dut.slave_0.set_response_latency), line:355:13, endln:355:73 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:355:55, endln:355:58 |vpiParent: @@ -9556,6 +9553,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.i), line:355:71, endln:355:72 |vpiParent: @@ -9580,7 +9578,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:356:37, endln:356:51 |vpiParent: \_operation: , line:356:37, endln:356:75 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:356:37, endln:356:40 |vpiParent: @@ -9602,6 +9599,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.read_response_latency), line:356:54, endln:356:75 |vpiParent: @@ -9664,7 +9662,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:361:91, endln:361:105 |vpiParent: \_operation: , line:361:37, endln:361:105 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:361:91, endln:361:94 |vpiParent: @@ -9678,6 +9675,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:361:91, endln:361:105 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.burstcount + |vpiName:rsp.burstcount |vpiOperand: \_constant: , line:361:108, endln:361:109 |vpiParent: @@ -9730,7 +9728,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:370:49, endln:370:57 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_address), line:370:7, endln:370:58 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:370:49, endln:370:52 |vpiParent: @@ -9744,6 +9741,7 @@ design: (work@top) \_hier_path: (cmd.addr), line:370:49, endln:370:57 |vpiName:addr |vpiFullName:work@test_program.configure_and_push_command_to_master_1.addr + |vpiName:cmd.addr |vpiName:$root.tb.dut.master_1.set_command_address |vpiStmt: \_func_call: ($root.tb.dut.master_1.set_command_burst_count), line:371:7, endln:371:68 @@ -9753,7 +9751,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:371:53, endln:371:67 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_burst_count), line:371:7, endln:371:68 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:371:53, endln:371:56 |vpiParent: @@ -9767,6 +9764,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:371:53, endln:371:67 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_command_to_master_1.burstcount + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_1.set_command_burst_count |vpiStmt: \_func_call: ($root.tb.dut.master_1.set_command_burst_size), line:372:7, endln:372:67 @@ -9776,7 +9774,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:372:52, endln:372:66 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_burst_size), line:372:7, endln:372:67 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:372:52, endln:372:55 |vpiParent: @@ -9790,6 +9787,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:372:52, endln:372:66 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_command_to_master_1.burstcount + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_1.set_command_burst_size |vpiStmt: \_func_call: ($root.tb.dut.master_1.set_command_init_latency), line:373:7, endln:373:68 @@ -9799,7 +9797,6 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:373:54, endln:373:67 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_init_latency), line:373:7, endln:373:68 - |vpiName:cmd.cmd_delay |vpiActual: \_ref_obj: (cmd), line:373:54, endln:373:57 |vpiParent: @@ -9813,6 +9810,7 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:373:54, endln:373:67 |vpiName:cmd_delay |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd_delay + |vpiName:cmd.cmd_delay |vpiName:$root.tb.dut.master_1.set_command_init_latency |vpiStmt: \_if_else: , line:375:7, endln:385:10 @@ -9827,7 +9825,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:375:11, endln:375:20 |vpiParent: \_operation: , line:375:11, endln:375:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:375:11, endln:375:14 |vpiParent: @@ -9841,6 +9838,7 @@ design: (work@top) \_hier_path: (cmd.trans), line:375:11, endln:375:20 |vpiName:trans |vpiFullName:work@test_program.configure_and_push_command_to_master_1.trans + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.WRITE), line:375:24, endln:375:29 |vpiParent: @@ -9873,13 +9871,13 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_1), line:375:31, endln:382:10 |vpiFullName:work@test_program.configure_and_push_command_to_master_1 |vpiForInitStmt: - \_assign_stmt: , line:377:15, endln:377:24 + \_assignment: , line:377:15, endln:377:24 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_command_to_master_1), line:377:10, endln:377:13 |vpiRhs: \_constant: , line:377:23, endln:377:24 |vpiParent: - \_assign_stmt: , line:377:15, endln:377:24 + \_assignment: , line:377:15, endln:377:24 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -9887,7 +9885,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 |vpiParent: - \_assign_stmt: , line:377:15, endln:377:24 + \_assignment: , line:377:15, endln:377:24 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_command_to_master_1.i) |vpiParent: @@ -9928,7 +9926,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:377:30, endln:377:44 |vpiParent: \_operation: , line:377:26, endln:377:44 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:377:30, endln:377:33 |vpiParent: @@ -9942,6 +9939,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:377:30, endln:377:44 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_command_to_master_1.burstcount + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_command_to_master_1), line:377:51, endln:381:13 |vpiParent: @@ -9955,7 +9953,6 @@ design: (work@top) \_hier_path: (cmd.data[i]), line:378:52, endln:378:63 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_data), line:378:13, endln:378:67 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:378:52, endln:378:55 |vpiParent: @@ -9977,6 +9974,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 + |vpiName:cmd.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.i), line:378:65, endln:378:66 |vpiParent: @@ -9994,7 +9992,6 @@ design: (work@top) \_hier_path: (cmd.byteenable[i]), line:379:59, endln:379:76 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_byte_enable), line:379:13, endln:379:80 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:379:59, endln:379:62 |vpiParent: @@ -10016,6 +10013,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 + |vpiName:cmd.byteenable[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.i), line:379:78, endln:379:79 |vpiParent: @@ -10033,7 +10031,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[i]), line:380:52, endln:380:69 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_idle), line:380:13, endln:380:73 - |vpiName:cmd.data_idles[i] |vpiActual: \_ref_obj: (cmd), line:380:52, endln:380:55 |vpiParent: @@ -10055,6 +10052,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd.data_idles[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 + |vpiName:cmd.data_idles[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.i), line:380:71, endln:380:72 |vpiParent: @@ -10090,7 +10088,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[0]), line:384:49, endln:384:66 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_idle), line:384:10, endln:384:70 - |vpiName:cmd.data_idles[0] |vpiActual: \_ref_obj: (cmd), line:384:49, endln:384:52 |vpiParent: @@ -10112,6 +10109,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:cmd.data_idles[0] |vpiArgument: \_constant: , line:384:68, endln:384:69 |vpiParent: @@ -10183,8 +10181,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size), line:414:27, endln:414:74 |vpiParent: \_assignment: , line:414:7, endln:414:74 - |vpiName:$root.tb.dut.master_1.get_response_burst_size - |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size |vpiActual: \_ref_obj: ($root), line:414:33, endln:414:35 |vpiParent: @@ -10210,11 +10206,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size), line:414:27, endln:414:74 |vpiName:get_response_burst_size + |vpiName:$root.tb.dut.master_1.get_response_burst_size + |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size |vpiLhs: \_hier_path: (rsp.burstcount), line:414:7, endln:414:21 |vpiParent: \_assignment: , line:414:7, endln:414:74 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:414:11, endln:414:21 |vpiParent: @@ -10227,19 +10224,20 @@ design: (work@top) |vpiParent: \_hier_path: (rsp.burstcount), line:414:7, endln:414:21 |vpiName:burstcount + |vpiName:rsp.burstcount |vpiStmt: \_for_stmt: (work@test_program.get_read_response_from_master_1), line:415:7, endln:415:10 |vpiParent: \_begin: (work@test_program.get_read_response_from_master_1), line:413:7, endln:413:44 |vpiFullName:work@test_program.get_read_response_from_master_1 |vpiForInitStmt: - \_assign_stmt: , line:415:12, endln:415:21 + \_assignment: , line:415:12, endln:415:21 |vpiParent: \_for_stmt: (work@test_program.get_read_response_from_master_1), line:415:7, endln:415:10 |vpiRhs: \_constant: , line:415:20, endln:415:21 |vpiParent: - \_assign_stmt: , line:415:12, endln:415:21 + \_assignment: , line:415:12, endln:415:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -10247,7 +10245,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_read_response_from_master_1.i), line:415:16, endln:415:17 |vpiParent: - \_assign_stmt: , line:415:12, endln:415:21 + \_assignment: , line:415:12, endln:415:21 |vpiTypespec: \_ref_typespec: (work@test_program.get_read_response_from_master_1.i) |vpiParent: @@ -10288,7 +10286,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:415:27, endln:415:41 |vpiParent: \_operation: , line:415:23, endln:415:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:415:27, endln:415:30 |vpiParent: @@ -10302,6 +10299,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:415:27, endln:415:41 |vpiName:burstcount |vpiFullName:work@test_program.get_read_response_from_master_1.burstcount + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_1), line:415:48, endln:417:10 |vpiParent: @@ -10317,8 +10315,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data), line:416:27, endln:416:69 |vpiParent: \_assignment: , line:416:10, endln:416:69 - |vpiName:$root.tb.dut.master_1.get_response_data - |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data |vpiActual: \_ref_obj: ($root), line:416:33, endln:416:35 |vpiParent: @@ -10344,11 +10340,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data), line:416:27, endln:416:69 |vpiName:get_response_data + |vpiName:$root.tb.dut.master_1.get_response_data + |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data |vpiLhs: \_hier_path: (rsp.data[i]), line:416:10, endln:416:21 |vpiParent: \_assignment: , line:416:10, endln:416:69 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:416:14, endln:416:18 |vpiParent: @@ -10370,6 +10367,7 @@ design: (work@top) |vpiFullName:work@test_program.get_read_response_from_master_1.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.get_read_response_from_master_1.i), line:415:16, endln:415:17 + |vpiName:rsp.data[i] |vpiStmt: \_return_stmt: , line:419:7, endln:419:13 |vpiParent: @@ -10439,8 +10437,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count), line:457:33, endln:457:79 |vpiParent: \_assignment: , line:457:7, endln:457:79 - |vpiName:$root.tb.dut.slave_1.get_command_burst_count - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count |vpiActual: \_ref_obj: ($root), line:457:39, endln:457:41 |vpiParent: @@ -10466,11 +10462,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count), line:457:33, endln:457:79 |vpiName:get_command_burst_count + |vpiName:$root.tb.dut.slave_1.get_command_burst_count + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count |vpiLhs: \_hier_path: (cmd.burstcount), line:457:7, endln:457:21 |vpiParent: \_assignment: , line:457:7, endln:457:79 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:457:11, endln:457:21 |vpiParent: @@ -10483,6 +10480,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.burstcount), line:457:7, endln:457:21 |vpiName:burstcount + |vpiName:cmd.burstcount |vpiStmt: \_assignment: , line:458:7, endln:458:75 |vpiParent: @@ -10493,8 +10491,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address), line:458:33, endln:458:75 |vpiParent: \_assignment: , line:458:7, endln:458:75 - |vpiName:$root.tb.dut.slave_1.get_command_address - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address |vpiActual: \_ref_obj: ($root), line:458:39, endln:458:41 |vpiParent: @@ -10520,11 +10516,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address), line:458:33, endln:458:75 |vpiName:get_command_address + |vpiName:$root.tb.dut.slave_1.get_command_address + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address |vpiLhs: \_hier_path: (cmd.addr), line:458:7, endln:458:15 |vpiParent: \_assignment: , line:458:7, endln:458:75 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:458:11, endln:458:15 |vpiParent: @@ -10537,6 +10534,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.addr), line:458:7, endln:458:15 |vpiName:addr + |vpiName:cmd.addr |vpiStmt: \_if_else: , line:460:7, endln:468:10 |vpiParent: @@ -10550,8 +10548,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request), line:460:11, endln:460:53 |vpiParent: \_operation: , line:460:11, endln:460:66 - |vpiName:$root.tb.dut.slave_1.get_command_request - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request |vpiActual: \_ref_obj: ($root), line:460:17, endln:460:19 |vpiParent: @@ -10577,6 +10573,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request), line:460:11, endln:460:53 |vpiName:get_command_request + |vpiName:$root.tb.dut.slave_1.get_command_request + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request |vpiOperand: \_ref_obj: (work@test_program.get_command_from_slave_1.REQ_WRITE), line:460:57, endln:460:66 |vpiParent: @@ -10608,7 +10606,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:461:10, endln:461:19 |vpiParent: \_assignment: , line:461:10, endln:461:27 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:461:14, endln:461:19 |vpiParent: @@ -10621,19 +10618,20 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.trans), line:461:10, endln:461:19 |vpiName:trans + |vpiName:cmd.trans |vpiStmt: \_for_stmt: (work@test_program.get_command_from_slave_1), line:462:10, endln:462:13 |vpiParent: \_begin: (work@test_program.get_command_from_slave_1), line:460:68, endln:466:10 |vpiFullName:work@test_program.get_command_from_slave_1 |vpiForInitStmt: - \_assign_stmt: , line:462:14, endln:462:23 + \_assignment: , line:462:14, endln:462:23 |vpiParent: \_for_stmt: (work@test_program.get_command_from_slave_1), line:462:10, endln:462:13 |vpiRhs: \_constant: , line:462:22, endln:462:23 |vpiParent: - \_assign_stmt: , line:462:14, endln:462:23 + \_assignment: , line:462:14, endln:462:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -10641,7 +10639,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_command_from_slave_1.i), line:462:18, endln:462:19 |vpiParent: - \_assign_stmt: , line:462:14, endln:462:23 + \_assignment: , line:462:14, endln:462:23 |vpiTypespec: \_ref_typespec: (work@test_program.get_command_from_slave_1.i) |vpiParent: @@ -10682,7 +10680,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:462:29, endln:462:43 |vpiParent: \_operation: , line:462:25, endln:462:43 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:462:29, endln:462:32 |vpiParent: @@ -10696,6 +10693,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:462:29, endln:462:43 |vpiName:burstcount |vpiFullName:work@test_program.get_command_from_slave_1.burstcount + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.get_command_from_slave_1), line:462:50, endln:465:13 |vpiParent: @@ -10711,8 +10709,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data), line:463:32, endln:463:72 |vpiParent: \_assignment: , line:463:13, endln:463:72 - |vpiName:$root.tb.dut.slave_1.get_command_data - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data |vpiActual: \_ref_obj: ($root), line:463:38, endln:463:40 |vpiParent: @@ -10738,11 +10734,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data), line:463:32, endln:463:72 |vpiName:get_command_data + |vpiName:$root.tb.dut.slave_1.get_command_data + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data |vpiLhs: \_hier_path: (cmd.data[i]), line:463:13, endln:463:24 |vpiParent: \_assignment: , line:463:13, endln:463:72 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:463:17, endln:463:21 |vpiParent: @@ -10764,6 +10761,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_1.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_1.i), line:462:18, endln:462:19 + |vpiName:cmd.data[i] |vpiStmt: \_assignment: , line:464:13, endln:464:79 |vpiParent: @@ -10774,8 +10772,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable), line:464:32, endln:464:79 |vpiParent: \_assignment: , line:464:13, endln:464:79 - |vpiName:$root.tb.dut.slave_1.get_command_byte_enable - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable |vpiActual: \_ref_obj: ($root), line:464:38, endln:464:40 |vpiParent: @@ -10801,11 +10797,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable), line:464:32, endln:464:79 |vpiName:get_command_byte_enable + |vpiName:$root.tb.dut.slave_1.get_command_byte_enable + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable |vpiLhs: \_hier_path: (cmd.byteenable[i]), line:464:13, endln:464:30 |vpiParent: \_assignment: , line:464:13, endln:464:79 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:464:17, endln:464:27 |vpiParent: @@ -10827,6 +10824,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_1.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_1.i), line:462:18, endln:462:19 + |vpiName:cmd.byteenable[i] |vpiElseStmt: \_begin: (work@test_program.get_command_from_slave_1), line:466:16, endln:468:10 |vpiParent: @@ -10850,7 +10848,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:467:10, endln:467:19 |vpiParent: \_assignment: , line:467:10, endln:467:26 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:467:14, endln:467:19 |vpiParent: @@ -10863,6 +10860,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.trans), line:467:10, endln:467:19 |vpiName:trans + |vpiName:cmd.trans |vpiStmt: \_return_stmt: , line:470:7, endln:470:13 |vpiParent: @@ -10940,7 +10938,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:490:52, endln:490:66 |vpiParent: \_func_call: ($root.tb.dut.slave_1.set_response_burst_size), line:490:7, endln:490:67 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:490:52, endln:490:55 |vpiParent: @@ -10954,6 +10951,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:490:52, endln:490:66 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.burstcount + |vpiName:rsp.burstcount |vpiName:$root.tb.dut.slave_1.set_response_burst_size |vpiStmt: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_1), line:491:7, endln:491:10 @@ -10961,13 +10959,13 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_response_to_slave_1), line:489:7, endln:489:59 |vpiFullName:work@test_program.configure_and_push_response_to_slave_1 |vpiForInitStmt: - \_assign_stmt: , line:491:12, endln:491:21 + \_assignment: , line:491:12, endln:491:21 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_1), line:491:7, endln:491:10 |vpiRhs: \_constant: , line:491:20, endln:491:21 |vpiParent: - \_assign_stmt: , line:491:12, endln:491:21 + \_assignment: , line:491:12, endln:491:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -10975,7 +10973,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 |vpiParent: - \_assign_stmt: , line:491:12, endln:491:21 + \_assignment: , line:491:12, endln:491:21 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_response_to_slave_1.i) |vpiParent: @@ -11016,7 +11014,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:491:27, endln:491:41 |vpiParent: \_operation: , line:491:23, endln:491:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:491:27, endln:491:30 |vpiParent: @@ -11030,6 +11027,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:491:27, endln:491:41 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.burstcount + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_response_to_slave_1), line:491:48, endln:502:10 |vpiParent: @@ -11043,7 +11041,6 @@ design: (work@top) \_hier_path: (rsp.data[i]), line:492:49, endln:492:60 |vpiParent: \_func_call: ($root.tb.dut.slave_1.set_response_data), line:492:10, endln:492:64 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:492:49, endln:492:52 |vpiParent: @@ -11065,6 +11062,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.i), line:492:62, endln:492:63 |vpiParent: @@ -11117,7 +11115,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:495:55, endln:495:69 |vpiParent: \_operation: , line:495:55, endln:495:99 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:495:55, endln:495:58 |vpiParent: @@ -11139,6 +11136,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.pending_read_cycles_slave_1), line:495:72, endln:495:99 |vpiParent: @@ -11166,7 +11164,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:496:37, endln:496:51 |vpiParent: \_assignment: , line:496:13, endln:496:51 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:496:37, endln:496:40 |vpiParent: @@ -11188,6 +11185,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiLhs: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.read_response_latency), line:496:13, endln:496:34 |vpiParent: @@ -11209,7 +11207,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:498:55, endln:498:69 |vpiParent: \_func_call: ($root.tb.dut.slave_1.set_response_latency), line:498:13, endln:498:73 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:498:55, endln:498:58 |vpiParent: @@ -11231,6 +11228,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.i), line:498:71, endln:498:72 |vpiParent: @@ -11255,7 +11253,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:499:37, endln:499:51 |vpiParent: \_operation: , line:499:37, endln:499:75 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:499:37, endln:499:40 |vpiParent: @@ -11277,6 +11274,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.read_response_latency), line:499:54, endln:499:75 |vpiParent: @@ -11339,7 +11337,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:504:91, endln:504:105 |vpiParent: \_operation: , line:504:37, endln:504:105 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:504:91, endln:504:94 |vpiParent: @@ -11353,6 +11350,7 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:504:91, endln:504:105 |vpiName:burstcount |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.burstcount + |vpiName:rsp.burstcount |vpiOperand: \_constant: , line:504:108, endln:504:109 |vpiParent: @@ -11506,13 +11504,13 @@ design: (work@top) \_begin: (work@test_program.master_send_commands), line:551:7, endln:551:32 |vpiFullName:work@test_program.master_send_commands |vpiForInitStmt: - \_assign_stmt: , line:554:12, endln:554:21 + \_assignment: , line:554:12, endln:554:21 |vpiParent: \_for_stmt: (work@test_program.master_send_commands), line:554:7, endln:554:10 |vpiRhs: \_constant: , line:554:20, endln:554:21 |vpiParent: - \_assign_stmt: , line:554:12, endln:554:21 + \_assignment: , line:554:12, endln:554:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -11520,7 +11518,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.master_send_commands.i), line:554:16, endln:554:17 |vpiParent: - \_assign_stmt: , line:554:12, endln:554:21 + \_assignment: , line:554:12, endln:554:21 |vpiTypespec: \_ref_typespec: (work@test_program.master_send_commands.i) |vpiParent: @@ -11870,7 +11868,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:579:10, endln:579:24 |vpiParent: \_assignment: , line:579:10, endln:579:61 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:579:14, endln:579:24 |vpiParent: @@ -11883,6 +11880,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.burstcount), line:579:10, endln:579:24 |vpiName:burstcount + |vpiName:cmd.burstcount |vpiElseStmt: \_begin: (work@test_program.create_command), line:580:16, endln:582:10 |vpiParent: @@ -11904,7 +11902,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:581:10, endln:581:24 |vpiParent: \_assignment: , line:581:10, endln:581:40 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:581:14, endln:581:24 |vpiParent: @@ -11917,6 +11914,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.burstcount), line:581:10, endln:581:24 |vpiName:burstcount + |vpiName:cmd.burstcount |vpiStmt: \_assignment: , line:584:7, endln:584:41 |vpiParent: @@ -11935,7 +11933,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:584:7, endln:584:16 |vpiParent: \_assignment: , line:584:7, endln:584:41 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:584:11, endln:584:16 |vpiParent: @@ -11950,6 +11947,7 @@ design: (work@top) |vpiName:trans |vpiActual: \_io_decl: (trans), line:571:22, endln:571:27 + |vpiName:cmd.trans |vpiStmt: \_assignment: , line:585:7, endln:585:77 |vpiParent: @@ -11975,7 +11973,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:585:7, endln:585:15 |vpiParent: \_assignment: , line:585:7, endln:585:77 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:585:11, endln:585:15 |vpiParent: @@ -11988,6 +11985,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.addr), line:585:7, endln:585:15 |vpiName:addr + |vpiName:cmd.addr |vpiStmt: \_assignment: , line:586:7, endln:586:71 |vpiParent: @@ -12017,7 +12015,6 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:586:7, endln:586:20 |vpiParent: \_assignment: , line:586:7, endln:586:71 - |vpiName:cmd.cmd_delay |vpiActual: \_ref_obj: (cmd), line:586:11, endln:586:20 |vpiParent: @@ -12030,6 +12027,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.cmd_delay), line:586:7, endln:586:20 |vpiName:cmd_delay + |vpiName:cmd.cmd_delay |vpiStmt: \_if_else: , line:588:7, endln:596:10 |vpiParent: @@ -12066,13 +12064,13 @@ design: (work@top) \_begin: (work@test_program.create_command), line:588:27, endln:594:10 |vpiFullName:work@test_program.create_command |vpiForInitStmt: - \_assign_stmt: , line:589:15, endln:589:24 + \_assignment: , line:589:15, endln:589:24 |vpiParent: \_for_stmt: (work@test_program.create_command), line:589:10, endln:589:13 |vpiRhs: \_constant: , line:589:23, endln:589:24 |vpiParent: - \_assign_stmt: , line:589:15, endln:589:24 + \_assignment: , line:589:15, endln:589:24 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -12080,7 +12078,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 |vpiParent: - \_assign_stmt: , line:589:15, endln:589:24 + \_assignment: , line:589:15, endln:589:24 |vpiTypespec: \_ref_typespec: (work@test_program.create_command.i) |vpiParent: @@ -12121,7 +12119,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:589:30, endln:589:44 |vpiParent: \_operation: , line:589:26, endln:589:44 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:589:30, endln:589:33 |vpiParent: @@ -12135,6 +12132,7 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:589:30, endln:589:44 |vpiName:burstcount |vpiFullName:work@test_program.create_command.burstcount + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.create_command), line:589:51, endln:593:13 |vpiParent: @@ -12155,7 +12153,6 @@ design: (work@top) \_hier_path: (cmd.data[i]), line:590:13, endln:590:24 |vpiParent: \_assignment: , line:590:13, endln:590:43 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:590:17, endln:590:21 |vpiParent: @@ -12177,6 +12174,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 + |vpiName:cmd.data[i] |vpiStmt: \_assignment: , line:591:13, endln:591:55 |vpiParent: @@ -12209,7 +12207,6 @@ design: (work@top) \_hier_path: (cmd.byteenable[i]), line:591:13, endln:591:30 |vpiParent: \_assignment: , line:591:13, endln:591:55 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:591:17, endln:591:27 |vpiParent: @@ -12231,6 +12228,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 + |vpiName:cmd.byteenable[i] |vpiStmt: \_assignment: , line:592:13, endln:592:68 |vpiParent: @@ -12260,7 +12258,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[i]), line:592:13, endln:592:30 |vpiParent: \_assignment: , line:592:13, endln:592:68 - |vpiName:cmd.data_idles[i] |vpiActual: \_ref_obj: (cmd), line:592:17, endln:592:27 |vpiParent: @@ -12282,6 +12279,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.cmd.data_idles[i].i |vpiActual: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 + |vpiName:cmd.data_idles[i] |vpiElseStmt: \_begin: (work@test_program.create_command), line:594:16, endln:596:10 |vpiParent: @@ -12316,7 +12314,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[0]), line:595:10, endln:595:27 |vpiParent: \_assignment: , line:595:10, endln:595:68 - |vpiName:cmd.data_idles[0] |vpiActual: \_ref_obj: (cmd), line:595:14, endln:595:24 |vpiParent: @@ -12338,6 +12335,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:cmd.data_idles[0] |vpiStmt: \_return_stmt: , line:598:7, endln:598:13 |vpiParent: @@ -12789,7 +12787,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:636:14, endln:636:23 |vpiParent: \_operation: , line:636:14, endln:636:32 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:636:14, endln:636:17 |vpiParent: @@ -12803,6 +12800,7 @@ design: (work@top) \_hier_path: (cmd.trans), line:636:14, endln:636:23 |vpiName:trans |vpiFullName:work@test_program.save_command_master.trans + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.save_command_master.WRITE), line:636:27, endln:636:32 |vpiParent: @@ -12914,7 +12912,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:649:52, endln:649:60 |vpiParent: \_func_call: (translate_master_to_slave_address), line:649:18, endln:649:61 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:649:52, endln:649:55 |vpiParent: @@ -12928,6 +12925,7 @@ design: (work@top) \_hier_path: (cmd.addr), line:649:52, endln:649:60 |vpiName:addr |vpiFullName:work@test_program.save_command_slave.addr + |vpiName:cmd.addr |vpiName:translate_master_to_slave_address |vpiFunction: \_function: (work@test_program.translate_master_to_slave_address), line:658:4, endln:668:15 @@ -12935,7 +12933,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:649:7, endln:649:15 |vpiParent: \_assignment: , line:649:7, endln:649:61 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:649:11, endln:649:15 |vpiParent: @@ -12948,6 +12945,7 @@ design: (work@top) |vpiParent: \_hier_path: (cmd.addr), line:649:7, endln:649:15 |vpiName:addr + |vpiName:cmd.addr |vpiStmt: \_if_else: , line:650:7, endln:654:10 |vpiParent: @@ -12961,7 +12959,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:650:11, endln:650:20 |vpiParent: \_operation: , line:650:11, endln:650:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:650:11, endln:650:14 |vpiParent: @@ -12975,6 +12972,7 @@ design: (work@top) \_hier_path: (cmd.trans), line:650:11, endln:650:20 |vpiName:trans |vpiFullName:work@test_program.save_command_slave.trans + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.save_command_slave.WRITE), line:650:24, endln:650:29 |vpiParent: @@ -13042,7 +13040,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.translate_master_to_slave_address.slave_id), line:661:11, endln:661:19 |vpiParent: - \_assign_stmt: , line:661:11, endln:661:39 + \_assignment: , line:661:11, endln:661:39 |vpiTypespec: \_ref_typespec: (work@test_program.translate_master_to_slave_address.slave_id) |vpiParent: @@ -13118,13 +13116,15 @@ design: (work@top) |vpiVariables: \_logic_var: (work@test_program.translate_master_to_slave_address.offset), line:662:37, endln:662:43 |vpiStmt: - \_assign_stmt: , line:661:11, endln:661:39 + \_assignment: , line:661:11, endln:661:39 |vpiParent: \_begin: (work@test_program.translate_master_to_slave_address), line:662:7, endln:662:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:661:22, endln:661:39 |vpiParent: - \_assign_stmt: , line:661:11, endln:661:39 + \_assignment: , line:661:11, endln:661:39 |vpiOpType:12 |vpiOperand: \_ref_obj: (work@test_program.translate_master_to_slave_address.addr), line:661:22, endln:661:26 @@ -13383,7 +13383,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.get_expected_command_for_slave.found), line:688:11, endln:688:16 |vpiParent: - \_assign_stmt: , line:688:11, endln:688:20 + \_assignment: , line:688:11, endln:688:20 |vpiTypespec: \_ref_typespec: (work@test_program.get_expected_command_for_slave.found) |vpiParent: @@ -13444,9 +13444,11 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.get_expected_command_for_slave.found), line:688:11, endln:688:16 |vpiStmt: - \_assign_stmt: , line:688:11, endln:688:20 + \_assignment: , line:688:11, endln:688:20 |vpiParent: \_begin: (work@test_program.get_expected_command_for_slave), line:688:7, endln:688:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:688:19, endln:688:20 |vpiDecompile:0 @@ -13468,7 +13470,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:690:11, endln:690:20 |vpiParent: \_operation: , line:690:11, endln:690:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:690:11, endln:690:14 |vpiParent: @@ -13482,6 +13483,7 @@ design: (work@top) \_hier_path: (cmd.trans), line:690:11, endln:690:20 |vpiName:trans |vpiFullName:work@test_program.get_expected_command_for_slave.trans + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.get_expected_command_for_slave.WRITE), line:690:24, endln:690:29 |vpiParent: @@ -13593,7 +13595,6 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:693:17, endln:693:29 |vpiParent: \_operation: , line:693:17, endln:693:41 - |vpiName:exp_cmd.addr |vpiActual: \_ref_obj: (exp_cmd), line:693:17, endln:693:24 |vpiParent: @@ -13607,11 +13608,11 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:693:17, endln:693:29 |vpiName:addr |vpiFullName:work@test_program.get_expected_command_for_slave.addr + |vpiName:exp_cmd.addr |vpiOperand: \_hier_path: (cmd.addr), line:693:33, endln:693:41 |vpiParent: \_operation: , line:693:17, endln:693:41 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:693:33, endln:693:36 |vpiParent: @@ -13625,6 +13626,7 @@ design: (work@top) \_hier_path: (cmd.addr), line:693:33, endln:693:41 |vpiName:addr |vpiFullName:work@test_program.get_expected_command_for_slave.addr + |vpiName:cmd.addr |vpiStmt: \_begin: (work@test_program.get_expected_command_for_slave), line:693:43, endln:697:16 |vpiParent: @@ -13713,7 +13715,6 @@ design: (work@top) \_hier_path: (write_command_queue_slave[slave_id].pop_front), line:700:23, endln:700:70 |vpiParent: \_assignment: , line:700:13, endln:700:70 - |vpiName:write_command_queue_slave[slave_id].pop_front |vpiActual: \_bit_select: (write_command_queue_slave[slave_id]), line:700:23, endln:700:48 |vpiParent: @@ -13733,6 +13734,7 @@ design: (work@top) |vpiParent: \_hier_path: (write_command_queue_slave[slave_id].pop_front), line:700:23, endln:700:70 |vpiName:pop_front + |vpiName:write_command_queue_slave[slave_id].pop_front |vpiLhs: \_ref_obj: (work@test_program.get_expected_command_for_slave.exp_cmd), line:700:13, endln:700:20 |vpiParent: @@ -13844,7 +13846,6 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:705:17, endln:705:29 |vpiParent: \_operation: , line:705:17, endln:705:41 - |vpiName:exp_cmd.addr |vpiActual: \_ref_obj: (exp_cmd), line:705:17, endln:705:24 |vpiParent: @@ -13858,11 +13859,11 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:705:17, endln:705:29 |vpiName:addr |vpiFullName:work@test_program.get_expected_command_for_slave.addr + |vpiName:exp_cmd.addr |vpiOperand: \_hier_path: (cmd.addr), line:705:33, endln:705:41 |vpiParent: \_operation: , line:705:17, endln:705:41 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:705:33, endln:705:36 |vpiParent: @@ -13876,6 +13877,7 @@ design: (work@top) \_hier_path: (cmd.addr), line:705:33, endln:705:41 |vpiName:addr |vpiFullName:work@test_program.get_expected_command_for_slave.addr + |vpiName:cmd.addr |vpiStmt: \_begin: (work@test_program.get_expected_command_for_slave), line:705:43, endln:709:16 |vpiParent: @@ -13964,7 +13966,6 @@ design: (work@top) \_hier_path: (read_command_queue_slave[slave_id].pop_front), line:712:23, endln:712:69 |vpiParent: \_assignment: , line:712:13, endln:712:69 - |vpiName:read_command_queue_slave[slave_id].pop_front |vpiActual: \_bit_select: (read_command_queue_slave[slave_id]), line:712:23, endln:712:47 |vpiParent: @@ -13984,6 +13985,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_command_queue_slave[slave_id].pop_front), line:712:23, endln:712:69 |vpiName:pop_front + |vpiName:read_command_queue_slave[slave_id].pop_front |vpiLhs: \_ref_obj: (work@test_program.get_expected_command_for_slave.exp_cmd), line:712:13, endln:712:20 |vpiParent: @@ -14061,7 +14063,6 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:723:38, endln:723:50 |vpiParent: \_task_call: (assert_equals), line:723:7, endln:723:68 - |vpiName:exp_cmd.addr |vpiActual: \_ref_obj: (exp_cmd), line:723:38, endln:723:45 |vpiParent: @@ -14075,11 +14076,11 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:723:38, endln:723:50 |vpiName:addr |vpiFullName:work@test_program.verify_command.addr + |vpiName:exp_cmd.addr |vpiArgument: \_hier_path: (actual_cmd.addr), line:723:52, endln:723:67 |vpiParent: \_task_call: (assert_equals), line:723:7, endln:723:68 - |vpiName:actual_cmd.addr |vpiActual: \_ref_obj: (actual_cmd), line:723:52, endln:723:62 |vpiParent: @@ -14093,6 +14094,7 @@ design: (work@top) \_hier_path: (actual_cmd.addr), line:723:52, endln:723:67 |vpiName:addr |vpiFullName:work@test_program.verify_command.addr + |vpiName:actual_cmd.addr |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -14112,7 +14114,6 @@ design: (work@top) \_hier_path: (exp_cmd.burstcount), line:724:41, endln:724:59 |vpiParent: \_task_call: (assert_equals), line:724:7, endln:724:83 - |vpiName:exp_cmd.burstcount |vpiActual: \_ref_obj: (exp_cmd), line:724:41, endln:724:48 |vpiParent: @@ -14126,11 +14127,11 @@ design: (work@top) \_hier_path: (exp_cmd.burstcount), line:724:41, endln:724:59 |vpiName:burstcount |vpiFullName:work@test_program.verify_command.burstcount + |vpiName:exp_cmd.burstcount |vpiArgument: \_hier_path: (actual_cmd.burstcount), line:724:61, endln:724:82 |vpiParent: \_task_call: (assert_equals), line:724:7, endln:724:83 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:724:61, endln:724:71 |vpiParent: @@ -14144,6 +14145,7 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:724:61, endln:724:82 |vpiName:burstcount |vpiFullName:work@test_program.verify_command.burstcount + |vpiName:actual_cmd.burstcount |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -14160,7 +14162,6 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:726:11, endln:726:27 |vpiParent: \_operation: , line:726:11, endln:726:36 - |vpiName:actual_cmd.trans |vpiActual: \_ref_obj: (actual_cmd), line:726:11, endln:726:21 |vpiParent: @@ -14174,6 +14175,7 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:726:11, endln:726:27 |vpiName:trans |vpiFullName:work@test_program.verify_command.trans + |vpiName:actual_cmd.trans |vpiOperand: \_ref_obj: (work@test_program.verify_command.WRITE), line:726:31, endln:726:36 |vpiParent: @@ -14193,13 +14195,13 @@ design: (work@top) \_begin: (work@test_program.verify_command), line:726:38, endln:731:10 |vpiFullName:work@test_program.verify_command |vpiForInitStmt: - \_assign_stmt: , line:727:15, endln:727:24 + \_assignment: , line:727:15, endln:727:24 |vpiParent: \_for_stmt: (work@test_program.verify_command), line:727:10, endln:727:13 |vpiRhs: \_constant: , line:727:23, endln:727:24 |vpiParent: - \_assign_stmt: , line:727:15, endln:727:24 + \_assignment: , line:727:15, endln:727:24 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -14207,7 +14209,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 |vpiParent: - \_assign_stmt: , line:727:15, endln:727:24 + \_assignment: , line:727:15, endln:727:24 |vpiTypespec: \_ref_typespec: (work@test_program.verify_command.i) |vpiParent: @@ -14248,7 +14250,6 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:727:30, endln:727:51 |vpiParent: \_operation: , line:727:26, endln:727:51 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:727:30, endln:727:40 |vpiParent: @@ -14262,6 +14263,7 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:727:30, endln:727:51 |vpiName:burstcount |vpiFullName:work@test_program.verify_command.burstcount + |vpiName:actual_cmd.burstcount |vpiStmt: \_begin: (work@test_program.verify_command), line:727:58, endln:730:13 |vpiParent: @@ -14283,7 +14285,6 @@ design: (work@top) \_hier_path: (exp_cmd.data[i]), line:728:47, endln:728:62 |vpiParent: \_task_call: (assert_equals), line:728:13, endln:728:83 - |vpiName:exp_cmd.data[i] |vpiActual: \_ref_obj: (exp_cmd), line:728:47, endln:728:54 |vpiParent: @@ -14305,11 +14306,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.exp_cmd.data[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:exp_cmd.data[i] |vpiArgument: \_hier_path: (actual_cmd.data[i]), line:728:64, endln:728:82 |vpiParent: \_task_call: (assert_equals), line:728:13, endln:728:83 - |vpiName:actual_cmd.data[i] |vpiActual: \_ref_obj: (actual_cmd), line:728:64, endln:728:74 |vpiParent: @@ -14331,6 +14332,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.actual_cmd.data[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:actual_cmd.data[i] |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -14350,7 +14352,6 @@ design: (work@top) \_hier_path: (exp_cmd.byteenable[i]), line:729:47, endln:729:68 |vpiParent: \_task_call: (assert_equals), line:729:13, endln:729:95 - |vpiName:exp_cmd.byteenable[i] |vpiActual: \_ref_obj: (exp_cmd), line:729:47, endln:729:54 |vpiParent: @@ -14372,11 +14373,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.exp_cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:exp_cmd.byteenable[i] |vpiArgument: \_hier_path: (actual_cmd.byteenable[i]), line:729:70, endln:729:94 |vpiParent: \_task_call: (assert_equals), line:729:13, endln:729:95 - |vpiName:actual_cmd.byteenable[i] |vpiActual: \_ref_obj: (actual_cmd), line:729:70, endln:729:80 |vpiParent: @@ -14398,6 +14399,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.actual_cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:actual_cmd.byteenable[i] |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -14675,7 +14677,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:765:7, endln:765:21 |vpiParent: \_assignment: , line:765:7, endln:765:40 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:765:11, endln:765:21 |vpiParent: @@ -14690,19 +14691,20 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_io_decl: (burstcount), line:760:18, endln:760:28 + |vpiName:rsp.burstcount |vpiStmt: \_for_stmt: (work@test_program.create_response), line:766:7, endln:766:10 |vpiParent: \_begin: (work@test_program.create_response), line:765:7, endln:765:41 |vpiFullName:work@test_program.create_response |vpiForInitStmt: - \_assign_stmt: , line:766:12, endln:766:21 + \_assignment: , line:766:12, endln:766:21 |vpiParent: \_for_stmt: (work@test_program.create_response), line:766:7, endln:766:10 |vpiRhs: \_constant: , line:766:20, endln:766:21 |vpiParent: - \_assign_stmt: , line:766:12, endln:766:21 + \_assignment: , line:766:12, endln:766:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -14710,7 +14712,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.create_response.i), line:766:16, endln:766:17 |vpiParent: - \_assign_stmt: , line:766:12, endln:766:21 + \_assignment: , line:766:12, endln:766:21 |vpiTypespec: \_ref_typespec: (work@test_program.create_response.i) |vpiParent: @@ -14775,7 +14777,6 @@ design: (work@top) \_hier_path: (rsp.data[i]), line:767:10, endln:767:21 |vpiParent: \_assignment: , line:767:10, endln:767:37 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:767:14, endln:767:18 |vpiParent: @@ -14797,6 +14798,7 @@ design: (work@top) |vpiFullName:work@test_program.create_response.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.create_response.i), line:766:16, endln:766:17 + |vpiName:rsp.data[i] |vpiStmt: \_assignment: , line:768:10, endln:768:62 |vpiParent: @@ -14826,7 +14828,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:768:10, endln:768:24 |vpiParent: \_assignment: , line:768:10, endln:768:62 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:768:14, endln:768:21 |vpiParent: @@ -14848,6 +14849,7 @@ design: (work@top) |vpiFullName:work@test_program.create_response.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.create_response.i), line:766:16, endln:766:17 + |vpiName:rsp.latency[i] |vpiStmt: \_return_stmt: , line:771:7, endln:771:13 |vpiParent: @@ -14884,7 +14886,7 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.get_expected_read_response.slave_id), line:779:16, endln:779:24 |vpiParent: - \_assign_stmt: , line:779:16, endln:779:48 + \_assignment: , line:779:16, endln:779:48 |vpiTypespec: \_ref_typespec: (work@test_program.get_expected_read_response.slave_id) |vpiParent: @@ -14932,19 +14934,20 @@ design: (work@top) |vpiVariables: \_int_var: (work@test_program.get_expected_read_response.slave_id), line:779:16, endln:779:24 |vpiStmt: - \_assign_stmt: , line:779:16, endln:779:48 + \_assignment: , line:779:16, endln:779:48 |vpiParent: \_begin: (work@test_program.get_expected_read_response), line:779:7, endln:779:49 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:779:27, endln:779:48 |vpiParent: - \_assign_stmt: , line:779:16, endln:779:48 + \_assignment: , line:779:16, endln:779:48 |vpiOpType:12 |vpiOperand: \_hier_path: (cmd.addr), line:779:27, endln:779:35 |vpiParent: \_operation: , line:779:27, endln:779:48 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:779:27, endln:779:30 |vpiParent: @@ -14958,6 +14961,7 @@ design: (work@top) \_hier_path: (cmd.addr), line:779:27, endln:779:35 |vpiName:addr |vpiFullName:work@test_program.get_expected_read_response.addr + |vpiName:cmd.addr |vpiOperand: \_ref_obj: (work@test_program.get_expected_read_response.SLAVE_SPAN), line:779:38, endln:779:48 |vpiParent: @@ -14976,7 +14980,6 @@ design: (work@top) \_hier_path: (read_response_queue_slave[slave_id].pop_front), line:781:13, endln:781:60 |vpiParent: \_assignment: , line:781:7, endln:781:60 - |vpiName:read_response_queue_slave[slave_id].pop_front |vpiActual: \_bit_select: (read_response_queue_slave[slave_id]), line:781:13, endln:781:38 |vpiParent: @@ -14996,6 +14999,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_response_queue_slave[slave_id].pop_front), line:781:13, endln:781:60 |vpiName:pop_front + |vpiName:read_response_queue_slave[slave_id].pop_front |vpiLhs: \_ref_obj: (work@test_program.get_expected_read_response.rsp), line:781:7, endln:781:10 |vpiParent: @@ -15073,7 +15077,6 @@ design: (work@top) \_hier_path: (exp_rsp.burstcount), line:790:41, endln:790:59 |vpiParent: \_task_call: (assert_equals), line:790:7, endln:790:83 - |vpiName:exp_rsp.burstcount |vpiActual: \_ref_obj: (exp_rsp), line:790:41, endln:790:48 |vpiParent: @@ -15087,11 +15090,11 @@ design: (work@top) \_hier_path: (exp_rsp.burstcount), line:790:41, endln:790:59 |vpiName:burstcount |vpiFullName:work@test_program.verify_response.burstcount + |vpiName:exp_rsp.burstcount |vpiArgument: \_hier_path: (actual_rsp.burstcount), line:790:61, endln:790:82 |vpiParent: \_task_call: (assert_equals), line:790:7, endln:790:83 - |vpiName:actual_rsp.burstcount |vpiActual: \_ref_obj: (actual_rsp), line:790:61, endln:790:71 |vpiParent: @@ -15105,6 +15108,7 @@ design: (work@top) \_hier_path: (actual_rsp.burstcount), line:790:61, endln:790:82 |vpiName:burstcount |vpiFullName:work@test_program.verify_response.burstcount + |vpiName:actual_rsp.burstcount |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -15114,13 +15118,13 @@ design: (work@top) \_begin: (work@test_program.verify_response), line:791:7, endln:793:10 |vpiFullName:work@test_program.verify_response |vpiForInitStmt: - \_assign_stmt: , line:791:12, endln:791:21 + \_assignment: , line:791:12, endln:791:21 |vpiParent: \_for_stmt: (work@test_program.verify_response), line:791:7, endln:791:10 |vpiRhs: \_constant: , line:791:20, endln:791:21 |vpiParent: - \_assign_stmt: , line:791:12, endln:791:21 + \_assignment: , line:791:12, endln:791:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -15128,7 +15132,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.verify_response.i), line:791:16, endln:791:17 |vpiParent: - \_assign_stmt: , line:791:12, endln:791:21 + \_assignment: , line:791:12, endln:791:21 |vpiTypespec: \_ref_typespec: (work@test_program.verify_response.i) |vpiParent: @@ -15169,7 +15173,6 @@ design: (work@top) \_hier_path: (actual_rsp.burstcount), line:791:27, endln:791:48 |vpiParent: \_operation: , line:791:23, endln:791:48 - |vpiName:actual_rsp.burstcount |vpiActual: \_ref_obj: (actual_rsp), line:791:27, endln:791:37 |vpiParent: @@ -15183,6 +15186,7 @@ design: (work@top) \_hier_path: (actual_rsp.burstcount), line:791:27, endln:791:48 |vpiName:burstcount |vpiFullName:work@test_program.verify_response.burstcount + |vpiName:actual_rsp.burstcount |vpiStmt: \_begin: (work@test_program.verify_response), line:791:55, endln:793:10 |vpiParent: @@ -15204,7 +15208,6 @@ design: (work@top) \_hier_path: (exp_rsp.data[i]), line:792:43, endln:792:58 |vpiParent: \_task_call: (assert_equals), line:792:10, endln:792:79 - |vpiName:exp_rsp.data[i] |vpiActual: \_ref_obj: (exp_rsp), line:792:43, endln:792:50 |vpiParent: @@ -15226,11 +15229,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.exp_rsp.data[i].i |vpiActual: \_int_var: (work@test_program.verify_response.i), line:791:16, endln:791:17 + |vpiName:exp_rsp.data[i] |vpiArgument: \_hier_path: (actual_rsp.data[i]), line:792:60, endln:792:78 |vpiParent: \_task_call: (assert_equals), line:792:10, endln:792:79 - |vpiName:actual_rsp.data[i] |vpiActual: \_ref_obj: (actual_rsp), line:792:60, endln:792:70 |vpiParent: @@ -15252,6 +15255,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.actual_rsp.data[i].i |vpiActual: \_int_var: (work@test_program.verify_response.i), line:791:16, endln:791:17 + |vpiName:actual_rsp.data[i] |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -15386,8 +15390,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_read_response_complete), line:249:13, endln:249:64 |vpiParent: \_event_control: , line:249:11, endln:249:65 - |vpiName:$root.tb.dut.master_0.signal_read_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_read_response_complete |vpiActual: \_ref_obj: ($root), line:249:19, endln:249:21 |vpiParent: @@ -15413,6 +15415,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_read_response_complete), line:249:13, endln:249:64 |vpiName:signal_read_response_complete + |vpiName:$root.tb.dut.master_0.signal_read_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_read_response_complete |vpiStmt: \_begin: (work@test_program), line:249:66, endln:258:7 |vpiParent: @@ -15467,7 +15471,6 @@ design: (work@top) \_hier_path: (read_command_queue_master[0].pop_front), line:254:13, endln:254:53 |vpiParent: \_assignment: , line:254:7, endln:254:53 - |vpiName:read_command_queue_master[0].pop_front |vpiActual: \_bit_select: (read_command_queue_master[0]), line:254:13, endln:254:38 |vpiParent: @@ -15485,6 +15488,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_command_queue_master[0].pop_front), line:254:13, endln:254:53 |vpiName:pop_front + |vpiName:read_command_queue_master[0].pop_front |vpiLhs: \_ref_obj: (work@test_program.cmd), line:254:7, endln:254:10 |vpiParent: @@ -15579,8 +15583,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_write_response_complete), line:261:13, endln:261:65 |vpiParent: \_event_control: , line:261:11, endln:261:66 - |vpiName:$root.tb.dut.master_0.signal_write_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_write_response_complete |vpiActual: \_ref_obj: ($root), line:261:19, endln:261:21 |vpiParent: @@ -15606,6 +15608,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_write_response_complete), line:261:13, endln:261:65 |vpiName:signal_write_response_complete + |vpiName:$root.tb.dut.master_0.signal_write_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_write_response_complete |vpiStmt: \_begin: (work@test_program), line:261:67, endln:263:7 |vpiParent: @@ -15629,8 +15633,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.slave_0.signal_command_received), line:282:13, endln:282:57 |vpiParent: \_event_control: , line:282:11, endln:282:58 - |vpiName:$root.tb.dut.slave_0.signal_command_received - |vpiFullName:work@test_program.$root.tb.dut.slave_0.signal_command_received |vpiActual: \_ref_obj: ($root), line:282:19, endln:282:21 |vpiParent: @@ -15656,6 +15658,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.slave_0.signal_command_received), line:282:13, endln:282:57 |vpiName:signal_command_received + |vpiName:$root.tb.dut.slave_0.signal_command_received + |vpiFullName:work@test_program.$root.tb.dut.slave_0.signal_command_received |vpiStmt: \_begin: (work@test_program), line:282:59, endln:305:7 |vpiParent: @@ -15721,13 +15725,13 @@ design: (work@top) \_begin: (work@test_program), line:282:59, endln:305:7 |vpiFullName:work@test_program |vpiForInitStmt: - \_assign_stmt: , line:290:12, endln:290:21 + \_assignment: , line:290:12, endln:290:21 |vpiParent: \_for_stmt: (work@test_program), line:290:7, endln:290:10 |vpiRhs: \_constant: , line:290:20, endln:290:21 |vpiParent: - \_assign_stmt: , line:290:12, endln:290:21 + \_assignment: , line:290:12, endln:290:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -15735,7 +15739,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.i), line:290:16, endln:290:17 |vpiParent: - \_assign_stmt: , line:290:12, endln:290:21 + \_assignment: , line:290:12, endln:290:21 |vpiTypespec: \_ref_typespec: (work@test_program.i) |vpiParent: @@ -15931,7 +15935,6 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:300:11, endln:300:27 |vpiParent: \_operation: , line:300:11, endln:300:35 - |vpiName:actual_cmd.trans |vpiActual: \_ref_obj: (actual_cmd), line:300:11, endln:300:21 |vpiParent: @@ -15945,6 +15948,7 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:300:11, endln:300:27 |vpiName:trans |vpiFullName:work@test_program.trans + |vpiName:actual_cmd.trans |vpiOperand: \_ref_obj: (work@test_program.READ), line:300:31, endln:300:35 |vpiParent: @@ -15972,7 +15976,6 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:301:32, endln:301:53 |vpiParent: \_func_call: (create_response), line:301:16, endln:301:54 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:301:32, endln:301:42 |vpiParent: @@ -15986,6 +15989,7 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:301:32, endln:301:53 |vpiName:burstcount |vpiFullName:work@test_program.burstcount + |vpiName:actual_cmd.burstcount |vpiName:create_response |vpiFunction: \_function: (work@test_program.create_response), line:759:4, endln:772:15 @@ -16049,8 +16053,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:333:21, endln:333:41 |vpiParent: \_operation: , line:333:13, endln:333:41 - |vpiName:$root.tb.dut.clk_clk - |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiActual: \_ref_obj: ($root), line:333:27, endln:333:29 |vpiParent: @@ -16071,6 +16073,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:333:21, endln:333:41 |vpiName:clk_clk + |vpiName:$root.tb.dut.clk_clk + |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiStmt: \_begin: (work@test_program), line:333:43, endln:337:7 |vpiParent: @@ -16132,8 +16136,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_read_response_complete), line:392:13, endln:392:64 |vpiParent: \_event_control: , line:392:11, endln:392:65 - |vpiName:$root.tb.dut.master_1.signal_read_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_read_response_complete |vpiActual: \_ref_obj: ($root), line:392:19, endln:392:21 |vpiParent: @@ -16159,6 +16161,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_read_response_complete), line:392:13, endln:392:64 |vpiName:signal_read_response_complete + |vpiName:$root.tb.dut.master_1.signal_read_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_read_response_complete |vpiStmt: \_begin: (work@test_program), line:392:66, endln:401:7 |vpiParent: @@ -16213,7 +16217,6 @@ design: (work@top) \_hier_path: (read_command_queue_master[1].pop_front), line:397:13, endln:397:53 |vpiParent: \_assignment: , line:397:7, endln:397:53 - |vpiName:read_command_queue_master[1].pop_front |vpiActual: \_bit_select: (read_command_queue_master[1]), line:397:13, endln:397:38 |vpiParent: @@ -16231,6 +16234,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_command_queue_master[1].pop_front), line:397:13, endln:397:53 |vpiName:pop_front + |vpiName:read_command_queue_master[1].pop_front |vpiLhs: \_ref_obj: (work@test_program.cmd), line:397:7, endln:397:10 |vpiParent: @@ -16325,8 +16329,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_write_response_complete), line:404:13, endln:404:65 |vpiParent: \_event_control: , line:404:11, endln:404:66 - |vpiName:$root.tb.dut.master_1.signal_write_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_write_response_complete |vpiActual: \_ref_obj: ($root), line:404:19, endln:404:21 |vpiParent: @@ -16352,6 +16354,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_write_response_complete), line:404:13, endln:404:65 |vpiName:signal_write_response_complete + |vpiName:$root.tb.dut.master_1.signal_write_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_write_response_complete |vpiStmt: \_begin: (work@test_program), line:404:67, endln:406:7 |vpiParent: @@ -16375,8 +16379,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.slave_1.signal_command_received), line:425:13, endln:425:57 |vpiParent: \_event_control: , line:425:11, endln:425:58 - |vpiName:$root.tb.dut.slave_1.signal_command_received - |vpiFullName:work@test_program.$root.tb.dut.slave_1.signal_command_received |vpiActual: \_ref_obj: ($root), line:425:19, endln:425:21 |vpiParent: @@ -16402,6 +16404,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.slave_1.signal_command_received), line:425:13, endln:425:57 |vpiName:signal_command_received + |vpiName:$root.tb.dut.slave_1.signal_command_received + |vpiFullName:work@test_program.$root.tb.dut.slave_1.signal_command_received |vpiStmt: \_begin: (work@test_program), line:425:59, endln:448:7 |vpiParent: @@ -16467,13 +16471,13 @@ design: (work@top) \_begin: (work@test_program), line:425:59, endln:448:7 |vpiFullName:work@test_program |vpiForInitStmt: - \_assign_stmt: , line:433:12, endln:433:21 + \_assignment: , line:433:12, endln:433:21 |vpiParent: \_for_stmt: (work@test_program), line:433:7, endln:433:10 |vpiRhs: \_constant: , line:433:20, endln:433:21 |vpiParent: - \_assign_stmt: , line:433:12, endln:433:21 + \_assignment: , line:433:12, endln:433:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -16481,7 +16485,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.i), line:433:16, endln:433:17 |vpiParent: - \_assign_stmt: , line:433:12, endln:433:21 + \_assignment: , line:433:12, endln:433:21 |vpiTypespec: \_ref_typespec: (work@test_program.i) |vpiParent: @@ -16677,7 +16681,6 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:443:11, endln:443:27 |vpiParent: \_operation: , line:443:11, endln:443:35 - |vpiName:actual_cmd.trans |vpiActual: \_ref_obj: (actual_cmd), line:443:11, endln:443:21 |vpiParent: @@ -16691,6 +16694,7 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:443:11, endln:443:27 |vpiName:trans |vpiFullName:work@test_program.trans + |vpiName:actual_cmd.trans |vpiOperand: \_ref_obj: (work@test_program.READ), line:443:31, endln:443:35 |vpiParent: @@ -16718,7 +16722,6 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:444:32, endln:444:53 |vpiParent: \_func_call: (create_response), line:444:16, endln:444:54 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:444:32, endln:444:42 |vpiParent: @@ -16732,6 +16735,7 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:444:32, endln:444:53 |vpiName:burstcount |vpiFullName:work@test_program.burstcount + |vpiName:actual_cmd.burstcount |vpiName:create_response |vpiFunction: \_function: (work@test_program.create_response), line:759:4, endln:772:15 @@ -16795,8 +16799,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:476:21, endln:476:41 |vpiParent: \_operation: , line:476:13, endln:476:41 - |vpiName:$root.tb.dut.clk_clk - |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiActual: \_ref_obj: ($root), line:476:27, endln:476:29 |vpiParent: @@ -16817,6 +16819,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:476:21, endln:476:41 |vpiName:clk_clk + |vpiName:$root.tb.dut.clk_clk + |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiStmt: \_begin: (work@test_program), line:476:43, endln:480:7 |vpiParent: @@ -16901,8 +16905,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.reset_reset_n), line:526:13, endln:526:39 |vpiParent: \_operation: , line:526:13, endln:526:44 - |vpiName:$root.tb.dut.reset_reset_n - |vpiFullName:work@test_program.$root.tb.dut.reset_reset_n |vpiActual: \_ref_obj: ($root), line:526:19, endln:526:21 |vpiParent: @@ -16923,6 +16925,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.reset_reset_n), line:526:13, endln:526:39 |vpiName:reset_reset_n + |vpiName:$root.tb.dut.reset_reset_n + |vpiFullName:work@test_program.$root.tb.dut.reset_reset_n |vpiOperand: \_constant: , line:526:43, endln:526:44 |vpiParent: @@ -17151,8 +17155,6 @@ design: (work@top) \_hier_path: (work@test_program1.$root.tb.dut.master_02.signal_write_response_complete), line:802:13, endln:802:68 |vpiParent: \_event_control: , line:802:11, endln:802:69 - |vpiName:$root.tb.dut.master_02.signal_write_response_complete - |vpiFullName:work@test_program1.$root.tb.dut.master_02.signal_write_response_complete |vpiActual: \_ref_obj: ($root), line:802:19, endln:802:21 |vpiParent: @@ -17190,6 +17192,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program1.$root.tb.dut.master_02.signal_write_response_complete), line:802:13, endln:802:68 |vpiName:signal_write_response_complete + |vpiName:$root.tb.dut.master_02.signal_write_response_complete + |vpiFullName:work@test_program1.$root.tb.dut.master_02.signal_write_response_complete |vpiStmt: \_begin: (work@test_program1), line:802:70, endln:804:7 |vpiParent: @@ -17287,8 +17291,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17 |vpiParent: \_cont_assign: , line:2:11, endln:2:26 - |vpiName:$root.top.a - |vpiFullName:work@top.$root.top.a |vpiActual: \_ref_obj: ($root), line:2:17, endln:2:20 |vpiParent: @@ -17304,6 +17306,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17 |vpiName:a + |vpiName:$root.top.a + |vpiFullName:work@top.$root.top.a |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10 |vpiName:work@top @@ -17400,8 +17404,6 @@ design: (work@top) \_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17 |vpiParent: \_cont_assign: , line:2:11, endln:2:26 - |vpiName:$root.top.a - |vpiFullName:work@top.$root.top.a |vpiActual: \_ref_obj: ($root), line:2:17, endln:2:20 |vpiParent: @@ -17421,6 +17423,8 @@ design: (work@top) |vpiName:a |vpiActual: \_logic_net: (work@top.a), line:1:41, endln:1:42 + |vpiName:$root.top.a + |vpiFullName:work@top.$root.top.a |uhdmtopModules: \_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10 |vpiName:work@test_program @@ -17976,7 +17980,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:227:49, endln:227:57 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_address), line:227:7, endln:227:58 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:227:49, endln:227:52 |vpiParent: @@ -17992,6 +17995,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiName:$root.tb.dut.master_0.set_command_address |vpiStmt: \_func_call: ($root.tb.dut.master_0.set_command_burst_count), line:228:7, endln:228:68 @@ -18001,7 +18005,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:228:53, endln:228:67 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_burst_count), line:228:7, endln:228:68 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:228:53, endln:228:56 |vpiParent: @@ -18017,6 +18020,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_0.set_command_burst_count |vpiStmt: \_func_call: ($root.tb.dut.master_0.set_command_burst_size), line:229:7, endln:229:67 @@ -18026,7 +18030,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:229:52, endln:229:66 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_burst_size), line:229:7, endln:229:67 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:229:52, endln:229:55 |vpiParent: @@ -18042,6 +18045,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_0.set_command_burst_size |vpiStmt: \_func_call: ($root.tb.dut.master_0.set_command_init_latency), line:230:7, endln:230:68 @@ -18051,7 +18055,6 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:230:54, endln:230:67 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_init_latency), line:230:7, endln:230:68 - |vpiName:cmd.cmd_delay |vpiActual: \_ref_obj: (cmd), line:230:54, endln:230:57 |vpiParent: @@ -18067,6 +18070,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd_delay |vpiActual: \_typespec_member: (cmd_delay), line:52:37, endln:52:46 + |vpiName:cmd.cmd_delay |vpiName:$root.tb.dut.master_0.set_command_init_latency |vpiStmt: \_if_else: , line:232:7, endln:242:10 @@ -18081,7 +18085,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:232:11, endln:232:20 |vpiParent: \_operation: , line:232:11, endln:232:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:232:11, endln:232:14 |vpiParent: @@ -18097,6 +18100,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.WRITE), line:232:24, endln:232:29 |vpiParent: @@ -18129,7 +18133,7 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_0), line:232:31, endln:239:10 |vpiFullName:work@test_program.configure_and_push_command_to_master_0 |vpiForInitStmt: - \_assign_stmt: , line:234:15, endln:234:24 + \_assignment: , line:234:15, endln:234:24 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_command_to_master_0), line:234:10, endln:234:13 |vpiRhs: @@ -18137,7 +18141,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 |vpiParent: - \_assign_stmt: , line:234:15, endln:234:24 + \_assignment: , line:234:15, endln:234:24 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_command_to_master_0.i) |vpiParent: @@ -18178,7 +18182,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:234:30, endln:234:44 |vpiParent: \_operation: , line:234:26, endln:234:44 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:234:30, endln:234:33 |vpiParent: @@ -18194,6 +18197,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_command_to_master_0), line:234:51, endln:238:13 |vpiParent: @@ -18207,7 +18211,6 @@ design: (work@top) \_hier_path: (cmd.data[i]), line:235:52, endln:235:63 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_data), line:235:13, endln:235:67 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:235:52, endln:235:55 |vpiParent: @@ -18231,6 +18234,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 + |vpiName:cmd.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.i), line:235:65, endln:235:66 |vpiParent: @@ -18248,7 +18252,6 @@ design: (work@top) \_hier_path: (cmd.byteenable[i]), line:236:59, endln:236:76 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_byte_enable), line:236:13, endln:236:80 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:236:59, endln:236:62 |vpiParent: @@ -18272,6 +18275,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 + |vpiName:cmd.byteenable[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.i), line:236:78, endln:236:79 |vpiParent: @@ -18289,7 +18293,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[i]), line:237:52, endln:237:69 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_idle), line:237:13, endln:237:73 - |vpiName:cmd.data_idles[i] |vpiActual: \_ref_obj: (cmd), line:237:52, endln:237:55 |vpiParent: @@ -18313,6 +18316,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_0.cmd.data_idles[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_0.i), line:234:19, endln:234:20 + |vpiName:cmd.data_idles[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_0.i), line:237:71, endln:237:72 |vpiParent: @@ -18348,7 +18352,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[0]), line:241:49, endln:241:66 |vpiParent: \_func_call: ($root.tb.dut.master_0.set_command_idle), line:241:10, endln:241:70 - |vpiName:cmd.data_idles[0] |vpiActual: \_ref_obj: (cmd), line:241:49, endln:241:52 |vpiParent: @@ -18366,6 +18369,7 @@ design: (work@top) \_typespec_member: (data_idles), line:53:37, endln:53:63 |vpiIndex: \_constant: , line:241:64, endln:241:65 + |vpiName:cmd.data_idles[0] |vpiArgument: \_constant: , line:241:68, endln:241:69 |vpiName:$root.tb.dut.master_0.set_command_idle @@ -18432,8 +18436,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size), line:271:27, endln:271:74 |vpiParent: \_assignment: , line:271:7, endln:271:74 - |vpiName:$root.tb.dut.master_0.get_response_burst_size - |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size |vpiActual: \_ref_obj: ($root), line:271:33, endln:271:35 |vpiParent: @@ -18459,11 +18461,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size), line:271:27, endln:271:74 |vpiName:get_response_burst_size + |vpiName:$root.tb.dut.master_0.get_response_burst_size + |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_burst_size |vpiLhs: \_hier_path: (rsp.burstcount), line:271:7, endln:271:21 |vpiParent: \_assignment: , line:271:7, endln:271:74 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:271:11, endln:271:21 |vpiParent: @@ -18478,13 +18481,14 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiStmt: \_for_stmt: (work@test_program.get_read_response_from_master_0), line:272:7, endln:272:10 |vpiParent: \_begin: (work@test_program.get_read_response_from_master_0), line:270:7, endln:270:44 |vpiFullName:work@test_program.get_read_response_from_master_0 |vpiForInitStmt: - \_assign_stmt: , line:272:12, endln:272:21 + \_assignment: , line:272:12, endln:272:21 |vpiParent: \_for_stmt: (work@test_program.get_read_response_from_master_0), line:272:7, endln:272:10 |vpiRhs: @@ -18492,7 +18496,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_read_response_from_master_0.i), line:272:16, endln:272:17 |vpiParent: - \_assign_stmt: , line:272:12, endln:272:21 + \_assignment: , line:272:12, endln:272:21 |vpiTypespec: \_ref_typespec: (work@test_program.get_read_response_from_master_0.i) |vpiParent: @@ -18533,7 +18537,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:272:27, endln:272:41 |vpiParent: \_operation: , line:272:23, endln:272:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:272:27, endln:272:30 |vpiParent: @@ -18549,6 +18552,7 @@ design: (work@top) |vpiFullName:work@test_program.get_read_response_from_master_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_0), line:272:48, endln:274:10 |vpiParent: @@ -18564,8 +18568,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data), line:273:27, endln:273:69 |vpiParent: \_assignment: , line:273:10, endln:273:69 - |vpiName:$root.tb.dut.master_0.get_response_data - |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data |vpiActual: \_ref_obj: ($root), line:273:33, endln:273:35 |vpiParent: @@ -18591,11 +18593,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data), line:273:27, endln:273:69 |vpiName:get_response_data + |vpiName:$root.tb.dut.master_0.get_response_data + |vpiFullName:work@test_program.get_read_response_from_master_0.$root.tb.dut.master_0.get_response_data |vpiLhs: \_hier_path: (rsp.data[i]), line:273:10, endln:273:21 |vpiParent: \_assignment: , line:273:10, endln:273:69 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:273:14, endln:273:18 |vpiParent: @@ -18619,6 +18622,7 @@ design: (work@top) |vpiFullName:work@test_program.get_read_response_from_master_0.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.get_read_response_from_master_0.i), line:272:16, endln:272:17 + |vpiName:rsp.data[i] |vpiStmt: \_return_stmt: , line:276:7, endln:276:13 |vpiParent: @@ -18689,8 +18693,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count), line:314:33, endln:314:79 |vpiParent: \_assignment: , line:314:7, endln:314:79 - |vpiName:$root.tb.dut.slave_0.get_command_burst_count - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count |vpiActual: \_ref_obj: ($root), line:314:39, endln:314:41 |vpiParent: @@ -18716,11 +18718,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count), line:314:33, endln:314:79 |vpiName:get_command_burst_count + |vpiName:$root.tb.dut.slave_0.get_command_burst_count + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_burst_count |vpiLhs: \_hier_path: (cmd.burstcount), line:314:7, endln:314:21 |vpiParent: \_assignment: , line:314:7, endln:314:79 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:314:11, endln:314:21 |vpiParent: @@ -18735,6 +18738,7 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_assignment: , line:315:7, endln:315:75 |vpiParent: @@ -18745,8 +18749,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address), line:315:33, endln:315:75 |vpiParent: \_assignment: , line:315:7, endln:315:75 - |vpiName:$root.tb.dut.slave_0.get_command_address - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address |vpiActual: \_ref_obj: ($root), line:315:39, endln:315:41 |vpiParent: @@ -18772,11 +18774,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address), line:315:33, endln:315:75 |vpiName:get_command_address + |vpiName:$root.tb.dut.slave_0.get_command_address + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_address |vpiLhs: \_hier_path: (cmd.addr), line:315:7, endln:315:15 |vpiParent: \_assignment: , line:315:7, endln:315:75 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:315:11, endln:315:15 |vpiParent: @@ -18791,6 +18794,7 @@ design: (work@top) |vpiName:addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiStmt: \_if_else: , line:317:7, endln:325:10 |vpiParent: @@ -18804,8 +18808,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request), line:317:11, endln:317:53 |vpiParent: \_operation: , line:317:11, endln:317:66 - |vpiName:$root.tb.dut.slave_0.get_command_request - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request |vpiActual: \_ref_obj: ($root), line:317:17, endln:317:19 |vpiParent: @@ -18831,6 +18833,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request), line:317:11, endln:317:53 |vpiName:get_command_request + |vpiName:$root.tb.dut.slave_0.get_command_request + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_request |vpiOperand: \_ref_obj: (work@test_program.get_command_from_slave_0.REQ_WRITE), line:317:57, endln:317:66 |vpiParent: @@ -18862,7 +18866,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:318:10, endln:318:19 |vpiParent: \_assignment: , line:318:10, endln:318:27 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:318:14, endln:318:19 |vpiParent: @@ -18877,13 +18880,14 @@ design: (work@top) |vpiName:trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiStmt: \_for_stmt: (work@test_program.get_command_from_slave_0), line:319:10, endln:319:13 |vpiParent: \_begin: (work@test_program.get_command_from_slave_0), line:317:68, endln:323:10 |vpiFullName:work@test_program.get_command_from_slave_0 |vpiForInitStmt: - \_assign_stmt: , line:319:14, endln:319:23 + \_assignment: , line:319:14, endln:319:23 |vpiParent: \_for_stmt: (work@test_program.get_command_from_slave_0), line:319:10, endln:319:13 |vpiRhs: @@ -18891,7 +18895,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_command_from_slave_0.i), line:319:18, endln:319:19 |vpiParent: - \_assign_stmt: , line:319:14, endln:319:23 + \_assignment: , line:319:14, endln:319:23 |vpiTypespec: \_ref_typespec: (work@test_program.get_command_from_slave_0.i) |vpiParent: @@ -18932,7 +18936,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:319:29, endln:319:43 |vpiParent: \_operation: , line:319:25, endln:319:43 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:319:29, endln:319:32 |vpiParent: @@ -18948,6 +18951,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.get_command_from_slave_0), line:319:50, endln:322:13 |vpiParent: @@ -18963,8 +18967,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data), line:320:32, endln:320:72 |vpiParent: \_assignment: , line:320:13, endln:320:72 - |vpiName:$root.tb.dut.slave_0.get_command_data - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data |vpiActual: \_ref_obj: ($root), line:320:38, endln:320:40 |vpiParent: @@ -18990,11 +18992,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data), line:320:32, endln:320:72 |vpiName:get_command_data + |vpiName:$root.tb.dut.slave_0.get_command_data + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_data |vpiLhs: \_hier_path: (cmd.data[i]), line:320:13, endln:320:24 |vpiParent: \_assignment: , line:320:13, endln:320:72 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:320:17, endln:320:21 |vpiParent: @@ -19018,6 +19021,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_0.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_0.i), line:319:18, endln:319:19 + |vpiName:cmd.data[i] |vpiStmt: \_assignment: , line:321:13, endln:321:79 |vpiParent: @@ -19028,8 +19032,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable), line:321:32, endln:321:79 |vpiParent: \_assignment: , line:321:13, endln:321:79 - |vpiName:$root.tb.dut.slave_0.get_command_byte_enable - |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable |vpiActual: \_ref_obj: ($root), line:321:38, endln:321:40 |vpiParent: @@ -19055,11 +19057,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable), line:321:32, endln:321:79 |vpiName:get_command_byte_enable + |vpiName:$root.tb.dut.slave_0.get_command_byte_enable + |vpiFullName:work@test_program.get_command_from_slave_0.$root.tb.dut.slave_0.get_command_byte_enable |vpiLhs: \_hier_path: (cmd.byteenable[i]), line:321:13, endln:321:30 |vpiParent: \_assignment: , line:321:13, endln:321:79 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:321:17, endln:321:27 |vpiParent: @@ -19083,6 +19086,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_0.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_0.i), line:319:18, endln:319:19 + |vpiName:cmd.byteenable[i] |vpiElseStmt: \_begin: (work@test_program.get_command_from_slave_0), line:323:16, endln:325:10 |vpiParent: @@ -19106,7 +19110,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:324:10, endln:324:19 |vpiParent: \_assignment: , line:324:10, endln:324:26 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:324:14, endln:324:19 |vpiParent: @@ -19121,6 +19124,7 @@ design: (work@top) |vpiName:trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiStmt: \_return_stmt: , line:327:7, endln:327:13 |vpiParent: @@ -19210,7 +19214,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:347:52, endln:347:66 |vpiParent: \_func_call: ($root.tb.dut.slave_0.set_response_burst_size), line:347:7, endln:347:67 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:347:52, endln:347:55 |vpiParent: @@ -19226,6 +19229,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiName:$root.tb.dut.slave_0.set_response_burst_size |vpiStmt: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_0), line:348:7, endln:348:10 @@ -19233,7 +19237,7 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_response_to_slave_0), line:346:7, endln:346:59 |vpiFullName:work@test_program.configure_and_push_response_to_slave_0 |vpiForInitStmt: - \_assign_stmt: , line:348:12, endln:348:21 + \_assignment: , line:348:12, endln:348:21 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_0), line:348:7, endln:348:10 |vpiRhs: @@ -19241,7 +19245,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 |vpiParent: - \_assign_stmt: , line:348:12, endln:348:21 + \_assignment: , line:348:12, endln:348:21 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_response_to_slave_0.i) |vpiParent: @@ -19282,7 +19286,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:348:27, endln:348:41 |vpiParent: \_operation: , line:348:23, endln:348:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:348:27, endln:348:30 |vpiParent: @@ -19298,6 +19301,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_response_to_slave_0), line:348:48, endln:359:10 |vpiParent: @@ -19311,7 +19315,6 @@ design: (work@top) \_hier_path: (rsp.data[i]), line:349:49, endln:349:60 |vpiParent: \_func_call: ($root.tb.dut.slave_0.set_response_data), line:349:10, endln:349:64 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:349:49, endln:349:52 |vpiParent: @@ -19335,6 +19338,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.i), line:349:62, endln:349:63 |vpiParent: @@ -19381,7 +19385,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:352:55, endln:352:69 |vpiParent: \_operation: , line:352:55, endln:352:99 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:352:55, endln:352:58 |vpiParent: @@ -19405,6 +19408,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.pending_read_cycles_slave_0), line:352:72, endln:352:99 |vpiParent: @@ -19432,7 +19436,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:353:37, endln:353:51 |vpiParent: \_assignment: , line:353:13, endln:353:51 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:353:37, endln:353:40 |vpiParent: @@ -19456,6 +19459,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiLhs: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.read_response_latency), line:353:13, endln:353:34 |vpiParent: @@ -19477,7 +19481,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:355:55, endln:355:69 |vpiParent: \_func_call: ($root.tb.dut.slave_0.set_response_latency), line:355:13, endln:355:73 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:355:55, endln:355:58 |vpiParent: @@ -19501,6 +19504,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.i), line:355:71, endln:355:72 |vpiParent: @@ -19525,7 +19529,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:356:37, endln:356:51 |vpiParent: \_operation: , line:356:37, endln:356:75 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:356:37, endln:356:40 |vpiParent: @@ -19549,6 +19552,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_0.i), line:348:16, endln:348:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_0.read_response_latency), line:356:54, endln:356:75 |vpiParent: @@ -19611,7 +19615,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:361:91, endln:361:105 |vpiParent: \_operation: , line:361:37, endln:361:105 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:361:91, endln:361:94 |vpiParent: @@ -19627,6 +19630,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_0.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiOperand: \_constant: , line:361:108, endln:361:109 |vpiLhs: @@ -19673,7 +19677,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:370:49, endln:370:57 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_address), line:370:7, endln:370:58 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:370:49, endln:370:52 |vpiParent: @@ -19689,6 +19692,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiName:$root.tb.dut.master_1.set_command_address |vpiStmt: \_func_call: ($root.tb.dut.master_1.set_command_burst_count), line:371:7, endln:371:68 @@ -19698,7 +19702,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:371:53, endln:371:67 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_burst_count), line:371:7, endln:371:68 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:371:53, endln:371:56 |vpiParent: @@ -19714,6 +19717,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_1.set_command_burst_count |vpiStmt: \_func_call: ($root.tb.dut.master_1.set_command_burst_size), line:372:7, endln:372:67 @@ -19723,7 +19727,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:372:52, endln:372:66 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_burst_size), line:372:7, endln:372:67 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:372:52, endln:372:55 |vpiParent: @@ -19739,6 +19742,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiName:$root.tb.dut.master_1.set_command_burst_size |vpiStmt: \_func_call: ($root.tb.dut.master_1.set_command_init_latency), line:373:7, endln:373:68 @@ -19748,7 +19752,6 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:373:54, endln:373:67 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_init_latency), line:373:7, endln:373:68 - |vpiName:cmd.cmd_delay |vpiActual: \_ref_obj: (cmd), line:373:54, endln:373:57 |vpiParent: @@ -19764,6 +19767,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd_delay |vpiActual: \_typespec_member: (cmd_delay), line:52:37, endln:52:46 + |vpiName:cmd.cmd_delay |vpiName:$root.tb.dut.master_1.set_command_init_latency |vpiStmt: \_if_else: , line:375:7, endln:385:10 @@ -19778,7 +19782,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:375:11, endln:375:20 |vpiParent: \_operation: , line:375:11, endln:375:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:375:11, endln:375:14 |vpiParent: @@ -19794,6 +19797,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.WRITE), line:375:24, endln:375:29 |vpiParent: @@ -19826,7 +19830,7 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_command_to_master_1), line:375:31, endln:382:10 |vpiFullName:work@test_program.configure_and_push_command_to_master_1 |vpiForInitStmt: - \_assign_stmt: , line:377:15, endln:377:24 + \_assignment: , line:377:15, endln:377:24 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_command_to_master_1), line:377:10, endln:377:13 |vpiRhs: @@ -19834,7 +19838,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 |vpiParent: - \_assign_stmt: , line:377:15, endln:377:24 + \_assignment: , line:377:15, endln:377:24 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_command_to_master_1.i) |vpiParent: @@ -19875,7 +19879,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:377:30, endln:377:44 |vpiParent: \_operation: , line:377:26, endln:377:44 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:377:30, endln:377:33 |vpiParent: @@ -19891,6 +19894,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_command_to_master_1), line:377:51, endln:381:13 |vpiParent: @@ -19904,7 +19908,6 @@ design: (work@top) \_hier_path: (cmd.data[i]), line:378:52, endln:378:63 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_data), line:378:13, endln:378:67 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:378:52, endln:378:55 |vpiParent: @@ -19928,6 +19931,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 + |vpiName:cmd.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.i), line:378:65, endln:378:66 |vpiParent: @@ -19945,7 +19949,6 @@ design: (work@top) \_hier_path: (cmd.byteenable[i]), line:379:59, endln:379:76 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_byte_enable), line:379:13, endln:379:80 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:379:59, endln:379:62 |vpiParent: @@ -19969,6 +19972,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 + |vpiName:cmd.byteenable[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.i), line:379:78, endln:379:79 |vpiParent: @@ -19986,7 +19990,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[i]), line:380:52, endln:380:69 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_idle), line:380:13, endln:380:73 - |vpiName:cmd.data_idles[i] |vpiActual: \_ref_obj: (cmd), line:380:52, endln:380:55 |vpiParent: @@ -20010,6 +20013,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_command_to_master_1.cmd.data_idles[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_command_to_master_1.i), line:377:19, endln:377:20 + |vpiName:cmd.data_idles[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_command_to_master_1.i), line:380:71, endln:380:72 |vpiParent: @@ -20045,7 +20049,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[0]), line:384:49, endln:384:66 |vpiParent: \_func_call: ($root.tb.dut.master_1.set_command_idle), line:384:10, endln:384:70 - |vpiName:cmd.data_idles[0] |vpiActual: \_ref_obj: (cmd), line:384:49, endln:384:52 |vpiParent: @@ -20063,6 +20066,7 @@ design: (work@top) \_typespec_member: (data_idles), line:53:37, endln:53:63 |vpiIndex: \_constant: , line:384:64, endln:384:65 + |vpiName:cmd.data_idles[0] |vpiArgument: \_constant: , line:384:68, endln:384:69 |vpiName:$root.tb.dut.master_1.set_command_idle @@ -20129,8 +20133,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size), line:414:27, endln:414:74 |vpiParent: \_assignment: , line:414:7, endln:414:74 - |vpiName:$root.tb.dut.master_1.get_response_burst_size - |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size |vpiActual: \_ref_obj: ($root), line:414:33, endln:414:35 |vpiParent: @@ -20156,11 +20158,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size), line:414:27, endln:414:74 |vpiName:get_response_burst_size + |vpiName:$root.tb.dut.master_1.get_response_burst_size + |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_burst_size |vpiLhs: \_hier_path: (rsp.burstcount), line:414:7, endln:414:21 |vpiParent: \_assignment: , line:414:7, endln:414:74 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:414:11, endln:414:21 |vpiParent: @@ -20175,13 +20178,14 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiStmt: \_for_stmt: (work@test_program.get_read_response_from_master_1), line:415:7, endln:415:10 |vpiParent: \_begin: (work@test_program.get_read_response_from_master_1), line:413:7, endln:413:44 |vpiFullName:work@test_program.get_read_response_from_master_1 |vpiForInitStmt: - \_assign_stmt: , line:415:12, endln:415:21 + \_assignment: , line:415:12, endln:415:21 |vpiParent: \_for_stmt: (work@test_program.get_read_response_from_master_1), line:415:7, endln:415:10 |vpiRhs: @@ -20189,7 +20193,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_read_response_from_master_1.i), line:415:16, endln:415:17 |vpiParent: - \_assign_stmt: , line:415:12, endln:415:21 + \_assignment: , line:415:12, endln:415:21 |vpiTypespec: \_ref_typespec: (work@test_program.get_read_response_from_master_1.i) |vpiParent: @@ -20230,7 +20234,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:415:27, endln:415:41 |vpiParent: \_operation: , line:415:23, endln:415:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:415:27, endln:415:30 |vpiParent: @@ -20246,6 +20249,7 @@ design: (work@top) |vpiFullName:work@test_program.get_read_response_from_master_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.get_read_response_from_master_1), line:415:48, endln:417:10 |vpiParent: @@ -20261,8 +20265,6 @@ design: (work@top) \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data), line:416:27, endln:416:69 |vpiParent: \_assignment: , line:416:10, endln:416:69 - |vpiName:$root.tb.dut.master_1.get_response_data - |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data |vpiActual: \_ref_obj: ($root), line:416:33, endln:416:35 |vpiParent: @@ -20288,11 +20290,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data), line:416:27, endln:416:69 |vpiName:get_response_data + |vpiName:$root.tb.dut.master_1.get_response_data + |vpiFullName:work@test_program.get_read_response_from_master_1.$root.tb.dut.master_1.get_response_data |vpiLhs: \_hier_path: (rsp.data[i]), line:416:10, endln:416:21 |vpiParent: \_assignment: , line:416:10, endln:416:69 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:416:14, endln:416:18 |vpiParent: @@ -20316,6 +20319,7 @@ design: (work@top) |vpiFullName:work@test_program.get_read_response_from_master_1.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.get_read_response_from_master_1.i), line:415:16, endln:415:17 + |vpiName:rsp.data[i] |vpiStmt: \_return_stmt: , line:419:7, endln:419:13 |vpiParent: @@ -20386,8 +20390,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count), line:457:33, endln:457:79 |vpiParent: \_assignment: , line:457:7, endln:457:79 - |vpiName:$root.tb.dut.slave_1.get_command_burst_count - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count |vpiActual: \_ref_obj: ($root), line:457:39, endln:457:41 |vpiParent: @@ -20413,11 +20415,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count), line:457:33, endln:457:79 |vpiName:get_command_burst_count + |vpiName:$root.tb.dut.slave_1.get_command_burst_count + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_burst_count |vpiLhs: \_hier_path: (cmd.burstcount), line:457:7, endln:457:21 |vpiParent: \_assignment: , line:457:7, endln:457:79 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:457:11, endln:457:21 |vpiParent: @@ -20432,6 +20435,7 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_assignment: , line:458:7, endln:458:75 |vpiParent: @@ -20442,8 +20446,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address), line:458:33, endln:458:75 |vpiParent: \_assignment: , line:458:7, endln:458:75 - |vpiName:$root.tb.dut.slave_1.get_command_address - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address |vpiActual: \_ref_obj: ($root), line:458:39, endln:458:41 |vpiParent: @@ -20469,11 +20471,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address), line:458:33, endln:458:75 |vpiName:get_command_address + |vpiName:$root.tb.dut.slave_1.get_command_address + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_address |vpiLhs: \_hier_path: (cmd.addr), line:458:7, endln:458:15 |vpiParent: \_assignment: , line:458:7, endln:458:75 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:458:11, endln:458:15 |vpiParent: @@ -20488,6 +20491,7 @@ design: (work@top) |vpiName:addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiStmt: \_if_else: , line:460:7, endln:468:10 |vpiParent: @@ -20501,8 +20505,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request), line:460:11, endln:460:53 |vpiParent: \_operation: , line:460:11, endln:460:66 - |vpiName:$root.tb.dut.slave_1.get_command_request - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request |vpiActual: \_ref_obj: ($root), line:460:17, endln:460:19 |vpiParent: @@ -20528,6 +20530,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request), line:460:11, endln:460:53 |vpiName:get_command_request + |vpiName:$root.tb.dut.slave_1.get_command_request + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_request |vpiOperand: \_ref_obj: (work@test_program.get_command_from_slave_1.REQ_WRITE), line:460:57, endln:460:66 |vpiParent: @@ -20559,7 +20563,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:461:10, endln:461:19 |vpiParent: \_assignment: , line:461:10, endln:461:27 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:461:14, endln:461:19 |vpiParent: @@ -20574,13 +20577,14 @@ design: (work@top) |vpiName:trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiStmt: \_for_stmt: (work@test_program.get_command_from_slave_1), line:462:10, endln:462:13 |vpiParent: \_begin: (work@test_program.get_command_from_slave_1), line:460:68, endln:466:10 |vpiFullName:work@test_program.get_command_from_slave_1 |vpiForInitStmt: - \_assign_stmt: , line:462:14, endln:462:23 + \_assignment: , line:462:14, endln:462:23 |vpiParent: \_for_stmt: (work@test_program.get_command_from_slave_1), line:462:10, endln:462:13 |vpiRhs: @@ -20588,7 +20592,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_command_from_slave_1.i), line:462:18, endln:462:19 |vpiParent: - \_assign_stmt: , line:462:14, endln:462:23 + \_assignment: , line:462:14, endln:462:23 |vpiTypespec: \_ref_typespec: (work@test_program.get_command_from_slave_1.i) |vpiParent: @@ -20629,7 +20633,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:462:29, endln:462:43 |vpiParent: \_operation: , line:462:25, endln:462:43 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:462:29, endln:462:32 |vpiParent: @@ -20645,6 +20648,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.get_command_from_slave_1), line:462:50, endln:465:13 |vpiParent: @@ -20660,8 +20664,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data), line:463:32, endln:463:72 |vpiParent: \_assignment: , line:463:13, endln:463:72 - |vpiName:$root.tb.dut.slave_1.get_command_data - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data |vpiActual: \_ref_obj: ($root), line:463:38, endln:463:40 |vpiParent: @@ -20687,11 +20689,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data), line:463:32, endln:463:72 |vpiName:get_command_data + |vpiName:$root.tb.dut.slave_1.get_command_data + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_data |vpiLhs: \_hier_path: (cmd.data[i]), line:463:13, endln:463:24 |vpiParent: \_assignment: , line:463:13, endln:463:72 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:463:17, endln:463:21 |vpiParent: @@ -20715,6 +20718,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_1.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_1.i), line:462:18, endln:462:19 + |vpiName:cmd.data[i] |vpiStmt: \_assignment: , line:464:13, endln:464:79 |vpiParent: @@ -20725,8 +20729,6 @@ design: (work@top) \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable), line:464:32, endln:464:79 |vpiParent: \_assignment: , line:464:13, endln:464:79 - |vpiName:$root.tb.dut.slave_1.get_command_byte_enable - |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable |vpiActual: \_ref_obj: ($root), line:464:38, endln:464:40 |vpiParent: @@ -20752,11 +20754,12 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable), line:464:32, endln:464:79 |vpiName:get_command_byte_enable + |vpiName:$root.tb.dut.slave_1.get_command_byte_enable + |vpiFullName:work@test_program.get_command_from_slave_1.$root.tb.dut.slave_1.get_command_byte_enable |vpiLhs: \_hier_path: (cmd.byteenable[i]), line:464:13, endln:464:30 |vpiParent: \_assignment: , line:464:13, endln:464:79 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:464:17, endln:464:27 |vpiParent: @@ -20780,6 +20783,7 @@ design: (work@top) |vpiFullName:work@test_program.get_command_from_slave_1.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.get_command_from_slave_1.i), line:462:18, endln:462:19 + |vpiName:cmd.byteenable[i] |vpiElseStmt: \_begin: (work@test_program.get_command_from_slave_1), line:466:16, endln:468:10 |vpiParent: @@ -20803,7 +20807,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:467:10, endln:467:19 |vpiParent: \_assignment: , line:467:10, endln:467:26 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:467:14, endln:467:19 |vpiParent: @@ -20818,6 +20821,7 @@ design: (work@top) |vpiName:trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiStmt: \_return_stmt: , line:470:7, endln:470:13 |vpiParent: @@ -20907,7 +20911,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:490:52, endln:490:66 |vpiParent: \_func_call: ($root.tb.dut.slave_1.set_response_burst_size), line:490:7, endln:490:67 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:490:52, endln:490:55 |vpiParent: @@ -20923,6 +20926,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiName:$root.tb.dut.slave_1.set_response_burst_size |vpiStmt: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_1), line:491:7, endln:491:10 @@ -20930,7 +20934,7 @@ design: (work@top) \_begin: (work@test_program.configure_and_push_response_to_slave_1), line:489:7, endln:489:59 |vpiFullName:work@test_program.configure_and_push_response_to_slave_1 |vpiForInitStmt: - \_assign_stmt: , line:491:12, endln:491:21 + \_assignment: , line:491:12, endln:491:21 |vpiParent: \_for_stmt: (work@test_program.configure_and_push_response_to_slave_1), line:491:7, endln:491:10 |vpiRhs: @@ -20938,7 +20942,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 |vpiParent: - \_assign_stmt: , line:491:12, endln:491:21 + \_assignment: , line:491:12, endln:491:21 |vpiTypespec: \_ref_typespec: (work@test_program.configure_and_push_response_to_slave_1.i) |vpiParent: @@ -20979,7 +20983,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:491:27, endln:491:41 |vpiParent: \_operation: , line:491:23, endln:491:41 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:491:27, endln:491:30 |vpiParent: @@ -20995,6 +20998,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiStmt: \_begin: (work@test_program.configure_and_push_response_to_slave_1), line:491:48, endln:502:10 |vpiParent: @@ -21008,7 +21012,6 @@ design: (work@top) \_hier_path: (rsp.data[i]), line:492:49, endln:492:60 |vpiParent: \_func_call: ($root.tb.dut.slave_1.set_response_data), line:492:10, endln:492:64 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:492:49, endln:492:52 |vpiParent: @@ -21032,6 +21035,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.data[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.i), line:492:62, endln:492:63 |vpiParent: @@ -21078,7 +21082,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:495:55, endln:495:69 |vpiParent: \_operation: , line:495:55, endln:495:99 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:495:55, endln:495:58 |vpiParent: @@ -21102,6 +21105,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.pending_read_cycles_slave_1), line:495:72, endln:495:99 |vpiParent: @@ -21129,7 +21133,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:496:37, endln:496:51 |vpiParent: \_assignment: , line:496:13, endln:496:51 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:496:37, endln:496:40 |vpiParent: @@ -21153,6 +21156,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiLhs: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.read_response_latency), line:496:13, endln:496:34 |vpiParent: @@ -21174,7 +21178,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:498:55, endln:498:69 |vpiParent: \_func_call: ($root.tb.dut.slave_1.set_response_latency), line:498:13, endln:498:73 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:498:55, endln:498:58 |vpiParent: @@ -21198,6 +21201,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiArgument: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.i), line:498:71, endln:498:72 |vpiParent: @@ -21222,7 +21226,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:499:37, endln:499:51 |vpiParent: \_operation: , line:499:37, endln:499:75 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:499:37, endln:499:40 |vpiParent: @@ -21246,6 +21249,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.configure_and_push_response_to_slave_1.i), line:491:16, endln:491:17 + |vpiName:rsp.latency[i] |vpiOperand: \_ref_obj: (work@test_program.configure_and_push_response_to_slave_1.read_response_latency), line:499:54, endln:499:75 |vpiParent: @@ -21308,7 +21312,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:504:91, endln:504:105 |vpiParent: \_operation: , line:504:37, endln:504:105 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:504:91, endln:504:94 |vpiParent: @@ -21324,6 +21327,7 @@ design: (work@top) |vpiFullName:work@test_program.configure_and_push_response_to_slave_1.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:rsp.burstcount |vpiOperand: \_constant: , line:504:108, endln:504:109 |vpiLhs: @@ -21528,7 +21532,7 @@ design: (work@top) \_begin: (work@test_program.master_send_commands), line:551:7, endln:551:32 |vpiFullName:work@test_program.master_send_commands |vpiForInitStmt: - \_assign_stmt: , line:554:12, endln:554:21 + \_assignment: , line:554:12, endln:554:21 |vpiParent: \_for_stmt: (work@test_program.master_send_commands), line:554:7, endln:554:10 |vpiRhs: @@ -21536,7 +21540,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.master_send_commands.i), line:554:16, endln:554:17 |vpiParent: - \_assign_stmt: , line:554:12, endln:554:21 + \_assignment: , line:554:12, endln:554:21 |vpiTypespec: \_ref_typespec: (work@test_program.master_send_commands.i) |vpiParent: @@ -21851,7 +21855,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:579:10, endln:579:24 |vpiParent: \_assignment: , line:579:10, endln:579:61 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:579:14, endln:579:24 |vpiParent: @@ -21866,6 +21869,7 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiElseStmt: \_begin: (work@test_program.create_command), line:580:16, endln:582:10 |vpiParent: @@ -21883,7 +21887,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:581:10, endln:581:24 |vpiParent: \_assignment: , line:581:10, endln:581:40 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:581:14, endln:581:24 |vpiParent: @@ -21898,6 +21901,7 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_assignment: , line:584:7, endln:584:41 |vpiParent: @@ -21916,7 +21920,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:584:7, endln:584:16 |vpiParent: \_assignment: , line:584:7, endln:584:41 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:584:11, endln:584:16 |vpiParent: @@ -21931,6 +21934,7 @@ design: (work@top) |vpiName:trans |vpiActual: \_io_decl: (trans), line:571:22, endln:571:27 + |vpiName:cmd.trans |vpiStmt: \_assignment: , line:585:7, endln:585:77 |vpiParent: @@ -21956,7 +21960,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:585:7, endln:585:15 |vpiParent: \_assignment: , line:585:7, endln:585:77 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:585:11, endln:585:15 |vpiParent: @@ -21971,6 +21974,7 @@ design: (work@top) |vpiName:addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiStmt: \_assignment: , line:586:7, endln:586:71 |vpiParent: @@ -21996,7 +22000,6 @@ design: (work@top) \_hier_path: (cmd.cmd_delay), line:586:7, endln:586:20 |vpiParent: \_assignment: , line:586:7, endln:586:71 - |vpiName:cmd.cmd_delay |vpiActual: \_ref_obj: (cmd), line:586:11, endln:586:20 |vpiParent: @@ -22011,6 +22014,7 @@ design: (work@top) |vpiName:cmd_delay |vpiActual: \_typespec_member: (cmd_delay), line:52:37, endln:52:46 + |vpiName:cmd.cmd_delay |vpiStmt: \_if_else: , line:588:7, endln:596:10 |vpiParent: @@ -22047,7 +22051,7 @@ design: (work@top) \_begin: (work@test_program.create_command), line:588:27, endln:594:10 |vpiFullName:work@test_program.create_command |vpiForInitStmt: - \_assign_stmt: , line:589:15, endln:589:24 + \_assignment: , line:589:15, endln:589:24 |vpiParent: \_for_stmt: (work@test_program.create_command), line:589:10, endln:589:13 |vpiRhs: @@ -22055,7 +22059,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 |vpiParent: - \_assign_stmt: , line:589:15, endln:589:24 + \_assignment: , line:589:15, endln:589:24 |vpiTypespec: \_ref_typespec: (work@test_program.create_command.i) |vpiParent: @@ -22096,7 +22100,6 @@ design: (work@top) \_hier_path: (cmd.burstcount), line:589:30, endln:589:44 |vpiParent: \_operation: , line:589:26, endln:589:44 - |vpiName:cmd.burstcount |vpiActual: \_ref_obj: (cmd), line:589:30, endln:589:33 |vpiParent: @@ -22112,6 +22115,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:cmd.burstcount |vpiStmt: \_begin: (work@test_program.create_command), line:589:51, endln:593:13 |vpiParent: @@ -22132,7 +22136,6 @@ design: (work@top) \_hier_path: (cmd.data[i]), line:590:13, endln:590:24 |vpiParent: \_assignment: , line:590:13, endln:590:43 - |vpiName:cmd.data[i] |vpiActual: \_ref_obj: (cmd), line:590:17, endln:590:21 |vpiParent: @@ -22156,6 +22159,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.cmd.data[i].i |vpiActual: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 + |vpiName:cmd.data[i] |vpiStmt: \_assignment: , line:591:13, endln:591:55 |vpiParent: @@ -22186,7 +22190,6 @@ design: (work@top) \_hier_path: (cmd.byteenable[i]), line:591:13, endln:591:30 |vpiParent: \_assignment: , line:591:13, endln:591:55 - |vpiName:cmd.byteenable[i] |vpiActual: \_ref_obj: (cmd), line:591:17, endln:591:27 |vpiParent: @@ -22210,6 +22213,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 + |vpiName:cmd.byteenable[i] |vpiStmt: \_assignment: , line:592:13, endln:592:68 |vpiParent: @@ -22235,7 +22239,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[i]), line:592:13, endln:592:30 |vpiParent: \_assignment: , line:592:13, endln:592:68 - |vpiName:cmd.data_idles[i] |vpiActual: \_ref_obj: (cmd), line:592:17, endln:592:27 |vpiParent: @@ -22259,6 +22262,7 @@ design: (work@top) |vpiFullName:work@test_program.create_command.cmd.data_idles[i].i |vpiActual: \_int_var: (work@test_program.create_command.i), line:589:19, endln:589:20 + |vpiName:cmd.data_idles[i] |vpiElseStmt: \_begin: (work@test_program.create_command), line:594:16, endln:596:10 |vpiParent: @@ -22289,7 +22293,6 @@ design: (work@top) \_hier_path: (cmd.data_idles[0]), line:595:10, endln:595:27 |vpiParent: \_assignment: , line:595:10, endln:595:68 - |vpiName:cmd.data_idles[0] |vpiActual: \_ref_obj: (cmd), line:595:14, endln:595:24 |vpiParent: @@ -22307,6 +22310,7 @@ design: (work@top) \_typespec_member: (data_idles), line:53:37, endln:53:63 |vpiIndex: \_constant: , line:595:25, endln:595:26 + |vpiName:cmd.data_idles[0] |vpiStmt: \_return_stmt: , line:598:7, endln:598:13 |vpiParent: @@ -22775,7 +22779,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:636:14, endln:636:23 |vpiParent: \_operation: , line:636:14, endln:636:32 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:636:14, endln:636:17 |vpiParent: @@ -22791,6 +22794,7 @@ design: (work@top) |vpiFullName:work@test_program.save_command_master.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.save_command_master.WRITE), line:636:27, endln:636:32 |vpiParent: @@ -22906,7 +22910,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:649:52, endln:649:60 |vpiParent: \_func_call: (translate_master_to_slave_address), line:649:18, endln:649:61 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:649:52, endln:649:55 |vpiParent: @@ -22922,6 +22925,7 @@ design: (work@top) |vpiFullName:work@test_program.save_command_slave.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiName:translate_master_to_slave_address |vpiFunction: \_function: (work@test_program.translate_master_to_slave_address), line:658:4, endln:668:15 @@ -22929,7 +22933,6 @@ design: (work@top) \_hier_path: (cmd.addr), line:649:7, endln:649:15 |vpiParent: \_assignment: , line:649:7, endln:649:61 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:649:11, endln:649:15 |vpiParent: @@ -22944,6 +22947,7 @@ design: (work@top) |vpiName:addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiStmt: \_if_else: , line:650:7, endln:654:10 |vpiParent: @@ -22957,7 +22961,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:650:11, endln:650:20 |vpiParent: \_operation: , line:650:11, endln:650:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:650:11, endln:650:14 |vpiParent: @@ -22973,6 +22976,7 @@ design: (work@top) |vpiFullName:work@test_program.save_command_slave.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.save_command_slave.WRITE), line:650:24, endln:650:29 |vpiParent: @@ -23144,13 +23148,15 @@ design: (work@top) |vpiName:offset |vpiFullName:work@test_program.translate_master_to_slave_address.offset |vpiStmt: - \_assign_stmt: , line:661:11, endln:661:39 + \_assignment: , line:661:11, endln:661:39 |vpiParent: \_begin: (work@test_program.translate_master_to_slave_address), line:662:7, endln:662:44 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:661:22, endln:661:39 |vpiParent: - \_assign_stmt: , line:661:11, endln:661:39 + \_assignment: , line:661:11, endln:661:39 |vpiOpType:12 |vpiOperand: \_ref_obj: (work@test_program.translate_master_to_slave_address.addr), line:661:22, endln:661:26 @@ -23171,7 +23177,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.translate_master_to_slave_address.slave_id), line:661:11, endln:661:19 |vpiParent: - \_assign_stmt: , line:661:11, endln:661:39 + \_assignment: , line:661:11, endln:661:39 |vpiTypespec: \_ref_typespec: (work@test_program.translate_master_to_slave_address.slave_id) |vpiParent: @@ -23489,15 +23495,17 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_command_for_slave.found |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:688:11, endln:688:20 + \_assignment: , line:688:11, endln:688:20 |vpiParent: \_begin: (work@test_program.get_expected_command_for_slave), line:688:7, endln:688:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:688:19, endln:688:20 |vpiLhs: \_int_var: (work@test_program.get_expected_command_for_slave.found), line:688:11, endln:688:16 |vpiParent: - \_assign_stmt: , line:688:11, endln:688:20 + \_assignment: , line:688:11, endln:688:20 |vpiTypespec: \_ref_typespec: (work@test_program.get_expected_command_for_slave.found) |vpiParent: @@ -23521,7 +23529,6 @@ design: (work@top) \_hier_path: (cmd.trans), line:690:11, endln:690:20 |vpiParent: \_operation: , line:690:11, endln:690:29 - |vpiName:cmd.trans |vpiActual: \_ref_obj: (cmd), line:690:11, endln:690:14 |vpiParent: @@ -23537,6 +23544,7 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_command_for_slave.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:cmd.trans |vpiOperand: \_ref_obj: (work@test_program.get_expected_command_for_slave.WRITE), line:690:24, endln:690:29 |vpiParent: @@ -23654,7 +23662,6 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:693:17, endln:693:29 |vpiParent: \_operation: , line:693:17, endln:693:41 - |vpiName:exp_cmd.addr |vpiActual: \_ref_obj: (exp_cmd), line:693:17, endln:693:24 |vpiParent: @@ -23670,11 +23677,11 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_command_for_slave.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:exp_cmd.addr |vpiOperand: \_hier_path: (cmd.addr), line:693:33, endln:693:41 |vpiParent: \_operation: , line:693:17, endln:693:41 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:693:33, endln:693:36 |vpiParent: @@ -23690,6 +23697,7 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_command_for_slave.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiStmt: \_begin: (work@test_program.get_expected_command_for_slave), line:693:43, endln:697:16 |vpiParent: @@ -23770,7 +23778,6 @@ design: (work@top) \_hier_path: (write_command_queue_slave[slave_id].pop_front), line:700:23, endln:700:70 |vpiParent: \_assignment: , line:700:13, endln:700:70 - |vpiName:write_command_queue_slave[slave_id].pop_front |vpiActual: \_bit_select: (write_command_queue_slave[slave_id]), line:700:23, endln:700:48 |vpiParent: @@ -23792,6 +23799,7 @@ design: (work@top) |vpiParent: \_hier_path: (write_command_queue_slave[slave_id].pop_front), line:700:23, endln:700:70 |vpiName:pop_front + |vpiName:write_command_queue_slave[slave_id].pop_front |vpiLhs: \_ref_obj: (work@test_program.get_expected_command_for_slave.exp_cmd), line:700:13, endln:700:20 |vpiParent: @@ -23909,7 +23917,6 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:705:17, endln:705:29 |vpiParent: \_operation: , line:705:17, endln:705:41 - |vpiName:exp_cmd.addr |vpiActual: \_ref_obj: (exp_cmd), line:705:17, endln:705:24 |vpiParent: @@ -23925,11 +23932,11 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_command_for_slave.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:exp_cmd.addr |vpiOperand: \_hier_path: (cmd.addr), line:705:33, endln:705:41 |vpiParent: \_operation: , line:705:17, endln:705:41 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:705:33, endln:705:36 |vpiParent: @@ -23945,6 +23952,7 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_command_for_slave.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiStmt: \_begin: (work@test_program.get_expected_command_for_slave), line:705:43, endln:709:16 |vpiParent: @@ -24025,7 +24033,6 @@ design: (work@top) \_hier_path: (read_command_queue_slave[slave_id].pop_front), line:712:23, endln:712:69 |vpiParent: \_assignment: , line:712:13, endln:712:69 - |vpiName:read_command_queue_slave[slave_id].pop_front |vpiActual: \_bit_select: (read_command_queue_slave[slave_id]), line:712:23, endln:712:47 |vpiParent: @@ -24047,6 +24054,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_command_queue_slave[slave_id].pop_front), line:712:23, endln:712:69 |vpiName:pop_front + |vpiName:read_command_queue_slave[slave_id].pop_front |vpiLhs: \_ref_obj: (work@test_program.get_expected_command_for_slave.exp_cmd), line:712:13, endln:712:20 |vpiParent: @@ -24118,7 +24126,6 @@ design: (work@top) \_hier_path: (exp_cmd.addr), line:723:38, endln:723:50 |vpiParent: \_task_call: (assert_equals), line:723:7, endln:723:68 - |vpiName:exp_cmd.addr |vpiActual: \_ref_obj: (exp_cmd), line:723:38, endln:723:45 |vpiParent: @@ -24134,11 +24141,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:exp_cmd.addr |vpiArgument: \_hier_path: (actual_cmd.addr), line:723:52, endln:723:67 |vpiParent: \_task_call: (assert_equals), line:723:7, endln:723:68 - |vpiName:actual_cmd.addr |vpiActual: \_ref_obj: (actual_cmd), line:723:52, endln:723:62 |vpiParent: @@ -24154,6 +24161,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:actual_cmd.addr |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -24167,7 +24175,6 @@ design: (work@top) \_hier_path: (exp_cmd.burstcount), line:724:41, endln:724:59 |vpiParent: \_task_call: (assert_equals), line:724:7, endln:724:83 - |vpiName:exp_cmd.burstcount |vpiActual: \_ref_obj: (exp_cmd), line:724:41, endln:724:48 |vpiParent: @@ -24183,11 +24190,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:exp_cmd.burstcount |vpiArgument: \_hier_path: (actual_cmd.burstcount), line:724:61, endln:724:82 |vpiParent: \_task_call: (assert_equals), line:724:7, endln:724:83 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:724:61, endln:724:71 |vpiParent: @@ -24203,6 +24210,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:actual_cmd.burstcount |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -24219,7 +24227,6 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:726:11, endln:726:27 |vpiParent: \_operation: , line:726:11, endln:726:36 - |vpiName:actual_cmd.trans |vpiActual: \_ref_obj: (actual_cmd), line:726:11, endln:726:21 |vpiParent: @@ -24235,6 +24242,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:actual_cmd.trans |vpiOperand: \_ref_obj: (work@test_program.verify_command.WRITE), line:726:31, endln:726:36 |vpiParent: @@ -24254,7 +24262,7 @@ design: (work@top) \_begin: (work@test_program.verify_command), line:726:38, endln:731:10 |vpiFullName:work@test_program.verify_command |vpiForInitStmt: - \_assign_stmt: , line:727:15, endln:727:24 + \_assignment: , line:727:15, endln:727:24 |vpiParent: \_for_stmt: (work@test_program.verify_command), line:727:10, endln:727:13 |vpiRhs: @@ -24262,7 +24270,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 |vpiParent: - \_assign_stmt: , line:727:15, endln:727:24 + \_assignment: , line:727:15, endln:727:24 |vpiTypespec: \_ref_typespec: (work@test_program.verify_command.i) |vpiParent: @@ -24303,7 +24311,6 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:727:30, endln:727:51 |vpiParent: \_operation: , line:727:26, endln:727:51 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:727:30, endln:727:40 |vpiParent: @@ -24319,6 +24326,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:actual_cmd.burstcount |vpiStmt: \_begin: (work@test_program.verify_command), line:727:58, endln:730:13 |vpiParent: @@ -24334,7 +24342,6 @@ design: (work@top) \_hier_path: (exp_cmd.data[i]), line:728:47, endln:728:62 |vpiParent: \_task_call: (assert_equals), line:728:13, endln:728:83 - |vpiName:exp_cmd.data[i] |vpiActual: \_ref_obj: (exp_cmd), line:728:47, endln:728:54 |vpiParent: @@ -24358,11 +24365,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.exp_cmd.data[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:exp_cmd.data[i] |vpiArgument: \_hier_path: (actual_cmd.data[i]), line:728:64, endln:728:82 |vpiParent: \_task_call: (assert_equals), line:728:13, endln:728:83 - |vpiName:actual_cmd.data[i] |vpiActual: \_ref_obj: (actual_cmd), line:728:64, endln:728:74 |vpiParent: @@ -24386,6 +24393,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.actual_cmd.data[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:actual_cmd.data[i] |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -24399,7 +24407,6 @@ design: (work@top) \_hier_path: (exp_cmd.byteenable[i]), line:729:47, endln:729:68 |vpiParent: \_task_call: (assert_equals), line:729:13, endln:729:95 - |vpiName:exp_cmd.byteenable[i] |vpiActual: \_ref_obj: (exp_cmd), line:729:47, endln:729:54 |vpiParent: @@ -24423,11 +24430,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.exp_cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:exp_cmd.byteenable[i] |vpiArgument: \_hier_path: (actual_cmd.byteenable[i]), line:729:70, endln:729:94 |vpiParent: \_task_call: (assert_equals), line:729:13, endln:729:95 - |vpiName:actual_cmd.byteenable[i] |vpiActual: \_ref_obj: (actual_cmd), line:729:70, endln:729:80 |vpiParent: @@ -24451,6 +24458,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_command.actual_cmd.byteenable[i].i |vpiActual: \_int_var: (work@test_program.verify_command.i), line:727:19, endln:727:20 + |vpiName:actual_cmd.byteenable[i] |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -24730,7 +24738,6 @@ design: (work@top) \_hier_path: (rsp.burstcount), line:765:7, endln:765:21 |vpiParent: \_assignment: , line:765:7, endln:765:40 - |vpiName:rsp.burstcount |vpiActual: \_ref_obj: (rsp), line:765:11, endln:765:21 |vpiParent: @@ -24745,13 +24752,14 @@ design: (work@top) |vpiName:burstcount |vpiActual: \_io_decl: (burstcount), line:760:18, endln:760:28 + |vpiName:rsp.burstcount |vpiStmt: \_for_stmt: (work@test_program.create_response), line:766:7, endln:766:10 |vpiParent: \_begin: (work@test_program.create_response), line:765:7, endln:765:41 |vpiFullName:work@test_program.create_response |vpiForInitStmt: - \_assign_stmt: , line:766:12, endln:766:21 + \_assignment: , line:766:12, endln:766:21 |vpiParent: \_for_stmt: (work@test_program.create_response), line:766:7, endln:766:10 |vpiRhs: @@ -24759,7 +24767,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.create_response.i), line:766:16, endln:766:17 |vpiParent: - \_assign_stmt: , line:766:12, endln:766:21 + \_assignment: , line:766:12, endln:766:21 |vpiTypespec: \_ref_typespec: (work@test_program.create_response.i) |vpiParent: @@ -24824,7 +24832,6 @@ design: (work@top) \_hier_path: (rsp.data[i]), line:767:10, endln:767:21 |vpiParent: \_assignment: , line:767:10, endln:767:37 - |vpiName:rsp.data[i] |vpiActual: \_ref_obj: (rsp), line:767:14, endln:767:18 |vpiParent: @@ -24848,6 +24855,7 @@ design: (work@top) |vpiFullName:work@test_program.create_response.rsp.data[i].i |vpiActual: \_int_var: (work@test_program.create_response.i), line:766:16, endln:766:17 + |vpiName:rsp.data[i] |vpiStmt: \_assignment: , line:768:10, endln:768:62 |vpiParent: @@ -24873,7 +24881,6 @@ design: (work@top) \_hier_path: (rsp.latency[i]), line:768:10, endln:768:24 |vpiParent: \_assignment: , line:768:10, endln:768:62 - |vpiName:rsp.latency[i] |vpiActual: \_ref_obj: (rsp), line:768:14, endln:768:21 |vpiParent: @@ -24897,6 +24904,7 @@ design: (work@top) |vpiFullName:work@test_program.create_response.rsp.latency[i].i |vpiActual: \_int_var: (work@test_program.create_response.i), line:766:16, endln:766:17 + |vpiName:rsp.latency[i] |vpiStmt: \_return_stmt: , line:771:7, endln:771:13 |vpiParent: @@ -24994,19 +25002,20 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_read_response.slave_id |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:779:16, endln:779:48 + \_assignment: , line:779:16, endln:779:48 |vpiParent: \_begin: (work@test_program.get_expected_read_response), line:779:7, endln:779:49 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:779:27, endln:779:48 |vpiParent: - \_assign_stmt: , line:779:16, endln:779:48 + \_assignment: , line:779:16, endln:779:48 |vpiOpType:12 |vpiOperand: \_hier_path: (cmd.addr), line:779:27, endln:779:35 |vpiParent: \_operation: , line:779:27, endln:779:48 - |vpiName:cmd.addr |vpiActual: \_ref_obj: (cmd), line:779:27, endln:779:30 |vpiParent: @@ -25022,6 +25031,7 @@ design: (work@top) |vpiFullName:work@test_program.get_expected_read_response.addr |vpiActual: \_typespec_member: (addr), line:49:37, endln:49:41 + |vpiName:cmd.addr |vpiOperand: \_ref_obj: (work@test_program.get_expected_read_response.SLAVE_SPAN), line:779:38, endln:779:48 |vpiParent: @@ -25033,7 +25043,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.get_expected_read_response.slave_id), line:779:16, endln:779:24 |vpiParent: - \_assign_stmt: , line:779:16, endln:779:48 + \_assignment: , line:779:16, endln:779:48 |vpiTypespec: \_ref_typespec: (work@test_program.get_expected_read_response.slave_id) |vpiParent: @@ -25054,7 +25064,6 @@ design: (work@top) \_hier_path: (read_response_queue_slave[slave_id].pop_front), line:781:13, endln:781:60 |vpiParent: \_assignment: , line:781:7, endln:781:60 - |vpiName:read_response_queue_slave[slave_id].pop_front |vpiActual: \_bit_select: (read_response_queue_slave[slave_id]), line:781:13, endln:781:38 |vpiParent: @@ -25076,6 +25085,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_response_queue_slave[slave_id].pop_front), line:781:13, endln:781:60 |vpiName:pop_front + |vpiName:read_response_queue_slave[slave_id].pop_front |vpiLhs: \_ref_obj: (work@test_program.get_expected_read_response.rsp), line:781:7, endln:781:10 |vpiParent: @@ -25147,7 +25157,6 @@ design: (work@top) \_hier_path: (exp_rsp.burstcount), line:790:41, endln:790:59 |vpiParent: \_task_call: (assert_equals), line:790:7, endln:790:83 - |vpiName:exp_rsp.burstcount |vpiActual: \_ref_obj: (exp_rsp), line:790:41, endln:790:48 |vpiParent: @@ -25163,11 +25172,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:exp_rsp.burstcount |vpiArgument: \_hier_path: (actual_rsp.burstcount), line:790:61, endln:790:82 |vpiParent: \_task_call: (assert_equals), line:790:7, endln:790:83 - |vpiName:actual_rsp.burstcount |vpiActual: \_ref_obj: (actual_rsp), line:790:61, endln:790:71 |vpiParent: @@ -25183,6 +25192,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:actual_rsp.burstcount |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -25192,7 +25202,7 @@ design: (work@top) \_begin: (work@test_program.verify_response), line:791:7, endln:793:10 |vpiFullName:work@test_program.verify_response |vpiForInitStmt: - \_assign_stmt: , line:791:12, endln:791:21 + \_assignment: , line:791:12, endln:791:21 |vpiParent: \_for_stmt: (work@test_program.verify_response), line:791:7, endln:791:10 |vpiRhs: @@ -25200,7 +25210,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.verify_response.i), line:791:16, endln:791:17 |vpiParent: - \_assign_stmt: , line:791:12, endln:791:21 + \_assignment: , line:791:12, endln:791:21 |vpiTypespec: \_ref_typespec: (work@test_program.verify_response.i) |vpiParent: @@ -25241,7 +25251,6 @@ design: (work@top) \_hier_path: (actual_rsp.burstcount), line:791:27, endln:791:48 |vpiParent: \_operation: , line:791:23, endln:791:48 - |vpiName:actual_rsp.burstcount |vpiActual: \_ref_obj: (actual_rsp), line:791:27, endln:791:37 |vpiParent: @@ -25257,6 +25266,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.burstcount |vpiActual: \_typespec_member: (burstcount), line:58:37, endln:58:47 + |vpiName:actual_rsp.burstcount |vpiStmt: \_begin: (work@test_program.verify_response), line:791:55, endln:793:10 |vpiParent: @@ -25272,7 +25282,6 @@ design: (work@top) \_hier_path: (exp_rsp.data[i]), line:792:43, endln:792:58 |vpiParent: \_task_call: (assert_equals), line:792:10, endln:792:79 - |vpiName:exp_rsp.data[i] |vpiActual: \_ref_obj: (exp_rsp), line:792:43, endln:792:50 |vpiParent: @@ -25296,11 +25305,11 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.exp_rsp.data[i].i |vpiActual: \_int_var: (work@test_program.verify_response.i), line:791:16, endln:791:17 + |vpiName:exp_rsp.data[i] |vpiArgument: \_hier_path: (actual_rsp.data[i]), line:792:60, endln:792:78 |vpiParent: \_task_call: (assert_equals), line:792:10, endln:792:79 - |vpiName:actual_rsp.data[i] |vpiActual: \_ref_obj: (actual_rsp), line:792:60, endln:792:70 |vpiParent: @@ -25324,6 +25333,7 @@ design: (work@top) |vpiFullName:work@test_program.verify_response.actual_rsp.data[i].i |vpiActual: \_int_var: (work@test_program.verify_response.i), line:791:16, endln:791:17 + |vpiName:actual_rsp.data[i] |vpiName:assert_equals |vpiTask: \_task: (work@test_program.assert_equals), line:735:4, endln:757:11 @@ -25342,8 +25352,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_read_response_complete), line:249:13, endln:249:64 |vpiParent: \_event_control: , line:249:11, endln:249:65 - |vpiName:$root.tb.dut.master_0.signal_read_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_read_response_complete |vpiActual: \_ref_obj: ($root), line:249:19, endln:249:21 |vpiParent: @@ -25369,6 +25377,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_read_response_complete), line:249:13, endln:249:64 |vpiName:signal_read_response_complete + |vpiName:$root.tb.dut.master_0.signal_read_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_read_response_complete |vpiStmt: \_begin: (work@test_program), line:249:66, endln:258:7 |vpiParent: @@ -25423,7 +25433,6 @@ design: (work@top) \_hier_path: (read_command_queue_master[0].pop_front), line:254:13, endln:254:53 |vpiParent: \_assignment: , line:254:7, endln:254:53 - |vpiName:read_command_queue_master[0].pop_front |vpiActual: \_bit_select: (read_command_queue_master[0]), line:254:13, endln:254:38 |vpiParent: @@ -25439,6 +25448,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_command_queue_master[0].pop_front), line:254:13, endln:254:53 |vpiName:pop_front + |vpiName:read_command_queue_master[0].pop_front |vpiLhs: \_ref_obj: (work@test_program.cmd), line:254:7, endln:254:10 |vpiParent: @@ -25533,8 +25543,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_write_response_complete), line:261:13, endln:261:65 |vpiParent: \_event_control: , line:261:11, endln:261:66 - |vpiName:$root.tb.dut.master_0.signal_write_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_write_response_complete |vpiActual: \_ref_obj: ($root), line:261:19, endln:261:21 |vpiParent: @@ -25560,6 +25568,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_0.signal_write_response_complete), line:261:13, endln:261:65 |vpiName:signal_write_response_complete + |vpiName:$root.tb.dut.master_0.signal_write_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_0.signal_write_response_complete |vpiStmt: \_begin: (work@test_program), line:261:67, endln:263:7 |vpiParent: @@ -25583,8 +25593,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.slave_0.signal_command_received), line:282:13, endln:282:57 |vpiParent: \_event_control: , line:282:11, endln:282:58 - |vpiName:$root.tb.dut.slave_0.signal_command_received - |vpiFullName:work@test_program.$root.tb.dut.slave_0.signal_command_received |vpiActual: \_ref_obj: ($root), line:282:19, endln:282:21 |vpiParent: @@ -25610,6 +25618,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.slave_0.signal_command_received), line:282:13, endln:282:57 |vpiName:signal_command_received + |vpiName:$root.tb.dut.slave_0.signal_command_received + |vpiFullName:work@test_program.$root.tb.dut.slave_0.signal_command_received |vpiStmt: \_begin: (work@test_program), line:282:59, endln:305:7 |vpiParent: @@ -25675,7 +25685,7 @@ design: (work@top) \_begin: (work@test_program), line:282:59, endln:305:7 |vpiFullName:work@test_program |vpiForInitStmt: - \_assign_stmt: , line:290:12, endln:290:21 + \_assignment: , line:290:12, endln:290:21 |vpiParent: \_for_stmt: (work@test_program), line:290:7, endln:290:10 |vpiRhs: @@ -25683,7 +25693,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.i), line:290:16, endln:290:17 |vpiParent: - \_assign_stmt: , line:290:12, endln:290:21 + \_assignment: , line:290:12, endln:290:21 |vpiTypespec: \_ref_typespec: (work@test_program.i) |vpiParent: @@ -25871,7 +25881,6 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:300:11, endln:300:27 |vpiParent: \_operation: , line:300:11, endln:300:35 - |vpiName:actual_cmd.trans |vpiActual: \_ref_obj: (actual_cmd), line:300:11, endln:300:21 |vpiParent: @@ -25887,6 +25896,7 @@ design: (work@top) |vpiFullName:work@test_program.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:actual_cmd.trans |vpiOperand: \_ref_obj: (work@test_program.READ), line:300:31, endln:300:35 |vpiParent: @@ -25914,7 +25924,6 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:301:32, endln:301:53 |vpiParent: \_func_call: (create_response), line:301:16, endln:301:54 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:301:32, endln:301:42 |vpiParent: @@ -25930,6 +25939,7 @@ design: (work@top) |vpiFullName:work@test_program.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:actual_cmd.burstcount |vpiName:create_response |vpiFunction: \_function: (work@test_program.create_response), line:759:4, endln:772:15 @@ -25995,8 +26005,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:333:21, endln:333:41 |vpiParent: \_operation: , line:333:13, endln:333:41 - |vpiName:$root.tb.dut.clk_clk - |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiActual: \_ref_obj: ($root), line:333:27, endln:333:29 |vpiParent: @@ -26017,6 +26025,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:333:21, endln:333:41 |vpiName:clk_clk + |vpiName:$root.tb.dut.clk_clk + |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiStmt: \_begin: (work@test_program), line:333:43, endln:337:7 |vpiParent: @@ -26072,8 +26082,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_read_response_complete), line:392:13, endln:392:64 |vpiParent: \_event_control: , line:392:11, endln:392:65 - |vpiName:$root.tb.dut.master_1.signal_read_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_read_response_complete |vpiActual: \_ref_obj: ($root), line:392:19, endln:392:21 |vpiParent: @@ -26099,6 +26107,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_read_response_complete), line:392:13, endln:392:64 |vpiName:signal_read_response_complete + |vpiName:$root.tb.dut.master_1.signal_read_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_read_response_complete |vpiStmt: \_begin: (work@test_program), line:392:66, endln:401:7 |vpiParent: @@ -26153,7 +26163,6 @@ design: (work@top) \_hier_path: (read_command_queue_master[1].pop_front), line:397:13, endln:397:53 |vpiParent: \_assignment: , line:397:7, endln:397:53 - |vpiName:read_command_queue_master[1].pop_front |vpiActual: \_bit_select: (read_command_queue_master[1]), line:397:13, endln:397:38 |vpiParent: @@ -26169,6 +26178,7 @@ design: (work@top) |vpiParent: \_hier_path: (read_command_queue_master[1].pop_front), line:397:13, endln:397:53 |vpiName:pop_front + |vpiName:read_command_queue_master[1].pop_front |vpiLhs: \_ref_obj: (work@test_program.cmd), line:397:7, endln:397:10 |vpiParent: @@ -26263,8 +26273,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_write_response_complete), line:404:13, endln:404:65 |vpiParent: \_event_control: , line:404:11, endln:404:66 - |vpiName:$root.tb.dut.master_1.signal_write_response_complete - |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_write_response_complete |vpiActual: \_ref_obj: ($root), line:404:19, endln:404:21 |vpiParent: @@ -26290,6 +26298,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.master_1.signal_write_response_complete), line:404:13, endln:404:65 |vpiName:signal_write_response_complete + |vpiName:$root.tb.dut.master_1.signal_write_response_complete + |vpiFullName:work@test_program.$root.tb.dut.master_1.signal_write_response_complete |vpiStmt: \_begin: (work@test_program), line:404:67, endln:406:7 |vpiParent: @@ -26313,8 +26323,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.slave_1.signal_command_received), line:425:13, endln:425:57 |vpiParent: \_event_control: , line:425:11, endln:425:58 - |vpiName:$root.tb.dut.slave_1.signal_command_received - |vpiFullName:work@test_program.$root.tb.dut.slave_1.signal_command_received |vpiActual: \_ref_obj: ($root), line:425:19, endln:425:21 |vpiParent: @@ -26340,6 +26348,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.slave_1.signal_command_received), line:425:13, endln:425:57 |vpiName:signal_command_received + |vpiName:$root.tb.dut.slave_1.signal_command_received + |vpiFullName:work@test_program.$root.tb.dut.slave_1.signal_command_received |vpiStmt: \_begin: (work@test_program), line:425:59, endln:448:7 |vpiParent: @@ -26405,7 +26415,7 @@ design: (work@top) \_begin: (work@test_program), line:425:59, endln:448:7 |vpiFullName:work@test_program |vpiForInitStmt: - \_assign_stmt: , line:433:12, endln:433:21 + \_assignment: , line:433:12, endln:433:21 |vpiParent: \_for_stmt: (work@test_program), line:433:7, endln:433:10 |vpiRhs: @@ -26413,7 +26423,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@test_program.i), line:433:16, endln:433:17 |vpiParent: - \_assign_stmt: , line:433:12, endln:433:21 + \_assignment: , line:433:12, endln:433:21 |vpiTypespec: \_ref_typespec: (work@test_program.i) |vpiParent: @@ -26601,7 +26611,6 @@ design: (work@top) \_hier_path: (actual_cmd.trans), line:443:11, endln:443:27 |vpiParent: \_operation: , line:443:11, endln:443:35 - |vpiName:actual_cmd.trans |vpiActual: \_ref_obj: (actual_cmd), line:443:11, endln:443:21 |vpiParent: @@ -26617,6 +26626,7 @@ design: (work@top) |vpiFullName:work@test_program.trans |vpiActual: \_typespec_member: (trans), line:47:37, endln:47:42 + |vpiName:actual_cmd.trans |vpiOperand: \_ref_obj: (work@test_program.READ), line:443:31, endln:443:35 |vpiParent: @@ -26644,7 +26654,6 @@ design: (work@top) \_hier_path: (actual_cmd.burstcount), line:444:32, endln:444:53 |vpiParent: \_func_call: (create_response), line:444:16, endln:444:54 - |vpiName:actual_cmd.burstcount |vpiActual: \_ref_obj: (actual_cmd), line:444:32, endln:444:42 |vpiParent: @@ -26660,6 +26669,7 @@ design: (work@top) |vpiFullName:work@test_program.burstcount |vpiActual: \_typespec_member: (burstcount), line:48:37, endln:48:47 + |vpiName:actual_cmd.burstcount |vpiName:create_response |vpiFunction: \_function: (work@test_program.create_response), line:759:4, endln:772:15 @@ -26725,8 +26735,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:476:21, endln:476:41 |vpiParent: \_operation: , line:476:13, endln:476:41 - |vpiName:$root.tb.dut.clk_clk - |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiActual: \_ref_obj: ($root), line:476:27, endln:476:29 |vpiParent: @@ -26747,6 +26755,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.clk_clk), line:476:21, endln:476:41 |vpiName:clk_clk + |vpiName:$root.tb.dut.clk_clk + |vpiFullName:work@test_program.$root.tb.dut.clk_clk |vpiStmt: \_begin: (work@test_program), line:476:43, endln:480:7 |vpiParent: @@ -26825,8 +26835,6 @@ design: (work@top) \_hier_path: (work@test_program.$root.tb.dut.reset_reset_n), line:526:13, endln:526:39 |vpiParent: \_operation: , line:526:13, endln:526:44 - |vpiName:$root.tb.dut.reset_reset_n - |vpiFullName:work@test_program.$root.tb.dut.reset_reset_n |vpiActual: \_ref_obj: ($root), line:526:19, endln:526:21 |vpiParent: @@ -26847,6 +26855,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program.$root.tb.dut.reset_reset_n), line:526:13, endln:526:39 |vpiName:reset_reset_n + |vpiName:$root.tb.dut.reset_reset_n + |vpiFullName:work@test_program.$root.tb.dut.reset_reset_n |vpiOperand: \_constant: , line:526:43, endln:526:44 |vpiStmt: @@ -27009,8 +27019,6 @@ design: (work@top) \_hier_path: (work@test_program1.$root.tb.dut.master_02.signal_write_response_complete), line:802:13, endln:802:68 |vpiParent: \_event_control: , line:802:11, endln:802:69 - |vpiName:$root.tb.dut.master_02.signal_write_response_complete - |vpiFullName:work@test_program1.$root.tb.dut.master_02.signal_write_response_complete |vpiActual: \_ref_obj: ($root), line:802:19, endln:802:21 |vpiParent: @@ -27044,6 +27052,8 @@ design: (work@top) |vpiParent: \_hier_path: (work@test_program1.$root.tb.dut.master_02.signal_write_response_complete), line:802:13, endln:802:68 |vpiName:signal_write_response_complete + |vpiName:$root.tb.dut.master_02.signal_write_response_complete + |vpiFullName:work@test_program1.$root.tb.dut.master_02.signal_write_response_complete |vpiStmt: \_begin: (work@test_program1), line:802:70, endln:804:7 |vpiParent: diff --git a/tests/EarlgreyPackParam/EarlgreyPackParam.log b/tests/EarlgreyPackParam/EarlgreyPackParam.log index a28878073f..28c010d6f8 100644 --- a/tests/EarlgreyPackParam/EarlgreyPackParam.log +++ b/tests/EarlgreyPackParam/EarlgreyPackParam.log @@ -407,7 +407,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 5. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 4 bit_typespec 15 constant 117 @@ -436,7 +436,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 4 bit_typespec 15 constant 117 @@ -693,7 +693,7 @@ design: (work@test) |vpiParent: \_module_inst: work@aes (work@aes), file:${SURELOG_DIR}/tests/EarlgreyPackParam/dut.sv, line:49:1, endln:60:10 |vpiForInitStmt: - \_assign_stmt: , line:52:9, endln:52:21 + \_assignment: , line:52:9, endln:52:21 |vpiParent: \_gen_for: |vpiRhs: @@ -705,7 +705,7 @@ design: (work@test) |vpiLhs: \_int_var: (work@aes.i), line:52:16, endln:52:17 |vpiParent: - \_assign_stmt: , line:52:9, endln:52:21 + \_assignment: , line:52:9, endln:52:21 |vpiTypespec: \_ref_typespec: (work@aes.i) |vpiParent: diff --git a/tests/ElabCParam/ElabCParam.log b/tests/ElabCParam/ElabCParam.log index dad7bb0fef..4b55891248 100644 --- a/tests/ElabCParam/ElabCParam.log +++ b/tests/ElabCParam/ElabCParam.log @@ -852,7 +852,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 bit_typespec 12 class_defn 8 class_typespec 4 @@ -892,7 +892,7 @@ unsupported_typespec 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 +assignment 2 bit_typespec 12 class_defn 8 class_typespec 4 @@ -1608,7 +1608,7 @@ design: (work@socket_1n) |vpiParent: \_module_inst: work@all_zero (work@all_zero), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:54:1, endln:67:10 |vpiForInitStmt: - \_assign_stmt: , line:60:8, endln:60:20 + \_assignment: , line:60:8, endln:60:20 |vpiParent: \_gen_for: |vpiRhs: @@ -1620,7 +1620,7 @@ design: (work@socket_1n) |vpiLhs: \_int_var: (work@all_zero.i), line:60:15, endln:60:16 |vpiParent: - \_assign_stmt: , line:60:8, endln:60:20 + \_assignment: , line:60:8, endln:60:20 |vpiTypespec: \_ref_typespec: (work@all_zero.i) |vpiParent: @@ -2054,7 +2054,7 @@ design: (work@socket_1n) |vpiParent: \_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10 |vpiForInitStmt: - \_assign_stmt: , line:44:8, endln:44:20 + \_assignment: , line:44:8, endln:44:20 |vpiParent: \_gen_for: |vpiRhs: @@ -2066,7 +2066,7 @@ design: (work@socket_1n) |vpiLhs: \_int_var: (work@socket_1n.i), line:44:15, endln:44:16 |vpiParent: - \_assign_stmt: , line:44:8, endln:44:20 + \_assignment: , line:44:8, endln:44:20 |vpiTypespec: \_ref_typespec: (work@socket_1n.i) |vpiParent: diff --git a/tests/EvalFunc/EvalFunc.log b/tests/EvalFunc/EvalFunc.log index 477917eb5f..16052c68d5 100644 --- a/tests/EvalFunc/EvalFunc.log +++ b/tests/EvalFunc/EvalFunc.log @@ -735,8 +735,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 5 -assignment 15 +assignment 20 begin 8 constant 104 design 1 @@ -765,8 +764,7 @@ sys_func_call 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 8 -assignment 30 +assignment 38 begin 16 constant 104 design 1 @@ -916,13 +914,13 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:5, endln:5:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:6:5, endln:6:8 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -930,7 +928,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:6:10, endln:6:16 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -1250,13 +1248,13 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:5, endln:5:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:6:5, endln:6:8 |vpiRhs: \_constant: , line:6:19, endln:6:20 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1264,7 +1262,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:6:10, endln:6:16 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -1915,13 +1913,13 @@ design: (work@top) \_begin: (work@top.log2), line:41:2, endln:46:5 |vpiFullName:work@top.log2 |vpiForInitStmt: - \_assign_stmt: , line:43:8, endln:43:13 + \_assignment: , line:43:8, endln:43:13 |vpiParent: \_for_stmt: (work@top.log2), line:43:3, endln:43:6 |vpiRhs: \_constant: , line:43:12, endln:43:13 |vpiParent: - \_assign_stmt: , line:43:8, endln:43:13 + \_assignment: , line:43:8, endln:43:13 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1929,7 +1927,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@top.log2.res), line:43:8, endln:43:11 |vpiParent: - \_assign_stmt: , line:43:8, endln:43:13 + \_assignment: , line:43:8, endln:43:13 |vpiName:res |vpiFullName:work@top.log2.res |vpiForIncStmt: @@ -2624,7 +2622,7 @@ design: (work@top) \_begin: (work@top.log2), line:41:2, endln:46:5 |vpiFullName:work@top.log2 |vpiForInitStmt: - \_assign_stmt: , line:43:8, endln:43:13 + \_assignment: , line:43:8, endln:43:13 |vpiParent: \_for_stmt: (work@top.log2), line:43:3, endln:43:6 |vpiRhs: @@ -2632,7 +2630,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@top.log2.res), line:43:8, endln:43:11 |vpiParent: - \_assign_stmt: , line:43:8, endln:43:13 + \_assignment: , line:43:8, endln:43:13 |vpiName:res |vpiFullName:work@top.log2.res |vpiActual: @@ -2997,7 +2995,7 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:5, endln:5:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:6:5, endln:6:8 |vpiRhs: @@ -3005,7 +3003,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:6:10, endln:6:16 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: @@ -3270,7 +3268,7 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:5, endln:5:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:6:5, endln:6:8 |vpiRhs: @@ -3278,7 +3276,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:6:10, endln:6:16 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:20 + \_assignment: , line:6:10, endln:6:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: diff --git a/tests/EvalFuncArray/EvalFuncArray.log b/tests/EvalFuncArray/EvalFuncArray.log index 02c89d3920..ea5477dc99 100644 --- a/tests/EvalFuncArray/EvalFuncArray.log +++ b/tests/EvalFuncArray/EvalFuncArray.log @@ -464,8 +464,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 -assignment 2 +assignment 6 begin 6 bit_select 4 class_defn 8 @@ -500,8 +499,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 8 -assignment 4 +assignment 12 begin 12 bit_select 8 class_defn 8 @@ -752,9 +750,11 @@ design: (unnamed) |vpiFullName:earlgrey::max_info_pages::current_max |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiParent: \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:14:23, endln:14:24 |vpiDecompile:0 @@ -764,7 +764,7 @@ design: (unnamed) |vpiLhs: \_int_var: (earlgrey::max_info_pages::current_max), line:14:9, endln:14:20 |vpiParent: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::current_max) |vpiParent: @@ -781,13 +781,13 @@ design: (unnamed) \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 |vpiFullName:earlgrey::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiParent: \_for_stmt: (earlgrey::max_info_pages), line:15:5, endln:15:8 |vpiRhs: \_constant: , line:15:18, endln:15:19 |vpiParent: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -795,7 +795,7 @@ design: (unnamed) |vpiLhs: \_int_var: (earlgrey::max_info_pages::i), line:15:14, endln:15:15 |vpiParent: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::i) |vpiParent: @@ -1133,9 +1133,11 @@ design: (unnamed) |vpiFullName:earlgrey::max_info_pages::current_max |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiParent: \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:14:23, endln:14:24 |vpiDecompile:0 @@ -1145,7 +1147,7 @@ design: (unnamed) |vpiLhs: \_int_var: (earlgrey::max_info_pages::current_max), line:14:9, endln:14:20 |vpiParent: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::current_max) |vpiParent: @@ -1162,13 +1164,13 @@ design: (unnamed) \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 |vpiFullName:earlgrey::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiParent: \_for_stmt: (earlgrey::max_info_pages), line:15:5, endln:15:8 |vpiRhs: \_constant: , line:15:18, endln:15:19 |vpiParent: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1176,7 +1178,7 @@ design: (unnamed) |vpiLhs: \_int_var: (earlgrey::max_info_pages::i), line:15:14, endln:15:15 |vpiParent: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::i) |vpiParent: @@ -1755,7 +1757,7 @@ design: (unnamed) |vpiVariables: \_int_var: (earlgrey::max_info_pages::current_max), line:14:9, endln:14:20 |vpiParent: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::current_max) |vpiParent: @@ -1812,9 +1814,11 @@ design: (unnamed) |vpiVariables: \_int_var: (earlgrey::max_info_pages::current_max), line:14:9, endln:14:20 |vpiStmt: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiParent: \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:14:23, endln:14:24 |vpiLhs: @@ -1825,7 +1829,7 @@ design: (unnamed) \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 |vpiFullName:earlgrey::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiParent: \_for_stmt: (earlgrey::max_info_pages), line:15:5, endln:15:8 |vpiRhs: @@ -1833,7 +1837,7 @@ design: (unnamed) |vpiLhs: \_int_var: (earlgrey::max_info_pages::i), line:15:14, endln:15:15 |vpiParent: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::i) |vpiParent: @@ -2001,7 +2005,7 @@ design: (unnamed) |vpiVariables: \_int_var: (earlgrey::max_info_pages::current_max), line:14:9, endln:14:20 |vpiParent: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::current_max) |vpiParent: @@ -2058,9 +2062,11 @@ design: (unnamed) |vpiVariables: \_int_var: (earlgrey::max_info_pages::current_max), line:14:9, endln:14:20 |vpiStmt: - \_assign_stmt: , line:14:9, endln:14:24 + \_assignment: , line:14:9, endln:14:24 |vpiParent: \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:14:23, endln:14:24 |vpiLhs: @@ -2071,7 +2077,7 @@ design: (unnamed) \_begin: (earlgrey::max_info_pages), line:15:5, endln:19:8 |vpiFullName:earlgrey::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiParent: \_for_stmt: (earlgrey::max_info_pages), line:15:5, endln:15:8 |vpiRhs: @@ -2079,7 +2085,7 @@ design: (unnamed) |vpiLhs: \_int_var: (earlgrey::max_info_pages::i), line:15:14, endln:15:15 |vpiParent: - \_assign_stmt: , line:15:10, endln:15:19 + \_assignment: , line:15:10, endln:15:19 |vpiTypespec: \_ref_typespec: (earlgrey::max_info_pages::i) |vpiParent: diff --git a/tests/EvalFuncPack/EvalFuncPack.log b/tests/EvalFuncPack/EvalFuncPack.log index 58a2c68d96..53f7c1fb3f 100644 --- a/tests/EvalFuncPack/EvalFuncPack.log +++ b/tests/EvalFuncPack/EvalFuncPack.log @@ -741,8 +741,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 8 -assignment 8 +assignment 16 begin 10 bit_select 4 class_defn 8 @@ -780,8 +779,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 16 -assignment 17 +assignment 33 begin 23 bit_select 10 class_defn 8 @@ -947,13 +945,13 @@ design: (work@flash_ctrl_info_cfg) \_begin: (prim_util_pkg::_clog2), line:8:5, endln:8:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:9:5, endln:9:8 |vpiRhs: \_constant: , line:9:19, endln:9:20 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -961,7 +959,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:9:10, endln:9:16 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -1391,9 +1389,11 @@ design: (work@flash_ctrl_info_cfg) |vpiFullName:flash_ctrl_pkg::max_info_pages::current_max |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiParent: \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:36:23, endln:36:24 |vpiDecompile:0 @@ -1403,7 +1403,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiParent: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::current_max) |vpiParent: @@ -1420,13 +1420,13 @@ design: (work@flash_ctrl_info_cfg) \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 |vpiFullName:flash_ctrl_pkg::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiParent: \_for_stmt: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:37:8 |vpiRhs: \_constant: , line:37:18, endln:37:19 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1434,7 +1434,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (flash_ctrl_pkg::max_info_pages::i), line:37:14, endln:37:15 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::i) |vpiParent: @@ -1858,13 +1858,13 @@ design: (work@flash_ctrl_info_cfg) \_begin: (prim_util_pkg::_clog2), line:8:5, endln:8:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:9:5, endln:9:8 |vpiRhs: \_constant: , line:9:19, endln:9:20 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1872,7 +1872,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:9:10, endln:9:16 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -2266,9 +2266,11 @@ design: (work@flash_ctrl_info_cfg) |vpiFullName:flash_ctrl_pkg::max_info_pages::current_max |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiParent: \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:36:23, endln:36:24 |vpiDecompile:0 @@ -2278,7 +2280,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiParent: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::current_max) |vpiParent: @@ -2295,13 +2297,13 @@ design: (work@flash_ctrl_info_cfg) \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 |vpiFullName:flash_ctrl_pkg::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiParent: \_for_stmt: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:37:8 |vpiRhs: \_constant: , line:37:18, endln:37:19 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2309,7 +2311,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (flash_ctrl_pkg::max_info_pages::i), line:37:14, endln:37:15 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::i) |vpiParent: @@ -3166,7 +3168,7 @@ design: (work@flash_ctrl_info_cfg) |vpiVariables: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiParent: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::current_max) |vpiParent: @@ -3223,9 +3225,11 @@ design: (work@flash_ctrl_info_cfg) |vpiVariables: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiStmt: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiParent: \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:36:23, endln:36:24 |vpiLhs: @@ -3236,7 +3240,7 @@ design: (work@flash_ctrl_info_cfg) \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 |vpiFullName:flash_ctrl_pkg::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiParent: \_for_stmt: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:37:8 |vpiRhs: @@ -3244,7 +3248,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (flash_ctrl_pkg::max_info_pages::i), line:37:14, endln:37:15 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::i) |vpiParent: @@ -3598,15 +3602,17 @@ design: (work@flash_ctrl_info_cfg) |vpiFullName:work@flash_ctrl_info_cfg.max_info_pages.current_max |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiParent: \_begin: (work@flash_ctrl_info_cfg.max_info_pages), line:37:5, endln:41:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:36:23, endln:36:24 |vpiLhs: \_int_var: (work@flash_ctrl_info_cfg.max_info_pages.current_max), line:36:9, endln:36:20 |vpiParent: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiTypespec: \_ref_typespec: (work@flash_ctrl_info_cfg.max_info_pages.current_max) |vpiParent: @@ -3623,7 +3629,7 @@ design: (work@flash_ctrl_info_cfg) \_begin: (work@flash_ctrl_info_cfg.max_info_pages), line:37:5, endln:41:8 |vpiFullName:work@flash_ctrl_info_cfg.max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiParent: \_for_stmt: (work@flash_ctrl_info_cfg.max_info_pages), line:37:5, endln:37:8 |vpiRhs: @@ -3631,7 +3637,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (work@flash_ctrl_info_cfg.max_info_pages.i), line:37:14, endln:37:15 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiTypespec: \_ref_typespec: (work@flash_ctrl_info_cfg.max_info_pages.i) |vpiParent: @@ -3843,7 +3849,7 @@ design: (work@flash_ctrl_info_cfg) \_begin: (prim_util_pkg::_clog2), line:8:5, endln:8:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:9:5, endln:9:8 |vpiRhs: @@ -3851,7 +3857,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:9:10, endln:9:16 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: @@ -4116,7 +4122,7 @@ design: (work@flash_ctrl_info_cfg) \_begin: (prim_util_pkg::_clog2), line:8:5, endln:8:23 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:9:5, endln:9:8 |vpiRhs: @@ -4124,7 +4130,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:9:10, endln:9:16 |vpiParent: - \_assign_stmt: , line:9:10, endln:9:20 + \_assignment: , line:9:10, endln:9:20 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: @@ -4346,7 +4352,7 @@ design: (work@flash_ctrl_info_cfg) |vpiVariables: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiParent: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::current_max) |vpiParent: @@ -4403,9 +4409,11 @@ design: (work@flash_ctrl_info_cfg) |vpiVariables: \_int_var: (flash_ctrl_pkg::max_info_pages::current_max), line:36:9, endln:36:20 |vpiStmt: - \_assign_stmt: , line:36:9, endln:36:24 + \_assignment: , line:36:9, endln:36:24 |vpiParent: \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:36:23, endln:36:24 |vpiLhs: @@ -4416,7 +4424,7 @@ design: (work@flash_ctrl_info_cfg) \_begin: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:41:8 |vpiFullName:flash_ctrl_pkg::max_info_pages |vpiForInitStmt: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiParent: \_for_stmt: (flash_ctrl_pkg::max_info_pages), line:37:5, endln:37:8 |vpiRhs: @@ -4424,7 +4432,7 @@ design: (work@flash_ctrl_info_cfg) |vpiLhs: \_int_var: (flash_ctrl_pkg::max_info_pages::i), line:37:14, endln:37:15 |vpiParent: - \_assign_stmt: , line:37:10, endln:37:19 + \_assignment: , line:37:10, endln:37:19 |vpiTypespec: \_ref_typespec: (flash_ctrl_pkg::max_info_pages::i) |vpiParent: diff --git a/tests/ExtendClassMember/ExtendClassMember.log b/tests/ExtendClassMember/ExtendClassMember.log index 346b6ec39d..6d1acc8846 100644 --- a/tests/ExtendClassMember/ExtendClassMember.log +++ b/tests/ExtendClassMember/ExtendClassMember.log @@ -218,7 +218,6 @@ design: (unnamed) \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiParent: \_assignment: , line:21:3, endln:21:42 - |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiActual: \_ref_obj: (sqr_rsp_analysis_fifo), line:21:25, endln:21:38 |vpiParent: @@ -229,6 +228,7 @@ design: (unnamed) |vpiParent: \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiName:print_enabled + |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ExtendClassMember/dut.sv, line:1:1, endln:26:11 |uhdmtopPackages: @@ -351,7 +351,6 @@ design: (unnamed) \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiParent: \_assignment: , line:21:3, endln:21:42 - |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiActual: \_ref_obj: (sqr_rsp_analysis_fifo), line:21:25, endln:21:38 |vpiParent: @@ -366,6 +365,7 @@ design: (unnamed) |vpiName:print_enabled |vpiActual: \_bit_var: (pkg::uvm_tlm_fifo::print_enabled), line:5:6, endln:5:19 + |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ExtendClassMember/dut.sv, line:1:1, endln:26:11 |vpiClassDefn: @@ -420,7 +420,6 @@ design: (unnamed) \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiParent: \_assignment: , line:21:3, endln:21:42 - |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiActual: \_ref_obj: (sqr_rsp_analysis_fifo), line:21:25, endln:21:38 |vpiParent: @@ -431,6 +430,7 @@ design: (unnamed) |vpiParent: \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiName:print_enabled + |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ExtendClassMember/dut.sv, line:1:1, endln:26:11 \_class_typespec: @@ -456,7 +456,6 @@ design: (unnamed) \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiParent: \_assignment: , line:21:3, endln:21:42 - |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiActual: \_ref_obj: (sqr_rsp_analysis_fifo), line:21:25, endln:21:38 |vpiParent: @@ -467,6 +466,7 @@ design: (unnamed) |vpiParent: \_hier_path: (sqr_rsp_analysis_fifo.print_enabled), line:21:3, endln:21:38 |vpiName:print_enabled + |vpiName:sqr_rsp_analysis_fifo.print_enabled |vpiInstance: \_package: pkg (pkg::), file:${SURELOG_DIR}/tests/ExtendClassMember/dut.sv, line:1:1, endln:26:11 \_class_typespec: diff --git a/tests/FSMBsp13/FSMBsp13.log b/tests/FSMBsp13/FSMBsp13.log index e86426eac9..08c80a6b61 100644 --- a/tests/FSMBsp13/FSMBsp13.log +++ b/tests/FSMBsp13/FSMBsp13.log @@ -16051,7 +16051,6 @@ design: (work@top) \_hier_path: (top.F2), line:121:17, endln:121:23 |vpiParent: \_sys_func_call: ($vtDumpvars), line:121:3, endln:121:24 - |vpiName:top.F2 |vpiActual: \_ref_obj: (top), line:121:17, endln:121:20 |vpiParent: @@ -16063,6 +16062,7 @@ design: (work@top) \_hier_path: (top.F2), line:121:17, endln:121:23 |vpiName:F2 |vpiFullName:work@top.F2 + |vpiName:top.F2 |vpiName:$vtDumpvars |vpiStmt: \_delay_control: , line:126:3, endln:126:11 @@ -18139,7 +18139,6 @@ design: (work@top) \_hier_path: (top.F2), line:121:17, endln:121:23 |vpiParent: \_sys_func_call: ($vtDumpvars), line:121:3, endln:121:24 - |vpiName:top.F2 |vpiActual: \_ref_obj: (top), line:121:17, endln:121:20 |vpiParent: @@ -18155,6 +18154,7 @@ design: (work@top) |vpiFullName:work@top.F2 |vpiActual: \_module_inst: work@FSM2 (work@top.F2), file:${SURELOG_DIR}/tests/FSMBsp13/top.v, line:17:1, endln:20:22 + |vpiName:top.F2 |vpiName:$vtDumpvars |vpiStmt: \_delay_control: , line:126:3, endln:126:11 diff --git a/tests/ForElab/ForElab.log b/tests/ForElab/ForElab.log index 285cf8af33..a0e82e1159 100644 --- a/tests/ForElab/ForElab.log +++ b/tests/ForElab/ForElab.log @@ -43,7 +43,7 @@ Instance tree: [NTE:EL0523] ${SURELOG_DIR}/tests/ForElab/top.v:41:10: Instance "work@tlul_socket_m1.gen_tree_arb.u_reqarb.gen_normal_case.gen_tree[2].gate". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 1 bit_typespec 2 @@ -419,13 +419,15 @@ design: (work@tlul_socket_m1) |vpiName:N_LEVELS |vpiFullName:work@prim_arbiter_tree.gen_normal_case.N_LEVELS |vpiStmt: - \_assign_stmt: , line:35:47, endln:35:50 + \_assignment: , line:35:47, endln:35:50 |vpiParent: \_named_begin: (work@prim_arbiter_tree.gen_normal_case) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@prim_arbiter_tree.gen_normal_case.req), line:35:47, endln:35:50 |vpiParent: - \_assign_stmt: , line:35:47, endln:35:50 + \_assignment: , line:35:47, endln:35:50 |vpiTypespec: \_ref_typespec: (work@prim_arbiter_tree.gen_normal_case.req) |vpiParent: diff --git a/tests/ForLoop/ForLoop.log b/tests/ForLoop/ForLoop.log index ba42fc829b..5074ded4ba 100644 --- a/tests/ForLoop/ForLoop.log +++ b/tests/ForLoop/ForLoop.log @@ -1064,8 +1064,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 15 -assignment 18 +assignment 33 begin 1 class_defn 8 class_typespec 4 @@ -1096,8 +1095,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 30 -assignment 36 +assignment 66 begin 2 class_defn 8 class_typespec 4 @@ -1967,13 +1965,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:12:11, endln:12:14 + \_assignment: , line:12:11, endln:12:14 |vpiParent: \_for_stmt: (work@t), line:12:6, endln:12:9 |vpiRhs: \_constant: , line:12:13, endln:12:14 |vpiParent: - \_assign_stmt: , line:12:11, endln:12:14 + \_assignment: , line:12:11, endln:12:14 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1981,7 +1979,7 @@ design: (work@t) |vpiLhs: \_ref_var: (work@t.a), line:12:11, endln:12:12 |vpiParent: - \_assign_stmt: , line:12:11, endln:12:14 + \_assignment: , line:12:11, endln:12:14 |vpiName:a |vpiFullName:work@t.a |vpiCondition: @@ -2011,13 +2009,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:13:11, endln:13:14 + \_assignment: , line:13:11, endln:13:14 |vpiParent: \_for_stmt: (work@t), line:13:6, endln:13:9 |vpiRhs: \_constant: , line:13:13, endln:13:14 |vpiParent: - \_assign_stmt: , line:13:11, endln:13:14 + \_assignment: , line:13:11, endln:13:14 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2025,7 +2023,7 @@ design: (work@t) |vpiLhs: \_ref_var: (work@t.a), line:13:11, endln:13:12 |vpiParent: - \_assign_stmt: , line:13:11, endln:13:14 + \_assignment: , line:13:11, endln:13:14 |vpiName:a |vpiFullName:work@t.a |vpiForIncStmt: @@ -2090,13 +2088,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:14:11, endln:14:14 + \_assignment: , line:14:11, endln:14:14 |vpiParent: \_for_stmt: (work@t), line:14:6, endln:14:9 |vpiRhs: \_constant: , line:14:13, endln:14:14 |vpiParent: - \_assign_stmt: , line:14:11, endln:14:14 + \_assignment: , line:14:11, endln:14:14 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2104,7 +2102,7 @@ design: (work@t) |vpiLhs: \_ref_var: (work@t.a), line:14:11, endln:14:12 |vpiParent: - \_assign_stmt: , line:14:11, endln:14:14 + \_assignment: , line:14:11, endln:14:14 |vpiName:a |vpiFullName:work@t.a |vpiForIncStmt: @@ -2204,13 +2202,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:15:11, endln:15:22 + \_assignment: , line:15:11, endln:15:22 |vpiParent: \_for_stmt: (work@t), line:15:6, endln:15:9 |vpiRhs: \_constant: , line:15:21, endln:15:22 |vpiParent: - \_assign_stmt: , line:15:11, endln:15:22 + \_assignment: , line:15:11, endln:15:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2218,7 +2216,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:15:19, endln:15:20 |vpiParent: - \_assign_stmt: , line:15:11, endln:15:22 + \_assignment: , line:15:11, endln:15:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2256,13 +2254,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:16:11, endln:16:22 + \_assignment: , line:16:11, endln:16:22 |vpiParent: \_for_stmt: (work@t), line:16:6, endln:16:9 |vpiRhs: \_constant: , line:16:21, endln:16:22 |vpiParent: - \_assign_stmt: , line:16:11, endln:16:22 + \_assignment: , line:16:11, endln:16:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2270,7 +2268,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:16:19, endln:16:20 |vpiParent: - \_assign_stmt: , line:16:11, endln:16:22 + \_assignment: , line:16:11, endln:16:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2343,13 +2341,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:17:11, endln:17:22 + \_assignment: , line:17:11, endln:17:22 |vpiParent: \_for_stmt: (work@t), line:17:6, endln:17:9 |vpiRhs: \_constant: , line:17:21, endln:17:22 |vpiParent: - \_assign_stmt: , line:17:11, endln:17:22 + \_assignment: , line:17:11, endln:17:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2357,7 +2355,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:17:19, endln:17:20 |vpiParent: - \_assign_stmt: , line:17:11, endln:17:22 + \_assignment: , line:17:11, endln:17:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2465,13 +2463,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:18:11, endln:18:26 + \_assignment: , line:18:11, endln:18:26 |vpiParent: \_for_stmt: (work@t), line:18:6, endln:18:9 |vpiRhs: \_constant: , line:18:25, endln:18:26 |vpiParent: - \_assign_stmt: , line:18:11, endln:18:26 + \_assignment: , line:18:11, endln:18:26 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2479,7 +2477,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:18:23, endln:18:24 |vpiParent: - \_assign_stmt: , line:18:11, endln:18:26 + \_assignment: , line:18:11, endln:18:26 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2517,13 +2515,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:19:11, endln:19:26 + \_assignment: , line:19:11, endln:19:26 |vpiParent: \_for_stmt: (work@t), line:19:6, endln:19:9 |vpiRhs: \_constant: , line:19:25, endln:19:26 |vpiParent: - \_assign_stmt: , line:19:11, endln:19:26 + \_assignment: , line:19:11, endln:19:26 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2531,7 +2529,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:19:23, endln:19:24 |vpiParent: - \_assign_stmt: , line:19:11, endln:19:26 + \_assignment: , line:19:11, endln:19:26 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2604,13 +2602,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:20:11, endln:20:26 + \_assignment: , line:20:11, endln:20:26 |vpiParent: \_for_stmt: (work@t), line:20:6, endln:20:9 |vpiRhs: \_constant: , line:20:25, endln:20:26 |vpiParent: - \_assign_stmt: , line:20:11, endln:20:26 + \_assignment: , line:20:11, endln:20:26 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2618,7 +2616,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:20:23, endln:20:24 |vpiParent: - \_assign_stmt: , line:20:11, endln:20:26 + \_assignment: , line:20:11, endln:20:26 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2726,13 +2724,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:21:11, endln:21:22 + \_assignment: , line:21:11, endln:21:22 |vpiParent: \_for_stmt: (work@t), line:21:6, endln:21:9 |vpiRhs: \_constant: , line:21:21, endln:21:22 |vpiParent: - \_assign_stmt: , line:21:11, endln:21:22 + \_assignment: , line:21:11, endln:21:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2740,7 +2738,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:21:19, endln:21:20 |vpiParent: - \_assign_stmt: , line:21:11, endln:21:22 + \_assignment: , line:21:11, endln:21:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2752,13 +2750,13 @@ design: (work@t) |vpiFullName:work@t.a |vpiSigned:1 |vpiForInitStmt: - \_assign_stmt: , line:21:24, endln:21:35 + \_assignment: , line:21:24, endln:21:35 |vpiParent: \_for_stmt: (work@t), line:21:6, endln:21:9 |vpiRhs: \_constant: , line:21:34, endln:21:35 |vpiParent: - \_assign_stmt: , line:21:24, endln:21:35 + \_assignment: , line:21:24, endln:21:35 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2766,7 +2764,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.b), line:21:32, endln:21:33 |vpiParent: - \_assign_stmt: , line:21:24, endln:21:35 + \_assignment: , line:21:24, endln:21:35 |vpiTypespec: \_ref_typespec: (work@t.b) |vpiParent: @@ -2804,13 +2802,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:22:11, endln:22:22 + \_assignment: , line:22:11, endln:22:22 |vpiParent: \_for_stmt: (work@t), line:22:6, endln:22:9 |vpiRhs: \_constant: , line:22:21, endln:22:22 |vpiParent: - \_assign_stmt: , line:22:11, endln:22:22 + \_assignment: , line:22:11, endln:22:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2818,7 +2816,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:22:19, endln:22:20 |vpiParent: - \_assign_stmt: , line:22:11, endln:22:22 + \_assignment: , line:22:11, endln:22:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2830,13 +2828,13 @@ design: (work@t) |vpiFullName:work@t.a |vpiSigned:1 |vpiForInitStmt: - \_assign_stmt: , line:22:24, endln:22:35 + \_assignment: , line:22:24, endln:22:35 |vpiParent: \_for_stmt: (work@t), line:22:6, endln:22:9 |vpiRhs: \_constant: , line:22:34, endln:22:35 |vpiParent: - \_assign_stmt: , line:22:24, endln:22:35 + \_assignment: , line:22:24, endln:22:35 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2844,7 +2842,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.b), line:22:32, endln:22:33 |vpiParent: - \_assign_stmt: , line:22:24, endln:22:35 + \_assignment: , line:22:24, endln:22:35 |vpiTypespec: \_ref_typespec: (work@t.b) |vpiParent: @@ -2917,13 +2915,13 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:23:11, endln:23:22 + \_assignment: , line:23:11, endln:23:22 |vpiParent: \_for_stmt: (work@t), line:23:6, endln:23:9 |vpiRhs: \_constant: , line:23:21, endln:23:22 |vpiParent: - \_assign_stmt: , line:23:11, endln:23:22 + \_assignment: , line:23:11, endln:23:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2931,7 +2929,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:23:19, endln:23:20 |vpiParent: - \_assign_stmt: , line:23:11, endln:23:22 + \_assignment: , line:23:11, endln:23:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -2943,13 +2941,13 @@ design: (work@t) |vpiFullName:work@t.a |vpiSigned:1 |vpiForInitStmt: - \_assign_stmt: , line:23:24, endln:23:35 + \_assignment: , line:23:24, endln:23:35 |vpiParent: \_for_stmt: (work@t), line:23:6, endln:23:9 |vpiRhs: \_constant: , line:23:34, endln:23:35 |vpiParent: - \_assign_stmt: , line:23:24, endln:23:35 + \_assignment: , line:23:24, endln:23:35 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2957,7 +2955,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.b), line:23:32, endln:23:33 |vpiParent: - \_assign_stmt: , line:23:24, endln:23:35 + \_assignment: , line:23:24, endln:23:35 |vpiTypespec: \_ref_typespec: (work@t.b) |vpiParent: @@ -3375,7 +3373,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:12:11, endln:12:14 + \_assignment: , line:12:11, endln:12:14 |vpiParent: \_for_stmt: (work@t), line:12:6, endln:12:9 |vpiRhs: @@ -3383,7 +3381,7 @@ design: (work@t) |vpiLhs: \_ref_var: (work@t.a), line:12:11, endln:12:12 |vpiParent: - \_assign_stmt: , line:12:11, endln:12:14 + \_assignment: , line:12:11, endln:12:14 |vpiName:a |vpiFullName:work@t.a |vpiActual: @@ -3409,7 +3407,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:13:11, endln:13:14 + \_assignment: , line:13:11, endln:13:14 |vpiParent: \_for_stmt: (work@t), line:13:6, endln:13:9 |vpiRhs: @@ -3417,7 +3415,7 @@ design: (work@t) |vpiLhs: \_ref_var: (work@t.a), line:13:11, endln:13:12 |vpiParent: - \_assign_stmt: , line:13:11, endln:13:14 + \_assignment: , line:13:11, endln:13:14 |vpiName:a |vpiFullName:work@t.a |vpiActual: @@ -3472,7 +3470,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:14:11, endln:14:14 + \_assignment: , line:14:11, endln:14:14 |vpiParent: \_for_stmt: (work@t), line:14:6, endln:14:9 |vpiRhs: @@ -3480,7 +3478,7 @@ design: (work@t) |vpiLhs: \_ref_var: (work@t.a), line:14:11, endln:14:12 |vpiParent: - \_assign_stmt: , line:14:11, endln:14:14 + \_assignment: , line:14:11, endln:14:14 |vpiName:a |vpiFullName:work@t.a |vpiActual: @@ -3564,7 +3562,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:15:11, endln:15:22 + \_assignment: , line:15:11, endln:15:22 |vpiParent: \_for_stmt: (work@t), line:15:6, endln:15:9 |vpiRhs: @@ -3572,7 +3570,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:15:19, endln:15:20 |vpiParent: - \_assign_stmt: , line:15:11, endln:15:22 + \_assignment: , line:15:11, endln:15:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3604,7 +3602,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:16:11, endln:16:22 + \_assignment: , line:16:11, endln:16:22 |vpiParent: \_for_stmt: (work@t), line:16:6, endln:16:9 |vpiRhs: @@ -3612,7 +3610,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:16:19, endln:16:20 |vpiParent: - \_assign_stmt: , line:16:11, endln:16:22 + \_assignment: , line:16:11, endln:16:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3673,7 +3671,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:17:11, endln:17:22 + \_assignment: , line:17:11, endln:17:22 |vpiParent: \_for_stmt: (work@t), line:17:6, endln:17:9 |vpiRhs: @@ -3681,7 +3679,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:17:19, endln:17:20 |vpiParent: - \_assign_stmt: , line:17:11, endln:17:22 + \_assignment: , line:17:11, endln:17:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3771,7 +3769,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:18:11, endln:18:26 + \_assignment: , line:18:11, endln:18:26 |vpiParent: \_for_stmt: (work@t), line:18:6, endln:18:9 |vpiRhs: @@ -3779,7 +3777,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:18:23, endln:18:24 |vpiParent: - \_assign_stmt: , line:18:11, endln:18:26 + \_assignment: , line:18:11, endln:18:26 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3811,7 +3809,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:19:11, endln:19:26 + \_assignment: , line:19:11, endln:19:26 |vpiParent: \_for_stmt: (work@t), line:19:6, endln:19:9 |vpiRhs: @@ -3819,7 +3817,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:19:23, endln:19:24 |vpiParent: - \_assign_stmt: , line:19:11, endln:19:26 + \_assignment: , line:19:11, endln:19:26 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3880,7 +3878,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:20:11, endln:20:26 + \_assignment: , line:20:11, endln:20:26 |vpiParent: \_for_stmt: (work@t), line:20:6, endln:20:9 |vpiRhs: @@ -3888,7 +3886,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:20:23, endln:20:24 |vpiParent: - \_assign_stmt: , line:20:11, endln:20:26 + \_assignment: , line:20:11, endln:20:26 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3978,7 +3976,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:21:11, endln:21:22 + \_assignment: , line:21:11, endln:21:22 |vpiParent: \_for_stmt: (work@t), line:21:6, endln:21:9 |vpiRhs: @@ -3986,7 +3984,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:21:19, endln:21:20 |vpiParent: - \_assign_stmt: , line:21:11, endln:21:22 + \_assignment: , line:21:11, endln:21:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -3998,7 +3996,7 @@ design: (work@t) |vpiFullName:work@t.a |vpiSigned:1 |vpiForInitStmt: - \_assign_stmt: , line:21:24, endln:21:35 + \_assignment: , line:21:24, endln:21:35 |vpiParent: \_for_stmt: (work@t), line:21:6, endln:21:9 |vpiRhs: @@ -4006,7 +4004,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.b), line:21:32, endln:21:33 |vpiParent: - \_assign_stmt: , line:21:24, endln:21:35 + \_assignment: , line:21:24, endln:21:35 |vpiTypespec: \_ref_typespec: (work@t.b) |vpiParent: @@ -4038,7 +4036,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:22:11, endln:22:22 + \_assignment: , line:22:11, endln:22:22 |vpiParent: \_for_stmt: (work@t), line:22:6, endln:22:9 |vpiRhs: @@ -4046,7 +4044,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:22:19, endln:22:20 |vpiParent: - \_assign_stmt: , line:22:11, endln:22:22 + \_assignment: , line:22:11, endln:22:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -4058,7 +4056,7 @@ design: (work@t) |vpiFullName:work@t.a |vpiSigned:1 |vpiForInitStmt: - \_assign_stmt: , line:22:24, endln:22:35 + \_assignment: , line:22:24, endln:22:35 |vpiParent: \_for_stmt: (work@t), line:22:6, endln:22:9 |vpiRhs: @@ -4066,7 +4064,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.b), line:22:32, endln:22:33 |vpiParent: - \_assign_stmt: , line:22:24, endln:22:35 + \_assignment: , line:22:24, endln:22:35 |vpiTypespec: \_ref_typespec: (work@t.b) |vpiParent: @@ -4127,7 +4125,7 @@ design: (work@t) \_begin: (work@t), line:5:11, endln:26:6 |vpiFullName:work@t |vpiForInitStmt: - \_assign_stmt: , line:23:11, endln:23:22 + \_assignment: , line:23:11, endln:23:22 |vpiParent: \_for_stmt: (work@t), line:23:6, endln:23:9 |vpiRhs: @@ -4135,7 +4133,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.a), line:23:19, endln:23:20 |vpiParent: - \_assign_stmt: , line:23:11, endln:23:22 + \_assignment: , line:23:11, endln:23:22 |vpiTypespec: \_ref_typespec: (work@t.a) |vpiParent: @@ -4147,7 +4145,7 @@ design: (work@t) |vpiFullName:work@t.a |vpiSigned:1 |vpiForInitStmt: - \_assign_stmt: , line:23:24, endln:23:35 + \_assignment: , line:23:24, endln:23:35 |vpiParent: \_for_stmt: (work@t), line:23:6, endln:23:9 |vpiRhs: @@ -4155,7 +4153,7 @@ design: (work@t) |vpiLhs: \_integer_var: (work@t.b), line:23:32, endln:23:33 |vpiParent: - \_assign_stmt: , line:23:24, endln:23:35 + \_assignment: , line:23:24, endln:23:35 |vpiTypespec: \_ref_typespec: (work@t.b) |vpiParent: @@ -4511,5 +4509,5 @@ design: (work@t) ============================== Begin RoundTrip Results ============================== [roundtrip]: ${SURELOG_DIR}/tests/ForLoop/builtin.sv | ${SURELOG_DIR}/build/regression/ForLoop/roundtrip/builtin_000.sv | 0 | 0 | -[roundtrip]: ${SURELOG_DIR}/tests/ForLoop/dut.sv | ${SURELOG_DIR}/build/regression/ForLoop/roundtrip/dut_000.sv | 13 | 28 | +[roundtrip]: ${SURELOG_DIR}/tests/ForLoop/dut.sv | ${SURELOG_DIR}/build/regression/ForLoop/roundtrip/dut_000.sv | 19 | 28 | ============================== End RoundTrip Results ============================== diff --git a/tests/ForLoopBind/ForLoopBind.log b/tests/ForLoopBind/ForLoopBind.log index ebd6d59e3f..63d65ef3fd 100644 --- a/tests/ForLoopBind/ForLoopBind.log +++ b/tests/ForLoopBind/ForLoopBind.log @@ -480,8 +480,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 6 -assignment 4 +assignment 10 begin 6 class_defn 13 class_typespec 17 @@ -513,8 +512,7 @@ unsupported_typespec 4 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 4 -assign_stmt 8 -assignment 8 +assignment 16 begin 12 class_defn 13 class_typespec 17 @@ -659,13 +657,13 @@ design: (unnamed) \_begin: (uvm::uvm_vreg::write), line:27:24, endln:33:7 |vpiFullName:uvm::uvm_vreg::write |vpiForInitStmt: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiParent: \_for_stmt: (uvm::uvm_vreg::write), line:29:7, endln:29:10 |vpiRhs: \_ref_obj: (uvm::uvm_vreg::write::cbs), line:29:36, endln:29:39 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiName:cbs |vpiFullName:uvm::uvm_vreg::write::cbs |vpiActual: @@ -673,7 +671,7 @@ design: (unnamed) |vpiLhs: \_class_var: (uvm::uvm_vreg::write::cb), line:29:31, endln:29:33 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiTypespec: \_ref_typespec: (uvm::uvm_vreg::write::cb) |vpiParent: @@ -747,7 +745,6 @@ design: (unnamed) \_hier_path: (cb.fname), line:31:10, endln:31:18 |vpiParent: \_assignment: , line:31:10, endln:31:22 - |vpiName:cb.fname |vpiActual: \_ref_obj: (cb), line:31:13, endln:31:18 |vpiParent: @@ -762,6 +759,7 @@ design: (unnamed) |vpiName:fname |vpiActual: \_int_var: (uvm::uvm_vreg_field_cbs::fname), line:14:7, endln:14:12 + |vpiName:cb.fname |vpiInstance: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/ForLoopBind/dut.sv, line:1:1, endln:36:11 |uhdmtopPackages: @@ -950,13 +948,13 @@ design: (unnamed) \_begin: (uvm::uvm_vreg::write), line:27:24, endln:33:7 |vpiFullName:uvm::uvm_vreg::write |vpiForInitStmt: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiParent: \_for_stmt: (uvm::uvm_vreg::write), line:29:7, endln:29:10 |vpiRhs: \_ref_obj: (uvm::uvm_vreg::write::cbs), line:29:36, endln:29:39 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiName:cbs |vpiFullName:uvm::uvm_vreg::write::cbs |vpiActual: @@ -964,7 +962,7 @@ design: (unnamed) |vpiLhs: \_class_var: (uvm::uvm_vreg::write::cb), line:29:31, endln:29:33 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiTypespec: \_ref_typespec: (uvm::uvm_vreg::write::cb) |vpiParent: @@ -1038,7 +1036,6 @@ design: (unnamed) \_hier_path: (cb.fname), line:31:10, endln:31:18 |vpiParent: \_assignment: , line:31:10, endln:31:22 - |vpiName:cb.fname |vpiActual: \_ref_obj: (cb), line:31:13, endln:31:18 |vpiParent: @@ -1053,6 +1050,7 @@ design: (unnamed) |vpiName:fname |vpiActual: \_int_var: (uvm::uvm_vreg_field_cbs::fname), line:14:7, endln:14:12 + |vpiName:cb.fname |vpiInstance: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/ForLoopBind/dut.sv, line:1:1, endln:36:11 |vpiClassDefn: @@ -1607,13 +1605,13 @@ design: (unnamed) \_begin: (uvm::uvm_vreg::write), line:27:24, endln:33:7 |vpiFullName:uvm::uvm_vreg::write |vpiForInitStmt: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiParent: \_for_stmt: (uvm::uvm_vreg::write), line:29:7, endln:29:10 |vpiRhs: \_ref_obj: (uvm::uvm_vreg::write::cbs), line:29:36, endln:29:39 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiName:cbs |vpiFullName:uvm::uvm_vreg::write::cbs |vpiActual: @@ -1621,7 +1619,7 @@ design: (unnamed) |vpiLhs: \_class_var: (uvm::uvm_vreg::write::cb), line:29:31, endln:29:33 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiTypespec: \_ref_typespec: (uvm::uvm_vreg::write::cb) |vpiParent: @@ -1672,7 +1670,6 @@ design: (unnamed) \_hier_path: (cb.fname), line:31:10, endln:31:18 |vpiParent: \_assignment: , line:31:10, endln:31:22 - |vpiName:cb.fname |vpiActual: \_ref_obj: (cb), line:31:13, endln:31:18 |vpiParent: @@ -1683,6 +1680,7 @@ design: (unnamed) |vpiParent: \_hier_path: (cb.fname), line:31:10, endln:31:18 |vpiName:fname + |vpiName:cb.fname \_begin: (uvm::uvm_vreg::write), line:27:24, endln:33:7 |vpiParent: \_foreach_stmt: (uvm::uvm_vreg::write), line:27:4, endln:27:11 @@ -1827,13 +1825,13 @@ design: (unnamed) \_begin: (uvm::uvm_vreg::write), line:27:24, endln:33:7 |vpiFullName:uvm::uvm_vreg::write |vpiForInitStmt: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiParent: \_for_stmt: (uvm::uvm_vreg::write), line:29:7, endln:29:10 |vpiRhs: \_ref_obj: (uvm::uvm_vreg::write::cbs), line:29:36, endln:29:39 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiName:cbs |vpiFullName:uvm::uvm_vreg::write::cbs |vpiActual: @@ -1841,7 +1839,7 @@ design: (unnamed) |vpiLhs: \_class_var: (uvm::uvm_vreg::write::cb), line:29:31, endln:29:33 |vpiParent: - \_assign_stmt: , line:29:12, endln:29:39 + \_assignment: , line:29:12, endln:29:39 |vpiTypespec: \_ref_typespec: (uvm::uvm_vreg::write::cb) |vpiParent: @@ -1905,7 +1903,6 @@ design: (unnamed) \_hier_path: (cb.fname), line:31:10, endln:31:18 |vpiParent: \_assignment: , line:31:10, endln:31:22 - |vpiName:cb.fname |vpiActual: \_ref_obj: (cb), line:31:13, endln:31:18 |vpiParent: @@ -1918,6 +1915,7 @@ design: (unnamed) |vpiParent: \_hier_path: (cb.fname), line:31:10, endln:31:18 |vpiName:fname + |vpiName:cb.fname \_begin: (uvm::uvm_vreg::write), line:27:4, endln:33:7 |vpiParent: \_task: (uvm::uvm_vreg::write), line:25:1, endln:34:8 diff --git a/tests/ForeachClass/ForeachClass.log b/tests/ForeachClass/ForeachClass.log index 2f02b4ab4f..e3ee17e998 100644 --- a/tests/ForeachClass/ForeachClass.log +++ b/tests/ForeachClass/ForeachClass.log @@ -128,7 +128,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 2 +assignment 2 begin 6 bit_select 4 class_defn 1 @@ -155,7 +155,7 @@ unsupported_typespec 2 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 4 -assign_stmt 2 +assignment 2 begin 12 bit_select 8 class_defn 1 @@ -246,7 +246,6 @@ design: (unnamed) \_hier_path: (top_map.m_mems_by_offset) |vpiParent: \_foreach_stmt: (uvm::f1), line:11:5, endln:11:12 - |vpiFullName:top_map.m_mems_by_offset |vpiActual: \_ref_obj: (uvm::f1::top_map), line:11:14, endln:11:21 |vpiParent: @@ -263,6 +262,7 @@ design: (unnamed) |vpiFullName:uvm::f1::m_mems_by_offset |vpiActual: \_array_var: (uvm::uvm_reg_map::m_mems_by_offset), line:4:17, endln:4:33 + |vpiFullName:top_map.m_mems_by_offset |vpiLoopVars: \_ref_var: (uvm::f1::range), line:11:39, endln:11:44 |vpiParent: @@ -313,7 +313,6 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiParent: \_operation: , line:12:11, endln:12:32 - |vpiName:range.min |vpiActual: \_ref_obj: (range), line:12:23, endln:12:28 |vpiParent: @@ -327,6 +326,7 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiName:min |vpiFullName:uvm::f1::min + |vpiName:range.min |vpiOperand: \_operation: , line:12:36, endln:12:57 |vpiParent: @@ -348,7 +348,6 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiParent: \_operation: , line:12:36, endln:12:57 - |vpiName:range.max |vpiActual: \_ref_obj: (range), line:12:48, endln:12:53 |vpiParent: @@ -362,6 +361,7 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiName:max |vpiFullName:uvm::f1::max + |vpiName:range.max |vpiStmt: \_begin: (uvm::f1), line:12:59, endln:13:10 |vpiParent: @@ -495,7 +495,6 @@ design: (unnamed) \_hier_path: (top_map.m_mems_by_offset) |vpiParent: \_foreach_stmt: (uvm::f1), line:11:5, endln:11:12 - |vpiFullName:top_map.m_mems_by_offset |vpiActual: \_ref_obj: (uvm::f1::top_map), line:11:14, endln:11:21 |vpiParent: @@ -512,6 +511,7 @@ design: (unnamed) |vpiFullName:uvm::f1::m_mems_by_offset |vpiActual: \_array_var: (uvm::uvm_reg_map::m_mems_by_offset), line:4:17, endln:4:33 + |vpiFullName:top_map.m_mems_by_offset |vpiLoopVars: \_array_var: (uvm::f1::range), line:11:39, endln:11:44 |vpiParent: @@ -560,7 +560,6 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiParent: \_operation: , line:12:11, endln:12:32 - |vpiName:range.min |vpiActual: \_ref_obj: (range), line:12:23, endln:12:28 |vpiParent: @@ -576,6 +575,7 @@ design: (unnamed) |vpiFullName:uvm::f1::min |vpiActual: \_func_call: (min) + |vpiName:range.min |vpiOperand: \_operation: , line:12:36, endln:12:57 |vpiParent: @@ -597,7 +597,6 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiParent: \_operation: , line:12:36, endln:12:57 - |vpiName:range.max |vpiActual: \_ref_obj: (range), line:12:48, endln:12:53 |vpiParent: @@ -613,6 +612,7 @@ design: (unnamed) |vpiFullName:uvm::f1::max |vpiActual: \_func_call: (max) + |vpiName:range.max |vpiStmt: \_begin: (uvm::f1), line:12:59, endln:13:10 |vpiParent: @@ -658,7 +658,6 @@ design: (unnamed) \_hier_path: (top_map.m_mems_by_offset) |vpiParent: \_foreach_stmt: (uvm::f1), line:11:5, endln:11:12 - |vpiFullName:top_map.m_mems_by_offset |vpiActual: \_ref_obj: (uvm::f1::top_map), line:11:14, endln:11:21 |vpiParent: @@ -673,6 +672,7 @@ design: (unnamed) \_hier_path: (top_map.m_mems_by_offset) |vpiName:m_mems_by_offset |vpiFullName:uvm::f1::m_mems_by_offset + |vpiFullName:top_map.m_mems_by_offset |vpiLoopVars: \_array_var: (uvm::f1::range), line:11:39, endln:11:44 |vpiParent: @@ -721,7 +721,6 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiParent: \_operation: , line:12:11, endln:12:32 - |vpiName:range.min |vpiActual: \_ref_obj: (range), line:12:23, endln:12:28 |vpiParent: @@ -735,6 +734,7 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiName:min |vpiFullName:uvm::f1::min + |vpiName:range.min |vpiOperand: \_operation: , line:12:36, endln:12:57 |vpiParent: @@ -756,7 +756,6 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiParent: \_operation: , line:12:36, endln:12:57 - |vpiName:range.max |vpiActual: \_ref_obj: (range), line:12:48, endln:12:53 |vpiParent: @@ -770,6 +769,7 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiName:max |vpiFullName:uvm::f1::max + |vpiName:range.max |vpiStmt: \_begin: (uvm::f1), line:12:59, endln:13:10 |vpiParent: @@ -817,7 +817,6 @@ design: (unnamed) \_hier_path: (top_map.m_mems_by_offset) |vpiParent: \_foreach_stmt: (uvm::f1), line:11:5, endln:11:12 - |vpiFullName:top_map.m_mems_by_offset |vpiActual: \_ref_obj: (uvm::f1::top_map), line:11:14, endln:11:21 |vpiParent: @@ -832,6 +831,7 @@ design: (unnamed) \_hier_path: (top_map.m_mems_by_offset) |vpiName:m_mems_by_offset |vpiFullName:uvm::f1::m_mems_by_offset + |vpiFullName:top_map.m_mems_by_offset |vpiLoopVars: \_ref_var: (uvm::f1::range), line:11:39, endln:11:44 |vpiParent: @@ -880,7 +880,6 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiParent: \_operation: , line:12:11, endln:12:32 - |vpiName:range.min |vpiActual: \_ref_obj: (range), line:12:23, endln:12:28 |vpiParent: @@ -894,6 +893,7 @@ design: (unnamed) \_hier_path: (range.min), line:12:23, endln:12:32 |vpiName:min |vpiFullName:uvm::f1::min + |vpiName:range.min |vpiOperand: \_operation: , line:12:36, endln:12:57 |vpiParent: @@ -915,7 +915,6 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiParent: \_operation: , line:12:36, endln:12:57 - |vpiName:range.max |vpiActual: \_ref_obj: (range), line:12:48, endln:12:53 |vpiParent: @@ -929,6 +928,7 @@ design: (unnamed) \_hier_path: (range.max), line:12:48, endln:12:57 |vpiName:max |vpiFullName:uvm::f1::max + |vpiName:range.max |vpiStmt: \_begin: (uvm::f1), line:12:59, endln:13:10 |vpiParent: diff --git a/tests/ForeachForeach/ForeachForeach.log b/tests/ForeachForeach/ForeachForeach.log index 8214a20637..fea7ad4493 100644 --- a/tests/ForeachForeach/ForeachForeach.log +++ b/tests/ForeachForeach/ForeachForeach.log @@ -117,8 +117,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 3 array_var 3 -assign_stmt 2 -assignment 2 +assignment 4 begin 6 bit_select 2 bit_typespec 3 @@ -144,8 +143,7 @@ unsupported_typespec 6 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 3 array_var 8 -assign_stmt 2 -assignment 4 +assignment 6 begin 12 bit_select 4 bit_typespec 3 @@ -307,7 +305,6 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiParent: \_foreach_stmt: (uvm::uvm_phase::get_adjacent_predecessor_nodes), line:14:12, endln:14:19 - |vpiFullName:p.m_predecessors |vpiActual: \_ref_obj: (uvm::uvm_phase::get_adjacent_predecessor_nodes::p), line:14:21, endln:14:22 |vpiParent: @@ -322,6 +319,7 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiName:m_predecessors |vpiFullName:uvm::uvm_phase::get_adjacent_predecessor_nodes::m_predecessors + |vpiFullName:p.m_predecessors |vpiLoopVars: \_ref_var: (uvm::uvm_phase::get_adjacent_predecessor_nodes::next_p), line:14:38, endln:14:44 |vpiParent: @@ -539,7 +537,6 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiParent: \_foreach_stmt: (uvm::uvm_phase::get_adjacent_predecessor_nodes), line:14:12, endln:14:19 - |vpiFullName:p.m_predecessors |vpiActual: \_ref_obj: (uvm::uvm_phase::get_adjacent_predecessor_nodes::p), line:14:21, endln:14:22 |vpiParent: @@ -556,6 +553,7 @@ design: (unnamed) |vpiFullName:uvm::uvm_phase::get_adjacent_predecessor_nodes::m_predecessors |vpiActual: \_array_var: (uvm::uvm_phase::m_predecessors), line:4:8, endln:4:22 + |vpiFullName:p.m_predecessors |vpiLoopVars: \_class_var: (uvm::uvm_phase::get_adjacent_predecessor_nodes::next_p), line:14:38, endln:14:44 |vpiParent: @@ -692,7 +690,6 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiParent: \_foreach_stmt: (uvm::uvm_phase::get_adjacent_predecessor_nodes), line:14:12, endln:14:19 - |vpiFullName:p.m_predecessors |vpiActual: \_ref_obj: (uvm::uvm_phase::get_adjacent_predecessor_nodes::p), line:14:21, endln:14:22 |vpiParent: @@ -705,6 +702,7 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiName:m_predecessors |vpiFullName:uvm::uvm_phase::get_adjacent_predecessor_nodes::m_predecessors + |vpiFullName:p.m_predecessors |vpiLoopVars: \_class_var: (uvm::uvm_phase::get_adjacent_predecessor_nodes::next_p), line:14:38, endln:14:44 |vpiParent: @@ -876,7 +874,6 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiParent: \_foreach_stmt: (uvm::uvm_phase::get_adjacent_predecessor_nodes), line:14:12, endln:14:19 - |vpiFullName:p.m_predecessors |vpiActual: \_ref_obj: (uvm::uvm_phase::get_adjacent_predecessor_nodes::p), line:14:21, endln:14:22 |vpiParent: @@ -891,6 +888,7 @@ design: (unnamed) \_hier_path: (p.m_predecessors) |vpiName:m_predecessors |vpiFullName:uvm::uvm_phase::get_adjacent_predecessor_nodes::m_predecessors + |vpiFullName:p.m_predecessors |vpiLoopVars: \_ref_var: (uvm::uvm_phase::get_adjacent_predecessor_nodes::next_p), line:14:38, endln:14:44 |vpiParent: diff --git a/tests/ForeachFunction/ForeachFunction.log b/tests/ForeachFunction/ForeachFunction.log index 48fb3e29c3..e381d05dae 100644 --- a/tests/ForeachFunction/ForeachFunction.log +++ b/tests/ForeachFunction/ForeachFunction.log @@ -75,7 +75,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 1 +assignment 1 begin 2 constant 3 design 1 @@ -97,7 +97,7 @@ unsupported_typespec 3 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 5 -assign_stmt 1 +assignment 1 begin 4 constant 3 design 1 diff --git a/tests/Func128Bits/Func128Bits.log b/tests/Func128Bits/Func128Bits.log index 6666a3460b..e6421c7ffb 100644 --- a/tests/Func128Bits/Func128Bits.log +++ b/tests/Func128Bits/Func128Bits.log @@ -669,8 +669,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 6 -assignment 9 +assignment 15 begin 6 constant 231 design 1 @@ -700,8 +699,7 @@ ref_var 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 7 -assignment 18 +assignment 25 begin 11 constant 231 design 1 @@ -1133,13 +1131,13 @@ design: (work@ScratchPad) \_begin: (work@ScratchPad.calcBaseAddrs), line:20:5, endln:35:8 |vpiFullName:work@ScratchPad.calcBaseAddrs |vpiForInitStmt: - \_assign_stmt: , line:23:14, endln:23:19 + \_assignment: , line:23:14, endln:23:19 |vpiParent: \_for_stmt: (work@ScratchPad.calcBaseAddrs), line:23:9, endln:23:12 |vpiRhs: \_constant: , line:23:18, endln:23:19 |vpiParent: - \_assign_stmt: , line:23:14, endln:23:19 + \_assignment: , line:23:14, endln:23:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1147,7 +1145,7 @@ design: (work@ScratchPad) |vpiLhs: \_ref_var: (work@ScratchPad.calcBaseAddrs.i), line:23:14, endln:23:15 |vpiParent: - \_assign_stmt: , line:23:14, endln:23:19 + \_assignment: , line:23:14, endln:23:19 |vpiName:i |vpiFullName:work@ScratchPad.calcBaseAddrs.i |vpiForIncStmt: @@ -1995,7 +1993,7 @@ design: (work@ScratchPad) \_begin: (work@ScratchPad.calcBaseAddrs), line:20:5, endln:35:8 |vpiFullName:work@ScratchPad.calcBaseAddrs |vpiForInitStmt: - \_assign_stmt: , line:23:14, endln:23:19 + \_assignment: , line:23:14, endln:23:19 |vpiParent: \_for_stmt: (work@ScratchPad.calcBaseAddrs), line:23:9, endln:23:12 |vpiRhs: @@ -2003,7 +2001,7 @@ design: (work@ScratchPad) |vpiLhs: \_ref_var: (work@ScratchPad.calcBaseAddrs.i), line:23:14, endln:23:15 |vpiParent: - \_assign_stmt: , line:23:14, endln:23:19 + \_assignment: , line:23:14, endln:23:19 |vpiName:i |vpiFullName:work@ScratchPad.calcBaseAddrs.i |vpiActual: diff --git a/tests/FuncArgDirection/FuncArgDirection.log b/tests/FuncArgDirection/FuncArgDirection.log index 9108b1184c..13f1c3601f 100644 --- a/tests/FuncArgDirection/FuncArgDirection.log +++ b/tests/FuncArgDirection/FuncArgDirection.log @@ -482,8 +482,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 -assignment 1 +assignment 3 begin 2 bit_select 2 class_defn 8 @@ -517,8 +516,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 3 -assignment 2 +assignment 5 begin 4 bit_select 4 class_defn 8 @@ -1106,13 +1104,13 @@ design: (work@dut) \_begin: (work@dut.aes_rev_order_bit), line:4:3, endln:6:6 |vpiFullName:work@dut.aes_rev_order_bit |vpiForInitStmt: - \_assign_stmt: , line:4:8, endln:4:15 + \_assignment: , line:4:8, endln:4:15 |vpiParent: \_for_stmt: (work@dut.aes_rev_order_bit), line:4:3, endln:4:6 |vpiRhs: \_constant: , line:4:14, endln:4:15 |vpiParent: - \_assign_stmt: , line:4:8, endln:4:15 + \_assignment: , line:4:8, endln:4:15 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1120,7 +1118,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.aes_rev_order_bit.i), line:4:12, endln:4:13 |vpiParent: - \_assign_stmt: , line:4:8, endln:4:15 + \_assignment: , line:4:8, endln:4:15 |vpiTypespec: \_ref_typespec: (work@dut.aes_rev_order_bit.i) |vpiParent: @@ -1410,7 +1408,7 @@ design: (work@dut) \_begin: (work@dut.aes_rev_order_bit), line:4:3, endln:6:6 |vpiFullName:work@dut.aes_rev_order_bit |vpiForInitStmt: - \_assign_stmt: , line:4:8, endln:4:15 + \_assignment: , line:4:8, endln:4:15 |vpiParent: \_for_stmt: (work@dut.aes_rev_order_bit), line:4:3, endln:4:6 |vpiRhs: @@ -1418,7 +1416,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.aes_rev_order_bit.i), line:4:12, endln:4:13 |vpiParent: - \_assign_stmt: , line:4:8, endln:4:15 + \_assignment: , line:4:8, endln:4:15 |vpiTypespec: \_ref_typespec: (work@dut.aes_rev_order_bit.i) |vpiParent: diff --git a/tests/FuncBindGen/FuncBindGen.log b/tests/FuncBindGen/FuncBindGen.log index 8de3c8ee50..8ee40b1039 100644 --- a/tests/FuncBindGen/FuncBindGen.log +++ b/tests/FuncBindGen/FuncBindGen.log @@ -187,7 +187,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 constant 26 cont_assign 3 @@ -216,7 +216,7 @@ return_stmt 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 +assignment 2 begin 2 constant 26 cont_assign 4 @@ -607,13 +607,15 @@ design: (work@top) |vpiName:dec_tmp_sub |vpiFullName:work@top.gen_block.get_casted_param.dec_tmp_sub |vpiStmt: - \_assign_stmt: , line:7:32, endln:7:65 + \_assignment: , line:7:32, endln:7:65 |vpiParent: \_begin: (work@top.gen_block.get_casted_param), line:8:10, endln:8:29 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:7:46, endln:7:65 |vpiParent: - \_assign_stmt: , line:7:32, endln:7:65 + \_assignment: , line:7:32, endln:7:65 |vpiTypespec: \_ref_typespec: (work@top.gen_block.get_casted_param) |vpiParent: @@ -640,7 +642,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.gen_block.get_casted_param.dec_tmp_sub), line:7:32, endln:7:43 |vpiParent: - \_assign_stmt: , line:7:32, endln:7:65 + \_assignment: , line:7:32, endln:7:65 |vpiTypespec: \_ref_typespec: (work@top.gen_block.get_casted_param.dec_tmp_sub) |vpiParent: @@ -683,7 +685,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.gen_block.get_casted_param.dec_tmp_sub), line:7:32, endln:7:43 |vpiParent: - \_assign_stmt: , line:7:32, endln:7:65 + \_assignment: , line:7:32, endln:7:65 |vpiTypespec: \_ref_typespec: (work@top.gen_block.get_casted_param.dec_tmp_sub) |vpiParent: @@ -705,13 +707,15 @@ design: (work@top) |vpiVariables: \_logic_var: (work@top.gen_block.get_casted_param.dec_tmp_sub), line:7:32, endln:7:43 |vpiStmt: - \_assign_stmt: , line:7:32, endln:7:65 + \_assignment: , line:7:32, endln:7:65 |vpiParent: \_begin: (work@top.gen_block.get_casted_param), line:8:10, endln:8:29 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_operation: , line:7:46, endln:7:65 |vpiParent: - \_assign_stmt: , line:7:32, endln:7:65 + \_assignment: , line:7:32, endln:7:65 |vpiTypespec: \_ref_typespec: (work@top.gen_block.get_casted_param) |vpiParent: diff --git a/tests/FuncDef/FuncDef.log b/tests/FuncDef/FuncDef.log index 6296821409..3de591017b 100644 --- a/tests/FuncDef/FuncDef.log +++ b/tests/FuncDef/FuncDef.log @@ -184,8 +184,7 @@ AST_DEBUG_END [WRN:EL0513] Nb undefined instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 3 +assignment 4 begin 1 constant 7 design 1 @@ -210,8 +209,7 @@ udp 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 6 +assignment 8 begin 2 constant 7 design 1 @@ -327,13 +325,13 @@ design: (work@mulAddRecFNToRaw_preMul) \_begin: (work@mulAddRecFNToRaw_preMul.clog2), line:6:5, endln:9:8 |vpiFullName:work@mulAddRecFNToRaw_preMul.clog2 |vpiForInitStmt: - \_assign_stmt: , line:8:14, endln:8:23 + \_assignment: , line:8:14, endln:8:23 |vpiParent: \_for_stmt: (work@mulAddRecFNToRaw_preMul.clog2), line:8:9, endln:8:12 |vpiRhs: \_constant: , line:8:22, endln:8:23 |vpiParent: - \_assign_stmt: , line:8:14, endln:8:23 + \_assignment: , line:8:14, endln:8:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -341,7 +339,7 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiLhs: \_ref_var: (work@mulAddRecFNToRaw_preMul.clog2.clog2), line:8:14, endln:8:19 |vpiParent: - \_assign_stmt: , line:8:14, endln:8:23 + \_assignment: , line:8:14, endln:8:23 |vpiName:clog2 |vpiFullName:work@mulAddRecFNToRaw_preMul.clog2.clog2 |vpiForIncStmt: @@ -559,7 +557,7 @@ design: (work@mulAddRecFNToRaw_preMul) \_begin: (work@mulAddRecFNToRaw_preMul.clog2), line:6:5, endln:9:8 |vpiFullName:work@mulAddRecFNToRaw_preMul.clog2 |vpiForInitStmt: - \_assign_stmt: , line:8:14, endln:8:23 + \_assignment: , line:8:14, endln:8:23 |vpiParent: \_for_stmt: (work@mulAddRecFNToRaw_preMul.clog2), line:8:9, endln:8:12 |vpiRhs: @@ -567,7 +565,7 @@ design: (work@mulAddRecFNToRaw_preMul) |vpiLhs: \_ref_var: (work@mulAddRecFNToRaw_preMul.clog2.clog2), line:8:14, endln:8:19 |vpiParent: - \_assign_stmt: , line:8:14, endln:8:23 + \_assignment: , line:8:14, endln:8:23 |vpiName:clog2 |vpiFullName:work@mulAddRecFNToRaw_preMul.clog2.clog2 |vpiActual: @@ -712,5 +710,5 @@ design: (work@mulAddRecFNToRaw_preMul) ============================== End Linting Results ============================== ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/FuncDef/dut.sv | ${SURELOG_DIR}/build/regression/FuncDef/roundtrip/dut_000.sv | 5 | 16 | +[roundtrip]: ${SURELOG_DIR}/tests/FuncDef/dut.sv | ${SURELOG_DIR}/build/regression/FuncDef/roundtrip/dut_000.sv | 6 | 16 | ============================== End RoundTrip Results ============================== diff --git a/tests/FuncDef2/FuncDef2.log b/tests/FuncDef2/FuncDef2.log index 3b1d4652f0..489691d49f 100644 --- a/tests/FuncDef2/FuncDef2.log +++ b/tests/FuncDef2/FuncDef2.log @@ -3631,8 +3631,7 @@ AST_DEBUG_END always 7 array_net 1 array_typespec 1 -assign_stmt 37 -assignment 115 +assignment 152 begin 97 bit_select 39 bit_typespec 9 @@ -3684,8 +3683,7 @@ unsupported_typespec 10 always 11 array_net 1 array_typespec 1 -assign_stmt 40 -assignment 276 +assignment 316 begin 236 bit_select 76 bit_typespec 9 @@ -4483,13 +4481,13 @@ design: (work@tnoc_vc_splitter) \_begin: (tnoc_pkg::tnoc_clog2), line:69:5, endln:69:17 |vpiFullName:tnoc_pkg::tnoc_clog2 |vpiForInitStmt: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiParent: \_for_stmt: (tnoc_pkg::tnoc_clog2), line:70:5, endln:70:8 |vpiRhs: \_constant: , line:70:18, endln:70:20 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiDecompile:31 |vpiSize:64 |UINT:31 @@ -4497,7 +4495,7 @@ design: (work@tnoc_vc_splitter) |vpiLhs: \_int_var: (tnoc_pkg::tnoc_clog2::i), line:70:14, endln:70:15 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiTypespec: \_ref_typespec: (tnoc_pkg::tnoc_clog2::i) |vpiParent: @@ -4732,7 +4730,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiParent: \_operation: , line:86:9, endln:86:34 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:86:9, endln:86:22 |vpiParent: @@ -4748,6 +4745,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_x_width::size_x |vpiActual: \_typespec_member: (size_x), line:45:15, endln:45:21 + |vpiName:packet_config.size_x |vpiOperand: \_constant: , line:86:33, endln:86:34 |vpiParent: @@ -4773,7 +4771,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiParent: \_func_call: (tnoc_clog2), line:87:14, endln:87:46 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:87:25, endln:87:38 |vpiParent: @@ -4789,6 +4786,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_x_width::size_x |vpiActual: \_typespec_member: (size_x), line:45:15, endln:45:21 + |vpiName:packet_config.size_x |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -4856,7 +4854,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiParent: \_operation: , line:95:9, endln:95:34 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:95:9, endln:95:22 |vpiParent: @@ -4872,6 +4869,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_y_width::size_y |vpiActual: \_typespec_member: (size_y), line:46:15, endln:46:21 + |vpiName:packet_config.size_y |vpiOperand: \_constant: , line:95:33, endln:95:34 |vpiParent: @@ -4897,7 +4895,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiParent: \_func_call: (tnoc_clog2), line:96:14, endln:96:46 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:96:25, endln:96:38 |vpiParent: @@ -4913,6 +4910,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_y_width::size_y |vpiActual: \_typespec_member: (size_y), line:46:15, endln:46:21 + |vpiName:packet_config.size_y |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -5055,7 +5053,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiParent: \_operation: , line:108:9, endln:108:44 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:108:9, endln:108:22 |vpiParent: @@ -5071,6 +5068,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels |vpiActual: \_typespec_member: (virtual_channels), line:47:15, endln:47:31 + |vpiName:packet_config.virtual_channels |vpiOperand: \_constant: , line:108:43, endln:108:44 |vpiParent: @@ -5096,7 +5094,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiParent: \_func_call: (tnoc_clog2), line:109:14, endln:109:56 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:109:25, endln:109:38 |vpiParent: @@ -5112,6 +5109,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels |vpiActual: \_typespec_member: (virtual_channels), line:47:15, endln:47:31 + |vpiName:packet_config.virtual_channels |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -5179,7 +5177,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiParent: \_operation: , line:117:9, endln:117:32 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:117:9, endln:117:22 |vpiParent: @@ -5195,6 +5192,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_tag_width::tags |vpiActual: \_typespec_member: (tags), line:48:15, endln:48:19 + |vpiName:packet_config.tags |vpiOperand: \_constant: , line:117:31, endln:117:32 |vpiParent: @@ -5220,7 +5218,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiParent: \_func_call: (tnoc_clog2), line:118:14, endln:118:44 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:118:25, endln:118:38 |vpiParent: @@ -5236,6 +5233,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_tag_width::tags |vpiActual: \_typespec_member: (tags), line:48:15, endln:48:19 + |vpiName:packet_config.tags |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -5303,7 +5301,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiParent: \_operation: , line:126:9, endln:126:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:126:9, endln:126:22 |vpiParent: @@ -5319,6 +5316,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:126:41, endln:126:43 |vpiParent: @@ -5358,7 +5356,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiParent: \_operation: , line:127:36, endln:127:68 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:127:36, endln:127:49 |vpiParent: @@ -5374,6 +5371,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:127:67, endln:127:68 |vpiParent: @@ -5464,7 +5462,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiParent: \_operation: , line:135:23, endln:135:56 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:135:23, endln:135:36 |vpiParent: @@ -5480,6 +5477,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:135:55, endln:135:56 |vpiParent: @@ -5540,7 +5538,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiParent: \_operation: , line:139:9, endln:139:43 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:139:9, endln:139:22 |vpiParent: @@ -5556,6 +5553,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:139:42, endln:139:43 |vpiParent: @@ -5581,7 +5579,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiParent: \_func_call: (tnoc_clog2), line:140:14, endln:140:55 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:140:25, endln:140:38 |vpiParent: @@ -5597,6 +5594,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -5664,7 +5662,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiParent: \_operation: , line:148:9, endln:148:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:148:9, endln:148:22 |vpiParent: @@ -5680,6 +5677,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:148:41, endln:148:43 |vpiParent: @@ -5710,7 +5708,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiParent: \_operation: , line:149:25, endln:149:57 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:149:25, endln:149:38 |vpiParent: @@ -5726,6 +5723,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:149:56, endln:149:57 |vpiParent: @@ -5801,7 +5799,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiParent: \_operation: , line:157:9, endln:157:39 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:157:9, endln:157:22 |vpiParent: @@ -5817,6 +5814,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_end_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:157:37, endln:157:39 |vpiParent: @@ -5847,7 +5845,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiParent: \_operation: , line:158:25, endln:158:53 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:158:25, endln:158:38 |vpiParent: @@ -5863,6 +5860,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_end_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:158:52, endln:158:53 |vpiParent: @@ -5973,7 +5971,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiParent: \_operation: , line:167:19, endln:167:47 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:167:19, endln:167:32 |vpiParent: @@ -5989,6 +5986,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_burst_length_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:167:46, endln:167:47 |vpiParent: @@ -6027,7 +6025,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiParent: \_operation: , line:168:24, endln:168:66 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:168:24, endln:168:37 |vpiParent: @@ -6043,6 +6040,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_burst_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_ref_obj: (tnoc_pkg::get_burst_length_width::byte_width), line:168:56, endln:168:66 |vpiParent: @@ -7035,7 +7033,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiParent: \_assignment: , line:245:5, endln:245:41 - |vpiName:packet_config.address_width |vpiActual: \_ref_obj: (packet_config), line:245:14, endln:245:27 |vpiParent: @@ -7051,6 +7048,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_request_header_width::address_width |vpiActual: \_typespec_member: (address_width), line:49:15, endln:49:28 + |vpiName:packet_config.address_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_header_width::width), line:245:5, endln:245:10 |vpiParent: @@ -7641,7 +7639,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiParent: \_assignment: , line:277:5, endln:277:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:277:14, endln:277:27 |vpiParent: @@ -7657,6 +7654,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_request_payload_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_payload_width::width), line:277:5, endln:277:10 |vpiParent: @@ -7680,7 +7678,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiParent: \_operation: , line:278:14, endln:278:42 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:278:14, endln:278:27 |vpiParent: @@ -7696,6 +7693,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_request_payload_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:278:41, endln:278:42 |vpiParent: @@ -7823,7 +7821,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiParent: \_assignment: , line:285:5, endln:285:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:285:14, endln:285:27 |vpiParent: @@ -7839,6 +7836,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_response_payload_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_response_payload_width::width), line:285:5, endln:285:10 |vpiParent: @@ -10287,13 +10285,13 @@ design: (work@tnoc_vc_splitter) \_begin: (tnoc_pkg::tnoc_clog2), line:69:5, endln:69:17 |vpiFullName:tnoc_pkg::tnoc_clog2 |vpiForInitStmt: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiParent: \_for_stmt: (tnoc_pkg::tnoc_clog2), line:70:5, endln:70:8 |vpiRhs: \_constant: , line:70:18, endln:70:20 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiDecompile:31 |vpiSize:64 |UINT:31 @@ -10301,7 +10299,7 @@ design: (work@tnoc_vc_splitter) |vpiLhs: \_int_var: (tnoc_pkg::tnoc_clog2::i), line:70:14, endln:70:15 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiTypespec: \_ref_typespec: (tnoc_pkg::tnoc_clog2::i) |vpiParent: @@ -10536,7 +10534,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiParent: \_operation: , line:86:9, endln:86:34 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:86:9, endln:86:22 |vpiParent: @@ -10552,6 +10549,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_x_width::size_x |vpiActual: \_typespec_member: (size_x), line:45:15, endln:45:21 + |vpiName:packet_config.size_x |vpiOperand: \_constant: , line:86:33, endln:86:34 |vpiParent: @@ -10577,7 +10575,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiParent: \_func_call: (tnoc_clog2), line:87:14, endln:87:46 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:87:25, endln:87:38 |vpiParent: @@ -10593,6 +10590,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_x_width::size_x |vpiActual: \_typespec_member: (size_x), line:45:15, endln:45:21 + |vpiName:packet_config.size_x |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -10660,7 +10658,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiParent: \_operation: , line:95:9, endln:95:34 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:95:9, endln:95:22 |vpiParent: @@ -10676,6 +10673,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_y_width::size_y |vpiActual: \_typespec_member: (size_y), line:46:15, endln:46:21 + |vpiName:packet_config.size_y |vpiOperand: \_constant: , line:95:33, endln:95:34 |vpiParent: @@ -10701,7 +10699,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiParent: \_func_call: (tnoc_clog2), line:96:14, endln:96:46 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:96:25, endln:96:38 |vpiParent: @@ -10717,6 +10714,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_id_y_width::size_y |vpiActual: \_typespec_member: (size_y), line:46:15, endln:46:21 + |vpiName:packet_config.size_y |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -10873,7 +10871,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiParent: \_operation: , line:108:9, endln:108:44 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:108:9, endln:108:22 |vpiParent: @@ -10889,6 +10886,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels |vpiActual: \_typespec_member: (virtual_channels), line:47:15, endln:47:31 + |vpiName:packet_config.virtual_channels |vpiOperand: \_constant: , line:108:43, endln:108:44 |vpiParent: @@ -10914,7 +10912,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiParent: \_func_call: (tnoc_clog2), line:109:14, endln:109:56 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:109:25, endln:109:38 |vpiParent: @@ -10930,6 +10927,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels |vpiActual: \_typespec_member: (virtual_channels), line:47:15, endln:47:31 + |vpiName:packet_config.virtual_channels |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -10997,7 +10995,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiParent: \_operation: , line:117:9, endln:117:32 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:117:9, endln:117:22 |vpiParent: @@ -11013,6 +11010,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_tag_width::tags |vpiActual: \_typespec_member: (tags), line:48:15, endln:48:19 + |vpiName:packet_config.tags |vpiOperand: \_constant: , line:117:31, endln:117:32 |vpiParent: @@ -11038,7 +11036,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiParent: \_func_call: (tnoc_clog2), line:118:14, endln:118:44 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:118:25, endln:118:38 |vpiParent: @@ -11054,6 +11051,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_tag_width::tags |vpiActual: \_typespec_member: (tags), line:48:15, endln:48:19 + |vpiName:packet_config.tags |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -11121,7 +11119,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiParent: \_operation: , line:126:9, endln:126:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:126:9, endln:126:22 |vpiParent: @@ -11137,6 +11134,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:126:41, endln:126:43 |vpiParent: @@ -11176,7 +11174,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiParent: \_operation: , line:127:36, endln:127:68 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:127:36, endln:127:49 |vpiParent: @@ -11192,6 +11189,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:127:67, endln:127:68 |vpiParent: @@ -11289,7 +11287,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiParent: \_operation: , line:135:23, endln:135:56 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:135:23, endln:135:36 |vpiParent: @@ -11305,6 +11302,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:135:55, endln:135:56 |vpiParent: @@ -11365,7 +11363,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiParent: \_operation: , line:139:9, endln:139:43 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:139:9, endln:139:22 |vpiParent: @@ -11381,6 +11378,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:139:42, endln:139:43 |vpiParent: @@ -11406,7 +11404,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiParent: \_func_call: (tnoc_clog2), line:140:14, endln:140:55 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:140:25, endln:140:38 |vpiParent: @@ -11422,6 +11419,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -11489,7 +11487,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiParent: \_operation: , line:148:9, endln:148:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:148:9, endln:148:22 |vpiParent: @@ -11505,6 +11502,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:148:41, endln:148:43 |vpiParent: @@ -11535,7 +11533,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiParent: \_operation: , line:149:25, endln:149:57 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:149:25, endln:149:38 |vpiParent: @@ -11551,6 +11548,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:149:56, endln:149:57 |vpiParent: @@ -11626,7 +11624,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiParent: \_operation: , line:157:9, endln:157:39 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:157:9, endln:157:22 |vpiParent: @@ -11642,6 +11639,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_end_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:157:37, endln:157:39 |vpiParent: @@ -11672,7 +11670,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiParent: \_operation: , line:158:25, endln:158:53 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:158:25, endln:158:38 |vpiParent: @@ -11688,6 +11685,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_byte_end_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:158:52, endln:158:53 |vpiParent: @@ -11798,7 +11796,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiParent: \_operation: , line:167:19, endln:167:47 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:167:19, endln:167:32 |vpiParent: @@ -11814,6 +11811,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_burst_length_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:167:46, endln:167:47 |vpiParent: @@ -11859,7 +11857,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiParent: \_operation: , line:168:24, endln:168:66 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:168:24, endln:168:37 |vpiParent: @@ -11875,6 +11872,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_burst_length_width::max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_ref_obj: (tnoc_pkg::get_burst_length_width::byte_width), line:168:56, endln:168:66 |vpiParent: @@ -12944,7 +12942,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiParent: \_assignment: , line:245:5, endln:245:41 - |vpiName:packet_config.address_width |vpiActual: \_ref_obj: (packet_config), line:245:14, endln:245:27 |vpiParent: @@ -12960,6 +12957,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_request_header_width::address_width |vpiActual: \_typespec_member: (address_width), line:49:15, endln:49:28 + |vpiName:packet_config.address_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_header_width::width), line:245:5, endln:245:10 |vpiParent: @@ -13540,7 +13538,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiParent: \_assignment: , line:277:5, endln:277:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:277:14, endln:277:27 |vpiParent: @@ -13556,6 +13553,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_request_payload_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_payload_width::width), line:277:5, endln:277:10 |vpiParent: @@ -13579,7 +13577,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiParent: \_operation: , line:278:14, endln:278:42 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:278:14, endln:278:27 |vpiParent: @@ -13595,6 +13592,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_request_payload_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:278:41, endln:278:42 |vpiParent: @@ -13722,7 +13720,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiParent: \_assignment: , line:285:5, endln:285:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:285:14, endln:285:27 |vpiParent: @@ -13738,6 +13735,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:tnoc_pkg::get_response_payload_width::data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_response_payload_width::width), line:285:5, endln:285:10 |vpiParent: @@ -15870,7 +15868,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (PACKET_CONFIG.virtual_channels), line:409:51, endln:409:81 |vpiParent: \_param_assign: , line:409:35, endln:409:81 - |vpiName:PACKET_CONFIG.virtual_channels |vpiActual: \_ref_obj: (PACKET_CONFIG), line:409:65, endln:409:81 |vpiParent: @@ -15881,6 +15878,7 @@ design: (work@tnoc_vc_splitter) |vpiParent: \_hier_path: (PACKET_CONFIG.virtual_channels), line:409:51, endln:409:81 |vpiName:virtual_channels + |vpiName:PACKET_CONFIG.virtual_channels |vpiLhs: \_parameter: (work@tnoc_vc_splitter.CHANNELS), line:409:35, endln:409:43 |vpiTypedef: @@ -15964,7 +15962,7 @@ design: (work@tnoc_vc_splitter) \_begin: (tnoc_pkg::tnoc_clog2), line:69:5, endln:69:17 |vpiFullName:tnoc_pkg::tnoc_clog2 |vpiForInitStmt: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiParent: \_for_stmt: (tnoc_pkg::tnoc_clog2), line:70:5, endln:70:8 |vpiRhs: @@ -15972,7 +15970,7 @@ design: (work@tnoc_vc_splitter) |vpiLhs: \_int_var: (tnoc_pkg::tnoc_clog2::i), line:70:14, endln:70:15 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiTypespec: \_ref_typespec: (tnoc_pkg::tnoc_clog2::i) |vpiParent: @@ -16178,7 +16176,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiParent: \_operation: , line:86:9, endln:86:34 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:86:9, endln:86:22 |vpiParent: @@ -16192,6 +16189,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiName:size_x |vpiFullName:tnoc_pkg::get_id_x_width::size_x + |vpiName:packet_config.size_x |vpiOperand: \_constant: , line:86:33, endln:86:34 |vpiStmt: @@ -16211,7 +16209,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiParent: \_func_call: (tnoc_clog2), line:87:14, endln:87:46 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:87:25, endln:87:38 |vpiParent: @@ -16225,6 +16222,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiName:size_x |vpiFullName:tnoc_pkg::get_id_x_width::size_x + |vpiName:packet_config.size_x |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -16277,7 +16275,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiParent: \_operation: , line:95:9, endln:95:34 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:95:9, endln:95:22 |vpiParent: @@ -16291,6 +16288,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiName:size_y |vpiFullName:tnoc_pkg::get_id_y_width::size_y + |vpiName:packet_config.size_y |vpiOperand: \_constant: , line:95:33, endln:95:34 |vpiStmt: @@ -16310,7 +16308,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiParent: \_func_call: (tnoc_clog2), line:96:14, endln:96:46 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:96:25, endln:96:38 |vpiParent: @@ -16324,6 +16321,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiName:size_y |vpiFullName:tnoc_pkg::get_id_y_width::size_y + |vpiName:packet_config.size_y |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -16454,7 +16452,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiParent: \_operation: , line:108:9, endln:108:44 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:108:9, endln:108:22 |vpiParent: @@ -16468,6 +16465,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiName:virtual_channels |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels + |vpiName:packet_config.virtual_channels |vpiOperand: \_constant: , line:108:43, endln:108:44 |vpiStmt: @@ -16487,7 +16485,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiParent: \_func_call: (tnoc_clog2), line:109:14, endln:109:56 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:109:25, endln:109:38 |vpiParent: @@ -16501,6 +16498,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiName:virtual_channels |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels + |vpiName:packet_config.virtual_channels |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -16553,7 +16551,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiParent: \_operation: , line:117:9, endln:117:32 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:117:9, endln:117:22 |vpiParent: @@ -16567,6 +16564,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiName:tags |vpiFullName:tnoc_pkg::get_tag_width::tags + |vpiName:packet_config.tags |vpiOperand: \_constant: , line:117:31, endln:117:32 |vpiStmt: @@ -16586,7 +16584,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiParent: \_func_call: (tnoc_clog2), line:118:14, endln:118:44 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:118:25, endln:118:38 |vpiParent: @@ -16600,6 +16597,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiName:tags |vpiFullName:tnoc_pkg::get_tag_width::tags + |vpiName:packet_config.tags |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -16652,7 +16650,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiParent: \_operation: , line:126:9, endln:126:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:126:9, endln:126:22 |vpiParent: @@ -16666,6 +16663,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:126:41, endln:126:43 |vpiStmt: @@ -16699,7 +16697,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiParent: \_operation: , line:127:36, endln:127:68 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:127:36, endln:127:49 |vpiParent: @@ -16713,6 +16710,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:127:67, endln:127:68 |vpiName:tnoc_clog2 @@ -16783,7 +16781,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiParent: \_operation: , line:135:23, endln:135:56 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:135:23, endln:135:36 |vpiParent: @@ -16797,6 +16794,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_byte_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:135:55, endln:135:56 |vpiName:tnoc_clog2 @@ -16840,7 +16838,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiParent: \_operation: , line:139:9, endln:139:43 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:139:9, endln:139:22 |vpiParent: @@ -16854,6 +16851,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:139:42, endln:139:43 |vpiStmt: @@ -16873,7 +16871,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiParent: \_func_call: (tnoc_clog2), line:140:14, endln:140:55 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:140:25, endln:140:38 |vpiParent: @@ -16887,6 +16884,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -16939,7 +16937,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiParent: \_operation: , line:148:9, endln:148:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:148:9, endln:148:22 |vpiParent: @@ -16953,6 +16950,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:148:41, endln:148:43 |vpiStmt: @@ -16977,7 +16975,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiParent: \_operation: , line:149:25, endln:149:57 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:149:25, endln:149:38 |vpiParent: @@ -16991,6 +16988,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:149:56, endln:149:57 |vpiName:tnoc_clog2 @@ -17045,7 +17043,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiParent: \_operation: , line:157:9, endln:157:39 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:157:9, endln:157:22 |vpiParent: @@ -17059,6 +17056,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiName:data_width |vpiFullName:tnoc_pkg::get_byte_end_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:157:37, endln:157:39 |vpiStmt: @@ -17083,7 +17081,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiParent: \_operation: , line:158:25, endln:158:53 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:158:25, endln:158:38 |vpiParent: @@ -17097,6 +17094,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiName:data_width |vpiFullName:tnoc_pkg::get_byte_end_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:158:52, endln:158:53 |vpiName:tnoc_clog2 @@ -17174,7 +17172,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiParent: \_operation: , line:167:19, endln:167:47 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:167:19, endln:167:32 |vpiParent: @@ -17188,6 +17185,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiName:data_width |vpiFullName:tnoc_pkg::get_burst_length_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:167:46, endln:167:47 |vpiLhs: @@ -17227,7 +17225,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiParent: \_operation: , line:168:24, endln:168:66 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:168:24, endln:168:37 |vpiParent: @@ -17241,6 +17238,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_burst_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiOperand: \_ref_obj: (tnoc_pkg::get_burst_length_width::byte_width), line:168:56, endln:168:66 |vpiParent: @@ -18096,7 +18094,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiParent: \_assignment: , line:245:5, endln:245:41 - |vpiName:packet_config.address_width |vpiActual: \_ref_obj: (packet_config), line:245:14, endln:245:27 |vpiParent: @@ -18110,6 +18107,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiName:address_width |vpiFullName:tnoc_pkg::get_request_header_width::address_width + |vpiName:packet_config.address_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_header_width::width), line:245:5, endln:245:10 |vpiParent: @@ -18601,7 +18599,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiParent: \_assignment: , line:277:5, endln:277:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:277:14, endln:277:27 |vpiParent: @@ -18615,6 +18612,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiName:data_width |vpiFullName:tnoc_pkg::get_request_payload_width::data_width + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_payload_width::width), line:277:5, endln:277:10 |vpiParent: @@ -18638,7 +18636,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiParent: \_operation: , line:278:14, endln:278:42 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:278:14, endln:278:27 |vpiParent: @@ -18652,6 +18649,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiName:data_width |vpiFullName:tnoc_pkg::get_request_payload_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:278:41, endln:278:42 |vpiLhs: @@ -18746,7 +18744,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiParent: \_assignment: , line:285:5, endln:285:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:285:14, endln:285:27 |vpiParent: @@ -18760,6 +18757,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiName:data_width |vpiFullName:tnoc_pkg::get_response_payload_width::data_width + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_response_payload_width::width), line:285:5, endln:285:10 |vpiParent: @@ -20290,7 +20288,7 @@ design: (work@tnoc_vc_splitter) |vpiParent: \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 |vpiForInitStmt: - \_assign_stmt: , line:415:8, endln:415:20 + \_assignment: , line:415:8, endln:415:20 |vpiParent: \_gen_for: |vpiRhs: @@ -20302,7 +20300,7 @@ design: (work@tnoc_vc_splitter) |vpiLhs: \_int_var: (work@tnoc_vc_splitter.i), line:415:15, endln:415:16 |vpiParent: - \_assign_stmt: , line:415:8, endln:415:20 + \_assignment: , line:415:8, endln:415:20 |vpiTypespec: \_ref_typespec: (work@tnoc_vc_splitter.i) |vpiParent: @@ -20369,7 +20367,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.valid[i]), line:417:33, endln:417:53 |vpiParent: \_assignment: , line:417:7, endln:417:53 - |vpiName:receiver_if.valid[i] |vpiActual: \_ref_obj: (receiver_if), line:417:33, endln:417:44 |vpiParent: @@ -20387,11 +20384,11 @@ design: (work@tnoc_vc_splitter) \_bit_select: (work@tnoc_vc_splitter.g.receiver_if.valid[i].valid), line:417:51, endln:417:52 |vpiName:i |vpiFullName:work@tnoc_vc_splitter.g.receiver_if.valid[i].i + |vpiName:receiver_if.valid[i] |vpiLhs: \_hier_path: (sender_if[i].valid), line:417:7, endln:417:16 |vpiParent: \_assignment: , line:417:7, endln:417:53 - |vpiName:sender_if[i].valid |vpiActual: \_bit_select: (sender_if[i]), line:417:7, endln:417:16 |vpiParent: @@ -20410,6 +20407,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].valid), line:417:7, endln:417:16 |vpiName:valid |vpiFullName:sender_if[i].valid + |vpiName:sender_if[i].valid |vpiStmt: \_assignment: , line:418:7, endln:418:51 |vpiParent: @@ -20420,7 +20418,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].ready), line:418:33, endln:418:51 |vpiParent: \_assignment: , line:418:7, endln:418:51 - |vpiName:sender_if[i].ready |vpiActual: \_bit_select: (sender_if[i]), line:418:33, endln:418:42 |vpiParent: @@ -20439,11 +20436,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].ready), line:418:33, endln:418:51 |vpiName:ready |vpiFullName:work@tnoc_vc_splitter.g.ready + |vpiName:sender_if[i].ready |vpiLhs: \_hier_path: (receiver_if.ready[i]), line:418:7, endln:418:27 |vpiParent: \_assignment: , line:418:7, endln:418:51 - |vpiName:receiver_if.ready[i] |vpiActual: \_ref_obj: (receiver_if), line:418:19, endln:418:24 |vpiParent: @@ -20461,6 +20458,7 @@ design: (work@tnoc_vc_splitter) \_bit_select: (work@tnoc_vc_splitter.g.receiver_if.ready[i].ready), line:418:25, endln:418:26 |vpiName:i |vpiFullName:work@tnoc_vc_splitter.g.receiver_if.ready[i].i + |vpiName:receiver_if.ready[i] |vpiStmt: \_assignment: , line:419:7, endln:419:54 |vpiParent: @@ -20471,7 +20469,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].vc_ready), line:419:33, endln:419:54 |vpiParent: \_assignment: , line:419:7, endln:419:54 - |vpiName:sender_if[i].vc_ready |vpiActual: \_bit_select: (sender_if[i]), line:419:33, endln:419:42 |vpiParent: @@ -20490,11 +20487,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].vc_ready), line:419:33, endln:419:54 |vpiName:vc_ready |vpiFullName:work@tnoc_vc_splitter.g.vc_ready + |vpiName:sender_if[i].vc_ready |vpiLhs: \_hier_path: (receiver_if.vc_ready[i]), line:419:7, endln:419:30 |vpiParent: \_assignment: , line:419:7, endln:419:54 - |vpiName:receiver_if.vc_ready[i] |vpiActual: \_ref_obj: (receiver_if), line:419:19, endln:419:27 |vpiParent: @@ -20512,6 +20509,7 @@ design: (work@tnoc_vc_splitter) \_bit_select: (work@tnoc_vc_splitter.g.receiver_if.vc_ready[i].vc_ready), line:419:28, endln:419:29 |vpiName:i |vpiFullName:work@tnoc_vc_splitter.g.receiver_if.vc_ready[i].i + |vpiName:receiver_if.vc_ready[i] |vpiAlwaysType:2 |vpiStmt: \_gen_if_else: , line:422:5, endln:431:8 @@ -20553,7 +20551,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.flit[i]), line:424:29, endln:424:48 |vpiParent: \_assignment: , line:424:9, endln:424:48 - |vpiName:receiver_if.flit[i] |vpiActual: \_ref_obj: (receiver_if), line:424:29, endln:424:40 |vpiParent: @@ -20571,11 +20568,11 @@ design: (work@tnoc_vc_splitter) \_bit_select: (work@tnoc_vc_splitter.g.g.receiver_if.flit[i].flit), line:424:46, endln:424:47 |vpiName:i |vpiFullName:work@tnoc_vc_splitter.g.g.receiver_if.flit[i].i + |vpiName:receiver_if.flit[i] |vpiLhs: \_hier_path: (sender_if[i].flit), line:424:9, endln:424:18 |vpiParent: \_assignment: , line:424:9, endln:424:48 - |vpiName:sender_if[i].flit |vpiActual: \_bit_select: (sender_if[i]), line:424:9, endln:424:18 |vpiParent: @@ -20594,6 +20591,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].flit), line:424:9, endln:424:18 |vpiName:flit |vpiFullName:sender_if[i].flit + |vpiName:sender_if[i].flit |vpiAlwaysType:2 |vpiElseStmt: \_named_begin: (work@tnoc_vc_splitter.g.g) @@ -20620,7 +20618,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.flit), line:429:29, endln:429:45 |vpiParent: \_assignment: , line:429:9, endln:429:45 - |vpiName:receiver_if.flit |vpiActual: \_ref_obj: (receiver_if), line:429:29, endln:429:40 |vpiParent: @@ -20632,11 +20629,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.flit), line:429:29, endln:429:45 |vpiName:flit |vpiFullName:work@tnoc_vc_splitter.g.g.flit + |vpiName:receiver_if.flit |vpiLhs: \_hier_path: (sender_if[i].flit), line:429:9, endln:429:18 |vpiParent: \_assignment: , line:429:9, endln:429:45 - |vpiName:sender_if[i].flit |vpiActual: \_bit_select: (sender_if[i]), line:429:9, endln:429:18 |vpiParent: @@ -20655,6 +20652,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].flit), line:429:9, endln:429:18 |vpiName:flit |vpiFullName:sender_if[i].flit + |vpiName:sender_if[i].flit |vpiAlwaysType:2 |uhdmtopModules: \_module_inst: work@tnoc_vc_splitter (work@tnoc_vc_splitter), file:${SURELOG_DIR}/tests/FuncDef2/dut.sv, line:404:1, endln:433:10 @@ -21068,7 +21066,7 @@ design: (work@tnoc_vc_splitter) \_begin: (work@tnoc_vc_splitter.tnoc_clog2), line:69:5, endln:69:17 |vpiFullName:work@tnoc_vc_splitter.tnoc_clog2 |vpiForInitStmt: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiParent: \_for_stmt: (work@tnoc_vc_splitter.tnoc_clog2), line:70:5, endln:70:8 |vpiRhs: @@ -21076,7 +21074,7 @@ design: (work@tnoc_vc_splitter) |vpiLhs: \_int_var: (work@tnoc_vc_splitter.tnoc_clog2.i), line:70:14, endln:70:15 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiTypespec: \_ref_typespec: (work@tnoc_vc_splitter.tnoc_clog2.i) |vpiParent: @@ -21282,7 +21280,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiParent: \_operation: , line:86:9, endln:86:34 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:86:9, endln:86:22 |vpiParent: @@ -21298,6 +21295,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_id_x_width.size_x |vpiActual: \_typespec_member: (size_x), line:45:15, endln:45:21 + |vpiName:packet_config.size_x |vpiOperand: \_constant: , line:86:33, endln:86:34 |vpiStmt: @@ -21317,7 +21315,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiParent: \_func_call: (tnoc_clog2), line:87:14, endln:87:46 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:87:25, endln:87:38 |vpiParent: @@ -21333,6 +21330,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_id_x_width.size_x |vpiActual: \_typespec_member: (size_x), line:45:15, endln:45:21 + |vpiName:packet_config.size_x |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -21385,7 +21383,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiParent: \_operation: , line:95:9, endln:95:34 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:95:9, endln:95:22 |vpiParent: @@ -21401,6 +21398,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_id_y_width.size_y |vpiActual: \_typespec_member: (size_y), line:46:15, endln:46:21 + |vpiName:packet_config.size_y |vpiOperand: \_constant: , line:95:33, endln:95:34 |vpiStmt: @@ -21420,7 +21418,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiParent: \_func_call: (tnoc_clog2), line:96:14, endln:96:46 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:96:25, endln:96:38 |vpiParent: @@ -21436,6 +21433,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_id_y_width.size_y |vpiActual: \_typespec_member: (size_y), line:46:15, endln:46:21 + |vpiName:packet_config.size_y |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -21566,7 +21564,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiParent: \_operation: , line:108:9, endln:108:44 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:108:9, endln:108:22 |vpiParent: @@ -21582,6 +21579,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_vc_width.virtual_channels |vpiActual: \_typespec_member: (virtual_channels), line:47:15, endln:47:31 + |vpiName:packet_config.virtual_channels |vpiOperand: \_constant: , line:108:43, endln:108:44 |vpiStmt: @@ -21601,7 +21599,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiParent: \_func_call: (tnoc_clog2), line:109:14, endln:109:56 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:109:25, endln:109:38 |vpiParent: @@ -21617,6 +21614,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_vc_width.virtual_channels |vpiActual: \_typespec_member: (virtual_channels), line:47:15, endln:47:31 + |vpiName:packet_config.virtual_channels |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -21669,7 +21667,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiParent: \_operation: , line:117:9, endln:117:32 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:117:9, endln:117:22 |vpiParent: @@ -21685,6 +21682,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_tag_width.tags |vpiActual: \_typespec_member: (tags), line:48:15, endln:48:19 + |vpiName:packet_config.tags |vpiOperand: \_constant: , line:117:31, endln:117:32 |vpiStmt: @@ -21704,7 +21702,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiParent: \_func_call: (tnoc_clog2), line:118:14, endln:118:44 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:118:25, endln:118:38 |vpiParent: @@ -21720,6 +21717,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_tag_width.tags |vpiActual: \_typespec_member: (tags), line:48:15, endln:48:19 + |vpiName:packet_config.tags |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -21772,7 +21770,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiParent: \_operation: , line:126:9, endln:126:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:126:9, endln:126:22 |vpiParent: @@ -21788,6 +21785,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_size_width.max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:126:41, endln:126:43 |vpiStmt: @@ -21828,7 +21826,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiParent: \_operation: , line:127:36, endln:127:68 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:127:36, endln:127:49 |vpiParent: @@ -21844,6 +21841,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_size_width.max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:127:67, endln:127:68 |vpiName:tnoc_clog2 @@ -21914,7 +21912,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiParent: \_operation: , line:135:23, endln:135:56 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:135:23, endln:135:36 |vpiParent: @@ -21930,6 +21927,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_length_width.max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:135:55, endln:135:56 |vpiName:tnoc_clog2 @@ -21973,7 +21971,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiParent: \_operation: , line:139:9, endln:139:43 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:139:9, endln:139:22 |vpiParent: @@ -21989,6 +21986,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_packed_byte_length_width.max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:139:42, endln:139:43 |vpiStmt: @@ -22008,7 +22006,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiParent: \_func_call: (tnoc_clog2), line:140:14, endln:140:55 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:140:25, endln:140:38 |vpiParent: @@ -22024,6 +22021,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_packed_byte_length_width.max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -22076,7 +22074,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiParent: \_operation: , line:148:9, endln:148:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:148:9, endln:148:22 |vpiParent: @@ -22092,6 +22089,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_offset_width.max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:148:41, endln:148:43 |vpiStmt: @@ -22116,7 +22114,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiParent: \_operation: , line:149:25, endln:149:57 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:149:25, endln:149:38 |vpiParent: @@ -22132,6 +22129,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_offset_width.max_data_width |vpiActual: \_typespec_member: (max_data_width), line:51:15, endln:51:29 + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:149:56, endln:149:57 |vpiName:tnoc_clog2 @@ -22186,7 +22184,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiParent: \_operation: , line:157:9, endln:157:39 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:157:9, endln:157:22 |vpiParent: @@ -22202,6 +22199,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_end_width.data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:157:37, endln:157:39 |vpiStmt: @@ -22226,7 +22224,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiParent: \_operation: , line:158:25, endln:158:53 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:158:25, endln:158:38 |vpiParent: @@ -22242,6 +22239,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_byte_end_width.data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:158:52, endln:158:53 |vpiName:tnoc_clog2 @@ -22331,7 +22329,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiParent: \_operation: , line:167:19, endln:167:47 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:167:19, endln:167:32 |vpiParent: @@ -22347,6 +22344,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_burst_length_width.data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:167:46, endln:167:47 |vpiLhs: @@ -22386,7 +22384,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiParent: \_operation: , line:168:24, endln:168:66 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:168:24, endln:168:37 |vpiParent: @@ -22402,6 +22399,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_burst_length_width.max_byte_length |vpiActual: \_typespec_member: (max_byte_length), line:52:15, endln:52:30 + |vpiName:packet_config.max_byte_length |vpiOperand: \_ref_obj: (work@tnoc_vc_splitter.get_burst_length_width.byte_width), line:168:56, endln:168:66 |vpiParent: @@ -23279,7 +23277,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiParent: \_assignment: , line:245:5, endln:245:41 - |vpiName:packet_config.address_width |vpiActual: \_ref_obj: (packet_config), line:245:14, endln:245:27 |vpiParent: @@ -23295,6 +23292,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_request_header_width.address_width |vpiActual: \_typespec_member: (address_width), line:49:15, endln:49:28 + |vpiName:packet_config.address_width |vpiLhs: \_ref_obj: (work@tnoc_vc_splitter.get_request_header_width.width), line:245:5, endln:245:10 |vpiParent: @@ -23822,7 +23820,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiParent: \_assignment: , line:277:5, endln:277:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:277:14, endln:277:27 |vpiParent: @@ -23838,6 +23835,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_request_payload_width.data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (work@tnoc_vc_splitter.get_request_payload_width.width), line:277:5, endln:277:10 |vpiParent: @@ -23861,7 +23859,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiParent: \_operation: , line:278:14, endln:278:42 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:278:14, endln:278:27 |vpiParent: @@ -23877,6 +23874,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_request_payload_width.data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:278:41, endln:278:42 |vpiLhs: @@ -23983,7 +23981,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiParent: \_assignment: , line:285:5, endln:285:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:285:14, endln:285:27 |vpiParent: @@ -23999,6 +23996,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.get_response_payload_width.data_width |vpiActual: \_typespec_member: (data_width), line:50:15, endln:50:25 + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (work@tnoc_vc_splitter.get_response_payload_width.width), line:285:5, endln:285:10 |vpiParent: @@ -25741,7 +25739,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.valid[i]), line:417:33, endln:417:53 |vpiParent: \_assignment: , line:417:7, endln:417:53 - |vpiName:receiver_if.valid[i] |vpiActual: \_ref_obj: (receiver_if), line:417:33, endln:417:44 |vpiParent: @@ -25763,11 +25760,11 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[0].receiver_if.valid[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[0].i), line:415:0 + |vpiName:receiver_if.valid[i] |vpiLhs: \_hier_path: (sender_if[i].valid), line:417:7, endln:417:16 |vpiParent: \_assignment: , line:417:7, endln:417:53 - |vpiName:sender_if[i].valid |vpiActual: \_bit_select: (sender_if[i]), line:417:7, endln:417:16 |vpiParent: @@ -25790,6 +25787,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].valid), line:417:7, endln:417:16 |vpiName:valid |vpiFullName:sender_if[i].valid + |vpiName:sender_if[i].valid |vpiStmt: \_assignment: , line:418:7, endln:418:51 |vpiParent: @@ -25800,7 +25798,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].ready), line:418:33, endln:418:51 |vpiParent: \_assignment: , line:418:7, endln:418:51 - |vpiName:sender_if[i].ready |vpiActual: \_bit_select: (sender_if[i]), line:418:33, endln:418:42 |vpiParent: @@ -25823,11 +25820,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].ready), line:418:33, endln:418:51 |vpiName:ready |vpiFullName:work@tnoc_vc_splitter.g[0].ready + |vpiName:sender_if[i].ready |vpiLhs: \_hier_path: (receiver_if.ready[i]), line:418:7, endln:418:27 |vpiParent: \_assignment: , line:418:7, endln:418:51 - |vpiName:receiver_if.ready[i] |vpiActual: \_ref_obj: (receiver_if), line:418:19, endln:418:24 |vpiParent: @@ -25849,6 +25846,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[0].receiver_if.ready[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[0].i), line:415:0 + |vpiName:receiver_if.ready[i] |vpiStmt: \_assignment: , line:419:7, endln:419:54 |vpiParent: @@ -25859,7 +25857,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].vc_ready), line:419:33, endln:419:54 |vpiParent: \_assignment: , line:419:7, endln:419:54 - |vpiName:sender_if[i].vc_ready |vpiActual: \_bit_select: (sender_if[i]), line:419:33, endln:419:42 |vpiParent: @@ -25882,11 +25879,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].vc_ready), line:419:33, endln:419:54 |vpiName:vc_ready |vpiFullName:work@tnoc_vc_splitter.g[0].vc_ready + |vpiName:sender_if[i].vc_ready |vpiLhs: \_hier_path: (receiver_if.vc_ready[i]), line:419:7, endln:419:30 |vpiParent: \_assignment: , line:419:7, endln:419:54 - |vpiName:receiver_if.vc_ready[i] |vpiActual: \_ref_obj: (receiver_if), line:419:19, endln:419:27 |vpiParent: @@ -25908,6 +25905,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[0].receiver_if.vc_ready[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[0].i), line:415:0 + |vpiName:receiver_if.vc_ready[i] |vpiAlwaysType:2 |vpiGenScopeArray: \_gen_scope_array: (work@tnoc_vc_splitter.g[0].g), line:422:35, endln:426:8 @@ -25939,7 +25937,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.flit[i]), line:424:29, endln:424:48 |vpiParent: \_assignment: , line:424:9, endln:424:48 - |vpiName:receiver_if.flit[i] |vpiActual: \_ref_obj: (receiver_if), line:424:29, endln:424:40 |vpiParent: @@ -25961,11 +25958,11 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[0].g.receiver_if.flit[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[0].i), line:415:0 + |vpiName:receiver_if.flit[i] |vpiLhs: \_hier_path: (sender_if[i].flit), line:424:9, endln:424:18 |vpiParent: \_assignment: , line:424:9, endln:424:48 - |vpiName:sender_if[i].flit |vpiActual: \_bit_select: (sender_if[i]), line:424:9, endln:424:18 |vpiParent: @@ -25988,6 +25985,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].flit), line:424:9, endln:424:18 |vpiName:flit |vpiFullName:sender_if[i].flit + |vpiName:sender_if[i].flit |vpiAlwaysType:2 |vpiGenScopeArray: \_gen_scope_array: (work@tnoc_vc_splitter.g[1]), line:415:39, endln:432:6 @@ -26034,7 +26032,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.valid[i]), line:417:33, endln:417:53 |vpiParent: \_assignment: , line:417:7, endln:417:53 - |vpiName:receiver_if.valid[i] |vpiActual: \_ref_obj: (receiver_if), line:417:33, endln:417:44 |vpiParent: @@ -26056,11 +26053,11 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[1].receiver_if.valid[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[1].i), line:415:0 + |vpiName:receiver_if.valid[i] |vpiLhs: \_hier_path: (sender_if[i].valid), line:417:7, endln:417:16 |vpiParent: \_assignment: , line:417:7, endln:417:53 - |vpiName:sender_if[i].valid |vpiActual: \_bit_select: (sender_if[i]), line:417:7, endln:417:16 |vpiParent: @@ -26083,6 +26080,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].valid), line:417:7, endln:417:16 |vpiName:valid |vpiFullName:sender_if[i].valid + |vpiName:sender_if[i].valid |vpiStmt: \_assignment: , line:418:7, endln:418:51 |vpiParent: @@ -26093,7 +26091,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].ready), line:418:33, endln:418:51 |vpiParent: \_assignment: , line:418:7, endln:418:51 - |vpiName:sender_if[i].ready |vpiActual: \_bit_select: (sender_if[i]), line:418:33, endln:418:42 |vpiParent: @@ -26116,11 +26113,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].ready), line:418:33, endln:418:51 |vpiName:ready |vpiFullName:work@tnoc_vc_splitter.g[1].ready + |vpiName:sender_if[i].ready |vpiLhs: \_hier_path: (receiver_if.ready[i]), line:418:7, endln:418:27 |vpiParent: \_assignment: , line:418:7, endln:418:51 - |vpiName:receiver_if.ready[i] |vpiActual: \_ref_obj: (receiver_if), line:418:19, endln:418:24 |vpiParent: @@ -26142,6 +26139,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[1].receiver_if.ready[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[1].i), line:415:0 + |vpiName:receiver_if.ready[i] |vpiStmt: \_assignment: , line:419:7, endln:419:54 |vpiParent: @@ -26152,7 +26150,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].vc_ready), line:419:33, endln:419:54 |vpiParent: \_assignment: , line:419:7, endln:419:54 - |vpiName:sender_if[i].vc_ready |vpiActual: \_bit_select: (sender_if[i]), line:419:33, endln:419:42 |vpiParent: @@ -26175,11 +26172,11 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].vc_ready), line:419:33, endln:419:54 |vpiName:vc_ready |vpiFullName:work@tnoc_vc_splitter.g[1].vc_ready + |vpiName:sender_if[i].vc_ready |vpiLhs: \_hier_path: (receiver_if.vc_ready[i]), line:419:7, endln:419:30 |vpiParent: \_assignment: , line:419:7, endln:419:54 - |vpiName:receiver_if.vc_ready[i] |vpiActual: \_ref_obj: (receiver_if), line:419:19, endln:419:27 |vpiParent: @@ -26201,6 +26198,7 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[1].receiver_if.vc_ready[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[1].i), line:415:0 + |vpiName:receiver_if.vc_ready[i] |vpiAlwaysType:2 |vpiGenScopeArray: \_gen_scope_array: (work@tnoc_vc_splitter.g[1].g), line:422:35, endln:426:8 @@ -26232,7 +26230,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (receiver_if.flit[i]), line:424:29, endln:424:48 |vpiParent: \_assignment: , line:424:9, endln:424:48 - |vpiName:receiver_if.flit[i] |vpiActual: \_ref_obj: (receiver_if), line:424:29, endln:424:40 |vpiParent: @@ -26254,11 +26251,11 @@ design: (work@tnoc_vc_splitter) |vpiFullName:work@tnoc_vc_splitter.g[1].g.receiver_if.flit[i].i |vpiActual: \_parameter: (work@tnoc_vc_splitter.g[1].i), line:415:0 + |vpiName:receiver_if.flit[i] |vpiLhs: \_hier_path: (sender_if[i].flit), line:424:9, endln:424:18 |vpiParent: \_assignment: , line:424:9, endln:424:48 - |vpiName:sender_if[i].flit |vpiActual: \_bit_select: (sender_if[i]), line:424:9, endln:424:18 |vpiParent: @@ -26281,6 +26278,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (sender_if[i].flit), line:424:9, endln:424:18 |vpiName:flit |vpiFullName:sender_if[i].flit + |vpiName:sender_if[i].flit |vpiAlwaysType:2 \_weaklyReferenced: \_short_int_typespec: , line:45:5, endln:45:13 @@ -26775,7 +26773,7 @@ design: (work@tnoc_vc_splitter) \_begin: (tnoc_pkg::tnoc_clog2), line:69:5, endln:69:17 |vpiFullName:tnoc_pkg::tnoc_clog2 |vpiForInitStmt: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiParent: \_for_stmt: (tnoc_pkg::tnoc_clog2), line:70:5, endln:70:8 |vpiRhs: @@ -26783,7 +26781,7 @@ design: (work@tnoc_vc_splitter) |vpiLhs: \_int_var: (tnoc_pkg::tnoc_clog2::i), line:70:14, endln:70:15 |vpiParent: - \_assign_stmt: , line:70:10, endln:70:20 + \_assignment: , line:70:10, endln:70:20 |vpiTypespec: \_ref_typespec: (tnoc_pkg::tnoc_clog2::i) |vpiParent: @@ -26988,7 +26986,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiParent: \_operation: , line:86:9, endln:86:34 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:86:9, endln:86:22 |vpiParent: @@ -27002,6 +26999,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:86:9, endln:86:29 |vpiName:size_x |vpiFullName:tnoc_pkg::get_id_x_width::size_x + |vpiName:packet_config.size_x |vpiOperand: \_constant: , line:86:33, endln:86:34 |vpiStmt: @@ -27021,7 +27019,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiParent: \_func_call: (tnoc_clog2), line:87:14, endln:87:46 - |vpiName:packet_config.size_x |vpiActual: \_ref_obj: (packet_config), line:87:25, endln:87:38 |vpiParent: @@ -27035,6 +27032,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_x), line:87:25, endln:87:45 |vpiName:size_x |vpiFullName:tnoc_pkg::get_id_x_width::size_x + |vpiName:packet_config.size_x |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -27086,7 +27084,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiParent: \_operation: , line:95:9, endln:95:34 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:95:9, endln:95:22 |vpiParent: @@ -27100,6 +27097,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:95:9, endln:95:29 |vpiName:size_y |vpiFullName:tnoc_pkg::get_id_y_width::size_y + |vpiName:packet_config.size_y |vpiOperand: \_constant: , line:95:33, endln:95:34 |vpiStmt: @@ -27119,7 +27117,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiParent: \_func_call: (tnoc_clog2), line:96:14, endln:96:46 - |vpiName:packet_config.size_y |vpiActual: \_ref_obj: (packet_config), line:96:25, endln:96:38 |vpiParent: @@ -27133,6 +27130,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.size_y), line:96:25, endln:96:45 |vpiName:size_y |vpiFullName:tnoc_pkg::get_id_y_width::size_y + |vpiName:packet_config.size_y |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -27247,7 +27245,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiParent: \_operation: , line:108:9, endln:108:44 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:108:9, endln:108:22 |vpiParent: @@ -27261,6 +27258,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:108:9, endln:108:39 |vpiName:virtual_channels |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels + |vpiName:packet_config.virtual_channels |vpiOperand: \_constant: , line:108:43, endln:108:44 |vpiStmt: @@ -27280,7 +27278,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiParent: \_func_call: (tnoc_clog2), line:109:14, endln:109:56 - |vpiName:packet_config.virtual_channels |vpiActual: \_ref_obj: (packet_config), line:109:25, endln:109:38 |vpiParent: @@ -27294,6 +27291,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.virtual_channels), line:109:25, endln:109:55 |vpiName:virtual_channels |vpiFullName:tnoc_pkg::get_vc_width::virtual_channels + |vpiName:packet_config.virtual_channels |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -27345,7 +27343,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiParent: \_operation: , line:117:9, endln:117:32 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:117:9, endln:117:22 |vpiParent: @@ -27359,6 +27356,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:117:9, endln:117:27 |vpiName:tags |vpiFullName:tnoc_pkg::get_tag_width::tags + |vpiName:packet_config.tags |vpiOperand: \_constant: , line:117:31, endln:117:32 |vpiStmt: @@ -27378,7 +27376,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiParent: \_func_call: (tnoc_clog2), line:118:14, endln:118:44 - |vpiName:packet_config.tags |vpiActual: \_ref_obj: (packet_config), line:118:25, endln:118:38 |vpiParent: @@ -27392,6 +27389,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.tags), line:118:25, endln:118:43 |vpiName:tags |vpiFullName:tnoc_pkg::get_tag_width::tags + |vpiName:packet_config.tags |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -27443,7 +27441,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiParent: \_operation: , line:126:9, endln:126:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:126:9, endln:126:22 |vpiParent: @@ -27457,6 +27454,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:126:9, endln:126:37 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:126:41, endln:126:43 |vpiStmt: @@ -27490,7 +27488,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiParent: \_operation: , line:127:36, endln:127:68 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:127:36, endln:127:49 |vpiParent: @@ -27504,6 +27501,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:127:36, endln:127:64 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_size_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:127:67, endln:127:68 |vpiName:tnoc_clog2 @@ -27566,7 +27564,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiParent: \_operation: , line:135:23, endln:135:56 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:135:23, endln:135:36 |vpiParent: @@ -27580,6 +27577,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:135:23, endln:135:52 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_byte_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:135:55, endln:135:56 |vpiName:tnoc_clog2 @@ -27622,7 +27620,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiParent: \_operation: , line:139:9, endln:139:43 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:139:9, endln:139:22 |vpiParent: @@ -27636,6 +27633,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:139:9, endln:139:38 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiOperand: \_constant: , line:139:42, endln:139:43 |vpiStmt: @@ -27655,7 +27653,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiParent: \_func_call: (tnoc_clog2), line:140:14, endln:140:55 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:140:25, endln:140:38 |vpiParent: @@ -27669,6 +27666,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:140:25, endln:140:54 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_packed_byte_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiName:tnoc_clog2 |vpiFunction: \_function: (tnoc_pkg::tnoc_clog2), line:66:3, endln:83:14 @@ -27720,7 +27718,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiParent: \_operation: , line:148:9, endln:148:43 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:148:9, endln:148:22 |vpiParent: @@ -27734,6 +27731,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:148:9, endln:148:37 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:148:41, endln:148:43 |vpiStmt: @@ -27758,7 +27756,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiParent: \_operation: , line:149:25, endln:149:57 - |vpiName:packet_config.max_data_width |vpiActual: \_ref_obj: (packet_config), line:149:25, endln:149:38 |vpiParent: @@ -27772,6 +27769,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_data_width), line:149:25, endln:149:53 |vpiName:max_data_width |vpiFullName:tnoc_pkg::get_byte_offset_width::max_data_width + |vpiName:packet_config.max_data_width |vpiOperand: \_constant: , line:149:56, endln:149:57 |vpiName:tnoc_clog2 @@ -27825,7 +27823,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiParent: \_operation: , line:157:9, endln:157:39 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:157:9, endln:157:22 |vpiParent: @@ -27839,6 +27836,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:157:9, endln:157:33 |vpiName:data_width |vpiFullName:tnoc_pkg::get_byte_end_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:157:37, endln:157:39 |vpiStmt: @@ -27863,7 +27861,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiParent: \_operation: , line:158:25, endln:158:53 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:158:25, endln:158:38 |vpiParent: @@ -27877,6 +27874,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:158:25, endln:158:49 |vpiName:data_width |vpiFullName:tnoc_pkg::get_byte_end_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:158:52, endln:158:53 |vpiName:tnoc_clog2 @@ -27953,7 +27951,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiParent: \_operation: , line:167:19, endln:167:47 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:167:19, endln:167:32 |vpiParent: @@ -27967,6 +27964,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:167:19, endln:167:43 |vpiName:data_width |vpiFullName:tnoc_pkg::get_burst_length_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:167:46, endln:167:47 |vpiLhs: @@ -27999,7 +27997,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiParent: \_operation: , line:168:24, endln:168:66 - |vpiName:packet_config.max_byte_length |vpiActual: \_ref_obj: (packet_config), line:168:24, endln:168:37 |vpiParent: @@ -28013,6 +28010,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.max_byte_length), line:168:24, endln:168:53 |vpiName:max_byte_length |vpiFullName:tnoc_pkg::get_burst_length_width::max_byte_length + |vpiName:packet_config.max_byte_length |vpiOperand: \_ref_obj: (tnoc_pkg::get_burst_length_width::byte_width), line:168:56, endln:168:66 |vpiParent: @@ -28862,7 +28860,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiParent: \_assignment: , line:245:5, endln:245:41 - |vpiName:packet_config.address_width |vpiActual: \_ref_obj: (packet_config), line:245:14, endln:245:27 |vpiParent: @@ -28876,6 +28873,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.address_width), line:245:14, endln:245:41 |vpiName:address_width |vpiFullName:tnoc_pkg::get_request_header_width::address_width + |vpiName:packet_config.address_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_header_width::width), line:245:5, endln:245:10 |vpiParent: @@ -29382,7 +29380,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiParent: \_assignment: , line:277:5, endln:277:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:277:14, endln:277:27 |vpiParent: @@ -29396,6 +29393,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:277:14, endln:277:38 |vpiName:data_width |vpiFullName:tnoc_pkg::get_request_payload_width::data_width + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_request_payload_width::width), line:277:5, endln:277:10 |vpiParent: @@ -29419,7 +29417,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiParent: \_operation: , line:278:14, endln:278:42 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:278:14, endln:278:27 |vpiParent: @@ -29433,6 +29430,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:278:14, endln:278:38 |vpiName:data_width |vpiFullName:tnoc_pkg::get_request_payload_width::data_width + |vpiName:packet_config.data_width |vpiOperand: \_constant: , line:278:41, endln:278:42 |vpiLhs: @@ -29526,7 +29524,6 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiParent: \_assignment: , line:285:5, endln:285:38 - |vpiName:packet_config.data_width |vpiActual: \_ref_obj: (packet_config), line:285:14, endln:285:27 |vpiParent: @@ -29540,6 +29537,7 @@ design: (work@tnoc_vc_splitter) \_hier_path: (packet_config.data_width), line:285:14, endln:285:38 |vpiName:data_width |vpiFullName:tnoc_pkg::get_response_payload_width::data_width + |vpiName:packet_config.data_width |vpiLhs: \_ref_obj: (tnoc_pkg::get_response_payload_width::width), line:285:5, endln:285:10 |vpiParent: diff --git a/tests/FuncInModule/FuncInModule.log b/tests/FuncInModule/FuncInModule.log index e2c98cc680..97c3042df9 100644 --- a/tests/FuncInModule/FuncInModule.log +++ b/tests/FuncInModule/FuncInModule.log @@ -1008,8 +1008,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 8 -assignment 13 +assignment 21 begin 11 bit_select 9 bit_typespec 12 @@ -1039,8 +1038,7 @@ while_stmt 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 10 -assignment 26 +assignment 36 begin 22 bit_select 18 bit_typespec 12 @@ -1794,13 +1792,13 @@ design: (work@rggen_or_reducer) \_begin: (work@rggen_or_reducer.get_offset_list), line:42:5, endln:49:8 |vpiFullName:work@rggen_or_reducer.get_offset_list |vpiForInitStmt: - \_assign_stmt: , line:42:10, endln:42:19 + \_assignment: , line:42:10, endln:42:19 |vpiParent: \_for_stmt: (work@rggen_or_reducer.get_offset_list), line:42:5, endln:42:8 |vpiRhs: \_constant: , line:42:18, endln:42:19 |vpiParent: - \_assign_stmt: , line:42:10, endln:42:19 + \_assignment: , line:42:10, endln:42:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1808,7 +1806,7 @@ design: (work@rggen_or_reducer) |vpiLhs: \_int_var: (work@rggen_or_reducer.get_offset_list.i), line:42:14, endln:42:15 |vpiParent: - \_assign_stmt: , line:42:10, endln:42:19 + \_assignment: , line:42:10, endln:42:19 |vpiTypespec: \_ref_typespec: (work@rggen_or_reducer.get_offset_list.i) |vpiParent: @@ -2099,13 +2097,13 @@ design: (work@rggen_or_reducer) \_begin: (work@rggen_or_reducer.get_next_n), line:57:5, endln:57:17 |vpiFullName:work@rggen_or_reducer.get_next_n |vpiForInitStmt: - \_assign_stmt: , line:58:10, endln:58:19 + \_assignment: , line:58:10, endln:58:19 |vpiParent: \_for_stmt: (work@rggen_or_reducer.get_next_n), line:58:5, endln:58:8 |vpiRhs: \_constant: , line:58:18, endln:58:19 |vpiParent: - \_assign_stmt: , line:58:10, endln:58:19 + \_assignment: , line:58:10, endln:58:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2113,7 +2111,7 @@ design: (work@rggen_or_reducer) |vpiLhs: \_int_var: (work@rggen_or_reducer.get_next_n.i), line:58:14, endln:58:15 |vpiParent: - \_assign_stmt: , line:58:10, endln:58:19 + \_assignment: , line:58:10, endln:58:19 |vpiTypespec: \_ref_typespec: (work@rggen_or_reducer.get_next_n.i) |vpiParent: @@ -2987,7 +2985,7 @@ design: (work@rggen_or_reducer) \_begin: (work@rggen_or_reducer.get_offset_list), line:42:5, endln:49:8 |vpiFullName:work@rggen_or_reducer.get_offset_list |vpiForInitStmt: - \_assign_stmt: , line:42:10, endln:42:19 + \_assignment: , line:42:10, endln:42:19 |vpiParent: \_for_stmt: (work@rggen_or_reducer.get_offset_list), line:42:5, endln:42:8 |vpiRhs: @@ -2995,7 +2993,7 @@ design: (work@rggen_or_reducer) |vpiLhs: \_int_var: (work@rggen_or_reducer.get_offset_list.i), line:42:14, endln:42:15 |vpiParent: - \_assign_stmt: , line:42:10, endln:42:19 + \_assignment: , line:42:10, endln:42:19 |vpiTypespec: \_ref_typespec: (work@rggen_or_reducer.get_offset_list.i) |vpiParent: @@ -3263,7 +3261,7 @@ design: (work@rggen_or_reducer) \_begin: (work@rggen_or_reducer.get_next_n), line:57:5, endln:57:17 |vpiFullName:work@rggen_or_reducer.get_next_n |vpiForInitStmt: - \_assign_stmt: , line:58:10, endln:58:19 + \_assignment: , line:58:10, endln:58:19 |vpiParent: \_for_stmt: (work@rggen_or_reducer.get_next_n), line:58:5, endln:58:8 |vpiRhs: @@ -3271,7 +3269,7 @@ design: (work@rggen_or_reducer) |vpiLhs: \_int_var: (work@rggen_or_reducer.get_next_n.i), line:58:14, endln:58:15 |vpiParent: - \_assign_stmt: , line:58:10, endln:58:19 + \_assignment: , line:58:10, endln:58:19 |vpiTypespec: \_ref_typespec: (work@rggen_or_reducer.get_next_n.i) |vpiParent: diff --git a/tests/FuncNoArgs/FuncNoArgs.log b/tests/FuncNoArgs/FuncNoArgs.log index b05f4d2ac3..1aaf45451c 100644 --- a/tests/FuncNoArgs/FuncNoArgs.log +++ b/tests/FuncNoArgs/FuncNoArgs.log @@ -523,8 +523,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 3 +assignment 4 begin 1 bit_select 1 class_defn 8 @@ -560,8 +559,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 6 +assignment 8 begin 2 bit_select 2 class_defn 8 @@ -1264,13 +1262,13 @@ design: (work@my_opt_reduce_or) \_begin: (work@my_opt_reduce_or.count_nonconst_bits), line:9:9, endln:14:12 |vpiFullName:work@my_opt_reduce_or.count_nonconst_bits |vpiForInitStmt: - \_assign_stmt: , line:11:18, endln:11:23 + \_assignment: , line:11:18, endln:11:23 |vpiParent: \_for_stmt: (work@my_opt_reduce_or.count_nonconst_bits), line:11:13, endln:11:16 |vpiRhs: \_constant: , line:11:22, endln:11:23 |vpiParent: - \_assign_stmt: , line:11:18, endln:11:23 + \_assignment: , line:11:18, endln:11:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1278,7 +1276,7 @@ design: (work@my_opt_reduce_or) |vpiLhs: \_ref_var: (work@my_opt_reduce_or.count_nonconst_bits.i), line:11:18, endln:11:19 |vpiParent: - \_assign_stmt: , line:11:18, endln:11:23 + \_assignment: , line:11:18, endln:11:23 |vpiName:i |vpiFullName:work@my_opt_reduce_or.count_nonconst_bits.i |vpiForIncStmt: @@ -1561,7 +1559,7 @@ design: (work@my_opt_reduce_or) \_begin: (work@my_opt_reduce_or.count_nonconst_bits), line:9:9, endln:14:12 |vpiFullName:work@my_opt_reduce_or.count_nonconst_bits |vpiForInitStmt: - \_assign_stmt: , line:11:18, endln:11:23 + \_assignment: , line:11:18, endln:11:23 |vpiParent: \_for_stmt: (work@my_opt_reduce_or.count_nonconst_bits), line:11:13, endln:11:16 |vpiRhs: @@ -1569,7 +1567,7 @@ design: (work@my_opt_reduce_or) |vpiLhs: \_ref_var: (work@my_opt_reduce_or.count_nonconst_bits.i), line:11:18, endln:11:19 |vpiParent: - \_assign_stmt: , line:11:18, endln:11:23 + \_assignment: , line:11:18, endln:11:23 |vpiName:i |vpiFullName:work@my_opt_reduce_or.count_nonconst_bits.i |vpiActual: diff --git a/tests/FuncParam/FuncParam.log b/tests/FuncParam/FuncParam.log index 77bdc28dcf..1d6ef322e6 100644 --- a/tests/FuncParam/FuncParam.log +++ b/tests/FuncParam/FuncParam.log @@ -18,7 +18,7 @@ [NTE:EL0511] Nb leaf instances: 2. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 class_defn 8 class_typespec 4 @@ -48,7 +48,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 begin 3 class_defn 8 class_typespec 4 diff --git a/tests/FuncRetArray/FuncRetArray.log b/tests/FuncRetArray/FuncRetArray.log index 7323a3eeec..a8db002e29 100644 --- a/tests/FuncRetArray/FuncRetArray.log +++ b/tests/FuncRetArray/FuncRetArray.log @@ -321,8 +321,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 5 array_var 1 -assign_stmt 1 -assignment 1 +assignment 2 begin 4 bit_select 7 constant 64 @@ -350,8 +349,7 @@ sys_task_call 1 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 5 array_var 1 -assign_stmt 2 -assignment 2 +assignment 4 begin 5 bit_select 8 constant 64 @@ -530,13 +528,13 @@ design: (work@main) \_function: (work@top.ASSIGN_VADDR), line:3:5, endln:7:16 |vpiFullName:work@top.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:4:14, endln:4:23 + \_assignment: , line:4:14, endln:4:23 |vpiParent: \_for_stmt: (work@top.ASSIGN_VADDR), line:4:9, endln:4:12 |vpiRhs: \_constant: , line:4:22, endln:4:23 |vpiParent: - \_assign_stmt: , line:4:14, endln:4:23 + \_assignment: , line:4:14, endln:4:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -544,7 +542,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@top.ASSIGN_VADDR.i), line:4:18, endln:4:19 |vpiParent: - \_assign_stmt: , line:4:14, endln:4:23 + \_assignment: , line:4:14, endln:4:23 |vpiTypespec: \_ref_typespec: (work@top.ASSIGN_VADDR.i) |vpiParent: @@ -824,7 +822,7 @@ design: (work@main) \_function: (work@main.top1.ASSIGN_VADDR), line:3:5, endln:7:16 |vpiFullName:work@main.top1.ASSIGN_VADDR |vpiForInitStmt: - \_assign_stmt: , line:4:14, endln:4:23 + \_assignment: , line:4:14, endln:4:23 |vpiParent: \_for_stmt: (work@main.top1.ASSIGN_VADDR), line:4:9, endln:4:12 |vpiRhs: @@ -832,7 +830,7 @@ design: (work@main) |vpiLhs: \_int_var: (work@main.top1.ASSIGN_VADDR.i), line:4:18, endln:4:19 |vpiParent: - \_assign_stmt: , line:4:14, endln:4:23 + \_assignment: , line:4:14, endln:4:23 |vpiTypespec: \_ref_typespec: (work@main.top1.ASSIGN_VADDR.i) |vpiParent: @@ -1046,5 +1044,5 @@ design: (work@main) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/FuncRetArray/dut.sv | ${SURELOG_DIR}/build/regression/FuncRetArray/roundtrip/dut_000.sv | 13 | 24 | +[roundtrip]: ${SURELOG_DIR}/tests/FuncRetArray/dut.sv | ${SURELOG_DIR}/build/regression/FuncRetArray/roundtrip/dut_000.sv | 14 | 24 | ============================== End RoundTrip Results ============================== diff --git a/tests/FuncStatic/FuncStatic.log b/tests/FuncStatic/FuncStatic.log index dd4c58a876..44dbbd374d 100644 --- a/tests/FuncStatic/FuncStatic.log +++ b/tests/FuncStatic/FuncStatic.log @@ -243,8 +243,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 2 constant 18 design 1 @@ -266,8 +265,7 @@ return_stmt 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 -assignment 4 +assignment 8 begin 4 constant 18 design 1 @@ -422,7 +420,7 @@ design: (work@test) |vpiVariables: \_int_var: (work@test.accumulate1.acc), line:4:14, endln:4:17 |vpiParent: - \_assign_stmt: , line:4:14, endln:4:21 + \_assignment: , line:4:14, endln:4:21 |vpiTypespec: \_ref_typespec: (work@test.accumulate1.acc) |vpiParent: @@ -468,9 +466,11 @@ design: (work@test) |vpiVariables: \_int_var: (work@test.accumulate1.acc), line:4:14, endln:4:17 |vpiStmt: - \_assign_stmt: , line:4:14, endln:4:21 + \_assignment: , line:4:14, endln:4:21 |vpiParent: \_begin: (work@test.accumulate1), line:5:3, endln:5:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:4:20, endln:4:21 |vpiDecompile:1 @@ -537,7 +537,7 @@ design: (work@test) |vpiVariables: \_int_var: (work@test.accumulate2.acc), line:10:7, endln:10:10 |vpiParent: - \_assign_stmt: , line:10:7, endln:10:14 + \_assignment: , line:10:7, endln:10:14 |vpiTypespec: \_ref_typespec: (work@test.accumulate2.acc) |vpiParent: @@ -583,9 +583,11 @@ design: (work@test) |vpiVariables: \_int_var: (work@test.accumulate2.acc), line:10:7, endln:10:10 |vpiStmt: - \_assign_stmt: , line:10:7, endln:10:14 + \_assignment: , line:10:7, endln:10:14 |vpiParent: \_begin: (work@test.accumulate2), line:11:3, endln:11:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:10:13, endln:10:14 |vpiDecompile:1 @@ -788,15 +790,17 @@ design: (work@test) |vpiFullName:work@test.accumulate1.acc |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:4:14, endln:4:21 + \_assignment: , line:4:14, endln:4:21 |vpiParent: \_begin: (work@test.accumulate1), line:5:3, endln:5:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:4:20, endln:4:21 |vpiLhs: \_int_var: (work@test.accumulate1.acc), line:4:14, endln:4:17 |vpiParent: - \_assign_stmt: , line:4:14, endln:4:21 + \_assignment: , line:4:14, endln:4:21 |vpiTypespec: \_ref_typespec: (work@test.accumulate1.acc) |vpiParent: @@ -912,15 +916,17 @@ design: (work@test) |vpiFullName:work@test.accumulate2.acc |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:10:7, endln:10:14 + \_assignment: , line:10:7, endln:10:14 |vpiParent: \_begin: (work@test.accumulate2), line:11:3, endln:11:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:10:13, endln:10:14 |vpiLhs: \_int_var: (work@test.accumulate2.acc), line:10:7, endln:10:10 |vpiParent: - \_assign_stmt: , line:10:7, endln:10:14 + \_assignment: , line:10:7, endln:10:14 |vpiTypespec: \_ref_typespec: (work@test.accumulate2.acc) |vpiParent: diff --git a/tests/FuncStruct/FuncStruct.log b/tests/FuncStruct/FuncStruct.log index 1e4b5769ac..03dfd90bee 100644 --- a/tests/FuncStruct/FuncStruct.log +++ b/tests/FuncStruct/FuncStruct.log @@ -243,8 +243,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 -assignment 4 +assignment 6 begin 2 bit_select 6 constant 91 @@ -268,8 +267,7 @@ ref_typespec 44 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 10 +assignment 12 begin 5 bit_select 10 constant 91 diff --git a/tests/GenBlockVar/GenBlockVar.log b/tests/GenBlockVar/GenBlockVar.log index 27fa428a1c..0fe3762306 100644 --- a/tests/GenBlockVar/GenBlockVar.log +++ b/tests/GenBlockVar/GenBlockVar.log @@ -338,7 +338,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 begin 1 bit_typespec 2 class_defn 8 @@ -369,7 +369,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 +assignment 2 begin 1 bit_typespec 2 class_defn 8 @@ -952,13 +952,15 @@ design: (work@top) |vpiName:gen_no_async |vpiFullName:work@top.gen_no_async |vpiStmt: - \_assign_stmt: , line:8:11, endln:8:18 + \_assignment: , line:8:11, endln:8:18 |vpiParent: \_named_begin: (work@top.gen_no_async) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.gen_no_async.diff_pq), line:8:11, endln:8:18 |vpiParent: - \_assign_stmt: , line:8:11, endln:8:18 + \_assignment: , line:8:11, endln:8:18 |vpiTypespec: \_ref_typespec: (work@top.gen_no_async.diff_pq) |vpiParent: @@ -969,13 +971,15 @@ design: (work@top) |vpiName:diff_pq |vpiFullName:work@top.gen_no_async.diff_pq |vpiStmt: - \_assign_stmt: , line:8:20, endln:8:27 + \_assignment: , line:8:20, endln:8:27 |vpiParent: \_named_begin: (work@top.gen_no_async) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.gen_no_async.diff_pd), line:8:20, endln:8:27 |vpiParent: - \_assign_stmt: , line:8:20, endln:8:27 + \_assignment: , line:8:20, endln:8:27 |vpiTypespec: \_ref_typespec: (work@top.gen_no_async.diff_pd) |vpiParent: @@ -1336,8 +1340,3 @@ design: (work@top) [ ERROR] : 0 [WARNING] : 1 [ NOTE] : 5 - -============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/GenBlockVar/builtin.sv | ${SURELOG_DIR}/build/regression/GenBlockVar/roundtrip/builtin_000.sv | 0 | 0 | -[roundtrip]: ${SURELOG_DIR}/tests/GenBlockVar/dut.sv | ${SURELOG_DIR}/build/regression/GenBlockVar/roundtrip/dut_000.sv | 6 | 12 | -============================== End RoundTrip Results ============================== diff --git a/tests/GenFor/GenFor.log b/tests/GenFor/GenFor.log index bbb392d456..623e47c159 100644 --- a/tests/GenFor/GenFor.log +++ b/tests/GenFor/GenFor.log @@ -85,8 +85,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 bit_select 7 constant 23 @@ -108,8 +107,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 bit_select 10 constant 23 @@ -155,7 +153,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenFor/dut.sv, line:2:1, endln:8:10 |vpiForInitStmt: - \_assign_stmt: , line:4:9, endln:4:14 + \_assignment: , line:4:9, endln:4:14 |vpiParent: \_gen_for: |vpiRhs: @@ -167,7 +165,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:4:9, endln:4:10 |vpiParent: - \_assign_stmt: , line:4:9, endln:4:14 + \_assignment: , line:4:9, endln:4:14 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: diff --git a/tests/GenForDec/GenForDec.log b/tests/GenForDec/GenForDec.log index d36e3835fc..f7c12d8df9 100644 --- a/tests/GenForDec/GenForDec.log +++ b/tests/GenForDec/GenForDec.log @@ -228,8 +228,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 -assignment 2 +assignment 6 begin 4 bit_select 24 constant 80 @@ -251,8 +250,7 @@ unsupported_typespec 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 -assignment 2 +assignment 6 begin 4 bit_select 34 constant 80 @@ -298,7 +296,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenForDec/dut.sv, line:2:1, endln:20:10 |vpiForInitStmt: - \_assign_stmt: , line:4:9, endln:4:14 + \_assignment: , line:4:9, endln:4:14 |vpiParent: \_gen_for: |vpiRhs: @@ -310,7 +308,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:4:9, endln:4:10 |vpiParent: - \_assign_stmt: , line:4:9, endln:4:14 + \_assignment: , line:4:9, endln:4:14 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -388,7 +386,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenForDec/dut.sv, line:2:1, endln:20:10 |vpiForInitStmt: - \_assign_stmt: , line:8:9, endln:8:14 + \_assignment: , line:8:9, endln:8:14 |vpiParent: \_gen_for: |vpiRhs: @@ -400,7 +398,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:8:9, endln:8:10 |vpiParent: - \_assign_stmt: , line:8:9, endln:8:14 + \_assignment: , line:8:9, endln:8:14 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -478,7 +476,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenForDec/dut.sv, line:2:1, endln:20:10 |vpiForInitStmt: - \_assign_stmt: , line:12:9, endln:12:14 + \_assignment: , line:12:9, endln:12:14 |vpiParent: \_gen_for: |vpiRhs: @@ -490,7 +488,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:12:9, endln:12:10 |vpiParent: - \_assign_stmt: , line:12:9, endln:12:14 + \_assignment: , line:12:9, endln:12:14 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -574,7 +572,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenForDec/dut.sv, line:2:1, endln:20:10 |vpiForInitStmt: - \_assign_stmt: , line:16:8, endln:16:13 + \_assignment: , line:16:8, endln:16:13 |vpiParent: \_gen_for: |vpiRhs: @@ -586,7 +584,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:16:8, endln:16:9 |vpiParent: - \_assign_stmt: , line:16:8, endln:16:13 + \_assignment: , line:16:8, endln:16:13 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: diff --git a/tests/GenIfNamed/GenIfNamed.log b/tests/GenIfNamed/GenIfNamed.log index 3f14fa8d83..94dc1e9a26 100644 --- a/tests/GenIfNamed/GenIfNamed.log +++ b/tests/GenIfNamed/GenIfNamed.log @@ -146,8 +146,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 bit_select 9 constant 29 cont_assign 9 @@ -170,8 +169,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 bit_select 12 constant 29 cont_assign 12 @@ -218,7 +216,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenIfNamed/dut.sv, line:2:1, endln:13:10 |vpiForInitStmt: - \_assign_stmt: , line:4:8, endln:4:13 + \_assignment: , line:4:8, endln:4:13 |vpiParent: \_gen_for: |vpiRhs: @@ -230,7 +228,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:4:8, endln:4:9 |vpiParent: - \_assign_stmt: , line:4:8, endln:4:13 + \_assignment: , line:4:8, endln:4:13 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: diff --git a/tests/GenModHierPath/GenModHierPath.log b/tests/GenModHierPath/GenModHierPath.log index 56ed192e21..22a7fd165f 100644 --- a/tests/GenModHierPath/GenModHierPath.log +++ b/tests/GenModHierPath/GenModHierPath.log @@ -209,7 +209,6 @@ design: (work@InitializedBlockRAM) \_hier_path: (body.ram.array), line:17:15, endln:17:29 |vpiParent: \_sys_func_call: ($readmemh), line:17:5, endln:17:30 - |vpiName:body.ram.array |vpiActual: \_ref_obj: (body), line:17:15, endln:17:19 |vpiParent: @@ -226,6 +225,7 @@ design: (work@InitializedBlockRAM) \_hier_path: (body.ram.array), line:17:15, endln:17:29 |vpiName:array |vpiFullName:work@InitializedBlockRAM.InitializeMemory.array + |vpiName:body.ram.array |vpiName:$readmemh |vpiInstance: \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 @@ -283,7 +283,6 @@ design: (work@InitializedBlockRAM) \_hier_path: (body.ram.array), line:17:15, endln:17:29 |vpiParent: \_sys_func_call: ($readmemh), line:17:5, endln:17:30 - |vpiName:body.ram.array |vpiActual: \_ref_obj: (body), line:17:15, endln:17:19 |vpiParent: @@ -306,6 +305,7 @@ design: (work@InitializedBlockRAM) |vpiFullName:work@InitializedBlockRAM.InitializeMemory.array |vpiActual: \_array_var: (work@InitializedBlockRAM.body.ram.array), line:3:7, endln:3:12 + |vpiName:body.ram.array |vpiName:$readmemh |vpiInstance: \_module_inst: work@InitializedBlockRAM (work@InitializedBlockRAM), file:${SURELOG_DIR}/tests/GenModHierPath/dut.sv, line:8:1, endln:20:10 diff --git a/tests/GenNet/GenNet.log b/tests/GenNet/GenNet.log index 6bbc93c37e..a7f43489ce 100644 --- a/tests/GenNet/GenNet.log +++ b/tests/GenNet/GenNet.log @@ -256,7 +256,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 begin 1 constant 49 cont_assign 3 @@ -283,7 +283,7 @@ string_typespec 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 +assignment 2 begin 1 constant 49 cont_assign 4 @@ -488,13 +488,15 @@ design: (work@dut) |vpiName:gen_w |vpiFullName:work@prim_subreg_arb.gen_w |vpiStmt: - \_assign_stmt: , line:9:20, endln:9:31 + \_assignment: , line:9:20, endln:9:31 |vpiParent: \_named_begin: (work@prim_subreg_arb.gen_w) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@prim_subreg_arb.gen_w.unused_q_wo), line:9:20, endln:9:31 |vpiParent: - \_assign_stmt: , line:9:20, endln:9:31 + \_assignment: , line:9:20, endln:9:31 |vpiTypespec: \_ref_typespec: (work@prim_subreg_arb.gen_w.unused_q_wo) |vpiParent: @@ -555,13 +557,15 @@ design: (work@dut) |vpiName:gen_ro |vpiFullName:work@prim_subreg_arb.gen_ro |vpiStmt: - \_assign_stmt: , line:12:20, endln:12:31 + \_assignment: , line:12:20, endln:12:31 |vpiParent: \_named_begin: (work@prim_subreg_arb.gen_ro) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@prim_subreg_arb.gen_ro.unused_q_ro), line:12:20, endln:12:31 |vpiParent: - \_assign_stmt: , line:12:20, endln:12:31 + \_assignment: , line:12:20, endln:12:31 |vpiTypespec: \_ref_typespec: (work@prim_subreg_arb.gen_ro.unused_q_ro) |vpiParent: @@ -981,7 +985,3 @@ design: (work@dut) [ ERROR] : 0 [WARNING] : 2 [ NOTE] : 5 - -============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/GenNet/dut.sv | ${SURELOG_DIR}/build/regression/GenNet/roundtrip/dut_000.sv | 12 | 23 | -============================== End RoundTrip Results ============================== diff --git a/tests/GenScopeFullName/GenScopeFullName.log b/tests/GenScopeFullName/GenScopeFullName.log index 4d7637bfab..8a10afda67 100644 --- a/tests/GenScopeFullName/GenScopeFullName.log +++ b/tests/GenScopeFullName/GenScopeFullName.log @@ -117,7 +117,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 3 constant 16 design 1 @@ -143,7 +143,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 6 constant 16 design 1 @@ -207,7 +207,7 @@ design: (work@dut) |vpiParent: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/GenScopeFullName/dut.sv, line:1:1, endln:10:10 |vpiForInitStmt: - \_assign_stmt: , line:4:8, endln:4:20 + \_assignment: , line:4:8, endln:4:20 |vpiParent: \_gen_for: |vpiRhs: @@ -219,7 +219,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.i), line:4:15, endln:4:16 |vpiParent: - \_assign_stmt: , line:4:8, endln:4:20 + \_assignment: , line:4:8, endln:4:20 |vpiTypespec: \_ref_typespec: (work@dut.i) |vpiParent: diff --git a/tests/GenScopeFunc/GenScopeFunc.log b/tests/GenScopeFunc/GenScopeFunc.log index a60e95fa0c..e26fb38b7e 100644 --- a/tests/GenScopeFunc/GenScopeFunc.log +++ b/tests/GenScopeFunc/GenScopeFunc.log @@ -211,7 +211,6 @@ design: (work@top) \_hier_path: (cscope.local_function), line:11:16, endln:11:46 |vpiParent: \_cont_assign: , line:11:10, endln:11:46 - |vpiName:cscope.local_function |vpiActual: \_ref_obj: (cscope), line:11:16, endln:11:22 |vpiParent: @@ -230,6 +229,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@mod.counter), line:11:38, endln:11:45 |vpiName:local_function + |vpiName:cscope.local_function |vpiLhs: \_ref_obj: (work@mod.foo), line:11:10, endln:11:13 |vpiParent: @@ -376,7 +376,6 @@ design: (work@top) \_hier_path: (cscope.local_function), line:11:16, endln:11:46 |vpiParent: \_cont_assign: , line:11:10, endln:11:46 - |vpiName:cscope.local_function |vpiActual: \_ref_obj: (cscope), line:11:16, endln:11:22 |vpiParent: @@ -399,6 +398,7 @@ design: (work@top) |vpiName:local_function |vpiFunction: \_function: (work@top.c.cscope.local_function), line:5:7, endln:7:18 + |vpiName:cscope.local_function |vpiLhs: \_ref_obj: (work@top.c.foo), line:11:10, endln:11:13 |vpiParent: diff --git a/tests/GenScopeHierPath/GenScopeHierPath.log b/tests/GenScopeHierPath/GenScopeHierPath.log index d4a0a91949..f8957a9b77 100644 --- a/tests/GenScopeHierPath/GenScopeHierPath.log +++ b/tests/GenScopeHierPath/GenScopeHierPath.log @@ -425,7 +425,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 4 constant 189 cont_assign 9 @@ -463,7 +463,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 4 constant 189 cont_assign 37 @@ -1226,7 +1226,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenScopeHierPath/dut.sv, line:44:1, endln:53:10 |vpiForInitStmt: - \_assign_stmt: , line:48:8, endln:48:20 + \_assignment: , line:48:8, endln:48:20 |vpiParent: \_gen_for: |vpiRhs: @@ -1238,7 +1238,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.k), line:48:15, endln:48:16 |vpiParent: - \_assign_stmt: , line:48:8, endln:48:20 + \_assignment: , line:48:8, endln:48:20 |vpiTypespec: \_ref_typespec: (work@top.k) |vpiParent: diff --git a/tests/GenScopeHierPath2/GenScopeHierPath2.log b/tests/GenScopeHierPath2/GenScopeHierPath2.log index 838e28f958..47c5b08a1a 100644 --- a/tests/GenScopeHierPath2/GenScopeHierPath2.log +++ b/tests/GenScopeHierPath2/GenScopeHierPath2.log @@ -614,7 +614,6 @@ design: (work@mod) \_hier_path: (blk1.w), line:18:28, endln:18:34 |vpiParent: \_sys_func_call: ($bits), line:18:22, endln:18:35 - |vpiName:blk1.w |vpiActual: \_ref_obj: (blk1), line:18:28, endln:18:32 |vpiParent: @@ -626,6 +625,7 @@ design: (work@mod) \_hier_path: (blk1.w), line:18:28, endln:18:34 |vpiName:w |vpiFullName:work@mod.w + |vpiName:blk1.w |vpiName:$bits |vpiLhs: \_ref_obj: (work@mod.out), line:18:16, endln:18:19 @@ -678,7 +678,6 @@ design: (work@mod) \_hier_path: (blk2.x), line:20:28, endln:20:34 |vpiParent: \_sys_func_call: ($bits), line:20:22, endln:20:35 - |vpiName:blk2.x |vpiActual: \_ref_obj: (blk2), line:20:28, endln:20:32 |vpiParent: @@ -690,6 +689,7 @@ design: (work@mod) \_hier_path: (blk2.x), line:20:28, endln:20:34 |vpiName:x |vpiFullName:work@mod.x + |vpiName:blk2.x |vpiName:$bits |vpiLhs: \_ref_obj: (work@mod.out), line:20:16, endln:20:19 @@ -742,7 +742,6 @@ design: (work@mod) \_hier_path: (blk3.y), line:22:28, endln:22:34 |vpiParent: \_sys_func_call: ($bits), line:22:22, endln:22:35 - |vpiName:blk3.y |vpiActual: \_ref_obj: (blk3), line:22:28, endln:22:32 |vpiParent: @@ -754,6 +753,7 @@ design: (work@mod) \_hier_path: (blk3.y), line:22:28, endln:22:34 |vpiName:y |vpiFullName:work@mod.y + |vpiName:blk3.y |vpiName:$bits |vpiLhs: \_ref_obj: (work@mod.out), line:22:16, endln:22:19 @@ -778,7 +778,6 @@ design: (work@mod) \_hier_path: (blk4.z), line:24:28, endln:24:34 |vpiParent: \_sys_func_call: ($bits), line:24:22, endln:24:35 - |vpiName:blk4.z |vpiActual: \_ref_obj: (blk4), line:24:28, endln:24:32 |vpiParent: @@ -790,6 +789,7 @@ design: (work@mod) \_hier_path: (blk4.z), line:24:28, endln:24:34 |vpiName:z |vpiFullName:work@mod.z + |vpiName:blk4.z |vpiName:$bits |vpiLhs: \_ref_obj: (work@mod.out), line:24:16, endln:24:19 @@ -966,7 +966,6 @@ design: (work@mod) \_hier_path: (blk4.z), line:24:28, endln:24:34 |vpiParent: \_sys_func_call: ($bits), line:24:22, endln:24:35 - |vpiName:blk4.z |vpiActual: \_ref_obj: (blk4), line:24:28, endln:24:32 |vpiParent: @@ -982,6 +981,7 @@ design: (work@mod) |vpiFullName:work@mod.genblk2.z |vpiActual: \_array_net: (work@mod.blk4.z), line:15:14, endln:15:15 + |vpiName:blk4.z |vpiName:$bits |vpiLhs: \_ref_obj: (work@mod.genblk2.out), line:24:16, endln:24:19 diff --git a/tests/GenerateBlock/GenerateBlock.log b/tests/GenerateBlock/GenerateBlock.log index c3ebff1914..5bb8b108d6 100644 --- a/tests/GenerateBlock/GenerateBlock.log +++ b/tests/GenerateBlock/GenerateBlock.log @@ -287,7 +287,6 @@ design: (work@gen_test9) \_hier_path: (B.y), line:16:36, endln:16:39 |vpiParent: \_operation: , line:16:36, endln:16:47 - |vpiName:B.y |vpiActual: \_ref_obj: (B), line:16:36, endln:16:37 |vpiParent: @@ -301,6 +300,7 @@ design: (work@gen_test9) \_hier_path: (B.y), line:16:36, endln:16:39 |vpiName:y |vpiFullName:work@gen_test9.A.y + |vpiName:B.y |vpiOperand: \_constant: , line:16:42, endln:16:47 |vpiParent: @@ -313,7 +313,6 @@ design: (work@gen_test9) \_hier_path: (C.z), line:16:50, endln:16:53 |vpiParent: \_operation: , line:16:36, endln:16:53 - |vpiName:C.z |vpiActual: \_ref_obj: (C), line:16:50, endln:16:51 |vpiParent: @@ -327,6 +326,7 @@ design: (work@gen_test9) \_hier_path: (C.z), line:16:50, endln:16:53 |vpiName:z |vpiFullName:work@gen_test9.A.z + |vpiName:C.z |vpiLhs: \_ref_obj: (work@gen_test9.A.x), line:16:32, endln:16:33 |vpiParent: @@ -396,7 +396,6 @@ design: (work@gen_test9) \_hier_path: (B.y), line:16:36, endln:16:39 |vpiParent: \_operation: , line:16:36, endln:16:47 - |vpiName:B.y |vpiActual: \_ref_obj: (B), line:16:36, endln:16:37 |vpiParent: @@ -412,6 +411,7 @@ design: (work@gen_test9) |vpiFullName:work@gen_test9.A.y |vpiActual: \_logic_net: (work@gen_test9.A.B.y), line:8:44, endln:8:45 + |vpiName:B.y |vpiOperand: \_constant: , line:16:42, endln:16:47 |vpiParent: @@ -424,7 +424,6 @@ design: (work@gen_test9) \_hier_path: (C.z), line:16:50, endln:16:53 |vpiParent: \_operation: , line:16:36, endln:16:53 - |vpiName:C.z |vpiActual: \_ref_obj: (C), line:16:50, endln:16:51 |vpiParent: @@ -440,6 +439,7 @@ design: (work@gen_test9) |vpiFullName:work@gen_test9.A.z |vpiActual: \_logic_net: (work@gen_test9.A.C.z), line:13:44, endln:13:45 + |vpiName:C.z |vpiLhs: \_ref_obj: (work@gen_test9.A.x), line:16:32, endln:16:33 |vpiParent: @@ -573,7 +573,6 @@ design: (work@gen_test9) \_hier_path: (B.y), line:16:36, endln:16:39 |vpiParent: \_operation: , line:16:36, endln:16:47 - |vpiName:B.y |vpiActual: \_ref_obj: (B), line:16:36, endln:16:37 |vpiParent: @@ -585,6 +584,7 @@ design: (work@gen_test9) \_hier_path: (B.y), line:16:36, endln:16:39 |vpiName:y |vpiFullName:work@gen_test9.A.y + |vpiName:B.y |vpiOperand: \_constant: , line:16:42, endln:16:47 \_operation: , line:16:36, endln:16:53 @@ -597,7 +597,6 @@ design: (work@gen_test9) \_hier_path: (C.z), line:16:50, endln:16:53 |vpiParent: \_operation: , line:16:36, endln:16:53 - |vpiName:C.z |vpiActual: \_ref_obj: (C), line:16:50, endln:16:51 |vpiParent: @@ -609,6 +608,7 @@ design: (work@gen_test9) \_hier_path: (C.z), line:16:50, endln:16:53 |vpiName:z |vpiFullName:work@gen_test9.A.z + |vpiName:C.z \_cont_assign: , line:16:32, endln:16:53 |vpiParent: \_gen_scope: (work@gen_test9.A), line:4:17, endln:17:20 diff --git a/tests/GenerateInterface/GenerateInterface.log b/tests/GenerateInterface/GenerateInterface.log index e5e7db86d4..e44aa30c1d 100644 --- a/tests/GenerateInterface/GenerateInterface.log +++ b/tests/GenerateInterface/GenerateInterface.log @@ -740,7 +740,7 @@ Instance tree: [NTE:EL0522] ${SURELOG_DIR}/tests/GenerateInterface/top.sv:28:40: Scope "work@top2.intf.each_pin_intf[1]". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 begin 2 bit_select 18 class_defn 8 @@ -1345,7 +1345,7 @@ design: (work@top) |vpiParent: \_interface_inst: work@abc_if (work@abc_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:1:1, endln:13:13 |vpiForInitStmt: - \_assign_stmt: , line:6:8, endln:6:18 + \_assignment: , line:6:8, endln:6:18 |vpiParent: \_gen_for: |vpiRhs: @@ -1357,7 +1357,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@abc_if.i), line:6:15, endln:6:16 |vpiParent: - \_assign_stmt: , line:6:8, endln:6:18 + \_assignment: , line:6:8, endln:6:18 |vpiTypespec: \_ref_typespec: (work@abc_if.i) |vpiParent: @@ -1486,7 +1486,7 @@ design: (work@top) |vpiParent: \_interface_inst: work@pins_if (work@pins_if), file:${SURELOG_DIR}/tests/GenerateInterface/top.sv, line:22:1, endln:32:13 |vpiForInitStmt: - \_assign_stmt: , line:28:10, endln:28:22 + \_assignment: , line:28:10, endln:28:22 |vpiParent: \_gen_for: |vpiRhs: @@ -1498,7 +1498,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@pins_if.i), line:28:17, endln:28:18 |vpiParent: - \_assign_stmt: , line:28:10, endln:28:22 + \_assignment: , line:28:10, endln:28:22 |vpiTypespec: \_ref_typespec: (work@pins_if.i) |vpiParent: diff --git a/tests/GenerateModule/GenerateModule.log b/tests/GenerateModule/GenerateModule.log index eec968e2a5..ddf40d1648 100644 --- a/tests/GenerateModule/GenerateModule.log +++ b/tests/GenerateModule/GenerateModule.log @@ -675,7 +675,7 @@ Instance tree: [NTE:EL0523] ${SURELOG_DIR}/tests/GenerateModule/top.v:13:17: Instance "work@small_test.B1[4].B4.B5[4].N4". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 2 bit_select 8 class_defn 8 @@ -1359,7 +1359,7 @@ design: (work@small_test) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/GenerateModule/top.v, line:21:1, endln:26:10 |vpiForInitStmt: - \_assign_stmt: , line:23:8, endln:23:18 + \_assignment: , line:23:8, endln:23:18 |vpiParent: \_gen_for: |vpiRhs: @@ -1371,7 +1371,7 @@ design: (work@small_test) |vpiLhs: \_int_var: (work@top.i), line:23:15, endln:23:16 |vpiParent: - \_assign_stmt: , line:23:8, endln:23:18 + \_assignment: , line:23:8, endln:23:18 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: diff --git a/tests/GenerateRegion/GenerateRegion.log b/tests/GenerateRegion/GenerateRegion.log index 810f79c5fe..5dc73f2707 100644 --- a/tests/GenerateRegion/GenerateRegion.log +++ b/tests/GenerateRegion/GenerateRegion.log @@ -1104,8 +1104,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 7 -assign_stmt 1 -assignment 9 +assignment 10 begin 6 bit_select 12 constant 195 @@ -1140,8 +1139,7 @@ sys_func_call 1 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 12 -assign_stmt 1 -assignment 15 +assignment 16 begin 6 bit_select 21 constant 197 @@ -1263,7 +1261,6 @@ design: (work@oh_delay) \_hier_path: (B.y), line:61:36, endln:61:39 |vpiParent: \_operation: , line:61:36, endln:61:47 - |vpiName:B.y |vpiActual: \_ref_obj: (B), line:61:36, endln:61:37 |vpiParent: @@ -1277,6 +1274,7 @@ design: (work@oh_delay) \_hier_path: (B.y), line:61:36, endln:61:39 |vpiName:y |vpiFullName:work@gen_test9.A.y + |vpiName:B.y |vpiOperand: \_constant: , line:61:42, endln:61:47 |vpiParent: @@ -1289,7 +1287,6 @@ design: (work@oh_delay) \_hier_path: (C.z), line:61:50, endln:61:53 |vpiParent: \_operation: , line:61:36, endln:61:53 - |vpiName:C.z |vpiActual: \_ref_obj: (C), line:61:50, endln:61:51 |vpiParent: @@ -1303,6 +1300,7 @@ design: (work@oh_delay) \_hier_path: (C.z), line:61:50, endln:61:53 |vpiName:z |vpiFullName:work@gen_test9.A.z + |vpiName:C.z |vpiLhs: \_ref_obj: (work@gen_test9.A.x), line:61:32, endln:61:33 |vpiParent: @@ -1719,13 +1717,15 @@ design: (work@oh_delay) \_gen_if_else: , line:103:7, endln:121:5 |vpiFullName:work@oh_rsync |vpiStmt: - \_assign_stmt: , line:105:24, endln:105:33 + \_assignment: , line:105:24, endln:105:33 |vpiParent: \_begin: (work@oh_rsync) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@oh_rsync.sync_pipe), line:105:24, endln:105:33 |vpiParent: - \_assign_stmt: , line:105:24, endln:105:33 + \_assignment: , line:105:24, endln:105:33 |vpiTypespec: \_ref_typespec: (work@oh_rsync.sync_pipe) |vpiParent: @@ -3258,7 +3258,6 @@ design: (work@oh_delay) \_hier_path: (B.y), line:61:36, endln:61:39 |vpiParent: \_operation: , line:61:36, endln:61:47 - |vpiName:B.y |vpiActual: \_ref_obj: (B), line:61:36, endln:61:37 |vpiParent: @@ -3274,6 +3273,7 @@ design: (work@oh_delay) |vpiFullName:work@gen_test9.A.y |vpiActual: \_logic_net: (work@gen_test9.A.B.y), line:53:44, endln:53:45 + |vpiName:B.y |vpiOperand: \_constant: , line:61:42, endln:61:47 |vpiParent: @@ -3286,7 +3286,6 @@ design: (work@oh_delay) \_hier_path: (C.z), line:61:50, endln:61:53 |vpiParent: \_operation: , line:61:36, endln:61:53 - |vpiName:C.z |vpiActual: \_ref_obj: (C), line:61:50, endln:61:51 |vpiParent: @@ -3302,6 +3301,7 @@ design: (work@oh_delay) |vpiFullName:work@gen_test9.A.z |vpiActual: \_logic_net: (work@gen_test9.A.C.z), line:58:44, endln:58:45 + |vpiName:C.z |vpiLhs: \_ref_obj: (work@gen_test9.A.x), line:61:32, endln:61:33 |vpiParent: @@ -4356,7 +4356,6 @@ design: (work@oh_delay) \_hier_path: (B.y), line:61:36, endln:61:39 |vpiParent: \_operation: , line:61:36, endln:61:47 - |vpiName:B.y |vpiActual: \_ref_obj: (B), line:61:36, endln:61:37 |vpiParent: @@ -4368,6 +4367,7 @@ design: (work@oh_delay) \_hier_path: (B.y), line:61:36, endln:61:39 |vpiName:y |vpiFullName:work@gen_test9.A.y + |vpiName:B.y |vpiOperand: \_constant: , line:61:42, endln:61:47 \_operation: , line:61:36, endln:61:53 @@ -4380,7 +4380,6 @@ design: (work@oh_delay) \_hier_path: (C.z), line:61:50, endln:61:53 |vpiParent: \_operation: , line:61:36, endln:61:53 - |vpiName:C.z |vpiActual: \_ref_obj: (C), line:61:50, endln:61:51 |vpiParent: @@ -4392,6 +4391,7 @@ design: (work@oh_delay) \_hier_path: (C.z), line:61:50, endln:61:53 |vpiName:z |vpiFullName:work@gen_test9.A.z + |vpiName:C.z \_cont_assign: , line:61:32, endln:61:53 |vpiParent: \_gen_scope: (work@gen_test9.A), line:49:17, endln:62:20 diff --git a/tests/HierBitSlice/HierBitSlice.log b/tests/HierBitSlice/HierBitSlice.log index 198cd9d488..ead4b450eb 100644 --- a/tests/HierBitSlice/HierBitSlice.log +++ b/tests/HierBitSlice/HierBitSlice.log @@ -5553,7 +5553,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch), line:291:16, endln:291:37 |vpiParent: \_operation: , line:290:13, endln:291:37 - |vpiName:of_instruction.branch |vpiActual: \_ref_obj: (of_instruction), line:291:16, endln:291:30 |vpiParent: @@ -5565,6 +5564,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch), line:291:16, endln:291:37 |vpiName:branch |vpiFullName:work@int_execute_stage.branch + |vpiName:of_instruction.branch |vpiOperand: \_operation: , line:292:16, endln:292:36 |vpiParent: @@ -5593,7 +5593,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:294:26, endln:294:52 |vpiParent: \_begin: (work@int_execute_stage), line:293:9, endln:319:12 - |vpiName:of_instruction.branch_type |vpiActual: \_ref_obj: (of_instruction), line:294:26, endln:294:40 |vpiParent: @@ -5605,6 +5604,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:294:26, endln:294:52 |vpiName:branch_type |vpiFullName:work@int_execute_stage.branch_type + |vpiName:of_instruction.branch_type |vpiCaseItem: \_case_item: , line:295:17, endln:299:20 |vpiParent: @@ -5976,7 +5976,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:332:22, endln:332:48 |vpiParent: \_begin: (work@int_execute_stage), line:324:5, endln:339:8 - |vpiName:of_instruction.branch_type |vpiActual: \_ref_obj: (of_instruction), line:332:22, endln:332:36 |vpiParent: @@ -5988,6 +5987,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:332:22, endln:332:48 |vpiName:branch_type |vpiFullName:work@int_execute_stage.branch_type + |vpiName:of_instruction.branch_type |vpiCaseItem: \_case_item: , line:333:13, endln:334:63 |vpiParent: @@ -6092,7 +6092,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.pc), line:337:35, endln:337:52 |vpiParent: \_operation: , line:337:35, endln:337:85 - |vpiName:of_instruction.pc |vpiActual: \_ref_obj: (of_instruction), line:337:35, endln:337:49 |vpiParent: @@ -6104,11 +6103,11 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.pc), line:337:35, endln:337:52 |vpiName:pc |vpiFullName:work@int_execute_stage.pc + |vpiName:of_instruction.pc |vpiOperand: \_hier_path: (of_instruction.immediate_value), line:337:55, endln:337:85 |vpiParent: \_operation: , line:337:35, endln:337:85 - |vpiName:of_instruction.immediate_value |vpiActual: \_ref_obj: (of_instruction), line:337:55, endln:337:69 |vpiParent: @@ -6120,6 +6119,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.immediate_value), line:337:55, endln:337:85 |vpiName:immediate_value |vpiFullName:work@int_execute_stage.immediate_value + |vpiName:of_instruction.immediate_value |vpiLhs: \_ref_obj: (work@int_execute_stage.ix_rollback_pc), line:337:17, endln:337:31 |vpiParent: @@ -6613,7 +6613,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.pipeline_sel), line:279:12, endln:279:39 |vpiParent: \_operation: , line:279:12, endln:279:57 - |vpiName:of_instruction.pipeline_sel |vpiActual: \_ref_obj: (of_instruction), line:279:12, endln:279:26 |vpiParent: @@ -6625,6 +6624,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.pipeline_sel), line:279:12, endln:279:39 |vpiName:pipeline_sel |vpiFullName:work@int_execute_stage.pipeline_sel + |vpiName:of_instruction.pipeline_sel |vpiOperand: \_ref_obj: (work@int_execute_stage.PIPE_INT_ARITH), line:279:43, endln:279:57 |vpiParent: @@ -6667,7 +6667,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch), line:281:12, endln:281:33 |vpiParent: \_operation: , line:280:19, endln:281:33 - |vpiName:of_instruction.branch |vpiActual: \_ref_obj: (of_instruction), line:281:12, endln:281:26 |vpiParent: @@ -6679,6 +6678,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch), line:281:12, endln:281:33 |vpiName:branch |vpiFullName:work@int_execute_stage.branch + |vpiName:of_instruction.branch |vpiOperand: \_operation: , line:282:12, endln:282:53 |vpiParent: @@ -6688,7 +6688,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:282:12, endln:282:38 |vpiParent: \_operation: , line:282:12, endln:282:53 - |vpiName:of_instruction.branch_type |vpiActual: \_ref_obj: (of_instruction), line:282:12, endln:282:26 |vpiParent: @@ -6700,6 +6699,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:282:12, endln:282:38 |vpiName:branch_type |vpiFullName:work@int_execute_stage.branch_type + |vpiName:of_instruction.branch_type |vpiOperand: \_ref_obj: (work@int_execute_stage.BRANCH_ERET), line:282:42, endln:282:53 |vpiParent: @@ -8570,7 +8570,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch), line:291:16, endln:291:37 |vpiParent: \_operation: , line:290:13, endln:291:37 - |vpiName:of_instruction.branch |vpiActual: \_ref_obj: (of_instruction), line:291:16, endln:291:30 |vpiParent: @@ -8586,6 +8585,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.branch |vpiActual: \_typespec_member: (branch), line:36:11, endln:36:17 + |vpiName:of_instruction.branch |vpiOperand: \_operation: , line:292:16, endln:292:36 |vpiParent: @@ -8614,7 +8614,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:294:26, endln:294:52 |vpiParent: \_case_stmt: , line:294:13, endln:318:20 - |vpiName:of_instruction.branch_type |vpiActual: \_ref_obj: (of_instruction), line:294:26, endln:294:40 |vpiParent: @@ -8630,6 +8629,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.branch_type |vpiActual: \_typespec_member: (branch_type), line:37:19, endln:37:30 + |vpiName:of_instruction.branch_type |vpiCaseItem: \_case_item: , line:295:17, endln:299:20 |vpiParent: @@ -8969,7 +8969,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:332:22, endln:332:48 |vpiParent: \_case_stmt: , line:332:9, endln:338:16 - |vpiName:of_instruction.branch_type |vpiActual: \_ref_obj: (of_instruction), line:332:22, endln:332:36 |vpiParent: @@ -8985,6 +8984,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.branch_type |vpiActual: \_typespec_member: (branch_type), line:37:19, endln:37:30 + |vpiName:of_instruction.branch_type |vpiCaseItem: \_case_item: , line:333:13, endln:334:63 |vpiParent: @@ -9087,7 +9087,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.pc), line:337:35, endln:337:52 |vpiParent: \_operation: , line:337:35, endln:337:85 - |vpiName:of_instruction.pc |vpiActual: \_ref_obj: (of_instruction), line:337:35, endln:337:49 |vpiParent: @@ -9103,11 +9102,11 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.pc |vpiActual: \_typespec_member: (pc), line:9:14, endln:9:16 + |vpiName:of_instruction.pc |vpiOperand: \_hier_path: (of_instruction.immediate_value), line:337:55, endln:337:85 |vpiParent: \_operation: , line:337:35, endln:337:85 - |vpiName:of_instruction.immediate_value |vpiActual: \_ref_obj: (of_instruction), line:337:55, endln:337:69 |vpiParent: @@ -9123,6 +9122,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.immediate_value |vpiActual: \_typespec_member: (immediate_value), line:35:14, endln:35:29 + |vpiName:of_instruction.immediate_value |vpiLhs: \_ref_obj: (work@int_execute_stage.ix_rollback_pc), line:337:17, endln:337:31 |vpiParent: @@ -12025,7 +12025,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:220:21, endln:220:40 |vpiParent: \_operation: , line:220:21, endln:220:45 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:220:21, endln:220:31 |vpiParent: @@ -12041,6 +12040,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].exponent |vpiActual: \_typespec_member: (exponent), line:4:34, endln:4:42 + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:220:44, endln:220:45 |vpiParent: @@ -12069,7 +12069,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:224:35, endln:224:50 |vpiParent: \_operation: , line:224:34, endln:224:65 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:224:35, endln:224:45 |vpiParent: @@ -12085,6 +12084,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].sign |vpiActual: \_typespec_member: (sign), line:3:9, endln:3:13 + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:224:52, endln:224:57 |vpiDecompile:8'hff @@ -12118,7 +12118,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:226:26, endln:226:45 |vpiParent: \_operation: , line:226:26, endln:226:54 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:226:26, endln:226:36 |vpiParent: @@ -12134,6 +12133,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].exponent |vpiActual: \_typespec_member: (exponent), line:4:34, endln:4:42 + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:226:49, endln:226:54 |vpiParent: @@ -12160,7 +12160,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand), line:228:25, endln:228:47 |vpiParent: \_operation: , line:228:25, endln:228:52 - |vpiName:fp_operand.significand |vpiActual: \_ref_obj: (fp_operand), line:228:25, endln:228:35 |vpiParent: @@ -12176,6 +12175,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].significand |vpiActual: \_typespec_member: (significand), line:5:34, endln:5:45 + |vpiName:fp_operand.significand |vpiOperand: \_constant: , line:228:51, endln:228:52 |vpiParent: @@ -12236,7 +12236,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:231:39, endln:231:54 |vpiParent: \_operation: , line:231:38, endln:231:74 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:231:39, endln:231:49 |vpiParent: @@ -12252,6 +12251,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].sign |vpiActual: \_typespec_member: (sign), line:3:9, endln:3:13 + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:231:56, endln:231:61 |vpiDecompile:8'h00 @@ -12292,7 +12292,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:235:35, endln:235:50 |vpiParent: \_operation: , line:235:34, endln:236:57 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:235:35, endln:235:45 |vpiParent: @@ -12308,6 +12307,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].sign |vpiActual: \_typespec_member: (sign), line:3:9, endln:3:13 + |vpiName:fp_operand.sign |vpiOperand: \_operation: , line:235:52, endln:235:123 |vpiParent: @@ -12330,7 +12330,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:235:61, endln:235:80 |vpiParent: \_operation: , line:235:52, endln:235:80 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:235:61, endln:235:71 |vpiParent: @@ -12346,6 +12345,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].exponent |vpiActual: \_typespec_member: (exponent), line:4:34, endln:4:42 + |vpiName:fp_operand.exponent |vpiOperand: \_operation: , line:235:83, endln:235:123 |vpiParent: @@ -12367,7 +12367,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand[22:17]), line:235:87, endln:235:116 |vpiParent: \_operation: , line:235:87, endln:235:121 - |vpiName:fp_operand.significand[22:17] |vpiActual: \_ref_obj: (fp_operand), line:235:87, endln:235:97 |vpiParent: @@ -12396,6 +12395,7 @@ design: (work@int_execute_stage) |vpiSize:64 |UINT:17 |vpiConstType:9 + |vpiName:fp_operand.significand[22:17] |vpiOperand: \_constant: , line:235:120, endln:235:121 |vpiParent: @@ -12462,7 +12462,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 |vpiParent: \_case_stmt: , line:242:17, endln:270:24 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:242:30, endln:242:44 |vpiParent: @@ -12478,6 +12477,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].alu_op |vpiActual: \_typespec_member: (alu_op), line:30:14, endln:30:20 + |vpiName:of_instruction.alu_op |vpiCaseItem: \_case_item: , line:243:21, endln:244:50 |vpiParent: @@ -14199,7 +14199,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:209:36, endln:209:57 |vpiParent: \_operation: , line:209:36, endln:209:68 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:209:36, endln:209:50 |vpiParent: @@ -14215,6 +14214,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].alu_op |vpiActual: \_typespec_member: (alu_op), line:30:14, endln:30:20 + |vpiName:of_instruction.alu_op |vpiOperand: \_ref_obj: (work@int_execute_stage.lane_alu_gen[0].OP_ASHR), line:209:61, endln:209:68 |vpiParent: @@ -14412,9 +14412,6 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rom.significand.fp_operand.significand[22:17] |vpiActual: \_struct_typespec: (float32_t), line:2:9, endln:6:2 - |vpiName:fp_operand.significand[22:17] - |vpiExpr: - \_struct_net: (work@int_execute_stage.lane_alu_gen[0].fp_operand), line:113:23, endln:113:33 |vpiActual: \_ref_obj: (fp_operand), line:215:30, endln:215:40 |vpiParent: @@ -14445,6 +14442,7 @@ design: (work@int_execute_stage) |vpiConstType:9 |vpiExpr: \_struct_net: (work@int_execute_stage.lane_alu_gen[0].fp_operand), line:113:23, endln:113:33 + |vpiName:fp_operand.significand[22:17] |vpiInstance: \_module_inst: work@int_execute_stage.lane_alu_gen[0]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[0].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiPort: @@ -16941,7 +16939,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:220:21, endln:220:40 |vpiParent: \_operation: , line:220:21, endln:220:45 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:220:21, endln:220:31 |vpiParent: @@ -16957,6 +16954,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].exponent |vpiActual: \_typespec_member: (exponent), line:4:34, endln:4:42 + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:220:44, endln:220:45 |vpiParent: @@ -16985,7 +16983,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:224:35, endln:224:50 |vpiParent: \_operation: , line:224:34, endln:224:65 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:224:35, endln:224:45 |vpiParent: @@ -17001,6 +16998,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].sign |vpiActual: \_typespec_member: (sign), line:3:9, endln:3:13 + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:224:52, endln:224:57 |vpiDecompile:8'hff @@ -17034,7 +17032,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:226:26, endln:226:45 |vpiParent: \_operation: , line:226:26, endln:226:54 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:226:26, endln:226:36 |vpiParent: @@ -17050,6 +17047,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].exponent |vpiActual: \_typespec_member: (exponent), line:4:34, endln:4:42 + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:226:49, endln:226:54 |vpiParent: @@ -17076,7 +17074,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand), line:228:25, endln:228:47 |vpiParent: \_operation: , line:228:25, endln:228:52 - |vpiName:fp_operand.significand |vpiActual: \_ref_obj: (fp_operand), line:228:25, endln:228:35 |vpiParent: @@ -17092,6 +17089,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].significand |vpiActual: \_typespec_member: (significand), line:5:34, endln:5:45 + |vpiName:fp_operand.significand |vpiOperand: \_constant: , line:228:51, endln:228:52 |vpiParent: @@ -17152,7 +17150,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:231:39, endln:231:54 |vpiParent: \_operation: , line:231:38, endln:231:74 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:231:39, endln:231:49 |vpiParent: @@ -17168,6 +17165,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].sign |vpiActual: \_typespec_member: (sign), line:3:9, endln:3:13 + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:231:56, endln:231:61 |vpiDecompile:8'h00 @@ -17208,7 +17206,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:235:35, endln:235:50 |vpiParent: \_operation: , line:235:34, endln:236:57 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:235:35, endln:235:45 |vpiParent: @@ -17224,6 +17221,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].sign |vpiActual: \_typespec_member: (sign), line:3:9, endln:3:13 + |vpiName:fp_operand.sign |vpiOperand: \_operation: , line:235:52, endln:235:123 |vpiParent: @@ -17246,7 +17244,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:235:61, endln:235:80 |vpiParent: \_operation: , line:235:52, endln:235:80 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:235:61, endln:235:71 |vpiParent: @@ -17262,6 +17259,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].exponent |vpiActual: \_typespec_member: (exponent), line:4:34, endln:4:42 + |vpiName:fp_operand.exponent |vpiOperand: \_operation: , line:235:83, endln:235:123 |vpiParent: @@ -17283,7 +17281,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand[22:17]), line:235:87, endln:235:116 |vpiParent: \_operation: , line:235:87, endln:235:121 - |vpiName:fp_operand.significand[22:17] |vpiActual: \_ref_obj: (fp_operand), line:235:87, endln:235:97 |vpiParent: @@ -17312,6 +17309,7 @@ design: (work@int_execute_stage) |vpiSize:64 |UINT:17 |vpiConstType:9 + |vpiName:fp_operand.significand[22:17] |vpiOperand: \_constant: , line:235:120, endln:235:121 |vpiParent: @@ -17378,7 +17376,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 |vpiParent: \_case_stmt: , line:242:17, endln:270:24 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:242:30, endln:242:44 |vpiParent: @@ -17394,6 +17391,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].alu_op |vpiActual: \_typespec_member: (alu_op), line:30:14, endln:30:20 + |vpiName:of_instruction.alu_op |vpiCaseItem: \_case_item: , line:243:21, endln:244:50 |vpiParent: @@ -19115,7 +19113,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:209:36, endln:209:57 |vpiParent: \_operation: , line:209:36, endln:209:68 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:209:36, endln:209:50 |vpiParent: @@ -19131,6 +19128,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].alu_op |vpiActual: \_typespec_member: (alu_op), line:30:14, endln:30:20 + |vpiName:of_instruction.alu_op |vpiOperand: \_ref_obj: (work@int_execute_stage.lane_alu_gen[1].OP_ASHR), line:209:61, endln:209:68 |vpiParent: @@ -19328,9 +19326,6 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rom.significand.fp_operand.significand[22:17] |vpiActual: \_struct_typespec: (float32_t), line:2:9, endln:6:2 - |vpiName:fp_operand.significand[22:17] - |vpiExpr: - \_struct_net: (work@int_execute_stage.lane_alu_gen[1].fp_operand), line:113:23, endln:113:33 |vpiActual: \_ref_obj: (fp_operand), line:215:30, endln:215:40 |vpiParent: @@ -19361,6 +19356,7 @@ design: (work@int_execute_stage) |vpiConstType:9 |vpiExpr: \_struct_net: (work@int_execute_stage.lane_alu_gen[1].fp_operand), line:113:23, endln:113:33 + |vpiName:fp_operand.significand[22:17] |vpiInstance: \_module_inst: work@int_execute_stage.lane_alu_gen[1]::reciprocal_rom (work@int_execute_stage.lane_alu_gen[1].rom), file:${SURELOG_DIR}/tests/HierBitSlice/dut.sv, line:214:13, endln:216:39 |vpiPort: @@ -19448,7 +19444,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.pipeline_sel), line:279:12, endln:279:39 |vpiParent: \_operation: , line:279:12, endln:279:57 - |vpiName:of_instruction.pipeline_sel |vpiActual: \_ref_obj: (of_instruction), line:279:12, endln:279:26 |vpiParent: @@ -19464,6 +19459,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.pipeline_sel |vpiActual: \_typespec_member: (pipeline_sel), line:39:20, endln:39:32 + |vpiName:of_instruction.pipeline_sel |vpiOperand: \_ref_obj: (work@int_execute_stage.PIPE_INT_ARITH), line:279:43, endln:279:57 |vpiParent: @@ -19506,7 +19502,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch), line:281:12, endln:281:33 |vpiParent: \_operation: , line:280:19, endln:281:33 - |vpiName:of_instruction.branch |vpiActual: \_ref_obj: (of_instruction), line:281:12, endln:281:26 |vpiParent: @@ -19522,6 +19517,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.branch |vpiActual: \_typespec_member: (branch), line:36:11, endln:36:17 + |vpiName:of_instruction.branch |vpiOperand: \_operation: , line:282:12, endln:282:53 |vpiParent: @@ -19531,7 +19527,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.branch_type), line:282:12, endln:282:38 |vpiParent: \_operation: , line:282:12, endln:282:53 - |vpiName:of_instruction.branch_type |vpiActual: \_ref_obj: (of_instruction), line:282:12, endln:282:26 |vpiParent: @@ -19547,6 +19542,7 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.branch_type |vpiActual: \_typespec_member: (branch_type), line:37:19, endln:37:30 + |vpiName:of_instruction.branch_type |vpiOperand: \_ref_obj: (work@int_execute_stage.BRANCH_ERET), line:282:42, endln:282:53 |vpiParent: @@ -21755,7 +21751,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:209:36, endln:209:57 |vpiParent: \_operation: , line:209:36, endln:209:68 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:209:36, endln:209:50 |vpiParent: @@ -21767,6 +21762,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:209:36, endln:209:57 |vpiName:alu_op |vpiFullName:work@int_execute_stage.lane_alu_gen[0].alu_op + |vpiName:of_instruction.alu_op |vpiOperand: \_ref_obj: (work@int_execute_stage.lane_alu_gen[0].OP_ASHR), line:209:61, endln:209:68 |vpiParent: @@ -21804,7 +21800,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:220:21, endln:220:40 |vpiParent: \_operation: , line:220:21, endln:220:45 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:220:21, endln:220:31 |vpiParent: @@ -21816,6 +21811,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:220:21, endln:220:40 |vpiName:exponent |vpiFullName:work@int_execute_stage.lane_alu_gen[0].exponent + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:220:44, endln:220:45 \_begin: (work@int_execute_stage.lane_alu_gen[0]), line:219:13, endln:238:16 @@ -21848,7 +21844,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:224:35, endln:224:50 |vpiParent: \_operation: , line:224:34, endln:224:65 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:224:35, endln:224:45 |vpiParent: @@ -21860,6 +21855,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:224:35, endln:224:50 |vpiName:sign |vpiFullName:work@int_execute_stage.lane_alu_gen[0].sign + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:224:52, endln:224:57 |vpiOperand: @@ -21885,7 +21881,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:226:26, endln:226:45 |vpiParent: \_operation: , line:226:26, endln:226:54 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:226:26, endln:226:36 |vpiParent: @@ -21897,6 +21892,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:226:26, endln:226:45 |vpiName:exponent |vpiFullName:work@int_execute_stage.lane_alu_gen[0].exponent + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:226:49, endln:226:54 |vpiStmt: @@ -21917,7 +21913,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand), line:228:25, endln:228:47 |vpiParent: \_operation: , line:228:25, endln:228:52 - |vpiName:fp_operand.significand |vpiActual: \_ref_obj: (fp_operand), line:228:25, endln:228:35 |vpiParent: @@ -21929,6 +21924,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand), line:228:25, endln:228:47 |vpiName:significand |vpiFullName:work@int_execute_stage.lane_alu_gen[0].significand + |vpiName:fp_operand.significand |vpiOperand: \_constant: , line:228:51, endln:228:52 |vpiStmt: @@ -21971,7 +21967,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:231:39, endln:231:54 |vpiParent: \_operation: , line:231:38, endln:231:74 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:231:39, endln:231:49 |vpiParent: @@ -21983,6 +21978,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:231:39, endln:231:54 |vpiName:sign |vpiFullName:work@int_execute_stage.lane_alu_gen[0].sign + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:231:56, endln:231:61 |vpiOperand: @@ -22015,7 +22011,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:235:35, endln:235:50 |vpiParent: \_operation: , line:235:34, endln:236:57 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:235:35, endln:235:45 |vpiParent: @@ -22027,6 +22022,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:235:35, endln:235:50 |vpiName:sign |vpiFullName:work@int_execute_stage.lane_alu_gen[0].sign + |vpiName:fp_operand.sign |vpiOperand: \_operation: , line:235:52, endln:235:123 |vpiParent: @@ -22043,7 +22039,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:235:61, endln:235:80 |vpiParent: \_operation: , line:235:52, endln:235:80 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:235:61, endln:235:71 |vpiParent: @@ -22055,6 +22050,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:235:61, endln:235:80 |vpiName:exponent |vpiFullName:work@int_execute_stage.lane_alu_gen[0].exponent + |vpiName:fp_operand.exponent |vpiOperand: \_operation: , line:235:83, endln:235:123 |vpiParent: @@ -22076,7 +22072,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand[22:17]), line:235:87, endln:235:116 |vpiParent: \_operation: , line:235:87, endln:235:121 - |vpiName:fp_operand.significand[22:17] |vpiActual: \_ref_obj: (fp_operand), line:235:87, endln:235:97 |vpiParent: @@ -22093,6 +22088,7 @@ design: (work@int_execute_stage) \_constant: , line:235:110, endln:235:112 |vpiRightRange: \_constant: , line:235:113, endln:235:115 + |vpiName:fp_operand.significand[22:17] |vpiOperand: \_constant: , line:235:120, endln:235:121 |vpiOperand: @@ -24289,7 +24285,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:209:36, endln:209:57 |vpiParent: \_operation: , line:209:36, endln:209:68 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:209:36, endln:209:50 |vpiParent: @@ -24301,6 +24296,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:209:36, endln:209:57 |vpiName:alu_op |vpiFullName:work@int_execute_stage.lane_alu_gen[1].alu_op + |vpiName:of_instruction.alu_op |vpiOperand: \_ref_obj: (work@int_execute_stage.lane_alu_gen[1].OP_ASHR), line:209:61, endln:209:68 |vpiParent: @@ -24338,7 +24334,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:220:21, endln:220:40 |vpiParent: \_operation: , line:220:21, endln:220:45 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:220:21, endln:220:31 |vpiParent: @@ -24350,6 +24345,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:220:21, endln:220:40 |vpiName:exponent |vpiFullName:work@int_execute_stage.lane_alu_gen[1].exponent + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:220:44, endln:220:45 \_begin: (work@int_execute_stage.lane_alu_gen[1]), line:219:13, endln:238:16 @@ -24382,7 +24378,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:224:35, endln:224:50 |vpiParent: \_operation: , line:224:34, endln:224:65 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:224:35, endln:224:45 |vpiParent: @@ -24394,6 +24389,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:224:35, endln:224:50 |vpiName:sign |vpiFullName:work@int_execute_stage.lane_alu_gen[1].sign + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:224:52, endln:224:57 |vpiOperand: @@ -24419,7 +24415,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:226:26, endln:226:45 |vpiParent: \_operation: , line:226:26, endln:226:54 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:226:26, endln:226:36 |vpiParent: @@ -24431,6 +24426,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:226:26, endln:226:45 |vpiName:exponent |vpiFullName:work@int_execute_stage.lane_alu_gen[1].exponent + |vpiName:fp_operand.exponent |vpiOperand: \_constant: , line:226:49, endln:226:54 |vpiStmt: @@ -24451,7 +24447,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand), line:228:25, endln:228:47 |vpiParent: \_operation: , line:228:25, endln:228:52 - |vpiName:fp_operand.significand |vpiActual: \_ref_obj: (fp_operand), line:228:25, endln:228:35 |vpiParent: @@ -24463,6 +24458,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand), line:228:25, endln:228:47 |vpiName:significand |vpiFullName:work@int_execute_stage.lane_alu_gen[1].significand + |vpiName:fp_operand.significand |vpiOperand: \_constant: , line:228:51, endln:228:52 |vpiStmt: @@ -24505,7 +24501,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:231:39, endln:231:54 |vpiParent: \_operation: , line:231:38, endln:231:74 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:231:39, endln:231:49 |vpiParent: @@ -24517,6 +24512,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:231:39, endln:231:54 |vpiName:sign |vpiFullName:work@int_execute_stage.lane_alu_gen[1].sign + |vpiName:fp_operand.sign |vpiOperand: \_constant: , line:231:56, endln:231:61 |vpiOperand: @@ -24549,7 +24545,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:235:35, endln:235:50 |vpiParent: \_operation: , line:235:34, endln:236:57 - |vpiName:fp_operand.sign |vpiActual: \_ref_obj: (fp_operand), line:235:35, endln:235:45 |vpiParent: @@ -24561,6 +24556,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.sign), line:235:35, endln:235:50 |vpiName:sign |vpiFullName:work@int_execute_stage.lane_alu_gen[1].sign + |vpiName:fp_operand.sign |vpiOperand: \_operation: , line:235:52, endln:235:123 |vpiParent: @@ -24577,7 +24573,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:235:61, endln:235:80 |vpiParent: \_operation: , line:235:52, endln:235:80 - |vpiName:fp_operand.exponent |vpiActual: \_ref_obj: (fp_operand), line:235:61, endln:235:71 |vpiParent: @@ -24589,6 +24584,7 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.exponent), line:235:61, endln:235:80 |vpiName:exponent |vpiFullName:work@int_execute_stage.lane_alu_gen[1].exponent + |vpiName:fp_operand.exponent |vpiOperand: \_operation: , line:235:83, endln:235:123 |vpiParent: @@ -24610,7 +24606,6 @@ design: (work@int_execute_stage) \_hier_path: (fp_operand.significand[22:17]), line:235:87, endln:235:116 |vpiParent: \_operation: , line:235:87, endln:235:121 - |vpiName:fp_operand.significand[22:17] |vpiActual: \_ref_obj: (fp_operand), line:235:87, endln:235:97 |vpiParent: @@ -24627,6 +24622,7 @@ design: (work@int_execute_stage) \_constant: , line:235:110, endln:235:112 |vpiRightRange: \_constant: , line:235:113, endln:235:115 + |vpiName:fp_operand.significand[22:17] |vpiOperand: \_constant: , line:235:120, endln:235:121 |vpiOperand: @@ -25431,7 +25427,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 |vpiParent: \_begin: (work@int_execute_stage.lane_alu_gen[0]), line:241:13, endln:271:16 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:242:30, endln:242:44 |vpiParent: @@ -25443,6 +25438,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 |vpiName:alu_op |vpiFullName:work@int_execute_stage.lane_alu_gen[0].alu_op + |vpiName:of_instruction.alu_op |vpiCaseItem: \_case_item: , line:243:21, endln:244:50 |vpiParent: @@ -27012,9 +27008,6 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[0].rom.significand.fp_operand.significand[22:17] |vpiActual: \_struct_typespec: (float32_t), line:2:9, endln:6:2 - |vpiName:fp_operand.significand[22:17] - |vpiExpr: - \_struct_net: (work@int_execute_stage.lane_alu_gen[0].fp_operand), line:113:23, endln:113:33 |vpiActual: \_ref_obj: (fp_operand), line:215:30, endln:215:40 |vpiParent: @@ -27033,6 +27026,7 @@ design: (work@int_execute_stage) \_constant: , line:215:56, endln:215:58 |vpiExpr: \_struct_net: (work@int_execute_stage.lane_alu_gen[0].fp_operand), line:113:23, endln:113:33 + |vpiName:fp_operand.significand[22:17] |vpiPort: \_port: (reciprocal_estimate), line:216:18, endln:216:37 |vpiParent: @@ -27261,7 +27255,6 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 |vpiParent: \_begin: (work@int_execute_stage.lane_alu_gen[1]), line:241:13, endln:271:16 - |vpiName:of_instruction.alu_op |vpiActual: \_ref_obj: (of_instruction), line:242:30, endln:242:44 |vpiParent: @@ -27273,6 +27266,7 @@ design: (work@int_execute_stage) \_hier_path: (of_instruction.alu_op), line:242:30, endln:242:51 |vpiName:alu_op |vpiFullName:work@int_execute_stage.lane_alu_gen[1].alu_op + |vpiName:of_instruction.alu_op |vpiCaseItem: \_case_item: , line:243:21, endln:244:50 |vpiParent: @@ -28842,9 +28836,6 @@ design: (work@int_execute_stage) |vpiFullName:work@int_execute_stage.lane_alu_gen[1].rom.significand.fp_operand.significand[22:17] |vpiActual: \_struct_typespec: (float32_t), line:2:9, endln:6:2 - |vpiName:fp_operand.significand[22:17] - |vpiExpr: - \_struct_net: (work@int_execute_stage.lane_alu_gen[1].fp_operand), line:113:23, endln:113:33 |vpiActual: \_ref_obj: (fp_operand), line:215:30, endln:215:40 |vpiParent: @@ -28863,6 +28854,7 @@ design: (work@int_execute_stage) \_constant: , line:215:56, endln:215:58 |vpiExpr: \_struct_net: (work@int_execute_stage.lane_alu_gen[1].fp_operand), line:113:23, endln:113:33 + |vpiName:fp_operand.significand[22:17] |vpiPort: \_port: (reciprocal_estimate), line:216:18, endln:216:37 |vpiParent: diff --git a/tests/HierMultiSelect/HierMultiSelect.log b/tests/HierMultiSelect/HierMultiSelect.log index 715d50e824..6d47dc8b62 100644 --- a/tests/HierMultiSelect/HierMultiSelect.log +++ b/tests/HierMultiSelect/HierMultiSelect.log @@ -319,7 +319,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr2), line:2:28, endln:2:43 |vpiParent: \_cont_assign: , line:2:10, endln:2:43 - |vpiName:dmi_req_i.addr2 |vpiActual: \_ref_obj: (dmi_req_i), line:2:28, endln:2:37 |vpiParent: @@ -331,11 +330,11 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr2), line:2:28, endln:2:43 |vpiName:addr2 |vpiFullName:work@dm_csrs.addr2 + |vpiName:dmi_req_i.addr2 |vpiLhs: \_hier_path: (dmi_req_i.addr1), line:2:10, endln:2:25 |vpiParent: \_cont_assign: , line:2:10, endln:2:43 - |vpiName:dmi_req_i.addr1 |vpiActual: \_ref_obj: (dmi_req_i), line:2:20, endln:2:25 |vpiParent: @@ -346,6 +345,7 @@ design: (work@dm_csrs) |vpiParent: \_hier_path: (dmi_req_i.addr1), line:2:10, endln:2:25 |vpiName:addr1 + |vpiName:dmi_req_i.addr1 |vpiContAssign: \_cont_assign: , line:3:10, endln:3:58 |vpiParent: @@ -370,7 +370,6 @@ design: (work@dm_csrs) \_hier_path: (keymgr_data_i.strb[i]), line:3:35, endln:3:56 |vpiParent: \_operation: , line:3:34, endln:3:57 - |vpiName:keymgr_data_i.strb[i] |vpiActual: \_ref_obj: (keymgr_data_i), line:3:35, endln:3:48 |vpiParent: @@ -390,6 +389,7 @@ design: (work@dm_csrs) |vpiFullName:work@dm_csrs.keymgr_data_i.strb[i].i |vpiActual: \_logic_net: (work@dm_csrs.i), line:3:24, endln:3:25 + |vpiName:keymgr_data_i.strb[i] |vpiLhs: \_indexed_part_select: kmac_mask_o (work@dm_csrs.kmac_mask_o), line:3:10, endln:3:29 |vpiParent: @@ -434,7 +434,6 @@ design: (work@dm_csrs) \_hier_path: (keymgr_key_i.key[0][1 * 32+:32]), line:4:14, endln:4:47 |vpiParent: \_cont_assign: , line:4:10, endln:4:47 - |vpiName:keymgr_key_i.key[0][1 * 32+:32] |vpiActual: \_ref_obj: (keymgr_key_i), line:4:14, endln:4:26 |vpiParent: @@ -490,6 +489,7 @@ design: (work@dm_csrs) |vpiSize:64 |UINT:32 |vpiConstType:9 + |vpiName:keymgr_key_i.key[0][1 * 32+:32] |vpiLhs: \_ref_obj: (work@dm_csrs.o), line:4:10, endln:4:11 |vpiParent: @@ -514,7 +514,6 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:5:10, endln:5:24 |vpiParent: \_cont_assign: , line:5:10, endln:5:39 - |vpiName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_bit_select: (sram_otp_key_o[2 - 2]), line:5:10, endln:5:24 |vpiParent: @@ -548,6 +547,7 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:5:10, endln:5:24 |vpiName:nonce |vpiFullName:sram_otp_key_o[2 - 2].nonce + |vpiName:sram_otp_key_o[2 - 2].nonce |uhdmtopModules: \_module_inst: work@dm_csrs (work@dm_csrs), file:${SURELOG_DIR}/tests/HierMultiSelect/dut.sv, line:1:1, endln:8:10 |vpiName:work@dm_csrs @@ -569,7 +569,6 @@ design: (work@dm_csrs) \_hier_path: (a[0].source[6-:2]), line:6:13, endln:6:32 |vpiParent: \_logic_var: (work@dm_csrs.c), line:6:9, endln:6:32 - |vpiName:a[0].source[6-:2] |vpiActual: \_bit_select: (a[0]), line:6:13, endln:6:14 |vpiParent: @@ -602,6 +601,7 @@ design: (work@dm_csrs) |vpiSize:64 |UINT:2 |vpiConstType:9 + |vpiName:a[0].source[6-:2] |vpiVariables: \_byte_var: (work@dm_csrs.o), line:7:8, endln:7:17 |vpiParent: @@ -620,7 +620,6 @@ design: (work@dm_csrs) \_hier_path: (b), line:7:12, endln:7:17 |vpiParent: \_byte_var: (work@dm_csrs.o), line:7:8, endln:7:17 - |vpiName:b |vpiActual: \_ref_obj: (work@dm_csrs.o.b), line:7:12, endln:7:13 |vpiParent: @@ -632,6 +631,7 @@ design: (work@dm_csrs) |vpiParent: \_hier_path: (b), line:7:12, endln:7:17 |vpiName:and + |vpiName:b |vpiDefName:work@dm_csrs |vpiTop:1 |vpiTopModule:1 @@ -643,7 +643,6 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr2), line:2:28, endln:2:43 |vpiParent: \_cont_assign: , line:2:10, endln:2:43 - |vpiName:dmi_req_i.addr2 |vpiActual: \_ref_obj: (dmi_req_i), line:2:28, endln:2:37 |vpiParent: @@ -655,11 +654,11 @@ design: (work@dm_csrs) \_hier_path: (dmi_req_i.addr2), line:2:28, endln:2:43 |vpiName:addr2 |vpiFullName:work@dm_csrs.addr2 + |vpiName:dmi_req_i.addr2 |vpiLhs: \_hier_path: (dmi_req_i.addr1), line:2:10, endln:2:25 |vpiParent: \_cont_assign: , line:2:10, endln:2:43 - |vpiName:dmi_req_i.addr1 |vpiActual: \_ref_obj: (dmi_req_i), line:2:20, endln:2:25 |vpiParent: @@ -670,6 +669,7 @@ design: (work@dm_csrs) |vpiParent: \_hier_path: (dmi_req_i.addr1), line:2:10, endln:2:25 |vpiName:addr1 + |vpiName:dmi_req_i.addr1 |vpiContAssign: \_cont_assign: , line:3:10, endln:3:58 |vpiParent: @@ -690,7 +690,6 @@ design: (work@dm_csrs) \_hier_path: (keymgr_data_i.strb[i]), line:3:35, endln:3:56 |vpiParent: \_operation: , line:3:34, endln:3:57 - |vpiName:keymgr_data_i.strb[i] |vpiActual: \_ref_obj: (keymgr_data_i), line:3:35, endln:3:48 |vpiParent: @@ -710,6 +709,7 @@ design: (work@dm_csrs) |vpiFullName:work@dm_csrs.keymgr_data_i.strb[i].i |vpiActual: \_logic_net: (work@dm_csrs.i), line:3:24, endln:3:25 + |vpiName:keymgr_data_i.strb[i] |vpiLhs: \_indexed_part_select: kmac_mask_o (work@dm_csrs.kmac_mask_o), line:3:10, endln:3:29 |vpiParent: @@ -744,7 +744,6 @@ design: (work@dm_csrs) \_hier_path: (keymgr_key_i.key[0][1 * 32+:32]), line:4:14, endln:4:47 |vpiParent: \_cont_assign: , line:4:10, endln:4:47 - |vpiName:keymgr_key_i.key[0][1 * 32+:32] |vpiActual: \_ref_obj: (keymgr_key_i), line:4:14, endln:4:26 |vpiParent: @@ -775,6 +774,7 @@ design: (work@dm_csrs) |vpiConstType:7 |vpiWidthExpr: \_constant: , line:4:44, endln:4:46 + |vpiName:keymgr_key_i.key[0][1 * 32+:32] |vpiLhs: \_ref_obj: (work@dm_csrs.o), line:4:10, endln:4:11 |vpiParent: @@ -793,7 +793,6 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:5:10, endln:5:24 |vpiParent: \_cont_assign: , line:5:10, endln:5:39 - |vpiName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_bit_select: (sram_otp_key_o[2 - 2]), line:5:10, endln:5:24 |vpiParent: @@ -812,6 +811,7 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:5:10, endln:5:24 |vpiName:nonce |vpiFullName:sram_otp_key_o[2 - 2].nonce + |vpiName:sram_otp_key_o[2 - 2].nonce \_weaklyReferenced: \_logic_typespec: , line:6:3, endln:6:8 |vpiParent: @@ -830,7 +830,6 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:5:10, endln:5:24 |vpiParent: \_cont_assign: , line:5:10, endln:5:39 - |vpiName:sram_otp_key_o[2 - 2].nonce |vpiActual: \_bit_select: (sram_otp_key_o[2 - 2]), line:5:10, endln:5:24 |vpiParent: @@ -864,6 +863,7 @@ design: (work@dm_csrs) \_hier_path: (sram_otp_key_o[2 - 2].nonce), line:5:10, endln:5:24 |vpiName:nonce |vpiFullName:sram_otp_key_o[2 - 2].nonce + |vpiName:sram_otp_key_o[2 - 2].nonce =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/HierPathBeginBlock/HierPathBeginBlock.log b/tests/HierPathBeginBlock/HierPathBeginBlock.log index 7b3d54c2ae..6af0ab8883 100644 --- a/tests/HierPathBeginBlock/HierPathBeginBlock.log +++ b/tests/HierPathBeginBlock/HierPathBeginBlock.log @@ -297,8 +297,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 -assignment 4 +assignment 8 begin 2 constant 34 cont_assign 10 @@ -320,8 +319,7 @@ ref_typespec 18 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 -assignment 8 +assignment 12 begin 3 constant 34 cont_assign 14 @@ -525,7 +523,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk1.x), line:10:16, endln:10:22 |vpiParent: \_assignment: , line:10:9, endln:10:22 - |vpiName:blk1.x |vpiActual: \_ref_obj: (blk1), line:10:16, endln:10:20 |vpiParent: @@ -539,6 +536,7 @@ design: (work@matching_end_labels_top) \_hier_path: (blk1.x), line:10:16, endln:10:22 |vpiName:x |vpiFullName:work@matching_end_labels_top.x + |vpiName:blk1.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.out1), line:10:9, endln:10:13 |vpiParent: @@ -597,7 +595,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk2.x), line:16:16, endln:16:22 |vpiParent: \_assignment: , line:16:9, endln:16:22 - |vpiName:blk2.x |vpiActual: \_ref_obj: (blk2), line:16:16, endln:16:20 |vpiParent: @@ -611,6 +608,7 @@ design: (work@matching_end_labels_top) \_hier_path: (blk2.x), line:16:16, endln:16:22 |vpiName:x |vpiFullName:work@matching_end_labels_top.x + |vpiName:blk2.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.out2), line:16:9, endln:16:13 |vpiParent: @@ -655,13 +653,15 @@ design: (work@matching_end_labels_top) |vpiName:blk3 |vpiFullName:work@matching_end_labels_top.blk3 |vpiStmt: - \_assign_stmt: , line:22:17, endln:22:18 + \_assignment: , line:22:17, endln:22:18 |vpiParent: \_named_begin: (work@matching_end_labels_top.blk3) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@matching_end_labels_top.blk3.x), line:22:17, endln:22:18 |vpiParent: - \_assign_stmt: , line:22:17, endln:22:18 + \_assignment: , line:22:17, endln:22:18 |vpiTypespec: \_ref_typespec: (work@matching_end_labels_top.blk3.x) |vpiParent: @@ -697,7 +697,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk3.x), line:25:23, endln:25:29 |vpiParent: \_cont_assign: , line:25:16, endln:25:29 - |vpiName:blk3.x |vpiActual: \_ref_obj: (blk3), line:25:23, endln:25:27 |vpiParent: @@ -711,6 +710,7 @@ design: (work@matching_end_labels_top) \_hier_path: (blk3.x), line:25:23, endln:25:29 |vpiName:x |vpiFullName:work@matching_end_labels_top.x + |vpiName:blk3.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.out3), line:25:16, endln:25:20 |vpiParent: @@ -736,13 +736,15 @@ design: (work@matching_end_labels_top) |vpiName:blk4 |vpiFullName:work@matching_end_labels_top.blk4 |vpiStmt: - \_assign_stmt: , line:27:17, endln:27:18 + \_assignment: , line:27:17, endln:27:18 |vpiParent: \_named_begin: (work@matching_end_labels_top.blk4) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@matching_end_labels_top.blk4.x), line:27:17, endln:27:18 |vpiParent: - \_assign_stmt: , line:27:17, endln:27:18 + \_assignment: , line:27:17, endln:27:18 |vpiTypespec: \_ref_typespec: (work@matching_end_labels_top.blk4.x) |vpiParent: @@ -778,7 +780,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk4.x), line:30:23, endln:30:29 |vpiParent: \_cont_assign: , line:30:16, endln:30:29 - |vpiName:blk4.x |vpiActual: \_ref_obj: (blk4), line:30:23, endln:30:27 |vpiParent: @@ -792,6 +793,7 @@ design: (work@matching_end_labels_top) \_hier_path: (blk4.x), line:30:23, endln:30:29 |vpiName:x |vpiFullName:work@matching_end_labels_top.x + |vpiName:blk4.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.out4), line:30:16, endln:30:20 |vpiParent: @@ -1006,7 +1008,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk1.x), line:10:16, endln:10:22 |vpiParent: \_assignment: , line:10:9, endln:10:22 - |vpiName:blk1.x |vpiActual: \_ref_obj: (blk1), line:10:16, endln:10:20 |vpiParent: @@ -1022,6 +1023,7 @@ design: (work@matching_end_labels_top) |vpiFullName:work@matching_end_labels_top.x |vpiActual: \_logic_var: (work@matching_end_labels_top.blk1.x), line:7:17, endln:7:18 + |vpiName:blk1.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.out1), line:10:9, endln:10:13 |vpiParent: @@ -1076,7 +1078,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk2.x), line:16:16, endln:16:22 |vpiParent: \_assignment: , line:16:9, endln:16:22 - |vpiName:blk2.x |vpiActual: \_ref_obj: (blk2), line:16:16, endln:16:20 |vpiParent: @@ -1092,6 +1093,7 @@ design: (work@matching_end_labels_top) |vpiFullName:work@matching_end_labels_top.x |vpiActual: \_logic_var: (work@matching_end_labels_top.blk2.x), line:13:17, endln:13:18 + |vpiName:blk2.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.out2), line:16:9, endln:16:13 |vpiParent: @@ -1119,7 +1121,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk3.x), line:25:23, endln:25:29 |vpiParent: \_cont_assign: , line:25:16, endln:25:29 - |vpiName:blk3.x |vpiActual: \_ref_obj: (blk3), line:25:23, endln:25:27 |vpiParent: @@ -1135,6 +1136,7 @@ design: (work@matching_end_labels_top) |vpiFullName:work@matching_end_labels_top.genblk2.x |vpiActual: \_logic_net: (work@matching_end_labels_top.genblk2.blk3.x), line:22:17, endln:22:18 + |vpiName:blk3.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.genblk2.out3), line:25:16, endln:25:20 |vpiParent: @@ -1151,7 +1153,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk4.x), line:30:23, endln:30:29 |vpiParent: \_cont_assign: , line:30:16, endln:30:29 - |vpiName:blk4.x |vpiActual: \_ref_obj: (blk4), line:30:23, endln:30:27 |vpiParent: @@ -1167,6 +1168,7 @@ design: (work@matching_end_labels_top) |vpiFullName:work@matching_end_labels_top.genblk2.x |vpiActual: \_logic_net: (work@matching_end_labels_top.genblk2.blk4.x), line:27:17, endln:27:18 + |vpiName:blk4.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.genblk2.out4), line:30:16, endln:30:20 |vpiParent: @@ -1441,7 +1443,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk3.x), line:25:23, endln:25:29 |vpiParent: \_cont_assign: , line:25:16, endln:25:29 - |vpiName:blk3.x |vpiActual: \_ref_obj: (blk3), line:25:23, endln:25:27 |vpiParent: @@ -1453,6 +1454,7 @@ design: (work@matching_end_labels_top) \_hier_path: (blk3.x), line:25:23, endln:25:29 |vpiName:x |vpiFullName:work@matching_end_labels_top.genblk2.x + |vpiName:blk3.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.genblk2.out3), line:25:16, endln:25:20 |vpiParent: @@ -1469,7 +1471,6 @@ design: (work@matching_end_labels_top) \_hier_path: (blk4.x), line:30:23, endln:30:29 |vpiParent: \_cont_assign: , line:30:16, endln:30:29 - |vpiName:blk4.x |vpiActual: \_ref_obj: (blk4), line:30:23, endln:30:27 |vpiParent: @@ -1481,6 +1482,7 @@ design: (work@matching_end_labels_top) \_hier_path: (blk4.x), line:30:23, endln:30:29 |vpiName:x |vpiFullName:work@matching_end_labels_top.genblk2.x + |vpiName:blk4.x |vpiLhs: \_ref_obj: (work@matching_end_labels_top.genblk2.out4), line:30:16, endln:30:20 |vpiParent: @@ -1531,7 +1533,3 @@ design: (work@matching_end_labels_top) [ ERROR] : 0 [WARNING] : 1 [ NOTE] : 5 - -============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/HierPathBeginBlock/dut.sv | ${SURELOG_DIR}/build/regression/HierPathBeginBlock/roundtrip/dut_000.sv | 17 | 33 | -============================== End RoundTrip Results ============================== diff --git a/tests/HierPathBind/HierPathBind.log b/tests/HierPathBind/HierPathBind.log index 5697462fe0..bdc6a9988b 100644 --- a/tests/HierPathBind/HierPathBind.log +++ b/tests/HierPathBind/HierPathBind.log @@ -305,7 +305,6 @@ design: (work@top) \_hier_path: (alert_rx_i.ping_p), line:14:15, endln:14:32 |vpiParent: \_cont_assign: , line:14:11, endln:14:32 - |vpiName:alert_rx_i.ping_p |vpiActual: \_ref_obj: (alert_rx_i), line:14:15, endln:14:25 |vpiParent: @@ -317,6 +316,7 @@ design: (work@top) \_hier_path: (alert_rx_i.ping_p), line:14:15, endln:14:32 |vpiName:ping_p |vpiFullName:work@top.ping_p + |vpiName:alert_rx_i.ping_p |vpiLhs: \_ref_obj: (work@top.o), line:14:11, endln:14:12 |vpiParent: @@ -342,7 +342,6 @@ design: (work@top) \_hier_path: (alert_rx_i.ping_p), line:12:13, endln:12:30 |vpiParent: \_port: (o), line:12:10, endln:12:31 - |vpiName:alert_rx_i.ping_p |vpiActual: \_ref_obj: (alert_rx_i), line:12:13, endln:12:23 |vpiParent: @@ -354,6 +353,7 @@ design: (work@top) \_hier_path: (alert_rx_i.ping_p), line:12:13, endln:12:30 |vpiName:ping_p |vpiFullName:work@top.d.o.ping_p + |vpiName:alert_rx_i.ping_p |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathBind/dut.sv, line:5:1, endln:15:10 |vpiName:work@top @@ -454,9 +454,6 @@ design: (work@top) |vpiFullName:work@top.d.o.alert_rx_i.ping_p |vpiActual: \_struct_typespec: (alert_rx_t), line:6:12, endln:8:5 - |vpiName:alert_rx_i.ping_p - |vpiExpr: - \_struct_net: (work@top.alert_rx_i), line:10:16, endln:10:26 |vpiActual: \_ref_obj: (alert_rx_i), line:12:13, endln:12:23 |vpiParent: @@ -474,6 +471,7 @@ design: (work@top) \_typespec_member: (ping_p), line:7:16, endln:7:22 |vpiExpr: \_struct_net: (work@top.alert_rx_i), line:10:16, endln:10:26 + |vpiName:alert_rx_i.ping_p |vpiLowConn: \_ref_obj: (work@top.d.o), line:12:11, endln:12:12 |vpiParent: @@ -513,7 +511,6 @@ design: (work@top) \_hier_path: (alert_rx_i.ping_p), line:14:15, endln:14:32 |vpiParent: \_cont_assign: , line:14:11, endln:14:32 - |vpiName:alert_rx_i.ping_p |vpiActual: \_ref_obj: (alert_rx_i), line:14:15, endln:14:25 |vpiParent: @@ -529,6 +526,7 @@ design: (work@top) |vpiFullName:work@top.ping_p |vpiActual: \_typespec_member: (ping_p), line:7:16, endln:7:22 + |vpiName:alert_rx_i.ping_p |vpiLhs: \_ref_obj: (work@top.o), line:14:11, endln:14:12 |vpiParent: diff --git a/tests/HierPathCont/HierPathCont.log b/tests/HierPathCont/HierPathCont.log index 2dc09f5fa2..bb0fa2be94 100644 --- a/tests/HierPathCont/HierPathCont.log +++ b/tests/HierPathCont/HierPathCont.log @@ -395,7 +395,6 @@ design: (work@unsized_single_bit_1) \_hier_path: (out3.a), line:17:10, endln:17:16 |vpiParent: \_cont_assign: , line:17:10, endln:17:21 - |vpiName:out3.a |vpiActual: \_ref_obj: (out3), line:17:15, endln:17:16 |vpiParent: @@ -406,6 +405,7 @@ design: (work@unsized_single_bit_1) |vpiParent: \_hier_path: (out3.a), line:17:10, endln:17:16 |vpiName:a + |vpiName:out3.a |vpiContAssign: \_cont_assign: , line:20:10, endln:20:31 |vpiParent: @@ -685,7 +685,6 @@ design: (work@unsized_single_bit_1) \_hier_path: (out3.a), line:17:10, endln:17:16 |vpiParent: \_cont_assign: , line:17:10, endln:17:21 - |vpiName:out3.a |vpiActual: \_ref_obj: (out3), line:17:15, endln:17:16 |vpiParent: @@ -700,6 +699,7 @@ design: (work@unsized_single_bit_1) |vpiName:a |vpiActual: \_typespec_member: (a), line:1:36, endln:1:37 + |vpiName:out3.a |vpiContAssign: \_cont_assign: , line:20:10, endln:20:31 |vpiParent: @@ -873,7 +873,6 @@ design: (work@unsized_single_bit_1) \_hier_path: (out3.a), line:17:10, endln:17:16 |vpiParent: \_cont_assign: , line:17:10, endln:17:21 - |vpiName:out3.a |vpiActual: \_ref_obj: (out3), line:17:15, endln:17:16 |vpiParent: @@ -884,6 +883,7 @@ design: (work@unsized_single_bit_1) |vpiParent: \_hier_path: (out3.a), line:17:10, endln:17:16 |vpiName:a + |vpiName:out3.a =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/HierPathInterfBlock/HierPathInterfBlock.log b/tests/HierPathInterfBlock/HierPathInterfBlock.log index b45ba9918c..90c90a66fc 100644 --- a/tests/HierPathInterfBlock/HierPathInterfBlock.log +++ b/tests/HierPathInterfBlock/HierPathInterfBlock.log @@ -468,7 +468,6 @@ design: (work@top) \_hier_path: (blk.f), line:24:18, endln:24:25 |vpiParent: \_sys_func_call: ($display), line:24:9, endln:24:26 - |vpiName:blk.f |vpiActual: \_ref_obj: (blk), line:24:18, endln:24:21 |vpiParent: @@ -479,6 +478,7 @@ design: (work@top) |vpiParent: \_hier_path: (blk.f), line:24:18, endln:24:25 |vpiName:f + |vpiName:blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:25:9, endln:25:24 @@ -488,7 +488,6 @@ design: (work@top) \_hier_path: (i.f), line:25:18, endln:25:23 |vpiParent: \_sys_func_call: ($display), line:25:9, endln:25:24 - |vpiName:i.f |vpiActual: \_ref_obj: (i), line:25:18, endln:25:19 |vpiParent: @@ -499,6 +498,7 @@ design: (work@top) |vpiParent: \_hier_path: (i.f), line:25:18, endln:25:23 |vpiName:f + |vpiName:i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:26:9, endln:26:28 @@ -508,7 +508,6 @@ design: (work@top) \_hier_path: (i.blk.f), line:26:18, endln:26:27 |vpiParent: \_sys_func_call: ($display), line:26:9, endln:26:28 - |vpiName:i.blk.f |vpiActual: \_ref_obj: (i), line:26:18, endln:26:19 |vpiParent: @@ -524,6 +523,7 @@ design: (work@top) |vpiParent: \_hier_path: (i.blk.f), line:26:18, endln:26:27 |vpiName:f + |vpiName:i.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:27:9, endln:27:26 @@ -533,7 +533,6 @@ design: (work@top) \_hier_path: (top.f), line:27:18, endln:27:25 |vpiParent: \_sys_func_call: ($display), line:27:9, endln:27:26 - |vpiName:top.f |vpiActual: \_ref_obj: (top), line:27:18, endln:27:21 |vpiParent: @@ -544,6 +543,7 @@ design: (work@top) |vpiParent: \_hier_path: (top.f), line:27:18, endln:27:25 |vpiName:f + |vpiName:top.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:28:9, endln:28:30 @@ -553,7 +553,6 @@ design: (work@top) \_hier_path: (top.blk.f), line:28:18, endln:28:29 |vpiParent: \_sys_func_call: ($display), line:28:9, endln:28:30 - |vpiName:top.blk.f |vpiActual: \_ref_obj: (top), line:28:18, endln:28:21 |vpiParent: @@ -569,6 +568,7 @@ design: (work@top) |vpiParent: \_hier_path: (top.blk.f), line:28:18, endln:28:29 |vpiName:f + |vpiName:top.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:29:9, endln:29:28 @@ -578,7 +578,6 @@ design: (work@top) \_hier_path: (top.i.f), line:29:18, endln:29:27 |vpiParent: \_sys_func_call: ($display), line:29:9, endln:29:28 - |vpiName:top.i.f |vpiActual: \_ref_obj: (top), line:29:18, endln:29:21 |vpiParent: @@ -594,6 +593,7 @@ design: (work@top) |vpiParent: \_hier_path: (top.i.f), line:29:18, endln:29:27 |vpiName:f + |vpiName:top.i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:30:9, endln:30:32 @@ -603,7 +603,6 @@ design: (work@top) \_hier_path: (top.i.blk.f), line:30:18, endln:30:31 |vpiParent: \_sys_func_call: ($display), line:30:9, endln:30:32 - |vpiName:top.i.blk.f |vpiActual: \_ref_obj: (top), line:30:18, endln:30:21 |vpiParent: @@ -624,6 +623,7 @@ design: (work@top) |vpiParent: \_hier_path: (top.i.blk.f), line:30:18, endln:30:31 |vpiName:f + |vpiName:top.i.blk.f |vpiName:$display |vpiRefModule: \_ref_module: work@intf (i), line:13:10, endln:13:11 @@ -759,7 +759,6 @@ design: (work@top) \_hier_path: (blk.f), line:24:18, endln:24:25 |vpiParent: \_sys_func_call: ($display), line:24:9, endln:24:26 - |vpiName:blk.f |vpiActual: \_ref_obj: (blk), line:24:18, endln:24:21 |vpiParent: @@ -774,6 +773,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:25:9, endln:25:24 @@ -783,7 +783,6 @@ design: (work@top) \_hier_path: (i.f), line:25:18, endln:25:23 |vpiParent: \_sys_func_call: ($display), line:25:9, endln:25:24 - |vpiName:i.f |vpiActual: \_ref_obj: (i), line:25:18, endln:25:19 |vpiParent: @@ -798,6 +797,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:26:9, endln:26:28 @@ -807,7 +807,6 @@ design: (work@top) \_hier_path: (i.blk.f), line:26:18, endln:26:27 |vpiParent: \_sys_func_call: ($display), line:26:9, endln:26:28 - |vpiName:i.blk.f |vpiActual: \_ref_obj: (i), line:26:18, endln:26:19 |vpiParent: @@ -829,6 +828,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:i.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:27:9, endln:27:26 @@ -838,7 +838,6 @@ design: (work@top) \_hier_path: (top.f), line:27:18, endln:27:25 |vpiParent: \_sys_func_call: ($display), line:27:9, endln:27:26 - |vpiName:top.f |vpiActual: \_ref_obj: (top), line:27:18, endln:27:21 |vpiParent: @@ -853,6 +852,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:top.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:28:9, endln:28:30 @@ -862,7 +862,6 @@ design: (work@top) \_hier_path: (top.blk.f), line:28:18, endln:28:29 |vpiParent: \_sys_func_call: ($display), line:28:9, endln:28:30 - |vpiName:top.blk.f |vpiActual: \_ref_obj: (top), line:28:18, endln:28:21 |vpiParent: @@ -884,6 +883,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:top.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:29:9, endln:29:28 @@ -893,7 +893,6 @@ design: (work@top) \_hier_path: (top.i.f), line:29:18, endln:29:27 |vpiParent: \_sys_func_call: ($display), line:29:9, endln:29:28 - |vpiName:top.i.f |vpiActual: \_ref_obj: (top), line:29:18, endln:29:21 |vpiParent: @@ -915,6 +914,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:top.i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:30:9, endln:30:32 @@ -924,7 +924,6 @@ design: (work@top) \_hier_path: (top.i.blk.f), line:30:18, endln:30:31 |vpiParent: \_sys_func_call: ($display), line:30:9, endln:30:32 - |vpiName:top.i.blk.f |vpiActual: \_ref_obj: (top), line:30:18, endln:30:21 |vpiParent: @@ -953,6 +952,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@intf.f), line:2:5, endln:4:16 + |vpiName:top.i.blk.f |vpiName:$display |vpiGenScopeArray: \_gen_scope_array: (work@top.blk), line:17:12, endln:21:8 diff --git a/tests/HierPathLhs/HierPathLhs.log b/tests/HierPathLhs/HierPathLhs.log index 8be0358108..fe94cb0fcf 100644 --- a/tests/HierPathLhs/HierPathLhs.log +++ b/tests/HierPathLhs/HierPathLhs.log @@ -164,7 +164,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 9 constant 32 cont_assign 5 @@ -193,7 +193,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 13 constant 32 cont_assign 7 @@ -247,7 +247,7 @@ design: (work@alert_handler_reg_wrap) |vpiParent: \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 |vpiForInitStmt: - \_assign_stmt: , line:2:8, endln:2:20 + \_assignment: , line:2:8, endln:2:20 |vpiParent: \_gen_for: |vpiRhs: @@ -259,7 +259,7 @@ design: (work@alert_handler_reg_wrap) |vpiLhs: \_int_var: (work@alert_handler_reg_wrap.k), line:2:15, endln:2:16 |vpiParent: - \_assign_stmt: , line:2:8, endln:2:20 + \_assignment: , line:2:8, endln:2:20 |vpiTypespec: \_ref_typespec: (work@alert_handler_reg_wrap.k) |vpiParent: @@ -325,7 +325,6 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiParent: \_cont_assign: , line:3:12, endln:3:43 - |vpiName:hw2reg.alert_cause[k].d |vpiActual: \_ref_obj: (hw2reg), line:3:19, endln:3:30 |vpiParent: @@ -348,6 +347,7 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiName:d |vpiFullName:alert_cause[k].d + |vpiName:hw2reg.alert_cause[k].d |uhdmallModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiParent: @@ -408,7 +408,6 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (a[0][0].x[0]), line:15:10, endln:15:11 |vpiParent: \_cont_assign: , line:15:10, endln:15:26 - |vpiName:a[0][0].x[0] |vpiActual: \_bit_select: (a[0]), line:15:10, endln:15:11 |vpiParent: @@ -446,6 +445,7 @@ design: (work@alert_handler_reg_wrap) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:a[0][0].x[0] |uhdmtopModules: \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:1:1, endln:5:10 |vpiName:work@alert_handler_reg_wrap @@ -494,7 +494,6 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiParent: \_cont_assign: , line:3:12, endln:3:43 - |vpiName:hw2reg.alert_cause[k].d |vpiActual: \_ref_obj: (hw2reg), line:3:19, endln:3:30 |vpiParent: @@ -520,6 +519,7 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiName:d |vpiFullName:alert_cause[k].d + |vpiName:hw2reg.alert_cause[k].d |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/HierPathLhs/dut.sv, line:8:1, endln:16:10 |vpiName:work@top @@ -597,7 +597,6 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (a[0][0].x[0]), line:15:10, endln:15:11 |vpiParent: \_cont_assign: , line:15:10, endln:15:26 - |vpiName:a[0][0].x[0] |vpiActual: \_bit_select: (a[0]), line:15:10, endln:15:11 |vpiParent: @@ -643,13 +642,14 @@ design: (work@alert_handler_reg_wrap) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:a[0][0].x[0] \_weaklyReferenced: \_hier_path: (alert_cause[k].d), line:3:19, endln:3:30 - |vpiName:alert_cause[k].d |vpiActual: \_bit_select: (alert_cause[k]), line:3:19, endln:3:30 |vpiActual: \_ref_obj: (alert_cause[k].d), line:3:37, endln:3:37 + |vpiName:alert_cause[k].d \_int_typespec: , line:10:5, endln:10:8 |vpiParent: \_typespec_member: (x), line:10:9, endln:10:10 @@ -710,7 +710,6 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiParent: \_cont_assign: , line:3:12, endln:3:43 - |vpiName:hw2reg.alert_cause[k].d |vpiActual: \_ref_obj: (hw2reg), line:3:19, endln:3:30 |vpiParent: @@ -734,6 +733,7 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (hw2reg.alert_cause[k].d), line:3:12, endln:3:35 |vpiName:d |vpiFullName:alert_cause[k].d + |vpiName:hw2reg.alert_cause[k].d \_gen_scope: (work@alert_handler_reg_wrap.gen_alert_cause[0]), line:2:34, endln:4:6 |vpiParent: \_gen_scope_array: (work@alert_handler_reg_wrap.gen_alert_cause[0]), line:2:34, endln:4:6 @@ -760,7 +760,6 @@ design: (work@alert_handler_reg_wrap) \_hier_path: (a[0][0].x[0]), line:15:10, endln:15:11 |vpiParent: \_cont_assign: , line:15:10, endln:15:26 - |vpiName:a[0][0].x[0] |vpiActual: \_bit_select: (a[0]), line:15:10, endln:15:11 |vpiParent: @@ -786,6 +785,7 @@ design: (work@alert_handler_reg_wrap) |vpiFullName:a[0][0].x[0] |vpiIndex: \_constant: , line:15:20, endln:15:21 + |vpiName:a[0][0].x[0] =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/HierPathModule/HierPathModule.log b/tests/HierPathModule/HierPathModule.log index 3d7c236cd1..b61c19f6c5 100644 --- a/tests/HierPathModule/HierPathModule.log +++ b/tests/HierPathModule/HierPathModule.log @@ -148,7 +148,6 @@ design: (work@top) \_hier_path: (medium.c), line:3:14, endln:3:22 |vpiParent: \_cont_assign: , line:3:10, endln:3:22 - |vpiName:medium.c |vpiActual: \_ref_obj: (medium), line:3:14, endln:3:20 |vpiParent: @@ -160,6 +159,7 @@ design: (work@top) \_hier_path: (medium.c), line:3:14, endln:3:22 |vpiName:c |vpiFullName:work@bottom.c + |vpiName:medium.c |vpiLhs: \_ref_obj: (work@bottom.o), line:3:10, endln:3:11 |vpiParent: @@ -260,7 +260,6 @@ design: (work@top) \_hier_path: (medium.c), line:3:14, endln:3:22 |vpiParent: \_cont_assign: , line:3:10, endln:3:22 - |vpiName:medium.c |vpiActual: \_ref_obj: (medium), line:3:14, endln:3:20 |vpiParent: @@ -276,6 +275,7 @@ design: (work@top) |vpiFullName:work@top.u1.b1.c |vpiActual: \_logic_net: (work@top.u1.c), line:7:8, endln:7:9 + |vpiName:medium.c |vpiLhs: \_ref_obj: (work@top.u1.b1.o), line:3:10, endln:3:11 |vpiParent: diff --git a/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log b/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log index f8e4af0e0c..544978e80c 100644 --- a/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log +++ b/tests/HierPathPackedArrayNet/HierPathPackedArrayNet.log @@ -215,7 +215,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 1 +assignment 1 begin 3 bit_select 1 constant 36 @@ -246,7 +246,7 @@ typespec_member 2 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 2 +assignment 2 begin 6 bit_select 2 constant 36 @@ -599,13 +599,13 @@ design: (work@rvfi_tracer) \_begin: (work@rvfi_tracer), line:16:28, endln:21:4 |vpiFullName:work@rvfi_tracer |vpiForInitStmt: - \_assign_stmt: , line:17:8, endln:17:17 + \_assignment: , line:17:8, endln:17:17 |vpiParent: \_for_stmt: (work@rvfi_tracer), line:17:3, endln:17:6 |vpiRhs: \_constant: , line:17:16, endln:17:17 |vpiParent: - \_assign_stmt: , line:17:8, endln:17:17 + \_assignment: , line:17:8, endln:17:17 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -613,7 +613,7 @@ design: (work@rvfi_tracer) |vpiLhs: \_int_var: (work@rvfi_tracer.i), line:17:12, endln:17:13 |vpiParent: - \_assign_stmt: , line:17:8, endln:17:17 + \_assignment: , line:17:8, endln:17:17 |vpiTypespec: \_ref_typespec: (work@rvfi_tracer.i) |vpiParent: @@ -669,7 +669,6 @@ design: (work@rvfi_tracer) \_hier_path: (rvfi_i[i].trap), line:18:9, endln:18:23 |vpiParent: \_begin: (work@rvfi_tracer), line:17:45, endln:20:6 - |vpiName:rvfi_i[i].trap |vpiActual: \_bit_select: (rvfi_i[i]), line:18:9, endln:18:15 |vpiParent: @@ -690,6 +689,7 @@ design: (work@rvfi_tracer) \_hier_path: (rvfi_i[i].trap), line:18:9, endln:18:23 |vpiName:trap |vpiFullName:work@rvfi_tracer.trap + |vpiName:rvfi_i[i].trap |vpiStmt: \_begin: (work@rvfi_tracer), line:18:25, endln:19:8 |vpiParent: @@ -832,7 +832,7 @@ design: (work@rvfi_tracer) \_begin: (work@rvfi_tracer), line:16:28, endln:21:4 |vpiFullName:work@rvfi_tracer |vpiForInitStmt: - \_assign_stmt: , line:17:8, endln:17:17 + \_assignment: , line:17:8, endln:17:17 |vpiParent: \_for_stmt: (work@rvfi_tracer), line:17:3, endln:17:6 |vpiRhs: @@ -840,7 +840,7 @@ design: (work@rvfi_tracer) |vpiLhs: \_int_var: (work@rvfi_tracer.i), line:17:12, endln:17:13 |vpiParent: - \_assign_stmt: , line:17:8, endln:17:17 + \_assignment: , line:17:8, endln:17:17 |vpiTypespec: \_ref_typespec: (work@rvfi_tracer.i) |vpiParent: @@ -898,7 +898,6 @@ design: (work@rvfi_tracer) \_hier_path: (rvfi_i[i].trap), line:18:9, endln:18:23 |vpiParent: \_if_stmt: , line:18:5, endln:19:8 - |vpiName:rvfi_i[i].trap |vpiActual: \_bit_select: (work@rvfi_tracer.rvfi_i), line:18:9, endln:18:15 |vpiParent: @@ -923,6 +922,7 @@ design: (work@rvfi_tracer) |vpiFullName:work@rvfi_tracer.trap |vpiActual: \_typespec_member: (trap), line:6:36, endln:6:40 + |vpiName:rvfi_i[i].trap |vpiStmt: \_begin: (work@rvfi_tracer), line:18:25, endln:19:8 |vpiParent: diff --git a/tests/HierPathPackedVar/HierPathPackedVar.log b/tests/HierPathPackedVar/HierPathPackedVar.log index 99d2472eb9..e43ccdb9d9 100644 --- a/tests/HierPathPackedVar/HierPathPackedVar.log +++ b/tests/HierPathPackedVar/HierPathPackedVar.log @@ -808,7 +808,6 @@ design: (work@axi_adapter_arbiter) \_hier_path: (req_i[i].req), line:22:12, endln:22:24 |vpiParent: \_operation: , line:22:12, endln:22:32 - |vpiName:req_i[i].req |vpiActual: \_bit_select: (req_i[i]), line:22:12, endln:22:17 |vpiParent: @@ -829,6 +828,7 @@ design: (work@axi_adapter_arbiter) \_hier_path: (req_i[i].req), line:22:12, endln:22:24 |vpiName:req |vpiFullName:work@axi_adapter_arbiter.req + |vpiName:req_i[i].req |vpiOperand: \_constant: , line:22:28, endln:22:32 |vpiParent: @@ -1013,7 +1013,6 @@ design: (work@axi_adapter_arbiter) \_hier_path: (req_i[i].req), line:22:12, endln:22:24 |vpiParent: \_operation: , line:22:12, endln:22:32 - |vpiName:req_i[i].req |vpiActual: \_bit_select: (req_i[i]), line:22:12, endln:22:17 |vpiParent: @@ -1038,6 +1037,7 @@ design: (work@axi_adapter_arbiter) |vpiFullName:work@axi_adapter_arbiter.req |vpiActual: \_typespec_member: (req), line:3:26, endln:3:29 + |vpiName:req_i[i].req |vpiOperand: \_constant: , line:22:28, endln:22:32 |vpiStmt: diff --git a/tests/HierPathSelect/HierPathSelect.log b/tests/HierPathSelect/HierPathSelect.log index ffebbdac4f..f3b9448f37 100644 --- a/tests/HierPathSelect/HierPathSelect.log +++ b/tests/HierPathSelect/HierPathSelect.log @@ -179,7 +179,6 @@ design: (work@dut2) \_hier_path: (read_buf.q[1]), line:8:8, endln:8:21 |vpiParent: \_cont_assign: , line:8:8, endln:8:28 - |vpiName:read_buf.q[1] |vpiActual: \_ref_obj: (read_buf), line:8:17, endln:8:18 |vpiParent: @@ -199,6 +198,7 @@ design: (work@dut2) |vpiSize:64 |UINT:1 |vpiConstType:9 + |vpiName:read_buf.q[1] |uhdmtopModules: \_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/HierPathSelect/dut.sv, line:1:1, endln:10:10 |vpiName:work@dut2 @@ -230,7 +230,6 @@ design: (work@dut2) \_hier_path: (read_buf.q[1]), line:8:8, endln:8:21 |vpiParent: \_cont_assign: , line:8:8, endln:8:28 - |vpiName:read_buf.q[1] |vpiActual: \_ref_obj: (read_buf), line:8:17, endln:8:18 |vpiParent: @@ -254,6 +253,7 @@ design: (work@dut2) |vpiSize:64 |UINT:1 |vpiConstType:9 + |vpiName:read_buf.q[1] \_weaklyReferenced: \_logic_typespec: , line:4:3, endln:4:14 |vpiParent: @@ -287,7 +287,6 @@ design: (work@dut2) \_hier_path: (read_buf.q[1]), line:8:8, endln:8:21 |vpiParent: \_cont_assign: , line:8:8, endln:8:28 - |vpiName:read_buf.q[1] |vpiActual: \_ref_obj: (read_buf), line:8:17, endln:8:18 |vpiParent: @@ -301,6 +300,7 @@ design: (work@dut2) |vpiFullName:work@dut2.read_buf.q[1].q |vpiIndex: \_constant: , line:8:19, endln:8:20 + |vpiName:read_buf.q[1] =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/HierPathStruct/HierPathStruct.log b/tests/HierPathStruct/HierPathStruct.log index bb6ca51936..04189b4cac 100644 --- a/tests/HierPathStruct/HierPathStruct.log +++ b/tests/HierPathStruct/HierPathStruct.log @@ -344,7 +344,6 @@ design: (work@dut) \_hier_path: (hw2reg.data_in.de), line:17:8, endln:17:25 |vpiParent: \_cont_assign: , line:17:8, endln:17:32 - |vpiName:hw2reg.data_in.de |vpiActual: \_ref_obj: (hw2reg), line:17:15, endln:17:22 |vpiParent: @@ -360,6 +359,7 @@ design: (work@dut) |vpiParent: \_hier_path: (hw2reg.data_in.de), line:17:8, endln:17:25 |vpiName:de + |vpiName:hw2reg.data_in.de |uhdmtopModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/HierPathStruct/dut.sv, line:13:1, endln:19:10 |vpiName:work@dut @@ -395,7 +395,6 @@ design: (work@dut) \_hier_path: (hw2reg.data_in.de), line:17:8, endln:17:25 |vpiParent: \_cont_assign: , line:17:8, endln:17:32 - |vpiName:hw2reg.data_in.de |vpiActual: \_ref_obj: (hw2reg), line:17:15, endln:17:22 |vpiParent: @@ -417,6 +416,7 @@ design: (work@dut) |vpiName:de |vpiActual: \_typespec_member: (de), line:4:18, endln:4:20 + |vpiName:hw2reg.data_in.de \_weaklyReferenced: \_logic_typespec: , line:3:5, endln:3:17 |vpiParent: @@ -487,7 +487,6 @@ design: (work@dut) \_hier_path: (hw2reg.data_in.de), line:17:8, endln:17:25 |vpiParent: \_cont_assign: , line:17:8, endln:17:32 - |vpiName:hw2reg.data_in.de |vpiActual: \_ref_obj: (hw2reg), line:17:15, endln:17:22 |vpiParent: @@ -503,6 +502,7 @@ design: (work@dut) |vpiParent: \_hier_path: (hw2reg.data_in.de), line:17:8, endln:17:25 |vpiName:de + |vpiName:hw2reg.data_in.de =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/HierPathStructTypespec/HierPathStructTypespec.log b/tests/HierPathStructTypespec/HierPathStructTypespec.log index 34766a846d..3190d2aa4f 100644 --- a/tests/HierPathStructTypespec/HierPathStructTypespec.log +++ b/tests/HierPathStructTypespec/HierPathStructTypespec.log @@ -1849,7 +1849,6 @@ design: (work@top) \_hier_path: (hw2reg.status.fifo_depth.d), line:37:11, endln:37:37 |vpiParent: \_sys_func_call: ($bits), line:37:5, endln:37:38 - |vpiName:hw2reg.status.fifo_depth.d |vpiActual: \_ref_obj: (hw2reg), line:37:11, endln:37:17 |vpiParent: @@ -1871,6 +1870,7 @@ design: (work@top) \_hier_path: (hw2reg.status.fifo_depth.d), line:37:11, endln:37:37 |vpiName:d |vpiFullName:work@top.d + |vpiName:hw2reg.status.fifo_depth.d |vpiName:$bits |vpiOperand: \_operation: , line:37:42, endln:37:57 diff --git a/tests/HierPathTfArg/HierPathTfArg.log b/tests/HierPathTfArg/HierPathTfArg.log index 05fff78a8d..d25e84f9de 100644 --- a/tests/HierPathTfArg/HierPathTfArg.log +++ b/tests/HierPathTfArg/HierPathTfArg.log @@ -514,7 +514,6 @@ design: (work@top) \_hier_path: (blk.f), line:28:18, endln:28:26 |vpiParent: \_sys_func_call: ($display), line:28:9, endln:28:27 - |vpiName:blk.f |vpiActual: \_ref_obj: (blk), line:28:18, endln:28:21 |vpiParent: @@ -533,6 +532,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f + |vpiName:blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:29:9, endln:29:25 @@ -542,7 +542,6 @@ design: (work@top) \_hier_path: (i.f), line:29:18, endln:29:24 |vpiParent: \_sys_func_call: ($display), line:29:9, endln:29:25 - |vpiName:i.f |vpiActual: \_ref_obj: (i), line:29:18, endln:29:19 |vpiParent: @@ -561,6 +560,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f + |vpiName:i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:30:9, endln:30:29 @@ -570,7 +570,6 @@ design: (work@top) \_hier_path: (i.blk.f), line:30:18, endln:30:28 |vpiParent: \_sys_func_call: ($display), line:30:9, endln:30:29 - |vpiName:i.blk.f |vpiActual: \_ref_obj: (i), line:30:18, endln:30:19 |vpiParent: @@ -594,6 +593,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f + |vpiName:i.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:31:9, endln:31:28 @@ -603,7 +603,6 @@ design: (work@top) \_hier_path: (top.f3), line:31:18, endln:31:27 |vpiParent: \_sys_func_call: ($display), line:31:9, endln:31:28 - |vpiName:top.f3 |vpiActual: \_ref_obj: (top), line:31:18, endln:31:21 |vpiParent: @@ -622,6 +621,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f3 + |vpiName:top.f3 |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:32:9, endln:32:31 @@ -631,7 +631,6 @@ design: (work@top) \_hier_path: (top.blk.f), line:32:18, endln:32:30 |vpiParent: \_sys_func_call: ($display), line:32:9, endln:32:31 - |vpiName:top.blk.f |vpiActual: \_ref_obj: (top), line:32:18, endln:32:21 |vpiParent: @@ -655,6 +654,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f + |vpiName:top.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:33:9, endln:33:29 @@ -664,7 +664,6 @@ design: (work@top) \_hier_path: (top.i.f), line:33:18, endln:33:28 |vpiParent: \_sys_func_call: ($display), line:33:9, endln:33:29 - |vpiName:top.i.f |vpiActual: \_ref_obj: (top), line:33:18, endln:33:21 |vpiParent: @@ -688,6 +687,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f + |vpiName:top.i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:34:9, endln:34:33 @@ -697,7 +697,6 @@ design: (work@top) \_hier_path: (top.i.blk.f), line:34:18, endln:34:32 |vpiParent: \_sys_func_call: ($display), line:34:9, endln:34:33 - |vpiName:top.i.blk.f |vpiActual: \_ref_obj: (top), line:34:18, endln:34:21 |vpiParent: @@ -726,6 +725,7 @@ design: (work@top) |UINT:0 |vpiConstType:9 |vpiName:f + |vpiName:top.i.blk.f |vpiName:$display |vpiGenStmt: \_gen_region: @@ -841,7 +841,6 @@ design: (work@top) \_hier_path: (blk.f), line:28:18, endln:28:26 |vpiParent: \_sys_func_call: ($display), line:28:9, endln:28:27 - |vpiName:blk.f |vpiActual: \_ref_obj: (blk), line:28:18, endln:28:21 |vpiParent: @@ -858,6 +857,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@top.blk.f), line:20:13, endln:23:24 + |vpiName:blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:29:9, endln:29:25 @@ -867,7 +867,6 @@ design: (work@top) \_hier_path: (i.f), line:29:18, endln:29:24 |vpiParent: \_sys_func_call: ($display), line:29:9, endln:29:25 - |vpiName:i.f |vpiActual: \_ref_obj: (i), line:29:18, endln:29:19 |vpiParent: @@ -884,6 +883,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@top.i.f), line:4:13, endln:7:24 + |vpiName:i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:30:9, endln:30:29 @@ -893,7 +893,6 @@ design: (work@top) \_hier_path: (i.blk.f), line:30:18, endln:30:28 |vpiParent: \_sys_func_call: ($display), line:30:9, endln:30:29 - |vpiName:i.blk.f |vpiActual: \_ref_obj: (i), line:30:18, endln:30:19 |vpiParent: @@ -917,6 +916,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@top.i.blk.f), line:9:17, endln:12:28 + |vpiName:i.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:31:9, endln:31:28 @@ -926,7 +926,6 @@ design: (work@top) \_hier_path: (top.f3), line:31:18, endln:31:27 |vpiParent: \_sys_func_call: ($display), line:31:9, endln:31:28 - |vpiName:top.f3 |vpiActual: \_ref_obj: (top), line:31:18, endln:31:21 |vpiParent: @@ -943,6 +942,7 @@ design: (work@top) |vpiName:f3 |vpiFunction: \_function: (work@top.f3), line:15:9, endln:18:20 + |vpiName:top.f3 |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:32:9, endln:32:31 @@ -952,7 +952,6 @@ design: (work@top) \_hier_path: (top.blk.f), line:32:18, endln:32:30 |vpiParent: \_sys_func_call: ($display), line:32:9, endln:32:31 - |vpiName:top.blk.f |vpiActual: \_ref_obj: (top), line:32:18, endln:32:21 |vpiParent: @@ -976,6 +975,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@top.blk.f), line:20:13, endln:23:24 + |vpiName:top.blk.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:33:9, endln:33:29 @@ -985,7 +985,6 @@ design: (work@top) \_hier_path: (top.i.f), line:33:18, endln:33:28 |vpiParent: \_sys_func_call: ($display), line:33:9, endln:33:29 - |vpiName:top.i.f |vpiActual: \_ref_obj: (top), line:33:18, endln:33:21 |vpiParent: @@ -1009,6 +1008,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@top.i.f), line:4:13, endln:7:24 + |vpiName:top.i.f |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:34:9, endln:34:33 @@ -1018,7 +1018,6 @@ design: (work@top) \_hier_path: (top.i.blk.f), line:34:18, endln:34:32 |vpiParent: \_sys_func_call: ($display), line:34:9, endln:34:33 - |vpiName:top.i.blk.f |vpiActual: \_ref_obj: (top), line:34:18, endln:34:21 |vpiParent: @@ -1049,6 +1048,7 @@ design: (work@top) |vpiName:f |vpiFunction: \_function: (work@top.blk.f), line:20:13, endln:23:24 + |vpiName:top.i.blk.f |vpiName:$display |vpiGenScopeArray: \_gen_scope_array: (work@top.i), line:3:16, endln:14:12 diff --git a/tests/HierPathTypespec/HierPathTypespec.log b/tests/HierPathTypespec/HierPathTypespec.log index 0caa6d4f72..e116ce7555 100644 --- a/tests/HierPathTypespec/HierPathTypespec.log +++ b/tests/HierPathTypespec/HierPathTypespec.log @@ -344,7 +344,6 @@ design: (work@top) \_hier_path: (c[1].x), line:12:11, endln:12:12 |vpiParent: \_cont_assign: , line:12:11, endln:12:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:12:11, endln:12:12 |vpiParent: @@ -363,6 +362,7 @@ design: (work@top) \_hier_path: (c[1].x), line:12:11, endln:12:12 |vpiName:x |vpiFullName:c[1].x + |vpiName:c[1].x |vpiContAssign: \_cont_assign: , line:13:11, endln:13:21 |vpiParent: @@ -371,7 +371,6 @@ design: (work@top) \_hier_path: (c[1].x), line:13:15, endln:13:21 |vpiParent: \_cont_assign: , line:13:11, endln:13:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:13:15, endln:13:16 |vpiParent: @@ -390,6 +389,7 @@ design: (work@top) \_hier_path: (c[1].x), line:13:15, endln:13:21 |vpiName:x |vpiFullName:work@top.x + |vpiName:c[1].x |vpiLhs: \_ref_obj: (work@top.o), line:13:11, endln:13:12 |vpiParent: @@ -464,7 +464,6 @@ design: (work@top) \_hier_path: (c[1].x), line:12:11, endln:12:12 |vpiParent: \_cont_assign: , line:12:11, endln:12:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:12:11, endln:12:12 |vpiParent: @@ -489,6 +488,7 @@ design: (work@top) |vpiFullName:c[1].x |vpiActual: \_typespec_member: (x), line:3:19, endln:3:20 + |vpiName:c[1].x |vpiContAssign: \_cont_assign: , line:13:11, endln:13:21 |vpiParent: @@ -497,7 +497,6 @@ design: (work@top) \_hier_path: (c[1].x), line:13:15, endln:13:21 |vpiParent: \_cont_assign: , line:13:11, endln:13:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:13:15, endln:13:16 |vpiParent: @@ -516,6 +515,7 @@ design: (work@top) |vpiFullName:work@top.x |vpiActual: \_typespec_member: (x), line:3:19, endln:3:20 + |vpiName:c[1].x |vpiLhs: \_ref_obj: (work@top.o), line:13:11, endln:13:12 |vpiParent: @@ -605,7 +605,6 @@ design: (work@top) \_hier_path: (c[1].x), line:12:11, endln:12:12 |vpiParent: \_cont_assign: , line:12:11, endln:12:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:12:11, endln:12:12 |vpiParent: @@ -620,6 +619,7 @@ design: (work@top) \_hier_path: (c[1].x), line:12:11, endln:12:12 |vpiName:x |vpiFullName:c[1].x + |vpiName:c[1].x =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/HierPathVarArray/HierPathVarArray.log b/tests/HierPathVarArray/HierPathVarArray.log index ee6b326338..475772c7bd 100644 --- a/tests/HierPathVarArray/HierPathVarArray.log +++ b/tests/HierPathVarArray/HierPathVarArray.log @@ -338,7 +338,6 @@ design: (work@top) \_hier_path: (c[1].x), line:11:11, endln:11:12 |vpiParent: \_cont_assign: , line:11:11, endln:11:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:11:11, endln:11:12 |vpiParent: @@ -357,6 +356,7 @@ design: (work@top) \_hier_path: (c[1].x), line:11:11, endln:11:12 |vpiName:x |vpiFullName:c[1].x + |vpiName:c[1].x |vpiContAssign: \_cont_assign: , line:12:11, endln:12:21 |vpiParent: @@ -365,7 +365,6 @@ design: (work@top) \_hier_path: (c[1].x), line:12:15, endln:12:21 |vpiParent: \_cont_assign: , line:12:11, endln:12:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:12:15, endln:12:16 |vpiParent: @@ -384,6 +383,7 @@ design: (work@top) \_hier_path: (c[1].x), line:12:15, endln:12:21 |vpiName:x |vpiFullName:work@top.x + |vpiName:c[1].x |vpiLhs: \_ref_obj: (work@top.o), line:12:11, endln:12:12 |vpiParent: @@ -458,7 +458,6 @@ design: (work@top) \_hier_path: (c[1].x), line:11:11, endln:11:12 |vpiParent: \_cont_assign: , line:11:11, endln:11:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:11:11, endln:11:12 |vpiParent: @@ -483,6 +482,7 @@ design: (work@top) |vpiFullName:c[1].x |vpiActual: \_typespec_member: (x), line:4:16, endln:4:17 + |vpiName:c[1].x |vpiContAssign: \_cont_assign: , line:12:11, endln:12:21 |vpiParent: @@ -491,7 +491,6 @@ design: (work@top) \_hier_path: (c[1].x), line:12:15, endln:12:21 |vpiParent: \_cont_assign: , line:12:11, endln:12:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:12:15, endln:12:16 |vpiParent: @@ -510,6 +509,7 @@ design: (work@top) |vpiFullName:work@top.x |vpiActual: \_typespec_member: (x), line:4:16, endln:4:17 + |vpiName:c[1].x |vpiLhs: \_ref_obj: (work@top.o), line:12:11, endln:12:12 |vpiParent: @@ -575,7 +575,6 @@ design: (work@top) \_hier_path: (c[1].x), line:11:11, endln:11:12 |vpiParent: \_cont_assign: , line:11:11, endln:11:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:11:11, endln:11:12 |vpiParent: @@ -590,6 +589,7 @@ design: (work@top) \_hier_path: (c[1].x), line:11:11, endln:11:12 |vpiName:x |vpiFullName:c[1].x + |vpiName:c[1].x =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/IOClassStruct/IOClassStruct.log b/tests/IOClassStruct/IOClassStruct.log index d57488c7f4..eb605b2eed 100644 --- a/tests/IOClassStruct/IOClassStruct.log +++ b/tests/IOClassStruct/IOClassStruct.log @@ -116,8 +116,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 class_defn 2 class_var 1 @@ -137,8 +136,7 @@ unsupported_typespec 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 2 +assignment 3 begin 2 class_defn 2 class_var 3 @@ -233,7 +231,6 @@ design: (unnamed) \_hier_path: (access_record.read_count), line:18:6, endln:18:30 |vpiParent: \_operation: , line:18:6, endln:18:32 - |vpiName:access_record.read_count |vpiActual: \_ref_obj: (access_record), line:18:20, endln:18:30 |vpiParent: @@ -248,6 +245,7 @@ design: (unnamed) |vpiName:read_count |vpiActual: \_typespec_member: (read_count), line:7:18, endln:7:28 + |vpiName:access_record.read_count |vpiMethod: \_function: (uvm_pkg::uvm_resource_base::init_access_record), line:23:3, endln:25:12 |vpiParent: @@ -285,7 +283,6 @@ design: (unnamed) \_hier_path: (access_record.read_count), line:24:3, endln:24:27 |vpiParent: \_assignment: , line:24:3, endln:24:31 - |vpiName:access_record.read_count |vpiActual: \_ref_obj: (access_record), line:24:17, endln:24:27 |vpiParent: @@ -300,6 +297,7 @@ design: (unnamed) |vpiName:read_count |vpiActual: \_typespec_member: (read_count), line:7:18, endln:7:28 + |vpiName:access_record.read_count |vpiClassDefn: \_class_defn: (uvm_pkg::uvm_resource_types), file:${SURELOG_DIR}/tests/IOClassStruct/dut.sv, line:3:1, endln:10:9 |vpiParent: diff --git a/tests/ImplicitGenBlock/ImplicitGenBlock.log b/tests/ImplicitGenBlock/ImplicitGenBlock.log index 19fc8924d0..8ea7ebaced 100644 --- a/tests/ImplicitGenBlock/ImplicitGenBlock.log +++ b/tests/ImplicitGenBlock/ImplicitGenBlock.log @@ -340,7 +340,6 @@ design: (work@top) \_hier_path: (genblk1.t), line:66:16, endln:66:25 |vpiParent: \_cont_assign: , line:66:16, endln:66:29 - |vpiName:genblk1.t |vpiActual: \_ref_obj: (genblk1), line:66:24, endln:66:25 |vpiParent: @@ -351,6 +350,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.t), line:66:16, endln:66:25 |vpiName:t + |vpiName:genblk1.t |vpiContAssign: \_cont_assign: , line:67:16, endln:67:34 |vpiParent: @@ -367,7 +367,6 @@ design: (work@top) \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30 |vpiParent: \_cont_assign: , line:67:16, endln:67:34 - |vpiName:genblk1.foo.x1 |vpiActual: \_ref_obj: (genblk1), line:67:24, endln:67:27 |vpiParent: @@ -383,6 +382,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30 |vpiName:x1 + |vpiName:genblk1.foo.x1 |vpiContAssign: \_cont_assign: , line:68:16, endln:68:29 |vpiParent: @@ -399,7 +399,6 @@ design: (work@top) \_hier_path: (genblk1.u), line:68:16, endln:68:25 |vpiParent: \_cont_assign: , line:68:16, endln:68:29 - |vpiName:genblk1.u |vpiActual: \_ref_obj: (genblk1), line:68:24, endln:68:25 |vpiParent: @@ -410,6 +409,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.u), line:68:16, endln:68:25 |vpiName:u + |vpiName:genblk1.u |vpiContAssign: \_cont_assign: , line:69:16, endln:69:27 |vpiParent: @@ -426,7 +426,6 @@ design: (work@top) \_hier_path: (bar2.x2), line:69:16, endln:69:23 |vpiParent: \_cont_assign: , line:69:16, endln:69:27 - |vpiName:bar2.x2 |vpiActual: \_ref_obj: (bar2), line:69:21, endln:69:23 |vpiParent: @@ -437,6 +436,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.x2), line:69:16, endln:69:23 |vpiName:x2 + |vpiName:bar2.x2 |vpiContAssign: \_cont_assign: , line:70:16, endln:70:27 |vpiParent: @@ -453,7 +453,6 @@ design: (work@top) \_hier_path: (bar2.y2), line:70:16, endln:70:23 |vpiParent: \_cont_assign: , line:70:16, endln:70:27 - |vpiName:bar2.y2 |vpiActual: \_ref_obj: (bar2), line:70:21, endln:70:23 |vpiParent: @@ -464,6 +463,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.y2), line:70:16, endln:70:23 |vpiName:y2 + |vpiName:bar2.y2 |vpiContAssign: \_cont_assign: , line:71:16, endln:71:31 |vpiParent: @@ -480,7 +480,6 @@ design: (work@top) \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27 |vpiParent: \_cont_assign: , line:71:16, endln:71:31 - |vpiName:bar2.baz.x3 |vpiActual: \_ref_obj: (bar2), line:71:21, endln:71:24 |vpiParent: @@ -496,6 +495,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27 |vpiName:x3 + |vpiName:bar2.baz.x3 |vpiContAssign: \_cont_assign: , line:72:16, endln:72:31 |vpiParent: @@ -512,7 +512,6 @@ design: (work@top) \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27 |vpiParent: \_cont_assign: , line:72:16, endln:72:31 - |vpiName:bar2.baz.z3 |vpiActual: \_ref_obj: (bar2), line:72:21, endln:72:24 |vpiParent: @@ -528,6 +527,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27 |vpiName:z3 + |vpiName:bar2.baz.z3 |vpiGenStmt: \_gen_region: |vpiParent: @@ -751,7 +751,6 @@ design: (work@top) \_hier_path: (genblk1.t), line:66:16, endln:66:25 |vpiParent: \_cont_assign: , line:66:16, endln:66:29 - |vpiName:genblk1.t |vpiActual: \_ref_obj: (genblk1), line:66:24, endln:66:25 |vpiParent: @@ -766,6 +765,7 @@ design: (work@top) |vpiName:t |vpiActual: \_logic_net: (work@top.genblk1.t), line:35:30, endln:35:31 + |vpiName:genblk1.t |vpiContAssign: \_cont_assign: , line:67:16, endln:67:34 |vpiParent: @@ -776,7 +776,6 @@ design: (work@top) \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30 |vpiParent: \_cont_assign: , line:67:16, endln:67:34 - |vpiName:genblk1.foo.x1 |vpiActual: \_ref_obj: (genblk1), line:67:24, endln:67:27 |vpiParent: @@ -796,6 +795,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30 |vpiName:x1 + |vpiName:genblk1.foo.x1 |vpiContAssign: \_cont_assign: , line:68:16, endln:68:29 |vpiParent: @@ -806,7 +806,6 @@ design: (work@top) \_hier_path: (genblk1.u), line:68:16, endln:68:25 |vpiParent: \_cont_assign: , line:68:16, endln:68:29 - |vpiName:genblk1.u |vpiActual: \_ref_obj: (genblk1), line:68:24, endln:68:25 |vpiParent: @@ -821,6 +820,7 @@ design: (work@top) |vpiName:u |vpiActual: \_logic_net: (work@top.genblk1.u), line:47:30, endln:47:31 + |vpiName:genblk1.u |vpiContAssign: \_cont_assign: , line:69:16, endln:69:27 |vpiParent: @@ -831,7 +831,6 @@ design: (work@top) \_hier_path: (bar2.x2), line:69:16, endln:69:23 |vpiParent: \_cont_assign: , line:69:16, endln:69:27 - |vpiName:bar2.x2 |vpiActual: \_ref_obj: (bar2), line:69:21, endln:69:23 |vpiParent: @@ -846,6 +845,7 @@ design: (work@top) |vpiName:x2 |vpiActual: \_logic_net: (work@top.bar2.x2), line:54:30, endln:54:32 + |vpiName:bar2.x2 |vpiContAssign: \_cont_assign: , line:70:16, endln:70:27 |vpiParent: @@ -856,7 +856,6 @@ design: (work@top) \_hier_path: (bar2.y2), line:70:16, endln:70:23 |vpiParent: \_cont_assign: , line:70:16, endln:70:27 - |vpiName:bar2.y2 |vpiActual: \_ref_obj: (bar2), line:70:21, endln:70:23 |vpiParent: @@ -871,6 +870,7 @@ design: (work@top) |vpiName:y2 |vpiActual: \_logic_net: (work@top.bar2.y2), line:56:30, endln:56:32 + |vpiName:bar2.y2 |vpiContAssign: \_cont_assign: , line:71:16, endln:71:31 |vpiParent: @@ -881,7 +881,6 @@ design: (work@top) \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27 |vpiParent: \_cont_assign: , line:71:16, endln:71:31 - |vpiName:bar2.baz.x3 |vpiActual: \_ref_obj: (bar2), line:71:21, endln:71:24 |vpiParent: @@ -901,6 +900,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27 |vpiName:x3 + |vpiName:bar2.baz.x3 |vpiContAssign: \_cont_assign: , line:72:16, endln:72:31 |vpiParent: @@ -911,7 +911,6 @@ design: (work@top) \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27 |vpiParent: \_cont_assign: , line:72:16, endln:72:31 - |vpiName:bar2.baz.z3 |vpiActual: \_ref_obj: (bar2), line:72:21, endln:72:24 |vpiParent: @@ -931,6 +930,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27 |vpiName:z3 + |vpiName:bar2.baz.z3 \_weaklyReferenced: \_logic_typespec: , line:35:25, endln:35:29 |vpiParent: @@ -968,7 +968,6 @@ design: (work@top) \_hier_path: (genblk1.t), line:66:16, endln:66:25 |vpiParent: \_cont_assign: , line:66:16, endln:66:29 - |vpiName:genblk1.t |vpiActual: \_ref_obj: (genblk1), line:66:24, endln:66:25 |vpiParent: @@ -979,6 +978,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.t), line:66:16, endln:66:25 |vpiName:t + |vpiName:genblk1.t \_cont_assign: , line:67:16, endln:67:34 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10 @@ -988,7 +988,6 @@ design: (work@top) \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30 |vpiParent: \_cont_assign: , line:67:16, endln:67:34 - |vpiName:genblk1.foo.x1 |vpiActual: \_ref_obj: (genblk1), line:67:24, endln:67:27 |vpiParent: @@ -1004,6 +1003,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.foo.x1), line:67:16, endln:67:30 |vpiName:x1 + |vpiName:genblk1.foo.x1 \_cont_assign: , line:68:16, endln:68:29 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10 @@ -1013,7 +1013,6 @@ design: (work@top) \_hier_path: (genblk1.u), line:68:16, endln:68:25 |vpiParent: \_cont_assign: , line:68:16, endln:68:29 - |vpiName:genblk1.u |vpiActual: \_ref_obj: (genblk1), line:68:24, endln:68:25 |vpiParent: @@ -1024,6 +1023,7 @@ design: (work@top) |vpiParent: \_hier_path: (genblk1.u), line:68:16, endln:68:25 |vpiName:u + |vpiName:genblk1.u \_cont_assign: , line:69:16, endln:69:27 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10 @@ -1033,7 +1033,6 @@ design: (work@top) \_hier_path: (bar2.x2), line:69:16, endln:69:23 |vpiParent: \_cont_assign: , line:69:16, endln:69:27 - |vpiName:bar2.x2 |vpiActual: \_ref_obj: (bar2), line:69:21, endln:69:23 |vpiParent: @@ -1044,6 +1043,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.x2), line:69:16, endln:69:23 |vpiName:x2 + |vpiName:bar2.x2 \_cont_assign: , line:70:16, endln:70:27 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10 @@ -1053,7 +1053,6 @@ design: (work@top) \_hier_path: (bar2.y2), line:70:16, endln:70:23 |vpiParent: \_cont_assign: , line:70:16, endln:70:27 - |vpiName:bar2.y2 |vpiActual: \_ref_obj: (bar2), line:70:21, endln:70:23 |vpiParent: @@ -1064,6 +1063,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.y2), line:70:16, endln:70:23 |vpiName:y2 + |vpiName:bar2.y2 \_cont_assign: , line:71:16, endln:71:31 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10 @@ -1073,7 +1073,6 @@ design: (work@top) \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27 |vpiParent: \_cont_assign: , line:71:16, endln:71:31 - |vpiName:bar2.baz.x3 |vpiActual: \_ref_obj: (bar2), line:71:21, endln:71:24 |vpiParent: @@ -1089,6 +1088,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.baz.x3), line:71:16, endln:71:27 |vpiName:x3 + |vpiName:bar2.baz.x3 \_cont_assign: , line:72:16, endln:72:31 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10 @@ -1098,7 +1098,6 @@ design: (work@top) \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27 |vpiParent: \_cont_assign: , line:72:16, endln:72:31 - |vpiName:bar2.baz.z3 |vpiActual: \_ref_obj: (bar2), line:72:21, endln:72:24 |vpiParent: @@ -1114,6 +1113,7 @@ design: (work@top) |vpiParent: \_hier_path: (bar2.baz.z3), line:72:16, endln:72:27 |vpiName:z3 + |vpiName:bar2.baz.z3 \_gen_scope: (work@top.genblk1), line:35:25, endln:35:32 |vpiParent: \_gen_scope_array: (work@top.genblk1), line:35:25, endln:35:32 diff --git a/tests/IncompFunc/IncompFunc.log b/tests/IncompFunc/IncompFunc.log index 7cc65d99e6..2faef3c6ab 100644 --- a/tests/IncompFunc/IncompFunc.log +++ b/tests/IncompFunc/IncompFunc.log @@ -159,8 +159,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 bit_select 1 constant 17 @@ -190,8 +189,7 @@ return_stmt 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 2 +assignment 3 begin 2 bit_select 2 constant 17 diff --git a/tests/IndexPartSelectBind/IndexPartSelectBind.log b/tests/IndexPartSelectBind/IndexPartSelectBind.log index f7146615a2..cd00b7bad0 100644 --- a/tests/IndexPartSelectBind/IndexPartSelectBind.log +++ b/tests/IndexPartSelectBind/IndexPartSelectBind.log @@ -150,8 +150,7 @@ AST_DEBUG_END [ERR:CP0317] ${SURELOG_DIR}/tests/IndexPartSelectBind/dut.sv:10:1: Undefined type "uvm_sequence_item". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 2 bit_select 1 class_defn 1 @@ -176,8 +175,7 @@ unsupported_typespec 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 4 bit_select 2 class_defn 1 @@ -322,13 +320,13 @@ design: (unnamed) \_begin: (pkg::tt::reg2bus), line:17:1, endln:17:11 |vpiFullName:pkg::tt::reg2bus |vpiForInitStmt: - \_assign_stmt: , line:12:6, endln:12:15 + \_assignment: , line:12:6, endln:12:15 |vpiParent: \_for_stmt: (pkg::tt::reg2bus), line:12:1, endln:12:4 |vpiRhs: \_constant: , line:12:14, endln:12:15 |vpiParent: - \_assign_stmt: , line:12:6, endln:12:15 + \_assignment: , line:12:6, endln:12:15 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -336,7 +334,7 @@ design: (unnamed) |vpiLhs: \_int_var: (pkg::tt::reg2bus::i), line:12:10, endln:12:11 |vpiParent: - \_assign_stmt: , line:12:6, endln:12:15 + \_assignment: , line:12:6, endln:12:15 |vpiTypespec: \_ref_typespec: (pkg::tt::reg2bus::i) |vpiParent: @@ -394,7 +392,6 @@ design: (unnamed) \_hier_path: (rw.data[i * 8+:8]), line:13:17, endln:13:32 |vpiParent: \_assignment: , line:13:4, endln:13:32 - |vpiName:rw.data[i * 8+:8] |vpiActual: \_ref_obj: (rw), line:13:17, endln:13:19 |vpiParent: @@ -439,11 +436,11 @@ design: (unnamed) |vpiSize:64 |UINT:8 |vpiConstType:9 + |vpiName:rw.data[i * 8+:8] |vpiLhs: \_hier_path: (rw.data[i]), line:13:4, endln:13:14 |vpiParent: \_assignment: , line:13:4, endln:13:32 - |vpiName:rw.data[i] |vpiActual: \_ref_obj: (rw), line:13:7, endln:13:11 |vpiParent: @@ -467,6 +464,7 @@ design: (unnamed) |vpiFullName:pkg::tt::reg2bus::rw.data[i]::i |vpiActual: \_int_var: (pkg::tt::reg2bus::i), line:12:10, endln:12:11 + |vpiName:rw.data[i] |vpiStmt: \_return_stmt: , line:17:1, endln:17:7 |vpiParent: @@ -524,7 +522,7 @@ design: (unnamed) \_begin: (pkg::tt::reg2bus), line:17:1, endln:17:11 |vpiFullName:pkg::tt::reg2bus |vpiForInitStmt: - \_assign_stmt: , line:12:6, endln:12:15 + \_assignment: , line:12:6, endln:12:15 |vpiParent: \_for_stmt: (pkg::tt::reg2bus), line:12:1, endln:12:4 |vpiRhs: @@ -532,7 +530,7 @@ design: (unnamed) |vpiLhs: \_int_var: (pkg::tt::reg2bus::i), line:12:10, endln:12:11 |vpiParent: - \_assign_stmt: , line:12:6, endln:12:15 + \_assignment: , line:12:6, endln:12:15 |vpiTypespec: \_ref_typespec: (pkg::tt::reg2bus::i) |vpiParent: @@ -586,7 +584,6 @@ design: (unnamed) \_hier_path: (rw.data[i * 8+:8]), line:13:17, endln:13:32 |vpiParent: \_assignment: , line:13:4, endln:13:32 - |vpiName:rw.data[i * 8+:8] |vpiActual: \_ref_obj: (rw), line:13:17, endln:13:19 |vpiParent: @@ -615,11 +612,11 @@ design: (unnamed) \_constant: , line:13:27, endln:13:28 |vpiWidthExpr: \_constant: , line:13:30, endln:13:31 + |vpiName:rw.data[i * 8+:8] |vpiLhs: \_hier_path: (rw.data[i]), line:13:4, endln:13:14 |vpiParent: \_assignment: , line:13:4, endln:13:32 - |vpiName:rw.data[i] |vpiActual: \_ref_obj: (rw), line:13:7, endln:13:11 |vpiParent: @@ -637,6 +634,7 @@ design: (unnamed) \_bit_select: (pkg::tt::reg2bus::rw.data[i]::data), line:13:12, endln:13:13 |vpiName:i |vpiFullName:pkg::tt::reg2bus::rw.data[i]::i + |vpiName:rw.data[i] |vpiStmt: \_return_stmt: , line:17:1, endln:17:7 |vpiParent: diff --git a/tests/IndexedSelectHex/IndexedSelectHex.log b/tests/IndexedSelectHex/IndexedSelectHex.log index 01364362e5..9fc656e0e1 100644 --- a/tests/IndexedSelectHex/IndexedSelectHex.log +++ b/tests/IndexedSelectHex/IndexedSelectHex.log @@ -425,7 +425,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 4 constant 189 cont_assign 9 @@ -463,7 +463,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 4 constant 189 cont_assign 37 @@ -1226,7 +1226,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/IndexedSelectHex/dut.sv, line:44:1, endln:53:10 |vpiForInitStmt: - \_assign_stmt: , line:48:8, endln:48:20 + \_assignment: , line:48:8, endln:48:20 |vpiParent: \_gen_for: |vpiRhs: @@ -1238,7 +1238,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.k), line:48:15, endln:48:16 |vpiParent: - \_assign_stmt: , line:48:8, endln:48:20 + \_assignment: , line:48:8, endln:48:20 |vpiTypespec: \_ref_typespec: (work@top.k) |vpiParent: diff --git a/tests/InterfArrayBind/InterfArrayBind.log b/tests/InterfArrayBind/InterfArrayBind.log index 323266f17b..fabc24f2d1 100644 --- a/tests/InterfArrayBind/InterfArrayBind.log +++ b/tests/InterfArrayBind/InterfArrayBind.log @@ -420,7 +420,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[IO_ONES].write_en), line:16:12, endln:16:29 |vpiParent: \_cont_assign: , line:16:12, endln:16:62 - |vpiName:peripheral_io_bus[IO_ONES].write_en |vpiActual: \_bit_select: (peripheral_io_bus[IO_ONES]), line:16:12, endln:16:29 |vpiParent: @@ -441,6 +440,7 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[IO_ONES].write_en), line:16:12, endln:16:29 |vpiName:write_en |vpiFullName:peripheral_io_bus[IO_ONES].write_en + |vpiName:peripheral_io_bus[IO_ONES].write_en |vpiGenStmt: \_gen_region: |vpiParent: @@ -598,7 +598,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[io_idx].write_en), line:22:20, endln:22:37 |vpiParent: \_cont_assign: , line:22:20, endln:22:58 - |vpiName:peripheral_io_bus[io_idx].write_en |vpiActual: \_bit_select: (peripheral_io_bus[io_idx]), line:22:20, endln:22:37 |vpiParent: @@ -623,6 +622,7 @@ design: (work@soc_tb) |vpiFullName:peripheral_io_bus[io_idx].write_en |vpiActual: \_logic_var: (work@soc_tb.peripheral_io_bus[0].write_en), line:2:11, endln:2:19 + |vpiName:peripheral_io_bus[io_idx].write_en |vpiGenScopeArray: \_gen_scope_array: (work@soc_tb.io_gen[1]), line:21:9, endln:23:12 |vpiParent: @@ -665,7 +665,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[io_idx].write_en), line:22:20, endln:22:37 |vpiParent: \_cont_assign: , line:22:20, endln:22:58 - |vpiName:peripheral_io_bus[io_idx].write_en |vpiActual: \_bit_select: (peripheral_io_bus[io_idx]), line:22:20, endln:22:37 |vpiParent: @@ -690,6 +689,7 @@ design: (work@soc_tb) |vpiFullName:peripheral_io_bus[io_idx].write_en |vpiActual: \_logic_var: (work@soc_tb.peripheral_io_bus[1].write_en), line:2:11, endln:2:19 + |vpiName:peripheral_io_bus[io_idx].write_en |vpiContAssign: \_cont_assign: , line:16:12, endln:16:62 |vpiParent: @@ -700,7 +700,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[IO_ONES].write_en), line:16:12, endln:16:29 |vpiParent: \_cont_assign: , line:16:12, endln:16:62 - |vpiName:peripheral_io_bus[IO_ONES].write_en |vpiActual: \_bit_select: (peripheral_io_bus[IO_ONES]), line:16:12, endln:16:29 |vpiParent: @@ -725,6 +724,7 @@ design: (work@soc_tb) |vpiFullName:peripheral_io_bus[IO_ONES].write_en |vpiActual: \_logic_var: (work@soc_tb.peripheral_io_bus[0].write_en), line:2:11, endln:2:19 + |vpiName:peripheral_io_bus[IO_ONES].write_en \_weaklyReferenced: \_int_typespec: , line:8:5, endln:8:35 \_module_typespec: (io_bus_interface), line:14:5, endln:14:21 @@ -840,7 +840,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[IO_ONES].write_en), line:16:12, endln:16:29 |vpiParent: \_cont_assign: , line:16:12, endln:16:62 - |vpiName:peripheral_io_bus[IO_ONES].write_en |vpiActual: \_bit_select: (peripheral_io_bus[IO_ONES]), line:16:12, endln:16:29 |vpiParent: @@ -861,6 +860,7 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[IO_ONES].write_en), line:16:12, endln:16:29 |vpiName:write_en |vpiFullName:peripheral_io_bus[IO_ONES].write_en + |vpiName:peripheral_io_bus[IO_ONES].write_en \_cont_assign: , line:22:20, endln:22:58 |vpiParent: \_gen_scope: (work@soc_tb.io_gen[0]), line:21:9, endln:23:12 @@ -870,7 +870,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[io_idx].write_en), line:22:20, endln:22:37 |vpiParent: \_cont_assign: , line:22:20, endln:22:58 - |vpiName:peripheral_io_bus[io_idx].write_en |vpiActual: \_bit_select: (peripheral_io_bus[io_idx]), line:22:20, endln:22:37 |vpiParent: @@ -889,6 +888,7 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[io_idx].write_en), line:22:20, endln:22:37 |vpiName:write_en |vpiFullName:peripheral_io_bus[io_idx].write_en + |vpiName:peripheral_io_bus[io_idx].write_en \_gen_scope: (work@soc_tb.io_gen[0]), line:21:9, endln:23:12 |vpiParent: \_gen_scope_array: (work@soc_tb.io_gen[0]), line:21:9, endln:23:12 @@ -914,7 +914,6 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[io_idx].write_en), line:22:20, endln:22:37 |vpiParent: \_cont_assign: , line:22:20, endln:22:58 - |vpiName:peripheral_io_bus[io_idx].write_en |vpiActual: \_bit_select: (peripheral_io_bus[io_idx]), line:22:20, endln:22:37 |vpiParent: @@ -933,6 +932,7 @@ design: (work@soc_tb) \_hier_path: (peripheral_io_bus[io_idx].write_en), line:22:20, endln:22:37 |vpiName:write_en |vpiFullName:peripheral_io_bus[io_idx].write_en + |vpiName:peripheral_io_bus[io_idx].write_en \_gen_scope: (work@soc_tb.io_gen[1]), line:21:9, endln:23:12 |vpiParent: \_gen_scope_array: (work@soc_tb.io_gen[1]), line:21:9, endln:23:12 diff --git a/tests/InterfBinding/InterfBinding.log b/tests/InterfBinding/InterfBinding.log index e1981e0b30..63a9b9de19 100644 --- a/tests/InterfBinding/InterfBinding.log +++ b/tests/InterfBinding/InterfBinding.log @@ -405,7 +405,6 @@ design: (work@BypassNetwork) \_hier_path: (ctrl.backEnd), line:33:13, endln:33:25 |vpiParent: \_cont_assign: , line:33:9, endln:33:25 - |vpiName:ctrl.backEnd |vpiActual: \_ref_obj: (ctrl), line:33:13, endln:33:17 |vpiParent: @@ -417,6 +416,7 @@ design: (work@BypassNetwork) \_hier_path: (ctrl.backEnd), line:33:13, endln:33:25 |vpiName:backEnd |vpiFullName:work@BypassNetwork.backEnd + |vpiName:ctrl.backEnd |vpiLhs: \_ref_obj: (work@BypassNetwork.o), line:33:9, endln:33:10 |vpiParent: @@ -547,7 +547,6 @@ design: (work@BypassNetwork) \_hier_path: (ctrl.backEnd), line:33:13, endln:33:25 |vpiParent: \_cont_assign: , line:33:9, endln:33:25 - |vpiName:ctrl.backEnd |vpiActual: \_ref_obj: (ctrl), line:33:13, endln:33:17 |vpiParent: @@ -563,6 +562,7 @@ design: (work@BypassNetwork) |vpiFullName:work@BypassNetwork.backEnd |vpiActual: \_struct_net: (work@BypassNetwork.ctrl.BypassNetwork.backEnd.backEnd), line:18:21, endln:18:28 + |vpiName:ctrl.backEnd |vpiLhs: \_ref_obj: (work@BypassNetwork.o), line:33:9, endln:33:10 |vpiParent: diff --git a/tests/InterfHierPath/InterfHierPath.log b/tests/InterfHierPath/InterfHierPath.log index 04c498ab3e..ae6448cc63 100644 --- a/tests/InterfHierPath/InterfHierPath.log +++ b/tests/InterfHierPath/InterfHierPath.log @@ -209,7 +209,6 @@ design: (work@or_ex) \_hier_path: (lg.a), line:14:10, endln:14:14 |vpiParent: \_cont_assign: , line:14:10, endln:14:18 - |vpiName:lg.a |vpiActual: \_ref_obj: (lg), line:14:13, endln:14:14 |vpiParent: @@ -220,6 +219,7 @@ design: (work@or_ex) |vpiParent: \_hier_path: (lg.a), line:14:10, endln:14:14 |vpiName:a + |vpiName:lg.a |vpiRefModule: \_ref_module: work@logic_gate_if (lg), line:12:17, endln:12:19 |vpiParent: @@ -312,7 +312,6 @@ design: (work@or_ex) \_hier_path: (lg.a), line:14:10, endln:14:14 |vpiParent: \_cont_assign: , line:14:10, endln:14:18 - |vpiName:lg.a |vpiActual: \_ref_obj: (lg), line:14:13, endln:14:14 |vpiParent: @@ -327,6 +326,7 @@ design: (work@or_ex) |vpiName:a |vpiActual: \_logic_net: (work@or_ex.a), line:9:22, endln:9:23 + |vpiName:lg.a \_weaklyReferenced: \_logic_typespec: , line:9:11, endln:9:21 |vpiRange: diff --git a/tests/InterfImport/InterfImport.log b/tests/InterfImport/InterfImport.log index afc5e5cf97..5f375ad586 100644 --- a/tests/InterfImport/InterfImport.log +++ b/tests/InterfImport/InterfImport.log @@ -531,7 +531,6 @@ design: (unnamed) \_hier_path: (PACKET_CONFIG.virtual_channels), line:11:31, endln:11:61 |vpiParent: \_param_assign: , line:11:19, endln:11:61 - |vpiName:PACKET_CONFIG.virtual_channels |vpiActual: \_ref_obj: (PACKET_CONFIG), line:11:45, endln:11:61 |vpiParent: @@ -542,6 +541,7 @@ design: (unnamed) |vpiParent: \_hier_path: (PACKET_CONFIG.virtual_channels), line:11:31, endln:11:61 |vpiName:virtual_channels + |vpiName:PACKET_CONFIG.virtual_channels |vpiLhs: \_parameter: (work@tnoc_port_control_if.CHANNELS), line:11:19, endln:11:27 |vpiTypedef: diff --git a/tests/InterfInst/InterfInst.log b/tests/InterfInst/InterfInst.log index 10e07bee61..01824a366e 100644 --- a/tests/InterfInst/InterfInst.log +++ b/tests/InterfInst/InterfInst.log @@ -272,7 +272,6 @@ design: (work@top) \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31 |vpiParent: \_cont_assign: , line:7:11, endln:7:31 - |vpiName:ss_if.start_addr |vpiActual: \_ref_obj: (ss_if), line:7:15, endln:7:20 |vpiParent: @@ -284,6 +283,7 @@ design: (work@top) \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31 |vpiName:start_addr |vpiFullName:work@dut.start_addr + |vpiName:ss_if.start_addr |vpiLhs: \_ref_obj: (work@dut.a), line:7:11, endln:7:12 |vpiParent: @@ -348,7 +348,6 @@ design: (work@top) \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35 |vpiParent: \_cont_assign: , line:12:11, endln:12:46 - |vpiName:u_sim_sram_if.start_addr |vpiActual: \_ref_obj: (u_sim_sram_if), line:12:25, endln:12:35 |vpiParent: @@ -359,6 +358,7 @@ design: (work@top) |vpiParent: \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35 |vpiName:start_addr + |vpiName:u_sim_sram_if.start_addr |vpiRefModule: \_ref_module: work@sim_sram_if (u_sim_sram_if), line:11:16, endln:11:29 |vpiParent: @@ -588,7 +588,6 @@ design: (work@top) \_hier_path: (ss_if.start_addr), line:7:15, endln:7:31 |vpiParent: \_cont_assign: , line:7:11, endln:7:31 - |vpiName:ss_if.start_addr |vpiActual: \_ref_obj: (ss_if), line:7:15, endln:7:20 |vpiParent: @@ -604,6 +603,7 @@ design: (work@top) |vpiFullName:work@top.u_dut.start_addr |vpiActual: \_int_var: (work@top.u_dut.ss_if.start_addr), line:3:8, endln:3:18 + |vpiName:ss_if.start_addr |vpiLhs: \_ref_obj: (work@top.u_dut.a), line:7:11, endln:7:12 |vpiParent: @@ -622,7 +622,6 @@ design: (work@top) \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35 |vpiParent: \_cont_assign: , line:12:11, endln:12:46 - |vpiName:u_sim_sram_if.start_addr |vpiActual: \_ref_obj: (u_sim_sram_if), line:12:25, endln:12:35 |vpiParent: @@ -637,6 +636,7 @@ design: (work@top) |vpiName:start_addr |vpiActual: \_int_var: (work@top.u_sim_sram_if.start_addr), line:3:8, endln:3:18 + |vpiName:u_sim_sram_if.start_addr \_weaklyReferenced: \_int_typespec: , line:10:19, endln:10:22 |vpiSigned:1 @@ -675,7 +675,6 @@ design: (work@top) \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35 |vpiParent: \_cont_assign: , line:12:11, endln:12:46 - |vpiName:u_sim_sram_if.start_addr |vpiActual: \_ref_obj: (u_sim_sram_if), line:12:25, endln:12:35 |vpiParent: @@ -686,6 +685,7 @@ design: (work@top) |vpiParent: \_hier_path: (u_sim_sram_if.start_addr), line:12:11, endln:12:35 |vpiName:start_addr + |vpiName:u_sim_sram_if.start_addr =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/InterfaceFuncCall/InterfaceFuncCall.log b/tests/InterfaceFuncCall/InterfaceFuncCall.log index 368ee332cc..45994ca535 100644 --- a/tests/InterfaceFuncCall/InterfaceFuncCall.log +++ b/tests/InterfaceFuncCall/InterfaceFuncCall.log @@ -355,7 +355,6 @@ design: (work@top) \_hier_path: (foo_1.bar), line:13:18, endln:13:30 |vpiParent: \_sys_func_call: ($display), line:13:9, endln:13:31 - |vpiName:foo_1.bar |vpiActual: \_ref_obj: (foo_1), line:13:18, endln:13:23 |vpiParent: @@ -374,6 +373,7 @@ design: (work@top) |UINT:3 |vpiConstType:9 |vpiName:bar + |vpiName:foo_1.bar |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:14:9, endln:14:31 @@ -383,7 +383,6 @@ design: (work@top) \_hier_path: (foo_2.bar), line:14:18, endln:14:30 |vpiParent: \_sys_func_call: ($display), line:14:9, endln:14:31 - |vpiName:foo_2.bar |vpiActual: \_ref_obj: (foo_2), line:14:18, endln:14:23 |vpiParent: @@ -402,6 +401,7 @@ design: (work@top) |UINT:3 |vpiConstType:9 |vpiName:bar + |vpiName:foo_2.bar |vpiName:$display |vpiRefModule: \_ref_module: work@Foo (foo_1), line:10:9, endln:10:14 @@ -539,7 +539,6 @@ design: (work@top) \_hier_path: (foo_1.bar), line:13:18, endln:13:30 |vpiParent: \_sys_func_call: ($display), line:13:9, endln:13:31 - |vpiName:foo_1.bar |vpiActual: \_ref_obj: (foo_1), line:13:18, endln:13:23 |vpiParent: @@ -556,6 +555,7 @@ design: (work@top) |vpiName:bar |vpiFunction: \_function: (work@Foo.bar), line:3:5, endln:6:16 + |vpiName:foo_1.bar |vpiName:$display |vpiStmt: \_sys_func_call: ($display), line:14:9, endln:14:31 @@ -565,7 +565,6 @@ design: (work@top) \_hier_path: (foo_2.bar), line:14:18, endln:14:30 |vpiParent: \_sys_func_call: ($display), line:14:9, endln:14:31 - |vpiName:foo_2.bar |vpiActual: \_ref_obj: (foo_2), line:14:18, endln:14:23 |vpiParent: @@ -582,6 +581,7 @@ design: (work@top) |vpiName:bar |vpiFunction: \_function: (work@Foo.bar), line:3:5, endln:6:16 + |vpiName:foo_2.bar |vpiName:$display \_weaklyReferenced: \_int_typespec: , line:2:5, endln:2:29 diff --git a/tests/InterfaceModExp/InterfaceModExp.log b/tests/InterfaceModExp/InterfaceModExp.log index 8f339daa35..31bbcc3547 100644 --- a/tests/InterfaceModExp/InterfaceModExp.log +++ b/tests/InterfaceModExp/InterfaceModExp.log @@ -511,7 +511,6 @@ design: (work@top) \_hier_path: (I.P), line:11:11, endln:11:14 |vpiParent: \_assignment: , line:11:11, endln:11:24 - |vpiName:I.P |vpiActual: \_ref_obj: (I), line:11:13, endln:11:14 |vpiParent: @@ -522,6 +521,7 @@ design: (work@top) |vpiParent: \_hier_path: (I.P), line:11:11, endln:11:14 |vpiName:P + |vpiName:I.P |uhdmallModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiParent: @@ -553,7 +553,6 @@ design: (work@top) \_hier_path: (inst.r), line:18:32, endln:18:38 |vpiParent: \_sys_func_call: ($display), line:18:14, endln:18:39 - |vpiName:inst.r |vpiActual: \_ref_obj: (inst), line:18:32, endln:18:36 |vpiParent: @@ -565,6 +564,7 @@ design: (work@top) \_hier_path: (inst.r), line:18:32, endln:18:38 |vpiName:r |vpiFullName:work@top.r + |vpiName:inst.r |vpiName:$display |vpiRefModule: \_ref_module: work@I (inst), line:15:5, endln:15:9 @@ -590,7 +590,6 @@ design: (work@top) \_hier_path: (inst.A), line:16:10, endln:16:16 |vpiParent: \_port: , line:16:10, endln:16:16 - |vpiName:inst.A |vpiActual: \_ref_obj: (inst), line:16:10, endln:16:14 |vpiParent: @@ -602,6 +601,7 @@ design: (work@top) \_hier_path: (inst.A), line:16:10, endln:16:16 |vpiName:A |vpiFullName:work@top.s.A + |vpiName:inst.A |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:14:1, endln:20:10 |vpiName:work@top @@ -791,7 +791,6 @@ design: (work@top) \_hier_path: (inst.r), line:18:32, endln:18:38 |vpiParent: \_sys_func_call: ($display), line:18:14, endln:18:39 - |vpiName:inst.r |vpiActual: \_ref_obj: (inst), line:18:32, endln:18:36 |vpiParent: @@ -807,6 +806,7 @@ design: (work@top) |vpiFullName:work@top.r |vpiActual: \_logic_var: (work@top.inst.r), line:2:13, endln:2:14 + |vpiName:inst.r |vpiName:$display |vpiModule: \_module_inst: work@sub (work@top.s), file:${SURELOG_DIR}/tests/InterfaceModExp/dut.sv, line:16:3, endln:16:18 @@ -829,7 +829,6 @@ design: (work@top) \_hier_path: (inst.A), line:16:10, endln:16:16 |vpiParent: \_port: (I), line:9:23, endln:9:24 - |vpiName:inst.A |vpiActual: \_ref_obj: (inst), line:16:10, endln:16:14 |vpiParent: @@ -845,6 +844,7 @@ design: (work@top) |vpiFullName:work@top.s.I.A |vpiActual: \_modport: (A), line:5:9, endln:5:10 + |vpiName:inst.A |vpiLowConn: \_ref_obj: (work@top.s.I), line:16:10, endln:16:16 |vpiParent: @@ -991,7 +991,6 @@ design: (work@top) \_hier_path: (I.P), line:11:11, endln:11:14 |vpiParent: \_assignment: , line:11:11, endln:11:24 - |vpiName:I.P |vpiActual: \_ref_obj: (I), line:11:13, endln:11:14 |vpiParent: @@ -1006,6 +1005,7 @@ design: (work@top) |vpiName:P |vpiActual: \_io_decl: (P), line:5:20, endln:5:21 + |vpiName:I.P \_weaklyReferenced: \_logic_typespec: , line:2:1, endln:2:12 |vpiParent: diff --git a/tests/InterfaceModPort/InterfaceModPort.log b/tests/InterfaceModPort/InterfaceModPort.log index bb6e052e78..dc71801a4f 100644 --- a/tests/InterfaceModPort/InterfaceModPort.log +++ b/tests/InterfaceModPort/InterfaceModPort.log @@ -2285,7 +2285,6 @@ design: (work@interface_modports) \_hier_path: (tif.reset), line:102:7, endln:102:16 |vpiParent: \_assignment: , line:102:7, endln:102:21 - |vpiName:tif.reset |vpiActual: \_ref_obj: (tif), line:102:11, endln:102:16 |vpiParent: @@ -2296,6 +2295,7 @@ design: (work@interface_modports) |vpiParent: \_hier_path: (tif.reset), line:102:7, endln:102:16 |vpiName:reset + |vpiName:tif.reset |vpiStmt: \_delay_control: , line:104:7, endln:104:10 |vpiParent: @@ -2597,7 +2597,6 @@ design: (work@interface_modports) \_hier_path: (mif.clk), line:69:19, endln:69:26 |vpiParent: \_operation: , line:69:11, endln:69:26 - |vpiName:mif.clk |vpiActual: \_ref_obj: (mif), line:69:19, endln:69:22 |vpiParent: @@ -2609,6 +2608,7 @@ design: (work@interface_modports) \_hier_path: (mif.clk), line:69:19, endln:69:26 |vpiName:clk |vpiFullName:work@memory_model.clk + |vpiName:mif.clk |vpiStmt: \_if_stmt: , line:70:2, endln:72:5 |vpiParent: @@ -2622,7 +2622,6 @@ design: (work@interface_modports) \_hier_path: (mif.ce_mem), line:70:6, endln:70:16 |vpiParent: \_operation: , line:70:6, endln:70:30 - |vpiName:mif.ce_mem |vpiActual: \_ref_obj: (mif), line:70:6, endln:70:9 |vpiParent: @@ -2634,11 +2633,11 @@ design: (work@interface_modports) \_hier_path: (mif.ce_mem), line:70:6, endln:70:16 |vpiName:ce_mem |vpiFullName:work@memory_model.ce_mem + |vpiName:mif.ce_mem |vpiOperand: \_hier_path: (mif.we_mem), line:70:20, endln:70:30 |vpiParent: \_operation: , line:70:6, endln:70:30 - |vpiName:mif.we_mem |vpiActual: \_ref_obj: (mif), line:70:20, endln:70:23 |vpiParent: @@ -2650,6 +2649,7 @@ design: (work@interface_modports) \_hier_path: (mif.we_mem), line:70:20, endln:70:30 |vpiName:we_mem |vpiFullName:work@memory_model.we_mem + |vpiName:mif.we_mem |vpiStmt: \_begin: (work@memory_model), line:70:32, endln:72:5 |vpiParent: @@ -2664,7 +2664,6 @@ design: (work@interface_modports) \_hier_path: (mif.datai_mem), line:71:25, endln:71:38 |vpiParent: \_assignment: , line:71:4, endln:71:38 - |vpiName:mif.datai_mem |vpiActual: \_ref_obj: (mif), line:71:25, endln:71:28 |vpiParent: @@ -2676,6 +2675,7 @@ design: (work@interface_modports) \_hier_path: (mif.datai_mem), line:71:25, endln:71:38 |vpiName:datai_mem |vpiFullName:work@memory_model.datai_mem + |vpiName:mif.datai_mem |vpiLhs: \_bit_select: (work@memory_model.mem), line:71:4, endln:71:21 |vpiParent: @@ -2686,7 +2686,6 @@ design: (work@interface_modports) \_hier_path: (mif.addr_mem), line:71:8, endln:71:20 |vpiParent: \_bit_select: (work@memory_model.mem), line:71:4, endln:71:21 - |vpiName:mif.addr_mem |vpiActual: \_ref_obj: (mif), line:71:8, endln:71:11 |vpiParent: @@ -2698,6 +2697,7 @@ design: (work@interface_modports) \_hier_path: (mif.addr_mem), line:71:8, endln:71:20 |vpiName:addr_mem |vpiFullName:work@memory_model.mem.addr_mem + |vpiName:mif.addr_mem |vpiAlwaysType:1 |vpiProcess: \_always: , line:77:1, endln:80:5 @@ -2716,7 +2716,6 @@ design: (work@interface_modports) \_hier_path: (mif.clk), line:77:19, endln:77:26 |vpiParent: \_operation: , line:77:11, endln:77:26 - |vpiName:mif.clk |vpiActual: \_ref_obj: (mif), line:77:19, endln:77:22 |vpiParent: @@ -2728,6 +2727,7 @@ design: (work@interface_modports) \_hier_path: (mif.clk), line:77:19, endln:77:26 |vpiName:clk |vpiFullName:work@memory_model.clk + |vpiName:mif.clk |vpiStmt: \_if_stmt: , line:78:2, endln:80:5 |vpiParent: @@ -2741,7 +2741,6 @@ design: (work@interface_modports) \_hier_path: (mif.ce_mem), line:78:6, endln:78:16 |vpiParent: \_operation: , line:78:6, endln:78:31 - |vpiName:mif.ce_mem |vpiActual: \_ref_obj: (mif), line:78:6, endln:78:9 |vpiParent: @@ -2753,6 +2752,7 @@ design: (work@interface_modports) \_hier_path: (mif.ce_mem), line:78:6, endln:78:16 |vpiName:ce_mem |vpiFullName:work@memory_model.ce_mem + |vpiName:mif.ce_mem |vpiOperand: \_operation: , line:78:20, endln:78:31 |vpiParent: @@ -2762,7 +2762,6 @@ design: (work@interface_modports) \_hier_path: (mif.we_mem), line:78:21, endln:78:31 |vpiParent: \_operation: , line:78:20, endln:78:31 - |vpiName:mif.we_mem |vpiActual: \_ref_obj: (mif), line:78:21, endln:78:24 |vpiParent: @@ -2774,6 +2773,7 @@ design: (work@interface_modports) \_hier_path: (mif.we_mem), line:78:21, endln:78:31 |vpiName:we_mem |vpiFullName:work@memory_model.we_mem + |vpiName:mif.we_mem |vpiStmt: \_begin: (work@memory_model), line:78:34, endln:80:5 |vpiParent: @@ -2794,7 +2794,6 @@ design: (work@interface_modports) \_hier_path: (mif.addr_mem), line:79:25, endln:79:37 |vpiParent: \_bit_select: (work@memory_model.mem), line:79:25, endln:79:37 - |vpiName:mif.addr_mem |vpiActual: \_ref_obj: (mif), line:79:25, endln:79:28 |vpiParent: @@ -2806,11 +2805,11 @@ design: (work@interface_modports) \_hier_path: (mif.addr_mem), line:79:25, endln:79:37 |vpiName:addr_mem |vpiFullName:work@memory_model.mem.addr_mem + |vpiName:mif.addr_mem |vpiLhs: \_hier_path: (mif.datao_mem), line:79:4, endln:79:17 |vpiParent: \_assignment: , line:79:4, endln:79:38 - |vpiName:mif.datao_mem |vpiActual: \_ref_obj: (mif), line:79:8, endln:79:17 |vpiParent: @@ -2821,6 +2820,7 @@ design: (work@interface_modports) |vpiParent: \_hier_path: (mif.datao_mem), line:79:4, endln:79:17 |vpiName:datao_mem + |vpiName:mif.datao_mem |vpiAlwaysType:1 |uhdmtopModules: \_module_inst: work@interface_modports (work@interface_modports), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:112:1, endln:124:10 diff --git a/tests/LhsHierPath/LhsHierPath.log b/tests/LhsHierPath/LhsHierPath.log index 8c9b0746ec..3e192b2cb4 100644 --- a/tests/LhsHierPath/LhsHierPath.log +++ b/tests/LhsHierPath/LhsHierPath.log @@ -388,7 +388,6 @@ design: (work@top) \_hier_path: (ast_alert_o.alerts_ack[0].p), line:14:7, endln:14:34 |vpiParent: \_assignment: , line:14:7, endln:14:41 - |vpiName:ast_alert_o.alerts_ack[0].p |vpiActual: \_ref_obj: (ast_alert_o), line:14:19, endln:14:29 |vpiParent: @@ -412,6 +411,7 @@ design: (work@top) \_hier_path: (ast_alert_o.alerts_ack[0].p), line:14:7, endln:14:34 |vpiName:p |vpiFullName:alerts_ack[0].p + |vpiName:ast_alert_o.alerts_ack[0].p |vpiAlwaysType:2 |vpiContAssign: \_cont_assign: , line:16:11, endln:16:42 @@ -421,7 +421,6 @@ design: (work@top) \_hier_path: (ast_alert_o.alerts_ack[0].p), line:16:15, endln:16:42 |vpiParent: \_cont_assign: , line:16:11, endln:16:42 - |vpiName:ast_alert_o.alerts_ack[0].p |vpiActual: \_ref_obj: (ast_alert_o), line:16:15, endln:16:26 |vpiParent: @@ -445,6 +444,7 @@ design: (work@top) \_hier_path: (ast_alert_o.alerts_ack[0].p), line:16:15, endln:16:42 |vpiName:p |vpiFullName:work@top.p + |vpiName:ast_alert_o.alerts_ack[0].p |vpiLhs: \_ref_obj: (work@top.o), line:16:11, endln:16:12 |vpiParent: @@ -530,7 +530,6 @@ design: (work@top) \_hier_path: (ast_alert_o.alerts_ack[0].p), line:14:7, endln:14:34 |vpiParent: \_assignment: , line:14:7, endln:14:41 - |vpiName:ast_alert_o.alerts_ack[0].p |vpiActual: \_ref_obj: (ast_alert_o), line:14:19, endln:14:29 |vpiParent: @@ -556,6 +555,7 @@ design: (work@top) |vpiFullName:alerts_ack[0].p |vpiActual: \_typespec_member: (p), line:3:13, endln:3:14 + |vpiName:ast_alert_o.alerts_ack[0].p |vpiAlwaysType:2 |vpiContAssign: \_cont_assign: , line:16:11, endln:16:42 @@ -565,7 +565,6 @@ design: (work@top) \_hier_path: (ast_alert_o.alerts_ack[0].p), line:16:15, endln:16:42 |vpiParent: \_cont_assign: , line:16:11, endln:16:42 - |vpiName:ast_alert_o.alerts_ack[0].p |vpiActual: \_ref_obj: (ast_alert_o), line:16:15, endln:16:26 |vpiParent: @@ -591,6 +590,7 @@ design: (work@top) |vpiFullName:work@top.p |vpiActual: \_typespec_member: (p), line:3:13, endln:3:14 + |vpiName:ast_alert_o.alerts_ack[0].p |vpiLhs: \_ref_obj: (work@top.o), line:16:11, endln:16:12 |vpiParent: diff --git a/tests/LhsOp/LhsOp.log b/tests/LhsOp/LhsOp.log index e72730a69c..3ba0d651eb 100644 --- a/tests/LhsOp/LhsOp.log +++ b/tests/LhsOp/LhsOp.log @@ -324,7 +324,6 @@ design: (work@top) \_hier_path: (hw2reg_wrap.class_esc_state), line:12:19, endln:12:46 |vpiParent: \_cont_assign: , line:11:11, endln:12:46 - |vpiName:hw2reg_wrap.class_esc_state |vpiActual: \_ref_obj: (hw2reg_wrap), line:12:19, endln:12:30 |vpiParent: @@ -336,6 +335,7 @@ design: (work@top) \_hier_path: (hw2reg_wrap.class_esc_state), line:12:19, endln:12:46 |vpiName:class_esc_state |vpiFullName:work@top.class_esc_state + |vpiName:hw2reg_wrap.class_esc_state |vpiLhs: \_operation: , line:11:13, endln:11:14 |vpiParent: @@ -484,7 +484,6 @@ design: (work@top) \_hier_path: (hw2reg_wrap.class_esc_state), line:12:19, endln:12:46 |vpiParent: \_cont_assign: , line:11:11, endln:12:46 - |vpiName:hw2reg_wrap.class_esc_state |vpiActual: \_ref_obj: (hw2reg_wrap), line:12:19, endln:12:30 |vpiParent: @@ -500,6 +499,7 @@ design: (work@top) |vpiFullName:work@top.class_esc_state |vpiActual: \_typespec_member: (class_esc_state), line:6:22, endln:6:37 + |vpiName:hw2reg_wrap.class_esc_state |vpiLhs: \_operation: , line:11:13, endln:11:14 |vpiParent: diff --git a/tests/LibraryIntercon/LibraryIntercon.log b/tests/LibraryIntercon/LibraryIntercon.log index 871913ce90..696ff2120a 100644 --- a/tests/LibraryIntercon/LibraryIntercon.log +++ b/tests/LibraryIntercon/LibraryIntercon.log @@ -99,8 +99,7 @@ Instance tree: always 2 array_typespec 4 array_var 4 -assign_stmt 2 -assignment 13 +assignment 15 begin 5 bit_select 14 class_defn 8 diff --git a/tests/LocalScopeAssign/LocalScopeAssign.log b/tests/LocalScopeAssign/LocalScopeAssign.log index cb1d012304..02feb8e9b1 100644 --- a/tests/LocalScopeAssign/LocalScopeAssign.log +++ b/tests/LocalScopeAssign/LocalScopeAssign.log @@ -188,7 +188,6 @@ design: (work@module_scope_Example) \_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34 |vpiParent: \_cont_assign: , line:7:11, endln:7:39 - |vpiName:module_scope_Example.o2 |vpiActual: \_ref_obj: (module_scope_Example), line:7:32, endln:7:34 |vpiParent: @@ -199,6 +198,7 @@ design: (work@module_scope_Example) |vpiParent: \_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34 |vpiName:o2 + |vpiName:module_scope_Example.o2 |uhdmtopModules: \_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10 |vpiName:work@module_scope_Example @@ -293,7 +293,6 @@ design: (work@module_scope_Example) \_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34 |vpiParent: \_cont_assign: , line:7:11, endln:7:39 - |vpiName:module_scope_Example.o2 |vpiActual: \_ref_obj: (module_scope_Example), line:7:32, endln:7:34 |vpiParent: @@ -308,6 +307,7 @@ design: (work@module_scope_Example) |vpiName:o2 |vpiActual: \_logic_net: (work@module_scope_Example.o2), line:3:33, endln:3:35 + |vpiName:module_scope_Example.o2 \_weaklyReferenced: \_logic_typespec: , line:4:11, endln:4:22 |vpiRange: diff --git a/tests/LocalScopeHierPath/LocalScopeHierPath.log b/tests/LocalScopeHierPath/LocalScopeHierPath.log index 14f7772bf2..185902b597 100644 --- a/tests/LocalScopeHierPath/LocalScopeHierPath.log +++ b/tests/LocalScopeHierPath/LocalScopeHierPath.log @@ -152,7 +152,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 3 +assignment 3 begin 3 bit_select 2 class_defn 2 @@ -179,7 +179,7 @@ unsupported_typespec 3 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 5 -assign_stmt 5 +assignment 5 begin 6 bit_select 4 class_defn 2 @@ -447,13 +447,15 @@ design: (unnamed) |vpiName:path |vpiFullName:pack::uvm_mem_mam::check_reg::path |vpiStmt: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:16:21, endln:21:6 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_bit_select: (pack::uvm_mem_mam::check_reg::paths), line:17:36, endln:17:37 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiName:paths |vpiFullName:pack::uvm_mem_mam::check_reg::paths |vpiActual: @@ -469,7 +471,7 @@ design: (unnamed) |vpiLhs: \_class_var: (pack::uvm_mem_mam::check_reg::path), line:17:25, endln:17:29 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::path) |vpiParent: @@ -488,7 +490,6 @@ design: (unnamed) \_hier_path: (path.slices) |vpiParent: \_foreach_stmt: (pack::uvm_mem_mam::check_reg), line:18:5, endln:18:12 - |vpiFullName:path.slices |vpiActual: \_ref_obj: (pack::uvm_mem_mam::check_reg::path), line:18:14, endln:18:18 |vpiParent: @@ -505,6 +506,7 @@ design: (unnamed) |vpiFullName:pack::uvm_mem_mam::check_reg::slices |vpiActual: \_array_var: (pack::uvm_hdl_path_concat::slices), line:8:23, endln:8:29 + |vpiFullName:path.slices |vpiLoopVars: \_ref_var: (pack::uvm_mem_mam::check_reg::j), line:18:26, endln:18:27 |vpiParent: @@ -539,14 +541,15 @@ design: (unnamed) |vpiName:p_ |vpiFullName:pack::uvm_mem_mam::check_reg::p_ |vpiStmt: - \_assign_stmt: , line:19:14, endln:19:39 + \_assignment: , line:19:14, endln:19:39 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:18:30, endln:20:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (path.slices[j].spath), line:19:19, endln:19:39 |vpiParent: - \_assign_stmt: , line:19:14, endln:19:39 - |vpiName:path.slices[j].spath + \_assignment: , line:19:14, endln:19:39 |vpiActual: \_ref_obj: (path), line:19:19, endln:19:23 |vpiParent: @@ -578,10 +581,11 @@ design: (unnamed) |vpiFullName:pack::uvm_mem_mam::check_reg::spath |vpiActual: \_typespec_member: (spath), line:4:11, endln:4:16 + |vpiName:path.slices[j].spath |vpiLhs: \_string_var: (pack::uvm_mem_mam::check_reg::p_), line:19:14, endln:19:16 |vpiParent: - \_assign_stmt: , line:19:14, endln:19:39 + \_assignment: , line:19:14, endln:19:39 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::p_) |vpiParent: @@ -677,7 +681,7 @@ design: (unnamed) |vpiVariables: \_class_var: (pack::uvm_mem_mam::check_reg::path), line:17:25, endln:17:29 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::path) |vpiParent: @@ -688,13 +692,15 @@ design: (unnamed) |vpiName:path |vpiFullName:pack::uvm_mem_mam::check_reg::path |vpiStmt: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:16:21, endln:21:6 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_bit_select: (pack::uvm_mem_mam::check_reg::paths), line:17:36, endln:17:37 |vpiParent: - \_assign_stmt: , line:17:25, endln:17:38 + \_assignment: , line:17:25, endln:17:38 |vpiName:paths |vpiFullName:pack::uvm_mem_mam::check_reg::paths |vpiIndex: @@ -714,7 +720,6 @@ design: (unnamed) \_hier_path: (path.slices) |vpiParent: \_foreach_stmt: (pack::uvm_mem_mam::check_reg), line:18:5, endln:18:12 - |vpiFullName:path.slices |vpiActual: \_ref_obj: (pack::uvm_mem_mam::check_reg::path), line:18:14, endln:18:18 |vpiParent: @@ -727,6 +732,7 @@ design: (unnamed) \_hier_path: (path.slices) |vpiName:slices |vpiFullName:pack::uvm_mem_mam::check_reg::slices + |vpiFullName:path.slices |vpiLoopVars: \_ref_var: (pack::uvm_mem_mam::check_reg::j), line:18:26, endln:18:27 |vpiParent: @@ -748,7 +754,7 @@ design: (unnamed) |vpiVariables: \_string_var: (pack::uvm_mem_mam::check_reg::p_), line:19:14, endln:19:16 |vpiParent: - \_assign_stmt: , line:19:14, endln:19:39 + \_assignment: , line:19:14, endln:19:39 |vpiTypespec: \_ref_typespec: (pack::uvm_mem_mam::check_reg::p_) |vpiParent: @@ -759,14 +765,15 @@ design: (unnamed) |vpiName:p_ |vpiFullName:pack::uvm_mem_mam::check_reg::p_ |vpiStmt: - \_assign_stmt: , line:19:14, endln:19:39 + \_assignment: , line:19:14, endln:19:39 |vpiParent: \_begin: (pack::uvm_mem_mam::check_reg), line:18:30, endln:20:8 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_hier_path: (path.slices[j].spath), line:19:19, endln:19:39 |vpiParent: - \_assign_stmt: , line:19:14, endln:19:39 - |vpiName:path.slices[j].spath + \_assignment: , line:19:14, endln:19:39 |vpiActual: \_ref_obj: (path), line:19:19, endln:19:23 |vpiParent: @@ -790,6 +797,7 @@ design: (unnamed) \_hier_path: (path.slices[j].spath), line:19:19, endln:19:39 |vpiName:spath |vpiFullName:pack::uvm_mem_mam::check_reg::spath + |vpiName:path.slices[j].spath |vpiLhs: \_string_var: (pack::uvm_mem_mam::check_reg::p_), line:19:14, endln:19:16 \_function: (pack::uvm_mem_mam::check_reg), line:13:1, endln:13:10 diff --git a/tests/LogicArrayParam/LogicArrayParam.log b/tests/LogicArrayParam/LogicArrayParam.log index 3a438dac94..d0d28a7374 100644 --- a/tests/LogicArrayParam/LogicArrayParam.log +++ b/tests/LogicArrayParam/LogicArrayParam.log @@ -252,7 +252,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 8. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 41 bit_typespec 8 @@ -282,7 +282,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 41 bit_typespec 8 @@ -746,7 +746,7 @@ design: (work@alert_handler) |vpiParent: \_module_inst: work@alert_handler (work@alert_handler), file:${SURELOG_DIR}/tests/LogicArrayParam/dut.sv, line:20:1, endln:32:10 |vpiForInitStmt: - \_assign_stmt: , line:25:8, endln:25:20 + \_assignment: , line:25:8, endln:25:20 |vpiParent: \_gen_for: |vpiRhs: @@ -758,7 +758,7 @@ design: (work@alert_handler) |vpiLhs: \_int_var: (work@alert_handler.k), line:25:15, endln:25:16 |vpiParent: - \_assign_stmt: , line:25:8, endln:25:20 + \_assignment: , line:25:8, endln:25:20 |vpiTypespec: \_ref_typespec: (work@alert_handler.k) |vpiParent: diff --git a/tests/LogicCast/LogicCast.log b/tests/LogicCast/LogicCast.log index 28c989cb0e..d327060a4c 100644 --- a/tests/LogicCast/LogicCast.log +++ b/tests/LogicCast/LogicCast.log @@ -982,7 +982,6 @@ design: (work@top) \_hier_path: (dmstatus.allnonexistent), line:3:3, endln:3:26 |vpiParent: \_assignment: , line:3:3, endln:3:67 - |vpiName:dmstatus.allnonexistent |vpiActual: \_ref_obj: (dmstatus), line:3:12, endln:3:26 |vpiParent: @@ -993,6 +992,7 @@ design: (work@top) |vpiParent: \_hier_path: (dmstatus.allnonexistent), line:3:3, endln:3:26 |vpiName:allnonexistent + |vpiName:dmstatus.allnonexistent |vpiAlwaysType:2 |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/LogicCast/dut.sv, line:1:1, endln:5:10 @@ -1072,7 +1072,6 @@ design: (work@top) \_hier_path: (dmstatus.allnonexistent), line:3:3, endln:3:26 |vpiParent: \_assignment: , line:3:3, endln:3:67 - |vpiName:dmstatus.allnonexistent |vpiActual: \_ref_obj: (dmstatus), line:3:12, endln:3:26 |vpiParent: @@ -1083,6 +1082,7 @@ design: (work@top) |vpiParent: \_hier_path: (dmstatus.allnonexistent), line:3:3, endln:3:26 |vpiName:allnonexistent + |vpiName:dmstatus.allnonexistent |vpiAlwaysType:2 \_weaklyReferenced: \_integer_typespec: , line:3:36, endln:3:38 diff --git a/tests/ModPortArrayBind/ModPortArrayBind.log b/tests/ModPortArrayBind/ModPortArrayBind.log index 86b315af73..6b33e75bb8 100644 --- a/tests/ModPortArrayBind/ModPortArrayBind.log +++ b/tests/ModPortArrayBind/ModPortArrayBind.log @@ -624,7 +624,6 @@ design: (work@r5p_bus_dec) \_hier_path: (m[i].vld), line:23:10, endln:23:11 |vpiParent: \_cont_assign: , line:23:10, endln:23:38 - |vpiName:m[i].vld |vpiActual: \_bit_select: (m[i]), line:23:10, endln:23:11 |vpiParent: @@ -649,6 +648,7 @@ design: (work@r5p_bus_dec) |vpiFullName:m[i].vld |vpiActual: \_logic_var: (work@r5p_bus_dec.m[0].vld), line:4:17, endln:4:20 + |vpiName:m[i].vld |vpiGenScopeArray: \_gen_scope_array: (work@r5p_bus_dec.gen_loop[1]), line:21:22, endln:25:14 |vpiParent: @@ -716,7 +716,6 @@ design: (work@r5p_bus_dec) \_hier_path: (m[i].vld), line:23:10, endln:23:11 |vpiParent: \_cont_assign: , line:23:10, endln:23:38 - |vpiName:m[i].vld |vpiActual: \_bit_select: (m[i]), line:23:10, endln:23:11 |vpiParent: @@ -741,6 +740,7 @@ design: (work@r5p_bus_dec) |vpiFullName:m[i].vld |vpiActual: \_logic_var: (work@r5p_bus_dec.m[1].vld), line:4:17, endln:4:20 + |vpiName:m[i].vld \_weaklyReferenced: \_int_typespec: , line:13:3, endln:13:15 |vpiParent: @@ -848,7 +848,6 @@ design: (work@r5p_bus_dec) \_hier_path: (m[i].vld), line:23:10, endln:23:11 |vpiParent: \_cont_assign: , line:23:10, endln:23:38 - |vpiName:m[i].vld |vpiActual: \_bit_select: (m[i]), line:23:10, endln:23:11 |vpiParent: @@ -867,6 +866,7 @@ design: (work@r5p_bus_dec) \_hier_path: (m[i].vld), line:23:10, endln:23:11 |vpiName:vld |vpiFullName:m[i].vld + |vpiName:m[i].vld \_gen_scope: (work@r5p_bus_dec.gen_loop[0]), line:21:22, endln:25:14 |vpiParent: \_gen_scope_array: (work@r5p_bus_dec.gen_loop[0]), line:21:22, endln:25:14 @@ -918,7 +918,6 @@ design: (work@r5p_bus_dec) \_hier_path: (m[i].vld), line:23:10, endln:23:11 |vpiParent: \_cont_assign: , line:23:10, endln:23:38 - |vpiName:m[i].vld |vpiActual: \_bit_select: (m[i]), line:23:10, endln:23:11 |vpiParent: @@ -937,6 +936,7 @@ design: (work@r5p_bus_dec) \_hier_path: (m[i].vld), line:23:10, endln:23:11 |vpiName:vld |vpiFullName:m[i].vld + |vpiName:m[i].vld \_gen_scope: (work@r5p_bus_dec.gen_loop[1]), line:21:22, endln:25:14 |vpiParent: \_gen_scope_array: (work@r5p_bus_dec.gen_loop[1]), line:21:22, endln:25:14 diff --git a/tests/MultiConcatValueSize/MultiConcatValueSize.log b/tests/MultiConcatValueSize/MultiConcatValueSize.log index 0288ebd48f..0468d4c7d6 100644 --- a/tests/MultiConcatValueSize/MultiConcatValueSize.log +++ b/tests/MultiConcatValueSize/MultiConcatValueSize.log @@ -762,7 +762,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 1 class_defn 8 class_typespec 4 @@ -808,7 +808,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 1 class_defn 8 class_typespec 4 @@ -2062,7 +2062,7 @@ design: (work@top) |vpiParent: \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/MultiConcatValueSize/dut.sv, line:41:1, endln:50:10 |vpiForInitStmt: - \_assign_stmt: , line:45:8, endln:45:20 + \_assignment: , line:45:8, endln:45:20 |vpiParent: \_gen_for: |vpiRhs: @@ -2074,7 +2074,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@sub_top.k), line:45:15, endln:45:16 |vpiParent: - \_assign_stmt: , line:45:8, endln:45:20 + \_assignment: , line:45:8, endln:45:20 |vpiTypespec: \_ref_typespec: (work@sub_top.k) |vpiParent: diff --git a/tests/MultiIndexBind/MultiIndexBind.log b/tests/MultiIndexBind/MultiIndexBind.log index 91c3cb8ef5..4309470a6b 100644 --- a/tests/MultiIndexBind/MultiIndexBind.log +++ b/tests/MultiIndexBind/MultiIndexBind.log @@ -364,7 +364,6 @@ design: (work@PreDecodeStage) \_hier_path: (microOps[i][1].operand.intOp.aluCode), line:28:12, endln:28:48 |vpiParent: \_cont_assign: , line:28:8, endln:28:48 - |vpiName:microOps[i][1].operand.intOp.aluCode |vpiActual: \_bit_select: (microOps[i]), line:28:12, endln:28:20 |vpiParent: @@ -408,6 +407,7 @@ design: (work@PreDecodeStage) \_hier_path: (microOps[i][1].operand.intOp.aluCode), line:28:12, endln:28:48 |vpiName:aluCode |vpiFullName:work@PreDecodeStage.aluCode + |vpiName:microOps[i][1].operand.intOp.aluCode |vpiLhs: \_ref_obj: (work@PreDecodeStage.o), line:28:8, endln:28:9 |vpiParent: @@ -497,7 +497,6 @@ design: (work@PreDecodeStage) \_hier_path: (microOps[i][1].operand.intOp.aluCode), line:28:12, endln:28:48 |vpiParent: \_cont_assign: , line:28:8, endln:28:48 - |vpiName:microOps[i][1].operand.intOp.aluCode |vpiActual: \_bit_select: (microOps[i]), line:28:12, endln:28:20 |vpiParent: @@ -543,6 +542,7 @@ design: (work@PreDecodeStage) |vpiFullName:work@PreDecodeStage.aluCode |vpiActual: \_typespec_member: (aluCode), line:11:17, endln:11:24 + |vpiName:microOps[i][1].operand.intOp.aluCode |vpiLhs: \_ref_obj: (work@PreDecodeStage.o), line:28:8, endln:28:9 |vpiParent: diff --git a/tests/NameCollisionBind/NameCollisionBind.log b/tests/NameCollisionBind/NameCollisionBind.log index d9ffdc9a39..443470bf9e 100644 --- a/tests/NameCollisionBind/NameCollisionBind.log +++ b/tests/NameCollisionBind/NameCollisionBind.log @@ -219,7 +219,6 @@ design: (work@CSR_Unit) \_hier_path: (perfCounter.perfCounter.numLoadMiss), line:25:18, endln:25:53 |vpiParent: \_cont_assign: , line:25:9, endln:25:53 - |vpiName:perfCounter.perfCounter.numLoadMiss |vpiActual: \_ref_obj: (perfCounter), line:25:18, endln:25:29 |vpiParent: @@ -236,6 +235,7 @@ design: (work@CSR_Unit) \_hier_path: (perfCounter.perfCounter.numLoadMiss), line:25:18, endln:25:53 |vpiName:numLoadMiss |vpiFullName:work@CSR_Unit.numLoadMiss + |vpiName:perfCounter.perfCounter.numLoadMiss |vpiLhs: \_ref_obj: (work@CSR_Unit.mshrID), line:25:9, endln:25:15 |vpiParent: @@ -349,7 +349,6 @@ design: (work@CSR_Unit) \_hier_path: (perfCounter.perfCounter.numLoadMiss), line:25:18, endln:25:53 |vpiParent: \_cont_assign: , line:25:9, endln:25:53 - |vpiName:perfCounter.perfCounter.numLoadMiss |vpiActual: \_ref_obj: (perfCounter), line:25:18, endln:25:29 |vpiParent: @@ -372,6 +371,7 @@ design: (work@CSR_Unit) |vpiFullName:work@CSR_Unit.numLoadMiss |vpiActual: \_typespec_member: (numLoadMiss), line:6:10, endln:6:21 + |vpiName:perfCounter.perfCounter.numLoadMiss |vpiLhs: \_ref_obj: (work@CSR_Unit.mshrID), line:25:9, endln:25:15 |vpiParent: diff --git a/tests/NamedEventHierPath/NamedEventHierPath.log b/tests/NamedEventHierPath/NamedEventHierPath.log index d64293ab2a..babff85629 100644 --- a/tests/NamedEventHierPath/NamedEventHierPath.log +++ b/tests/NamedEventHierPath/NamedEventHierPath.log @@ -82,8 +82,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 class_defn 1 class_typespec 2 @@ -101,8 +100,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 2 +assignment 3 begin 2 class_defn 1 class_typespec 2 @@ -217,7 +215,6 @@ design: (unnamed) \_hier_path: (e.m_event), line:9:11, endln:9:20 |vpiParent: \_assignment: , line:9:1, endln:9:20 - |vpiName:e.m_event |vpiActual: \_ref_obj: (e), line:9:11, endln:9:12 |vpiParent: @@ -233,6 +230,7 @@ design: (unnamed) |vpiFullName:pack::uvm_event_base::do_copy::m_event |vpiActual: \_named_event: (pack::uvm_event_base::m_event), line:4:23, endln:4:30 + |vpiName:e.m_event |vpiLhs: \_ref_obj: (pack::uvm_event_base::do_copy::m_event), line:9:1, endln:9:8 |vpiParent: diff --git a/tests/NegInt/NegInt.log b/tests/NegInt/NegInt.log index bc251a70cf..6685669007 100644 --- a/tests/NegInt/NegInt.log +++ b/tests/NegInt/NegInt.log @@ -122,7 +122,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 3 constant 10 @@ -143,7 +143,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 begin 1 bit_select 3 constant 10 @@ -219,7 +219,7 @@ design: (work@find_first_one) |vpiParent: \_module_inst: work@find_first_one (work@find_first_one), file:${SURELOG_DIR}/tests/NegInt/dut.sv, line:1:1, endln:5:10 |vpiForInitStmt: - \_assign_stmt: , line:2:10, endln:2:22 + \_assignment: , line:2:10, endln:2:22 |vpiParent: \_gen_for: |vpiRhs: @@ -231,7 +231,7 @@ design: (work@find_first_one) |vpiLhs: \_int_var: (work@find_first_one.i), line:2:17, endln:2:18 |vpiParent: - \_assign_stmt: , line:2:10, endln:2:22 + \_assignment: , line:2:10, endln:2:22 |vpiTypespec: \_ref_typespec: (work@find_first_one.i) |vpiParent: diff --git a/tests/NetLValue/NetLValue.log b/tests/NetLValue/NetLValue.log index 20c3ea7327..5fb0779de7 100644 --- a/tests/NetLValue/NetLValue.log +++ b/tests/NetLValue/NetLValue.log @@ -259,7 +259,6 @@ design: (work@t) \_hier_path: (s[0].x), line:7:10, endln:7:16 |vpiParent: \_assignment: , line:7:6, endln:7:16 - |vpiName:s[0].x |vpiActual: \_bit_select: (s[0]), line:7:10, endln:7:11 |vpiParent: @@ -278,6 +277,7 @@ design: (work@t) \_hier_path: (s[0].x), line:7:10, endln:7:16 |vpiName:x |vpiFullName:work@t.x + |vpiName:s[0].x |vpiLhs: \_ref_obj: (work@t.y), line:7:6, endln:7:7 |vpiParent: @@ -302,7 +302,6 @@ design: (work@t) \_hier_path: (s[1].x), line:8:6, endln:8:7 |vpiParent: \_assignment: , line:8:6, endln:8:16 - |vpiName:s[1].x |vpiActual: \_bit_select: (s[1]), line:8:6, endln:8:7 |vpiParent: @@ -321,6 +320,7 @@ design: (work@t) \_hier_path: (s[1].x), line:8:6, endln:8:7 |vpiName:x |vpiFullName:s[1].x + |vpiName:s[1].x |vpiAlwaysType:2 |uhdmtopModules: \_module_inst: work@t (work@t), file:${SURELOG_DIR}/tests/NetLValue/dut.sv, line:1:1, endln:10:10 @@ -402,7 +402,6 @@ design: (work@t) \_hier_path: (s[0].x), line:7:10, endln:7:16 |vpiParent: \_assignment: , line:7:6, endln:7:16 - |vpiName:s[0].x |vpiActual: \_bit_select: (s[0]), line:7:10, endln:7:11 |vpiParent: @@ -421,6 +420,7 @@ design: (work@t) |vpiFullName:work@t.x |vpiActual: \_typespec_member: (x), line:2:25, endln:2:26 + |vpiName:s[0].x |vpiLhs: \_ref_obj: (work@t.y), line:7:6, endln:7:7 |vpiParent: @@ -441,7 +441,6 @@ design: (work@t) \_hier_path: (s[1].x), line:8:6, endln:8:7 |vpiParent: \_assignment: , line:8:6, endln:8:16 - |vpiName:s[1].x |vpiActual: \_bit_select: (s[1]), line:8:6, endln:8:7 |vpiParent: @@ -460,6 +459,7 @@ design: (work@t) |vpiFullName:s[1].x |vpiActual: \_typespec_member: (x), line:2:25, endln:2:26 + |vpiName:s[1].x |vpiAlwaysType:2 \_weaklyReferenced: \_int_typespec: , line:2:21, endln:2:24 diff --git a/tests/NetType/NetType.log b/tests/NetType/NetType.log index a182974481..afd2fcab4c 100644 --- a/tests/NetType/NetType.log +++ b/tests/NetType/NetType.log @@ -533,7 +533,6 @@ design: (work@dut) \_hier_path: (Tsum.field1), line:29:3, endln:29:14 |vpiParent: \_assignment: , line:29:3, endln:29:20 - |vpiName:Tsum.field1 |vpiActual: \_ref_obj: (Tsum), line:29:8, endln:29:14 |vpiParent: @@ -546,6 +545,7 @@ design: (work@dut) |vpiParent: \_hier_path: (Tsum.field1), line:29:3, endln:29:14 |vpiName:field1 + |vpiName:Tsum.field1 |vpiStmt: \_foreach_stmt: (Tsum), line:30:3, endln:30:10 |vpiParent: @@ -587,7 +587,6 @@ design: (work@dut) \_hier_path: (driver[i].field1), line:31:20, endln:31:36 |vpiParent: \_assignment: , line:31:5, endln:31:36 - |vpiName:driver[i].field1 |vpiActual: \_bit_select: (driver[i]), line:31:20, endln:31:26 |vpiParent: @@ -610,11 +609,11 @@ design: (work@dut) \_hier_path: (driver[i].field1), line:31:20, endln:31:36 |vpiName:field1 |vpiFullName:Tsum.field1 + |vpiName:driver[i].field1 |vpiLhs: \_hier_path: (Tsum.field1), line:31:5, endln:31:16 |vpiParent: \_assignment: , line:31:5, endln:31:36 - |vpiName:Tsum.field1 |vpiActual: \_ref_obj: (Tsum), line:31:10, endln:31:16 |vpiParent: @@ -627,6 +626,7 @@ design: (work@dut) |vpiParent: \_hier_path: (Tsum.field1), line:31:5, endln:31:16 |vpiName:field1 + |vpiName:Tsum.field1 |vpiTaskFunc: \_function: (my_function), line:3:1, endln:4:12 |vpiTaskFunc: diff --git a/tests/NoReducTypespec/NoReducTypespec.log b/tests/NoReducTypespec/NoReducTypespec.log index efa9c20bed..a8699bcbfb 100644 --- a/tests/NoReducTypespec/NoReducTypespec.log +++ b/tests/NoReducTypespec/NoReducTypespec.log @@ -644,7 +644,6 @@ design: (work@cheshire_soc) \_hier_path: (Cfg.NoSlvPorts), line:12:21, endln:12:35 |vpiParent: \_param_assign: , line:12:13, endln:12:35 - |vpiName:Cfg.NoSlvPorts |vpiActual: \_ref_obj: (Cfg), line:12:25, endln:12:35 |vpiParent: @@ -655,6 +654,7 @@ design: (work@cheshire_soc) |vpiParent: \_hier_path: (Cfg.NoSlvPorts), line:12:21, endln:12:35 |vpiName:NoSlvPorts + |vpiName:Cfg.NoSlvPorts |vpiLhs: \_parameter: (work@axi_xbar.DEBUG), line:12:13, endln:12:18 |vpiParamAssign: @@ -1041,7 +1041,6 @@ design: (work@cheshire_soc) \_hier_path: (Cfg.NoSlvPorts), line:13:18, endln:13:32 |vpiParent: \_operation: , line:13:18, endln:13:34 - |vpiName:Cfg.NoSlvPorts |vpiActual: \_ref_obj: (Cfg), line:13:22, endln:13:32 |vpiParent: @@ -1052,6 +1051,7 @@ design: (work@cheshire_soc) |vpiParent: \_hier_path: (Cfg.NoSlvPorts), line:13:18, endln:13:32 |vpiName:NoSlvPorts + |vpiName:Cfg.NoSlvPorts |vpiOperand: \_constant: , line:13:33, endln:13:34 |vpiParent: @@ -1081,7 +1081,6 @@ design: (work@cheshire_soc) \_hier_path: (Cfg.NoMstPorts), line:13:38, endln:13:52 |vpiParent: \_operation: , line:13:38, endln:13:54 - |vpiName:Cfg.NoMstPorts |vpiActual: \_ref_obj: (Cfg), line:13:42, endln:13:52 |vpiParent: @@ -1092,6 +1091,7 @@ design: (work@cheshire_soc) |vpiParent: \_hier_path: (Cfg.NoMstPorts), line:13:38, endln:13:52 |vpiName:NoMstPorts + |vpiName:Cfg.NoMstPorts |vpiOperand: \_constant: , line:13:53, endln:13:54 |vpiParent: @@ -1754,7 +1754,6 @@ design: (work@cheshire_soc) \_hier_path: (Cfg.NoSlvPorts), line:13:18, endln:13:32 |vpiParent: \_operation: , line:13:18, endln:13:34 - |vpiName:Cfg.NoSlvPorts |vpiActual: \_ref_obj: (Cfg), line:13:22, endln:13:32 |vpiParent: @@ -1767,6 +1766,7 @@ design: (work@cheshire_soc) |vpiParent: \_hier_path: (Cfg.NoSlvPorts), line:13:18, endln:13:32 |vpiName:NoSlvPorts + |vpiName:Cfg.NoSlvPorts |vpiOperand: \_constant: , line:13:33, endln:13:34 |vpiParent: @@ -1796,7 +1796,6 @@ design: (work@cheshire_soc) \_hier_path: (Cfg.NoMstPorts), line:13:38, endln:13:52 |vpiParent: \_operation: , line:13:38, endln:13:54 - |vpiName:Cfg.NoMstPorts |vpiActual: \_ref_obj: (Cfg), line:13:42, endln:13:52 |vpiParent: @@ -1809,6 +1808,7 @@ design: (work@cheshire_soc) |vpiParent: \_hier_path: (Cfg.NoMstPorts), line:13:38, endln:13:52 |vpiName:NoMstPorts + |vpiName:Cfg.NoMstPorts |vpiOperand: \_constant: , line:13:53, endln:13:54 |vpiParent: diff --git a/tests/NonAnsiPort/NonAnsiPort.log b/tests/NonAnsiPort/NonAnsiPort.log index 175fe8369a..f9e4431986 100644 --- a/tests/NonAnsiPort/NonAnsiPort.log +++ b/tests/NonAnsiPort/NonAnsiPort.log @@ -510,7 +510,6 @@ design: (work@dut) \_hier_path: (var1.first), line:22:12, endln:22:22 |vpiParent: \_cont_assign: , line:22:12, endln:22:28 - |vpiName:var1.first |vpiActual: \_ref_obj: (var1), line:22:17, endln:22:22 |vpiParent: @@ -521,6 +520,7 @@ design: (work@dut) |vpiParent: \_hier_path: (var1.first), line:22:12, endln:22:22 |vpiName:first + |vpiName:var1.first |vpiContAssign: \_cont_assign: , line:23:12, endln:23:29 |vpiParent: @@ -537,7 +537,6 @@ design: (work@dut) \_hier_path: (var2.second), line:23:12, endln:23:23 |vpiParent: \_cont_assign: , line:23:12, endln:23:29 - |vpiName:var2.second |vpiActual: \_ref_obj: (var2), line:23:17, endln:23:23 |vpiParent: @@ -548,6 +547,7 @@ design: (work@dut) |vpiParent: \_hier_path: (var2.second), line:23:12, endln:23:23 |vpiName:second + |vpiName:var2.second |vpiContAssign: \_cont_assign: , line:24:12, endln:24:27 |vpiParent: @@ -564,7 +564,6 @@ design: (work@dut) \_hier_path: (var3.third), line:24:12, endln:24:22 |vpiParent: \_cont_assign: , line:24:12, endln:24:27 - |vpiName:var3.third |vpiActual: \_ref_obj: (var3), line:24:17, endln:24:22 |vpiParent: @@ -575,6 +574,7 @@ design: (work@dut) |vpiParent: \_hier_path: (var3.third), line:24:12, endln:24:22 |vpiName:third + |vpiName:var3.third |uhdmtopModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/NonAnsiPort/dut.sv, line:13:1, endln:25:10 |vpiName:work@dut @@ -697,7 +697,6 @@ design: (work@dut) \_hier_path: (var1.first), line:22:12, endln:22:22 |vpiParent: \_cont_assign: , line:22:12, endln:22:28 - |vpiName:var1.first |vpiActual: \_ref_obj: (var1), line:22:17, endln:22:22 |vpiParent: @@ -708,6 +707,7 @@ design: (work@dut) |vpiParent: \_hier_path: (var1.first), line:22:12, endln:22:22 |vpiName:first + |vpiName:var1.first |vpiContAssign: \_cont_assign: , line:23:12, endln:23:29 |vpiParent: @@ -718,7 +718,6 @@ design: (work@dut) \_hier_path: (var2.second), line:23:12, endln:23:23 |vpiParent: \_cont_assign: , line:23:12, endln:23:29 - |vpiName:var2.second |vpiActual: \_ref_obj: (var2), line:23:17, endln:23:23 |vpiParent: @@ -729,6 +728,7 @@ design: (work@dut) |vpiParent: \_hier_path: (var2.second), line:23:12, endln:23:23 |vpiName:second + |vpiName:var2.second |vpiContAssign: \_cont_assign: , line:24:12, endln:24:27 |vpiParent: @@ -739,7 +739,6 @@ design: (work@dut) \_hier_path: (var3.third), line:24:12, endln:24:22 |vpiParent: \_cont_assign: , line:24:12, endln:24:27 - |vpiName:var3.third |vpiActual: \_ref_obj: (var3), line:24:17, endln:24:22 |vpiParent: @@ -750,6 +749,7 @@ design: (work@dut) |vpiParent: \_hier_path: (var3.third), line:24:12, endln:24:22 |vpiName:third + |vpiName:var3.third \_weaklyReferenced: \_logic_typespec: , line:3:9, endln:3:20 |vpiParent: diff --git a/tests/OneNetInterf/OneNetInterf.log b/tests/OneNetInterf/OneNetInterf.log index f7d40d9a46..a886188fb5 100644 --- a/tests/OneNetInterf/OneNetInterf.log +++ b/tests/OneNetInterf/OneNetInterf.log @@ -673,7 +673,6 @@ design: (work@dut) \_hier_path: (conn.con_i), line:11:17, endln:11:27 |vpiParent: \_port: (inp), line:11:12, endln:11:28 - |vpiName:conn.con_i |vpiActual: \_ref_obj: (conn), line:11:17, endln:11:21 |vpiParent: @@ -685,6 +684,7 @@ design: (work@dut) \_hier_path: (conn.con_i), line:11:17, endln:11:27 |vpiName:con_i |vpiFullName:work@middle.sub1.inp.con_i + |vpiName:conn.con_i |vpiPort: \_port: (out), line:11:29, endln:11:45 |vpiParent: @@ -694,7 +694,6 @@ design: (work@dut) \_hier_path: (conn.con_o), line:11:34, endln:11:44 |vpiParent: \_port: (out), line:11:29, endln:11:45 - |vpiName:conn.con_o |vpiActual: \_ref_obj: (conn), line:11:34, endln:11:38 |vpiParent: @@ -706,6 +705,7 @@ design: (work@dut) \_hier_path: (conn.con_o), line:11:34, endln:11:44 |vpiName:con_o |vpiFullName:work@middle.sub1.out.con_o + |vpiName:conn.con_o |uhdmallModules: \_module_inst: work@tb (work@tb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:14:1, endln:19:10 |vpiParent: @@ -818,7 +818,6 @@ design: (work@dut) \_hier_path: (conntb.con_o), line:18:25, endln:18:37 |vpiParent: \_port: (observe), line:18:16, endln:18:38 - |vpiName:conntb.con_o |vpiActual: \_ref_obj: (conntb), line:18:25, endln:18:31 |vpiParent: @@ -830,6 +829,7 @@ design: (work@dut) \_hier_path: (conntb.con_o), line:18:25, endln:18:37 |vpiName:con_o |vpiFullName:work@tb.tb.observe.con_o + |vpiName:conntb.con_o |vpiPort: \_port: (drive), line:18:39, endln:18:59 |vpiParent: @@ -839,7 +839,6 @@ design: (work@dut) \_hier_path: (conntb.con_i), line:18:46, endln:18:58 |vpiParent: \_port: (drive), line:18:39, endln:18:59 - |vpiName:conntb.con_i |vpiActual: \_ref_obj: (conntb), line:18:46, endln:18:52 |vpiParent: @@ -851,6 +850,7 @@ design: (work@dut) \_hier_path: (conntb.con_i), line:18:46, endln:18:58 |vpiName:con_i |vpiFullName:work@tb.tb.drive.con_i + |vpiName:conntb.con_i |uhdmtopModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:2:1, endln:5:10 |vpiName:work@dut @@ -1169,12 +1169,6 @@ design: (work@dut) \_hier_path: (conn.con_i), line:11:17, endln:11:27 |vpiParent: \_port: (inp), line:14:24, endln:14:27 - |vpiName:conn.con_i - |vpiExpr: - \_ref_obj: (work@dut.middle1.conn), line:4:18, endln:4:24 - |vpiFullName:work@dut.middle1.conn - |vpiActual: - \_interface_inst: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 |vpiActual: \_ref_obj: (conn), line:11:17, endln:11:21 |vpiParent: @@ -1192,6 +1186,10 @@ design: (work@dut) \_logic_net: (con_i), line:7:33, endln:7:38 |vpiExpr: \_ref_obj: (work@dut.middle1.conn), line:4:18, endln:4:24 + |vpiFullName:work@dut.middle1.conn + |vpiActual: + \_interface_inst: work@ConnectTB (work@dut.middle1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:4:0 + |vpiName:conn.con_i |vpiLowConn: \_ref_obj: (work@dut.middle1.sub1.inp), line:11:13, endln:11:16 |vpiParent: @@ -1219,9 +1217,6 @@ design: (work@dut) \_hier_path: (conn.con_o), line:11:34, endln:11:44 |vpiParent: \_port: (out), line:14:40, endln:14:43 - |vpiName:conn.con_o - |vpiExpr: - \_ref_obj: (work@dut.middle1.conn), line:4:18, endln:4:24 |vpiActual: \_ref_obj: (conn), line:11:34, endln:11:38 |vpiParent: @@ -1239,6 +1234,7 @@ design: (work@dut) \_logic_net: (con_o), line:7:51, endln:7:56 |vpiExpr: \_ref_obj: (work@dut.middle1.conn), line:4:18, endln:4:24 + |vpiName:conn.con_o |vpiLowConn: \_ref_obj: (work@dut.middle1.sub1.out), line:11:30, endln:11:33 |vpiParent: @@ -1332,7 +1328,6 @@ design: (work@dut) \_hier_path: (conntb.con_o), line:18:25, endln:18:37 |vpiParent: \_port: (observe), line:1:30, endln:1:37 - |vpiName:conntb.con_o |vpiActual: \_ref_obj: (conntb), line:18:25, endln:18:31 |vpiParent: @@ -1346,6 +1341,7 @@ design: (work@dut) \_hier_path: (conntb.con_o), line:18:25, endln:18:37 |vpiName:con_o |vpiFullName:work@tb.tb.observe.con_o + |vpiName:conntb.con_o |vpiLowConn: \_ref_obj: (work@tb.tb.observe), line:18:17, endln:18:24 |vpiParent: @@ -1371,7 +1367,6 @@ design: (work@dut) \_hier_path: (conntb.con_i), line:18:46, endln:18:58 |vpiParent: \_port: (drive), line:1:50, endln:1:55 - |vpiName:conntb.con_i |vpiActual: \_ref_obj: (conntb), line:18:46, endln:18:52 |vpiParent: @@ -1385,6 +1380,7 @@ design: (work@dut) \_hier_path: (conntb.con_i), line:18:46, endln:18:58 |vpiName:con_i |vpiFullName:work@tb.tb.drive.con_i + |vpiName:conntb.con_i |vpiLowConn: \_ref_obj: (work@tb.tb.drive), line:18:40, endln:18:45 |vpiParent: @@ -1667,12 +1663,6 @@ design: (work@dut) \_hier_path: (conn.con_i), line:11:17, endln:11:27 |vpiParent: \_port: (inp), line:14:24, endln:14:27 - |vpiName:conn.con_i - |vpiExpr: - \_ref_obj: (work@tb.dut1.conn), line:17:15, endln:17:21 - |vpiFullName:work@tb.dut1.conn - |vpiActual: - \_interface_inst: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 |vpiActual: \_ref_obj: (conn), line:11:17, endln:11:21 |vpiParent: @@ -1690,6 +1680,10 @@ design: (work@dut) \_logic_net: (con_i), line:7:33, endln:7:38 |vpiExpr: \_ref_obj: (work@tb.dut1.conn), line:17:15, endln:17:21 + |vpiFullName:work@tb.dut1.conn + |vpiActual: + \_interface_inst: work@ConnectTB (work@tb.dut1.conn), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:17:0 + |vpiName:conn.con_i |vpiLowConn: \_ref_obj: (work@tb.dut1.sub1.inp), line:11:13, endln:11:16 |vpiParent: @@ -1717,9 +1711,6 @@ design: (work@dut) \_hier_path: (conn.con_o), line:11:34, endln:11:44 |vpiParent: \_port: (out), line:14:40, endln:14:43 - |vpiName:conn.con_o - |vpiExpr: - \_ref_obj: (work@tb.dut1.conn), line:17:15, endln:17:21 |vpiActual: \_ref_obj: (conn), line:11:34, endln:11:38 |vpiParent: @@ -1737,6 +1728,7 @@ design: (work@dut) \_logic_net: (con_o), line:7:51, endln:7:56 |vpiExpr: \_ref_obj: (work@tb.dut1.conn), line:17:15, endln:17:21 + |vpiName:conn.con_o |vpiLowConn: \_ref_obj: (work@tb.dut1.sub1.out), line:11:30, endln:11:33 |vpiParent: diff --git a/tests/OneNetModPort/OneNetModPort.log b/tests/OneNetModPort/OneNetModPort.log index d13b271d14..41274caac3 100644 --- a/tests/OneNetModPort/OneNetModPort.log +++ b/tests/OneNetModPort/OneNetModPort.log @@ -176,7 +176,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:5:46, endln:5:56 |vpiParent: \_sys_func_call: ($monitor), line:5:5, endln:5:71 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:5:46, endln:5:50 |vpiParent: @@ -188,11 +187,11 @@ design: (work@TOP) \_hier_path: (intf.drive), line:5:46, endln:5:56 |vpiName:drive |vpiFullName:work@TOP.tb.drive + |vpiName:intf.drive |vpiArgument: \_hier_path: (intf.observe), line:5:58, endln:5:70 |vpiParent: \_sys_func_call: ($monitor), line:5:5, endln:5:71 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:5:58, endln:5:62 |vpiParent: @@ -204,6 +203,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:5:58, endln:5:70 |vpiName:observe |vpiFullName:work@TOP.tb.observe + |vpiName:intf.observe |vpiName:$monitor |vpiStmt: \_assignment: , line:6:5, endln:6:19 @@ -221,7 +221,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:6:5, endln:6:15 |vpiParent: \_assignment: , line:6:5, endln:6:19 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:6:10, endln:6:15 |vpiParent: @@ -232,6 +231,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (intf.drive), line:6:5, endln:6:15 |vpiName:drive + |vpiName:intf.drive |vpiStmt: \_delay_control: , line:7:5, endln:7:7 |vpiParent: @@ -250,7 +250,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:7:15, endln:7:25 |vpiParent: \_operation: , line:7:15, endln:7:41 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:7:15, endln:7:19 |vpiParent: @@ -262,11 +261,11 @@ design: (work@TOP) \_hier_path: (intf.drive), line:7:15, endln:7:25 |vpiName:drive |vpiFullName:work@TOP.tb.drive + |vpiName:intf.drive |vpiOperand: \_hier_path: (intf.observe), line:7:29, endln:7:41 |vpiParent: \_operation: , line:7:15, endln:7:41 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:7:29, endln:7:33 |vpiParent: @@ -278,6 +277,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:7:29, endln:7:41 |vpiName:observe |vpiFullName:work@TOP.tb.observe + |vpiName:intf.observe |vpiStmt: \_sys_func_call: ($display), line:7:43, endln:7:58 |vpiParent: @@ -333,7 +333,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:8:10, endln:8:20 |vpiParent: \_assignment: , line:8:10, endln:8:24 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:8:15, endln:8:20 |vpiParent: @@ -344,6 +343,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (intf.drive), line:8:10, endln:8:20 |vpiName:drive + |vpiName:intf.drive |vpiStmt: \_delay_control: , line:9:5, endln:9:7 |vpiParent: @@ -362,7 +362,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:9:15, endln:9:25 |vpiParent: \_operation: , line:9:15, endln:9:41 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:9:15, endln:9:19 |vpiParent: @@ -374,11 +373,11 @@ design: (work@TOP) \_hier_path: (intf.drive), line:9:15, endln:9:25 |vpiName:drive |vpiFullName:work@TOP.tb.drive + |vpiName:intf.drive |vpiOperand: \_hier_path: (intf.observe), line:9:29, endln:9:41 |vpiParent: \_operation: , line:9:15, endln:9:41 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:9:29, endln:9:33 |vpiParent: @@ -390,6 +389,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:9:29, endln:9:41 |vpiName:observe |vpiFullName:work@TOP.tb.observe + |vpiName:intf.observe |vpiStmt: \_sys_func_call: ($display), line:9:43, endln:9:58 |vpiParent: @@ -654,7 +654,6 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:3:10, endln:3:22 |vpiParent: \_cont_assign: , line:3:10, endln:3:26 - |vpiName:conntb.drive |vpiActual: \_ref_obj: (conntb), line:3:17, endln:3:22 |vpiParent: @@ -665,6 +664,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (conntb.drive), line:3:10, endln:3:22 |vpiName:drive + |vpiName:conntb.drive |vpiContAssign: \_cont_assign: , line:4:10, endln:4:28 |vpiParent: @@ -673,7 +673,6 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:4:14, endln:4:28 |vpiParent: \_cont_assign: , line:4:10, endln:4:28 - |vpiName:conntb.observe |vpiActual: \_ref_obj: (conntb), line:4:14, endln:4:20 |vpiParent: @@ -685,6 +684,7 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:4:14, endln:4:28 |vpiName:observe |vpiFullName:work@dut.observe + |vpiName:conntb.observe |vpiLhs: \_ref_obj: (work@dut.o), line:4:10, endln:4:11 |vpiParent: @@ -771,7 +771,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:23:17, endln:23:27 |vpiParent: \_port: (inp), line:23:12, endln:23:28 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:23:17, endln:23:21 |vpiParent: @@ -783,6 +782,7 @@ design: (work@TOP) \_hier_path: (intf.drive), line:23:17, endln:23:27 |vpiName:drive |vpiFullName:work@middle.sub1.inp.drive + |vpiName:intf.drive |vpiPort: \_port: (out), line:23:30, endln:23:48 |vpiParent: @@ -792,7 +792,6 @@ design: (work@TOP) \_hier_path: (intf.observe), line:23:35, endln:23:47 |vpiParent: \_port: (out), line:23:30, endln:23:48 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:23:35, endln:23:39 |vpiParent: @@ -804,6 +803,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:23:35, endln:23:47 |vpiName:observe |vpiFullName:work@middle.sub1.out.observe + |vpiName:intf.observe |uhdmtopModules: \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10 |vpiName:work@TOP @@ -977,7 +977,6 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:17:12, endln:17:24 |vpiParent: \_port: (i), line:2:24, endln:2:25 - |vpiName:conntb.drive |vpiActual: \_ref_obj: (conntb), line:17:19, endln:17:24 |vpiParent: @@ -988,6 +987,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (conntb.drive), line:17:12, endln:17:24 |vpiName:drive + |vpiName:conntb.drive |vpiLowConn: \_ref_obj: (work@TOP.dut1.i), line:2:24, endln:2:25 |vpiParent: @@ -1013,7 +1013,6 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:17:26, endln:17:40 |vpiParent: \_port: (o), line:2:38, endln:2:39 - |vpiName:conntb.observe |vpiActual: \_ref_obj: (conntb), line:17:26, endln:17:32 |vpiParent: @@ -1025,6 +1024,7 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:17:26, endln:17:40 |vpiName:observe |vpiFullName:work@TOP.dut1.o.observe + |vpiName:conntb.observe |vpiLowConn: \_ref_obj: (work@TOP.dut1.o), line:2:38, endln:2:39 |vpiParent: @@ -1263,9 +1263,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:23:17, endln:23:27 |vpiParent: \_port: (inp), line:26:24, endln:26:27 - |vpiName:intf.drive - |vpiExpr: - \_ref_obj: (work@TOP.dut1.middle1.intf), line:6:18, endln:6:24 |vpiActual: \_ref_obj: (intf), line:23:17, endln:23:21 |vpiParent: @@ -1279,6 +1276,7 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.inp.drive |vpiExpr: \_ref_obj: (work@TOP.dut1.middle1.intf), line:6:18, endln:6:24 + |vpiName:intf.drive |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.sub1.inp), line:23:13, endln:23:16 |vpiParent: @@ -1304,9 +1302,6 @@ design: (work@TOP) \_hier_path: (intf.observe), line:23:35, endln:23:47 |vpiParent: \_port: (out), line:26:40, endln:26:43 - |vpiName:intf.observe - |vpiExpr: - \_ref_obj: (work@TOP.dut1.middle1.intf), line:6:18, endln:6:24 |vpiActual: \_ref_obj: (intf), line:23:35, endln:23:39 |vpiParent: @@ -1320,6 +1315,7 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.out.observe |vpiExpr: \_ref_obj: (work@TOP.dut1.middle1.intf), line:6:18, endln:6:24 + |vpiName:intf.observe |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.sub1.out), line:23:31, endln:23:34 |vpiParent: diff --git a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log index 8ade64a053..c956159b17 100644 --- a/tests/OneNetModPortGeneric/OneNetModPortGeneric.log +++ b/tests/OneNetModPortGeneric/OneNetModPortGeneric.log @@ -186,7 +186,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:5:46, endln:5:56 |vpiParent: \_sys_func_call: ($monitor), line:5:5, endln:5:71 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:5:46, endln:5:50 |vpiParent: @@ -198,11 +197,11 @@ design: (work@TOP) \_hier_path: (intf.drive), line:5:46, endln:5:56 |vpiName:drive |vpiFullName:work@TOP.tb.drive + |vpiName:intf.drive |vpiArgument: \_hier_path: (intf.observe), line:5:58, endln:5:70 |vpiParent: \_sys_func_call: ($monitor), line:5:5, endln:5:71 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:5:58, endln:5:62 |vpiParent: @@ -214,6 +213,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:5:58, endln:5:70 |vpiName:observe |vpiFullName:work@TOP.tb.observe + |vpiName:intf.observe |vpiName:$monitor |vpiStmt: \_assignment: , line:6:5, endln:6:19 @@ -231,7 +231,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:6:5, endln:6:15 |vpiParent: \_assignment: , line:6:5, endln:6:19 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:6:10, endln:6:15 |vpiParent: @@ -242,6 +241,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (intf.drive), line:6:5, endln:6:15 |vpiName:drive + |vpiName:intf.drive |vpiStmt: \_delay_control: , line:7:5, endln:7:7 |vpiParent: @@ -260,7 +260,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:7:15, endln:7:25 |vpiParent: \_operation: , line:7:15, endln:7:41 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:7:15, endln:7:19 |vpiParent: @@ -272,11 +271,11 @@ design: (work@TOP) \_hier_path: (intf.drive), line:7:15, endln:7:25 |vpiName:drive |vpiFullName:work@TOP.tb.drive + |vpiName:intf.drive |vpiOperand: \_hier_path: (intf.observe), line:7:29, endln:7:41 |vpiParent: \_operation: , line:7:15, endln:7:41 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:7:29, endln:7:33 |vpiParent: @@ -288,6 +287,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:7:29, endln:7:41 |vpiName:observe |vpiFullName:work@TOP.tb.observe + |vpiName:intf.observe |vpiStmt: \_sys_func_call: ($display), line:7:43, endln:7:58 |vpiParent: @@ -343,7 +343,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:8:10, endln:8:20 |vpiParent: \_assignment: , line:8:10, endln:8:24 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:8:15, endln:8:20 |vpiParent: @@ -354,6 +353,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (intf.drive), line:8:10, endln:8:20 |vpiName:drive + |vpiName:intf.drive |vpiStmt: \_delay_control: , line:9:5, endln:9:7 |vpiParent: @@ -372,7 +372,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:9:15, endln:9:25 |vpiParent: \_operation: , line:9:15, endln:9:41 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:9:15, endln:9:19 |vpiParent: @@ -384,11 +383,11 @@ design: (work@TOP) \_hier_path: (intf.drive), line:9:15, endln:9:25 |vpiName:drive |vpiFullName:work@TOP.tb.drive + |vpiName:intf.drive |vpiOperand: \_hier_path: (intf.observe), line:9:29, endln:9:41 |vpiParent: \_operation: , line:9:15, endln:9:41 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:9:29, endln:9:33 |vpiParent: @@ -400,6 +399,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:9:29, endln:9:41 |vpiName:observe |vpiFullName:work@TOP.tb.observe + |vpiName:intf.observe |vpiStmt: \_sys_func_call: ($display), line:9:43, endln:9:58 |vpiParent: @@ -506,7 +506,6 @@ design: (work@TOP) \_hier_path: (intf.observe), line:31:17, endln:31:29 |vpiParent: \_cont_assign: , line:31:11, endln:31:29 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:31:17, endln:31:21 |vpiParent: @@ -518,6 +517,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:31:17, endln:31:29 |vpiName:observe |vpiFullName:work@OBSERVER.observe + |vpiName:intf.observe |vpiLhs: \_ref_obj: (work@OBSERVER.obs), line:31:11, endln:31:14 |vpiParent: @@ -646,7 +646,6 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:17:16, endln:17:28 |vpiParent: \_port: (i), line:17:13, endln:17:29 - |vpiName:conntb.drive |vpiActual: \_ref_obj: (conntb), line:17:16, endln:17:22 |vpiParent: @@ -658,6 +657,7 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:17:16, endln:17:28 |vpiName:drive |vpiFullName:work@TOP.dut1.i.drive + |vpiName:conntb.drive |vpiPort: \_port: (o), line:17:31, endln:17:49 |vpiParent: @@ -667,7 +667,6 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:17:34, endln:17:48 |vpiParent: \_port: (o), line:17:31, endln:17:49 - |vpiName:conntb.observe |vpiActual: \_ref_obj: (conntb), line:17:34, endln:17:40 |vpiParent: @@ -679,6 +678,7 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:17:34, endln:17:48 |vpiName:observe |vpiFullName:work@TOP.dut1.o.observe + |vpiName:conntb.observe |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15 |vpiParent: @@ -696,7 +696,6 @@ design: (work@TOP) \_hier_path: (conntb.tb), line:18:22, endln:18:31 |vpiParent: \_port: (intf), line:18:16, endln:18:32 - |vpiName:conntb.tb |vpiActual: \_ref_obj: (conntb), line:18:22, endln:18:28 |vpiParent: @@ -708,6 +707,7 @@ design: (work@TOP) \_hier_path: (conntb.tb), line:18:22, endln:18:31 |vpiName:tb |vpiFullName:work@TOP.tb.intf.tb + |vpiName:conntb.tb |vpiRefModule: \_ref_module: work@OBSERVER (obs), line:19:12, endln:19:15 |vpiParent: @@ -807,7 +807,6 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:3:10, endln:3:22 |vpiParent: \_cont_assign: , line:3:10, endln:3:26 - |vpiName:conntb.drive |vpiActual: \_ref_obj: (conntb), line:3:17, endln:3:22 |vpiParent: @@ -818,6 +817,7 @@ design: (work@TOP) |vpiParent: \_hier_path: (conntb.drive), line:3:10, endln:3:22 |vpiName:drive + |vpiName:conntb.drive |vpiContAssign: \_cont_assign: , line:4:10, endln:4:28 |vpiParent: @@ -826,7 +826,6 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:4:14, endln:4:28 |vpiParent: \_cont_assign: , line:4:10, endln:4:28 - |vpiName:conntb.observe |vpiActual: \_ref_obj: (conntb), line:4:14, endln:4:20 |vpiParent: @@ -838,6 +837,7 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:4:14, endln:4:28 |vpiName:observe |vpiFullName:work@dut.observe + |vpiName:conntb.observe |vpiLhs: \_ref_obj: (work@dut.o), line:4:10, endln:4:11 |vpiParent: @@ -871,7 +871,6 @@ design: (work@TOP) \_hier_path: (conntb.dut), line:6:25, endln:6:35 |vpiParent: \_port: (intf), line:6:19, endln:6:36 - |vpiName:conntb.dut |vpiActual: \_ref_obj: (conntb), line:6:25, endln:6:31 |vpiParent: @@ -883,6 +882,7 @@ design: (work@TOP) \_hier_path: (conntb.dut), line:6:25, endln:6:35 |vpiName:dut |vpiFullName:work@dut.middle1.intf.dut + |vpiName:conntb.dut |uhdmallModules: \_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/dut.v, line:22:1, endln:24:10 |vpiParent: @@ -933,7 +933,6 @@ design: (work@TOP) \_hier_path: (intf.drive), line:23:17, endln:23:27 |vpiParent: \_port: (inp), line:23:12, endln:23:28 - |vpiName:intf.drive |vpiActual: \_ref_obj: (intf), line:23:17, endln:23:21 |vpiParent: @@ -945,6 +944,7 @@ design: (work@TOP) \_hier_path: (intf.drive), line:23:17, endln:23:27 |vpiName:drive |vpiFullName:work@middle.sub1.inp.drive + |vpiName:intf.drive |vpiPort: \_port: (out), line:23:30, endln:23:48 |vpiParent: @@ -954,7 +954,6 @@ design: (work@TOP) \_hier_path: (intf.observe), line:23:35, endln:23:47 |vpiParent: \_port: (out), line:23:30, endln:23:48 - |vpiName:intf.observe |vpiActual: \_ref_obj: (intf), line:23:35, endln:23:39 |vpiParent: @@ -966,6 +965,7 @@ design: (work@TOP) \_hier_path: (intf.observe), line:23:35, endln:23:47 |vpiName:observe |vpiFullName:work@middle.sub1.out.observe + |vpiName:intf.observe |uhdmtopModules: \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPortGeneric/tb.v, line:15:1, endln:20:10 |vpiName:work@TOP @@ -1007,7 +1007,6 @@ design: (work@TOP) \_hier_path: (conntb.tb), line:18:22, endln:18:31 |vpiParent: \_port: (intf), line:1:31, endln:1:35 - |vpiName:conntb.tb |vpiActual: \_ref_obj: (conntb), line:18:22, endln:18:28 |vpiParent: @@ -1019,6 +1018,7 @@ design: (work@TOP) \_hier_path: (conntb.tb), line:18:22, endln:18:31 |vpiName:tb |vpiFullName:work@TOP.tb.intf.tb + |vpiName:conntb.tb |vpiLowConn: \_ref_obj: (work@TOP.tb.intf), line:1:31, endln:1:35 |vpiParent: @@ -1188,7 +1188,6 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:17:16, endln:17:28 |vpiParent: \_port: (i), line:2:24, endln:2:25 - |vpiName:conntb.drive |vpiActual: \_ref_obj: (conntb), line:17:16, endln:17:22 |vpiParent: @@ -1200,6 +1199,7 @@ design: (work@TOP) \_hier_path: (conntb.drive), line:17:16, endln:17:28 |vpiName:drive |vpiFullName:work@TOP.dut1.i.drive + |vpiName:conntb.drive |vpiLowConn: \_ref_obj: (work@TOP.dut1.i), line:17:14, endln:17:15 |vpiParent: @@ -1225,7 +1225,6 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:17:34, endln:17:48 |vpiParent: \_port: (o), line:2:38, endln:2:39 - |vpiName:conntb.observe |vpiActual: \_ref_obj: (conntb), line:17:34, endln:17:40 |vpiParent: @@ -1237,6 +1236,7 @@ design: (work@TOP) \_hier_path: (conntb.observe), line:17:34, endln:17:48 |vpiName:observe |vpiFullName:work@TOP.dut1.o.observe + |vpiName:conntb.observe |vpiLowConn: \_ref_obj: (work@TOP.dut1.o), line:17:32, endln:17:33 |vpiParent: @@ -1363,7 +1363,6 @@ design: (work@TOP) \_hier_path: (conntb.dut), line:6:25, endln:6:35 |vpiParent: \_port: (intf), line:22:26, endln:22:30 - |vpiName:conntb.dut |vpiActual: \_ref_obj: (conntb), line:6:25, endln:6:31 |vpiParent: @@ -1375,6 +1374,7 @@ design: (work@TOP) \_hier_path: (conntb.dut), line:6:25, endln:6:35 |vpiName:dut |vpiFullName:work@TOP.dut1.middle1.intf.dut + |vpiName:conntb.dut |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.intf), line:22:26, endln:22:30 |vpiParent: @@ -1503,9 +1503,6 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.inp.intf.drive |vpiActual: \_unsupported_typespec: (intf), line:22:26, endln:22:30 - |vpiName:intf.drive - |vpiExpr: - \_logic_net: (work@TOP.dut1.middle1.intf), line:22:26, endln:22:30 |vpiActual: \_ref_obj: (intf), line:23:17, endln:23:21 |vpiParent: @@ -1519,6 +1516,7 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.inp.drive |vpiExpr: \_logic_net: (work@TOP.dut1.middle1.intf), line:22:26, endln:22:30 + |vpiName:intf.drive |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.sub1.inp), line:23:13, endln:23:16 |vpiParent: @@ -1551,9 +1549,6 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.out.intf.observe |vpiActual: \_unsupported_typespec: (intf), line:22:26, endln:22:30 - |vpiName:intf.observe - |vpiExpr: - \_logic_net: (work@TOP.dut1.middle1.intf), line:22:26, endln:22:30 |vpiActual: \_ref_obj: (intf), line:23:35, endln:23:39 |vpiParent: @@ -1567,6 +1562,7 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.middle1.sub1.out.observe |vpiExpr: \_logic_net: (work@TOP.dut1.middle1.intf), line:22:26, endln:22:30 + |vpiName:intf.observe |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.sub1.out), line:23:31, endln:23:34 |vpiParent: diff --git a/tests/OneNetRange/OneNetRange.log b/tests/OneNetRange/OneNetRange.log index 70cf38c74e..5bb400df08 100644 --- a/tests/OneNetRange/OneNetRange.log +++ b/tests/OneNetRange/OneNetRange.log @@ -731,7 +731,6 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:21:24, endln:21:36 |vpiParent: \_port: (i), line:21:21, endln:21:37 - |vpiName:conntb.con_i |vpiActual: \_ref_obj: (conntb), line:21:24, endln:21:30 |vpiParent: @@ -743,6 +742,7 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:21:24, endln:21:36 |vpiName:con_i |vpiFullName:work@TOP.dut1.i.con_i + |vpiName:conntb.con_i |vpiPort: \_port: (o), line:21:39, endln:21:55 |vpiParent: @@ -752,7 +752,6 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:21:42, endln:21:54 |vpiParent: \_port: (o), line:21:39, endln:21:55 - |vpiName:conntb.con_o |vpiActual: \_ref_obj: (conntb), line:21:42, endln:21:48 |vpiParent: @@ -764,6 +763,7 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:21:42, endln:21:54 |vpiName:con_o |vpiFullName:work@TOP.dut1.o.con_o + |vpiName:conntb.con_o |vpiRefModule: \_ref_module: work@TESTBENCH (tb), line:22:22, endln:22:24 |vpiParent: @@ -781,7 +781,6 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:22:34, endln:22:46 |vpiParent: \_port: (observe), line:22:25, endln:22:47 - |vpiName:conntb.con_o |vpiActual: \_ref_obj: (conntb), line:22:34, endln:22:40 |vpiParent: @@ -793,6 +792,7 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:22:34, endln:22:46 |vpiName:con_o |vpiFullName:work@TOP.tb.observe.con_o + |vpiName:conntb.con_o |vpiPort: \_port: (drive), line:22:48, endln:22:68 |vpiParent: @@ -802,7 +802,6 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:22:55, endln:22:67 |vpiParent: \_port: (drive), line:22:48, endln:22:68 - |vpiName:conntb.con_i |vpiActual: \_ref_obj: (conntb), line:22:55, endln:22:61 |vpiParent: @@ -814,6 +813,7 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:22:55, endln:22:67 |vpiName:con_i |vpiFullName:work@TOP.tb.drive.con_i + |vpiName:conntb.con_i |uhdmallModules: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:2:1, endln:5:10 |vpiParent: @@ -1057,7 +1057,6 @@ design: (work@TOP) \_hier_path: (conn.con_i), line:12:34, endln:12:44 |vpiParent: \_port: (inp), line:12:29, endln:12:45 - |vpiName:conn.con_i |vpiActual: \_ref_obj: (conn), line:12:34, endln:12:38 |vpiParent: @@ -1069,6 +1068,7 @@ design: (work@TOP) \_hier_path: (conn.con_i), line:12:34, endln:12:44 |vpiName:con_i |vpiFullName:work@middle.sub1.inp.con_i + |vpiName:conn.con_i |vpiPort: \_port: (out), line:12:46, endln:12:62 |vpiParent: @@ -1078,7 +1078,6 @@ design: (work@TOP) \_hier_path: (conn.con_o), line:12:51, endln:12:61 |vpiParent: \_port: (out), line:12:46, endln:12:62 - |vpiName:conn.con_o |vpiActual: \_ref_obj: (conn), line:12:51, endln:12:55 |vpiParent: @@ -1090,6 +1089,7 @@ design: (work@TOP) \_hier_path: (conn.con_o), line:12:51, endln:12:61 |vpiName:con_o |vpiFullName:work@middle.sub1.out.con_o + |vpiName:conn.con_o |uhdmtopModules: \_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetRange/tb.v, line:16:1, endln:23:10 |vpiName:work@TOP @@ -1181,7 +1181,6 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:22:34, endln:22:46 |vpiParent: \_port: (observe), line:1:66, endln:1:73 - |vpiName:conntb.con_o |vpiActual: \_ref_obj: (conntb), line:22:34, endln:22:40 |vpiParent: @@ -1195,6 +1194,7 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:22:34, endln:22:46 |vpiName:con_o |vpiFullName:work@TOP.tb.observe.con_o + |vpiName:conntb.con_o |vpiLowConn: \_ref_obj: (work@TOP.tb.observe), line:22:26, endln:22:33 |vpiParent: @@ -1220,7 +1220,6 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:22:55, endln:22:67 |vpiParent: \_port: (drive), line:1:98, endln:1:103 - |vpiName:conntb.con_i |vpiActual: \_ref_obj: (conntb), line:22:55, endln:22:61 |vpiParent: @@ -1234,6 +1233,7 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:22:55, endln:22:67 |vpiName:con_i |vpiFullName:work@TOP.tb.drive.con_i + |vpiName:conntb.con_i |vpiLowConn: \_ref_obj: (work@TOP.tb.drive), line:22:49, endln:22:54 |vpiParent: @@ -1496,7 +1496,6 @@ design: (work@TOP) \_hier_path: (conntb.con_i), line:21:24, endln:21:36 |vpiParent: \_port: (i), line:2:59, endln:2:60 - |vpiName:conntb.con_i |vpiActual: \_ref_obj: (conntb), line:21:24, endln:21:30 |vpiParent: @@ -1512,6 +1511,7 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.i.con_i |vpiActual: \_logic_net: (work@TOP.conntb.con_i), line:8:68, endln:8:73 + |vpiName:conntb.con_i |vpiLowConn: \_ref_obj: (work@TOP.dut1.i), line:21:22, endln:21:23 |vpiParent: @@ -1539,7 +1539,6 @@ design: (work@TOP) \_hier_path: (conntb.con_o), line:21:42, endln:21:54 |vpiParent: \_port: (o), line:2:85, endln:2:86 - |vpiName:conntb.con_o |vpiActual: \_ref_obj: (conntb), line:21:42, endln:21:48 |vpiParent: @@ -1555,6 +1554,7 @@ design: (work@TOP) |vpiFullName:work@TOP.dut1.o.con_o |vpiActual: \_logic_net: (work@TOP.conntb.con_o), line:8:98, endln:8:103 + |vpiName:conntb.con_o |vpiLowConn: \_ref_obj: (work@TOP.dut1.o), line:21:40, endln:21:41 |vpiParent: @@ -1918,12 +1918,6 @@ design: (work@TOP) \_hier_path: (conn.con_i), line:12:34, endln:12:44 |vpiParent: \_port: (inp), line:15:59, endln:15:62 - |vpiName:conn.con_i - |vpiExpr: - \_ref_obj: (work@TOP.dut1.middle1.conn), line:4:35, endln:4:41 - |vpiFullName:work@TOP.dut1.middle1.conn - |vpiActual: - \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 |vpiActual: \_ref_obj: (conn), line:12:34, endln:12:38 |vpiParent: @@ -1941,6 +1935,10 @@ design: (work@TOP) \_logic_net: (con_i), line:8:68, endln:8:73 |vpiExpr: \_ref_obj: (work@TOP.dut1.middle1.conn), line:4:35, endln:4:41 + |vpiFullName:work@TOP.dut1.middle1.conn + |vpiActual: + \_interface_inst: work@ConnectTB (work@TOP.dut1.middle1.conn), file:${SURELOG_DIR}/tests/OneNetRange/dut.v, line:4:0 + |vpiName:conn.con_i |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.sub1.inp), line:12:30, endln:12:33 |vpiParent: @@ -1968,9 +1966,6 @@ design: (work@TOP) \_hier_path: (conn.con_o), line:12:51, endln:12:61 |vpiParent: \_port: (out), line:15:87, endln:15:90 - |vpiName:conn.con_o - |vpiExpr: - \_ref_obj: (work@TOP.dut1.middle1.conn), line:4:35, endln:4:41 |vpiActual: \_ref_obj: (conn), line:12:51, endln:12:55 |vpiParent: @@ -1988,6 +1983,7 @@ design: (work@TOP) \_logic_net: (con_o), line:8:98, endln:8:103 |vpiExpr: \_ref_obj: (work@TOP.dut1.middle1.conn), line:4:35, endln:4:41 + |vpiName:conn.con_o |vpiLowConn: \_ref_obj: (work@TOP.dut1.middle1.sub1.out), line:12:47, endln:12:50 |vpiParent: diff --git a/tests/PackFuncParent/PackFuncParent.log b/tests/PackFuncParent/PackFuncParent.log index 32a7e194a7..9ed2b718a4 100644 --- a/tests/PackFuncParent/PackFuncParent.log +++ b/tests/PackFuncParent/PackFuncParent.log @@ -229,8 +229,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 2 constant 57 cont_assign 1 @@ -254,8 +253,7 @@ return_stmt 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 4 +assignment 6 begin 4 constant 57 cont_assign 2 diff --git a/tests/PackStructField/PackStructField.log b/tests/PackStructField/PackStructField.log index 40f81939c4..3254f13bf2 100644 --- a/tests/PackStructField/PackStructField.log +++ b/tests/PackStructField/PackStructField.log @@ -487,7 +487,6 @@ design: (work@my_module) \_hier_path: (work@my_module), line:21:12, endln:21:38 |vpiParent: \_cont_assign: , line:21:8, endln:21:38 - |vpiFullName:work@my_module |vpiActual: \_ref_obj: (my_package::my_parameter), line:21:12, endln:21:24 |vpiParent: @@ -501,6 +500,7 @@ design: (work@my_module) \_hier_path: (work@my_module), line:21:12, endln:21:38 |vpiName:a |vpiFullName:work@my_module.a + |vpiFullName:work@my_module |vpiLhs: \_ref_obj: (work@my_module.x), line:21:8, endln:21:9 |vpiParent: @@ -517,7 +517,6 @@ design: (work@my_module) \_hier_path: (work@my_module), line:22:12, endln:22:38 |vpiParent: \_cont_assign: , line:22:8, endln:22:38 - |vpiFullName:work@my_module |vpiActual: \_ref_obj: (my_package::my_parameter), line:22:12, endln:22:24 |vpiParent: @@ -531,6 +530,7 @@ design: (work@my_module) \_hier_path: (work@my_module), line:22:12, endln:22:38 |vpiName:b |vpiFullName:work@my_module.b + |vpiFullName:work@my_module |vpiLhs: \_ref_obj: (work@my_module.y), line:22:8, endln:22:9 |vpiParent: diff --git a/tests/PackageBind/PackageBind.log b/tests/PackageBind/PackageBind.log index 58cf672c8d..662d62575a 100644 --- a/tests/PackageBind/PackageBind.log +++ b/tests/PackageBind/PackageBind.log @@ -159,8 +159,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 -assignment 2 +assignment 6 begin 4 constant 18 cont_assign 2 @@ -186,8 +185,7 @@ return_stmt 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 6 -assignment 4 +assignment 10 begin 8 constant 18 cont_assign 3 @@ -299,13 +297,13 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:7, endln:7:10 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:5:7, endln:5:10 |vpiRhs: \_constant: , line:5:21, endln:5:22 |vpiParent: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -313,7 +311,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:5:12, endln:5:18 |vpiParent: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -487,13 +485,13 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:7, endln:7:10 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:5:7, endln:5:10 |vpiRhs: \_constant: , line:5:21, endln:5:22 |vpiParent: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -501,7 +499,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:5:12, endln:5:18 |vpiParent: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiActual: @@ -775,7 +773,7 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:7, endln:7:10 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:5:7, endln:5:10 |vpiRhs: @@ -783,7 +781,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:5:12, endln:5:18 |vpiParent: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: @@ -923,7 +921,7 @@ design: (work@top) \_begin: (prim_util_pkg::_clog2), line:5:7, endln:7:10 |vpiFullName:prim_util_pkg::_clog2 |vpiForInitStmt: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiParent: \_for_stmt: (prim_util_pkg::_clog2), line:5:7, endln:5:10 |vpiRhs: @@ -931,7 +929,7 @@ design: (work@top) |vpiLhs: \_ref_var: (prim_util_pkg::_clog2::result), line:5:12, endln:5:18 |vpiParent: - \_assign_stmt: , line:5:12, endln:5:22 + \_assignment: , line:5:12, endln:5:22 |vpiName:result |vpiFullName:prim_util_pkg::_clog2::result |vpiForIncStmt: diff --git a/tests/PackageFuncCall/PackageFuncCall.log b/tests/PackageFuncCall/PackageFuncCall.log index 2292e0acd8..d8cbbc45ee 100644 --- a/tests/PackageFuncCall/PackageFuncCall.log +++ b/tests/PackageFuncCall/PackageFuncCall.log @@ -762,8 +762,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 4 -assignment 5 +assignment 9 begin 4 bit_select 3 class_defn 8 @@ -802,8 +801,7 @@ var_select 1 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 6 -assignment 10 +assignment 16 begin 8 bit_select 6 class_defn 8 @@ -1103,13 +1101,13 @@ design: (work@top) \_begin: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:13:8 |vpiFullName:prim_cipher_pkg::sbox4_64bit |vpiForInitStmt: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiParent: \_for_stmt: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:11:8 |vpiRhs: \_constant: , line:11:18, endln:11:19 |vpiParent: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1117,7 +1115,7 @@ design: (work@top) |vpiLhs: \_int_var: (prim_cipher_pkg::sbox4_64bit::k), line:11:14, endln:11:15 |vpiParent: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiTypespec: \_ref_typespec: (prim_cipher_pkg::sbox4_64bit::k) |vpiParent: @@ -1570,13 +1568,13 @@ design: (work@top) \_begin: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:13:8 |vpiFullName:prim_cipher_pkg::sbox4_64bit |vpiForInitStmt: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiParent: \_for_stmt: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:11:8 |vpiRhs: \_constant: , line:11:18, endln:11:19 |vpiParent: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1584,7 +1582,7 @@ design: (work@top) |vpiLhs: \_int_var: (prim_cipher_pkg::sbox4_64bit::k), line:11:14, endln:11:15 |vpiParent: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiTypespec: \_ref_typespec: (prim_cipher_pkg::sbox4_64bit::k) |vpiParent: @@ -2674,7 +2672,7 @@ design: (work@top) \_begin: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:13:8 |vpiFullName:prim_cipher_pkg::sbox4_64bit |vpiForInitStmt: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiParent: \_for_stmt: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:11:8 |vpiRhs: @@ -2682,7 +2680,7 @@ design: (work@top) |vpiLhs: \_int_var: (prim_cipher_pkg::sbox4_64bit::k), line:11:14, endln:11:15 |vpiParent: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiTypespec: \_ref_typespec: (prim_cipher_pkg::sbox4_64bit::k) |vpiParent: @@ -3096,7 +3094,7 @@ design: (work@top) \_begin: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:13:8 |vpiFullName:prim_cipher_pkg::sbox4_64bit |vpiForInitStmt: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiParent: \_for_stmt: (prim_cipher_pkg::sbox4_64bit), line:11:5, endln:11:8 |vpiRhs: @@ -3104,7 +3102,7 @@ design: (work@top) |vpiLhs: \_int_var: (prim_cipher_pkg::sbox4_64bit::k), line:11:14, endln:11:15 |vpiParent: - \_assign_stmt: , line:11:10, endln:11:19 + \_assignment: , line:11:10, endln:11:19 |vpiTypespec: \_ref_typespec: (prim_cipher_pkg::sbox4_64bit::k) |vpiParent: diff --git a/tests/PackageHierRef/PackageHierRef.log b/tests/PackageHierRef/PackageHierRef.log index d8c328c0e0..3762f8e9df 100644 --- a/tests/PackageHierRef/PackageHierRef.log +++ b/tests/PackageHierRef/PackageHierRef.log @@ -722,8 +722,7 @@ Instance tree: [NTE:EL0523] ${SURELOG_DIR}/tests/PackageHierRef/top.sv:34:5: Instance "work@m.sB1.sInst". [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 9 -assignment 8 +assignment 17 class_defn 8 class_typespec 4 class_var 3 diff --git a/tests/PackageVar/PackageVar.log b/tests/PackageVar/PackageVar.log index b8fcbe06d7..03c8a61565 100644 --- a/tests/PackageVar/PackageVar.log +++ b/tests/PackageVar/PackageVar.log @@ -375,7 +375,6 @@ design: (unnamed) \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiParent: \_if_else: , line:28:3, endln:38:6 - |vpiName:printer.istop |vpiActual: \_ref_obj: (printer), line:28:6, endln:28:13 |vpiParent: @@ -388,6 +387,7 @@ design: (unnamed) |vpiParent: \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiName:istop + |vpiName:printer.istop |vpiStmt: \_begin: (pack::ovm_object::print), line:28:23, endln:30:6 |vpiParent: @@ -440,7 +440,6 @@ design: (unnamed) \_hier_path: (ovm_auto_options_object.printer), line:34:5, endln:34:36 |vpiParent: \_assignment: , line:34:5, endln:34:46 - |vpiName:ovm_auto_options_object.printer |vpiActual: \_ref_obj: (ovm_auto_options_object), line:34:29, endln:34:36 |vpiParent: @@ -455,6 +454,7 @@ design: (unnamed) |vpiName:printer |vpiActual: \_class_var: (pack::ovm_options_container::printer), line:7:17, endln:7:24 + |vpiName:ovm_auto_options_object.printer |vpiStmt: \_func_call: (m_field_automation), line:35:5, endln:35:44 |vpiParent: @@ -630,7 +630,6 @@ design: (unnamed) \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiParent: \_if_else: , line:28:3, endln:38:6 - |vpiName:printer.istop |vpiActual: \_ref_obj: (printer), line:28:6, endln:28:13 |vpiParent: @@ -643,6 +642,7 @@ design: (unnamed) |vpiParent: \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiName:istop + |vpiName:printer.istop |vpiStmt: \_begin: (pack::ovm_object::print), line:28:23, endln:30:6 |vpiParent: @@ -695,7 +695,6 @@ design: (unnamed) \_hier_path: (ovm_auto_options_object.printer), line:34:5, endln:34:36 |vpiParent: \_assignment: , line:34:5, endln:34:46 - |vpiName:ovm_auto_options_object.printer |vpiActual: \_ref_obj: (ovm_auto_options_object), line:34:29, endln:34:36 |vpiParent: @@ -710,6 +709,7 @@ design: (unnamed) |vpiName:printer |vpiActual: \_io_decl: (printer), line:23:45, endln:23:52 + |vpiName:ovm_auto_options_object.printer |vpiStmt: \_func_call: (m_field_automation), line:35:5, endln:35:44 |vpiParent: @@ -858,7 +858,6 @@ design: (unnamed) \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiParent: \_begin: (pack::ovm_object::print), line:28:3, endln:38:6 - |vpiName:printer.istop |vpiActual: \_ref_obj: (printer), line:28:6, endln:28:13 |vpiParent: @@ -869,6 +868,7 @@ design: (unnamed) |vpiParent: \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiName:istop + |vpiName:printer.istop |vpiStmt: \_begin: (pack::ovm_object::print), line:28:23, endln:30:6 |vpiParent: @@ -919,7 +919,6 @@ design: (unnamed) \_hier_path: (ovm_auto_options_object.printer), line:34:5, endln:34:36 |vpiParent: \_assignment: , line:34:5, endln:34:46 - |vpiName:ovm_auto_options_object.printer |vpiActual: \_ref_obj: (ovm_auto_options_object), line:34:29, endln:34:36 |vpiParent: @@ -930,6 +929,7 @@ design: (unnamed) |vpiParent: \_hier_path: (ovm_auto_options_object.printer), line:34:5, endln:34:36 |vpiName:printer + |vpiName:ovm_auto_options_object.printer |vpiStmt: \_func_call: (m_field_automation), line:35:5, endln:35:44 |vpiParent: @@ -1039,7 +1039,6 @@ design: (unnamed) \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiParent: \_begin: (pack::ovm_object::print), line:28:3, endln:38:6 - |vpiName:printer.istop |vpiActual: \_ref_obj: (printer), line:28:6, endln:28:13 |vpiParent: @@ -1052,6 +1051,7 @@ design: (unnamed) |vpiParent: \_hier_path: (printer.istop), line:28:6, endln:28:21 |vpiName:istop + |vpiName:printer.istop |vpiStmt: \_begin: (pack::ovm_object::print), line:28:23, endln:30:6 |vpiParent: @@ -1104,7 +1104,6 @@ design: (unnamed) \_hier_path: (ovm_auto_options_object.printer), line:34:5, endln:34:36 |vpiParent: \_assignment: , line:34:5, endln:34:46 - |vpiName:ovm_auto_options_object.printer |vpiActual: \_ref_obj: (ovm_auto_options_object), line:34:29, endln:34:36 |vpiParent: @@ -1119,6 +1118,7 @@ design: (unnamed) |vpiName:printer |vpiActual: \_io_decl: (printer), line:23:45, endln:23:52 + |vpiName:ovm_auto_options_object.printer |vpiStmt: \_func_call: (m_field_automation), line:35:5, endln:35:44 |vpiParent: diff --git a/tests/PackedArrayBind/PackedArrayBind.log b/tests/PackedArrayBind/PackedArrayBind.log index f3c87407dd..ad02aedd60 100644 --- a/tests/PackedArrayBind/PackedArrayBind.log +++ b/tests/PackedArrayBind/PackedArrayBind.log @@ -321,7 +321,6 @@ design: (work@PreDecodeStage) \_hier_path: (replayEntryOut.memData[0].memOpInfo.mshrID), line:24:18, endln:24:60 |vpiParent: \_cont_assign: , line:24:9, endln:24:60 - |vpiName:replayEntryOut.memData[0].memOpInfo.mshrID |vpiActual: \_ref_obj: (replayEntryOut), line:24:18, endln:24:32 |vpiParent: @@ -350,6 +349,7 @@ design: (work@PreDecodeStage) \_hier_path: (replayEntryOut.memData[0].memOpInfo.mshrID), line:24:18, endln:24:60 |vpiName:mshrID |vpiFullName:work@PreDecodeStage.mshrID + |vpiName:replayEntryOut.memData[0].memOpInfo.mshrID |vpiLhs: \_ref_obj: (work@PreDecodeStage.mshrID), line:24:9, endln:24:15 |vpiParent: @@ -394,7 +394,6 @@ design: (work@PreDecodeStage) \_hier_path: (replayEntryOut.memData[0].memOpInfo.mshrID), line:24:18, endln:24:60 |vpiParent: \_cont_assign: , line:24:9, endln:24:60 - |vpiName:replayEntryOut.memData[0].memOpInfo.mshrID |vpiActual: \_ref_obj: (replayEntryOut), line:24:18, endln:24:32 |vpiParent: @@ -427,6 +426,7 @@ design: (work@PreDecodeStage) |vpiFullName:work@PreDecodeStage.mshrID |vpiActual: \_typespec_member: (mshrID), line:7:20, endln:7:26 + |vpiName:replayEntryOut.memData[0].memOpInfo.mshrID |vpiLhs: \_ref_obj: (work@PreDecodeStage.mshrID), line:24:9, endln:24:15 |vpiParent: diff --git a/tests/PackedArrayHierPath/PackedArrayHierPath.log b/tests/PackedArrayHierPath/PackedArrayHierPath.log index 77d01a8f98..13aa6f71bb 100644 --- a/tests/PackedArrayHierPath/PackedArrayHierPath.log +++ b/tests/PackedArrayHierPath/PackedArrayHierPath.log @@ -504,7 +504,6 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:18:8, endln:18:34 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:8, endln:18:20 |vpiParent: @@ -529,11 +528,11 @@ design: (unnamed) |vpiFullName:uvm::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:3:16, endln:3:24 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:18:37, endln:18:63 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:37, endln:18:49 |vpiParent: @@ -558,6 +557,7 @@ design: (unnamed) |vpiFullName:uvm::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:4:16, endln:4:24 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:18:66, endln:18:67 |vpiParent: @@ -814,7 +814,6 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:18:8, endln:18:34 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:8, endln:18:20 |vpiParent: @@ -839,11 +838,11 @@ design: (unnamed) |vpiFullName:uvm::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:3:16, endln:3:24 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:18:37, endln:18:63 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:37, endln:18:49 |vpiParent: @@ -868,6 +867,7 @@ design: (unnamed) |vpiFullName:uvm::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:4:16, endln:4:24 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:18:66, endln:18:67 |vpiParent: @@ -919,7 +919,6 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:18:8, endln:18:34 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:8, endln:18:20 |vpiParent: @@ -942,11 +941,11 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:18:8, endln:18:34 |vpiName:exp_bits |vpiFullName:uvm::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:18:37, endln:18:63 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:37, endln:18:49 |vpiParent: @@ -969,6 +968,7 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:18:37, endln:18:63 |vpiName:man_bits |vpiFullName:uvm::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:18:66, endln:18:67 |vpiInstance: @@ -1063,7 +1063,6 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:18:8, endln:18:34 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:8, endln:18:20 |vpiParent: @@ -1086,11 +1085,11 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:18:8, endln:18:34 |vpiName:exp_bits |vpiFullName:uvm::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:18:37, endln:18:63 |vpiParent: \_operation: , line:18:8, endln:18:63 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:18:37, endln:18:49 |vpiParent: @@ -1113,6 +1112,7 @@ design: (unnamed) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:18:37, endln:18:63 |vpiName:man_bits |vpiFullName:uvm::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:18:66, endln:18:67 |vpiInstance: diff --git a/tests/PackedEnumVar/PackedEnumVar.log b/tests/PackedEnumVar/PackedEnumVar.log index 38b887e3c9..fa1ad05dcf 100644 --- a/tests/PackedEnumVar/PackedEnumVar.log +++ b/tests/PackedEnumVar/PackedEnumVar.log @@ -181,8 +181,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 2 +assignment 3 begin 1 bit_select 2 constant 22 @@ -211,8 +210,7 @@ return_stmt 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 4 +assignment 5 begin 2 bit_select 4 constant 22 diff --git a/tests/ParamArray/ParamArray.log b/tests/ParamArray/ParamArray.log index de5e83d3d4..227cb7171d 100644 --- a/tests/ParamArray/ParamArray.log +++ b/tests/ParamArray/ParamArray.log @@ -1728,7 +1728,6 @@ design: (work@top) \_hier_path: (Info.size), line:36:33, endln:36:42 |vpiParent: \_operation: , line:36:33, endln:36:47 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:36:38, endln:36:42 |vpiParent: @@ -1739,6 +1738,7 @@ design: (work@top) |vpiParent: \_hier_path: (Info.size), line:36:33, endln:36:42 |vpiName:size + |vpiName:Info.size |vpiOperand: \_constant: , line:36:46, endln:36:47 |vpiParent: diff --git a/tests/ParamArraySelect/ParamArraySelect.log b/tests/ParamArraySelect/ParamArraySelect.log index 66db55aed8..2101f2fde1 100644 --- a/tests/ParamArraySelect/ParamArraySelect.log +++ b/tests/ParamArraySelect/ParamArraySelect.log @@ -786,7 +786,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 10 -assign_stmt 1 +assignment 1 begin 1 bit_select 14 class_defn 8 @@ -832,7 +832,7 @@ unsupported_typespec 2 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === array_typespec 10 -assign_stmt 1 +assignment 1 begin 1 bit_select 14 class_defn 8 @@ -2113,7 +2113,6 @@ design: (work@top) \_hier_path: (Info.size), line:40:33, endln:40:42 |vpiParent: \_operation: , line:40:33, endln:40:47 - |vpiName:Info.size |vpiActual: \_ref_obj: (Info), line:40:38, endln:40:42 |vpiParent: @@ -2124,6 +2123,7 @@ design: (work@top) |vpiParent: \_hier_path: (Info.size), line:40:33, endln:40:42 |vpiName:size + |vpiName:Info.size |vpiOperand: \_constant: , line:40:46, endln:40:47 |vpiParent: @@ -2525,7 +2525,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamArraySelect/dut.sv, line:51:1, endln:71:10 |vpiForInitStmt: - \_assign_stmt: , line:61:7, endln:61:19 + \_assignment: , line:61:7, endln:61:19 |vpiParent: \_gen_for: |vpiRhs: @@ -2537,7 +2537,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.k), line:61:14, endln:61:15 |vpiParent: - \_assign_stmt: , line:61:7, endln:61:19 + \_assignment: , line:61:7, endln:61:19 |vpiTypespec: \_ref_typespec: (work@top.k) |vpiParent: @@ -2619,7 +2619,6 @@ design: (work@top) \_hier_path: (PartInfo[k].offset), line:62:75, endln:62:83 |vpiParent: \_operation: , line:62:53, endln:62:94 - |vpiName:PartInfo[k].offset |vpiActual: \_bit_select: (PartInfo[k]), line:62:75, endln:62:83 |vpiParent: @@ -2638,6 +2637,7 @@ design: (work@top) \_hier_path: (PartInfo[k].offset), line:62:75, endln:62:83 |vpiName:offset |vpiFullName:work@top.gen_part_sel.offset + |vpiName:PartInfo[k].offset |vpiOperand: \_operation: , line:63:53, endln:63:92 |vpiParent: @@ -2654,7 +2654,6 @@ design: (work@top) \_hier_path: (PartInfo[k].size), line:63:75, endln:63:83 |vpiParent: \_operation: , line:63:53, endln:63:92 - |vpiName:PartInfo[k].size |vpiActual: \_bit_select: (PartInfo[k]), line:63:75, endln:63:83 |vpiParent: @@ -2673,6 +2672,7 @@ design: (work@top) \_hier_path: (PartInfo[k].size), line:63:75, endln:63:83 |vpiName:size |vpiFullName:work@top.gen_part_sel.size + |vpiName:PartInfo[k].size |vpiLhs: \_parameter: (work@top.gen_part_sel.PartEnd), line:62:43, endln:63:92 |vpiParent: @@ -5051,7 +5051,6 @@ design: (work@top) \_hier_path: (PartInfo[LifeCycleIdx].size), line:59:10, endln:59:18 |vpiParent: \_range: , line:59:9, endln:59:40 - |vpiName:PartInfo[LifeCycleIdx].size |vpiActual: \_bit_select: (PartInfo[LifeCycleIdx]), line:59:10, endln:59:18 |vpiParent: @@ -5070,6 +5069,7 @@ design: (work@top) |vpiParent: \_hier_path: (PartInfo[LifeCycleIdx].size), line:59:10, endln:59:18 |vpiName:size + |vpiName:PartInfo[LifeCycleIdx].size |vpiRightRange: \_constant: , line:59:38, endln:59:39 |vpiParent: diff --git a/tests/ParamBitSelect/ParamBitSelect.log b/tests/ParamBitSelect/ParamBitSelect.log index 2e5ef7fcf7..e52bbcdb25 100644 --- a/tests/ParamBitSelect/ParamBitSelect.log +++ b/tests/ParamBitSelect/ParamBitSelect.log @@ -172,7 +172,7 @@ AST_DEBUG_END [WRN:EL0513] Nb undefined instances: 2. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 begin 4 bit_select 5 constant 57 @@ -199,7 +199,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 begin 4 bit_select 5 constant 57 @@ -291,7 +291,7 @@ design: (work@dut) |vpiParent: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/ParamBitSelect/dut.sv, line:5:1, endln:21:10 |vpiForInitStmt: - \_assign_stmt: , line:9:6, endln:9:18 + \_assignment: , line:9:6, endln:9:18 |vpiParent: \_gen_for: |vpiRhs: @@ -303,7 +303,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.k), line:9:13, endln:9:14 |vpiParent: - \_assign_stmt: , line:9:6, endln:9:18 + \_assignment: , line:9:6, endln:9:18 |vpiTypespec: \_ref_typespec: (work@dut.k) |vpiParent: diff --git a/tests/ParamElabMulti/ParamElabMulti.log b/tests/ParamElabMulti/ParamElabMulti.log index 9b87a1372e..ae059f0b0f 100644 --- a/tests/ParamElabMulti/ParamElabMulti.log +++ b/tests/ParamElabMulti/ParamElabMulti.log @@ -467,7 +467,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 1 constant 187 cont_assign 3 @@ -504,7 +504,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 1 constant 187 cont_assign 10 @@ -1174,7 +1174,7 @@ design: (work@top) |vpiParent: \_module_inst: work@sub_top (work@sub_top), file:${SURELOG_DIR}/tests/ParamElabMulti/dut.sv, line:41:1, endln:50:10 |vpiForInitStmt: - \_assign_stmt: , line:45:8, endln:45:20 + \_assignment: , line:45:8, endln:45:20 |vpiParent: \_gen_for: |vpiRhs: @@ -1186,7 +1186,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@sub_top.k), line:45:15, endln:45:16 |vpiParent: - \_assign_stmt: , line:45:8, endln:45:20 + \_assignment: , line:45:8, endln:45:20 |vpiTypespec: \_ref_typespec: (work@sub_top.k) |vpiParent: diff --git a/tests/ParamOverload3/ParamOverload3.log b/tests/ParamOverload3/ParamOverload3.log index e66910c4df..c6a0806b0a 100644 --- a/tests/ParamOverload3/ParamOverload3.log +++ b/tests/ParamOverload3/ParamOverload3.log @@ -641,7 +641,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 7 constant 269 cont_assign 3 @@ -682,7 +682,7 @@ unsupported_typespec 8 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_select 12 constant 270 cont_assign 4 @@ -1172,7 +1172,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:38:12, endln:38:38 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:12, endln:38:24 |vpiParent: @@ -1197,11 +1196,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:7:18, endln:7:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:38:41, endln:38:67 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:41, endln:38:53 |vpiParent: @@ -1226,6 +1225,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:8:18, endln:8:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:38:70, endln:38:71 |vpiParent: @@ -1683,7 +1683,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:38:12, endln:38:38 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:12, endln:38:24 |vpiParent: @@ -1708,11 +1707,11 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::exp_bits |vpiActual: \_typespec_member: (exp_bits), line:7:18, endln:7:26 + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:38:41, endln:38:67 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:41, endln:38:53 |vpiParent: @@ -1737,6 +1736,7 @@ design: (work@top) |vpiFullName:fpnew_pkg::fp_width::man_bits |vpiActual: \_typespec_member: (man_bits), line:8:18, endln:8:26 + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:38:70, endln:38:71 |vpiParent: @@ -1921,7 +1921,6 @@ design: (work@top) \_hier_path: (Features.Width), line:46:22, endln:46:36 |vpiParent: \_param_assign: , line:46:14, endln:46:36 - |vpiName:Features.Width |vpiActual: \_ref_obj: (Features), line:46:31, endln:46:36 |vpiParent: @@ -1932,6 +1931,7 @@ design: (work@top) |vpiParent: \_hier_path: (Features.Width), line:46:22, endln:46:36 |vpiName:Width + |vpiName:Features.Width |vpiLhs: \_parameter: (work@top.WIDTH), line:46:14, endln:46:19 |vpiDefName:work@top @@ -1947,7 +1947,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ParamOverload3/dut.sv, line:43:1, endln:64:10 |vpiForInitStmt: - \_assign_stmt: , line:49:8, endln:49:22 + \_assignment: , line:49:8, endln:49:22 |vpiParent: \_gen_for: |vpiRhs: @@ -1959,7 +1959,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.fmt), line:49:15, endln:49:18 |vpiParent: - \_assign_stmt: , line:49:8, endln:49:22 + \_assignment: , line:49:8, endln:49:22 |vpiTypespec: \_ref_typespec: (work@top.fmt) |vpiParent: @@ -2075,7 +2075,6 @@ design: (work@top) \_hier_path: (Features.EnableNanBox), line:52:9, endln:52:30 |vpiParent: \_operation: , line:52:9, endln:52:52 - |vpiName:Features.EnableNanBox |vpiActual: \_ref_obj: (Features), line:52:18, endln:52:30 |vpiParent: @@ -2086,6 +2085,7 @@ design: (work@top) |vpiParent: \_hier_path: (Features.EnableNanBox), line:52:9, endln:52:30 |vpiName:EnableNanBox + |vpiName:Features.EnableNanBox |vpiOperand: \_operation: , line:52:35, endln:52:51 |vpiParent: @@ -2752,7 +2752,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:38:12, endln:38:38 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:12, endln:38:24 |vpiParent: @@ -2775,11 +2774,11 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:38:12, endln:38:38 |vpiName:exp_bits |vpiFullName:fpnew_pkg::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:38:41, endln:38:67 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:41, endln:38:53 |vpiParent: @@ -2802,6 +2801,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:38:41, endln:38:67 |vpiName:man_bits |vpiFullName:fpnew_pkg::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:38:70, endln:38:71 |vpiInstance: @@ -2950,7 +2950,6 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:38:12, endln:38:38 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:12, endln:38:24 |vpiParent: @@ -2973,11 +2972,11 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].exp_bits), line:38:12, endln:38:38 |vpiName:exp_bits |vpiFullName:fpnew_pkg::fp_width::exp_bits + |vpiName:FP_ENCODINGS[fmt].exp_bits |vpiOperand: \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:38:41, endln:38:67 |vpiParent: \_operation: , line:38:12, endln:38:67 - |vpiName:FP_ENCODINGS[fmt].man_bits |vpiActual: \_bit_select: (FP_ENCODINGS[fmt]), line:38:41, endln:38:53 |vpiParent: @@ -3000,6 +2999,7 @@ design: (work@top) \_hier_path: (FP_ENCODINGS[fmt].man_bits), line:38:41, endln:38:67 |vpiName:man_bits |vpiFullName:fpnew_pkg::fp_width::man_bits + |vpiName:FP_ENCODINGS[fmt].man_bits |vpiOperand: \_constant: , line:38:70, endln:38:71 |vpiInstance: diff --git a/tests/ParamOverload4/ParamOverload4.log b/tests/ParamOverload4/ParamOverload4.log index 2e7d3853b5..bcb403dee7 100644 --- a/tests/ParamOverload4/ParamOverload4.log +++ b/tests/ParamOverload4/ParamOverload4.log @@ -424,7 +424,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 constant 1074 design 1 gen_for 1 @@ -445,7 +445,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 constant 1074 design 1 gen_for 1 @@ -595,7 +595,7 @@ design: (work@ibex_pmp) |vpiParent: \_module_inst: work@ibex_pmp (work@ibex_pmp), file:${SURELOG_DIR}/tests/ParamOverload4/dut.sv, line:2:1, endln:34:10 |vpiForInitStmt: - \_assign_stmt: , line:20:8, endln:20:20 + \_assignment: , line:20:8, endln:20:20 |vpiParent: \_gen_for: |vpiRhs: @@ -607,7 +607,7 @@ design: (work@ibex_pmp) |vpiLhs: \_int_var: (work@ibex_pmp.r), line:20:15, endln:20:16 |vpiParent: - \_assign_stmt: , line:20:8, endln:20:20 + \_assignment: , line:20:8, endln:20:20 |vpiTypespec: \_ref_typespec: (work@ibex_pmp.r) |vpiParent: diff --git a/tests/ParamSubstituteComplex/ParamSubstituteComplex.log b/tests/ParamSubstituteComplex/ParamSubstituteComplex.log index eb5ad2becc..b8d55c4f1c 100644 --- a/tests/ParamSubstituteComplex/ParamSubstituteComplex.log +++ b/tests/ParamSubstituteComplex/ParamSubstituteComplex.log @@ -1270,7 +1270,6 @@ design: (work@top) \_hier_path: (Features.FpFmtMask), line:41:45, endln:41:63 |vpiParent: \_param_assign: , line:41:29, endln:41:63 - |vpiName:Features.FpFmtMask |vpiActual: \_ref_obj: (Features), line:41:54, endln:41:63 |vpiParent: @@ -1281,6 +1280,7 @@ design: (work@top) |vpiParent: \_hier_path: (Features.FpFmtMask), line:41:45, endln:41:63 |vpiName:FpFmtMask + |vpiName:Features.FpFmtMask |vpiLhs: \_parameter: (work@top.FpFmtMask), line:41:29, endln:41:38 |vpiParamAssign: diff --git a/tests/PartSelect4/PartSelect4.log b/tests/PartSelect4/PartSelect4.log index c405e13aeb..3f9cd7690a 100644 --- a/tests/PartSelect4/PartSelect4.log +++ b/tests/PartSelect4/PartSelect4.log @@ -259,7 +259,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 9. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 bit_typespec 2 constant 110 design 1 @@ -285,7 +285,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 bit_typespec 2 constant 110 design 1 @@ -398,7 +398,7 @@ design: (work@xbar_main) |vpiParent: \_module_inst: work@tlul_socket_1n (work@tlul_socket_1n), file:${SURELOG_DIR}/tests/PartSelect4/dut.sv, line:5:1, endln:9:10 |vpiForInitStmt: - \_assign_stmt: , line:6:8, endln:6:20 + \_assignment: , line:6:8, endln:6:20 |vpiParent: \_gen_for: |vpiRhs: @@ -410,7 +410,7 @@ design: (work@xbar_main) |vpiLhs: \_int_var: (work@tlul_socket_1n.i), line:6:15, endln:6:16 |vpiParent: - \_assign_stmt: , line:6:8, endln:6:20 + \_assignment: , line:6:8, endln:6:20 |vpiTypespec: \_ref_typespec: (work@tlul_socket_1n.i) |vpiParent: diff --git a/tests/PartSelectHier/PartSelectHier.log b/tests/PartSelectHier/PartSelectHier.log index 504fc1254d..6c3fe1d91e 100644 --- a/tests/PartSelectHier/PartSelectHier.log +++ b/tests/PartSelectHier/PartSelectHier.log @@ -278,7 +278,6 @@ design: (work@dut) \_hier_path: (drsp_fifo_o.d_source[8:3]), line:9:24, endln:9:49 |vpiParent: \_cont_assign: , line:9:10, endln:9:49 - |vpiName:drsp_fifo_o.d_source[8:3] |vpiActual: \_ref_obj: (drsp_fifo_o), line:9:24, endln:9:35 |vpiParent: @@ -303,6 +302,7 @@ design: (work@dut) |vpiSize:64 |UINT:3 |vpiConstType:9 + |vpiName:drsp_fifo_o.d_source[8:3] |vpiLhs: \_ref_obj: (work@dut.hfifo_rspid), line:9:10, endln:9:21 |vpiParent: @@ -353,7 +353,6 @@ design: (work@dut) \_hier_path: (drsp_fifo_o.d_source[8:3]), line:9:24, endln:9:49 |vpiParent: \_cont_assign: , line:9:10, endln:9:49 - |vpiName:drsp_fifo_o.d_source[8:3] |vpiActual: \_ref_obj: (drsp_fifo_o), line:9:24, endln:9:35 |vpiParent: @@ -374,6 +373,7 @@ design: (work@dut) \_constant: , line:9:45, endln:9:46 |vpiRightRange: \_constant: , line:9:47, endln:9:48 + |vpiName:drsp_fifo_o.d_source[8:3] |vpiLhs: \_ref_obj: (work@dut.hfifo_rspid), line:9:10, endln:9:21 |vpiParent: diff --git a/tests/PartSelectHierPath/PartSelectHierPath.log b/tests/PartSelectHierPath/PartSelectHierPath.log index 4887827939..46dab17329 100644 --- a/tests/PartSelectHierPath/PartSelectHierPath.log +++ b/tests/PartSelectHierPath/PartSelectHierPath.log @@ -300,7 +300,6 @@ design: (work@top) \_hier_path: (trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0]), line:13:41, endln:13:84 |vpiParent: \_cont_assign: , line:13:10, endln:13:84 - |vpiName:trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0] |vpiActual: \_ref_obj: (trace_rv_trace_pkt), line:13:41, endln:13:59 |vpiParent: @@ -325,6 +324,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0] |vpiLhs: \_part_select: trace_rv_i_insn_ip (work@top.trace_rv_i_insn_ip), line:13:10, endln:13:34 |vpiParent: @@ -376,7 +376,6 @@ design: (work@top) \_hier_path: (trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0]), line:13:41, endln:13:84 |vpiParent: \_cont_assign: , line:13:10, endln:13:84 - |vpiName:trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0] |vpiActual: \_ref_obj: (trace_rv_trace_pkt), line:13:41, endln:13:59 |vpiParent: @@ -397,6 +396,7 @@ design: (work@top) \_constant: , line:13:79, endln:13:81 |vpiRightRange: \_constant: , line:13:82, endln:13:83 + |vpiName:trace_rv_trace_pkt.trace_rv_i_insn_ip[63:0] |vpiLhs: \_part_select: trace_rv_i_insn_ip (work@top.trace_rv_i_insn_ip), line:13:10, endln:13:34 |vpiParent: diff --git a/tests/PartSelectNoParent/PartSelectNoParent.log b/tests/PartSelectNoParent/PartSelectNoParent.log index 4119dc949c..bad3d97ea6 100644 --- a/tests/PartSelectNoParent/PartSelectNoParent.log +++ b/tests/PartSelectNoParent/PartSelectNoParent.log @@ -237,8 +237,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 1 -assignment 1 +assignment 2 begin 1 constant 49 cont_assign 2 @@ -269,8 +268,7 @@ var_select 1 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 2 -assignment 2 +assignment 4 begin 2 constant 49 cont_assign 3 @@ -804,13 +802,13 @@ design: (work@top) \_named_begin: (work@top.key_sideload_get), line:14:24, endln:14:40 |vpiFullName:work@top.key_sideload_get |vpiForInitStmt: - \_assign_stmt: , line:15:12, endln:15:21 + \_assignment: , line:15:12, endln:15:21 |vpiParent: \_for_stmt: (work@top.key_sideload_get), line:15:7, endln:15:10 |vpiRhs: \_constant: , line:15:20, endln:15:21 |vpiParent: - \_assign_stmt: , line:15:12, endln:15:21 + \_assignment: , line:15:12, endln:15:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -818,7 +816,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.key_sideload_get.i), line:15:16, endln:15:17 |vpiParent: - \_assign_stmt: , line:15:12, endln:15:21 + \_assignment: , line:15:12, endln:15:21 |vpiTypespec: \_ref_typespec: (work@top.key_sideload_get.i) |vpiParent: @@ -885,7 +883,6 @@ design: (work@top) \_hier_path: (keymgr_key_i.key[0][31:0]), line:16:14, endln:16:41 |vpiParent: \_assignment: , line:16:10, endln:16:41 - |vpiName:keymgr_key_i.key[0][31:0] |vpiActual: \_ref_obj: (keymgr_key_i), line:16:14, endln:16:26 |vpiParent: @@ -925,6 +922,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:keymgr_key_i.key[0][31:0] |vpiLhs: \_ref_obj: (work@top.key_sideload_get.o), line:16:10, endln:16:11 |vpiParent: @@ -1122,7 +1120,7 @@ design: (work@top) \_named_begin: (work@top.key_sideload_get), line:14:24, endln:14:40 |vpiFullName:work@top.key_sideload_get |vpiForInitStmt: - \_assign_stmt: , line:15:12, endln:15:21 + \_assignment: , line:15:12, endln:15:21 |vpiParent: \_for_stmt: (work@top.key_sideload_get), line:15:7, endln:15:10 |vpiRhs: @@ -1130,7 +1128,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.key_sideload_get.i), line:15:16, endln:15:17 |vpiParent: - \_assign_stmt: , line:15:12, endln:15:21 + \_assignment: , line:15:12, endln:15:21 |vpiTypespec: \_ref_typespec: (work@top.key_sideload_get.i) |vpiParent: @@ -1184,7 +1182,6 @@ design: (work@top) \_hier_path: (keymgr_key_i.key[0][31:0]), line:16:14, endln:16:41 |vpiParent: \_assignment: , line:16:10, endln:16:41 - |vpiName:keymgr_key_i.key[0][31:0] |vpiActual: \_ref_obj: (keymgr_key_i), line:16:14, endln:16:26 |vpiParent: @@ -1214,6 +1211,7 @@ design: (work@top) \_constant: , line:16:34, endln:16:36 |vpiRightRange: \_constant: , line:16:39, endln:16:40 + |vpiName:keymgr_key_i.key[0][31:0] |vpiLhs: \_ref_obj: (work@top.key_sideload_get.o), line:16:10, endln:16:11 |vpiParent: diff --git a/tests/PartSelectRange/PartSelectRange.log b/tests/PartSelectRange/PartSelectRange.log index 4d1bea577a..5a69ed9e17 100644 --- a/tests/PartSelectRange/PartSelectRange.log +++ b/tests/PartSelectRange/PartSelectRange.log @@ -241,8 +241,7 @@ AST_DEBUG_END [WRN:EL0513] Nb undefined instances: 2. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 constant 75 design 1 @@ -270,8 +269,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 constant 75 design 1 @@ -393,7 +391,7 @@ design: (work@test) |vpiParent: \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/PartSelectRange/dut.sv, line:1:1, endln:19:10 |vpiForInitStmt: - \_assign_stmt: , line:7:7, endln:7:10 + \_assignment: , line:7:7, endln:7:10 |vpiParent: \_gen_for: |vpiRhs: @@ -405,7 +403,7 @@ design: (work@test) |vpiLhs: \_int_var: (work@test.i), line:7:7, endln:7:8 |vpiParent: - \_assign_stmt: , line:7:7, endln:7:10 + \_assignment: , line:7:7, endln:7:10 |vpiTypespec: \_ref_typespec: (work@test.i) |vpiParent: diff --git a/tests/PkgImportFunc/PkgImportFunc.log b/tests/PkgImportFunc/PkgImportFunc.log index 96a735b681..8e85c78903 100644 --- a/tests/PkgImportFunc/PkgImportFunc.log +++ b/tests/PkgImportFunc/PkgImportFunc.log @@ -108,7 +108,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 +assignment 4 begin 4 constant 7 cont_assign 2 @@ -131,7 +131,7 @@ return_stmt 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 8 +assignment 8 begin 8 constant 7 cont_assign 3 @@ -222,9 +222,11 @@ design: (work@top) |vpiFullName:prim_util_pkg::get_5::result |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (prim_util_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiDecompile:5 @@ -234,7 +236,7 @@ design: (work@top) |vpiLhs: \_int_var: (prim_util_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (prim_util_pkg::get_5::result) |vpiParent: @@ -323,13 +325,15 @@ design: (work@top) |vpiFullName:lc_ctrl_state_pkg::get_5::result |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (lc_ctrl_state_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiDecompile:5 |vpiSize:64 |UINT:5 @@ -337,7 +341,7 @@ design: (work@top) |vpiLhs: \_int_var: (lc_ctrl_state_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (lc_ctrl_state_pkg::get_5::result) |vpiParent: @@ -414,9 +418,11 @@ design: (work@top) |vpiFullName:prim_util_pkg::get_5::result |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (prim_util_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiDecompile:5 @@ -426,7 +432,7 @@ design: (work@top) |vpiLhs: \_int_var: (prim_util_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (prim_util_pkg::get_5::result) |vpiParent: @@ -505,13 +511,15 @@ design: (work@top) |vpiFullName:lc_ctrl_state_pkg::get_5::result |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (lc_ctrl_state_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiDecompile:5 |vpiSize:64 |UINT:5 @@ -519,7 +527,7 @@ design: (work@top) |vpiLhs: \_int_var: (lc_ctrl_state_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (lc_ctrl_state_pkg::get_5::result) |vpiParent: @@ -669,7 +677,7 @@ design: (work@top) |vpiVariables: \_int_var: (prim_util_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (prim_util_pkg::get_5::result) |vpiParent: @@ -692,9 +700,11 @@ design: (work@top) |vpiVariables: \_int_var: (prim_util_pkg::get_5::result), line:3:11, endln:3:17 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (prim_util_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiLhs: @@ -729,7 +739,7 @@ design: (work@top) |vpiVariables: \_int_var: (prim_util_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (prim_util_pkg::get_5::result) |vpiParent: @@ -752,9 +762,11 @@ design: (work@top) |vpiVariables: \_int_var: (prim_util_pkg::get_5::result), line:3:11, endln:3:17 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (prim_util_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiLhs: @@ -824,15 +836,17 @@ design: (work@top) |vpiFullName:lc_ctrl_state_pkg::get_5::result |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (lc_ctrl_state_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiLhs: \_int_var: (lc_ctrl_state_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (lc_ctrl_state_pkg::get_5::result) |vpiParent: @@ -926,15 +940,17 @@ design: (work@top) |vpiFullName:lc_ctrl_state_pkg::get_5::result |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiParent: \_begin: (lc_ctrl_state_pkg::get_5), line:4:7, endln:4:21 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiLhs: \_int_var: (lc_ctrl_state_pkg::get_5::result), line:3:11, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:11, endln:3:21 + \_assignment: , line:3:11, endln:3:21 |vpiTypespec: \_ref_typespec: (lc_ctrl_state_pkg::get_5::result) |vpiParent: diff --git a/tests/PortInterface/PortInterface.log b/tests/PortInterface/PortInterface.log index 0453dd3fd2..2bc25dac87 100644 --- a/tests/PortInterface/PortInterface.log +++ b/tests/PortInterface/PortInterface.log @@ -237,7 +237,6 @@ design: (work@top) \_hier_path: (ss_if.start_addr), line:9:11, endln:9:27 |vpiParent: \_cont_assign: , line:9:11, endln:9:38 - |vpiName:ss_if.start_addr |vpiActual: \_ref_obj: (ss_if), line:9:17, endln:9:27 |vpiParent: @@ -248,6 +247,7 @@ design: (work@top) |vpiParent: \_hier_path: (ss_if.start_addr), line:9:11, endln:9:27 |vpiName:start_addr + |vpiName:ss_if.start_addr |uhdmallModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PortInterface/dut.sv, line:12:1, endln:18:10 |vpiParent: @@ -296,7 +296,6 @@ design: (work@top) \_hier_path: (u_sim_sram_if.start_addr), line:17:14, endln:17:38 |vpiParent: \_cont_assign: , line:17:10, endln:17:38 - |vpiName:u_sim_sram_if.start_addr |vpiActual: \_ref_obj: (u_sim_sram_if), line:17:14, endln:17:27 |vpiParent: @@ -308,6 +307,7 @@ design: (work@top) \_hier_path: (u_sim_sram_if.start_addr), line:17:14, endln:17:38 |vpiName:start_addr |vpiFullName:work@top.start_addr + |vpiName:u_sim_sram_if.start_addr |vpiLhs: \_ref_obj: (work@top.o), line:17:10, endln:17:11 |vpiParent: @@ -488,7 +488,6 @@ design: (work@top) \_hier_path: (ss_if.start_addr), line:9:11, endln:9:27 |vpiParent: \_cont_assign: , line:9:11, endln:9:38 - |vpiName:ss_if.start_addr |vpiActual: \_ref_obj: (ss_if), line:9:17, endln:9:27 |vpiParent: @@ -503,6 +502,7 @@ design: (work@top) |vpiName:start_addr |vpiActual: \_int_var: (work@top.u_dut.ss_if.start_addr), line:5:8, endln:5:18 + |vpiName:ss_if.start_addr |vpiContAssign: \_cont_assign: , line:17:10, endln:17:38 |vpiParent: @@ -511,7 +511,6 @@ design: (work@top) \_hier_path: (u_sim_sram_if.start_addr), line:17:14, endln:17:38 |vpiParent: \_cont_assign: , line:17:10, endln:17:38 - |vpiName:u_sim_sram_if.start_addr |vpiActual: \_ref_obj: (u_sim_sram_if), line:17:14, endln:17:27 |vpiParent: @@ -527,6 +526,7 @@ design: (work@top) |vpiFullName:work@top.start_addr |vpiActual: \_int_var: (work@top.u_sim_sram_if.start_addr), line:5:8, endln:5:18 + |vpiName:u_sim_sram_if.start_addr |vpiLhs: \_ref_obj: (work@top.o), line:17:10, endln:17:11 |vpiParent: @@ -565,7 +565,6 @@ design: (work@top) \_hier_path: (ss_if.start_addr), line:9:11, endln:9:27 |vpiParent: \_cont_assign: , line:9:11, endln:9:38 - |vpiName:ss_if.start_addr |vpiActual: \_ref_obj: (ss_if), line:9:17, endln:9:27 |vpiParent: @@ -576,6 +575,7 @@ design: (work@top) |vpiParent: \_hier_path: (ss_if.start_addr), line:9:11, endln:9:27 |vpiName:start_addr + |vpiName:ss_if.start_addr =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/PpLppdr/PpLppdr.log b/tests/PpLppdr/PpLppdr.log index 52922cb8a1..3d8436ec5e 100644 --- a/tests/PpLppdr/PpLppdr.log +++ b/tests/PpLppdr/PpLppdr.log @@ -109,7 +109,7 @@ bit_select 1 constant 3 design 1 func_call 2 -logic_net 3 +logic_net 2 module_inst 2 ref_obj 5 task 1 @@ -122,7 +122,7 @@ bit_select 2 constant 3 design 1 func_call 4 -logic_net 3 +logic_net 2 module_inst 2 ref_obj 10 task 2 @@ -181,7 +181,7 @@ design: (work@top) |vpiName:wdata |vpiFullName:work@top.set_refgen_en.wdata |vpiActual: - \_logic_net: (work@top.wdata), line:11:74, endln:11:79 + \_bit_select: (work@top.set_refgen_en.wdata), line:12:36, endln:12:46 |vpiName:csr_read |vpiStmt: \_assignment: , line:12:36, endln:12:51 @@ -238,7 +238,7 @@ design: (work@top) |vpiName:wdata |vpiFullName:work@top.set_refgen_en.wdata |vpiActual: - \_logic_net: (work@top.wdata), line:11:74, endln:11:79 + \_bit_select: (work@top.set_refgen_en.wdata), line:12:36, endln:12:46 |vpiName:csr_write |vpiInstance: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 @@ -250,13 +250,6 @@ design: (work@top) |vpiFullName:work@top.DDR_CMN_OFFSET |vpiNetType:1 |vpiNet: - \_logic_net: (work@top.wdata), line:11:74, endln:11:79 - |vpiParent: - \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 - |vpiName:wdata - |vpiFullName:work@top.wdata - |vpiNetType:1 - |vpiNet: \_logic_net: (work@top.en), line:12:49, endln:12:51 |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 @@ -302,7 +295,7 @@ design: (work@top) |vpiName:wdata |vpiFullName:work@top.set_refgen_en.wdata |vpiActual: - \_logic_net: (work@top.wdata), line:11:74, endln:11:79 + \_bit_select: (work@top.set_refgen_en.wdata), line:12:36, endln:12:46 |vpiName:csr_read |vpiStmt: \_assignment: , line:12:36, endln:12:51 @@ -347,7 +340,7 @@ design: (work@top) |vpiName:wdata |vpiFullName:work@top.set_refgen_en.wdata |vpiActual: - \_logic_net: (work@top.wdata), line:11:74, endln:11:79 + \_bit_select: (work@top.set_refgen_en.wdata), line:12:36, endln:12:46 |vpiName:csr_write |vpiInstance: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/PpLppdr/dut.sv, line:16:1, endln:25:10 diff --git a/tests/PragmaProtect/PragmaProtect.log b/tests/PragmaProtect/PragmaProtect.log index d1cb2bc7a1..0b297b5f1e 100644 --- a/tests/PragmaProtect/PragmaProtect.log +++ b/tests/PragmaProtect/PragmaProtect.log @@ -18,8 +18,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 array_net 1 -assign_stmt 1 -assignment 7 +assignment 8 begin 6 bit_select 3 class_defn 8 diff --git a/tests/PreprocFunc/PreprocFunc.log b/tests/PreprocFunc/PreprocFunc.log index be01d9d4d5..5ab7c5d947 100644 --- a/tests/PreprocFunc/PreprocFunc.log +++ b/tests/PreprocFunc/PreprocFunc.log @@ -642,8 +642,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 5 +assignment 6 begin 2 class_defn 8 class_typespec 4 @@ -678,8 +677,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 10 +assignment 12 begin 4 class_defn 8 class_typespec 4 @@ -1604,13 +1602,13 @@ design: (work@asym_ram) \_begin: (work@asym_ram.log2), line:21:2, endln:26:5 |vpiFullName:work@asym_ram.log2 |vpiForInitStmt: - \_assign_stmt: , line:23:8, endln:23:13 + \_assignment: , line:23:8, endln:23:13 |vpiParent: \_for_stmt: (work@asym_ram.log2), line:23:3, endln:23:6 |vpiRhs: \_constant: , line:23:12, endln:23:13 |vpiParent: - \_assign_stmt: , line:23:8, endln:23:13 + \_assignment: , line:23:8, endln:23:13 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1618,7 +1616,7 @@ design: (work@asym_ram) |vpiLhs: \_ref_var: (work@asym_ram.log2.res), line:23:8, endln:23:11 |vpiParent: - \_assign_stmt: , line:23:8, endln:23:13 + \_assignment: , line:23:8, endln:23:13 |vpiName:res |vpiFullName:work@asym_ram.log2.res |vpiForIncStmt: @@ -2039,7 +2037,7 @@ design: (work@asym_ram) \_begin: (work@asym_ram.log2), line:21:2, endln:26:5 |vpiFullName:work@asym_ram.log2 |vpiForInitStmt: - \_assign_stmt: , line:23:8, endln:23:13 + \_assignment: , line:23:8, endln:23:13 |vpiParent: \_for_stmt: (work@asym_ram.log2), line:23:3, endln:23:6 |vpiRhs: @@ -2047,7 +2045,7 @@ design: (work@asym_ram) |vpiLhs: \_ref_var: (work@asym_ram.log2.res), line:23:8, endln:23:11 |vpiParent: - \_assign_stmt: , line:23:8, endln:23:13 + \_assignment: , line:23:8, endln:23:13 |vpiName:res |vpiFullName:work@asym_ram.log2.res |vpiActual: diff --git a/tests/ProcForLoop/ProcForLoop.log b/tests/ProcForLoop/ProcForLoop.log index 58bec1f95d..0d645a9494 100644 --- a/tests/ProcForLoop/ProcForLoop.log +++ b/tests/ProcForLoop/ProcForLoop.log @@ -412,8 +412,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 -assignment 1 +assignment 3 begin 3 class_defn 8 class_typespec 4 @@ -439,8 +438,7 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 -assignment 2 +assignment 6 begin 6 class_defn 8 class_typespec 4 @@ -984,13 +982,13 @@ design: (work@top) \_begin: (work@top.foo), line:6:7, endln:8:10 |vpiFullName:work@top.foo |vpiForInitStmt: - \_assign_stmt: , line:3:13, endln:3:20 + \_assignment: , line:3:13, endln:3:20 |vpiParent: \_for_stmt: (work@top.foo), line:3:7, endln:3:10 |vpiRhs: \_constant: , line:3:19, endln:3:20 |vpiParent: - \_assign_stmt: , line:3:13, endln:3:20 + \_assignment: , line:3:13, endln:3:20 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -998,7 +996,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.foo.i), line:3:17, endln:3:18 |vpiParent: - \_assign_stmt: , line:3:13, endln:3:20 + \_assignment: , line:3:13, endln:3:20 |vpiTypespec: \_ref_typespec: (work@top.foo.i) |vpiParent: @@ -1097,13 +1095,13 @@ design: (work@top) \_begin: (work@top.foo), line:6:7, endln:8:10 |vpiFullName:work@top.foo |vpiForInitStmt: - \_assign_stmt: , line:6:13, endln:6:21 + \_assignment: , line:6:13, endln:6:21 |vpiParent: \_for_stmt: (work@top.foo), line:6:7, endln:6:10 |vpiRhs: \_constant: , line:6:20, endln:6:21 |vpiParent: - \_assign_stmt: , line:6:13, endln:6:21 + \_assignment: , line:6:13, endln:6:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1111,7 +1109,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.foo.j), line:6:17, endln:6:18 |vpiParent: - \_assign_stmt: , line:6:13, endln:6:21 + \_assignment: , line:6:13, endln:6:21 |vpiTypespec: \_ref_typespec: (work@top.foo.j) |vpiParent: @@ -1209,7 +1207,7 @@ design: (work@top) \_begin: (work@top.foo), line:6:7, endln:8:10 |vpiFullName:work@top.foo |vpiForInitStmt: - \_assign_stmt: , line:3:13, endln:3:20 + \_assignment: , line:3:13, endln:3:20 |vpiParent: \_for_stmt: (work@top.foo), line:3:7, endln:3:10 |vpiRhs: @@ -1217,7 +1215,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.foo.i), line:3:17, endln:3:18 |vpiParent: - \_assign_stmt: , line:3:13, endln:3:20 + \_assignment: , line:3:13, endln:3:20 |vpiTypespec: \_ref_typespec: (work@top.foo.i) |vpiParent: @@ -1298,7 +1296,7 @@ design: (work@top) \_begin: (work@top.foo), line:6:7, endln:8:10 |vpiFullName:work@top.foo |vpiForInitStmt: - \_assign_stmt: , line:6:13, endln:6:21 + \_assignment: , line:6:13, endln:6:21 |vpiParent: \_for_stmt: (work@top.foo), line:6:7, endln:6:10 |vpiRhs: @@ -1306,7 +1304,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.foo.j), line:6:17, endln:6:18 |vpiParent: - \_assign_stmt: , line:6:13, endln:6:21 + \_assignment: , line:6:13, endln:6:21 |vpiTypespec: \_ref_typespec: (work@top.foo.j) |vpiParent: @@ -1595,5 +1593,5 @@ design: (work@top) ============================== Begin RoundTrip Results ============================== [roundtrip]: ${SURELOG_DIR}/tests/ProcForLoop/builtin.sv | ${SURELOG_DIR}/build/regression/ProcForLoop/roundtrip/builtin_000.sv | 0 | 0 | -[roundtrip]: ${SURELOG_DIR}/tests/ProcForLoop/dut.sv | ${SURELOG_DIR}/build/regression/ProcForLoop/roundtrip/dut_000.sv | 1 | 11 | +[roundtrip]: ${SURELOG_DIR}/tests/ProcForLoop/dut.sv | ${SURELOG_DIR}/build/regression/ProcForLoop/roundtrip/dut_000.sv | 2 | 11 | ============================== End RoundTrip Results ============================== diff --git a/tests/RangeSelect/RangeSelect.log b/tests/RangeSelect/RangeSelect.log index 59b41f7670..3c675329d9 100644 --- a/tests/RangeSelect/RangeSelect.log +++ b/tests/RangeSelect/RangeSelect.log @@ -165,7 +165,6 @@ design: (work@top) \_hier_path: (a[0].source[6-:2]), line:8:14, endln:8:33 |vpiParent: \_logic_var: (work@top.c), line:8:10, endln:8:33 - |vpiName:a[0].source[6-:2] |vpiActual: \_bit_select: (a[0]), line:8:14, endln:8:15 |vpiParent: @@ -200,6 +199,7 @@ design: (work@top) |vpiSize:64 |UINT:2 |vpiConstType:9 + |vpiName:a[0].source[6-:2] |vpiVariables: \_logic_var: (work@top.d), line:9:16, endln:9:36 |vpiParent: @@ -218,7 +218,6 @@ design: (work@top) \_hier_path: (b.source[6-:2]), line:9:20, endln:9:36 |vpiParent: \_logic_var: (work@top.d), line:9:16, endln:9:36 - |vpiName:b.source[6-:2] |vpiActual: \_ref_obj: (b), line:9:20, endln:9:21 |vpiParent: @@ -246,6 +245,7 @@ design: (work@top) |vpiSize:64 |UINT:2 |vpiConstType:9 + |vpiName:b.source[6-:2] |vpiTypedef: \_struct_typespec: (tl_h2d_t), line:2:12, endln:6:17 |vpiDefName:work@top diff --git a/tests/RewriteNonConstForLoopCond/RewriteNonConstForLoopCond.log b/tests/RewriteNonConstForLoopCond/RewriteNonConstForLoopCond.log index bdad0e535e..0de4655bd1 100644 --- a/tests/RewriteNonConstForLoopCond/RewriteNonConstForLoopCond.log +++ b/tests/RewriteNonConstForLoopCond/RewriteNonConstForLoopCond.log @@ -151,8 +151,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 1 -assignment 2 +assignment 3 begin 3 constant 6 design 1 @@ -171,8 +170,7 @@ ref_typespec 3 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 2 -assignment 4 +assignment 6 begin 6 constant 6 design 1 @@ -258,13 +256,13 @@ design: (work@top) \_begin: (work@top), line:6:6, endln:17:9 |vpiFullName:work@top |vpiForInitStmt: - \_assign_stmt: , line:10:14, endln:10:21 + \_assignment: , line:10:14, endln:10:21 |vpiParent: \_for_stmt: (work@top), line:10:9, endln:10:12 |vpiRhs: \_constant: , line:10:20, endln:10:21 |vpiParent: - \_assign_stmt: , line:10:14, endln:10:21 + \_assignment: , line:10:14, endln:10:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -272,7 +270,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:10:18, endln:10:19 |vpiParent: - \_assign_stmt: , line:10:14, endln:10:21 + \_assignment: , line:10:14, endln:10:21 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -450,7 +448,7 @@ design: (work@top) \_begin: (work@top), line:6:6, endln:17:9 |vpiFullName:work@top |vpiForInitStmt: - \_assign_stmt: , line:10:14, endln:10:21 + \_assignment: , line:10:14, endln:10:21 |vpiParent: \_for_stmt: (work@top), line:10:9, endln:10:12 |vpiRhs: @@ -458,7 +456,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:10:18, endln:10:19 |vpiParent: - \_assign_stmt: , line:10:14, endln:10:21 + \_assignment: , line:10:14, endln:10:21 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -578,5 +576,5 @@ design: (work@top) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/RewriteNonConstForLoopCond/dut.sv | ${SURELOG_DIR}/build/regression/RewriteNonConstForLoopCond/roundtrip/dut_000.sv | 0 | 20 | +[roundtrip]: ${SURELOG_DIR}/tests/RewriteNonConstForLoopCond/dut.sv | ${SURELOG_DIR}/build/regression/RewriteNonConstForLoopCond/roundtrip/dut_000.sv | 1 | 20 | ============================== End RoundTrip Results ============================== diff --git a/tests/SelectHierPath/SelectHierPath.log b/tests/SelectHierPath/SelectHierPath.log index 87f409f751..7b473a4955 100644 --- a/tests/SelectHierPath/SelectHierPath.log +++ b/tests/SelectHierPath/SelectHierPath.log @@ -168,7 +168,6 @@ design: (work@IntegerRegisterWriteStage) \_hier_path: (pipeReg[1].brResult.nextAddr), line:14:12, endln:14:40 |vpiParent: \_cont_assign: , line:14:8, endln:14:40 - |vpiName:pipeReg[1].brResult.nextAddr |vpiActual: \_bit_select: (pipeReg[1]), line:14:12, endln:14:19 |vpiParent: @@ -192,6 +191,7 @@ design: (work@IntegerRegisterWriteStage) \_hier_path: (pipeReg[1].brResult.nextAddr), line:14:12, endln:14:40 |vpiName:nextAddr |vpiFullName:work@IntegerRegisterWriteStage.nextAddr + |vpiName:pipeReg[1].brResult.nextAddr |vpiLhs: \_ref_obj: (work@IntegerRegisterWriteStage.o), line:14:8, endln:14:9 |vpiParent: @@ -314,7 +314,6 @@ design: (work@IntegerRegisterWriteStage) \_hier_path: (pipeReg[1].brResult.nextAddr), line:14:12, endln:14:40 |vpiParent: \_cont_assign: , line:14:8, endln:14:40 - |vpiName:pipeReg[1].brResult.nextAddr |vpiActual: \_bit_select: (pipeReg[1]), line:14:12, endln:14:19 |vpiParent: @@ -340,6 +339,7 @@ design: (work@IntegerRegisterWriteStage) |vpiFullName:work@IntegerRegisterWriteStage.nextAddr |vpiActual: \_typespec_member: (nextAddr), line:2:9, endln:2:17 + |vpiName:pipeReg[1].brResult.nextAddr |vpiLhs: \_ref_obj: (work@IntegerRegisterWriteStage.o), line:14:8, endln:14:9 |vpiParent: diff --git a/tests/SelectSelect/SelectSelect.log b/tests/SelectSelect/SelectSelect.log index 2e10750805..fee85380b5 100644 --- a/tests/SelectSelect/SelectSelect.log +++ b/tests/SelectSelect/SelectSelect.log @@ -1068,7 +1068,6 @@ design: (work@adc_ctrl_core) \_hier_path: (a[0][0].min_v), line:7:20, endln:7:33 |vpiParent: \_logic_var: (work@adc_ctrl_core.x), line:7:16, endln:7:33 - |vpiName:a[0][0].min_v |vpiActual: \_bit_select: (a[0]), line:7:20, endln:7:21 |vpiParent: @@ -1100,6 +1099,7 @@ design: (work@adc_ctrl_core) \_hier_path: (a[0][0].min_v), line:7:20, endln:7:33 |vpiName:min_v |vpiFullName:work@adc_ctrl_core.x.min_v + |vpiName:a[0][0].min_v |vpiTypedef: \_struct_typespec: (filter_ctl_t), line:2:12, endln:4:5 |vpiDefName:work@adc_ctrl_core diff --git a/tests/Selects/Selects.log b/tests/Selects/Selects.log index 905d566647..901dcbb8ec 100644 --- a/tests/Selects/Selects.log +++ b/tests/Selects/Selects.log @@ -382,7 +382,6 @@ design: (work@t) \_hier_path: (reg2hw.sw_rst_ctrl_n[0].q), line:14:13, endln:14:38 |vpiParent: \_logic_var: (work@t.X), line:14:9, endln:14:38 - |vpiName:reg2hw.sw_rst_ctrl_n[0].q |vpiActual: \_ref_obj: (reg2hw), line:14:13, endln:14:19 |vpiParent: @@ -410,6 +409,7 @@ design: (work@t) \_hier_path: (reg2hw.sw_rst_ctrl_n[0].q), line:14:13, endln:14:38 |vpiName:q |vpiFullName:work@t.X.q + |vpiName:reg2hw.sw_rst_ctrl_n[0].q |vpiVariables: \_logic_var: (work@t.Y), line:15:9, endln:15:31 |vpiParent: @@ -428,7 +428,6 @@ design: (work@t) \_hier_path: (sw_rst_ctrl_n[0].q), line:15:13, endln:15:31 |vpiParent: \_logic_var: (work@t.Y), line:15:9, endln:15:31 - |vpiName:sw_rst_ctrl_n[0].q |vpiActual: \_bit_select: (sw_rst_ctrl_n[0]), line:15:13, endln:15:26 |vpiParent: @@ -449,6 +448,7 @@ design: (work@t) \_hier_path: (sw_rst_ctrl_n[0].q), line:15:13, endln:15:31 |vpiName:q |vpiFullName:work@t.Y.q + |vpiName:sw_rst_ctrl_n[0].q |vpiTypedef: \_struct_typespec: (rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t), line:3:11, endln:5:4 |vpiTypedef: diff --git a/tests/SimpleClass1/SimpleClass1.log b/tests/SimpleClass1/SimpleClass1.log index 47db4c915c..0e42d14508 100644 --- a/tests/SimpleClass1/SimpleClass1.log +++ b/tests/SimpleClass1/SimpleClass1.log @@ -403,8 +403,7 @@ Instance tree: === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 686 array_var 664 -assign_stmt 3550 -assignment 6293 +assignment 9843 begin 6772 bit_select 2126 bit_typespec 9936 @@ -468,12 +467,12 @@ range 9969 real_typespec 33 real_var 8 ref_obj 41265 -ref_typespec 31270 +ref_typespec 31268 ref_var 1789 repeat 26 return_stmt 3276 -string_typespec 3665 -string_var 1632 +string_typespec 3663 +string_var 1630 struct_typespec 14 struct_var 35 sys_func_call 1314 @@ -4052,15 +4051,12 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2156:11: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2179:12: Unsupported typespec, m_sync [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2230:12: Unsupported typespec, m_successors -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:15: Unsupported typespec, m_object_names [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: Unsupported typespec, i [LINT]: \_ ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: @@ -4492,7 +4488,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4500,8 +4495,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/tests/SimpleConstraint/SimpleConstraint.log b/tests/SimpleConstraint/SimpleConstraint.log index d444ba7a0d..df8d38c216 100644 --- a/tests/SimpleConstraint/SimpleConstraint.log +++ b/tests/SimpleConstraint/SimpleConstraint.log @@ -1008,8 +1008,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1 array_var 1 -assign_stmt 4 -assignment 4 +assignment 8 begin 11 bit_select 1 bit_typespec 1 diff --git a/tests/SimpleInterface/SimpleInterface.log b/tests/SimpleInterface/SimpleInterface.log index 64e224f9f7..bbe7ac474a 100644 --- a/tests/SimpleInterface/SimpleInterface.log +++ b/tests/SimpleInterface/SimpleInterface.log @@ -1787,8 +1787,7 @@ Instance tree: always 3 array_typespec 615 array_var 593 -assign_stmt 3548 -assignment 6303 +assignment 9851 begin 6770 bit_select 2128 bit_typespec 4736 @@ -1861,12 +1860,12 @@ real_typespec 33 real_var 8 ref_module 2 ref_obj 41270 -ref_typespec 23809 +ref_typespec 23807 ref_var 1789 repeat 26 return_stmt 3272 -string_typespec 3335 -string_var 1421 +string_typespec 3333 +string_var 1419 struct_typespec 14 struct_var 35 sys_func_call 1285 @@ -5407,15 +5406,12 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2156:11: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2179:12: Unsupported typespec, m_sync [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2230:12: Unsupported typespec, m_successors -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:15: Unsupported typespec, m_object_names [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: Unsupported typespec, i [LINT]: \_ ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: @@ -5847,7 +5843,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -5855,8 +5850,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/tests/StandardBlock/StandardBlock.log b/tests/StandardBlock/StandardBlock.log index cb9c8a8b0d..9b31b177c3 100644 --- a/tests/StandardBlock/StandardBlock.log +++ b/tests/StandardBlock/StandardBlock.log @@ -260,8 +260,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 9 -assignment 2 +assignment 11 begin 8 constant 31 design 1 @@ -287,8 +286,7 @@ unsupported_typespec 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 9 -assignment 2 +assignment 11 begin 8 constant 31 design 1 @@ -384,13 +382,15 @@ design: (work@top) \_gen_if_else: |vpiFullName:work@top |vpiStmt: - \_assign_stmt: , line:5:20, endln:5:21 + \_assignment: , line:5:20, endln:5:21 |vpiParent: \_begin: (work@top) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.a), line:5:20, endln:5:21 |vpiParent: - \_assign_stmt: , line:5:20, endln:5:21 + \_assignment: , line:5:20, endln:5:21 |vpiTypespec: \_ref_typespec: (work@top.a) |vpiParent: @@ -406,13 +406,15 @@ design: (work@top) \_gen_if_else: |vpiFullName:work@top |vpiStmt: - \_assign_stmt: , line:6:12, endln:6:13 + \_assignment: , line:6:12, endln:6:13 |vpiParent: \_begin: (work@top) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.b), line:6:12, endln:6:13 |vpiParent: - \_assign_stmt: , line:6:12, endln:6:13 + \_assignment: , line:6:12, endln:6:13 |vpiTypespec: \_ref_typespec: (work@top.b) |vpiParent: @@ -438,13 +440,15 @@ design: (work@top) \_gen_if_else: |vpiFullName:work@top |vpiStmt: - \_assign_stmt: , line:9:20, endln:9:21 + \_assignment: , line:9:20, endln:9:21 |vpiParent: \_begin: (work@top) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.a), line:9:20, endln:9:21 |vpiParent: - \_assign_stmt: , line:9:20, endln:9:21 + \_assignment: , line:9:20, endln:9:21 |vpiTypespec: \_ref_typespec: (work@top.a) |vpiParent: @@ -460,13 +464,15 @@ design: (work@top) \_gen_if_else: |vpiFullName:work@top |vpiStmt: - \_assign_stmt: , line:10:12, endln:10:13 + \_assignment: , line:10:12, endln:10:13 |vpiParent: \_begin: (work@top) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.b), line:10:12, endln:10:13 |vpiParent: - \_assign_stmt: , line:10:12, endln:10:13 + \_assignment: , line:10:12, endln:10:13 |vpiTypespec: \_ref_typespec: (work@top.b) |vpiParent: @@ -481,7 +487,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiForInitStmt: - \_assign_stmt: , line:13:6, endln:13:11 + \_assignment: , line:13:6, endln:13:11 |vpiParent: \_gen_for: |vpiRhs: @@ -493,7 +499,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:13:6, endln:13:7 |vpiParent: - \_assign_stmt: , line:13:6, endln:13:11 + \_assignment: , line:13:6, endln:13:11 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -582,13 +588,15 @@ design: (work@top) \_gen_if: , line:16:1, endln:16:3 |vpiFullName:work@top.g1 |vpiStmt: - \_assign_stmt: , line:16:14, endln:16:15 + \_assignment: , line:16:14, endln:16:15 |vpiParent: \_begin: (work@top.g1) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.g1.a), line:16:14, endln:16:15 |vpiParent: - \_assign_stmt: , line:16:14, endln:16:15 + \_assignment: , line:16:14, endln:16:15 |vpiTypespec: \_ref_typespec: (work@top.g1.a) |vpiParent: @@ -603,7 +611,7 @@ design: (work@top) |vpiParent: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StandardBlock/dut.sv, line:1:1, endln:28:10 |vpiForInitStmt: - \_assign_stmt: , line:22:6, endln:22:11 + \_assignment: , line:22:6, endln:22:11 |vpiParent: \_gen_for: |vpiRhs: @@ -615,7 +623,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:22:6, endln:22:7 |vpiParent: - \_assign_stmt: , line:22:6, endln:22:11 + \_assignment: , line:22:6, endln:22:11 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -703,13 +711,15 @@ design: (work@top) \_gen_if: , line:25:1, endln:25:3 |vpiFullName:work@top |vpiStmt: - \_assign_stmt: , line:25:14, endln:25:15 + \_assignment: , line:25:14, endln:25:15 |vpiParent: \_begin: (work@top) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.a), line:25:14, endln:25:15 |vpiParent: - \_assign_stmt: , line:25:14, endln:25:15 + \_assignment: , line:25:14, endln:25:15 |vpiTypespec: \_ref_typespec: (work@top.a) |vpiParent: @@ -737,13 +747,15 @@ design: (work@top) \_gen_if: , line:27:1, endln:27:3 |vpiFullName:work@top |vpiStmt: - \_assign_stmt: , line:27:14, endln:27:15 + \_assignment: , line:27:14, endln:27:15 |vpiParent: \_begin: (work@top) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@top.a), line:27:14, endln:27:15 |vpiParent: - \_assign_stmt: , line:27:14, endln:27:15 + \_assignment: , line:27:14, endln:27:15 |vpiTypespec: \_ref_typespec: (work@top.a) |vpiParent: diff --git a/tests/StaticTask/StaticTask.log b/tests/StaticTask/StaticTask.log index 4e63b74eae..7e56d3ed5b 100644 --- a/tests/StaticTask/StaticTask.log +++ b/tests/StaticTask/StaticTask.log @@ -94,8 +94,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 constant 3 design 1 @@ -112,8 +111,7 @@ task_call 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 2 constant 3 design 1 @@ -151,7 +149,7 @@ design: (work@tb) |vpiVariables: \_integer_var: (work@tb.display.i), line:6:10, endln:6:11 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:15 + \_assignment: , line:6:10, endln:6:15 |vpiTypespec: \_ref_typespec: (work@tb.display.i) |vpiParent: @@ -171,9 +169,11 @@ design: (work@tb) |vpiVariables: \_integer_var: (work@tb.display.i), line:6:10, endln:6:11 |vpiStmt: - \_assign_stmt: , line:6:10, endln:6:15 + \_assignment: , line:6:10, endln:6:15 |vpiParent: \_begin: (work@tb.display), line:7:2, endln:7:12 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:6:14, endln:6:15 |vpiDecompile:0 @@ -297,15 +297,17 @@ design: (work@tb) |vpiFullName:work@tb.display.i |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:6:10, endln:6:15 + \_assignment: , line:6:10, endln:6:15 |vpiParent: \_begin: (work@tb.display), line:7:2, endln:7:12 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:6:14, endln:6:15 |vpiLhs: \_integer_var: (work@tb.display.i), line:6:10, endln:6:11 |vpiParent: - \_assign_stmt: , line:6:10, endln:6:15 + \_assignment: , line:6:10, endln:6:15 |vpiTypespec: \_ref_typespec: (work@tb.display.i) |vpiParent: diff --git a/tests/StringMethod/StringMethod.log b/tests/StringMethod/StringMethod.log index 15ef94fd71..48c28996b3 100644 --- a/tests/StringMethod/StringMethod.log +++ b/tests/StringMethod/StringMethod.log @@ -1116,7 +1116,6 @@ design: (work@top) \_hier_path: (s.substr), line:3:15, endln:3:29 |vpiParent: \_string_var: (work@top.t), line:3:11, endln:3:29 - |vpiName:s.substr |vpiActual: \_ref_obj: (s), line:3:15, endln:3:16 |vpiParent: @@ -1145,6 +1144,7 @@ design: (work@top) |UINT:2 |vpiConstType:9 |vpiName:substr + |vpiName:s.substr |vpiVariables: \_byte_var: (work@top.a), line:7:9, endln:7:22 |vpiParent: @@ -1163,7 +1163,6 @@ design: (work@top) \_hier_path: (s.getc), line:7:13, endln:7:22 |vpiParent: \_byte_var: (work@top.a), line:7:9, endln:7:22 - |vpiName:s.getc |vpiActual: \_ref_obj: (s), line:7:13, endln:7:14 |vpiParent: @@ -1184,6 +1183,7 @@ design: (work@top) |UINT:1 |vpiConstType:9 |vpiName:getc + |vpiName:s.getc |vpiVariables: \_int_var: (work@top.b), line:8:9, endln:8:25 |vpiParent: @@ -1202,7 +1202,6 @@ design: (work@top) \_hier_path: (s.compare), line:8:13, endln:8:25 |vpiParent: \_int_var: (work@top.b), line:8:9, endln:8:25 - |vpiName:s.compare |vpiActual: \_ref_obj: (s), line:8:13, endln:8:14 |vpiParent: @@ -1223,6 +1222,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.t), line:3:11, endln:3:12 |vpiName:compare + |vpiName:s.compare |vpiVariables: \_int_var: (work@top.c), line:9:9, endln:9:26 |vpiParent: @@ -1241,7 +1241,6 @@ design: (work@top) \_hier_path: (s.icompare), line:9:13, endln:9:26 |vpiParent: \_int_var: (work@top.c), line:9:9, endln:9:26 - |vpiName:s.icompare |vpiActual: \_ref_obj: (s), line:9:13, endln:9:14 |vpiParent: @@ -1262,6 +1261,7 @@ design: (work@top) |vpiActual: \_logic_net: (work@top.t), line:3:11, endln:3:12 |vpiName:icompare + |vpiName:s.icompare |vpiDefName:work@top |vpiTop:1 |vpiTopModule:1 diff --git a/tests/StringRange/StringRange.log b/tests/StringRange/StringRange.log index a43911545a..928daf7d9a 100644 --- a/tests/StringRange/StringRange.log +++ b/tests/StringRange/StringRange.log @@ -1750,8 +1750,7 @@ AST_DEBUG_END [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 1 -assignment 11 +assignment 12 begin 5 constant 5558 cont_assign 20 @@ -1790,8 +1789,7 @@ sys_func_call 6 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 2 -assign_stmt 5 -assignment 46 +assignment 51 begin 10 constant 5558 cont_assign 29 @@ -2098,13 +2096,13 @@ design: (work@top) \_begin: (work@Example), line:31:13, endln:36:8 |vpiFullName:work@Example |vpiForInitStmt: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiParent: \_for_stmt: (work@Example), line:33:9, endln:33:12 |vpiRhs: \_constant: , line:33:18, endln:33:19 |vpiParent: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2112,7 +2110,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@Example.j), line:33:14, endln:33:15 |vpiParent: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiName:j |vpiFullName:work@Example.j |vpiForIncStmt: @@ -4698,7 +4696,7 @@ design: (work@top) \_begin: (work@top.e1), line:31:13, endln:36:8 |vpiFullName:work@top.e1 |vpiForInitStmt: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiParent: \_for_stmt: (work@top.e1), line:33:9, endln:33:12 |vpiRhs: @@ -4706,7 +4704,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@top.e1.j), line:33:14, endln:33:15 |vpiParent: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiName:j |vpiFullName:work@top.e1.j |vpiActual: @@ -7406,7 +7404,7 @@ design: (work@top) \_begin: (work@top.e2), line:31:13, endln:36:8 |vpiFullName:work@top.e2 |vpiForInitStmt: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiParent: \_for_stmt: (work@top.e2), line:33:9, endln:33:12 |vpiRhs: @@ -7414,7 +7412,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@top.e2.j), line:33:14, endln:33:15 |vpiParent: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiName:j |vpiFullName:work@top.e2.j |vpiActual: @@ -10114,7 +10112,7 @@ design: (work@top) \_begin: (work@top.e3), line:31:13, endln:36:8 |vpiFullName:work@top.e3 |vpiForInitStmt: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiParent: \_for_stmt: (work@top.e3), line:33:9, endln:33:12 |vpiRhs: @@ -10122,7 +10120,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@top.e3.j), line:33:14, endln:33:15 |vpiParent: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiName:j |vpiFullName:work@top.e3.j |vpiActual: @@ -12423,7 +12421,7 @@ design: (work@top) \_begin: (work@top.e4), line:31:13, endln:36:8 |vpiFullName:work@top.e4 |vpiForInitStmt: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiParent: \_for_stmt: (work@top.e4), line:33:9, endln:33:12 |vpiRhs: @@ -12431,7 +12429,7 @@ design: (work@top) |vpiLhs: \_ref_var: (work@top.e4.j), line:33:14, endln:33:15 |vpiParent: - \_assign_stmt: , line:33:14, endln:33:19 + \_assignment: , line:33:14, endln:33:19 |vpiName:j |vpiFullName:work@top.e4.j |vpiActual: diff --git a/tests/StructAccess/StructAccess.log b/tests/StructAccess/StructAccess.log index 36b855b723..a847ce696e 100644 --- a/tests/StructAccess/StructAccess.log +++ b/tests/StructAccess/StructAccess.log @@ -1267,7 +1267,6 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_ie.mode), line:28:9, endln:28:28 |vpiParent: \_cont_assign: , line:28:9, endln:28:43 - |vpiName:csr_pmp_cfg_ie.mode |vpiActual: \_ref_obj: (csr_pmp_cfg_ie), line:28:24, endln:28:28 |vpiParent: @@ -1278,6 +1277,7 @@ design: (work@top) |vpiParent: \_hier_path: (csr_pmp_cfg_ie.mode), line:28:9, endln:28:28 |vpiName:mode + |vpiName:csr_pmp_cfg_ie.mode |uhdmtopModules: \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/StructAccess/dut.sv, line:1:1, endln:30:10 |vpiName:work@top @@ -1416,7 +1416,6 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_i[0].mode), line:24:23, endln:24:44 |vpiParent: \_enum_var: (work@top.first), line:24:15, endln:24:20 - |vpiName:csr_pmp_cfg_i[0].mode |vpiActual: \_bit_select: (csr_pmp_cfg_i[0]), line:24:23, endln:24:36 |vpiParent: @@ -1437,6 +1436,7 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_i[0].mode), line:24:23, endln:24:44 |vpiName:mode |vpiFullName:work@top.first.mode + |vpiName:csr_pmp_cfg_i[0].mode |vpiVariables: \_logic_var: (work@top.second), line:25:8, endln:25:39 |vpiParent: @@ -1455,7 +1455,6 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_ie.mode[0]), line:25:17, endln:25:39 |vpiParent: \_logic_var: (work@top.second), line:25:8, endln:25:39 - |vpiName:csr_pmp_cfg_ie.mode[0] |vpiActual: \_ref_obj: (csr_pmp_cfg_ie), line:25:17, endln:25:31 |vpiParent: @@ -1477,6 +1476,7 @@ design: (work@top) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiName:csr_pmp_cfg_ie.mode[0] |vpiVariables: \_logic_var: (work@top.third), line:26:8, endln:26:43 |vpiParent: @@ -1495,7 +1495,6 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_ie.struct_var.a), line:26:16, endln:26:43 |vpiParent: \_logic_var: (work@top.third), line:26:8, endln:26:43 - |vpiName:csr_pmp_cfg_ie.struct_var.a |vpiActual: \_ref_obj: (csr_pmp_cfg_ie), line:26:16, endln:26:30 |vpiParent: @@ -1514,6 +1513,7 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_ie.struct_var.a), line:26:16, endln:26:43 |vpiName:a |vpiFullName:work@top.third.a + |vpiName:csr_pmp_cfg_ie.struct_var.a |vpiTypedef: \_enum_typespec: (pmp_cfg_enum), line:3:2, endln:5:17 |vpiTypedef: @@ -1559,7 +1559,6 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_ie.mode), line:28:9, endln:28:28 |vpiParent: \_cont_assign: , line:28:9, endln:28:43 - |vpiName:csr_pmp_cfg_ie.mode |vpiActual: \_ref_obj: (csr_pmp_cfg_ie), line:28:24, endln:28:28 |vpiParent: @@ -1574,6 +1573,7 @@ design: (work@top) |vpiName:mode |vpiActual: \_typespec_member: (mode), line:12:17, endln:12:21 + |vpiName:csr_pmp_cfg_ie.mode \_weaklyReferenced: \_logic_typespec: , line:3:15, endln:3:26 |vpiRange: @@ -1847,7 +1847,6 @@ design: (work@top) \_hier_path: (csr_pmp_cfg_ie.mode), line:28:9, endln:28:28 |vpiParent: \_cont_assign: , line:28:9, endln:28:43 - |vpiName:csr_pmp_cfg_ie.mode |vpiActual: \_ref_obj: (csr_pmp_cfg_ie), line:28:24, endln:28:28 |vpiParent: @@ -1858,6 +1857,7 @@ design: (work@top) |vpiParent: \_hier_path: (csr_pmp_cfg_ie.mode), line:28:9, endln:28:28 |vpiName:mode + |vpiName:csr_pmp_cfg_ie.mode =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/StructNetUnionTypespec/StructNetUnionTypespec.log b/tests/StructNetUnionTypespec/StructNetUnionTypespec.log index 882db1f768..723a8e9298 100644 --- a/tests/StructNetUnionTypespec/StructNetUnionTypespec.log +++ b/tests/StructNetUnionTypespec/StructNetUnionTypespec.log @@ -1089,7 +1089,6 @@ design: (work@AnonymousUnion) \_hier_path: (un.v1), line:8:7, endln:8:12 |vpiParent: \_assignment: , line:8:7, endln:8:16 - |vpiName:un.v1 |vpiActual: \_ref_obj: (un), line:8:10, endln:8:12 |vpiParent: @@ -1100,6 +1099,7 @@ design: (work@AnonymousUnion) |vpiParent: \_hier_path: (un.v1), line:8:7, endln:8:12 |vpiName:v1 + |vpiName:un.v1 |vpiStmt: \_assignment: , line:9:7, endln:9:16 |vpiParent: @@ -1110,7 +1110,6 @@ design: (work@AnonymousUnion) \_hier_path: (un.v2), line:9:11, endln:9:16 |vpiParent: \_assignment: , line:9:7, endln:9:16 - |vpiName:un.v2 |vpiActual: \_ref_obj: (un), line:9:11, endln:9:13 |vpiParent: @@ -1122,6 +1121,7 @@ design: (work@AnonymousUnion) \_hier_path: (un.v2), line:9:11, endln:9:16 |vpiName:v2 |vpiFullName:work@AnonymousUnion.v2 + |vpiName:un.v2 |vpiLhs: \_ref_obj: (work@AnonymousUnion.o), line:9:7, endln:9:8 |vpiParent: @@ -1216,7 +1216,6 @@ design: (work@AnonymousUnion) \_hier_path: (un.field), line:20:11, endln:20:19 |vpiParent: \_assignment: , line:20:7, endln:20:19 - |vpiName:un.field |vpiActual: \_ref_obj: (un), line:20:11, endln:20:13 |vpiParent: @@ -1228,6 +1227,7 @@ design: (work@AnonymousUnion) \_hier_path: (un.field), line:20:11, endln:20:19 |vpiName:field |vpiFullName:work@AssignToUnionAndReadField.field + |vpiName:un.field |vpiLhs: \_ref_obj: (work@AssignToUnionAndReadField.o), line:20:7, endln:20:8 |vpiParent: @@ -1314,7 +1314,6 @@ design: (work@AnonymousUnion) \_hier_path: (un.v1), line:8:7, endln:8:12 |vpiParent: \_assignment: , line:8:7, endln:8:16 - |vpiName:un.v1 |vpiActual: \_ref_obj: (un), line:8:10, endln:8:12 |vpiParent: @@ -1329,6 +1328,7 @@ design: (work@AnonymousUnion) |vpiName:v1 |vpiActual: \_typespec_member: (v1), line:3:11, endln:3:13 + |vpiName:un.v1 |vpiStmt: \_assignment: , line:9:7, endln:9:16 |vpiParent: @@ -1339,7 +1339,6 @@ design: (work@AnonymousUnion) \_hier_path: (un.v2), line:9:11, endln:9:16 |vpiParent: \_assignment: , line:9:7, endln:9:16 - |vpiName:un.v2 |vpiActual: \_ref_obj: (un), line:9:11, endln:9:13 |vpiParent: @@ -1355,6 +1354,7 @@ design: (work@AnonymousUnion) |vpiFullName:work@AnonymousUnion.v2 |vpiActual: \_typespec_member: (v2), line:4:11, endln:4:13 + |vpiName:un.v2 |vpiLhs: \_ref_obj: (work@AnonymousUnion.o), line:9:7, endln:9:8 |vpiParent: @@ -1454,7 +1454,6 @@ design: (work@AnonymousUnion) \_hier_path: (un.field), line:20:11, endln:20:19 |vpiParent: \_assignment: , line:20:7, endln:20:19 - |vpiName:un.field |vpiActual: \_ref_obj: (un), line:20:11, endln:20:13 |vpiParent: @@ -1470,6 +1469,7 @@ design: (work@AnonymousUnion) |vpiFullName:work@AssignToUnionAndReadField.field |vpiActual: \_typespec_member: (field), line:15:17, endln:15:22 + |vpiName:un.field |vpiLhs: \_ref_obj: (work@AssignToUnionAndReadField.o), line:20:7, endln:20:8 |vpiParent: diff --git a/tests/StructStructHierPath/StructStructHierPath.log b/tests/StructStructHierPath/StructStructHierPath.log index 48d9ee5808..ed1e8102c8 100644 --- a/tests/StructStructHierPath/StructStructHierPath.log +++ b/tests/StructStructHierPath/StructStructHierPath.log @@ -563,7 +563,6 @@ design: (work@r5p_wbu) \_hier_path: (ctl.gpr.e.rd), line:33:12, endln:33:24 |vpiParent: \_assignment: , line:33:5, endln:33:24 - |vpiName:ctl.gpr.e.rd |vpiActual: \_ref_obj: (ctl), line:33:12, endln:33:15 |vpiParent: @@ -585,6 +584,7 @@ design: (work@r5p_wbu) \_hier_path: (ctl.gpr.e.rd), line:33:12, endln:33:24 |vpiName:rd |vpiFullName:work@r5p_wbu.rd + |vpiName:ctl.gpr.e.rd |vpiLhs: \_ref_obj: (work@r5p_wbu.wen), line:33:5, endln:33:8 |vpiParent: @@ -703,7 +703,6 @@ design: (work@r5p_wbu) \_hier_path: (ctl.gpr.e.rd), line:33:12, endln:33:24 |vpiParent: \_assignment: , line:33:5, endln:33:24 - |vpiName:ctl.gpr.e.rd |vpiActual: \_ref_obj: (ctl), line:33:12, endln:33:15 |vpiParent: @@ -733,6 +732,7 @@ design: (work@r5p_wbu) |vpiFullName:work@r5p_wbu.rd |vpiActual: \_typespec_member: (rd), line:8:19, endln:8:21 + |vpiName:ctl.gpr.e.rd |vpiLhs: \_ref_obj: (work@r5p_wbu.wen), line:33:5, endln:33:8 |vpiParent: diff --git a/tests/StructVar/StructVar.log b/tests/StructVar/StructVar.log index f4f4fa4be3..33dd80ff48 100644 --- a/tests/StructVar/StructVar.log +++ b/tests/StructVar/StructVar.log @@ -22,7 +22,7 @@ array_net 2 array_typespec 7 array_var 7 -assign_stmt 1 +assignment 1 bit_select 6 bit_typespec 5 constant 83 @@ -61,7 +61,7 @@ unsupported_typespec 1 array_net 2 array_typespec 7 array_var 7 -assign_stmt 1 +assignment 1 bit_select 10 bit_typespec 5 constant 83 @@ -490,7 +490,7 @@ design: (work@test) |vpiParent: \_module_inst: work@prim_generic_ram_1 (work@prim_generic_ram_1), file:${SURELOG_DIR}/tests/StructVar/dut.sv, line:47:1, endln:66:10 |vpiForInitStmt: - \_assign_stmt: , line:59:7, endln:59:19 + \_assignment: , line:59:7, endln:59:19 |vpiParent: \_gen_for: |vpiRhs: @@ -502,7 +502,7 @@ design: (work@test) |vpiLhs: \_int_var: (work@prim_generic_ram_1.i), line:59:14, endln:59:15 |vpiParent: - \_assign_stmt: , line:59:7, endln:59:19 + \_assignment: , line:59:7, endln:59:19 |vpiTypespec: \_ref_typespec: (work@prim_generic_ram_1.i) |vpiParent: @@ -570,7 +570,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiParent: \_operation: , line:61:24, endln:61:40 - |vpiName:pmp_cfg[i].lock |vpiActual: \_bit_select: (pmp_cfg[i]), line:61:25, endln:61:32 |vpiParent: @@ -589,6 +588,7 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiName:lock |vpiFullName:work@prim_generic_ram_1.g_pmp_csrs.lock + |vpiName:pmp_cfg[i].lock |vpiOperand: \_operation: , line:62:4, endln:62:37 |vpiParent: @@ -598,7 +598,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiParent: \_operation: , line:62:4, endln:62:37 - |vpiName:pmp_cfg[i + 1].mode |vpiActual: \_bit_select: (pmp_cfg[i + 1]), line:62:4, endln:62:11 |vpiParent: @@ -630,6 +629,7 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiName:mode |vpiFullName:work@prim_generic_ram_1.g_pmp_csrs.mode + |vpiName:pmp_cfg[i + 1].mode |vpiOperand: \_ref_obj: (work@prim_generic_ram_1.g_pmp_csrs.PMP_MODE_TOR), line:62:25, endln:62:37 |vpiParent: @@ -1453,7 +1453,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiParent: \_operation: , line:61:24, endln:61:40 - |vpiName:pmp_cfg[i].lock |vpiActual: \_bit_select: (pmp_cfg[i]), line:61:25, endln:61:32 |vpiParent: @@ -1478,6 +1477,7 @@ design: (work@test) |vpiFullName:work@test.u3.g_pmp_csrs[0].lock |vpiActual: \_typespec_member: (lock), line:53:20, endln:53:24 + |vpiName:pmp_cfg[i].lock |vpiOperand: \_operation: , line:62:4, endln:62:37 |vpiParent: @@ -1487,7 +1487,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiParent: \_operation: , line:62:4, endln:62:37 - |vpiName:pmp_cfg[i + 1].mode |vpiActual: \_bit_select: (pmp_cfg[i + 1]), line:62:4, endln:62:11 |vpiParent: @@ -1525,6 +1524,7 @@ design: (work@test) |vpiFullName:work@test.u3.g_pmp_csrs[0].mode |vpiActual: \_typespec_member: (mode), line:54:20, endln:54:24 + |vpiName:pmp_cfg[i + 1].mode |vpiOperand: \_ref_obj: (work@test.u3.g_pmp_csrs[0].PMP_MODE_TOR), line:62:25, endln:62:37 |vpiParent: @@ -1583,7 +1583,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiParent: \_operation: , line:61:24, endln:61:40 - |vpiName:pmp_cfg[i].lock |vpiActual: \_bit_select: (pmp_cfg[i]), line:61:25, endln:61:32 |vpiParent: @@ -1608,6 +1607,7 @@ design: (work@test) |vpiFullName:work@test.u3.g_pmp_csrs[1].lock |vpiActual: \_typespec_member: (lock), line:53:20, endln:53:24 + |vpiName:pmp_cfg[i].lock |vpiOperand: \_operation: , line:62:4, endln:62:37 |vpiParent: @@ -1617,7 +1617,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiParent: \_operation: , line:62:4, endln:62:37 - |vpiName:pmp_cfg[i + 1].mode |vpiActual: \_bit_select: (pmp_cfg[i + 1]), line:62:4, endln:62:11 |vpiParent: @@ -1655,6 +1654,7 @@ design: (work@test) |vpiFullName:work@test.u3.g_pmp_csrs[1].mode |vpiActual: \_typespec_member: (mode), line:54:20, endln:54:24 + |vpiName:pmp_cfg[i + 1].mode |vpiOperand: \_ref_obj: (work@test.u3.g_pmp_csrs[1].PMP_MODE_TOR), line:62:25, endln:62:37 |vpiParent: @@ -1889,7 +1889,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiParent: \_operation: , line:62:4, endln:62:37 - |vpiName:pmp_cfg[i + 1].mode |vpiActual: \_bit_select: (pmp_cfg[i + 1]), line:62:4, endln:62:11 |vpiParent: @@ -1904,6 +1903,7 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiName:mode |vpiFullName:work@test.u3.g_pmp_csrs[0].mode + |vpiName:pmp_cfg[i + 1].mode \_operation: , line:62:4, endln:62:37 |vpiParent: \_operation: , line:61:24, endln:62:38 @@ -1929,7 +1929,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiParent: \_operation: , line:61:24, endln:61:40 - |vpiName:pmp_cfg[i].lock |vpiActual: \_bit_select: (pmp_cfg[i]), line:61:25, endln:61:32 |vpiParent: @@ -1948,6 +1947,7 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiName:lock |vpiFullName:work@test.u3.g_pmp_csrs[0].lock + |vpiName:pmp_cfg[i].lock |vpiOperand: \_operation: , line:62:4, endln:62:37 \_cont_assign: , line:61:10, endln:62:38 @@ -1976,7 +1976,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiParent: \_operation: , line:62:4, endln:62:37 - |vpiName:pmp_cfg[i + 1].mode |vpiActual: \_bit_select: (pmp_cfg[i + 1]), line:62:4, endln:62:11 |vpiParent: @@ -1991,6 +1990,7 @@ design: (work@test) \_hier_path: (pmp_cfg[i + 1].mode), line:62:4, endln:62:21 |vpiName:mode |vpiFullName:work@test.u3.g_pmp_csrs[1].mode + |vpiName:pmp_cfg[i + 1].mode \_operation: , line:62:4, endln:62:37 |vpiParent: \_operation: , line:61:24, endln:62:38 @@ -2016,7 +2016,6 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiParent: \_operation: , line:61:24, endln:61:40 - |vpiName:pmp_cfg[i].lock |vpiActual: \_bit_select: (pmp_cfg[i]), line:61:25, endln:61:32 |vpiParent: @@ -2035,6 +2034,7 @@ design: (work@test) \_hier_path: (pmp_cfg[i].lock), line:61:25, endln:61:40 |vpiName:lock |vpiFullName:work@test.u3.g_pmp_csrs[1].lock + |vpiName:pmp_cfg[i].lock |vpiOperand: \_operation: , line:62:4, endln:62:37 \_cont_assign: , line:61:10, endln:62:38 diff --git a/tests/TaskBind/TaskBind.log b/tests/TaskBind/TaskBind.log index 12d90ec019..6a3d96aebc 100644 --- a/tests/TaskBind/TaskBind.log +++ b/tests/TaskBind/TaskBind.log @@ -95,8 +95,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 1 constant 3 design 1 @@ -113,8 +112,7 @@ task_call 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 2 constant 3 design 1 @@ -152,7 +150,7 @@ design: (work@tb) |vpiVariables: \_integer_var: (work@tb.display.i), line:5:10, endln:5:11 |vpiParent: - \_assign_stmt: , line:5:10, endln:5:15 + \_assignment: , line:5:10, endln:5:15 |vpiTypespec: \_ref_typespec: (work@tb.display.i) |vpiParent: @@ -173,9 +171,11 @@ design: (work@tb) |vpiVariables: \_integer_var: (work@tb.display.i), line:5:10, endln:5:11 |vpiStmt: - \_assign_stmt: , line:5:10, endln:5:15 + \_assignment: , line:5:10, endln:5:15 |vpiParent: \_begin: (work@tb.display), line:6:2, endln:6:12 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:5:14, endln:5:15 |vpiDecompile:0 @@ -300,15 +300,17 @@ design: (work@tb) |vpiFullName:work@tb.display.i |vpiSigned:1 |vpiStmt: - \_assign_stmt: , line:5:10, endln:5:15 + \_assignment: , line:5:10, endln:5:15 |vpiParent: \_begin: (work@tb.display), line:6:2, endln:6:12 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:5:14, endln:5:15 |vpiLhs: \_integer_var: (work@tb.display.i), line:5:10, endln:5:11 |vpiParent: - \_assign_stmt: , line:5:10, endln:5:15 + \_assignment: , line:5:10, endln:5:15 |vpiTypespec: \_ref_typespec: (work@tb.display.i) |vpiParent: diff --git a/tests/TaskDeclNoOrder/TaskDeclNoOrder.log b/tests/TaskDeclNoOrder/TaskDeclNoOrder.log index 7ff39c36ab..fca05b8414 100644 --- a/tests/TaskDeclNoOrder/TaskDeclNoOrder.log +++ b/tests/TaskDeclNoOrder/TaskDeclNoOrder.log @@ -228,7 +228,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 5 +assignment 5 begin 1 constant 26 design 1 @@ -245,7 +245,7 @@ task 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 9 +assignment 9 begin 2 constant 30 design 1 @@ -283,7 +283,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.set_pll_fast_run.band_vco1_val), line:4:24, endln:4:37 |vpiParent: - \_assign_stmt: , line:4:24, endln:4:42 + \_assignment: , line:4:24, endln:4:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.band_vco1_val) |vpiParent: @@ -296,7 +296,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.set_pll_fast_run.fine_vco1_val), line:5:24, endln:5:37 |vpiParent: - \_assign_stmt: , line:5:24, endln:5:42 + \_assignment: , line:5:24, endln:5:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.fine_vco1_val) |vpiParent: @@ -309,7 +309,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.set_pll_fast_run.band_vco2_val), line:6:24, endln:6:37 |vpiParent: - \_assign_stmt: , line:6:24, endln:6:42 + \_assignment: , line:6:24, endln:6:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.band_vco2_val) |vpiParent: @@ -322,7 +322,7 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.set_pll_fast_run.fine_vco2_val), line:7:24, endln:7:37 |vpiParent: - \_assign_stmt: , line:7:24, endln:7:42 + \_assignment: , line:7:24, endln:7:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.fine_vco2_val) |vpiParent: @@ -444,9 +444,11 @@ design: (work@dut) |vpiVariables: \_logic_var: (work@dut.set_pll_fast_run.pll_core_ready), line:8:11, endln:8:25 |vpiStmt: - \_assign_stmt: , line:4:24, endln:4:42 + \_assignment: , line:4:24, endln:4:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:4:38, endln:4:42 |vpiDecompile:'h1A @@ -456,9 +458,11 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.band_vco1_val), line:4:24, endln:4:37 |vpiStmt: - \_assign_stmt: , line:5:24, endln:5:42 + \_assignment: , line:5:24, endln:5:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:5:38, endln:5:42 |vpiDecompile:'h04 @@ -468,9 +472,11 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.fine_vco1_val), line:5:24, endln:5:37 |vpiStmt: - \_assign_stmt: , line:6:24, endln:6:42 + \_assignment: , line:6:24, endln:6:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:6:38, endln:6:42 |vpiDecompile:'h04 @@ -480,9 +486,11 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.band_vco2_val), line:6:24, endln:6:37 |vpiStmt: - \_assign_stmt: , line:7:24, endln:7:42 + \_assignment: , line:7:24, endln:7:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:7:38, endln:7:42 |vpiDecompile:'h1C @@ -723,13 +731,15 @@ design: (work@dut) |vpiName:pll_core_ready |vpiFullName:work@dut.set_pll_fast_run.pll_core_ready |vpiStmt: - \_assign_stmt: , line:4:24, endln:4:42 + \_assignment: , line:4:24, endln:4:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:4:38, endln:4:42 |vpiParent: - \_assign_stmt: , line:4:24, endln:4:42 + \_assignment: , line:4:24, endln:4:42 |vpiDecompile:'h1A |vpiSize:-1 |HEX:1A @@ -737,7 +747,7 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.band_vco1_val), line:4:24, endln:4:37 |vpiParent: - \_assign_stmt: , line:4:24, endln:4:42 + \_assignment: , line:4:24, endln:4:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.band_vco1_val) |vpiParent: @@ -748,13 +758,15 @@ design: (work@dut) |vpiName:band_vco1_val |vpiFullName:work@dut.set_pll_fast_run.band_vco1_val |vpiStmt: - \_assign_stmt: , line:5:24, endln:5:42 + \_assignment: , line:5:24, endln:5:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:5:38, endln:5:42 |vpiParent: - \_assign_stmt: , line:5:24, endln:5:42 + \_assignment: , line:5:24, endln:5:42 |vpiDecompile:'h04 |vpiSize:-1 |HEX:04 @@ -762,7 +774,7 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.fine_vco1_val), line:5:24, endln:5:37 |vpiParent: - \_assign_stmt: , line:5:24, endln:5:42 + \_assignment: , line:5:24, endln:5:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.fine_vco1_val) |vpiParent: @@ -773,13 +785,15 @@ design: (work@dut) |vpiName:fine_vco1_val |vpiFullName:work@dut.set_pll_fast_run.fine_vco1_val |vpiStmt: - \_assign_stmt: , line:6:24, endln:6:42 + \_assignment: , line:6:24, endln:6:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:6:38, endln:6:42 |vpiParent: - \_assign_stmt: , line:6:24, endln:6:42 + \_assignment: , line:6:24, endln:6:42 |vpiDecompile:'h04 |vpiSize:-1 |HEX:04 @@ -787,7 +801,7 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.band_vco2_val), line:6:24, endln:6:37 |vpiParent: - \_assign_stmt: , line:6:24, endln:6:42 + \_assignment: , line:6:24, endln:6:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.band_vco2_val) |vpiParent: @@ -798,13 +812,15 @@ design: (work@dut) |vpiName:band_vco2_val |vpiFullName:work@dut.set_pll_fast_run.band_vco2_val |vpiStmt: - \_assign_stmt: , line:7:24, endln:7:42 + \_assignment: , line:7:24, endln:7:42 |vpiParent: \_begin: (work@dut.set_pll_fast_run), line:5:5, endln:5:43 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:7:38, endln:7:42 |vpiParent: - \_assign_stmt: , line:7:24, endln:7:42 + \_assignment: , line:7:24, endln:7:42 |vpiDecompile:'h1C |vpiSize:-1 |HEX:1C @@ -812,7 +828,7 @@ design: (work@dut) |vpiLhs: \_logic_var: (work@dut.set_pll_fast_run.fine_vco2_val), line:7:24, endln:7:37 |vpiParent: - \_assign_stmt: , line:7:24, endln:7:42 + \_assignment: , line:7:24, endln:7:42 |vpiTypespec: \_ref_typespec: (work@dut.set_pll_fast_run.fine_vco2_val) |vpiParent: diff --git a/tests/TaskDecls/TaskDecls.log b/tests/TaskDecls/TaskDecls.log index 42f9bb20d6..90f63a6929 100644 --- a/tests/TaskDecls/TaskDecls.log +++ b/tests/TaskDecls/TaskDecls.log @@ -501,8 +501,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 4 -assignment 3 +assignment 7 begin 4 class_defn 8 class_typespec 4 @@ -533,8 +532,7 @@ task 12 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 -assignment 6 +assignment 10 begin 8 class_defn 8 class_typespec 4 @@ -556,10 +554,10 @@ logic_var 1 module_inst 4 operation 5 package 4 -param_assign 4 -parameter 4 +param_assign 5 +parameter 5 range 3 -ref_obj 23 +ref_obj 24 ref_typespec 45 task 24 === UHDM Object Stats End === @@ -1439,6 +1437,8 @@ design: (work@gen_errors) \_task: (work@gen_errors.A), line:20:4, endln:35:11 |vpiFullName:work@gen_errors.A |vpiStmt: + \_param_assign: , line:30:16, endln:30:30 + |vpiStmt: \_begin: (work@gen_errors.A), line:31:6, endln:33:9 |vpiParent: \_begin: (work@gen_errors.A), line:31:6, endln:33:9 @@ -1606,6 +1606,25 @@ design: (work@gen_errors) \_task: (work@gen_errors.A), line:20:4, endln:35:11 |vpiFullName:work@gen_errors.A |vpiStmt: + \_param_assign: , line:30:16, endln:30:30 + |vpiParent: + \_begin: (work@gen_errors.A), line:31:6, endln:33:9 + |vpiRhs: + \_ref_obj: (work@gen_errors.A.width_a), line:30:23, endln:30:30 + |vpiParent: + \_param_assign: , line:30:16, endln:30:30 + |vpiName:width_a + |vpiFullName:work@gen_errors.A.width_a + |vpiActual: + \_parameter: (work@gen_errors.width_a), line:19:12, endln:19:19 + |vpiLhs: + \_parameter: (work@gen_errors.A.llen), line:30:16, endln:30:30 + |vpiParent: + \_param_assign: , line:30:16, endln:30:30 + |vpiLocalParam:1 + |vpiName:llen + |vpiFullName:work@gen_errors.A.llen + |vpiStmt: \_begin: (work@gen_errors.A), line:31:6, endln:33:9 |vpiParent: \_begin: (work@gen_errors.A), line:31:6, endln:33:9 diff --git a/tests/ThisHier/ThisHier.log b/tests/ThisHier/ThisHier.log index efac5efd82..44669a57f9 100644 --- a/tests/ThisHier/ThisHier.log +++ b/tests/ThisHier/ThisHier.log @@ -238,7 +238,6 @@ design: (unnamed) \_hier_path: (super.m_successors), line:27:32, endln:27:50 |vpiParent: \_assignment: , line:27:5, endln:27:50 - |vpiName:super.m_successors |vpiActual: \_ref_obj: (super), line:27:38, endln:27:50 |vpiParent: @@ -249,11 +248,11 @@ design: (unnamed) |vpiParent: \_hier_path: (super.m_successors), line:27:32, endln:27:50 |vpiName:m_successors + |vpiName:super.m_successors |vpiLhs: \_hier_path: (this.m_predecessors.size), line:27:5, endln:27:9 |vpiParent: \_assignment: , line:27:5, endln:27:50 - |vpiName:this.m_predecessors.size |vpiActual: \_ref_obj: (this), line:27:10, endln:27:24 |vpiParent: @@ -271,6 +270,7 @@ design: (unnamed) \_hier_path: (this.m_predecessors.size), line:27:5, endln:27:9 |vpiName:size |vpiFullName:uvm::uvm_phase::add::size + |vpiName:this.m_predecessors.size |vpiInstance: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/ThisHier/dut.sv, line:1:1, endln:33:11 |uhdmtopPackages: @@ -350,7 +350,6 @@ design: (unnamed) \_hier_path: (this.threshold), line:13:5, endln:13:9 |vpiParent: \_assignment: , line:13:5, endln:13:31 - |vpiName:this.threshold |vpiActual: \_ref_obj: (this), line:13:10, endln:13:19 |vpiParent: @@ -366,6 +365,7 @@ design: (unnamed) |vpiFullName:uvm::uvm_barrier::new::threshold |vpiActual: \_int_var: (uvm::uvm_barrier::threshold), line:10:20, endln:10:29 + |vpiName:this.threshold |vpiClassDefn: \_class_defn: (uvm::uvm_object), file:${SURELOG_DIR}/tests/ThisHier/dut.sv, line:3:1, endln:5:9 |vpiParent: @@ -477,7 +477,6 @@ design: (unnamed) \_hier_path: (super.m_successors), line:27:32, endln:27:50 |vpiParent: \_assignment: , line:27:5, endln:27:50 - |vpiName:super.m_successors |vpiActual: \_ref_obj: (super), line:27:38, endln:27:50 |vpiParent: @@ -492,11 +491,11 @@ design: (unnamed) |vpiName:m_successors |vpiActual: \_array_var: (uvm::uvm_object::m_successors), line:4:16, endln:4:28 + |vpiName:super.m_successors |vpiLhs: \_hier_path: (this.m_predecessors.size), line:27:5, endln:27:9 |vpiParent: \_assignment: , line:27:5, endln:27:50 - |vpiName:this.m_predecessors.size |vpiActual: \_ref_obj: (this), line:27:10, endln:27:24 |vpiParent: @@ -520,6 +519,7 @@ design: (unnamed) |vpiFullName:uvm::uvm_phase::add::size |vpiActual: \_func_call: (size) + |vpiName:this.m_predecessors.size |vpiInstance: \_package: uvm (uvm::), file:${SURELOG_DIR}/tests/ThisHier/dut.sv, line:1:1, endln:33:11 |vpiClassDefn: @@ -549,7 +549,6 @@ design: (unnamed) \_hier_path: (this.threshold), line:13:5, endln:13:9 |vpiParent: \_assignment: , line:13:5, endln:13:31 - |vpiName:this.threshold |vpiActual: \_ref_obj: (this), line:13:10, endln:13:19 |vpiParent: @@ -561,6 +560,7 @@ design: (unnamed) \_hier_path: (this.threshold), line:13:5, endln:13:9 |vpiName:threshold |vpiFullName:uvm::uvm_barrier::new::threshold + |vpiName:this.threshold \_class_typespec: |vpiClassDefn: \_class_defn: (uvm::uvm_barrier), file:${SURELOG_DIR}/tests/ThisHier/dut.sv, line:8:1, endln:17:9 diff --git a/tests/TypeDefScope/TypeDefScope.log b/tests/TypeDefScope/TypeDefScope.log index 6da3008725..8d0ae3fabc 100644 --- a/tests/TypeDefScope/TypeDefScope.log +++ b/tests/TypeDefScope/TypeDefScope.log @@ -371,7 +371,7 @@ there are 1 more instances of this message. [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 begin 1 class_defn 8 class_typespec 4 @@ -400,7 +400,7 @@ unsupported_typespec 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 +assignment 2 begin 2 class_defn 8 class_typespec 4 diff --git a/tests/TypeParamOverride/TypeParamOverride.log b/tests/TypeParamOverride/TypeParamOverride.log index 1e89d1dd22..b5466b6e0f 100644 --- a/tests/TypeParamOverride/TypeParamOverride.log +++ b/tests/TypeParamOverride/TypeParamOverride.log @@ -352,7 +352,6 @@ design: (work@ariane_testharness) \_hier_path: (err_resp.w_ready), line:17:5, endln:17:21 |vpiParent: \_assignment: , line:17:5, endln:17:29 - |vpiName:err_resp.w_ready |vpiActual: \_ref_obj: (err_resp), line:17:14, endln:17:21 |vpiParent: @@ -363,6 +362,7 @@ design: (work@ariane_testharness) |vpiParent: \_hier_path: (err_resp.w_ready), line:17:5, endln:17:21 |vpiName:w_ready + |vpiName:err_resp.w_ready |vpiAlwaysType:2 |uhdmtopModules: \_module_inst: work@ariane_testharness (work@ariane_testharness), file:${SURELOG_DIR}/tests/TypeParamOverride/dut.sv, line:23:1, endln:31:10 @@ -430,7 +430,6 @@ design: (work@ariane_testharness) \_hier_path: (err_resp.w_ready), line:17:5, endln:17:21 |vpiParent: \_assignment: , line:17:5, endln:17:29 - |vpiName:err_resp.w_ready |vpiActual: \_ref_obj: (err_resp), line:17:14, endln:17:21 |vpiParent: @@ -445,6 +444,7 @@ design: (work@ariane_testharness) |vpiName:w_ready |vpiActual: \_typespec_member: (w_ready), line:4:19, endln:4:26 + |vpiName:err_resp.w_ready |vpiAlwaysType:2 \_weaklyReferenced: \_logic_typespec: , line:4:5, endln:4:10 diff --git a/tests/TypedefUnpacked/TypedefUnpacked.log b/tests/TypedefUnpacked/TypedefUnpacked.log index 60e3188f54..5185e91452 100644 --- a/tests/TypedefUnpacked/TypedefUnpacked.log +++ b/tests/TypedefUnpacked/TypedefUnpacked.log @@ -206,7 +206,6 @@ design: (work@dut) \_hier_path: (c[1].x), line:10:11, endln:10:12 |vpiParent: \_cont_assign: , line:10:11, endln:10:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:10:11, endln:10:12 |vpiParent: @@ -225,6 +224,7 @@ design: (work@dut) \_hier_path: (c[1].x), line:10:11, endln:10:12 |vpiName:x |vpiFullName:c[1].x + |vpiName:c[1].x |vpiContAssign: \_cont_assign: , line:11:11, endln:11:21 |vpiParent: @@ -233,7 +233,6 @@ design: (work@dut) \_hier_path: (c[1].x), line:11:15, endln:11:21 |vpiParent: \_cont_assign: , line:11:11, endln:11:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:11:15, endln:11:16 |vpiParent: @@ -252,6 +251,7 @@ design: (work@dut) \_hier_path: (c[1].x), line:11:15, endln:11:21 |vpiName:x |vpiFullName:work@dut.x + |vpiName:c[1].x |vpiLhs: \_ref_obj: (work@dut.o), line:11:11, endln:11:12 |vpiParent: @@ -324,7 +324,6 @@ design: (work@dut) \_hier_path: (c[1].x), line:10:11, endln:10:12 |vpiParent: \_cont_assign: , line:10:11, endln:10:21 - |vpiName:c[1].x |vpiActual: \_bit_select: (c[1]), line:10:11, endln:10:12 |vpiParent: @@ -345,6 +344,7 @@ design: (work@dut) \_hier_path: (c[1].x), line:10:11, endln:10:12 |vpiName:x |vpiFullName:c[1].x + |vpiName:c[1].x |vpiContAssign: \_cont_assign: , line:11:11, endln:11:21 \_weaklyReferenced: diff --git a/tests/Udp/Udp.log b/tests/Udp/Udp.log index e6c0056626..f14c943a8d 100644 --- a/tests/Udp/Udp.log +++ b/tests/Udp/Udp.log @@ -930,8 +930,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 10 +assignment 11 attribute 4 begin 1 class_defn 8 @@ -965,8 +964,7 @@ udp_defn 4 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 -assignment 20 +assignment 21 attribute 4 begin 2 class_defn 8 @@ -1785,13 +1783,13 @@ design: (work@udp_body_tb) |vpiParent: \_udp_defn: work@udp_sequential_initial, line:60:1, endln:82:13 |vpiStmt: - \_assign_stmt: , line:66:1, endln:67:9 + \_assignment: , line:66:1, endln:67:9 |vpiParent: \_initial: , line:66:1, endln:67:9 |vpiRhs: \_constant: , line:67:7, endln:67:8 |vpiParent: - \_assign_stmt: , line:66:1, endln:67:9 + \_assignment: , line:66:1, endln:67:9 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1799,7 +1797,7 @@ design: (work@udp_body_tb) |vpiLhs: \_ref_obj: (work@udp_sequential_initial.q), line:67:3, endln:67:4 |vpiParent: - \_assign_stmt: , line:66:1, endln:67:9 + \_assignment: , line:66:1, endln:67:9 |vpiName:q |vpiFullName:work@udp_sequential_initial.q |uhdmallModules: diff --git a/tests/UhdmCoverage/UhdmCoverage.log b/tests/UhdmCoverage/UhdmCoverage.log index 36087eb718..f26ed1e1f2 100644 --- a/tests/UhdmCoverage/UhdmCoverage.log +++ b/tests/UhdmCoverage/UhdmCoverage.log @@ -1681,7 +1681,6 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (decode_tv_r.amo_op), line:129:37, endln:129:55 |vpiParent: \_operation: , line:129:37, endln:131:51 - |vpiName:decode_tv_r.amo_op |vpiActual: \_ref_obj: (decode_tv_r), line:129:37, endln:129:48 |vpiParent: @@ -1693,6 +1692,7 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (decode_tv_r.amo_op), line:129:37, endln:129:55 |vpiName:amo_op |vpiFullName:work@divSqrtRecFN_small.atomic.amo_op + |vpiName:decode_tv_r.amo_op |vpiOperand: \_indexed_part_select: atomic_result (work@divSqrtRecFN_small.atomic.atomic_result), line:130:34, endln:130:51 |vpiParent: @@ -1921,7 +1921,6 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (resp_concentrated_link_lo.data), line:102:51, endln:102:81 |vpiParent: \_operation: , line:102:33, endln:105:38 - |vpiName:resp_concentrated_link_lo.data |vpiActual: \_ref_obj: (resp_concentrated_link_lo), line:102:51, endln:102:76 |vpiParent: @@ -1933,6 +1932,7 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (resp_concentrated_link_lo.data), line:102:51, endln:102:81 |vpiName:data |vpiFullName:work@e.data + |vpiName:resp_concentrated_link_lo.data |vpiTypespec: \_ref_typespec: (work@e) |vpiParent: @@ -1948,7 +1948,6 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (resp_concentrated_link_lo.v), line:103:57, endln:103:84 |vpiParent: \_operation: , line:102:33, endln:105:38 - |vpiName:resp_concentrated_link_lo.v |vpiActual: \_ref_obj: (resp_concentrated_link_lo), line:103:57, endln:103:82 |vpiParent: @@ -1960,6 +1959,7 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (resp_concentrated_link_lo.v), line:103:57, endln:103:84 |vpiName:v |vpiFullName:work@e.v + |vpiName:resp_concentrated_link_lo.v |vpiTypespec: \_ref_typespec: (work@e) |vpiParent: @@ -1975,7 +1975,6 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (cce_lce_resp_link_lo.ready_and_rev), line:104:53, endln:104:87 |vpiParent: \_operation: , line:102:33, endln:105:38 - |vpiName:cce_lce_resp_link_lo.ready_and_rev |vpiActual: \_ref_obj: (cce_lce_resp_link_lo), line:104:53, endln:104:73 |vpiParent: @@ -1987,6 +1986,7 @@ design: (work@divSqrtRecFNToRaw_small) \_hier_path: (cce_lce_resp_link_lo.ready_and_rev), line:104:53, endln:104:87 |vpiName:ready_and_rev |vpiFullName:work@e.ready_and_rev + |vpiName:cce_lce_resp_link_lo.ready_and_rev |vpiTypespec: \_ref_typespec: (work@e) |vpiParent: diff --git a/tests/UnaryPlus/UnaryPlus.log b/tests/UnaryPlus/UnaryPlus.log index a2d27864d9..89733ffa34 100644 --- a/tests/UnaryPlus/UnaryPlus.log +++ b/tests/UnaryPlus/UnaryPlus.log @@ -59,7 +59,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 constant 30 design 1 gen_for 1 @@ -79,7 +79,7 @@ unsupported_typespec 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 constant 30 design 1 gen_for 1 @@ -123,7 +123,7 @@ design: (work@alert_handler_reg_wrap) |vpiParent: \_module_inst: work@alert_handler_reg_wrap (work@alert_handler_reg_wrap), file:${SURELOG_DIR}/tests/UnaryPlus/dut.sv, line:1:1, endln:4:10 |vpiForInitStmt: - \_assign_stmt: , line:2:7, endln:2:24 + \_assignment: , line:2:7, endln:2:24 |vpiParent: \_gen_for: |vpiRhs: @@ -135,7 +135,7 @@ design: (work@alert_handler_reg_wrap) |vpiLhs: \_int_var: (work@alert_handler_reg_wrap.i_word), line:2:14, endln:2:20 |vpiParent: - \_assign_stmt: , line:2:7, endln:2:24 + \_assignment: , line:2:7, endln:2:24 |vpiTypespec: \_ref_typespec: (work@alert_handler_reg_wrap.i_word) |vpiParent: diff --git a/tests/UnionCast/UnionCast.log b/tests/UnionCast/UnionCast.log index 1a00cc104d..d5ab3500bf 100644 --- a/tests/UnionCast/UnionCast.log +++ b/tests/UnionCast/UnionCast.log @@ -5197,7 +5197,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rd), line:161:14, endln:161:22 |vpiParent: \_cont_assign: , line:161:8, endln:161:22 - |vpiName:dec.r.rd |vpiActual: \_ref_obj: (dec), line:161:14, endln:161:17 |vpiParent: @@ -5214,6 +5213,7 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rd), line:161:14, endln:161:22 |vpiName:rd |vpiFullName:work@r5p_lsu.rd + |vpiName:dec.r.rd |vpiLhs: \_ref_obj: (work@r5p_lsu.rd), line:161:8, endln:161:10 |vpiParent: @@ -5230,7 +5230,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rs1), line:162:14, endln:162:23 |vpiParent: \_cont_assign: , line:162:8, endln:162:23 - |vpiName:dec.r.rs1 |vpiActual: \_ref_obj: (dec), line:162:14, endln:162:17 |vpiParent: @@ -5247,6 +5246,7 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rs1), line:162:14, endln:162:23 |vpiName:rs1 |vpiFullName:work@r5p_lsu.rs1 + |vpiName:dec.r.rs1 |vpiLhs: \_ref_obj: (work@r5p_lsu.rs1), line:162:8, endln:162:11 |vpiParent: @@ -5263,7 +5263,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rs2), line:163:14, endln:163:23 |vpiParent: \_cont_assign: , line:163:8, endln:163:23 - |vpiName:dec.r.rs2 |vpiActual: \_ref_obj: (dec), line:163:14, endln:163:17 |vpiParent: @@ -5280,6 +5279,7 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rs2), line:163:14, endln:163:23 |vpiName:rs2 |vpiFullName:work@r5p_lsu.rs2 + |vpiName:dec.r.rs2 |vpiLhs: \_ref_obj: (work@r5p_lsu.rs2), line:163:8, endln:163:11 |vpiParent: @@ -5296,7 +5296,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.i.imm_11_0), line:164:14, endln:164:28 |vpiParent: \_cont_assign: , line:164:8, endln:164:28 - |vpiName:dec.i.imm_11_0 |vpiActual: \_ref_obj: (dec), line:164:14, endln:164:17 |vpiParent: @@ -5313,6 +5312,7 @@ design: (work@r5p_lsu) \_hier_path: (dec.i.imm_11_0), line:164:14, endln:164:28 |vpiName:imm_11_0 |vpiFullName:work@r5p_lsu.imm_11_0 + |vpiName:dec.i.imm_11_0 |vpiLhs: \_ref_obj: (work@r5p_lsu.imm), line:164:8, endln:164:11 |vpiParent: @@ -5680,7 +5680,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rd), line:161:14, endln:161:22 |vpiParent: \_cont_assign: , line:161:8, endln:161:22 - |vpiName:dec.r.rd |vpiActual: \_ref_obj: (dec), line:161:14, endln:161:17 |vpiParent: @@ -5703,6 +5702,7 @@ design: (work@r5p_lsu) |vpiFullName:work@r5p_lsu.rd |vpiActual: \_logic_net: (work@r5p_lsu.rd), line:151:25, endln:151:27 + |vpiName:dec.r.rd |vpiLhs: \_ref_obj: (work@r5p_lsu.rd), line:161:8, endln:161:10 |vpiParent: @@ -5719,7 +5719,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rs1), line:162:14, endln:162:23 |vpiParent: \_cont_assign: , line:162:8, endln:162:23 - |vpiName:dec.r.rs1 |vpiActual: \_ref_obj: (dec), line:162:14, endln:162:17 |vpiParent: @@ -5742,6 +5741,7 @@ design: (work@r5p_lsu) |vpiFullName:work@r5p_lsu.rs1 |vpiActual: \_logic_net: (work@r5p_lsu.rs1), line:152:25, endln:152:28 + |vpiName:dec.r.rs1 |vpiLhs: \_ref_obj: (work@r5p_lsu.rs1), line:162:8, endln:162:11 |vpiParent: @@ -5758,7 +5758,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.r.rs2), line:163:14, endln:163:23 |vpiParent: \_cont_assign: , line:163:8, endln:163:23 - |vpiName:dec.r.rs2 |vpiActual: \_ref_obj: (dec), line:163:14, endln:163:17 |vpiParent: @@ -5781,6 +5780,7 @@ design: (work@r5p_lsu) |vpiFullName:work@r5p_lsu.rs2 |vpiActual: \_logic_net: (work@r5p_lsu.rs2), line:153:25, endln:153:28 + |vpiName:dec.r.rs2 |vpiLhs: \_ref_obj: (work@r5p_lsu.rs2), line:163:8, endln:163:11 |vpiParent: @@ -5797,7 +5797,6 @@ design: (work@r5p_lsu) \_hier_path: (dec.i.imm_11_0), line:164:14, endln:164:28 |vpiParent: \_cont_assign: , line:164:8, endln:164:28 - |vpiName:dec.i.imm_11_0 |vpiActual: \_ref_obj: (dec), line:164:14, endln:164:17 |vpiParent: @@ -5820,6 +5819,7 @@ design: (work@r5p_lsu) |vpiFullName:work@r5p_lsu.imm_11_0 |vpiActual: \_typespec_member: (imm_11_0), line:108:38, endln:108:46 + |vpiName:dec.i.imm_11_0 |vpiLhs: \_ref_obj: (work@r5p_lsu.imm), line:164:8, endln:164:11 |vpiParent: diff --git a/tests/UnitElabBlock/UnitElabBlock.log b/tests/UnitElabBlock/UnitElabBlock.log index 5e5d850fa0..50485a2816 100644 --- a/tests/UnitElabBlock/UnitElabBlock.log +++ b/tests/UnitElabBlock/UnitElabBlock.log @@ -511,8 +511,7 @@ Instance tree: [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 1 -assign_stmt 2 -assignment 2 +assignment 4 begin 1 class_defn 8 class_typespec 4 @@ -547,8 +546,7 @@ task 9 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === always 3 -assign_stmt 3 -assignment 5 +assignment 8 begin 2 class_defn 8 class_typespec 4 diff --git a/tests/UnitForLoop/UnitForLoop.log b/tests/UnitForLoop/UnitForLoop.log index 42b68935eb..9eaf0d108b 100644 --- a/tests/UnitForLoop/UnitForLoop.log +++ b/tests/UnitForLoop/UnitForLoop.log @@ -318,7 +318,7 @@ Instance tree: ${SURELOG_DIR}/tests/UnitForLoop/top.v:1:1: type definition. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 begin 5 class_defn 1 constant 4 @@ -409,13 +409,13 @@ design: (unnamed) \_begin: (work@top::f1), line:12:3, endln:15:7 |vpiFullName:work@top::f1 |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:21 + \_assignment: , line:8:10, endln:8:21 |vpiParent: \_for_stmt: (work@top::f1), line:8:4, endln:8:7 |vpiRhs: \_constant: , line:8:16, endln:8:17 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:21 + \_assignment: , line:8:10, endln:8:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -423,7 +423,7 @@ design: (unnamed) |vpiLhs: \_int_var: (work@top::f1::j), line:8:14, endln:8:15 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:21 + \_assignment: , line:8:10, endln:8:21 |vpiTypespec: \_ref_typespec: (work@top::f1::j) |vpiParent: @@ -522,13 +522,13 @@ design: (unnamed) \_begin: (work@top::f1), line:12:3, endln:15:7 |vpiFullName:work@top::f1 |vpiForInitStmt: - \_assign_stmt: , line:12:9, endln:12:22 + \_assignment: , line:12:9, endln:12:22 |vpiParent: \_for_stmt: (work@top::f1), line:12:3, endln:12:6 |vpiRhs: \_constant: , line:12:15, endln:12:16 |vpiParent: - \_assign_stmt: , line:12:9, endln:12:22 + \_assignment: , line:12:9, endln:12:22 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -536,7 +536,7 @@ design: (unnamed) |vpiLhs: \_int_var: (work@top::f1::j), line:12:13, endln:12:14 |vpiParent: - \_assign_stmt: , line:12:9, endln:12:22 + \_assignment: , line:12:9, endln:12:22 |vpiTypespec: \_ref_typespec: (work@top::f1::j) |vpiParent: diff --git a/tests/UnitForeach/UnitForeach.log b/tests/UnitForeach/UnitForeach.log index 9c68901577..dbe7704449 100644 --- a/tests/UnitForeach/UnitForeach.log +++ b/tests/UnitForeach/UnitForeach.log @@ -723,7 +723,7 @@ Instance tree: === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 4 array_var 4 -assign_stmt 2 +assignment 2 begin 7 bit_select 4 class_defn 10 @@ -836,7 +836,6 @@ design: (unnamed) \_hier_path: (arb_sequence_q.size), line:7:53, endln:7:74 |vpiParent: \_method_func_call: (print_array_header), line:7:13, endln:7:31 - |vpiName:arb_sequence_q.size |vpiActual: \_ref_obj: (arb_sequence_q), line:7:53, endln:7:67 |vpiParent: @@ -847,6 +846,7 @@ design: (unnamed) |vpiParent: \_hier_path: (arb_sequence_q.size), line:7:53, endln:7:74 |vpiName:size + |vpiName:arb_sequence_q.size |vpiName:print_array_header |vpiPrefix: \_ref_obj: (uvm_pkg::uvm_sequencer_base::do_print::printer), line:7:5, endln:7:12 @@ -924,7 +924,6 @@ design: (unnamed) \_hier_path: (arb_sequence_q[i].request.name), line:10:34, endln:10:66 |vpiParent: \_sys_func_call: ($sformatf), line:10:10, endln:10:97 - |vpiName:arb_sequence_q[i].request.name |vpiActual: \_bit_select: (arb_sequence_q[i]), line:10:34, endln:10:48 |vpiParent: @@ -947,11 +946,11 @@ design: (unnamed) |vpiParent: \_hier_path: (arb_sequence_q[i].request.name), line:10:34, endln:10:66 |vpiName:name + |vpiName:arb_sequence_q[i].request.name |vpiArgument: \_hier_path: (arb_sequence_q[i].sequence_id), line:10:67, endln:10:96 |vpiParent: \_sys_func_call: ($sformatf), line:10:10, endln:10:97 - |vpiName:arb_sequence_q[i].sequence_id |vpiActual: \_bit_select: (arb_sequence_q[i]), line:10:67, endln:10:81 |vpiParent: @@ -970,6 +969,7 @@ design: (unnamed) \_hier_path: (arb_sequence_q[i].sequence_id), line:10:67, endln:10:96 |vpiName:sequence_id |vpiFullName:uvm_pkg::uvm_sequencer_base::do_print::sequence_id + |vpiName:arb_sequence_q[i].sequence_id |vpiName:$sformatf |vpiArgument: \_constant: , line:10:99, endln:10:102 @@ -1094,7 +1094,6 @@ design: (unnamed) \_hier_path: (arb_sequence_q.size), line:7:53, endln:7:74 |vpiParent: \_method_func_call: (print_array_header), line:7:13, endln:7:31 - |vpiName:arb_sequence_q.size |vpiActual: \_ref_obj: (arb_sequence_q), line:7:53, endln:7:67 |vpiParent: @@ -1105,6 +1104,7 @@ design: (unnamed) |vpiParent: \_hier_path: (arb_sequence_q.size), line:7:53, endln:7:74 |vpiName:size + |vpiName:arb_sequence_q.size |vpiName:print_array_header |vpiPrefix: \_ref_obj: (uvm_pkg::uvm_sequencer_base::do_print::printer), line:7:5, endln:7:12 @@ -1184,7 +1184,6 @@ design: (unnamed) \_hier_path: (arb_sequence_q[i].request.name), line:10:34, endln:10:66 |vpiParent: \_sys_func_call: ($sformatf), line:10:10, endln:10:97 - |vpiName:arb_sequence_q[i].request.name |vpiActual: \_bit_select: (arb_sequence_q[i]), line:10:34, endln:10:48 |vpiParent: @@ -1209,11 +1208,11 @@ design: (unnamed) |vpiParent: \_hier_path: (arb_sequence_q[i].request.name), line:10:34, endln:10:66 |vpiName:name + |vpiName:arb_sequence_q[i].request.name |vpiArgument: \_hier_path: (arb_sequence_q[i].sequence_id), line:10:67, endln:10:96 |vpiParent: \_sys_func_call: ($sformatf), line:10:10, endln:10:97 - |vpiName:arb_sequence_q[i].sequence_id |vpiActual: \_bit_select: (arb_sequence_q[i]), line:10:67, endln:10:81 |vpiParent: @@ -1234,6 +1233,7 @@ design: (unnamed) \_hier_path: (arb_sequence_q[i].sequence_id), line:10:67, endln:10:96 |vpiName:sequence_id |vpiFullName:uvm_pkg::uvm_sequencer_base::do_print::sequence_id + |vpiName:arb_sequence_q[i].sequence_id |vpiName:$sformatf |vpiArgument: \_constant: , line:10:99, endln:10:102 diff --git a/tests/UnitQueue/UnitQueue.log b/tests/UnitQueue/UnitQueue.log index 3913239d8e..410ed52eff 100644 --- a/tests/UnitQueue/UnitQueue.log +++ b/tests/UnitQueue/UnitQueue.log @@ -467,7 +467,7 @@ Instance tree: === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 2 +assignment 2 begin 1 class_defn 10 class_typespec 5 diff --git a/tests/UnitThisNew/UnitThisNew.log b/tests/UnitThisNew/UnitThisNew.log index 72e682baaa..d6be2ee233 100644 --- a/tests/UnitThisNew/UnitThisNew.log +++ b/tests/UnitThisNew/UnitThisNew.log @@ -565,8 +565,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 2 array_var 2 -assign_stmt 4 -assignment 6 +assignment 10 begin 12 bit_typespec 4 bit_var 4 @@ -604,8 +603,7 @@ unsupported_typespec 12 === UHDM Object Stats Begin (Elaborated Model) === array_typespec 2 array_var 6 -assign_stmt 4 -assignment 12 +assignment 16 begin 24 bit_typespec 4 bit_var 4 @@ -980,7 +978,6 @@ design: (unnamed) \_hier_path: (this.fields.get_lsb_pos_in_register), line:27:8, endln:27:52 |vpiParent: \_if_stmt: , line:27:4, endln:28:7 - |vpiName:this.fields.get_lsb_pos_in_register |vpiActual: \_ref_obj: (this), line:27:13, endln:27:19 |vpiParent: @@ -996,6 +993,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.fields.get_lsb_pos_in_register), line:27:8, endln:27:52 |vpiName:get_lsb_pos_in_register + |vpiName:this.fields.get_lsb_pos_in_register |vpiStmt: \_begin: (toto::uvm_reg::add_field), line:27:54, endln:28:7 |vpiParent: @@ -1035,7 +1033,6 @@ design: (unnamed) \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiParent: \_operation: , line:33:11, endln:33:37 - |vpiName:this.stream_handle |vpiActual: \_ref_obj: (this), line:33:16, endln:33:29 |vpiParent: @@ -1046,6 +1043,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiName:stream_handle + |vpiName:this.stream_handle |vpiOperand: \_constant: , line:33:33, endln:33:37 |vpiParent: @@ -1509,7 +1507,6 @@ design: (unnamed) \_hier_path: (this.fields.get_lsb_pos_in_register), line:27:8, endln:27:52 |vpiParent: \_if_stmt: , line:27:4, endln:28:7 - |vpiName:this.fields.get_lsb_pos_in_register |vpiActual: \_ref_obj: (this), line:27:13, endln:27:19 |vpiParent: @@ -1525,6 +1522,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.fields.get_lsb_pos_in_register), line:27:8, endln:27:52 |vpiName:get_lsb_pos_in_register + |vpiName:this.fields.get_lsb_pos_in_register |vpiStmt: \_begin: (toto::uvm_reg::add_field), line:27:54, endln:28:7 |vpiParent: @@ -1564,7 +1562,6 @@ design: (unnamed) \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiParent: \_operation: , line:33:11, endln:33:37 - |vpiName:this.stream_handle |vpiActual: \_ref_obj: (this), line:33:16, endln:33:29 |vpiParent: @@ -1575,6 +1572,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiName:stream_handle + |vpiName:this.stream_handle |vpiOperand: \_constant: , line:33:33, endln:33:37 |vpiParent: @@ -2341,7 +2339,6 @@ design: (unnamed) \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiParent: \_operation: , line:33:11, endln:33:37 - |vpiName:this.stream_handle |vpiActual: \_ref_obj: (this), line:33:16, endln:33:29 |vpiParent: @@ -2352,6 +2349,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiName:stream_handle + |vpiName:this.stream_handle |vpiOperand: \_constant: , line:33:33, endln:33:37 |vpiInstance: @@ -2407,15 +2405,15 @@ design: (unnamed) \_hier_path: (m_b_inst) |vpiParent: \_assignment: , line:18:6, endln:18:20 - |vpiName:m_b_inst |vpiActual: \_ref_obj: (toto::m_initialize::m_b_inst), line:18:6, endln:18:14 + |vpiName:m_b_inst \_hier_path: (m_pool) |vpiParent: \_assignment: , line:19:6, endln:19:22 - |vpiName:m_pool |vpiActual: \_ref_obj: (toto::m_initialize::m_pool), line:19:6, endln:19:12 + |vpiName:m_pool \_unsupported_typespec: (uvm_reg_field), line:25:34, endln:25:47 |vpiName:uvm_reg_field |vpiInstance: @@ -2727,7 +2725,6 @@ design: (unnamed) \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiParent: \_operation: , line:33:11, endln:33:37 - |vpiName:this.stream_handle |vpiActual: \_ref_obj: (this), line:33:16, endln:33:29 |vpiParent: @@ -2738,6 +2735,7 @@ design: (unnamed) |vpiParent: \_hier_path: (this.stream_handle), line:33:11, endln:33:29 |vpiName:stream_handle + |vpiName:this.stream_handle |vpiOperand: \_constant: , line:33:33, endln:33:37 |vpiInstance: @@ -2793,15 +2791,15 @@ design: (unnamed) \_hier_path: (m_b_inst) |vpiParent: \_assignment: , line:18:6, endln:18:20 - |vpiName:m_b_inst |vpiActual: \_ref_obj: (toto::m_initialize::m_b_inst), line:18:6, endln:18:14 + |vpiName:m_b_inst \_hier_path: (m_pool) |vpiParent: \_assignment: , line:19:6, endln:19:22 - |vpiName:m_pool |vpiActual: \_ref_obj: (toto::m_initialize::m_pool), line:19:6, endln:19:12 + |vpiName:m_pool \_unsupported_typespec: (uvm_reg_field), line:25:34, endln:25:47 |vpiName:uvm_reg_field |vpiInstance: diff --git a/tests/UnpackPort/UnpackPort.log b/tests/UnpackPort/UnpackPort.log index 0478ace129..56b39f0cb4 100644 --- a/tests/UnpackPort/UnpackPort.log +++ b/tests/UnpackPort/UnpackPort.log @@ -398,7 +398,7 @@ AST_DEBUG_END === UHDM Object Stats Begin (Non-Elaborated Model) === array_net 1 array_typespec 1 -assign_stmt 1 +assignment 1 bit_select 15 class_defn 8 class_typespec 4 @@ -439,7 +439,7 @@ unsupported_typespec 2 === UHDM Object Stats Begin (Elaborated Model) === array_net 1 array_typespec 1 -assign_stmt 1 +assignment 1 bit_select 22 class_defn 8 class_typespec 4 @@ -1037,7 +1037,7 @@ design: (work@dut) |vpiParent: \_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/UnpackPort/dut.sv, line:1:1, endln:11:10 |vpiForInitStmt: - \_assign_stmt: , line:8:8, endln:8:18 + \_assignment: , line:8:8, endln:8:18 |vpiParent: \_gen_for: |vpiRhs: @@ -1049,7 +1049,7 @@ design: (work@dut) |vpiLhs: \_int_var: (work@dut.i), line:8:15, endln:8:16 |vpiParent: - \_assign_stmt: , line:8:8, endln:8:18 + \_assignment: , line:8:8, endln:8:18 |vpiTypespec: \_ref_typespec: (work@dut.i) |vpiParent: diff --git a/tests/UnsizedFunc/UnsizedFunc.log b/tests/UnsizedFunc/UnsizedFunc.log index b18c13ea65..077d1d5262 100644 --- a/tests/UnsizedFunc/UnsizedFunc.log +++ b/tests/UnsizedFunc/UnsizedFunc.log @@ -194,8 +194,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 1 +assignment 2 begin 2 constant 12 design 1 @@ -220,8 +219,7 @@ return_stmt 1 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 2 +assignment 4 begin 4 constant 13 design 1 @@ -302,7 +300,7 @@ design: (work@top) |vpiVariables: \_logic_var: (work@prim_lfsr.get_1s.a), line:6:26, endln:6:27 |vpiParent: - \_assign_stmt: , line:6:26, endln:6:32 + \_assignment: , line:6:26, endln:6:32 |vpiTypespec: \_ref_typespec: (work@prim_lfsr.get_1s.a) |vpiParent: @@ -334,9 +332,11 @@ design: (work@top) |vpiVariables: \_logic_var: (work@prim_lfsr.get_1s.a), line:6:26, endln:6:27 |vpiStmt: - \_assign_stmt: , line:6:26, endln:6:32 + \_assignment: , line:6:26, endln:6:32 |vpiParent: \_begin: (work@prim_lfsr.get_1s), line:7:7, endln:7:16 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:6:30, endln:6:32 |vpiDecompile:'1 @@ -628,13 +628,15 @@ design: (work@top) |vpiName:a |vpiFullName:work@top.u_lfsr.get_1s.a |vpiStmt: - \_assign_stmt: , line:6:26, endln:6:32 + \_assignment: , line:6:26, endln:6:32 |vpiParent: \_begin: (work@top.u_lfsr.get_1s), line:7:7, endln:7:16 + |vpiOpType:82 + |vpiBlocking:1 |vpiRhs: \_constant: , line:6:30, endln:6:32 |vpiParent: - \_assign_stmt: , line:6:26, endln:6:32 + \_assignment: , line:6:26, endln:6:32 |vpiDecompile:1111111111111111 |vpiSize:16 |BIN:1111111111111111 @@ -642,7 +644,7 @@ design: (work@top) |vpiLhs: \_logic_var: (work@top.u_lfsr.get_1s.a), line:6:26, endln:6:27 |vpiParent: - \_assign_stmt: , line:6:26, endln:6:32 + \_assignment: , line:6:26, endln:6:32 |vpiTypespec: \_ref_typespec: (work@top.u_lfsr.get_1s.a) |vpiParent: diff --git a/tests/VarDecl/VarDecl.log b/tests/VarDecl/VarDecl.log index c5bb5c1325..2bef959d9f 100644 --- a/tests/VarDecl/VarDecl.log +++ b/tests/VarDecl/VarDecl.log @@ -95,7 +95,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assignment 2 begin 1 constant 2 design 1 @@ -114,7 +114,7 @@ ref_typespec 6 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 3 +assignment 3 begin 2 constant 2 design 1 @@ -171,13 +171,13 @@ design: (work@top) \_function: (work@top.theta), line:2:4, endln:6:23 |vpiFullName:work@top.theta |vpiForInitStmt: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiParent: \_for_stmt: (work@top.theta), line:3:7, endln:3:10 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiParent: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -185,7 +185,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.theta.x), line:3:16, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiTypespec: \_ref_typespec: (work@top.theta.x) |vpiParent: @@ -301,7 +301,7 @@ design: (work@top) \_function: (work@top.theta), line:2:4, endln:6:23 |vpiFullName:work@top.theta |vpiForInitStmt: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiParent: \_for_stmt: (work@top.theta), line:3:7, endln:3:10 |vpiRhs: @@ -309,7 +309,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.theta.x), line:3:16, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiTypespec: \_ref_typespec: (work@top.theta.x) |vpiParent: @@ -426,5 +426,5 @@ design: (work@top) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/VarDecl/dut.sv | ${SURELOG_DIR}/build/regression/VarDecl/roundtrip/dut_000.sv | 3 | 7 | +[roundtrip]: ${SURELOG_DIR}/tests/VarDecl/dut.sv | ${SURELOG_DIR}/build/regression/VarDecl/roundtrip/dut_000.sv | 4 | 7 | ============================== End RoundTrip Results ============================== diff --git a/tests/VarDecl2/VarDecl2.log b/tests/VarDecl2/VarDecl2.log index 4d098e7a88..0594e39d6a 100644 --- a/tests/VarDecl2/VarDecl2.log +++ b/tests/VarDecl2/VarDecl2.log @@ -115,7 +115,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 3 +assignment 3 begin 2 constant 4 design 1 @@ -133,7 +133,7 @@ return_stmt 2 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 4 +assignment 4 begin 4 constant 4 design 1 @@ -195,13 +195,13 @@ design: (work@top) \_begin: (work@top.theta), line:8:7, endln:8:16 |vpiFullName:work@top.theta |vpiForInitStmt: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiParent: \_for_stmt: (work@top.theta), line:3:7, endln:3:10 |vpiRhs: \_constant: , line:3:20, endln:3:21 |vpiParent: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -209,7 +209,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.theta.x), line:3:16, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiTypespec: \_ref_typespec: (work@top.theta.x) |vpiParent: @@ -378,7 +378,7 @@ design: (work@top) \_begin: (work@top.theta), line:8:7, endln:8:16 |vpiFullName:work@top.theta |vpiForInitStmt: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiParent: \_for_stmt: (work@top.theta), line:3:7, endln:3:10 |vpiRhs: @@ -386,7 +386,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.theta.x), line:3:16, endln:3:17 |vpiParent: - \_assign_stmt: , line:3:12, endln:3:21 + \_assignment: , line:3:12, endln:3:21 |vpiTypespec: \_ref_typespec: (work@top.theta.x) |vpiParent: @@ -521,5 +521,5 @@ design: (work@top) [ NOTE] : 5 ============================== Begin RoundTrip Results ============================== -[roundtrip]: ${SURELOG_DIR}/tests/VarDecl2/dut.sv | ${SURELOG_DIR}/build/regression/VarDecl2/roundtrip/dut_000.sv | 5 | 11 | +[roundtrip]: ${SURELOG_DIR}/tests/VarDecl2/dut.sv | ${SURELOG_DIR}/build/regression/VarDecl2/roundtrip/dut_000.sv | 6 | 11 | ============================== End RoundTrip Results ============================== diff --git a/tests/VarInFunc/VarInFunc.log b/tests/VarInFunc/VarInFunc.log index 677569b0d1..05b6d1cb2a 100644 --- a/tests/VarInFunc/VarInFunc.log +++ b/tests/VarInFunc/VarInFunc.log @@ -388,7 +388,8 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 2 +assign_stmt 1 +assignment 1 begin 1 class_defn 8 class_typespec 4 @@ -420,7 +421,8 @@ task 9 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 3 +assign_stmt 2 +assignment 1 begin 2 class_defn 8 class_typespec 4 diff --git a/tests/VarSelect/VarSelect.log b/tests/VarSelect/VarSelect.log index 56b08d73de..77fe24b5fd 100644 --- a/tests/VarSelect/VarSelect.log +++ b/tests/VarSelect/VarSelect.log @@ -436,8 +436,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 -assignment 2 +assignment 3 begin 2 bit_select 1 class_defn 8 @@ -469,8 +468,7 @@ var_select 3 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 2 -assignment 4 +assignment 6 begin 4 bit_select 2 class_defn 8 @@ -1026,13 +1024,13 @@ design: (work@top) \_begin: (work@top), line:7:10, endln:12:5 |vpiFullName:work@top |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:17 + \_assignment: , line:8:10, endln:8:17 |vpiParent: \_for_stmt: (work@top), line:8:5, endln:8:8 |vpiRhs: \_constant: , line:8:16, endln:8:17 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:17 + \_assignment: , line:8:10, endln:8:17 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1040,7 +1038,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:8:14, endln:8:15 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:17 + \_assignment: , line:8:10, endln:8:17 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -1219,7 +1217,7 @@ design: (work@top) \_begin: (work@top), line:7:10, endln:12:5 |vpiFullName:work@top |vpiForInitStmt: - \_assign_stmt: , line:8:10, endln:8:17 + \_assignment: , line:8:10, endln:8:17 |vpiParent: \_for_stmt: (work@top), line:8:5, endln:8:8 |vpiRhs: @@ -1227,7 +1225,7 @@ design: (work@top) |vpiLhs: \_int_var: (work@top.i), line:8:14, endln:8:15 |vpiParent: - \_assign_stmt: , line:8:10, endln:8:17 + \_assignment: , line:8:10, endln:8:17 |vpiTypespec: \_ref_typespec: (work@top.i) |vpiParent: @@ -1685,5 +1683,5 @@ design: (work@top) ============================== Begin RoundTrip Results ============================== [roundtrip]: ${SURELOG_DIR}/tests/VarSelect/builtin.sv | ${SURELOG_DIR}/build/regression/VarSelect/roundtrip/builtin_000.sv | 0 | 0 | -[roundtrip]: ${SURELOG_DIR}/tests/VarSelect/dut.sv | ${SURELOG_DIR}/build/regression/VarSelect/roundtrip/dut_000.sv | 2 | 14 | +[roundtrip]: ${SURELOG_DIR}/tests/VarSelect/dut.sv | ${SURELOG_DIR}/build/regression/VarSelect/roundtrip/dut_000.sv | 3 | 14 | ============================== End RoundTrip Results ============================== diff --git a/tests/VarSelectGenStmt/VarSelectGenStmt.log b/tests/VarSelectGenStmt/VarSelectGenStmt.log index 6ea9ab09b2..bcbafe2883 100644 --- a/tests/VarSelectGenStmt/VarSelectGenStmt.log +++ b/tests/VarSelectGenStmt/VarSelectGenStmt.log @@ -198,7 +198,7 @@ AST_DEBUG_END [NTE:EL0511] Nb leaf instances: 4. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -assign_stmt 1 +assignment 1 constant 142 design 1 gen_for 1 @@ -223,7 +223,7 @@ var_select 8 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -assign_stmt 1 +assignment 1 constant 142 design 1 gen_for 1 @@ -334,7 +334,7 @@ design: (work@aes_sub_bytes) |vpiParent: \_module_inst: work@aes_sub_bytes (work@aes_sub_bytes), file:${SURELOG_DIR}/tests/VarSelectGenStmt/dut.sv, line:8:1, endln:23:10 |vpiForInitStmt: - \_assign_stmt: , line:14:8, endln:14:20 + \_assignment: , line:14:8, endln:14:20 |vpiParent: \_gen_for: |vpiRhs: @@ -346,7 +346,7 @@ design: (work@aes_sub_bytes) |vpiLhs: \_int_var: (work@aes_sub_bytes.j), line:14:15, endln:14:16 |vpiParent: - \_assign_stmt: , line:14:8, endln:14:20 + \_assignment: , line:14:8, endln:14:20 |vpiTypespec: \_ref_typespec: (work@aes_sub_bytes.j) |vpiParent: diff --git a/third_party/UHDM b/third_party/UHDM index 366faed557..0098e460bb 160000 --- a/third_party/UHDM +++ b/third_party/UHDM @@ -1 +1 @@ -Subproject commit 366faed5577333c9ebd7909b95eef5988d9cf785 +Subproject commit 0098e460bb1c219653a2f0b2d7374de00567a6be diff --git a/third_party/tests/AVLMM/AVLMM.log b/third_party/tests/AVLMM/AVLMM.log index 3a3839b3cc..fc9bc97aa3 100644 --- a/third_party/tests/AVLMM/AVLMM.log +++ b/third_party/tests/AVLMM/AVLMM.log @@ -29,8 +29,7 @@ always 9 array_typespec 15 array_var 5 -assign_stmt 53 -assignment 67 +assignment 120 begin 85 bit_select 41 bit_typespec 7 diff --git a/third_party/tests/AmiqEth/AmiqEth.log b/third_party/tests/AmiqEth/AmiqEth.log index 87ee568b56..829dc282e9 100644 --- a/third_party/tests/AmiqEth/AmiqEth.log +++ b/third_party/tests/AmiqEth/AmiqEth.log @@ -811,8 +811,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/ovm-2.1.2/src/ovm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 3997 array_var 3751 -assign_stmt 8663 -assignment 26129 +assignment 34786 begin 27526 bit_select 8927 bit_typespec 92944 @@ -881,12 +880,12 @@ range 96114 real_typespec 71 real_var 11 ref_obj 171349 -ref_typespec 202281 +ref_typespec 202279 ref_var 6605 repeat 94 return_stmt 11549 -string_typespec 18695 -string_var 8647 +string_typespec 18693 +string_var 8645 struct_typespec 158 struct_var 143 sys_func_call 6106 @@ -24285,7 +24284,6 @@ while_stmt 463 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -24293,8 +24291,6 @@ while_stmt 463 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -29508,7 +29504,6 @@ while_stmt 463 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -29516,8 +29511,6 @@ while_stmt 463 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log index 309bd7c889..fdd5d01332 100644 --- a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log +++ b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log @@ -439,8 +439,7 @@ always 1 array_typespec 1492 array_var 1470 assert_stmt 32 -assign_stmt 5509 -assignment 15786 +assignment 21291 begin 16817 bit_select 5585 bit_typespec 14878 @@ -516,12 +515,12 @@ real_typespec 41 real_var 8 ref_module 5 ref_obj 102956 -ref_typespec 56924 +ref_typespec 56922 ref_var 4666 repeat 76 return_stmt 6983 -string_typespec 7332 -string_var 3292 +string_typespec 7330 +string_var 3290 struct_typespec 110 struct_var 107 sys_func_call 3088 @@ -14378,7 +14377,6 @@ while_stmt 271 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -14386,8 +14384,6 @@ while_stmt 271 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -17829,7 +17825,6 @@ while_stmt 271 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -17837,8 +17832,6 @@ while_stmt 271 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/ApbSlave/ApbSlave.log b/third_party/tests/ApbSlave/ApbSlave.log index fa0b6f887b..822141c6cf 100644 --- a/third_party/tests/ApbSlave/ApbSlave.log +++ b/third_party/tests/ApbSlave/ApbSlave.log @@ -37,8 +37,7 @@ always 1 array_typespec 7 array_var 7 -assign_stmt 36 -assignment 79 +assignment 115 begin 78 bit_select 2 bit_typespec 10 diff --git a/third_party/tests/AxiInterconnect/AxiInterconnect.log b/third_party/tests/AxiInterconnect/AxiInterconnect.log index 8805489ed3..c3eab2c9bd 100644 --- a/third_party/tests/AxiInterconnect/AxiInterconnect.log +++ b/third_party/tests/AxiInterconnect/AxiInterconnect.log @@ -91,8 +91,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 8 array_net 4 -assign_stmt 12 -assignment 269 +assignment 281 begin 97 bit_select 115 case_item 8 @@ -149,8 +148,7 @@ var_select 52 === UHDM Object Stats Begin (Elaborated Model) === always 16 array_net 4 -assign_stmt 15 -assignment 534 +assignment 549 begin 184 bit_select 232 case_item 16 @@ -4038,13 +4036,13 @@ design: (work@axi_interconnect_wrapper) \_begin: (work@axi_interconnect.calcBaseAddrs), line:200:5, endln:215:8 |vpiFullName:work@axi_interconnect.calcBaseAddrs |vpiForInitStmt: - \_assign_stmt: , line:203:14, endln:203:19 + \_assignment: , line:203:14, endln:203:19 |vpiParent: \_for_stmt: (work@axi_interconnect.calcBaseAddrs), line:203:9, endln:203:12 |vpiRhs: \_constant: , line:203:18, endln:203:19 |vpiParent: - \_assign_stmt: , line:203:14, endln:203:19 + \_assignment: , line:203:14, endln:203:19 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -4052,7 +4050,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.calcBaseAddrs.i), line:203:14, endln:203:15 |vpiParent: - \_assign_stmt: , line:203:14, endln:203:19 + \_assignment: , line:203:14, endln:203:19 |vpiName:i |vpiFullName:work@axi_interconnect.calcBaseAddrs.i |vpiForIncStmt: @@ -11221,13 +11219,13 @@ design: (work@axi_interconnect_wrapper) \_begin: (work@axi_interconnect), line:614:23, endln:650:12 |vpiFullName:work@axi_interconnect |vpiForInitStmt: - \_assign_stmt: , line:618:18, endln:618:23 + \_assignment: , line:618:18, endln:618:23 |vpiParent: \_for_stmt: (work@axi_interconnect), line:618:13, endln:618:16 |vpiRhs: \_constant: , line:618:22, endln:618:23 |vpiParent: - \_assign_stmt: , line:618:18, endln:618:23 + \_assignment: , line:618:18, endln:618:23 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -11235,7 +11233,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.i), line:618:18, endln:618:19 |vpiParent: - \_assign_stmt: , line:618:18, endln:618:23 + \_assignment: , line:618:18, endln:618:23 |vpiName:i |vpiFullName:work@axi_interconnect.i |vpiForIncStmt: @@ -11303,13 +11301,13 @@ design: (work@axi_interconnect_wrapper) \_begin: (work@axi_interconnect), line:618:49, endln:626:16 |vpiFullName:work@axi_interconnect |vpiForInitStmt: - \_assign_stmt: , line:619:22, endln:619:27 + \_assignment: , line:619:22, endln:619:27 |vpiParent: \_for_stmt: (work@axi_interconnect), line:619:17, endln:619:20 |vpiRhs: \_constant: , line:619:26, endln:619:27 |vpiParent: - \_assign_stmt: , line:619:22, endln:619:27 + \_assignment: , line:619:22, endln:619:27 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -11317,7 +11315,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.j), line:619:22, endln:619:23 |vpiParent: - \_assign_stmt: , line:619:22, endln:619:27 + \_assignment: , line:619:22, endln:619:27 |vpiName:j |vpiFullName:work@axi_interconnect.j |vpiForIncStmt: @@ -18152,7 +18150,7 @@ design: (work@axi_interconnect_wrapper) |vpiParent: \_module_inst: work@axi_interconnect (work@axi_interconnect), file:${SURELOG_DIR}/third_party/tests/AxiInterconnect/axi_interconnect.v, line:34:1, endln:989:10 |vpiForInitStmt: - \_assign_stmt: , line:229:10, endln:229:15 + \_assignment: , line:229:10, endln:229:15 |vpiParent: \_gen_for: |vpiRhs: @@ -18164,7 +18162,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.i), line:229:10, endln:229:11 |vpiParent: - \_assign_stmt: , line:229:10, endln:229:15 + \_assignment: , line:229:10, endln:229:15 |vpiTypespec: \_ref_typespec: (work@axi_interconnect.i) |vpiParent: @@ -18473,7 +18471,7 @@ design: (work@axi_interconnect_wrapper) |vpiParent: \_module_inst: work@axi_interconnect (work@axi_interconnect), file:${SURELOG_DIR}/third_party/tests/AxiInterconnect/axi_interconnect.v, line:34:1, endln:989:10 |vpiForInitStmt: - \_assign_stmt: , line:240:10, endln:240:15 + \_assignment: , line:240:10, endln:240:15 |vpiParent: \_gen_for: |vpiRhs: @@ -18485,7 +18483,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.i), line:240:10, endln:240:11 |vpiParent: - \_assign_stmt: , line:240:10, endln:240:15 + \_assignment: , line:240:10, endln:240:15 |vpiTypespec: \_ref_typespec: (work@axi_interconnect.i) |vpiParent: @@ -18612,7 +18610,7 @@ design: (work@axi_interconnect_wrapper) |vpiParent: \_module_inst: work@axi_interconnect (work@axi_interconnect), file:${SURELOG_DIR}/third_party/tests/AxiInterconnect/axi_interconnect.v, line:34:1, endln:989:10 |vpiForInitStmt: - \_assign_stmt: , line:252:10, endln:252:15 + \_assignment: , line:252:10, endln:252:15 |vpiParent: \_gen_for: |vpiRhs: @@ -18624,7 +18622,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.i), line:252:10, endln:252:11 |vpiParent: - \_assign_stmt: , line:252:10, endln:252:15 + \_assignment: , line:252:10, endln:252:15 |vpiTypespec: \_ref_typespec: (work@axi_interconnect.i) |vpiParent: @@ -18827,7 +18825,7 @@ design: (work@axi_interconnect_wrapper) |vpiParent: \_module_inst: work@axi_interconnect (work@axi_interconnect), file:${SURELOG_DIR}/third_party/tests/AxiInterconnect/axi_interconnect.v, line:34:1, endln:989:10 |vpiForInitStmt: - \_assign_stmt: , line:267:10, endln:267:15 + \_assignment: , line:267:10, endln:267:15 |vpiParent: \_gen_for: |vpiRhs: @@ -18839,7 +18837,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect.i), line:267:10, endln:267:11 |vpiParent: - \_assign_stmt: , line:267:10, endln:267:15 + \_assignment: , line:267:10, endln:267:15 |vpiTypespec: \_ref_typespec: (work@axi_interconnect.i) |vpiParent: @@ -64426,7 +64424,7 @@ design: (work@axi_interconnect_wrapper) \_begin: (work@axi_interconnect_wrapper.axi_interconnect.calcBaseAddrs), line:200:5, endln:215:8 |vpiFullName:work@axi_interconnect_wrapper.axi_interconnect.calcBaseAddrs |vpiForInitStmt: - \_assign_stmt: , line:203:14, endln:203:19 + \_assignment: , line:203:14, endln:203:19 |vpiParent: \_for_stmt: (work@axi_interconnect_wrapper.axi_interconnect.calcBaseAddrs), line:203:9, endln:203:12 |vpiRhs: @@ -64434,7 +64432,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect_wrapper.axi_interconnect.calcBaseAddrs.i), line:203:14, endln:203:15 |vpiParent: - \_assign_stmt: , line:203:14, endln:203:19 + \_assignment: , line:203:14, endln:203:19 |vpiName:i |vpiFullName:work@axi_interconnect_wrapper.axi_interconnect.calcBaseAddrs.i |vpiActual: @@ -75505,7 +75503,7 @@ design: (work@axi_interconnect_wrapper) \_begin: (work@axi_interconnect_wrapper.axi_interconnect), line:614:23, endln:650:12 |vpiFullName:work@axi_interconnect_wrapper.axi_interconnect |vpiForInitStmt: - \_assign_stmt: , line:618:18, endln:618:23 + \_assignment: , line:618:18, endln:618:23 |vpiParent: \_for_stmt: (work@axi_interconnect_wrapper.axi_interconnect), line:618:13, endln:618:16 |vpiRhs: @@ -75513,7 +75511,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect_wrapper.axi_interconnect.i), line:618:18, endln:618:19 |vpiParent: - \_assign_stmt: , line:618:18, endln:618:23 + \_assignment: , line:618:18, endln:618:23 |vpiName:i |vpiFullName:work@axi_interconnect_wrapper.axi_interconnect.i |vpiActual: @@ -75579,7 +75577,7 @@ design: (work@axi_interconnect_wrapper) \_begin: (work@axi_interconnect_wrapper.axi_interconnect), line:618:49, endln:626:16 |vpiFullName:work@axi_interconnect_wrapper.axi_interconnect |vpiForInitStmt: - \_assign_stmt: , line:619:22, endln:619:27 + \_assignment: , line:619:22, endln:619:27 |vpiParent: \_for_stmt: (work@axi_interconnect_wrapper.axi_interconnect), line:619:17, endln:619:20 |vpiRhs: @@ -75587,7 +75585,7 @@ design: (work@axi_interconnect_wrapper) |vpiLhs: \_ref_var: (work@axi_interconnect_wrapper.axi_interconnect.j), line:619:22, endln:619:23 |vpiParent: - \_assign_stmt: , line:619:22, endln:619:27 + \_assignment: , line:619:22, endln:619:27 |vpiName:j |vpiFullName:work@axi_interconnect_wrapper.axi_interconnect.j |vpiActual: diff --git a/third_party/tests/AzadiRTL/AzadiRTL.log b/third_party/tests/AzadiRTL/AzadiRTL.log index ac547c155b..23700df356 100644 --- a/third_party/tests/AzadiRTL/AzadiRTL.log +++ b/third_party/tests/AzadiRTL/AzadiRTL.log @@ -13814,8 +13814,7 @@ array_net 21 array_typespec 197 array_var 124 assert_stmt 31 -assign_stmt 465 -assignment 5224 +assignment 5689 begin 2961 bit_select 9058 bit_typespec 660 @@ -13896,8 +13895,7 @@ array_net 21 array_typespec 349 array_var 128 assert_stmt 110 -assign_stmt 727 -assignment 10772 +assignment 11499 begin 7885 bit_select 21981 bit_typespec 660 diff --git a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log index 3e90159093..9aaab95c3e 100644 --- a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log +++ b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log @@ -410,8 +410,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 142 array_var 126 -assign_stmt 1150 -assignment 2675 +assignment 3825 begin 2597 bit_select 844 bit_typespec 862 diff --git a/third_party/tests/BuildUVMPkg/BuildUVMPkg.log b/third_party/tests/BuildUVMPkg/BuildUVMPkg.log index 49c555df64..e28612acd1 100644 --- a/third_party/tests/BuildUVMPkg/BuildUVMPkg.log +++ b/third_party/tests/BuildUVMPkg/BuildUVMPkg.log @@ -344,8 +344,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 663 array_var 641 -assign_stmt 3545 -assignment 6285 +assignment 9830 begin 6766 bit_select 2126 bit_typespec 2188 @@ -406,12 +405,12 @@ range 1976 real_typespec 33 real_var 8 ref_obj 41125 -ref_typespec 19304 +ref_typespec 19302 ref_var 1788 repeat 26 return_stmt 3272 -string_typespec 3166 -string_var 1368 +string_typespec 3164 +string_var 1366 struct_typespec 14 struct_var 36 sys_func_call 1267 @@ -3918,15 +3917,12 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:33804:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:33892:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:33929:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:34210:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:34252:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:34506:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:34548:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:34577:13: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:35106:11: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:35129:12: Unsupported typespec, m_sync [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:35185:12: Unsupported typespec, m_successors -[LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:22452:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:25324:15: Unsupported typespec, m_object_names [LINT]: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:25324:30: Unsupported typespec, i [LINT]: \_ ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/pp_output/uvm_pkg.sv:25324:30: diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log index fe307ef78e..4378993f2f 100644 --- a/third_party/tests/CoresSweRV/CoresSweRV.log +++ b/third_party/tests/CoresSweRV/CoresSweRV.log @@ -2411,8 +2411,7 @@ array_expr 1 array_net 38 array_typespec 672 array_var 648 -assign_stmt 3658 -assignment 7737 +assignment 11395 begin 7196 bit_select 20124 bit_typespec 2219 @@ -2488,12 +2487,12 @@ real_typespec 33 real_var 8 ref_module 2139 ref_obj 136747 -ref_typespec 91110 +ref_typespec 91108 ref_var 1830 repeat 26 return_stmt 3379 -string_typespec 3206 -string_var 1405 +string_typespec 3204 +string_var 1403 struct_net 199 struct_typespec 52 struct_var 55 @@ -2518,8 +2517,7 @@ array_expr 1 array_net 38 array_typespec 675 array_var 5037 -assign_stmt 10248 -assignment 43769 +assignment 53892 begin 46172 bit_select 25897 bit_typespec 2220 @@ -2596,12 +2594,12 @@ real_typespec 33 real_var 10 ref_module 2139 ref_obj 383727 -ref_typespec 191633 +ref_typespec 191621 ref_var 8701 repeat 207 return_stmt 19618 -string_typespec 3206 -string_var 5171 +string_typespec 3204 +string_var 5169 struct_net 199 struct_typespec 66 struct_var 184 @@ -6330,15 +6328,12 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2156:11: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2179:12: Unsupported typespec, m_sync [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2230:12: Unsupported typespec, m_successors -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:15: Unsupported typespec, m_object_names [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: Unsupported typespec, i [LINT]: \_ ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 78e9ba3baa..89f146c6aa 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -9,7 +9,7 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): CMake that the project does not need compatibility with older versions. --- Configuring done (0.1s) +-- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser [100%] Generating preprocessing @@ -77,23 +77,23 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required): CMake that the project does not need compatibility with older versions. --- Configuring done (0.1s) +-- Configuring done (0.0s) -- Generating done (0.0s) -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 10_lsu_bus_intf.sv -[ 12%] Generating 11_ifu_bp_ctl.sv -[ 18%] Generating 12_beh_lib.sv -[ 25%] Generating 13_ifu_mem_ctl.sv -[ 31%] Generating 14_mem_lib.sv +[ 6%] Generating 11_ifu_bp_ctl.sv +[ 12%] Generating 12_beh_lib.sv +[ 18%] Generating 13_ifu_mem_ctl.sv +[ 25%] Generating 14_mem_lib.sv +[ 31%] Generating 10_lsu_bus_intf.sv [ 37%] Generating 15_exu.sv [ 43%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv -[ 62%] Generating 3_rvjtag_tap.sv -[ 68%] Generating 4_dec_tlu_ctl.sv -[ 75%] Generating 5_lsu_bus_buffer.sv -[ 81%] Generating 7_axi4_to_ahb.sv -[ 87%] Generating 6_dbg.sv +[ 62%] Generating 4_dec_tlu_ctl.sv +[ 68%] Generating 3_rvjtag_tap.sv +[ 81%] Generating 6_dbg.sv +[ 81%] Generating 5_lsu_bus_buffer.sv +[ 87%] Generating 7_axi4_to_ahb.sv [ 93%] Generating 8_ifu_aln_ctl.sv [100%] Generating 9_tb_top.sv [100%] Built target Parse @@ -2502,8 +2502,7 @@ array_expr 1 array_net 38 array_typespec 672 array_var 648 -assign_stmt 3658 -assignment 7737 +assignment 11395 begin 7196 bit_select 20124 bit_typespec 2219 @@ -2579,12 +2578,12 @@ real_typespec 33 real_var 8 ref_module 2139 ref_obj 136747 -ref_typespec 91110 +ref_typespec 91108 ref_var 1830 repeat 26 return_stmt 3379 -string_typespec 3206 -string_var 1405 +string_typespec 3204 +string_var 1403 struct_net 199 struct_typespec 52 struct_var 55 @@ -2609,8 +2608,7 @@ array_expr 1 array_net 38 array_typespec 675 array_var 5037 -assign_stmt 10248 -assignment 43769 +assignment 53892 begin 46172 bit_select 25897 bit_typespec 2220 @@ -2687,12 +2685,12 @@ real_typespec 33 real_var 10 ref_module 2139 ref_obj 383727 -ref_typespec 191633 +ref_typespec 191621 ref_var 8701 repeat 207 return_stmt 19618 -string_typespec 3206 -string_var 5171 +string_typespec 3204 +string_var 5169 struct_net 199 struct_typespec 66 struct_var 184 @@ -6421,15 +6419,12 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2156:11: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2179:12: Unsupported typespec, m_sync [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2230:12: Unsupported typespec, m_successors -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:15: Unsupported typespec, m_object_names [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: Unsupported typespec, i [LINT]: \_ ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: diff --git a/third_party/tests/Driver/Driver.log b/third_party/tests/Driver/Driver.log index 6c8963c1e9..7f32191a98 100644 --- a/third_party/tests/Driver/Driver.log +++ b/third_party/tests/Driver/Driver.log @@ -400,8 +400,7 @@ there are 1 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 624 array_var 602 -assign_stmt 3586 -assignment 6339 +assignment 9925 begin 6842 bit_select 2128 bit_typespec 4595 @@ -475,12 +474,12 @@ real_typespec 33 real_var 8 ref_module 1 ref_obj 41535 -ref_typespec 23336 +ref_typespec 23334 ref_var 1795 repeat 30 return_stmt 3301 -string_typespec 3378 -string_var 1458 +string_typespec 3376 +string_var 1456 struct_typespec 14 struct_var 35 sys_func_call 1356 @@ -4098,7 +4097,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4106,8 +4104,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -4673,7 +4669,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4681,8 +4676,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log index a68f47120c..feb0eaee86 100644 --- a/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log +++ b/third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log @@ -6160,8 +6160,7 @@ array_net 29 array_typespec 840 array_var 226 assert_stmt 2 -assign_stmt 679 -assignment 8517 +assignment 9196 begin 5057 bit_select 23031 bit_typespec 1043 @@ -6236,8 +6235,7 @@ array_net 29 array_typespec 1101 array_var 259 assert_stmt 4 -assign_stmt 1914 -assignment 34005 +assignment 35919 begin 20995 bit_select 62249 bit_typespec 1043 diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log index 3d0b46e3fb..7ebbba682a 100644 --- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log +++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log @@ -14327,8 +14327,7 @@ always 1957 array_net 83 array_typespec 3315 array_var 477 -assign_stmt 1180 -assignment 16228 +assignment 17408 attribute 35 begin 8926 bit_select 46270 @@ -14413,8 +14412,7 @@ always 17644 array_net 83 array_typespec 3666 array_var 749 -assign_stmt 9782 -assignment 109977 +assignment 119759 attribute 35 begin 86444 bit_select 360189 diff --git a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log index 09cfc5f435..7218d51d19 100644 --- a/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log +++ b/third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log @@ -5810,8 +5810,7 @@ always 1153 array_net 29 array_typespec 847 array_var 246 -assign_stmt 717 -assignment 8948 +assignment 9665 begin 5303 bit_select 22529 bit_typespec 1099 @@ -5892,8 +5891,7 @@ always 6045 array_net 29 array_typespec 1108 array_var 279 -assign_stmt 1936 -assignment 34591 +assignment 36527 begin 21437 bit_select 60983 bit_typespec 1099 diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log index d248d35b3a..63351a9b25 100644 --- a/third_party/tests/Ibex/Ibex.log +++ b/third_party/tests/Ibex/Ibex.log @@ -783,8 +783,7 @@ array_net 9 array_typespec 3623 array_var 3581 assert_stmt 75 -assign_stmt 9034 -assignment 36357 +assignment 45379 begin 36900 bit_select 14755 bit_typespec 56304 @@ -866,12 +865,12 @@ real_typespec 59 real_var 9 ref_module 55 ref_obj 237322 -ref_typespec 164329 +ref_typespec 164327 ref_var 9791 repeat 164 return_stmt 14242 -string_typespec 16373 -string_var 7935 +string_typespec 16371 +string_var 7933 struct_net 9 struct_typespec 320 struct_var 263 @@ -35419,7 +35418,6 @@ while_stmt 599 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -35427,8 +35425,6 @@ while_stmt 599 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -43993,7 +43989,6 @@ while_stmt 599 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -44001,8 +43996,6 @@ while_stmt 599 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/IbexGoogle/IbexGoogle.log b/third_party/tests/IbexGoogle/IbexGoogle.log index edd3517538..2b99857915 100644 --- a/third_party/tests/IbexGoogle/IbexGoogle.log +++ b/third_party/tests/IbexGoogle/IbexGoogle.log @@ -468,8 +468,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/uvm-1.2/src/uvm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1831 array_var 1732 -assign_stmt 5660 -assignment 16879 +assignment 22535 begin 17510 bit_select 6042 bit_typespec 15830 @@ -534,12 +533,12 @@ range 16740 real_typespec 41 real_var 8 ref_obj 110782 -ref_typespec 59065 +ref_typespec 59063 ref_var 4642 repeat 73 return_stmt 7108 -string_typespec 7571 -string_var 3525 +string_typespec 7569 +string_var 3523 struct_typespec 112 struct_var 112 sys_func_call 3559 @@ -14479,7 +14478,6 @@ while_stmt 276 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -14487,8 +14485,6 @@ while_stmt 276 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -17905,7 +17901,6 @@ while_stmt 276 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -17913,8 +17908,6 @@ while_stmt 276 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/IncompTitan/IncompTitan.log b/third_party/tests/IncompTitan/IncompTitan.log index d6f6807318..a25716e6ad 100644 --- a/third_party/tests/IncompTitan/IncompTitan.log +++ b/third_party/tests/IncompTitan/IncompTitan.log @@ -5324,8 +5324,7 @@ array_net 38 array_typespec 866 array_var 231 assert_stmt 428 -assign_stmt 767 -assignment 5452 +assignment 6219 assume 30 attribute 33 begin 4027 diff --git a/third_party/tests/MiniAmiq/MiniAmiq.log b/third_party/tests/MiniAmiq/MiniAmiq.log index 8f54fe045a..79bd786a93 100644 --- a/third_party/tests/MiniAmiq/MiniAmiq.log +++ b/third_party/tests/MiniAmiq/MiniAmiq.log @@ -403,8 +403,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/uvm-1.2/src/uvm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1127 array_var 1105 -assign_stmt 4652 -assignment 11150 +assignment 15800 begin 12054 bit_select 3949 bit_typespec 6474 @@ -472,12 +471,12 @@ range 6646 real_typespec 37 real_var 8 ref_obj 72751 -ref_typespec 35146 +ref_typespec 35144 ref_var 3341 repeat 48 return_stmt 5223 -string_typespec 5315 -string_var 2369 +string_typespec 5313 +string_var 2367 struct_typespec 62 struct_var 72 sys_func_call 2228 @@ -9230,7 +9229,6 @@ while_stmt 191 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -9238,8 +9236,6 @@ while_stmt 191 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/Monitor/Monitor.log b/third_party/tests/Monitor/Monitor.log index e8392aa1bb..637b83c535 100644 --- a/third_party/tests/Monitor/Monitor.log +++ b/third_party/tests/Monitor/Monitor.log @@ -433,8 +433,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pk === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1077 array_var 1055 -assign_stmt 4660 -assignment 11190 +assignment 15848 begin 12089 bit_select 3949 bit_typespec 9136 @@ -509,12 +508,12 @@ real_typespec 37 real_var 8 ref_module 1 ref_obj 72940 -ref_typespec 39565 +ref_typespec 39563 ref_var 3347 repeat 50 return_stmt 5240 -string_typespec 5505 -string_var 2444 +string_typespec 5503 +string_var 2442 struct_typespec 62 struct_var 71 sys_func_call 2306 @@ -9301,7 +9300,6 @@ while_stmt 191 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -9309,8 +9307,6 @@ while_stmt 191 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -11470,7 +11466,6 @@ while_stmt 191 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -11478,8 +11473,6 @@ while_stmt 191 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index e7dc0e8fc9..1b534595de 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -883,8 +883,7 @@ always 542 array_net 39 array_typespec 185 array_var 144 -assign_stmt 70 -assignment 5881 +assignment 5951 begin 1513 bit_select 5412 bit_typespec 18 @@ -963,8 +962,7 @@ always 1836 array_net 39 array_typespec 185 array_var 289 -assign_stmt 238 -assignment 22060 +assignment 22298 begin 4762 bit_select 15708 bit_typespec 18 diff --git a/third_party/tests/OVMSwitch/OVMSwitch.log b/third_party/tests/OVMSwitch/OVMSwitch.log index 0347271890..5baa1d6c2c 100644 --- a/third_party/tests/OVMSwitch/OVMSwitch.log +++ b/third_party/tests/OVMSwitch/OVMSwitch.log @@ -364,8 +364,7 @@ always 13 array_net 5 array_typespec 334 array_var 315 -assign_stmt 1209 -assignment 2940 +assignment 4149 begin 2825 bit_select 963 bit_typespec 1115 diff --git a/third_party/tests/Opentitan/Earlgrey.log b/third_party/tests/Opentitan/Earlgrey.log index a278e8b9c2..e82645189c 100644 --- a/third_party/tests/Opentitan/Earlgrey.log +++ b/third_party/tests/Opentitan/Earlgrey.log @@ -25166,8 +25166,7 @@ array_net 23 array_typespec 559 array_var 229 assert_stmt 2 -assign_stmt 235 -assignment 6311 +assignment 6546 begin 3834 bit_select 14053 bit_typespec 598 @@ -25240,8 +25239,7 @@ array_net 23 array_typespec 802 array_var 373 assert_stmt 4 -assign_stmt 1430 -assignment 26234 +assignment 27664 begin 15948 bit_select 41769 bit_typespec 598 diff --git a/third_party/tests/Opentitan/Opentitan.log b/third_party/tests/Opentitan/Opentitan.log index f836a22779..801c1f0c3c 100644 --- a/third_party/tests/Opentitan/Opentitan.log +++ b/third_party/tests/Opentitan/Opentitan.log @@ -4174,8 +4174,7 @@ array_net 23 array_typespec 1222 array_var 870 assert_stmt 526 -assign_stmt 3789 -assignment 12636 +assignment 16425 assume 114 begin 10742 bit_select 16762 @@ -4261,13 +4260,13 @@ real_typespec 33 real_var 8 ref_module 1427 ref_obj 155881 -ref_typespec 113094 +ref_typespec 113092 ref_var 1842 repeat 26 return_stmt 3321 sequence_decl 18 -string_typespec 5659 -string_var 1368 +string_typespec 5657 +string_var 1366 struct_net 108 struct_typespec 1441 struct_var 1037 @@ -4292,8 +4291,7 @@ array_net 23 array_typespec 1468 array_var 5403 assert_stmt 4393 -assign_stmt 11571 -assignment 68436 +assignment 79882 assume 360 begin 62066 bit_select 51781 @@ -4380,13 +4378,13 @@ real_typespec 33 real_var 10 ref_module 1427 ref_obj 563093 -ref_typespec 269998 +ref_typespec 269986 ref_var 8711 repeat 207 return_stmt 19839 sequence_decl 90 -string_typespec 5929 -string_var 5122 +string_typespec 5927 +string_var 5120 struct_net 108 struct_typespec 1455 struct_var 1468 @@ -10060,15 +10058,12 @@ while_stmt 353 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2156:11: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2179:12: Unsupported typespec, m_sync [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:2230:12: Unsupported typespec, m_successors -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:15: Unsupported typespec, m_object_names [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: Unsupported typespec, i [LINT]: \_ ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_recorder.svh:774:30: diff --git a/third_party/tests/RiscV/RiscV.log b/third_party/tests/RiscV/RiscV.log index 18af6c3519..fde53d9cb4 100644 --- a/third_party/tests/RiscV/RiscV.log +++ b/third_party/tests/RiscV/RiscV.log @@ -60,8 +60,7 @@ there are 2 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 40 array_net 3 -assign_stmt 3 -assignment 417 +assignment 420 begin 192 bit_select 61 case_item 171 diff --git a/third_party/tests/Rp32/rp32.log b/third_party/tests/Rp32/rp32.log index d173a61571..2ef29f431b 100644 --- a/third_party/tests/Rp32/rp32.log +++ b/third_party/tests/Rp32/rp32.log @@ -237,8 +237,7 @@ always 36 array_net 7 array_typespec 9 array_var 1 -assign_stmt 13 -assignment 861 +assignment 874 begin 281 bit_select 158 bit_typespec 5539 @@ -310,8 +309,7 @@ always 62 array_net 7 array_typespec 9 array_var 1 -assign_stmt 14 -assignment 5712 +assignment 5726 begin 1795 bit_select 215 bit_typespec 5539 diff --git a/third_party/tests/SVSwitch/SVSwitch.log b/third_party/tests/SVSwitch/SVSwitch.log index da448c3928..bb7279e681 100644 --- a/third_party/tests/SVSwitch/SVSwitch.log +++ b/third_party/tests/SVSwitch/SVSwitch.log @@ -212,8 +212,7 @@ always 13 array_net 5 array_typespec 5 array_var 5 -assign_stmt 8 -assignment 200 +assignment 208 begin 97 bit_select 105 bit_typespec 32 diff --git a/third_party/tests/Scoreboard/Scoreboard.log b/third_party/tests/Scoreboard/Scoreboard.log index 4a1a89b51d..8dd8b0436f 100644 --- a/third_party/tests/Scoreboard/Scoreboard.log +++ b/third_party/tests/Scoreboard/Scoreboard.log @@ -393,8 +393,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/uvm-1.2/src/uvm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 600 array_var 578 -assign_stmt 3577 -assignment 6324 +assignment 9901 begin 6823 bit_select 2126 bit_typespec 2666 @@ -460,12 +459,12 @@ range 2463 real_typespec 33 real_var 8 ref_obj 41395 -ref_typespec 20141 +ref_typespec 20139 ref_var 1793 repeat 26 return_stmt 3287 -string_typespec 3243 -string_var 1388 +string_typespec 3241 +string_var 1386 struct_typespec 14 struct_var 35 sys_func_call 1352 @@ -4092,7 +4091,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4100,8 +4098,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -4657,7 +4653,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4665,8 +4660,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log index 96a1ddbc4e..ce0b254928 100644 --- a/third_party/tests/Scr1/Scr1.log +++ b/third_party/tests/Scr1/Scr1.log @@ -223,8 +223,7 @@ always 242 array_typespec 11 array_var 11 assert_stmt 38 -assign_stmt 73 -assignment 2074 +assignment 2147 begin 1309 bit_select 628 bit_typespec 251 diff --git a/third_party/tests/Scr1SvTests/Scr1SvTests.log b/third_party/tests/Scr1SvTests/Scr1SvTests.log index d380f94561..270952df58 100644 --- a/third_party/tests/Scr1SvTests/Scr1SvTests.log +++ b/third_party/tests/Scr1SvTests/Scr1SvTests.log @@ -155,8 +155,7 @@ always 266 array_typespec 11 array_var 11 assert_stmt 32 -assign_stmt 65 -assignment 1813 +assignment 1878 begin 1103 bit_select 579 bit_typespec 246 diff --git a/third_party/tests/SeqDriver/SeqDriver.log b/third_party/tests/SeqDriver/SeqDriver.log index cb0992d1e7..e8004e2a96 100644 --- a/third_party/tests/SeqDriver/SeqDriver.log +++ b/third_party/tests/SeqDriver/SeqDriver.log @@ -385,8 +385,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/uvm-1.2/src/uvm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1055 array_var 1033 -assign_stmt 4400 -assignment 10901 +assignment 15299 begin 11485 bit_select 3762 bit_typespec 5433 @@ -456,12 +455,12 @@ real_typespec 37 real_var 8 ref_module 1 ref_obj 70933 -ref_typespec 32679 +ref_typespec 32677 ref_var 3113 repeat 49 return_stmt 5036 -string_typespec 4934 -string_var 2191 +string_typespec 4932 +string_var 2189 struct_typespec 62 struct_var 72 sys_func_call 2056 @@ -9090,7 +9089,6 @@ while_stmt 188 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -9098,8 +9096,6 @@ while_stmt 188 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -10980,7 +10976,6 @@ while_stmt 188 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -10988,8 +10983,6 @@ while_stmt 188 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/SimpleOVM/SimpleOVM.log b/third_party/tests/SimpleOVM/SimpleOVM.log index faa81ae416..aba71a53b9 100644 --- a/third_party/tests/SimpleOVM/SimpleOVM.log +++ b/third_party/tests/SimpleOVM/SimpleOVM.log @@ -325,8 +325,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/ovm-2.1.2/src/ovm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 123 array_var 107 -assign_stmt 1150 -assignment 2675 +assignment 3825 begin 2597 bit_select 844 bit_typespec 862 diff --git a/third_party/tests/SimpleParserTest/SimpleParserTest.log b/third_party/tests/SimpleParserTest/SimpleParserTest.log index 1f5a40f8fb..4597fadbdc 100644 --- a/third_party/tests/SimpleParserTest/SimpleParserTest.log +++ b/third_party/tests/SimpleParserTest/SimpleParserTest.log @@ -58,8 +58,7 @@ there are 1 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 25 array_net 3 -assign_stmt 11 -assignment 146 +assignment 157 begin 55 bit_select 97 case_item 35 @@ -1023,13 +1022,13 @@ design: (work@dff_async_reset) \_begin: (work@LFSR_TASK.LFSR_TAPS8_TASK), line:16:2, endln:24:5 |vpiFullName:work@LFSR_TASK.LFSR_TAPS8_TASK |vpiForInitStmt: - \_assign_stmt: , line:18:7, endln:18:10 + \_assignment: , line:18:7, endln:18:10 |vpiParent: \_for_stmt: (work@LFSR_TASK.LFSR_TAPS8_TASK), line:18:2, endln:18:5 |vpiRhs: \_constant: , line:18:9, endln:18:10 |vpiParent: - \_assign_stmt: , line:18:7, endln:18:10 + \_assignment: , line:18:7, endln:18:10 |vpiDecompile:1 |vpiSize:64 |UINT:1 @@ -1037,7 +1036,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@LFSR_TASK.LFSR_TAPS8_TASK.i), line:18:7, endln:18:8 |vpiParent: - \_assign_stmt: , line:18:7, endln:18:10 + \_assignment: , line:18:7, endln:18:10 |vpiName:i |vpiFullName:work@LFSR_TASK.LFSR_TAPS8_TASK.i |vpiForIncStmt: @@ -2207,13 +2206,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:22:2, endln:29:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:23:7, endln:23:10 + \_assignment: , line:23:7, endln:23:10 |vpiParent: \_for_stmt: (work@arbiter), line:23:2, endln:23:5 |vpiRhs: \_constant: , line:23:9, endln:23:10 |vpiParent: - \_assign_stmt: , line:23:7, endln:23:10 + \_assignment: , line:23:7, endln:23:10 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2221,7 +2220,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.i), line:23:7, endln:23:8 |vpiParent: - \_assign_stmt: , line:23:7, endln:23:10 + \_assignment: , line:23:7, endln:23:10 |vpiName:i |vpiFullName:work@arbiter.i |vpiForIncStmt: @@ -2289,13 +2288,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:24:2, endln:28:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:25:7, endln:25:10 + \_assignment: , line:25:7, endln:25:10 |vpiParent: \_for_stmt: (work@arbiter), line:25:2, endln:25:5 |vpiRhs: \_constant: , line:25:9, endln:25:10 |vpiParent: - \_assign_stmt: , line:25:7, endln:25:10 + \_assignment: , line:25:7, endln:25:10 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2303,7 +2302,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.j), line:25:7, endln:25:8 |vpiParent: - \_assign_stmt: , line:25:7, endln:25:10 + \_assignment: , line:25:7, endln:25:10 |vpiName:j |vpiFullName:work@arbiter.j |vpiForIncStmt: @@ -2794,13 +2793,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:63:2, endln:66:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:64:6, endln:64:9 + \_assignment: , line:64:6, endln:64:9 |vpiParent: \_for_stmt: (work@arbiter), line:64:2, endln:64:5 |vpiRhs: \_constant: , line:64:8, endln:64:9 |vpiParent: - \_assign_stmt: , line:64:6, endln:64:9 + \_assignment: , line:64:6, endln:64:9 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -2808,7 +2807,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.k), line:64:6, endln:64:7 |vpiParent: - \_assign_stmt: , line:64:6, endln:64:9 + \_assignment: , line:64:6, endln:64:9 |vpiName:k |vpiFullName:work@arbiter.k |vpiForIncStmt: @@ -2991,13 +2990,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:69:2, endln:73:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:70:6, endln:70:9 + \_assignment: , line:70:6, endln:70:9 |vpiParent: \_for_stmt: (work@arbiter), line:70:2, endln:70:5 |vpiRhs: \_constant: , line:70:8, endln:70:9 |vpiParent: - \_assign_stmt: , line:70:6, endln:70:9 + \_assignment: , line:70:6, endln:70:9 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -3005,7 +3004,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.r), line:70:6, endln:70:7 |vpiParent: - \_assign_stmt: , line:70:6, endln:70:9 + \_assignment: , line:70:6, endln:70:9 |vpiName:r |vpiFullName:work@arbiter.r |vpiForIncStmt: @@ -3318,13 +3317,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:79:2, endln:83:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:81:7, endln:81:10 + \_assignment: , line:81:7, endln:81:10 |vpiParent: \_for_stmt: (work@arbiter), line:81:2, endln:81:5 |vpiRhs: \_constant: , line:81:9, endln:81:10 |vpiParent: - \_assign_stmt: , line:81:7, endln:81:10 + \_assignment: , line:81:7, endln:81:10 |vpiDecompile:1 |vpiSize:64 |UINT:1 @@ -3332,7 +3331,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.p), line:81:7, endln:81:8 |vpiParent: - \_assign_stmt: , line:81:7, endln:81:10 + \_assignment: , line:81:7, endln:81:10 |vpiName:p |vpiFullName:work@arbiter.p |vpiForIncStmt: @@ -3641,13 +3640,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:87:2, endln:90:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:88:6, endln:88:9 + \_assignment: , line:88:6, endln:88:9 |vpiParent: \_for_stmt: (work@arbiter), line:88:2, endln:88:5 |vpiRhs: \_constant: , line:88:8, endln:88:9 |vpiParent: - \_assign_stmt: , line:88:6, endln:88:9 + \_assignment: , line:88:6, endln:88:9 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -3655,7 +3654,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.q), line:88:6, endln:88:7 |vpiParent: - \_assign_stmt: , line:88:6, endln:88:9 + \_assignment: , line:88:6, endln:88:9 |vpiName:q |vpiFullName:work@arbiter.q |vpiForIncStmt: @@ -3808,13 +3807,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:95:2, endln:98:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:96:6, endln:96:9 + \_assignment: , line:96:6, endln:96:9 |vpiParent: \_for_stmt: (work@arbiter), line:96:2, endln:96:5 |vpiRhs: \_constant: , line:96:8, endln:96:9 |vpiParent: - \_assign_stmt: , line:96:6, endln:96:9 + \_assignment: , line:96:6, endln:96:9 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -3822,7 +3821,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.s), line:96:6, endln:96:7 |vpiParent: - \_assign_stmt: , line:96:6, endln:96:9 + \_assignment: , line:96:6, endln:96:9 |vpiName:s |vpiFullName:work@arbiter.s |vpiForIncStmt: @@ -4209,13 +4208,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:102:2, endln:106:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:104:6, endln:104:9 + \_assignment: , line:104:6, endln:104:9 |vpiParent: \_for_stmt: (work@arbiter), line:104:2, endln:104:5 |vpiRhs: \_constant: , line:104:8, endln:104:9 |vpiParent: - \_assign_stmt: , line:104:6, endln:104:9 + \_assignment: , line:104:6, endln:104:9 |vpiDecompile:1 |vpiSize:64 |UINT:1 @@ -4223,7 +4222,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.t), line:104:6, endln:104:7 |vpiParent: - \_assign_stmt: , line:104:6, endln:104:9 + \_assignment: , line:104:6, endln:104:9 |vpiName:t |vpiFullName:work@arbiter.t |vpiForIncStmt: @@ -4604,13 +4603,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:110:2, endln:114:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:112:6, endln:112:9 + \_assignment: , line:112:6, endln:112:9 |vpiParent: \_for_stmt: (work@arbiter), line:112:2, endln:112:5 |vpiRhs: \_constant: , line:112:8, endln:112:9 |vpiParent: - \_assign_stmt: , line:112:6, endln:112:9 + \_assignment: , line:112:6, endln:112:9 |vpiDecompile:1 |vpiSize:64 |UINT:1 @@ -4618,7 +4617,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.u), line:112:6, endln:112:7 |vpiParent: - \_assign_stmt: , line:112:6, endln:112:9 + \_assignment: , line:112:6, endln:112:9 |vpiName:u |vpiFullName:work@arbiter.u |vpiForIncStmt: @@ -4806,13 +4805,13 @@ design: (work@dff_async_reset) \_begin: (work@arbiter), line:116:2, endln:120:5 |vpiFullName:work@arbiter |vpiForInitStmt: - \_assign_stmt: , line:118:6, endln:118:9 + \_assignment: , line:118:6, endln:118:9 |vpiParent: \_for_stmt: (work@arbiter), line:118:2, endln:118:5 |vpiRhs: \_constant: , line:118:8, endln:118:9 |vpiParent: - \_assign_stmt: , line:118:6, endln:118:9 + \_assignment: , line:118:6, endln:118:9 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -4820,7 +4819,7 @@ design: (work@dff_async_reset) |vpiLhs: \_ref_var: (work@arbiter.v), line:118:6, endln:118:7 |vpiParent: - \_assign_stmt: , line:118:6, endln:118:9 + \_assignment: , line:118:6, endln:118:9 |vpiName:v |vpiFullName:work@arbiter.v |vpiForIncStmt: diff --git a/third_party/tests/SimpleUVM/SimpleUVM.log b/third_party/tests/SimpleUVM/SimpleUVM.log index c48afa1184..32650fb1ce 100644 --- a/third_party/tests/SimpleUVM/SimpleUVM.log +++ b/third_party/tests/SimpleUVM/SimpleUVM.log @@ -382,8 +382,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/uvm-1.2/src/uvm_pkg.sv always 1 array_typespec 598 array_var 576 -assign_stmt 3547 -assignment 6293 +assignment 9840 begin 6779 bit_select 2126 bit_typespec 3078 @@ -455,12 +454,12 @@ real_typespec 33 real_var 8 ref_module 1 ref_obj 41230 -ref_typespec 20781 +ref_typespec 20779 ref_var 1788 repeat 27 return_stmt 3272 -string_typespec 3218 -string_var 1373 +string_typespec 3216 +string_var 1371 struct_typespec 14 struct_var 35 sys_func_call 1273 @@ -4021,7 +4020,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4029,8 +4027,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -4595,7 +4591,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -4603,8 +4598,6 @@ while_stmt 108 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/SimpleVMM/SimpleVMM.log b/third_party/tests/SimpleVMM/SimpleVMM.log index 29a970cc3d..dcddb486a0 100644 --- a/third_party/tests/SimpleVMM/SimpleVMM.log +++ b/third_party/tests/SimpleVMM/SimpleVMM.log @@ -100,8 +100,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 92 array_var 92 -assign_stmt 280 -assignment 654 +assignment 934 begin 1034 bit_select 98 bit_typespec 214 diff --git a/third_party/tests/Tnoc/Tnoc.log b/third_party/tests/Tnoc/Tnoc.log index ad07ea3497..1248021543 100644 --- a/third_party/tests/Tnoc/Tnoc.log +++ b/third_party/tests/Tnoc/Tnoc.log @@ -4025,8 +4025,7 @@ always 2638 array_typespec 60 array_var 30 -assign_stmt 225 -assignment 5405 +assignment 5630 begin 4926 bit_select 10479 bit_typespec 5173 diff --git a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log index ebdb474889..e9c124463c 100644 --- a/third_party/tests/UVMNestedSeq/UVMNestedSeq.log +++ b/third_party/tests/UVMNestedSeq/UVMNestedSeq.log @@ -435,8 +435,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/uvm-1.2/src/uvm_pkg.sv always 1 array_typespec 2261 array_var 2239 -assign_stmt 7029 -assignment 24796 +assignment 31817 begin 25650 bit_select 8670 bit_typespec 16636 @@ -505,12 +504,12 @@ real_typespec 49 real_var 8 ref_module 2 ref_obj 160658 -ref_typespec 74372 +ref_typespec 74370 ref_var 7104 repeat 118 return_stmt 10392 -string_typespec 10391 -string_var 4758 +string_typespec 10389 +string_var 4756 struct_typespec 206 struct_var 180 sys_func_call 4415 @@ -24496,7 +24495,6 @@ while_stmt 428 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -24504,8 +24502,6 @@ while_stmt 428 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -30334,7 +30330,6 @@ while_stmt 428 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -30342,8 +30337,6 @@ while_stmt 428 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/UVMSwitch/UVMSwitch.log b/third_party/tests/UVMSwitch/UVMSwitch.log index 2c7a0a2dd7..fdd3598957 100644 --- a/third_party/tests/UVMSwitch/UVMSwitch.log +++ b/third_party/tests/UVMSwitch/UVMSwitch.log @@ -6027,8 +6027,7 @@ always 13 array_net 5 array_typespec 717 array_var 682 -assign_stmt 3601 -assignment 6523 +assignment 10124 begin 6997 bit_select 2244 bit_typespec 10624 @@ -6106,12 +6105,12 @@ real_typespec 33 real_var 8 ref_module 3 ref_obj 42731 -ref_typespec 32651 +ref_typespec 32649 ref_var 1821 repeat 30 return_stmt 3331 -string_typespec 3724 -string_var 1675 +string_typespec 3722 +string_var 1673 struct_typespec 14 struct_var 35 sys_func_call 1351 @@ -9757,7 +9756,6 @@ while_stmt 109 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -9765,8 +9763,6 @@ while_stmt 109 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors @@ -10364,7 +10360,6 @@ while_stmt 109 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1971:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_factory.svh:1991:14: Unsupported typespec, m_override_info [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -10372,8 +10367,6 @@ while_stmt 109 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/UnitAmiqEth/UnitAmiqEth.log b/third_party/tests/UnitAmiqEth/UnitAmiqEth.log index a740b4865b..844a8f1f1b 100644 --- a/third_party/tests/UnitAmiqEth/UnitAmiqEth.log +++ b/third_party/tests/UnitAmiqEth/UnitAmiqEth.log @@ -645,8 +645,7 @@ PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/ovm-2.1.2/src/ovm_pkg.sv === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1291 array_var 1243 -assign_stmt 5724 -assignment 13692 +assignment 19414 begin 14257 bit_select 4637 bit_typespec 8825 @@ -714,12 +713,12 @@ range 8768 real_typespec 55 real_var 11 ref_obj 88969 -ref_typespec 45027 +ref_typespec 45025 ref_var 3476 repeat 50 return_stmt 6655 -string_typespec 7078 -string_var 3049 +string_typespec 7076 +string_var 3047 struct_typespec 62 struct_var 72 sys_func_call 2831 @@ -10953,7 +10952,6 @@ while_stmt 250 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:120:15: Unsupported typespec, uvm_severity [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_globals.svh:219:3: Unsupported typespec, process [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_printer.svh:1454:13: Unsupported typespec, m_children -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_packer.svh:717:11: Unsupported typespec, m_object_references [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1152:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1170:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1193:12: Unsupported typespec, m_predecessors @@ -10961,8 +10959,6 @@ while_stmt 250 [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1244:12: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1332:12: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1357:14: Unsupported typespec, m_sync -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1502:31: Unsupported typespec, m_executing_phases -[LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1521:31: Unsupported typespec, m_executing_phases [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1680:14: Unsupported typespec, m_successors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1702:13: Unsupported typespec, m_predecessors [LINT]: ${SURELOG_DIR}/build/bin/1800.2-2017-1.0/src/base/uvm_phase.svh:1731:13: Unsupported typespec, m_successors diff --git a/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log b/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log index 7ff17f1d50..56c62d971f 100644 --- a/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log +++ b/third_party/tests/YosysBigSim/aes_5cycle_2stage/YosysBigSimAes.log @@ -16,8 +16,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 13 array_net 1 -assign_stmt 1 -assignment 636 +assignment 637 begin 21 bit_select 287 case_item 267 diff --git a/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log b/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log index 3054b7864e..cadbb30411 100644 --- a/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log +++ b/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log @@ -257,8 +257,7 @@ there are 2 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 206 array_net 15 -assign_stmt 16 -assignment 1228 +assignment 1244 begin 246 bit_select 1789 case_item 395 diff --git a/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log b/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log index 7bf454e7dd..6398529bc3 100644 --- a/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log +++ b/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log @@ -90,8 +90,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 95 array_net 21 -assign_stmt 5 -assignment 737 +assignment 742 begin 350 bit_select 267 case_item 89 diff --git a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log index 350c3b80fc..bb4fbb318d 100644 --- a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log +++ b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log @@ -69,8 +69,7 @@ there are 25 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 113 array_net 4 -assign_stmt 2 -assignment 484 +assignment 486 begin 23 bit_select 1078 case_item 70 @@ -78,7 +77,7 @@ case_stmt 13 class_defn 8 class_typespec 4 class_var 3 -constant 7571 +constant 7567 cont_assign 817 delay_control 6 design 1 @@ -102,8 +101,8 @@ integer_typespec 6 integer_var 3 io_decl 16 logic_net 2206 -logic_typespec 2569 -logic_var 13 +logic_typespec 2567 +logic_var 11 module_inst 57 named_event 1 operation 3587 @@ -112,10 +111,10 @@ param_assign 230 parameter 230 part_select 223 port 994 -range 1924 +range 1922 ref_module 16 ref_obj 4426 -ref_typespec 3299 +ref_typespec 3297 ref_var 2 sys_func_call 12 task 9 diff --git a/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log b/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log index 4d91d3c1fa..98c8ee3c80 100644 --- a/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log +++ b/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log @@ -46,8 +46,7 @@ there are 5 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 21 array_net 31 -assign_stmt 11 -assignment 1829 +assignment 1840 begin 345 bit_select 1034 case_item 125 diff --git a/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log b/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log index 64291025d7..6b648cc2de 100644 --- a/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log +++ b/third_party/tests/YosysBigSim/softusb_navre/YosysBigSimSoft.log @@ -17,8 +17,7 @@ there are 2 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 19 array_net 4 -assign_stmt 4 -assignment 541 +assignment 545 begin 119 bit_select 215 case_item 187 diff --git a/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log b/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log index 03a37c28c8..618ecefc39 100644 --- a/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log +++ b/third_party/tests/YosysBigSim/verilog-pong/YosysBigSimPong.log @@ -25,8 +25,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 16 array_net 1 -assign_stmt 3 -assignment 2214 +assignment 2217 begin 52 bit_select 18 case_item 2075 diff --git a/third_party/tests/YosysCam/YosysCam.log b/third_party/tests/YosysCam/YosysCam.log index cd03153583..aa77d5b632 100644 --- a/third_party/tests/YosysCam/YosysCam.log +++ b/third_party/tests/YosysCam/YosysCam.log @@ -709,8 +709,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 1050 array_net 19 -assign_stmt 6 -assignment 1138 +assignment 1144 begin 1620 bit_select 1629 case_item 10 diff --git a/third_party/tests/YosysDsp/YosysDsp.log b/third_party/tests/YosysDsp/YosysDsp.log index d129f8508c..7ac49644bd 100644 --- a/third_party/tests/YosysDsp/YosysDsp.log +++ b/third_party/tests/YosysDsp/YosysDsp.log @@ -1434,8 +1434,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 510 array_net 25 -assign_stmt 5 -assignment 957 +assignment 962 begin 50 bit_select 5763 class_defn 8 @@ -1486,8 +1485,7 @@ var_select 23 === UHDM Object Stats Begin (Elaborated Model) === always 4976 array_net 25 -assign_stmt 5 -assignment 15581 +assignment 15586 begin 2374 bit_select 14968 class_defn 8 diff --git a/third_party/tests/YosysIce40/YosysIce40.log b/third_party/tests/YosysIce40/YosysIce40.log index a8170d2269..b96d2513ed 100644 --- a/third_party/tests/YosysIce40/YosysIce40.log +++ b/third_party/tests/YosysIce40/YosysIce40.log @@ -339,8 +339,7 @@ there are 5 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 179 array_net 11 -assign_stmt 2 -assignment 5210 +assignment 5212 attribute 17 begin 726 bit_select 3742 diff --git a/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log b/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log index 65a45718e9..dffa1a049c 100644 --- a/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log +++ b/third_party/tests/YosysOldTests/openmsp430/YosysOldOpen.log @@ -93,7 +93,7 @@ case_stmt 13 class_defn 8 class_typespec 4 class_var 3 -constant 7159 +constant 7155 cont_assign 861 design 1 enum_const 5 @@ -109,8 +109,8 @@ int_typespec 447 int_var 4 io_decl 16 logic_net 2265 -logic_typespec 2662 -logic_var 13 +logic_typespec 2660 +logic_var 11 module_inst 67 operation 3756 package 2 @@ -118,10 +118,10 @@ param_assign 226 parameter 226 part_select 218 port 1047 -range 1866 +range 1864 ref_module 16 ref_obj 4591 -ref_typespec 3380 +ref_typespec 3378 task 9 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/YosysOldOpen/slpp_unit/surelog.uhdm ... diff --git a/third_party/tests/YosysRiscv/YosysRiscv.log b/third_party/tests/YosysRiscv/YosysRiscv.log index ff56c537b9..7e2d9a45a3 100644 --- a/third_party/tests/YosysRiscv/YosysRiscv.log +++ b/third_party/tests/YosysRiscv/YosysRiscv.log @@ -73,8 +73,7 @@ there are 4 more instances of this message. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === always 5 -assign_stmt 10 -assignment 52 +assignment 62 begin 9 bit_select 115 case_item 3 diff --git a/third_party/tests/YosysSmall/YosysSmall.log b/third_party/tests/YosysSmall/YosysSmall.log index e20221cc3a..bd2763c604 100644 --- a/third_party/tests/YosysSmall/YosysSmall.log +++ b/third_party/tests/YosysSmall/YosysSmall.log @@ -31,8 +31,7 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === always 5 array_net 4 -assign_stmt 3 -assignment 287 +assignment 290 begin 15 bit_select 275 class_defn 8 diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log index c2febeb660..89667fd776 100644 --- a/third_party/tests/oh/BasicOh.log +++ b/third_party/tests/oh/BasicOh.log @@ -656,8 +656,7 @@ always 76 array_net 1 array_typespec 2 array_var 2 -assign_stmt 30 -assignment 157 +assignment 187 begin 97 bit_select 114 class_defn 8 @@ -716,8 +715,7 @@ always 108 array_net 1 array_typespec 2 array_var 2 -assign_stmt 33 -assignment 222 +assignment 255 begin 99 bit_select 179 class_defn 8 @@ -1473,13 +1471,13 @@ design: (work@oh_fifo_async) \_begin: (work@oh_bin2gray), line:25:6, endln:29:9 |vpiFullName:work@oh_bin2gray |vpiForInitStmt: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiParent: \_for_stmt: (work@oh_bin2gray), line:27:2, endln:27:5 |vpiRhs: \_constant: , line:27:9, endln:27:10 |vpiParent: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -1487,7 +1485,7 @@ design: (work@oh_fifo_async) |vpiLhs: \_ref_var: (work@oh_bin2gray.i), line:27:7, endln:27:8 |vpiParent: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiName:i |vpiFullName:work@oh_bin2gray.i |vpiForIncStmt: @@ -2057,13 +2055,15 @@ design: (work@oh_fifo_async) \_gen_if_else: , line:22:7, endln:42:5 |vpiFullName:work@oh_dsync |vpiStmt: - \_assign_stmt: , line:23:20, endln:23:29 + \_assignment: , line:23:20, endln:23:29 |vpiParent: \_begin: (work@oh_dsync) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@oh_dsync.sync_pipe), line:23:20, endln:23:29 |vpiParent: - \_assign_stmt: , line:23:20, endln:23:29 + \_assignment: , line:23:20, endln:23:29 |vpiTypespec: \_ref_typespec: (work@oh_dsync.sync_pipe) |vpiParent: @@ -5727,13 +5727,15 @@ design: (work@oh_fifo_async) \_gen_if_else: , line:43:7, endln:76:10 |vpiFullName:work@oh_memory_dp |vpiStmt: - \_assign_stmt: , line:48:22, endln:48:40 + \_assignment: , line:48:22, endln:48:40 |vpiParent: \_begin: (work@oh_memory_dp) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_array_var: (work@oh_memory_dp.ram), line:48:22, endln:48:25 |vpiParent: - \_assign_stmt: , line:48:22, endln:48:40 + \_assignment: , line:48:22, endln:48:40 |vpiTypespec: \_ref_typespec: (work@oh_memory_dp.ram) |vpiParent: @@ -5757,13 +5759,15 @@ design: (work@oh_fifo_async) \_logic_typespec: , line:48:3, endln:48:14 |vpiFullName:work@oh_memory_dp.ram |vpiStmt: - \_assign_stmt: , line:50:17, endln:50:18 + \_assignment: , line:50:17, endln:50:18 |vpiParent: \_begin: (work@oh_memory_dp) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_integer_var: (work@oh_memory_dp.i), line:50:17, endln:50:18 |vpiParent: - \_assign_stmt: , line:50:17, endln:50:18 + \_assignment: , line:50:17, endln:50:18 |vpiTypespec: \_ref_typespec: (work@oh_memory_dp.i) |vpiParent: @@ -5799,13 +5803,13 @@ design: (work@oh_fifo_async) \_event_control: , line:53:10, endln:53:27 |vpiFullName:work@oh_memory_dp |vpiForInitStmt: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiParent: \_for_stmt: (work@oh_memory_dp), line:54:5, endln:54:8 |vpiRhs: \_constant: , line:54:12, endln:54:13 |vpiParent: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -5813,7 +5817,7 @@ design: (work@oh_fifo_async) |vpiLhs: \_ref_var: (work@oh_memory_dp.i), line:54:10, endln:54:11 |vpiParent: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiName:i |vpiFullName:work@oh_memory_dp.i |vpiForIncStmt: @@ -6032,13 +6036,15 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiStmt: - \_assign_stmt: , line:62:21, endln:62:27 + \_assignment: , line:62:21, endln:62:27 |vpiParent: \_begin: (work@oh_memory_dp) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@oh_memory_dp.rd_reg), line:62:21, endln:62:27 |vpiParent: - \_assign_stmt: , line:62:21, endln:62:27 + \_assignment: , line:62:21, endln:62:27 |vpiTypespec: \_ref_typespec: (work@oh_memory_dp.rd_reg) |vpiParent: @@ -6518,13 +6524,15 @@ design: (work@oh_fifo_async) \_gen_if_else: , line:20:7, endln:38:5 |vpiFullName:work@oh_rsync |vpiStmt: - \_assign_stmt: , line:22:24, endln:22:33 + \_assignment: , line:22:24, endln:22:33 |vpiParent: \_begin: (work@oh_rsync) + |vpiOpType:82 + |vpiBlocking:1 |vpiLhs: \_logic_var: (work@oh_rsync.sync_pipe), line:22:24, endln:22:33 |vpiParent: - \_assign_stmt: , line:22:24, endln:22:33 + \_assignment: , line:22:24, endln:22:33 |vpiTypespec: \_ref_typespec: (work@oh_rsync.sync_pipe) |vpiParent: @@ -9595,7 +9603,7 @@ design: (work@oh_fifo_async) \_begin: (work@oh_fifo_async.wr_bin2gray), line:25:6, endln:29:9 |vpiFullName:work@oh_fifo_async.wr_bin2gray |vpiForInitStmt: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiParent: \_for_stmt: (work@oh_fifo_async.wr_bin2gray), line:27:2, endln:27:5 |vpiRhs: @@ -9603,7 +9611,7 @@ design: (work@oh_fifo_async) |vpiLhs: \_ref_var: (work@oh_fifo_async.wr_bin2gray.i), line:27:7, endln:27:8 |vpiParent: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiName:i |vpiFullName:work@oh_fifo_async.wr_bin2gray.i |vpiActual: @@ -13996,7 +14004,7 @@ design: (work@oh_fifo_async) \_begin: (work@oh_fifo_async.rd_bin2gray), line:25:6, endln:29:9 |vpiFullName:work@oh_fifo_async.rd_bin2gray |vpiForInitStmt: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiParent: \_for_stmt: (work@oh_fifo_async.rd_bin2gray), line:27:2, endln:27:5 |vpiRhs: @@ -14004,7 +14012,7 @@ design: (work@oh_fifo_async) |vpiLhs: \_ref_var: (work@oh_fifo_async.rd_bin2gray.i), line:27:7, endln:27:8 |vpiParent: - \_assign_stmt: , line:27:7, endln:27:10 + \_assignment: , line:27:7, endln:27:10 |vpiName:i |vpiFullName:work@oh_fifo_async.rd_bin2gray.i |vpiActual: @@ -19514,13 +19522,13 @@ design: (work@oh_fifo_async) \_event_control: , line:53:10, endln:53:27 |vpiFullName:work@oh_fifo_async.oh_memory_dp.genblk1 |vpiForInitStmt: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiParent: \_for_stmt: (work@oh_fifo_async.oh_memory_dp.genblk1), line:54:5, endln:54:8 |vpiRhs: \_constant: , line:54:12, endln:54:13 |vpiParent: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiDecompile:0 |vpiSize:64 |UINT:0 @@ -19528,7 +19536,7 @@ design: (work@oh_fifo_async) |vpiLhs: \_ref_var: (work@oh_fifo_async.oh_memory_dp.genblk1.i), line:54:10, endln:54:11 |vpiParent: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiName:i |vpiFullName:work@oh_fifo_async.oh_memory_dp.genblk1.i |vpiActual: @@ -22656,7 +22664,7 @@ design: (work@oh_fifo_async) |vpiConstType:9 \_int_typespec: |UINT:1 -\_assign_stmt: , line:54:10, endln:54:13 +\_assignment: , line:54:10, endln:54:13 |vpiParent: \_for_stmt: (work@oh_fifo_async.oh_memory_dp.genblk1), line:54:5, endln:54:8 |vpiRhs: @@ -22664,7 +22672,7 @@ design: (work@oh_fifo_async) |vpiLhs: \_ref_var: (work@oh_fifo_async.oh_memory_dp.genblk1.i), line:54:10, endln:54:11 |vpiParent: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiName:i |vpiFullName:work@oh_fifo_async.oh_memory_dp.genblk1.i \_for_stmt: (work@oh_fifo_async.oh_memory_dp.genblk1), line:54:5, endln:54:8 @@ -22672,7 +22680,7 @@ design: (work@oh_fifo_async) \_event_control: , line:53:10, endln:53:27 |vpiFullName:work@oh_fifo_async.oh_memory_dp.genblk1 |vpiForInitStmt: - \_assign_stmt: , line:54:10, endln:54:13 + \_assignment: , line:54:10, endln:54:13 |vpiForIncStmt: \_assignment: , line:54:18, endln:54:23 |vpiParent: diff --git a/third_party/tests/rggen/Rggen.log b/third_party/tests/rggen/Rggen.log index 215b2abb23..5edb5d1937 100644 --- a/third_party/tests/rggen/Rggen.log +++ b/third_party/tests/rggen/Rggen.log @@ -4502,8 +4502,7 @@ always 342 array_typespec 203 array_var 137 -assign_stmt 42 -assignment 726 +assignment 768 begin 990 bit_select 5350 bit_typespec 3251 @@ -4570,8 +4569,7 @@ while_stmt 1 always 1459 array_typespec 203 array_var 4895 -assign_stmt 590 -assignment 29251 +assignment 29841 begin 15959 bit_select 48633 bit_typespec 3251