diff --git a/src/main/scala/chisel3/ltl/LTL.scala b/src/main/scala/chisel3/ltl/LTL.scala
index 73c4ef8f895..b5400afb9c6 100644
--- a/src/main/scala/chisel3/ltl/LTL.scala
+++ b/src/main/scala/chisel3/ltl/LTL.scala
@@ -136,7 +136,7 @@ object Sequence extends SequenceObjIntf {
     OpaqueSequence(LTLDelayIntrinsic(delay, None)(seq.inner))
 
   protected def _past(seq: Sequence, delay: Int)(implicit sourceInfo: SourceInfo): Sequence =
-    OpaqueSequence(LTLPastIntrinsic(delay)(seq.inner))
+    _pastClock(seq, delay, Module.clock)
 
   protected def _pastClock(seq: Sequence, delay: Int, clock: Clock)(implicit sourceInfo: SourceInfo): Sequence =
     OpaqueSequence(LTLPastIntrinsic(delay, Some(clock))(seq.inner))
diff --git a/src/test/scala/chiselTests/LTLSpec.scala b/src/test/scala/chiselTests/LTLSpec.scala
index fa557b75070..2f600ed5f4c 100644
--- a/src/test/scala/chiselTests/LTLSpec.scala
+++ b/src/test/scala/chiselTests/LTLSpec.scala
@@ -75,15 +75,15 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselSim with FileCheck {
     ChiselStage.emitSystemVerilog(new DelaysMod)
   }
 
-  class PastMod extends RawModule {
+  class PastMod extends Module {
     implicit val info: SourceInfo = SourceLine("Foo.scala", 1, 2)
     val a, b = IO(Input(Bool()))
-    val clock = IO(Input(Clock()))
+    val myClock = IO(Input(Clock()))
     val s0: Sequence = a.past()
     val s1: Sequence = a.past(3)
     val s2: Sequence = Sequence.past(b, 2)
-    val s3: Sequence = a.past(clock)
-    val s4: Sequence = a.past(2, clock)
+    val s3: Sequence = a.past(myClock)
+    val s4: Sequence = a.past(2, myClock)
   }
   it should "support sequence past operations" in {
     val sourceLoc = "@[Foo.scala 1:2]"
@@ -92,12 +92,12 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselSim with FileCheck {
       .fileCheck()(
         s"""|CHECK: input a : UInt<1>
             |CHECK: input b : UInt<1>
-            |CHECK: input clock : Clock
-            |CHECK: intrinsic(circt_ltl_past<delay = 1> : UInt<1>, a) $sourceLoc
-            |CHECK: intrinsic(circt_ltl_past<delay = 3> : UInt<1>, a) $sourceLoc
-            |CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, b) $sourceLoc
+            |CHECK: input myClock : Clock
             |CHECK: intrinsic(circt_ltl_past<delay = 1> : UInt<1>, a, clock) $sourceLoc
-            |CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, a, clock) $sourceLoc
+            |CHECK: intrinsic(circt_ltl_past<delay = 3> : UInt<1>, a, clock) $sourceLoc
+            |CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, b, clock) $sourceLoc
+            |CHECK: intrinsic(circt_ltl_past<delay = 1> : UInt<1>, a, myClock) $sourceLoc
+            |CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, a, myClock) $sourceLoc
             |""".stripMargin
       )
   }