diff --git a/ALU.vhd b/ALU.vhd
new file mode 100644
index 0000000..9e3ee40
--- /dev/null
+++ b/ALU.vhd
@@ -0,0 +1,43 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   ALU.vhd
+-- Deskripsi        :   blok ALU
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY ALU IS
+PORT (
+	OPRND_1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1 
+	OPRND_2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
+	OP_SEL : IN std_logic; -- Operation Select
+	RESULT : OUT std_logic_vector (31 DOWNTO 0) -- Data Output
+);
+END ALU;
+
+ARCHITECTURE BEHAVIOUR of ALU IS
+COMPONENT CLA_32 IS
+PORT (
+		OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Operand 1
+		OPRND_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Operand 2
+		C_IN : IN STD_LOGIC; -- Carry In
+		RESULT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Result
+		C_OUT : OUT STD_LOGIC -- Overflow
+);
+END COMPONENT;
+
+BEGIN
+
+ALU_BLOCK: CLA_32
+				PORT MAP(OPRND_1 => OPRND_1,
+							OPRND_2 => OPRND_2,
+							C_IN	  => OP_SEL,
+							RESULT  => RESULT,
+							C_OUT	  => OPEN);
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/BR_INTERRUPT.vhd b/BR_INTERRUPT.vhd
new file mode 100644
index 0000000..43033fd
--- /dev/null
+++ b/BR_INTERRUPT.vhd
@@ -0,0 +1,28 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   BR_INTERRUPT.vhd
+-- Deskripsi        :   Blok kombinasional untuk selektor mux2to1 apabila branching
+
+LIBRARY ieee; 
+USE ieee.std_logic_1164.all; 
+USE ieee.numeric_std.all;
+
+ENTITY BR_INTERRUPT IS
+PORT(	sig_branch: IN STD_LOGIC;
+		sig_bne:		IN STD_LOGIC;
+		comp:			IN STD_LOGIC;
+		pc_sel:		OUT STD_LOGIC
+	);
+END BR_INTERRUPT;
+
+ARCHITECTURE BEHAVIOUR of BR_INTERRUPT IS
+BEGIN
+
+--Blok menentukan apakah PC dipilih target address atau hasil increment + 4
+pc_sel <= (sig_bne AND NOT(COMP)) OR (sig_branch AND COMP);
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/CU.vhd b/CU.vhd
new file mode 100644
index 0000000..08f5fd5
--- /dev/null
+++ b/CU.vhd
@@ -0,0 +1,175 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   CU.vhd
+-- Deskripsi        :   Implementasi blok Control Unit
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY cu IS
+PORT (
+			--INPUT
+			OP_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			FUNCT_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			--OUTPUT
+			Sig_Jmp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_Bne : OUT STD_LOGIC;
+			Sig_Branch : OUT STD_LOGIC;
+			Sig_MemtoReg : OUT STD_LOGIC;
+			Sig_MemRead : OUT STD_LOGIC;
+			Sig_MemWrite : OUT STD_LOGIC;
+			Sig_RegDest : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_RegWrite : OUT STD_LOGIC;
+			Sig_ALUSrc : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_ALUCtrl : OUT STD_LOGIC
+);
+END cu;
+
+ARCHITECTURE BEHAVIOURAL of cu IS
+SIGNAL JUMP: STD_LOGIC_VECTOR (1 DOWNTO 0);
+SIGNAL BNE:  STD_LOGIC;
+SIGNAL BRANCH: STD_LOGIC;
+SIGNAL MEMTOREG: STD_LOGIC;
+SIGNAL MEMREAD: STD_LOGIC;
+SIGNAL MEMWRITE: STD_LOGIC;
+SIGNAL REGDEST: STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL REGWRITE: STD_LOGIC;
+SIGNAL ALUSRC: STD_LOGIC_VECTOR (1 DOWNTO 0);
+SIGNAL ALUCTRL: STD_LOGIC;
+
+BEGIN
+--Kombinasional Output
+Sig_Jmp			<= 	JUMP;
+Sig_Bne			<= 	BNE;
+Sig_Branch		<= 	BRANCH;
+Sig_MemtoReg	<=		MEMTOREG;
+Sig_MemRead		<=		MEMREAD;
+Sig_MemWrite	<=		MEMWRITE;
+Sig_RegDest		<=		REGDEST;
+Sig_RegWrite	<=		REGWRITE;
+Sig_ALUSrc		<=		ALUSRC;
+Sig_ALUCtrl		<=		ALUCTRL;
+
+--Generate Sinyal Kontrol
+CONTROL:
+	PROCESS(OP_In, FUNCT_In)
+	BEGIN
+		IF ((OP_In = "000000") AND (FUNCT_In = "100000")) THEN --add
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "01";
+			REGWRITE <= '1';
+			ALUSRC <= "00";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "000000") AND (FUNCT_In = "100010")) THEN --sub
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "01";
+			REGWRITE <= '1';
+			ALUSRC <= "00";
+			ALUCTRL <= '1';
+		ELSIF ((OP_In = "000100")) THEN	--beq
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '1';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "--";
+			REGWRITE <= '0';
+			ALUSRC <= "--";
+			ALUCTRL <= '-';
+		ELSIF ((OP_In = "000101")) THEN --bne
+			JUMP <= "00";
+			BNE  <= '1';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "--";
+			REGWRITE <= '0';
+			ALUSRC <= "--";
+			ALUCTRL <= '-';
+		ELSIF ((OP_In = "001000")) THEN --addi
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '1';
+			ALUSRC <= "01";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "100011")) THEN --lw
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '1';
+			MEMREAD <= '1';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '1';
+			ALUSRC <= "01";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "101011")) THEN --sw
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '1';
+			REGDEST <= "00";
+			REGWRITE <= '0';
+			ALUSRC <= "01";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "000010")) THEN --jmp
+			JUMP <= "01";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "--";
+			REGWRITE <= '0';
+			ALUSRC <= "--";
+			ALUCTRL <= '-';
+		ELSIF ((OP_In = "000000")) THEN --nop
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '0';
+			ALUSRC <= "00";
+			ALUCTRL <= '0';
+		ELSE							--SUPAYA TIDAK ADA LATCH
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '0';
+			ALUSRC <= "00";
+			ALUCTRL <= '0';
+		END IF;
+	END PROCESS CONTROL;
+
+END BEHAVIOURAL;
\ No newline at end of file
diff --git a/Instruction_Memory.vhd b/Instruction_Memory.vhd
new file mode 100644
index 0000000..c43c866
--- /dev/null
+++ b/Instruction_Memory.vhd
@@ -0,0 +1,56 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   Instruction_Memory.vhd
+-- Deskripsi        :   Implementasi blok Instruction_Memory
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity Instruction_Memory is
+    Port ( addr  : in	STD_LOGIC_VECTOR (31 downto 0);
+			  clock : in	STD_LOGIC;
+			  reset : in	STD_LOGIC;
+           instr : out  STD_LOGIC_VECTOR (31 downto 0));
+end Instruction_Memory;
+
+architecture Behavioral of Instruction_Memory is
+type mem is array(0 to 255) of std_logic_vector(31 downto 0);
+signal memory : mem := (
+		x"20100013",x"1000fffb",x"ac040000",x"1000ffff",
+		x"20110015",x"00000013",x"00000000",x"00000000",
+		x"16530001",x"00000011",x"00000000",x"00000003",
+		x"00000000",x"00000072",x"00000098",x"00000020",
+		x"02119822",x"00000000",x"00000000",x"00000004",
+		x"22730000",x"00000000",x"00000000",x"00000000",
+		x"22140004",x"00000000",x"00000000",x"00000000",
+		x"ae910000",x"00000000",x"00000000",x"00000000",
+		x"8e950000",x"00000000",x"00000000",x"00000000",
+		x"02a0a820",x"00000000",x"00000000",x"00000000",
+		x"08000000",x"00000000",x"00000000",x"00000000",
+		x"00000000",x"00000000",x"00000000",x"00000000",
+		others => x"00000000"
+		);
+
+signal wire_in: STD_LOGIC_VECTOR(31 DOWNTO 0);
+--signal instr_read: STD_LOGIC_VECTOR (31 downto 0);
+
+begin
+
+--instr_read <= memory(to_integer(unsigned(ADDR)));
+wire_in <= addr;
+
+	process(clock, reset, addr, memory)
+	begin
+		if (reset = '1') then
+			instr <= (others => '0');
+		elsif (rising_edge(clock)) then
+			instr <= memory(to_integer(unsigned(wire_in)));
+		end if;
+	end process;
+	
+end Behavioral;
\ No newline at end of file
diff --git a/PC.vhd b/PC.vhd
new file mode 100644
index 0000000..f51064a
--- /dev/null
+++ b/PC.vhd
@@ -0,0 +1,39 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   PC.vhd
+-- Deskripsi        :   Implementasi blok Program Counter
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity PC is
+    Port ( clock:		in  STD_LOGIC;
+           PC_in:		in  STD_LOGIC_VECTOR(31 DOWNTO 0);
+           PC_out:	out STD_LOGIC_VECTOR (31 downto 0));
+end PC;
+
+architecture Behavioral of PC is
+SIGNAL wire_in:  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL wire_out: STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+
+BEGIN
+
+--Kombinasional
+	wire_in  <= PC_in;
+	PC_out	<= wire_out;
+
+	process(clock)
+	begin
+		if(rising_edge(clock)) then
+			wire_out <= wire_in;
+		end if;
+	end process;
+
+end Behavioral;
\ No newline at end of file
diff --git a/bus_merger.vhd b/bus_merger.vhd
new file mode 100644
index 0000000..15f1379
--- /dev/null
+++ b/bus_merger.vhd
@@ -0,0 +1,27 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   bus_merger.vhd
+-- Deskripsi        :   Implementasi blok bus_merger
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY bus_merger IS
+PORT (
+			DATA_IN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			DATA_IN2 : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
+			DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+);
+END bus_merger;
+
+ARCHITECTURE BEHAVIOURAL of bus_merger IS
+BEGIN
+
+DATA_OUT <= DATA_IN1 & DATA_IN2;
+
+END BEHAVIOURAL;
\ No newline at end of file
diff --git a/cla.vhd b/cla.vhd
new file mode 100644
index 0000000..6396a2e
--- /dev/null
+++ b/cla.vhd
@@ -0,0 +1,32 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   cla.vhd
+-- Deskripsi        :   Implementasi blok paling rendah dari Carry Lookahead Adder
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity cla is
+port (
+      P :      in std_logic_vector(3 downto 0);
+      G :      in std_logic_vector(3 downto 0);
+		cin :    in std_logic;
+      Cout :   out std_logic_vector(4 downto 0)
+     );
+end cla;
+
+architecture Behavioral of cla is
+BEGIN
+
+Cout(0) <= cin;
+Cout(1) <= G(0) or (P(0) and cin);
+Cout(2) <= G(1) or (P(1) and G(0)) or (P(1) and P(0) and cin);
+Cout(3) <= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0)) or (P(2) and P(1) and P(0) and cin);
+Cout(4) <= G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1)) or (P(3) and P(2) and P(1) and G(0)) or (P(3) and P(2) and P(1) and P(0) and cin);
+ 
+END Behavioral;
\ No newline at end of file
diff --git a/cla_32.vhd b/cla_32.vhd
new file mode 100644
index 0000000..2975147
--- /dev/null
+++ b/cla_32.vhd
@@ -0,0 +1,109 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   cla_32.vhd
+-- Deskripsi        :   Implementasi Top-level Untuk Carry-Lookahead Adder 32 bit
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY cla_32 IS
+PORT (
+		OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Operand 1
+		OPRND_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Operand 2
+		C_IN : IN STD_LOGIC; -- Carry In
+		RESULT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Result
+		C_OUT : OUT STD_LOGIC -- Overflow
+);
+END cla_32;
+
+ARCHITECTURE BEHAVIOUR of cla_32 IS
+SIGNAL wire0: STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
+signal complement1: STD_LOGIC_VECTOR(31 DOWNTO 0);
+COMPONENT CLA_8BIT IS
+PORT (
+			A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Operand 1
+			B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- Operand 2
+			C_IN : IN STD_LOGIC; -- Carry In
+			RESULT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Result
+			C_Out: OUT STD_LOGIC
+);
+END COMPONENT;
+
+BEGIN
+ONES: FOR i IN 0 TO 31 GENERATE
+		complement1(i) <= OPRND_2(i) xor C_IN;
+		END GENERATE;
+		
+wire0(0) <= C_IN;
+CLA_1: CLA_8BIT
+			port map(A => OPRND_1(3 DOWNTO 0),
+						B => complement1(3 DOWNTO 0),
+						C_IN => wire0(0),
+						RESULT => RESULT(3 DOWNTO 0),
+						C_Out => wire0(1)
+						);
+
+CLA_2: CLA_8BIT
+			port map(A => OPRND_1(7 DOWNTO 4),
+						B => complement1(7 DOWNTO 4),
+						C_IN => wire0(1),
+						RESULT => RESULT(7 DOWNTO 4),
+						C_Out => wire0(2)
+						);
+						
+CLA_3: CLA_8BIT
+			port map(A => OPRND_1(11 DOWNTO 8),
+						B => complement1(11 DOWNTO 8),
+						C_IN => wire0(2),
+						RESULT => RESULT(11 DOWNTO 8),
+						C_Out => wire0(3)
+						);
+						
+CLA_4: CLA_8BIT
+			port map(A => OPRND_1(15 DOWNTO 12),
+						B => complement1(15 DOWNTO 12),
+						C_IN => wire0(3),
+						RESULT => RESULT(15 DOWNTO 12),
+						C_Out => wire0(4)
+						);
+						
+CLA_5: CLA_8BIT
+			port map(A => OPRND_1(19 DOWNTO 16),
+						B => complement1(19 DOWNTO 16),
+						C_IN => wire0(4),
+						RESULT => RESULT(19 DOWNTO 16),
+						C_Out => wire0(5)
+						);
+						
+CLA_6: CLA_8BIT
+			port map(A => OPRND_1(23 DOWNTO 20),
+						B => complement1(23 DOWNTO 20),
+						C_IN => wire0(5),
+						RESULT => RESULT(23 DOWNTO 20),
+						C_Out => wire0(6)
+						);
+						
+CLA_7: CLA_8BIT
+			port map(A => OPRND_1(27 DOWNTO 24),
+						B => complement1(27 DOWNTO 24),
+						C_IN => wire0(6),
+						RESULT => RESULT(27 DOWNTO 24),
+						C_Out => wire0(7)
+						);
+						
+CLA_8: CLA_8BIT
+			port map(A => OPRND_1(31 DOWNTO 28),
+						B => complement1(31 DOWNTO 28),
+						C_IN => wire0(7),
+						RESULT => RESULT(31 DOWNTO 28),
+						C_Out => wire0(8)
+						);
+						
+C_OUT <= wire0(8);
+				
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/cla_8bit.vhd b/cla_8bit.vhd
new file mode 100644
index 0000000..309eeb8
--- /dev/null
+++ b/cla_8bit.vhd
@@ -0,0 +1,48 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   cla_8bit.vhd
+-- Deskripsi        :   Implementasi blok cla untuk 8 bit
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY cla_8bit IS --harusnya 4bit
+PORT (
+			A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Operand 1
+			B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- Operand 2
+			C_IN : IN STD_LOGIC; -- Carry In
+			RESULT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Result
+			C_Out: OUT STD_LOGIC
+);
+END cla_8bit;
+
+ARCHITECTURE BEHAVIOUR of cla_8bit IS
+signal P,G : STD_LOGIC_VECTOR(3 DOWNTO 0) :=  "0000";
+signal COUT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
+--signal complement1: STD_LOGIC_VECTOR(3 DOWNTO 0);
+component cla is
+port (
+      P :    in std_logic_vector(3 downto 0);
+      G :    in std_logic_vector(3 downto 0);
+		Cin :  in std_logic;
+      Cout : out std_logic_vector(4 downto 0)
+     );
+end component;
+
+BEGIN
+
+P <= A xor B;
+G <= A and B;
+
+CARRYLOOKAHEAD: cla
+					 port map(P=>P, G=>G, Cout=>COUT, Cin=>C_IN);
+
+RESULT <= P xor COUT(3 DOWNTO 0);
+C_Out <= COUT(4);
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/comparator.vhd b/comparator.vhd
new file mode 100644
index 0000000..9d04818
--- /dev/null
+++ b/comparator.vhd
@@ -0,0 +1,35 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   comparator.vhd
+-- Deskripsi        :   Implementasi blok comparator
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY comparator IS
+PORT (
+			D_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			D_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			EQ : OUT STD_LOGIC -- Hasil Perbandingan EQ
+);
+
+END comparator;
+
+ARCHITECTURE BEHAVIOUR of comparator IS
+BEGIN
+
+PROCESS (D_1, D_2)
+BEGIN
+	IF (D_1 = D_2) THEN
+		EQ <= '1';
+	ELSE
+		EQ <= '0';
+	END IF;
+END PROCESS;
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/data_memory.vhd b/data_memory.vhd
new file mode 100644
index 0000000..f4da276
--- /dev/null
+++ b/data_memory.vhd
@@ -0,0 +1,60 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   data_memory.vhd
+-- Deskripsi        :   Implementasi blok data_memory
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY data_memory IS
+PORT ( ADDR : 	IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- alamat
+		 WR_EN:	IN STD_LOGIC; --INDIKATOR PENULISAN
+		 RD_EN:	IN STD_LOGIC; --INDIKATOR PEMBACAAN
+		 clock : IN STD_LOGIC; -- clock 
+		 WR_DATA: IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- DATA YANG AKAN DIASSIGN KE MEMORY
+		 RD_DATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- VALUE MEMORY YANG DIBACA
+	  ); 
+
+END data_memory;
+
+ARCHITECTURE structural OF data_memory IS
+type mem is array(0 to 255) of std_logic_vector(31 downto 0);
+	signal memory : mem := (
+		x"00000000",x"8c010000",x"8c020004",x"8c030008",
+		x"00000000",x"00822020",x"0043282a",x"10a00002",
+		x"0000000a",x"1000fffb",x"ac040000",x"1000ffff",
+		x"00000020",x"00000013",x"00000000",x"00000000",
+		x"00000012",x"00000011",x"00000000",x"00000003",
+		x"00000002",x"00000072",x"00000098",x"00000020",
+		x"00000022",x"00000010",x"00000000",x"00000001",
+		x"00000008",x"00000000",x"00000000",x"00000004",
+		others => x"00000000"
+		);
+signal temp_rd_data: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+BEGIN
+--Kombinasional
+RD_DATA <= temp_rd_data;
+
+PROCESS (clock, wr_en, rd_en, addr, memory, wr_data)
+BEGIN
+	if (rising_edge(clock)) then
+				if ((WR_EN = '1') and (RD_EN = '0')) then
+					memory(to_integer(unsigned(ADDR))) <= WR_Data;
+				end if;
+	end if;
+	
+	if (falling_edge(clock)) then
+				if ((WR_EN = '0') and (RD_EN = '1')) then
+					temp_rd_data <= memory(to_integer(unsigned(ADDR)));
+				end if;
+	end if;
+	
+end PROCESS;
+
+END structural;
\ No newline at end of file
diff --git a/lshift_26_28.vhd b/lshift_26_28.vhd
new file mode 100644
index 0000000..8f977ea
--- /dev/null
+++ b/lshift_26_28.vhd
@@ -0,0 +1,26 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   lshift_26_28.vhd
+-- Deskripsi        :   Implementasi blok shifter 26 bit ke 28 bit
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY lshift_26_28 IS
+PORT (
+			D_IN : IN STD_LOGIC_VECTOR (25 DOWNTO 0); -- Input 26-bit;
+			D_OUT : OUT STD_LOGIC_VECTOR (27 DOWNTO 0) -- Output 28-bit;
+);
+END lshift_26_28;
+
+ARCHITECTURE BEHAVIOUR of lshift_26_28 IS
+BEGIN
+
+D_OUT <= STD_LOGIC_VECTOR(SHIFT_LEFT(UNSIGNED(("00" & D_IN)), 2));
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/lshift_32_32.vhd b/lshift_32_32.vhd
new file mode 100644
index 0000000..5a9631d
--- /dev/null
+++ b/lshift_32_32.vhd
@@ -0,0 +1,26 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   lshift_32_32.vhd
+-- Deskripsi        :   Implementasi blok shifter 32 bit ke 32 bit
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY lshift_32_32 IS
+PORT (
+			D_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Input 32-bit;
+			D_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- Output 32-bit;
+);
+END lshift_32_32;
+
+ARCHITECTURE BEHAVIOUR of lshift_32_32 IS
+BEGIN
+
+D_OUT <= STD_LOGIC_VECTOR(SHIFT_LEFT(UNSIGNED(D_IN), 2));
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/mips32.vhd b/mips32.vhd
new file mode 100644
index 0000000..d1432ba
--- /dev/null
+++ b/mips32.vhd
@@ -0,0 +1,424 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   MIPS32.vhd
+-- Deskripsi        :   TOP_LEVEL module
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY MIPS32 IS
+PORT (	CLK: IN STD_LOGIC;
+			RST: IN STD_LOGIC;
+			pcin: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			JumpCU: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			bneCU:  OUT STD_LOGIC;
+			branchCU:	OUT STD_LOGIC;
+			memtoregCU:	OUT STD_LOGIC;
+			memreadCU:	OUT STD_LOGIC;
+			memwriteCU:	OUT STD_LOGIC;
+			regdestCU:	OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			regwriteCU:	OUT STD_LOGIC;
+			ALUSrcCU:	OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			ALUCtrl:		OUT STD_LOGIC;
+			ProgramCounter: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			PChasilInkremen: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			Instruksi:  OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			DestinationReg: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+			Nilai_Rs:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			Nilai_Rt:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			HasilKomparasi: OUT STD_LOGIC;
+			HasilALU: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			MuxyangMaukeALU: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			BacaanMemori: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			WriteBack:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			AlamatBNE: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			busmerge_out: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			branch_detector: OUT STD_LOGIC;
+			bit_OP_In: OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+			bit_Funct: OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+			bit_addr_1: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+			bit_addr_2: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+			bit_SignExt: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+			bit_shift26_28: OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
+	  );
+END MIPS32;
+
+
+ARCHITECTURE TOP_LEVEL of MIPS32 IS
+COMPONENT mux_2to1_32bit IS --MUX
+PORT (
+			D1 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D2 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			SEL:	IN			STD_LOGIC;
+			Y	:	OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 );
+END COMPONENT;
+
+COMPONENT mux_4to1_32bit IS --MUX
+PORT (
+			D1 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D2 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D3 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D4 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			SEL:	IN			STD_LOGIC_VECTOR(1  DOWNTO 0);
+			Y	:	OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 );
+
+END COMPONENT;
+
+COMPONENT mux_4to1_5bit IS --MUX
+PORT (
+			D1 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 1 
+			D2 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 2 
+			D3 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 3 
+			D4 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 4
+			SEL : IN std_logic_vector  (1 DOWNTO 0); -- Selector
+			Y :  OUT std_logic_vector (4 DOWNTO 0)  -- Selected Data
+	 );
+
+END COMPONENT;
+
+COMPONENT PC IS --PROGRAM COUNTER
+Port ( 	  clock:		in  STD_LOGIC;
+           PC_in:		in  STD_LOGIC_VECTOR(31 DOWNTO 0);
+           PC_out:	out STD_LOGIC_VECTOR (31 downto 0));
+end COMPONENT;
+
+COMPONENT Instruction_Memory IS --INSTRUCTION MEMORY
+Port ( 	  addr  : in	STD_LOGIC_VECTOR (31 downto 0);
+			  clock : in	STD_LOGIC;
+			  reset : in	STD_LOGIC;
+           instr : out  STD_LOGIC_VECTOR (31 downto 0));
+end COMPONENT;
+
+COMPONENT cla_32 IS --ADDER 32 BIT
+PORT (
+		OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Operand 1
+		OPRND_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Operand 2
+		C_IN : IN STD_LOGIC; -- Carry In
+		RESULT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Result
+		C_OUT : OUT STD_LOGIC -- Overflow
+);
+END COMPONENT;
+
+COMPONENT reg_file IS
+PORT ( ADDR1 : 	 IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- REGISTER Rs
+		 ADDR2 : 	 IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- REGISTER Rt
+		 ADDR3 : 	 IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- REGISTER Rd
+		 WR_EN:		 IN STD_LOGIC; --INDIKATOR PENULISAN
+		 clock : 	 IN STD_LOGIC; -- clock 
+		 WR_Data_3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);-- write data
+		 RD_DATA_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- READ DATA1
+		 RD_DATA_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- READ DATA2
+	  );
+END COMPONENT;
+
+COMPONENT CU IS
+PORT (
+			--INPUT
+			OP_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			FUNCT_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			--OUTPUT
+			Sig_Jmp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_Bne : OUT STD_LOGIC;
+			Sig_Branch : OUT STD_LOGIC;
+			Sig_MemtoReg : OUT STD_LOGIC;
+			Sig_MemRead : OUT STD_LOGIC;
+			Sig_MemWrite : OUT STD_LOGIC;
+			Sig_RegDest : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_RegWrite : OUT STD_LOGIC;
+			Sig_ALUSrc : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_ALUCtrl : OUT STD_LOGIC
+);
+END COMPONENT;
+
+COMPONENT sign_extender IS
+PORT (
+			D_In :IN std_logic_vector (15 DOWNTO 0); -- Data Input 1 
+			D_Out :OUT std_logic_vector (31 DOWNTO 0) -- Data Input 2
+);
+END COMPONENT;
+
+COMPONENT lshift_26_28 IS
+PORT (
+			D_IN : IN STD_LOGIC_VECTOR (25 DOWNTO 0); -- Input 32-bit;
+			D_OUT : OUT STD_LOGIC_VECTOR (27 DOWNTO 0) -- Output 32-bit;
+);
+END COMPONENT;
+
+COMPONENT lshift_32_32 IS
+PORT (
+			D_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Input 32-bit;
+			D_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- Output 32-bit;
+);
+END COMPONENT;
+
+COMPONENT bus_merger IS
+PORT (
+			DATA_IN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			DATA_IN2 : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
+			DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+);
+END COMPONENT;
+
+COMPONENT COMPARATOR IS
+PORT (
+			D_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			D_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			EQ : OUT STD_LOGIC -- Hasil Perbandingan EQ
+);
+
+END COMPONENT;
+
+COMPONENT ALU IS
+PORT (
+	OPRND_1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1 
+	OPRND_2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
+	OP_SEL : IN std_logic; -- Operation Select
+	RESULT : OUT std_logic_vector (31 DOWNTO 0) -- Data Output
+);
+END COMPONENT;
+
+COMPONENT data_memory IS
+PORT ( ADDR : 	IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- alamat
+		 WR_EN:	IN STD_LOGIC; --INDIKATOR PENULISAN
+		 RD_EN:	IN STD_LOGIC; --INDIKATOR PEMBACAAN
+		 clock : IN STD_LOGIC; -- clock 
+		 WR_DATA: IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- DATA YANG AKAN DIASSIGN KE MEMORY
+		 RD_DATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- VALUE MEMORY YANG DIBACA
+	  ); 
+
+END COMPONENT;
+
+COMPONENT BR_INTERRUPT IS
+PORT(	sig_branch: IN STD_LOGIC;
+		sig_bne:		IN STD_LOGIC;
+		comp:			IN STD_LOGIC;
+		pc_sel:		OUT STD_LOGIC
+	);
+END COMPONENT;
+--WIRES
+signal mux2to1_mux4to1: STD_LOGIC_VECTOR (31 DOWNTO 0);
+signal mux4to1_reset:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+--RESET
+signal reset_PC:			STD_LOGIC_VECTOR (31 DOWNTO 0);
+--Output dari PC
+signal wirePCout:			STD_LOGIC_VECTOR (31 DOWNTO 0);
+--Output dari Instruction Memory
+signal wireInstr:			STD_LOGIC_VECTOR (31 DOWNTO 0);
+--Output dari Adder Increment PC
+signal wirePCincrement:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+--wire dari blok CU
+signal wirejump:			STD_LOGIC_VECTOR (1  DOWNTO 0);
+signal wirebne:			STD_LOGIC;
+signal wirebranch:		STD_LOGIC;
+signal wirememtoreg:		STD_LOGIC;
+signal wirememread:		STD_LOGIC;
+signal wirememwrite:		STD_LOGIC;
+signal wireregdest:		STD_LOGIC_VECTOR (1  DOWNTO 0);
+signal wireregwrite:		STD_LOGIC;
+signal wireALUSrc:		STD_LOGIC_VECTOR (1  DOWNTO 0);
+signal wireALUCtrl:		STD_LOGIC;
+--wire dari blok Register
+signal wirereadData1:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+signal wirereadData2:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+--wire dari mux selecting destination register
+signal mux4to1_addr3:	STD_LOGIC_VECTOR (4 DOWNTO 0);
+--wire dari blok Sign Extender
+signal wiresignextend:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+--output dari blok left shifter 26 bit to 28 bit
+signal shft28_busmerge:	STD_LOGIC_VECTOR (27 DOWNTO 0);
+--output dari bus merge ke mux4to1
+signal busmerge_mux4to1:STD_LOGIC_VECTOR (31 DOWNTO 0);
+--wire dari comparator
+signal wirecomp:			STD_LOGIC;
+--wire dari mux4to1 ke ALU
+signal mux4to1_ALU:		STD_LOGIC_VECTOR (31 DOWNTO 0);
+--wire dari blok ALU
+signal wireALU:			STD_LOGIC_VECTOR (31 DOWNTO 0);
+--output dari blok left shifter 32 bit to 32 bit
+signal shft32_adder:		STD_LOGIC_VECTOR (31 DOWNTO 0);
+--output dari RD_DATA memory ke MUX2to1
+signal wireDatafromMem:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+--output dari blok branch interrupt
+signal wireBRinterr:		STD_LOGIC;
+--wire dari mux2to1 ke writedata Register
+signal mux2to1_WriteReg:STD_LOGIC_VECTOR (31 DOWNTO 0);
+--output dari adder untuk instruksi Jump
+signal Adder_mux2to1:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+BEGIN
+
+jumpCU     <= wirejump;
+bneCU      <= wirebne;
+branchCU   <= wirebranch;
+memtoregCU <= wirememtoreg;
+memreadCU  <= wirememread;
+memwriteCU <= wirememwrite;
+regdestCU  <= wireregdest;
+regwriteCU <= wireregwrite;
+ALUSrcCU   <= wireALUSrc;
+ALUCtrl    <= wireALUCtrl;
+
+pcin <= reset_PC;
+ProgramCounter <= wirePCout;
+PChasilInkremen <= wirePCincrement;
+Instruksi <= wireInstr;
+DestinationReg <= mux4to1_addr3;
+Nilai_Rs <= wirereadData1;
+Nilai_Rt <= wirereadData2;
+HasilKomparasi <= wirecomp;
+HasilALU <= wireALU;
+MuxyangMaukeALU <= mux4to1_ALU;
+BacaanMemori <= wireDatafromMem;
+WriteBack <= mux2to1_WriteReg;
+AlamatBNE <= Adder_mux2to1;
+busmerge_out <= busmerge_mux4to1;
+branch_detector <= wireBRinterr;
+bit_OP_In <= wireInstr(31 downto 26);
+bit_Funct <= wireInstr(5 downto 0);
+bit_addr_1 <= wireInstr(25 downto 21);
+bit_addr_2 <= wireInstr(20 downto 16);
+bit_SignExt <= wireInstr(15 downto 0);
+bit_shift26_28 <= wireInstr(25 downto 0);
+
+
+
+MUX2TO1_reset: mux_2to1_32bit
+						PORT MAP( D1	=>	mux4to1_reset,
+									 D2	=>	x"00000000",
+									 SEL	=>	RST,
+									 Y		=>	reset_PC);
+
+MUX2TO1_A: mux_2to1_32bit
+						PORT MAP( D1	=>	wirePCincrement,
+									 D2	=>	Adder_mux2to1,
+									 SEL	=>	wireBRinterr,
+									 Y		=>	mux2to1_mux4to1);
+
+MUX4TO1_A: mux_4to1_32bit
+						PORT MAP( D1	=>	mux2to1_mux4to1,
+									 D2	=>	busmerge_mux4to1,
+									 D3	=>	(OTHERS => '0'),
+									 D4	=>	(OTHERS => '0'),
+									 SEL	=>	wirejump,
+									 Y		=>	mux4to1_reset);
+
+PROGRAM_COUNTER:	PC
+						PORT MAP( CLOCK  => CLK,
+									 PC_In  => reset_PC,
+									 PC_Out => wirePCout);
+								
+INSTRUCT_MEMORY: Instruction_Memory
+							PORT MAP( ADDR	 => wirePCout,
+										 CLOCK => CLK,
+										 RESET => RST,
+										 INSTR => wireInstr);
+
+PC_INCREMENT:	CLA_32
+					PORT MAP( OPRND_1	=> wirePCout,
+								 OPRND_2	=>	X"00000004",
+								 C_IN		=>	'0',
+								 RESULT	=>	wirePCincrement,
+								 C_OUT	=>	OPEN);
+
+CONTROL_UNIT: CU
+					PORT MAP( OP_In			=>	wireInstr(31 DOWNTO 26),
+								 FUNCT_In		=>	wireInstr(5  DOWNTO  0),
+								 Sig_Jmp			=> wirejump,
+								 Sig_Bne			=> wirebne,
+								 Sig_Branch		=> wirebranch,
+								 Sig_MemtoReg	=> wirememtoreg,
+								 Sig_MemRead 	=> wirememread,
+								 Sig_MemWrite	=> wirememwrite,
+								 Sig_RegDest	=>	wireregdest,
+								 Sig_RegWrite	=> wireregwrite,
+								 Sig_ALUSrc		=>	wireALUSrc,
+								 Sig_ALUCtrL	=> wireALUCtrl);
+
+REGISTER_FILES:	REG_FILE
+						PORT MAP( ADDR1		=>	wireInstr(25 DOWNTO 21),
+									 ADDR2		=>	wireInstr(20 DOWNTO 16),
+									 ADDR3		=>	mux4to1_addr3,
+									 WR_EN		=>	wireregwrite,
+									 CLOCK		=> CLK,
+									 WR_Data_3	=>	mux2to1_WriteReg,
+									 RD_DATA_1	=> wirereadData1,
+									 RD_DATA_2	=>	wirereadData2);
+									 
+MUX4TO1_B:	mux_4to1_5bit
+				PORT MAP( D1	=>	wireInstr(20 DOWNTO 16),
+							 D2	=>	wireInstr(15 DOWNTO 11),
+							 D3	=>	(OTHERS => '0'),
+							 D4	=>	(OTHERS => '0'),
+							 SEL	=>	wireregdest,
+							 Y		=>	mux4to1_addr3);
+
+SIGN_EXTENDED:	SIGN_EXTENDER
+					PORT MAP( D_In		=>	wireInstr(15 DOWNTO 0),
+								 D_Out	=>	wiresignextend);
+
+LEFT_SHIFTER_26_28:	LSHIFT_26_28
+							PORT MAP( D_IN		=>	wireInstr(25 DOWNTO 0),
+										 D_OUT	=>	shft28_busmerge);
+
+BUS_MERGE:	BUS_MERGER
+				PORT MAP( DATA_IN1	=>	wirePCincrement(31 DOWNTO 28),
+							 DATA_IN2	=>	shft28_busmerge,
+							 DATA_OUT	=>	busmerge_mux4to1);
+
+MUX4TO1_C:	 mux_4to1_32bit
+						PORT MAP( D1	=>	wirereadData2,
+									 D2	=>	wiresignextend,
+									 D3	=>	(OTHERS => '0'),
+									 D4	=>	(OTHERS => '0'),
+									 SEL	=>	wireALUSrc,
+									 Y		=>	mux4to1_ALU);
+										
+COMPARATOR_BLOCK:	COMPARATOR
+							PORT MAP( D_1	=>	wirereadData1,
+										 D_2	=>	wirereadData2,
+										 EQ	=>	wirecomp);
+
+ALU_BLOCK:	ALU
+				PORT MAP( OPRND_1	=> wirereadData1,
+							 OPRND_2	=>	mux4to1_ALU,
+							 OP_SEL	=>	wireALUCtrl,
+							 RESULT	=>	wireALU);
+
+LEFT_SHIFTER_23_32:	LSHIFT_32_32
+							PORT MAP( D_IN		=>	wiresignextend,
+										 D_OUT	=> shft32_adder);
+
+BRANCH_ADDRESS_ADDER:	CLA_32
+								PORT MAP( OPRND_1	=> shft32_adder,
+											 OPRND_2	=>	wirePCincrement,
+											 C_IN		=>	'0',
+											 RESULT	=>	Adder_mux2to1,
+											 C_OUT	=>	OPEN);
+
+BRANCH_TEST: BR_INTERRUPT
+					PORT MAP( sig_branch	=>	wirebranch,
+								 sig_bne		=>	wirebne,
+								 comp			=>	wirecomp,
+								 pc_sel		=>	wireBRinterr);
+								 
+MEMORY_FILES:	DATA_MEMORY
+					 PORT MAP( ADDR		=>	wireALU,
+								  WR_EN		=>	wirememwrite,
+								  RD_EN		=> wirememread,
+								  CLOCK		=> CLK,
+								  WR_DATA	=>	wirereadData2,
+								  RD_DATA	=>	wireDatafromMem);
+								  
+MUX2TO1_B:	mux_2to1_32bit
+				 PORT MAP( D1	=>	wireALU,
+							  D2	=>	wireDatafromMem,
+							  SEL	=>	wirememtoreg,
+							  Y	=>	mux2to1_WriteReg);
+END TOP_LEVEL;
\ No newline at end of file
diff --git a/mux_2to1_32bit.vhd b/mux_2to1_32bit.vhd
new file mode 100644
index 0000000..17dcd23
--- /dev/null
+++ b/mux_2to1_32bit.vhd
@@ -0,0 +1,32 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   mux_2to1_32bit.vhd
+-- Deskripsi        :   Implementasi blok mux_2to1 untuk 32 bits wide data
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY mux_2to1_32bit IS
+PORT (
+			D1 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D2 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			SEL:	IN			STD_LOGIC;
+			Y	:	OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 );
+
+END mux_2to1_32bit;
+
+ARCHITECTURE BEHAVIOURAL of mux_2to1_32bit IS
+
+BEGIN
+
+Y <= D1 WHEN (SEL = '0') ELSE
+	  D2 WHEN (SEL = '1') ELSE
+	  D1;
+
+END BEHAVIOURAL;
\ No newline at end of file
diff --git a/mux_4to1_32bit.vhd b/mux_4to1_32bit.vhd
new file mode 100644
index 0000000..e4b4382
--- /dev/null
+++ b/mux_4to1_32bit.vhd
@@ -0,0 +1,36 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   mux_4to1_32bit.vhd
+-- Deskripsi        :   Implementasi blok mux_4to1 untuk 32 bits wide data
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY mux_4to1_32bit IS
+PORT (
+			D1 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D2 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D3 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			D4 :	IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			SEL:	IN			STD_LOGIC_VECTOR(1  DOWNTO 0);
+			Y	:	OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 );
+
+END mux_4to1_32bit;
+
+ARCHITECTURE BEHAVIOURAL of mux_4to1_32bit IS
+
+BEGIN
+
+Y <= D1 WHEN (SEL = "00") ELSE
+	  D2 WHEN (SEL = "01") ELSE
+	  D3 WHEN (SEL = "10") ELSE
+	  D4 WHEN (SEL = "11") ELSE
+	  D1;
+
+END BEHAVIOURAL;
\ No newline at end of file
diff --git a/mux_4to1_5bit.vhd b/mux_4to1_5bit.vhd
new file mode 100644
index 0000000..ca9a452
--- /dev/null
+++ b/mux_4to1_5bit.vhd
@@ -0,0 +1,38 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   mux_4to1_5bit.vhd
+-- Deskripsi        :   Implementasi blok mux_4to1 untuk 5 bits wide data
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+ENTITY mux_4to1_5bit IS
+PORT (
+			D1 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 1 
+			D2 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 2 
+			D3 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 3 
+			D4 :  IN std_logic_vector (4 DOWNTO 0); -- Data Input 4
+			SEL : IN std_logic_vector  (1 DOWNTO 0); -- Selector
+			Y :  OUT std_logic_vector (4 DOWNTO 0)  -- Selected Data
+	 );
+
+END mux_4to1_5bit;
+
+
+ARCHITECTURE BEHAVIOUR of mux_4to1_5bit IS
+
+BEGIN
+
+Y <= D1 WHEN (SEL = "00") ELSE
+	  D2 WHEN (SEL = "01") ELSE
+	  D3 WHEN (SEL = "10") ELSE
+	  D4 WHEN (SEL = "11") ELSE
+	  D1;
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/reg_file.vhd b/reg_file.vhd
new file mode 100644
index 0000000..16f53d4
--- /dev/null
+++ b/reg_file.vhd
@@ -0,0 +1,68 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul			:	5
+-- Percobaan		:	1 dan 2
+-- Tanggal			:	25 November 2021
+-- Rombongan		:	A
+-- Nama (NIM)		:	Christian Reivan (13219005)
+-- Nama File		:	reg_file.vhd
+-- Deskripsi		:	Implementasi Register
+
+LIBRARY ieee; 
+USE ieee.std_logic_1164.all; 
+USE ieee.numeric_std.all;
+
+ENTITY REG_FILE IS 
+PORT ( ADDR1 : 	 IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- REGISTER Rs
+		 ADDR2 : 	 IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- REGISTER Rt
+		 ADDR3 : 	 IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- REGISTER Rd
+		 WR_EN:		 IN STD_LOGIC; --INDIKATOR PENULISAN
+		 clock : 	 IN STD_LOGIC; -- clock 
+		 WR_Data_3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);-- write data
+		 RD_DATA_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- READ DATA1
+		 RD_DATA_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- READ DATA2
+	  ); 
+
+END ENTITY;
+
+ARCHITECTURE structural OF REG_FILE IS
+TYPE ramtype IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL mem: ramtype := (
+   x"00000000", x"8c030001", x"00430820", x"ac010003",	--r0, at, v0, v1
+   x"1022ffff", x"1021fffa", x"0043282a", x"10a00002", 	--a0, a1, a2, a3
+   x"1000fffb", x"ac040000", x"1000ffff", x"00000000",	--t0, t1, t2, t3
+   x"00000000", x"00000004", x"00000008", x"00000000",	--t4, t5, t6, t7
+   x"00000000", x"00000000", x"00000000", x"00000000",	--s0, s1, s2, s3
+   x"00000000", x"00000000", x"00000000", x"00000000",	--s4, s5, s6, s7
+   x"00000000", x"00000000", x"00000000", x"00000000",	--t8, t9, k0, k1
+   x"00000000", x"00000000", x"00000000", x"00000000"		--gp, sp, s8, ra
+   );
+SIGNAL rd_data1: STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL rd_data2: STD_LOGIC_VECTOR(31 DOWNTO 0);
+--SIGNAL address1: STD_LOGIC_VECTOR(4  DOWNTO 0);
+--SIGNAL address2: STD_LOGIC_VECTOR(4  DOWNTO 0);
+
+BEGIN
+-- Blok Kombinasional
+RD_DATA_1 <= rd_data1;
+RD_DATA_2 <= rd_data2;
+--address1 <= ADDR1;
+--address2 <= ADDR2;
+
+PROCESS (CLOCK, ADDR1, ADDR2, ADDR3, WR_EN, MEM, WR_Data_3)
+BEGIN
+			if (rising_edge(clock)) then
+				if (WR_EN = '1') then
+					if (addr3 /= "00000") then
+						mem(to_integer(unsigned(ADDR3))) <= WR_Data_3;
+					end if;
+				end if;
+			end if;
+			
+			if (falling_edge(clock)) then
+					rd_data1 <= mem(to_integer(unsigned(ADDR1)));
+					rd_data2 <= mem(to_integer(unsigned(ADDR2)));
+			end if;
+			
+end process;
+		
+END structural;
\ No newline at end of file
diff --git a/sign_extender.vhd b/sign_extender.vhd
new file mode 100644
index 0000000..3f6d253
--- /dev/null
+++ b/sign_extender.vhd
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY sign_extender IS
+PORT (
+			D_In :IN std_logic_vector (15 DOWNTO 0); -- Data Input 1 
+			D_Out :OUT std_logic_vector (31 DOWNTO 0) -- Data Input 2
+);
+END sign_extender;
+
+ARCHITECTURE BEHAVIOUR of sign_extender IS
+SIGNAL trailing: unsigned (15 DOWNTO 0);
+BEGIN
+
+trailing <= (OTHERS => D_In(15));
+
+D_Out <= std_logic_vector(trailing & unsigned(D_In));
+
+
+END BEHAVIOUR;
\ No newline at end of file
diff --git a/testbench.vhd b/testbench.vhd
new file mode 100644
index 0000000..9f15cdb
--- /dev/null
+++ b/testbench.vhd
@@ -0,0 +1,137 @@
+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   testbench.vhd
+-- Deskripsi        :   testbench untuk top-level
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity testbench is
+end testbench;
+
+architecture structural of testbench is
+component mips32 is
+PORT (	CLK: IN STD_LOGIC;
+			RST: IN STD_LOGIC;
+			pcin: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			JumpCU: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			bneCU:  OUT STD_LOGIC;
+			branchCU:	OUT STD_LOGIC;
+			memtoregCU:	OUT STD_LOGIC;
+			memreadCU:	OUT STD_LOGIC;
+			memwriteCU:	OUT STD_LOGIC;
+			regdestCU:	OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			regwriteCU:	OUT STD_LOGIC;
+			ALUSrcCU:	OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			ALUCtrl:		OUT STD_LOGIC;
+			ProgramCounter: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			PChasilInkremen: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			Instruksi:  OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			DestinationReg: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+			Nilai_Rs:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			Nilai_Rt:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			HasilKomparasi: OUT STD_LOGIC;
+			HasilALU: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			MuxyangMaukeALU: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			BacaanMemori: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			WriteBack:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			AlamatBNE: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			busmerge_out: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			branch_detector: OUT STD_LOGIC;
+			bit_OP_In: OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+			bit_Funct: OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+			bit_addr_1: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+			bit_addr_2: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+			bit_SignExt: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+			bit_shift26_28: OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
+	  );
+END COMPONENT;
+
+signal tb_clock: std_logic := '0';
+signal tb_reset: std_logic := '1';
+signal tb_pcin: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_jump_cu: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal tb_bne_cu: std_logic;
+signal tb_branch_cu: STD_LOGIC;
+signal tb_memtoregCU: STD_LOGIC;
+signal tb_memreadCU: STD_LOGIC;
+signal tb_memwriteCU: STD_LOGIC;
+signal tb_regdestCU: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal tb_regwriteCU: STD_LOGIC;
+signal tb_ALUSrcCU: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal tb_ALUCtrl:STD_LOGIC;
+signal tb_ProgramCounter:STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_PChasilInkremen:STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_instruksi: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_DestinationReg: STD_LOGIC_VECTOR(4 DOWNTO 0);
+signal tb_Nilai_Rs: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_Nilai_Rt: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_HasilKomparasi: STD_LOGIC;
+signal tb_HasilAlu: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_MuxyangMaukeALU: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_BacaanMemori: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_WriteBack: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_AlamatBNE: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_busmerge_out: STD_LOGIC_VECTOR(31 DOWNTO 0);
+signal tb_branch_detector: STD_LOGIC;
+signal tb_bit_OP_In: STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal tb_bit_Funct: STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal tb_bit_addr_1: STD_LOGIC_VECTOR(4 DOWNTO 0);
+signal tb_bit_addr_2: STD_LOGIC_VECTOR(4 DOWNTO 0);
+signal tb_bit_SignExt: STD_LOGIC_VECTOR(15 DOWNTO 0);
+signal tb_bit_shift26_28: STD_LOGIC_VECTOR(25 DOWNTO 0);
+
+BEGIN
+
+dut: mips32
+     port map(	 CLK						=> tb_clock,
+					 RST                 => tb_reset,
+                pcin                => tb_pcin,
+                JumpCU              => tb_jump_cu,
+                bneCU               => tb_bne_cu,
+                branchCU            => tb_branch_cu,
+                memtoregCU          => tb_memtoregCU,
+                memreadCU           => tb_memreadCU,
+                memwriteCU          => tb_memwriteCU,
+                regdestCU           => tb_regdestCU,
+                regwriteCU          => tb_regwriteCU,
+                ALUSrcCU            => tb_ALUSrcCU,
+                ALUCtrl             => tb_ALUCtrl,
+                ProgramCounter      => tb_ProgramCounter,
+                PChasilInkremen     => tb_PChasilInkremen,
+                Instruksi           => tb_instruksi,
+                DestinationReg      => tb_DestinationReg,
+                Nilai_Rs            => tb_Nilai_Rs,
+                Nilai_Rt            => tb_Nilai_Rt,
+                HasilKomparasi      => tb_HasilKomparasi,
+                HasilALU            => tb_HasilAlu,
+                MuxyangMaukeALU     => tb_MuxyangMaukeALU,
+                BacaanMemori        => tb_BacaanMemori,
+                WriteBack           => tb_WriteBack,
+                AlamatBNE           => tb_AlamatBNE,
+                busmerge_out        => tb_busmerge_out,
+                branch_detector     => tb_branch_detector,
+                bit_OP_In           => tb_bit_OP_In,
+                bit_Funct           => tb_bit_Funct,
+                bit_addr_1          => tb_bit_addr_1,
+                bit_addr_2          => tb_bit_addr_2,
+                bit_SignExt         => tb_bit_SignExt,
+                bit_shift26_28      =>  tb_bit_shift26_28
+);
+
+MY_CLOCK: PROCESS
+          BEGIN
+            WAIT FOR 10 ps; tb_clock <= NOT(tb_clock);
+          END PROCESS MY_CLOCK;
+
+MY_RESET: PROCESS
+          BEGIN
+            WAIT FOR 40 ps; tb_reset <= '0';
+			 END PROCESS MY_RESET;
+
+end structural;
\ No newline at end of file