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This repository has been archived by the owner on Sep 7, 2018. It is now read-only.
@tomjaguarpaw what kind of VHDL/Verilog do you expect CLaSH to output given the following Haskell code?:
topEntity::BitVector0->BitVector0
topEntity =id
An entity with 1 input port and 1 output port, both of width 0? Or, an entity without input or output ports?
I'm asking, because VHDL/Verilog synthesis tools loudly complain about things that are 0-bit wide. So if you expect the entity to have an input and an output port, then the instance should be:
There should be
I know this seems trivial but it's going to be needed by someone sooner or later (probably because they are generating code).
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