diff --git a/cabal.project b/cabal.project
index 7dcd22a..7a41efc 100644
--- a/cabal.project
+++ b/cabal.project
@@ -52,7 +52,14 @@ source-repository-package
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-protocols.git
-  tag: eb76cd1be746ae91beff60c0f16d8c1dd888662c
+  tag: 0832a422e77422739401896f6612620d17baa289
+  subdir: clash-protocols
+
+source-repository-package
+  type: git
+  location: https://github.com/clash-lang/clash-protocols.git
+  tag: 0832a422e77422739401896f6612620d17baa289
+  subdir: clash-protocols-base
 
 source-repository-package
   type: git
diff --git a/clash-vexriscv/src/VexRiscv.hs b/clash-vexriscv/src/VexRiscv.hs
index 7aab01c..edd6f2e 100644
--- a/clash-vexriscv/src/VexRiscv.hs
+++ b/clash-vexriscv/src/VexRiscv.hs
@@ -27,6 +27,7 @@ import GHC.IO (unsafePerformIO, unsafeInterleaveIO)
 import GHC.Stack (HasCallStack)
 import Language.Haskell.TH.Syntax
 import Protocols
+import Protocols.Idle
 import Protocols.Wishbone
 
 import VexRiscv.ClockTicks
@@ -72,6 +73,10 @@ instance Protocol (Jtag dom) where
   type Fwd (Jtag dom) = Signal dom JtagIn
   type Bwd (Jtag dom) = Signal dom JtagOut
 
+instance IdleCircuit (Jtag dom) where
+  idleFwd _ = pure $ JtagIn 0 0 0
+  idleBwd _ = pure $ JtagOut 0 0
+
 vexRiscv ::
   forall dom .
   ( HasCallStack