Makefile

test::
test_post::
syn::

testdata32.hex: testdata
	./testdata

testdata32g.hex: testdata32.hex
testdata32go.hex: testdata32.hex
testdata64.hex: testdata32.hex
testdata64g.hex: testdata32.hex
testdata64go.hex: testdata32.hex

testdata: testdata.cc
	clang++ -std=c++11 -Wall -O -ggdb -o $@ $^

bextdep_pps.v: ppsmaker.py
	echo "// DO NOT EDIT -- Generated by ppsmaker.py (see Makefile)" > bextdep_pps.v.new
	python3 ppsmaker.py    -i 1 -o 8 -n 4  -m bextdep_pps4   >> bextdep_pps.v.new
	python3 ppsmaker.py    -i 1 -o 8 -n 8  -m bextdep_pps8   >> bextdep_pps.v.new
	python3 ppsmaker.py    -i 1 -o 8 -n 16 -m bextdep_pps16  >> bextdep_pps.v.new
	python3 ppsmaker.py    -i 1 -o 8 -n 32 -m bextdep_pps32  >> bextdep_pps.v.new
	python3 ppsmaker.py    -i 1 -o 8 -n 64 -m bextdep_pps64  >> bextdep_pps.v.new
	python3 ppsmaker.py -f -i 1 -o 8 -n 32 -m bextdep_pps32f >> bextdep_pps.v.new
	python3 ppsmaker.py -f -i 1 -o 8 -n 64 -m bextdep_pps64f >> bextdep_pps.v.new
	mv bextdep_pps.v.new bextdep_pps.v

report: vscalealu32.rpt vscalealu64.rpt vscalealu64.vivlog vscalealu32.vivlog tinyrocket-src/OK
	python3 report.py

vscalealu64.rpt: vscalealu.v
	yosys -p "read_verilog vscalealu.v; synth -flatten -top vscalealu64" \
		-p "rename -hide; abc -dff -g cmos2; opt -fast" \
		-p "tee -o vscalealu64.rpt stat; tee -a vscalealu64.rpt ltp -noff"

vscalealu32.rpt: vscalealu.v
	yosys -p "read_verilog vscalealu.v; synth -flatten -top vscalealu32" \
		-p "rename -hide; abc -dff -g cmos2; opt -fast" \
		-p "tee -o vscalealu32.rpt stat; tee -a vscalealu32.rpt ltp -noff"

vscalealu64.vivlog: vscalealu.v bextdep.v bextdep_pps.v vivado.tcl
	top_module=vscalealu64 vivado -mode batch -nojournal -log $@ -source vivado.tcl

vscalealu32.vivlog: vscalealu.v bextdep.v bextdep_pps.v
	top_module=vscalealu32 vivado -mode batch -nojournal -log $@ -source vivado.tcl

tinyrocket-src/OK: tinyrocket.sh
	bash tinyrocket.sh

define coretpl =
testbench$1$2: testbench.v bextdep.v bextdep_pps.v
	iverilog -s testbench -D TB_XLEN=$1 -D TB_UUT=bextdep$1$2 \
			-D 'TB_TESTDATA="testdata$1$3.hex"' -o $$@ $$^

testbench$1$2_post: testbench.v syn$1$2.v
	iverilog -s testbench -D TB_XLEN=$1 -D TB_UUT=bextdep$1$2 \
			-D 'TB_TESTDATA="testdata$1$3.hex"' -o $$@ $$^

test$1$2: testbench$1$2 testdata$1$3.hex
	vvp -N ./testbench$1$2

test$1$2_post: testbench$1$2_post testdata$1$3.hex
	vvp -N ./testbench$1$2_post

report: syn$1$2.v
syn$1$2.v: bextdep.v bextdep_pps.v
	yosys -p "read_verilog bextdep.v bextdep_pps.v; synth -flatten -top bextdep$1$2" \
		-p "rename -hide; abc -dff -g cmos2; opt -fast; write_verilog syn$1$2.v" \
		-p "tee -o syn$1$2.rpt stat; tee -a syn$1$2.rpt ltp -noff"

report: bextdep$1$2.vivlog
bextdep$1$2.vivlog: vscalealu.v bextdep.v bextdep_pps.v vivado.tcl
	top_module=bextdep$1$2 vivado -mode batch -nojournal -log $$@ -source vivado.tcl

test:: test$1$2
test_post:: test$1$2_post
syn:: syn$1$2.v

clean::
	rm -f testbench$1$2 testbench$1$2_post syn$1$2.v syn$1$2.rpt bextdep$1$2.vivlog
endef

$(eval $(call coretpl,64,g3,g))
$(eval $(call coretpl,64,p3,))
$(eval $(call coretpl,64,g2,g))
$(eval $(call coretpl,64,p2,))
$(eval $(call coretpl,64,g1,g))
$(eval $(call coretpl,64,p1,))
$(eval $(call coretpl,64,sh,))
$(eval $(call coretpl,64,sb,))
$(eval $(call coretpl,64,sn,))
$(eval $(call coretpl,64,sx,))
$(eval $(call coretpl,64,go,go))

$(eval $(call coretpl,32,g3,g))
$(eval $(call coretpl,32,p3,))
$(eval $(call coretpl,32,g2,g))
$(eval $(call coretpl,32,p2,))
$(eval $(call coretpl,32,g1,g))
$(eval $(call coretpl,32,p1,))
$(eval $(call coretpl,32,sb,))
$(eval $(call coretpl,32,sn,))
$(eval $(call coretpl,32,sx,))
$(eval $(call coretpl,32,go,go))

clean::
	rm -f testdata32.hex testdata32g.hex testdata32go.hex
	rm -f testdata64.hex testdata64g.hex testdata64go.hex
	rm -f testdata testbench.vcd # bextdep_pps.v
	rm -f vscalealu64.rpt vscalealu64.vivlog
	rm -f vscalealu32.rpt vscalealu32.vivlog
	rm -rf .Xil