diff --git a/.gitignore b/.gitignore index e3a6114..e4cce4e 100644 --- a/.gitignore +++ b/.gitignore @@ -30,7 +30,7 @@ *.exe *.out *.app -/.metadata/ +/.metadata/ .jxbrowser-data RemoteSystemsTempFiles diff --git a/README.md b/README.md index e914048..729c06f 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ This is the firmware for an experimental lathe electronic leadscrew controller. gears or gearbox on a metalworking lathe with a stepper motor controlled electronically based on an encoder on the lathe spindle. The electronic controller allows setting different virtual gear ratios for feeds and threading. -![Silkscreened Control Panel](https://raw.githubusercontent.com/clough42/electronic-leadscrew/master/docs/images/CPKit.jpg) +![Silkscreened Control Panel](https://raw.githubusercontent.com/kentavv/electronic-leadscrew/feature-nextion/docs/images/Touchscreen.png) ## Latest Version diff --git a/docs/images/Touchscreen.png b/docs/images/Touchscreen.png new file mode 100644 index 0000000..c816b1e Binary files /dev/null and b/docs/images/Touchscreen.png differ diff --git a/els-f280049c/.cproject b/els-f280049c/.cproject index bbf0e3c..4c61a7d 100644 --- a/els-f280049c/.cproject +++ b/els-f280049c/.cproject @@ -3,6 +3,10 @@ + + + + @@ -15,69 +19,94 @@ - - + + + + + + + + @@ -87,6 +116,10 @@ + + + + @@ -99,73 +132,107 @@ - - + + + + + + + + + @@ -178,6 +245,15 @@ - + + + + + + + + + + diff --git a/els-f280049c/.launches/els-f280049c.launch b/els-f280049c/.launches/els-f280049c.launch new file mode 100644 index 0000000..fb160b1 --- /dev/null +++ b/els-f280049c/.launches/els-f280049c.launch @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/els-f280049c/.project b/els-f280049c/.project index e8c34c3..34b90f5 100644 --- a/els-f280049c/.project +++ b/els-f280049c/.project @@ -24,4 +24,72 @@ org.eclipse.cdt.core.ccnature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + driverlib.lib + 1 + $%7BC2000WARE_DLIB_ROOT%7D/ccs/Release/driverlib.lib + + + device/f28004x_codestartbranch.asm + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_codestartbranch.asm + + + device/f28004x_cputimers.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_cputimers.c + + + device/f28004x_defaultisr.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_defaultisr.c + + + device/f28004x_globalvariabledefs.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/headers/source/f28004x_globalvariabledefs.c + + + device/f28004x_gpio.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_gpio.c + + + device/f28004x_headers_nonbios.cmd + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/headers/cmd/f28004x_headers_nonbios.cmd + + + device/f28004x_piectrl.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_piectrl.c + + + device/f28004x_pievect.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_pievect.c + + + device/f28004x_spi.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_spi.c + + + device/f28004x_sysctrl.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_sysctrl.c + + + device/f28004x_usdelay.asm + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_usdelay.asm + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/driverlib/f28004x/driverlib + + diff --git a/els-f280049c/.settings/com.ti.ccstudio.project.core.prefs b/els-f280049c/.settings/com.ti.ccstudio.project.core.prefs new file mode 100644 index 0000000..76e251e --- /dev/null +++ b/els-f280049c/.settings/com.ti.ccstudio.project.core.prefs @@ -0,0 +1,4 @@ +ccsVersionValidationPolicy=warning +compilerVersionValidationPolicy=flexible +eclipse.preferences.version=1 +productVersionsValidationPolicy=flexible diff --git a/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs b/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs index 98b6350..b4a10b6 100644 --- a/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs +++ b/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs @@ -1,3 +1,103 @@ eclipse.preferences.version=1 inEditor=false onBuild=false +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=-Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning 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+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error 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arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error 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parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/els-f280049c/.settings/org.eclipse.core.resources.prefs b/els-f280049c/.settings/org.eclipse.core.resources.prefs index 8e309e6..bb9eacc 100644 --- a/els-f280049c/.settings/org.eclipse.core.resources.prefs +++ b/els-f280049c/.settings/org.eclipse.core.resources.prefs @@ -1,21 +1,15 @@ eclipse.preferences.version=1 -encoding//Debug/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 +encoding//Debug/device/subdir_rules.mk=UTF-8 +encoding//Debug/device/subdir_vars.mk=UTF-8 encoding//Debug/makefile=UTF-8 encoding//Debug/objects.mk=UTF-8 encoding//Debug/sources.mk=UTF-8 encoding//Debug/subdir_rules.mk=UTF-8 encoding//Debug/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 +encoding//Release/device/source/subdir_rules.mk=UTF-8 +encoding//Release/device/source/subdir_vars.mk=UTF-8 +encoding//Release/device/subdir_rules.mk=UTF-8 +encoding//Release/device/subdir_vars.mk=UTF-8 encoding//Release/makefile=UTF-8 encoding//Release/objects.mk=UTF-8 encoding//Release/sources.mk=UTF-8 diff --git a/els-f280049c/28004x_generic_flash_lnk.cmd b/els-f280049c/28004x_generic_flash_lnk.cmd index aa33b0e..ae52fda 100644 --- a/els-f280049c/28004x_generic_flash_lnk.cmd +++ b/els-f280049c/28004x_generic_flash_lnk.cmd @@ -23,14 +23,13 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. - MEMORY { PAGE 0 : /* BEGIN is used for the "boot to Flash" bootloader mode */ BEGIN : origin = 0x080000, length = 0x000002 - RAMM0 : origin = 0x0000F5, length = 0x00030B + RAMM0 : origin = 0x0000F3, length = 0x00030D RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 @@ -74,12 +73,15 @@ PAGE 0 : FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */ - FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */ + FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */ + +// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ PAGE 1 : - BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 @@ -88,28 +90,53 @@ PAGE 1 : RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 - RAMGS3 : origin = 0x012000, length = 0x002000 + RAMGS3 : origin = 0x012000, length = 0x001FF8 +// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } SECTIONS { codestart : > BEGIN, PAGE = 0, ALIGN(4) - .text : >>FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3, PAGE = 0, ALIGN(4) + .text : >>FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5, PAGE = 0, ALIGN(4) .cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) - .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ - .cio : > RAMLS0, PAGE = 0 .stack : > RAMM1, PAGE = 1 - .ebss : > RAMLS5, PAGE = 1 - .esysmem : > RAMLS5, PAGE = 1 - .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4) + +#if defined(__TI_EABI__) + .init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS0, PAGE = 0 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : >>FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7, PAGE = 0, ALIGN(4) +#else + .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) + .ebss : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS0, PAGE = 0 + .econst : >>FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7, PAGE = 0, ALIGN(4) +#endif ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 + +#if defined(__TI_EABI__) + .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(4) +#else .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, LOAD_START(_RamfuncsLoadStart), @@ -119,6 +146,12 @@ SECTIONS RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0, ALIGN(4) +#endif } +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/els-f280049c/28004x_generic_ram_lnk.cmd b/els-f280049c/28004x_generic_ram_lnk.cmd index 5fd166d..bbe5d30 100644 --- a/els-f280049c/28004x_generic_ram_lnk.cmd +++ b/els-f280049c/28004x_generic_ram_lnk.cmd @@ -23,14 +23,13 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. - MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 - RAMM0 : origin = 0x0000F5, length = 0x00030B + RAMM0 : origin = 0x0000F3, length = 0x00030D RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 @@ -78,8 +77,9 @@ PAGE 0 : PAGE 1 : - BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 @@ -88,27 +88,44 @@ PAGE 1 : RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 - RAMGS3 : origin = 0x012000, length = 0x002000 + RAMGS3 : origin = 0x012000, length = 0x001FF8 +// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } /*You can arrange the .text, .cinit, .const, .pinit, .switch and .econst to FLASH when RAM is filled up.*/ SECTIONS { codestart : > BEGIN, PAGE = 0 - .TI.ramfunc : > RAMM0 PAGE = 0 - .text : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .TI.ramfunc : > RAMM0, PAGE = 0 + .text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 .cinit : > RAMM0, PAGE = 0 - .pinit : > RAMM0, PAGE = 0 .switch : > RAMM0, PAGE = 0 - .cio : > RAMLS0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .stack : > RAMM1, PAGE = 1 - .ebss : > RAMLS5|RAMLS6, PAGE = 1 - .econst : > RAMLS5|RAMLS6, PAGE = 1 - .esysmem : > RAMLS5|RAMLS6, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS5, PAGE = 1 + .init_array : > RAMM0, PAGE = 0 + .const : >> RAMLS6|RAMLS7, PAGE = 1, ALIGN(4) + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + .bss:cio : > RAMLS0, PAGE = 0 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : >> RAMLS6|RAMLS7, PAGE = 1, ALIGN(4) + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS0, PAGE = 0 +#endif ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 } +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/els-f280049c/Core.cpp b/els-f280049c/Core.cpp index e0fc0c4..697c165 100644 --- a/els-f280049c/Core.cpp +++ b/els-f280049c/Core.cpp @@ -42,6 +42,10 @@ Core :: Core( Encoder *encoder, StepperDrive *stepperDrive ) this->previousFeed = NULL; this->powerOn = true; // default to power on + + // KVV + this->enabled = true; + this->reenabled = true; } void Core :: setReverse(bool reverse) diff --git a/els-f280049c/Core.h b/els-f280049c/Core.h index af21e7e..acb1dac 100644 --- a/els-f280049c/Core.h +++ b/els-f280049c/Core.h @@ -56,6 +56,10 @@ class Core bool powerOn; + // KVV + bool enabled; + bool reenabled; + public: Core( Encoder *encoder, StepperDrive *stepperDrive ); @@ -68,8 +72,26 @@ class Core void setPowerOn(bool); void ISR( void ); + + // KVV + void setEnabled(bool v); + bool isEnabled() const; }; +// KVV +inline void Core :: setEnabled(bool v) +{ + if(enabled != v) { + enabled = v; + reenabled = enabled; + } +} + +inline bool Core :: isEnabled() const +{ + return enabled; +} + inline void Core :: setFeed(const FEED_THREAD *feed) { #ifdef USE_FLOATING_POINT @@ -105,7 +127,7 @@ inline int32 Core :: feedRatio(Uint32 count) inline void Core :: ISR( void ) { - if( this->feed != NULL ) { + if( this->enabled && this->feed != NULL ) { // read the encoder Uint32 spindlePosition = encoder->getPosition(); @@ -122,8 +144,10 @@ inline void Core :: ISR( void ) } // if the feed or direction changed, reset sync to avoid a big step - if( feed != previousFeed || feedDirection != previousFeedDirection) { + if( feed != previousFeed || feedDirection != previousFeedDirection || reenabled) { stepperDrive->setCurrentPosition(desiredSteps); + // KVV + reenabled = false; } // remember values for next time diff --git a/els-f280049c/UserInterface.cpp b/els-f280049c/UserInterface.cpp index 0bf1200..b1ccbc3 100644 --- a/els-f280049c/UserInterface.cpp +++ b/els-f280049c/UserInterface.cpp @@ -25,6 +25,8 @@ #include "UserInterface.h" +// KVV +#include "nextion.h" const MESSAGE STARTUP_MESSAGE_2 = { @@ -128,15 +130,37 @@ void UserInterface :: overrideMessage( void ) void UserInterface :: loop( void ) { + const FEED_THREAD *newFeed = NULL; + // read the RPM up front so we can use it to make decisions Uint16 currentRpm = core->getRPM(); // display an override message, if there is one overrideMessage(); + // just in case, initialize the first time through + if( feedTable == NULL ) { + newFeed = loadFeedTable(); + } + // read keypresses from the control panel keys = controlPanel->getKeys(); + // KVV + { + bool at_stop; + bool enabled = core->isEnabled(); + bool nextion_init = false; + KEY_REG nkeys = nextion_loop(core->isAlarm(), enabled, at_stop, nextion_init); + core->setEnabled(enabled); + if (nkeys.all) { + keys = nkeys; + } + if( nextion_init ) { + newFeed = loadFeedTable(); + } + } + // respond to keypresses if( currentRpm == 0 ) { @@ -150,17 +174,19 @@ void UserInterface :: loop( void ) if( keys.bit.IN_MM ) { this->metric = ! this->metric; - core->setFeed(loadFeedTable()); + newFeed = loadFeedTable(); } if( keys.bit.FEED_THREAD ) { this->thread = ! this->thread; - core->setFeed(loadFeedTable()); + newFeed = loadFeedTable(); } if( keys.bit.FWD_REV ) { this->reverse = ! this->reverse; core->setReverse(this->reverse); + // feed table hasn't changed, but we need to trigger an update + newFeed = loadFeedTable(); } if( keys.bit.SET ) { @@ -179,11 +205,11 @@ void UserInterface :: loop( void ) // these keys can be operated when the machine is running if( keys.bit.UP ) { - core->setFeed(feedTable->next()); + newFeed = feedTable->next(); } if( keys.bit.DOWN ) { - core->setFeed(feedTable->previous()); + newFeed = feedTable->previous(); } } @@ -191,15 +217,31 @@ void UserInterface :: loop( void ) } #endif // IGNORE_ALL_KEYS_WHEN_RUNNING - // update the control panel - controlPanel->setLEDs(calculateLEDs()); - controlPanel->setValue(feedTable->current()->display); - controlPanel->setRPM(currentRpm); - + // if we have changed the feed + if( newFeed != NULL ) { + // update the control panel + LED_REG leds = this->calculateLEDs(); + controlPanel->setLEDs(leds); + controlPanel->setValue(newFeed->display); + + // KVV + // Must pass leds as newFeed->leds is out of date, and may not have foward/reverse set. + nextion_feed(newFeed, leds); + + // update the core + core->setFeed(newFeed); + core->setReverse(this->reverse); + } if( ! core->isPowerOn() ) { controlPanel->setValue(VALUE_BLANK); } + // update the RPM display + controlPanel->setRPM(currentRpm); + // KVV + nextion_rpm(currentRpm); + + // write data out to the display controlPanel->refresh(); } diff --git a/els-f280049c/device/placeholder.txt b/els-f280049c/device/placeholder.txt new file mode 100644 index 0000000..e69de29 diff --git a/els-f280049c/device_support_f28004x/common/include/F28x_Project.h b/els-f280049c/device_support_f28004x/common/include/F28x_Project.h deleted file mode 100644 index daebcc0..0000000 --- a/els-f280049c/device_support_f28004x/common/include/F28x_Project.h +++ /dev/null @@ -1,51 +0,0 @@ -//############################################################################# -// -// FILE: F28x_Project.h -// -// TITLE: F28x Project Headerfile and Examples Include File -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F28X_PROJECT_H -#define F28X_PROJECT_H - -#include "f28004x_cla_typedefs.h" // f28004x CLA Type definitions -#include "f28004x_device.h" // f28004x Headerfile Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -#endif // end of F28X_PROJECT_H definition - diff --git a/els-f280049c/device_support_f28004x/common/include/device.h b/els-f280049c/device_support_f28004x/common/include/device.h deleted file mode 100644 index 26690ad..0000000 --- a/els-f280049c/device_support_f28004x/common/include/device.h +++ /dev/null @@ -1,307 +0,0 @@ -//############################################################################# -// -// FILE: device.h -// -// TITLE: Device setup for examples. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef __DEVICE_H__ -#define __DEVICE_H__ - -// -// Included Files -// -#include "driverlib.h" - -//***************************************************************************** -// -// Defines for pin numbers and other GPIO configuration -// -//***************************************************************************** -#ifdef _LAUNCHXL_F280049C -// -// LaunchPad -// - -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 34U // GPIO number for LD4 -#define DEVICE_GPIO_PIN_LED2 23U // GPIO number for LD5 -#define DEVICE_GPIO_CFG_LED1 GPIO_34_GPIO34 // "pinConfig" for LD4 -#define DEVICE_GPIO_CFG_LED2 GPIO_23_GPIO23 // "pinConfig" for LD5 - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 32U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 33U // GPIO number for CANRXA -#define DEVICE_GPIO_CFG_CANRXA GPIO_33_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_32_CANTXA // "pinConfig" for CANA TX - -// -// LINA -// -#define DEVICE_GPIO_CFG_LINTXA GPIO_37_LINTXA // "pinConfig" for LINA TX -#define DEVICE_GPIO_CFG_LINRXA GPIO_35_LINRXA // "pinConfig" for LINA RX - -// -// FSI -// -#define DEVICE_GPIO_PIN_FSI_RXCLK 33U // GPIO number for FSI RXCLK -#define DEVICE_GPIO_CFG_FSI_RXCLK GPIO_33_FSI_RXCLK // "pinConfig" for FSI RXCLK - -// -// SPI -// -#define DEVICE_GPIO_PIN_SPICLKA 56U // GPIO number for SPI CLKA -#define DEVICE_GPIO_PIN_SPISIMOA 16U // GPIO number for SPI SIMOA -#define DEVICE_GPIO_PIN_SPISOMIA 17U // GPIO number for SPI SOMIA -#define DEVICE_GPIO_PIN_SPISTEA 57U // GPIO number for SPI STEA -#define DEVICE_GPIO_CFG_SPICLKA GPIO_56_SPICLKA // "pinConfig" for SPI CLKA -#define DEVICE_GPIO_CFG_SPISIMOA GPIO_16_SPISIMOA // "pinConfig" for SPI SIMOA -#define DEVICE_GPIO_CFG_SPISOMIA GPIO_17_SPISOMIA // "pinConfig" for SPI SOMIA -#define DEVICE_GPIO_CFG_SPISTEA GPIO_57_SPISTEA // "pinConfig" for SPI STEA -#define DEVICE_GPIO_PIN_SPICLKB 26U // GPIO number for SPI CLKB -#define DEVICE_GPIO_PIN_SPISIMOB 24U // GPIO number for SPI SIMOB -#define DEVICE_GPIO_PIN_SPISOMIB 31U // GPIO number for SPI SOMIB -#define DEVICE_GPIO_PIN_SPISTEB 27U // GPIO number for SPI STEB -#define DEVICE_GPIO_CFG_SPICLKB GPIO_26_SPICLKB // "pinConfig" for SPI CLKB -#define DEVICE_GPIO_CFG_SPISIMOB GPIO_24_SPISIMOB // "pinConfig" for SPI SIMOB -#define DEVICE_GPIO_CFG_SPISOMIB GPIO_31_SPISOMIB // "pinConfig" for SPI SOMIB -#define DEVICE_GPIO_CFG_SPISTEB GPIO_27_SPISTEB // "pinConfig" for SPI STEB - -// -// I2C -// -#define DEVICE_GPIO_PIN_SDAA 35U // GPIO number for I2C SDAA -#define DEVICE_GPIO_PIN_SCLA 37U // GPIO number for I2C SCLA -#define DEVICE_GPIO_CFG_SDAA GPIO_35_SDAA // "pinConfig" for I2C SDAA -#define DEVICE_GPIO_CFG_SCLA GPIO_37_SCLA // "pinConfig" for I2C SCLA - -// -// eQEP -// -#define DEVICE_GPIO_PIN_EQEP1A 35U // GPIO number for EQEP 1A -#define DEVICE_GPIO_PIN_EQEP1B 37U // GPIO number for EQEP 1B -#define DEVICE_GPIO_PIN_EQEP1I 59U // GPIO number for EQEP 1I -#define DEVICE_GPIO_CFG_EQEP1A GPIO_35_EQEP1A // "pinConfig" for EQEP 1A -#define DEVICE_GPIO_CFG_EQEP1B GPIO_37_EQEP1B // "pinConfig" for EQEP 1B -#define DEVICE_GPIO_CFG_EQEP1I GPIO_59_EQEP1I // "pinConfig" for EQEP 1I - -// -// EPWM -// -#define DEVICE_PERIPHERAL_BASE_EPWM EPWM6_BASE // Base peripheral EPWM 6 -#define DEVICE_PERIPHERAL_INT_EPWM INT_EPWM6 // Base peripheral EPWM 6 interrupt -#define DEVICE_GPIO_PIN_EPWMxA 10U // GPIO number for EPWM6A -#define DEVICE_GPIO_PIN_EPWMxB 11U // GPIO number for EPWM6B -#define DEVICE_GPIO_PIN_IOINDEX 8U // GPIO number for IO Index -#define DEVICE_GPIO_CFG_EPWMxA GPIO_10_EPWM6A // "pinConfig" for EPWM6A -#define DEVICE_GPIO_CFG_EPWMxB GPIO_11_EPWM6B // "pinConfig" for EPWM6B -#define DEVICE_GPIO_CFG_IOINDEX GPIO_8_GPIO8 // "pinConfig" for IO Index - -#else -// -// ControlCARD -// - -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 -#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 -#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 -#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA - -// -// CAN External Loopback -// -#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX -#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX -#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX - -// -// LINA -// -#define DEVICE_GPIO_CFG_LINTXA GPIO_46_LINTXA // "pinConfig" for LINA TX -#define DEVICE_GPIO_CFG_LINRXA GPIO_47_LINRXA // "pinConfig" for LINA RX - -// -// FSI -// -#define DEVICE_GPIO_PIN_FSI_RXCLK 13U // GPIO number for FSI RXCLK -#define DEVICE_GPIO_CFG_FSI_RXCLK GPIO_13_FSI_RXCLK // "pinConfig" for FSI RXCLK - -// -// SPI -// -#define DEVICE_GPIO_PIN_SPICLKA 9U // GPIO number for SPI CLKA -#define DEVICE_GPIO_PIN_SPISIMOA 8U // GPIO number for SPI SIMOA -#define DEVICE_GPIO_PIN_SPISOMIA 10U // GPIO number for SPI SOMIA -#define DEVICE_GPIO_PIN_SPISTEA 11U // GPIO number for SPI STEA -#define DEVICE_GPIO_CFG_SPICLKA GPIO_9_SPICLKA // "pinConfig" for SPI CLKA -#define DEVICE_GPIO_CFG_SPISIMOA GPIO_8_SPISIMOA // "pinConfig" for SPI SIMOA -#define DEVICE_GPIO_CFG_SPISOMIA GPIO_10_SPISOMIA // "pinConfig" for SPI SOMIA -#define DEVICE_GPIO_CFG_SPISTEA GPIO_11_SPISTEA // "pinConfig" for SPI STEA -#define DEVICE_GPIO_PIN_SPICLKB 26U // GPIO number for SPI CLKB -#define DEVICE_GPIO_PIN_SPISIMOB 24U // GPIO number for SPI SIMOB -#define DEVICE_GPIO_PIN_SPISOMIB 25U // GPIO number for SPI SOMIB -#define DEVICE_GPIO_PIN_SPISTEB 27U // GPIO number for SPI STEB -#define DEVICE_GPIO_CFG_SPICLKB GPIO_26_SPICLKB // "pinConfig" for SPI CLKB -#define DEVICE_GPIO_CFG_SPISIMOB GPIO_24_SPISIMOB // "pinConfig" for SPI SIMOB -#define DEVICE_GPIO_CFG_SPISOMIB GPIO_25_SPISOMIB // "pinConfig" for SPI SOMIB -#define DEVICE_GPIO_CFG_SPISTEB GPIO_27_SPISTEB // "pinConfig" for SPI STEB - -// -// I2C -// -#define DEVICE_GPIO_PIN_SDAA 32U // GPIO number for I2C SDAA -#define DEVICE_GPIO_PIN_SCLA 33U // GPIO number for I2C SCLA -#define DEVICE_GPIO_CFG_SDAA GPIO_32_SDAA // "pinConfig" for I2C SDAA -#define DEVICE_GPIO_CFG_SCLA GPIO_33_SCLA // "pinConfig" for I2C SCLA - -// -// eQEP -// -#define DEVICE_GPIO_PIN_EQEP1A 6U // GPIO number for EQEP 1A -#define DEVICE_GPIO_PIN_EQEP1B 7U // GPIO number for EQEP 1B -#define DEVICE_GPIO_PIN_EQEP1I 9U // GPIO number for EQEP 1I -#define DEVICE_GPIO_CFG_EQEP1A GPIO_6_EQEP1A // "pinConfig" for EQEP 1A -#define DEVICE_GPIO_CFG_EQEP1B GPIO_7_EQEP1B // "pinConfig" for EQEP 1B -#define DEVICE_GPIO_CFG_EQEP1I GPIO_9_EQEP1I // "pinConfig" for EQEP 1I - -// -// EPWM -// -#define DEVICE_PERIPHERAL_BASE_EPWM EPWM1_BASE // Base peripheral EPWM 1 -#define DEVICE_PERIPHERAL_INT_EPWM INT_EPWM1 // Base peripheral EPWM 1 interrupt -#define DEVICE_GPIO_PIN_EPWMxA 0U // GPIO number for EPWM1A -#define DEVICE_GPIO_PIN_EPWMxB 1U // GPIO number for EPWM1B -#define DEVICE_GPIO_PIN_IOINDEX 2U // GPIO number for IO Index -#define DEVICE_GPIO_CFG_EPWMxA GPIO_0_EPWM1A // "pinConfig" for EPWM1A -#define DEVICE_GPIO_CFG_EPWMxB GPIO_1_EPWM1B // "pinConfig" for EPWM1B -#define DEVICE_GPIO_CFG_IOINDEX GPIO_2_GPIO2 // "pinConfig" for IO Index - -#endif - -// -// SCI for USB-to-UART adapter on FTDI chip -// -#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX -#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX -#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX -#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX - -//***************************************************************************** -// -// Defines related to clock configuration -// -//***************************************************************************** -// -// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). -// -#define DEVICE_OSCSRC_FREQ 20000000U - -// -// Define to pass to SysCtl_setClock(). Will configure the clock as follows: -// PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) -// -#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) | \ - SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ - SYSCTL_PLL_ENABLE) - -// -// 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the -// code below if a different clock configuration is used! -// -#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 10 * 1) / 2) - -// -// 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default -// low speed peripheral clock divider of 4. Update the code below if a -// different LSPCLK divider is used! -// -#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) - -//***************************************************************************** -// -// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro -// will convert the desired delay in microseconds to the count value expected -// by the function. \b x is the number of microseconds to delay. -// -//***************************************************************************** -#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ - (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) - -//***************************************************************************** -// -// Defines, Globals, and Header Includes related to Flash Support -// -//***************************************************************************** -#ifdef _FLASH -#include - -extern uint16_t RamfuncsLoadStart; -extern uint16_t RamfuncsLoadEnd; -extern uint16_t RamfuncsLoadSize; -extern uint16_t RamfuncsRunStart; -extern uint16_t RamfuncsRunEnd; -extern uint16_t RamfuncsRunSize; -#endif - -#define DEVICE_FLASH_WAITSTATES 4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void Device_init(void); -extern void Device_enableAllPeripherals(void); -extern void Device_initGPIO(void); -extern void __error__(char *filename, uint32_t line); - -#endif // __DEVICE_H__ diff --git a/els-f280049c/device_support_f28004x/common/include/driverlib.h b/els-f280049c/device_support_f28004x/common/include/driverlib.h deleted file mode 100644 index 54b5ba6..0000000 --- a/els-f280049c/device_support_f28004x/common/include/driverlib.h +++ /dev/null @@ -1,82 +0,0 @@ -//############################################################################# -// -// FILE: driverlib.h -// -// TITLE: C28x Driverlib Header File -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef DRIVERLIB_H -#define DRIVERLIB_H - -#include "inc/hw_memmap.h" - -#include "adc.h" -#include "asysctl.h" -#include "can.h" -#include "cla.h" -#include "clapromcrc.h" -#include "cmpss.h" -#include "cpu.h" -#include "cputimer.h" -#include "dac.h" -#include "dcc.h" -#include "dcsm.h" -#include "debug.h" -#include "dma.h" -#include "ecap.h" -#include "epwm.h" -#include "eqep.h" -#include "flash.h" -#include "fsi.h" -#include "gpio.h" -#include "hrcap.h" -#include "hrpwm.h" -#include "i2c.h" -#include "interrupt.h" -#include "lin.h" -#include "memcfg.h" -#include "pga.h" -#include "pin_map.h" -#include "pmbus.h" -#include "sci.h" -#include "sdfm.h" -#include "spi.h" -#include "sysctl.h" -#include "version.h" -#include "xbar.h" - -#endif // end of DRIVERLIB_H definition diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h deleted file mode 100644 index 9b89799..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h +++ /dev/null @@ -1,199 +0,0 @@ -//############################################################################# -// -// FILE: f28004x_cla_defines.h -// -// TITLE: #defines used in CLA examples -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef F28004X_CLA_DEFINES_H_ -#define F28004X_CLA_DEFINES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// MCTL Register -// -#define CLA_FORCE_RESET 0x1 -#define CLA_IACK_ENABLE 0x1 -#define CLA_IACK_DISABLE 0x0 - -// -// MMEMCFG Register -// -#define CLA_CLA_SPACE 0x1 -#define CLA_CPU_SPACE 0x0 - -// -// MIER Interrupt Enable Register -// -#define CLA_INT_ENABLE 0x1 -#define CLA_INT_DISABLE 0x0 - -// -// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register -// -#define CLA_TRIG_NOPERPH 0 -#define CLA_TRIG_ADCAINT1 1 -#define CLA_TRIG_ADCAINT2 2 -#define CLA_TRIG_ADCAINT3 3 -#define CLA_TRIG_ADCAINT4 4 -#define CLA_TRIG_ADCAEVT 5 -#define CLA_TRIG_ADCBINT1 6 -#define CLA_TRIG_ADCBINT2 7 -#define CLA_TRIG_ADCBINT3 8 -#define CLA_TRIG_ADCBINT4 9 -#define CLA_TRIG_ADCBEVT 10 -#define CLA_TRIG_ADCCINT1 11 -#define CLA_TRIG_ADCCINT2 12 -#define CLA_TRIG_ADCCINT3 13 -#define CLA_TRIG_ADCCINT4 14 -#define CLA_TRIG_ADCCEVT 15 - -#define CLA_TRIG_XINT1 29 -#define CLA_TRIG_XINT2 30 -#define CLA_TRIG_XINT3 31 -#define CLA_TRIG_XINT4 32 -#define CLA_TRIG_XINT5 33 - -#define CLA_TRIG_EPWM1INT 36 -#define CLA_TRIG_EPWM2INT 37 -#define CLA_TRIG_EPWM3INT 38 -#define CLA_TRIG_EPWM4INT 39 -#define CLA_TRIG_EPWM5INT 40 -#define CLA_TRIG_EPWM6INT 41 -#define CLA_TRIG_EPWM7INT 42 -#define CLA_TRIG_EPWM8INT 43 - -#define CLA_TRIG_TINT0 68 -#define CLA_TRIG_TINT1 69 -#define CLA_TRIG_TINT2 70 - -#define CLA_TRIG_ECAP1INT 75 -#define CLA_TRIG_ECAP2INT 76 -#define CLA_TRIG_ECAP3INT 77 -#define CLA_TRIG_ECAP4INT 78 -#define CLA_TRIG_ECAP5INT 79 -#define CLA_TRIG_ECAP6INT 80 -#define CLA_TRIG_ECAP7INT 81 - -#define CLA_TRIG_EQEP1INT 83 -#define CLA_TRIG_EQEP2INT 84 - -#define CLA_TRIG_ECAP6INT2 92 -#define CLA_TRIG_ECAP7INT2 93 - -#define CLA_TRIG_SD1INT 95 -#define CLA_TRIG_SD1DRINT1 96 -#define CLA_TRIG_SD1DRINT2 97 -#define CLA_TRIG_SD1DRINT3 98 -#define CLA_TRIG_SD1DRINT4 99 - -#define CLA_TRIG_PMBUSAINT 105 - -#define CLA_TRIG_SPITXINTA 109 -#define CLA_TRIG_SPIRXINTA 110 -#define CLA_TRIG_SPITXINTB 111 -#define CLA_TRIG_SPIRXINTB 112 - -#define CLA_TRIG_LINA_INT1 117 -#define CLA_TRIG_LINA_INT0 118 - -#define CLA_TRIG_CLA1PROMCRC 121 - -#define CLA_TRIG_FSITXINT1 123 -#define CLA_TRIG_FSITXINT2 124 -#define CLA_TRIG_FSIRXINT1 125 -#define CLA_TRIG_FSIRXINT2 126 -#define CLA_TRIG_CLB1INT 127 -#define CLA_TRIG_CLB2INT 128 -#define CLA_TRIG_CLB3INT 129 -#define CLA_TRIG_CLB4INT 130 - -#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT1 == 1); - -#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT2 == 1); - -#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT3 == 1); - -#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT4 == 1); - -#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT5 == 1); - -#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT6 == 1); - -#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT7 == 1); - -#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT8 == 1); - -#define Cla1ForceTask1() asm(" IACK #0x0001") -#define Cla1ForceTask2() asm(" IACK #0x0002") -#define Cla1ForceTask3() asm(" IACK #0x0004") -#define Cla1ForceTask4() asm(" IACK #0x0008") -#define Cla1ForceTask5() asm(" IACK #0x0010") -#define Cla1ForceTask6() asm(" IACK #0x0020") -#define Cla1ForceTask7() asm(" IACK #0x0040") -#define Cla1ForceTask8() asm(" IACK #0x0080") - -#ifdef __cplusplus -} -#endif - - - -#endif /* F2004X_CLA_DEFINES_H_ */ diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h deleted file mode 100644 index ce918c1..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h +++ /dev/null @@ -1,128 +0,0 @@ - //########################################################################### -// -// FILE: f28004x_cla_typedefs.h -// -// TITLE: Variable type definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - - -#ifndef F28004x_CLA_TYPEDEFS_H_ -#define F28004x_CLA_TYPEDEFS_H_ - -// -// Macros to manipulate pre-processor to generate a header file name -// at compile time that is based on the test name and can be used as -// an argument to #include -// -#define XSTRINGIZE(s) STRINGIZE(s) -#define STRINGIZE(s) #s -#define XCONCAT(x,y) CONCAT(x,y) -#define CONCAT(x,y) x##y - -// -// Suppress warnings casting CLA pointers -// -#pragma diag_suppress 70,770,232 - -#ifdef __TMS320C28XX_CLA__ -// -// For Portability, User Is Recommended To Use Following Data Type Size -// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: -// -// CLA does not support 64-bit types -// This definition is only to allow inclusion of the standard header files -// which do use 64-bit types -// - -#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) -#define F28_DATA_TYPES -#define DSP28_DATA_TYPES -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else -#error f28004x_Cla_Typedefs.h must be included before f28004x_Device.h or any other header \ -file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES -#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) - -#ifndef _TI_STD_TYPES -#define _TI_STD_TYPES -// -// These types are also defined in DSP/BIOS 5.x's and the -// SYS/BIOS 6.x's files. We need to protect their -// definition with the #ifndef/#define guard to avoid the duplicate -// definition warning. -// -// SYS/BIOS requires that the file be included before -// any other .h files. -// -#endif - -// -// MSTF bit description -// -struct MSTF_SHADOW_BITS { - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Rounding Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint16 RPCL:4; // 15:12 Return PC: Low Portion - Uint16 RPCH:8; // 23:16 Return PC: High Portion - Uint16 rsvd4:8; // 31:24 Reserved -}; -extern __cregister volatile unsigned int MSTF; - -#endif - -#ifndef __TMS320C28XX__ -#define __cregister -#endif - -#endif /*f28004x_CLA_TYPEDEFS_H_*/ diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h deleted file mode 100644 index 2b92a3f..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h +++ /dev/null @@ -1,143 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimervars.h -// -// TITLE: f28004x Device CPUTIMERS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_CPUTIMERVARS_H -#define F28004x_CPUTIMERVARS_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Cputimers External References & Function Declarations -// - -// -// CPU Timer Support Variables: -// -struct CPUTIMER_VARS { - volatile struct CPUTIMER_REGS *RegsAddr; - Uint32 InterruptCount; - float CPUFreqInMHz; - float PeriodInUSec; -}; - -// -// Function prototypes and external definitions: -// -void InitCpuTimers(void); -void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); - -extern struct CPUTIMER_VARS CpuTimer0; -extern struct CPUTIMER_VARS CpuTimer1; -extern struct CPUTIMER_VARS CpuTimer2; - -// -// Useful Timer Operations -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of f28004x_CPUTIMERVARS_H definition - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h b/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h deleted file mode 100644 index ddfb733..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h +++ /dev/null @@ -1,202 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_defaultisr.h -// -// TITLE: f28004x Device Default Interrupt Service Routines Definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_DEFAULT_ISR_H -#define F28004x_DEFAULT_ISR_H -#ifdef __cplusplus -extern "C" { -#endif - -// -// Default Interrupt Service Routine Declarations: -// The following function prototypes are for the -// default ISR routines used with the default PIE vector table. -// This default vector table is found in the f28004x_pievect.h -// file. -// -interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt -interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt -interrupt void DATALOG_ISR(void); // Datalogging Interrupt -interrupt void RTOS_ISR(void); // RTOS Interrupt -interrupt void EMU_ISR(void); // Emulation Interrupt -interrupt void NMI_ISR(void); // Non-Maskable Interrupt -interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap -interrupt void USER1_ISR(void); // User Defined Trap 1 -interrupt void USER2_ISR(void); // User Defined Trap 2 -interrupt void USER3_ISR(void); // User Defined Trap 3 -interrupt void USER4_ISR(void); // User Defined Trap 4 -interrupt void USER5_ISR(void); // User Defined Trap 5 -interrupt void USER6_ISR(void); // User Defined Trap 6 -interrupt void USER7_ISR(void); // User Defined Trap 7 -interrupt void USER8_ISR(void); // User Defined Trap 8 -interrupt void USER9_ISR(void); // User Defined Trap 9 -interrupt void USER10_ISR(void); // User Defined Trap 10 -interrupt void USER11_ISR(void); // User Defined Trap 11 -interrupt void USER12_ISR(void); // User Defined Trap 12 -interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 -interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 -interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 -interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt -interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt -interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt -interrupt void WAKE_ISR(void); // 1.8 - Halt Wakeup Interrupt -interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt -interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt -interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt -interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt -interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt -interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt -interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt -interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt -interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt -interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt -interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt -interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt -interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt -interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt -interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt -interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt -interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt -interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt -interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt -interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt -interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt -interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt -interrupt void ECAP7_ISR(void); // 4.7 - eCAP7 Interrupt -interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt -interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt -interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt -interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt -interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt -interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt -interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt -interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt -interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt -interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt -interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt -interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt -interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 -interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 -interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt -interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt -interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt -interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt -interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 -interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 -interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 -interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 -interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt -interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 -interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 -interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 -interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt -interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 -interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 -interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 -interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 -interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 -interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 -interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 -interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 -interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 -interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 -interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 -interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt -interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt -interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt -interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt -interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt -interrupt void ECAP6_2_ISR(void); // 4.14 - eCAP6 HR Calibration Interrupt -interrupt void ECAP7_2_ISR(void); // 4.15 - eCAP6 HR Calibration Interrupt -interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt -interrupt void SD1DR1_ISR(void); // 5.13 - SDFM1 DR Interrupt 1 -interrupt void SD1DR2_ISR(void); // 5.14 - SDFM1 DR Interrupt 2 -interrupt void SD1DR3_ISR(void); // 5.15 - SDFM1 DR Interrupt 3 -interrupt void SD1DR4_ISR(void); // 5.16 - SDFM1 DR Interrupt 4 -interrupt void FSITXA1_ISR(void); // 7.11 - FSITXA1 Interrupt -interrupt void FSITXA2_ISR(void); // 7.12 - FSITXA2 Interrupt -interrupt void FSIRXA1_ISR(void); // 7.13 - FSIRXA1 Interrupt -interrupt void FSIRXA2_ISR(void); // 7.14 - FSIRXA2 Interrupt -interrupt void CLA1PROMCRC_ISR(void); // 7.15 - CLAP1ROMCRC Interrupt -interrupt void LINA_0_ISR(void); // 8.9 - LINA Interrupt 0 -interrupt void LINA_1_ISR(void); // 8.10 - LINA Interrupt 1 -interrupt void PMBUSA_ISR(void); // 8.13 - PMBUSA Interrupt -interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt -interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 -interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 -interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 -// -// 12.10 - RAM Correctable Error Interrupt -// -interrupt void RAM_CORRECTABLE_ERROR_ISR(void); - -// -// 12.11 - Flash Correctable Error Interrupt -// -interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); - -// -// 12.12 - RAM Access Violation Interrupt -// -interrupt void RAM_ACCESS_VIOLATION_ISR(void); - -interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip Interrupt -interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow Interrupt -interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow Interrupt - -// -// Catch-all for PIE Reserved Locations for testing purposes: -// -interrupt void PIE_RESERVED_ISR(void); // Reserved ISR -interrupt void EMPTY_ISR(void); // Only does a return -interrupt void NOTUSED_ISR(void); // Unused ISR -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F28004x_PIEVECT_H definition -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h deleted file mode 100644 index 75dc6fb..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h +++ /dev/null @@ -1,193 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma_defines.h -// -// TITLE: #defines used in DMA examples -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F28004X_DMA_DEFINES_H_ -#define F28004X_DMA_DEFINES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// PERINTSEL bits -// -#define DMA_ADCAINT1 1 -#define DMA_ADCAINT2 2 -#define DMA_ADCAINT3 3 -#define DMA_ADCAINT4 4 -#define DMA_ADCAEVT 5 -#define DMA_ADCBINT1 6 -#define DMA_ADCBINT2 7 -#define DMA_ADCBINT3 8 -#define DMA_ADCBINT4 9 -#define DMA_ADCBEVT 10 -#define DMA_ADCCINT1 11 -#define DMA_ADCCINT2 12 -#define DMA_ADCCINT3 13 -#define DMA_ADCCINT4 14 -#define DMA_ADCCEVT 15 - -#define DMA_XINT1 29 -#define DMA_XINT2 30 -#define DMA_XINT3 31 -#define DMA_XINT4 32 -#define DMA_XINT5 33 - -#define DMA_EPWM1A 36 -#define DMA_EPWM1B 37 -#define DMA_EPWM2A 38 -#define DMA_EPWM2B 39 -#define DMA_EPWM3A 40 -#define DMA_EPWM3B 41 -#define DMA_EPWM4A 42 -#define DMA_EPWM4B 43 -#define DMA_EPWM5A 44 -#define DMA_EPWM5B 45 -#define DMA_EPWM6A 46 -#define DMA_EPWM6B 47 -#define DMA_EPWM7A 48 -#define DMA_EPWM7B 49 -#define DMA_EPWM8A 50 -#define DMA_EPWM8B 51 - -#define DMA_TINT0 68 -#define DMA_TINT1 69 -#define DMA_TINT2 70 - -#define DMA_ECAP1 75 -#define DMA_ECAP2 76 -#define DMA_ECAP3 77 -#define DMA_ECAP4 78 -#define DMA_ECAP5 79 -#define DMA_ECAP6 80 -#define DMA_ECAP7 81 - -#define DMA_SD1FLT1 96 -#define DMA_SD1FLT2 97 -#define DMA_SD1FLT3 98 -#define DMA_SD1FLT4 99 - -#define DMA_SPIATX 109 -#define DMA_SPIARX 110 -#define DMA_SPIBTX 111 -#define DMA_SPIBRX 112 - -#define DMA_LINATX 117 -#define DMA_LINARX 118 - -#define DMA_FSITXA 123 - -#define DMA_FSIRXA 125 - -#define DMA_CANAIF1 167 -#define DMA_CANAIF2 168 -#define DMA_CANAIF3 169 -#define DMA_CANBIF1 170 -#define DMA_CANBIF2 171 -#define DMA_CANBIF3 172 - -// -// OVERINTE bit -// -#define OVRFLOW_DISABLE 0x0 -#define OVEFLOW_ENABLE 0x1 - -// -// PERINTE bit -// -#define PERINT_DISABLE 0x0 -#define PERINT_ENABLE 0x1 - -// -// CHINTMODE bits -// -#define CHINT_BEGIN 0x0 -#define CHINT_END 0x1 - -// -// ONESHOT bits -// -#define ONESHOT_DISABLE 0x0 -#define ONESHOT_ENABLE 0x1 - -// -// CONTINOUS bit -// -#define CONT_DISABLE 0x0 -#define CONT_ENABLE 0x1 - -// -// SYNCE bit -// -#define SYNC_DISABLE 0x0 -#define SYNC_ENABLE 0x1 - -// -// SYNCSEL bit -// -#define SYNC_SRC 0x0 -#define SYNC_DST 0x1 - -// -// DATASIZE bit -// -#define SIXTEEN_BIT 0x0 -#define THIRTYTWO_BIT 0x1 - -// -// CHINTE bit -// -#define CHINT_DISABLE 0x0 -#define CHINT_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif - -#endif /*end of F28004X_DMA_DEFINES_H_ */ -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h deleted file mode 100644 index 2d4595f..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h +++ /dev/null @@ -1,342 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm_defines.h -// -// TITLE: f28004x Device EPWM Register Bit Defines -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_EPWM_DEFINES_H -#define F28004x_EPWM_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// TBCTL (Time-Base Control) -// - -// -// CTRMODE bits -// -#define TB_COUNT_UP 0x0 -#define TB_COUNT_DOWN 0x1 -#define TB_COUNT_UPDOWN 0x2 -#define TB_FREEZE 0x3 - -// -// PHSEN bit -// -#define TB_DISABLE 0x0 -#define TB_ENABLE 0x1 - -// -// PRDLD bit -// -#define TB_SHADOW 0x0 -#define TB_IMMEDIATE 0x1 - -// -// SYNCOSEL bits -// -#define TB_SYNC_IN 0x0 -#define TB_CTR_ZERO 0x1 -#define TB_CTR_CMPB 0x2 -#define TB_SYNC_DISABLE 0x3 - -// -// HSPCLKDIV and CLKDIV bits -// -#define TB_DIV1 0x0 -#define TB_DIV2 0x1 -#define TB_DIV4 0x2 - -// -// PHSDIR bit -// -#define TB_DOWN 0x0 -#define TB_UP 0x1 - -// -// CMPCTL (Compare Control) -// - -// -// LOADAMODE and LOADBMODE bits -// -#define CC_CTR_ZERO 0x0 -#define CC_CTR_PRD 0x1 -#define CC_CTR_ZERO_PRD 0x2 -#define CC_LD_DISABLE 0x3 - -// -// SHDWAMODE and SHDWBMODE bits -// -#define CC_SHADOW 0x0 -#define CC_IMMEDIATE 0x1 - -// -// AQCTLA and AQCTLB (Action Qualifier Control) -// - -// -// ZRO, PRD, CAU, CAD, CBU, CBD bits -// -#define AQ_NO_ACTION 0x0 -#define AQ_CLEAR 0x1 -#define AQ_SET 0x2 -#define AQ_TOGGLE 0x3 - -// -// DBCTL (Dead-Band Control) -// - -// -// OUT MODE bits -// -#define DB_DISABLE 0x0 -#define DBB_ENABLE 0x1 -#define DBA_ENABLE 0x2 -#define DB_FULL_ENABLE 0x3 - -// -// POLSEL bits -// -#define DB_ACTV_HI 0x0 -#define DB_ACTV_LOC 0x1 -#define DB_ACTV_HIC 0x2 -#define DB_ACTV_LO 0x3 - -// -// IN MODE -// -#define DBA_ALL 0x0 -#define DBB_RED_DBA_FED 0x1 -#define DBA_RED_DBB_FED 0x2 -#define DBB_ALL 0x3 - -// -// CHPCTL (chopper control) -// - -// -// CHPEN bit -// -#define CHP_DISABLE 0x0 -#define CHP_ENABLE 0x1 - -// -// CHPFREQ bits -// -#define CHP_DIV1 0x0 -#define CHP_DIV2 0x1 -#define CHP_DIV3 0x2 -#define CHP_DIV4 0x3 -#define CHP_DIV5 0x4 -#define CHP_DIV6 0x5 -#define CHP_DIV7 0x6 -#define CHP_DIV8 0x7 - -// -// CHPDUTY bits -// -#define CHP1_8TH 0x0 -#define CHP2_8TH 0x1 -#define CHP3_8TH 0x2 -#define CHP4_8TH 0x3 -#define CHP5_8TH 0x4 -#define CHP6_8TH 0x5 -#define CHP7_8TH 0x6 - -// -// TZSEL (Trip Zone Select) -// - -// -// CBCn and OSHTn bits -// -#define TZ_DISABLE 0x0 -#define TZ_ENABLE 0x1 - -// -// TZCTL (Trip Zone Control) -// - -// -// TZA and TZB bits -// -#define TZ_HIZ 0x0 -#define TZ_FORCE_HI 0x1 -#define TZ_FORCE_LO 0x2 -#define TZ_NO_CHANGE 0x3 - -// -// TZDCSEL (Trip Zone Digital Compare) -// - -// -// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits -// -#define TZ_EVT_DISABLE 0x0 -#define TZ_DCAH_LOW 0x1 -#define TZ_DCAH_HI 0x2 -#define TZ_DCAL_LOW 0x3 -#define TZ_DCAL_HI 0x4 -#define TZ_DCAL_HI_DCAH_LOW 0x5 - -#define TZ_DCBH_LOW 0x1 -#define TZ_DCBH_HI 0x2 -#define TZ_DCBL_LOW 0x3 -#define TZ_DCBL_HI 0x4 -#define TZ_DCBL_HI_DCBH_LOW 0x5 - -// -// ETSEL (Event Trigger Select) -// -#define ET_DCAEVT1SOC 0x0 -#define ET_CTR_ZERO 0x1 -#define ET_CTR_PRD 0x2 -#define ET_CTR_PRDZERO 0x3 -#define ET_CTRU_CMPA 0x4 -#define ET_CTRD_CMPA 0x5 -#define ET_CTRU_CMPB 0x6 -#define ET_CTRD_CMPB 0x7 - -// -// ETPS (Event Trigger Pre-scale) -// - -// -// INTPRD, SOCAPRD, SOCBPRD bits -// -#define ET_DISABLE 0x0 -#define ET_1ST 0x1 -#define ET_2ND 0x2 -#define ET_3RD 0x3 - -// -// HRPWM (High Resolution PWM) -// - -// -// HRCNFG -// -#define HR_DISABLE 0x0 -#define HR_REP 0x1 -#define HR_FEP 0x2 -#define HR_BEP 0x3 - -#define HR_CMP 0x0 -#define HR_PHS 0x1 - -#define HR_CTR_ZERO 0x0 -#define HR_CTR_PRD 0x1 -#define HR_CTR_ZERO_PRD 0x2 - -#define HR_NORM_B 0x0 -#define HR_INVERT_B 0x1 - -// -// DC (Digital Compare) -// - -// -// DCTRIPSEL -// -#define DC_TZ1 0x0 -#define DC_TZ2 0x1 -#define DC_TZ3 0x2 -#define DC_TRIPIN1 0x0 -#define DC_TRIPIN2 0x1 -#define DC_TRIPIN3 0x2 -#define DC_TRIPIN4 0x3 -#define DC_TRIPIN5 0x4 -#define DC_TRIPIN6 0x5 -#define DC_TRIPIN7 0x6 -#define DC_TRIPIN8 0x7 -#define DC_TRIPIN9 0x8 -#define DC_TRIPIN10 0x9 -#define DC_TRIPIN11 0xA -#define DC_TRIPIN12 0xB -// Reserved 0xC -#define DC_TRIPIN14 0xD -#define DC_TRIPIN15 0xE -#define DC_COMBINATION 0xF - -// -// DCFCTL -// -#define DC_SRC_DCAEVT1 0x0 -#define DC_SRC_DCAEVT2 0x1 -#define DC_SRC_DCBEVT1 0x2 -#define DC_SRC_DCBEVT2 0x3 - -#define DC_PULSESEL_PRD 0x0 -#define DC_PULSESEL_ZERO 0x1 -#define DC_PULSESEL_ZERO_PRD 0x2 - -#define DC_BLANK_DISABLE 0x0 -#define DC_BLANK_ENABLE 0x1 - -#define DC_BLANK_NOTINV 0x0 -#define DC_BLANK_INV 0x1 - -// -//DCACTL/DCBCTL -// -#define DC_EVT1 0x0 -#define DC_EVT2 0x0 -#define DC_EVT_FLT 0x1 -#define DC_EVT_SYNC 0x0 -#define DC_EVT_ASYNC 0x1 -#define DC_SOC_DISABLE 0x0 -#define DC_SOC_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_EPWM_DEFINES_H - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h b/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h deleted file mode 100644 index c1a6266..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h +++ /dev/null @@ -1,429 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_examples.h -// -// TITLE: f28004x Device Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_EXAMPLES_H -#define F28004x_EXAMPLES_H - -#ifdef __cplusplus -extern "C" { -#endif - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select SYSPLL integer multiplier -//***************************************************************************** - -#define IMULT_0 0 -#define IMULT_1 1 -#define IMULT_2 2 -#define IMULT_3 3 -#define IMULT_4 4 -#define IMULT_5 5 -#define IMULT_6 6 -#define IMULT_7 7 -#define IMULT_8 8 -#define IMULT_9 9 -#define IMULT_10 10 -#define IMULT_11 11 -#define IMULT_12 12 -#define IMULT_13 13 -#define IMULT_14 14 -#define IMULT_15 15 -#define IMULT_16 16 -#define IMULT_17 17 -#define IMULT_18 18 -#define IMULT_19 19 -#define IMULT_20 20 -#define IMULT_21 21 -#define IMULT_22 22 -#define IMULT_23 23 -#define IMULT_24 24 -#define IMULT_25 25 -#define IMULT_26 26 -#define IMULT_27 27 -#define IMULT_28 28 -#define IMULT_29 29 -#define IMULT_30 30 -#define IMULT_31 31 -#define IMULT_32 32 -#define IMULT_33 33 -#define IMULT_34 34 -#define IMULT_35 35 -#define IMULT_36 36 -#define IMULT_37 37 -#define IMULT_38 38 -#define IMULT_39 39 -#define IMULT_40 40 -#define IMULT_41 41 -#define IMULT_42 42 -#define IMULT_43 43 -#define IMULT_44 44 -#define IMULT_45 45 -#define IMULT_46 46 -#define IMULT_47 47 -#define IMULT_48 48 -#define IMULT_49 49 -#define IMULT_50 50 -#define IMULT_51 51 -#define IMULT_52 52 -#define IMULT_53 53 -#define IMULT_54 54 -#define IMULT_55 55 -#define IMULT_56 56 -#define IMULT_57 57 -#define IMULT_58 58 -#define IMULT_59 59 -#define IMULT_60 60 -#define IMULT_61 61 -#define IMULT_62 62 -#define IMULT_63 63 -#define IMULT_64 64 -#define IMULT_65 65 -#define IMULT_66 66 -#define IMULT_67 67 -#define IMULT_68 68 -#define IMULT_69 69 -#define IMULT_70 70 -#define IMULT_71 71 -#define IMULT_72 72 -#define IMULT_73 73 -#define IMULT_74 74 -#define IMULT_75 75 -#define IMULT_76 76 -#define IMULT_77 77 -#define IMULT_78 78 -#define IMULT_79 79 -#define IMULT_80 80 -#define IMULT_81 81 -#define IMULT_82 82 -#define IMULT_83 83 -#define IMULT_84 84 -#define IMULT_85 85 -#define IMULT_86 86 -#define IMULT_87 87 -#define IMULT_88 88 -#define IMULT_89 89 -#define IMULT_90 90 -#define IMULT_91 91 -#define IMULT_92 92 -#define IMULT_93 93 -#define IMULT_94 94 -#define IMULT_95 95 -#define IMULT_96 96 -#define IMULT_97 97 -#define IMULT_98 98 -#define IMULT_99 99 -#define IMULT_100 100 -#define IMULT_101 101 -#define IMULT_102 102 -#define IMULT_103 103 -#define IMULT_104 104 -#define IMULT_105 105 -#define IMULT_106 106 -#define IMULT_107 107 -#define IMULT_108 108 -#define IMULT_109 109 -#define IMULT_110 110 -#define IMULT_111 111 -#define IMULT_112 112 -#define IMULT_113 113 -#define IMULT_114 114 -#define IMULT_115 115 -#define IMULT_116 116 -#define IMULT_117 117 -#define IMULT_118 118 -#define IMULT_119 119 -#define IMULT_120 120 -#define IMULT_121 121 -#define IMULT_122 122 -#define IMULT_123 123 -#define IMULT_124 124 -#define IMULT_125 125 -#define IMULT_126 126 -#define IMULT_127 127 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select SYSPLL fractional multiplier -//***************************************************************************** - -#define FMULT_0 0 -#define FMULT_0pt25 1 -#define FMULT_0pt5 2 -#define FMULT_0pt75 3 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select divsel for SYSPLL -//***************************************************************************** - -#define PLLCLK_BY_1 0 -#define PLLCLK_BY_2 1 -#define PLLCLK_BY_4 2 -#define PLLCLK_BY_6 3 -#define PLLCLK_BY_8 4 -#define PLLCLK_BY_10 5 -#define PLLCLK_BY_12 6 -#define PLLCLK_BY_14 7 -#define PLLCLK_BY_16 8 -#define PLLCLK_BY_18 9 -#define PLLCLK_BY_20 10 -#define PLLCLK_BY_22 11 -#define PLLCLK_BY_24 12 -#define PLLCLK_BY_26 13 -#define PLLCLK_BY_28 14 -#define PLLCLK_BY_30 15 -#define PLLCLK_BY_32 16 -#define PLLCLK_BY_34 17 -#define PLLCLK_BY_36 18 -#define PLLCLK_BY_38 19 -#define PLLCLK_BY_40 20 -#define PLLCLK_BY_42 21 -#define PLLCLK_BY_44 22 -#define PLLCLK_BY_46 23 -#define PLLCLK_BY_48 24 -#define PLLCLK_BY_50 25 -#define PLLCLK_BY_52 26 -#define PLLCLK_BY_54 27 -#define PLLCLK_BY_56 28 -#define PLLCLK_BY_58 29 -#define PLLCLK_BY_60 30 -#define PLLCLK_BY_62 31 -#define PLLCLK_BY_64 32 -#define PLLCLK_BY_66 33 -#define PLLCLK_BY_68 34 -#define PLLCLK_BY_70 35 -#define PLLCLK_BY_72 36 -#define PLLCLK_BY_74 37 -#define PLLCLK_BY_76 38 -#define PLLCLK_BY_78 39 -#define PLLCLK_BY_80 40 -#define PLLCLK_BY_82 41 -#define PLLCLK_BY_84 42 -#define PLLCLK_BY_86 43 -#define PLLCLK_BY_88 44 -#define PLLCLK_BY_90 45 -#define PLLCLK_BY_92 46 -#define PLLCLK_BY_94 47 -#define PLLCLK_BY_96 48 -#define PLLCLK_BY_98 49 -#define PLLCLK_BY_100 50 -#define PLLCLK_BY_102 51 -#define PLLCLK_BY_104 52 -#define PLLCLK_BY_106 53 -#define PLLCLK_BY_108 54 -#define PLLCLK_BY_110 55 -#define PLLCLK_BY_112 56 -#define PLLCLK_BY_114 57 -#define PLLCLK_BY_116 58 -#define PLLCLK_BY_118 59 -#define PLLCLK_BY_120 60 -#define PLLCLK_BY_122 61 -#define PLLCLK_BY_124 62 -#define PLLCLK_BY_126 63 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select clock source -//***************************************************************************** - -#define INT_OSC2 0 // Internal oscillator 2 -#define XTAL_OSC 1 // External oscillator, crystal mode -#define INT_OSC1 2 // Internal oscillator 1 -#define XTAL_OSC_SE 5 // External oscillator, single-ended mode - -/*----------------------------------------------------------------------------- - Specify the clock rate of the CPU (SYSCLKOUT) in nS. - - Take into account the input clock frequency and the PLL multiplier - selected in step 1. - - Use one of the values provided, or define your own. - The trailing L is required tells the compiler to treat - the number as a 64-bit value. - - Only one statement should be uncommented. - - Example: 100 MHz devices: - CLKIN is a 10 MHz crystal or internal 10 MHz oscillator - - In step 1 the user specified the PLL multiplier = 0x20 for a - 100 MHz CPU clock (SYSCLKOUT = 100 MHz). - - In this case, the CPU_RATE will be 10.000L - Uncomment the line: #define CPU_RATE 10.000L - ------------------------------------------------------------------------------*/ - -#define CPU_RATE 10.00L // for a 100MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 11.111L // for a 90MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 12.500L // for a 80MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 25.000L // for a 40MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) - -// -// The following pointer to a function call calibrates the ADC reference, -// DAC offset, and internal oscillators -// -#define Device_cal (void (*)(void))0x070282 - -// -// The following pointers to functions calibrate the ADC linearity. Use this -// in the AdcSetMode(...) function only -// -#define CalAdcaINL (void (*)(void))0x0703B4 -#define CalAdcbINL (void (*)(void))0x0703B2 -#define CalAdccINL (void (*)(void))0x0703B0 -#define CalAdcdINL (void (*)(void))0x0703AE - -// -// The following pointer to a function call looks up the ADC offset trim for a -// given condition. Use this in the AdcSetMode(...) function only. -// -#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC - -// -// Include Example Header Files: -// - -#include "f28004x_globalprototypes.h" //Prototypes for global functions - //within the .c files. -#include "f28004x_adc_defines.h" -#include "f28004x_cputimervars.h" -#include "f28004x_epwm_defines.h" -#include "f28004x_gpio_defines.h" // Macros used for GPIO support code -#include "f28004x_pie_defines.h" // Macros used for PIE examples -#include "f28004x_sysctrl_defines.h" // Macros used for LPM support code -#include "f28004x_dma_defines.h" // Macros used for DMA support code -#include "f28004x_cla_defines.h" //Macros used for CLA support code - -#define PARTNO_28004xPACKAGEHERE 0x00 - -#define CPU_FRQ_100MHZ 1 - -// -// Include files not used with F/BIOS -// -#ifndef F28_BIOS -#include "f28004x_defaultisr.h" -#endif - -extern void F28x_usDelay(long LoopCount); -// DO NOT MODIFY THIS LINE. -#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) - -// -// Useful Timer Operations -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F28004x_EXAMPLES_H definition - -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h b/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h deleted file mode 100644 index 0d6a25a..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_globalprototypes.h -// -// TITLE: Global prototypes for f28004x Examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_GLOBALPROTOTYPES_H -#define F28004x_GLOBALPROTOTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// shared global function prototypes -// -extern void EnableInterrupts(void); -extern void InitPeripheralClocks(void); -extern void DisablePeripheralClocks(void); -extern void InitPieCtrl(void); -extern void InitPieVectTable(void); -extern void InitSpi(void); -extern void InitSpiGpio(void); -extern void InitSpiaGpio(void); -extern void InitSysCtrl(void); -extern void InitSysPll(Uint16 clock_source, - Uint16 imult, Uint16 fmult, Uint16 divsel); -extern bool IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult); - -// -// For compatibility with previous versions -// -#define KickDog ServiceDog -extern void ServiceDog(void); -extern void DisableDog(void); - -extern Uint16 CsmUnlock(void); -extern void SysIntOsc1Sel (void); -extern void SysIntOsc2Sel (void); -extern void SysXtalOscSel (void); -extern void SysXtalOscSESel (void); - -// -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -extern void InitFlash(void); -extern void FlashOff(void); - -// -// LPM functions in f28004x_sysctrl.c -// -void IDLE(void); -void HALT(void); - -// -// ADC functions -// -extern void SetVREF(int module, int mode, int ref); - -// -// DMA Functions -// -extern void DMAInitialize(void); - -// -// DMA Channel 1 -// -extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, - int16 desbstep); -extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH1(void); - -// -// DMA Channel 2 -// -extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, - Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, Uint16 chinte); -extern void StartDMACH2(void); - -// -// DMA Channel 3 -// -extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH3(void); - -// -// DMA Channel 4 -// -extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH4(void); - -// -// DMA Channel 5 -// -extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH5(void); - -// -// DMA Channel 6 -// -extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); -extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH6(void); - -// -// GPIO Functions -// -extern void InitGpio(void); -extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, - Uint16 muxPosition); -extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, - Uint16 flags); -extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); -extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); -Uint16 GPIO_ReadPin(Uint16 gpioNumber); -void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); - -// External symbols created by the linker cmd file -// DSP28 examples will use these to relocate code from one LOAD location -// in Flash to a different RUN location in internal -// RAM -// -extern Uint16 RamfuncsLoadStart; -extern Uint16 RamfuncsLoadEnd; -extern Uint16 RamfuncsLoadSize; -extern Uint16 RamfuncsRunStart; -extern Uint16 RamfuncsRunEnd; -extern Uint16 RamfuncsRunSize; - - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_GLOBALPROTOTYPES_H - -// -// End of file. -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h deleted file mode 100644 index 5503c44..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h +++ /dev/null @@ -1,105 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio_defines.h -// -// TITLE: f28004x GPIO support definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_GPIO_DEFINES_H -#define F28004x_GPIO_DEFINES_H - -// -// Defines -// - -// -// CPU pin masters for GPIO_SelectPinMux() -// -#define GPIO_MUX_CPU1 0x0 -#define GPIO_MUX_CPU1CLA 0x1 - -// -// Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, -// QUAL6, and ASYNC) take up two bits and must be in the order specified. -// -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 -#define GPIO_PUSHPULL 0 -#define GPIO_PULLUP (1 << 0) -#define GPIO_INVERT (1 << 1) -#define GPIO_OPENDRAIN (1 << 2) -#define GPIO_SYNC (0x0 << 4) -#define GPIO_QUAL3 (0x1 << 4) -#define GPIO_QUAL6 (0x2 << 4) -#define GPIO_ASYNC (0x3 << 4) - -// -// Flags for GPIO_SetupLock(). -// -#define GPIO_UNLOCK 0 -#define GPIO_LOCK 1 - -// -// Helpful constants for array-based access to GPIO registers -// -#define GPY_CTRL_OFFSET (0x40/2) -#define GPY_DATA_OFFSET (0x8/2) - -#define GPYQSEL (0x2/2) -#define GPYMUX (0x6/2) -#define GPYDIR (0xA/2) -#define GPYPUD (0xC/2) -#define GPYINV (0x10/2) -#define GPYODR (0x12/2) -#define GPYGMUX (0x20/2) -#define GPYCSEL (0x28/2) -#define GPYLOCK (0x3C/2) -#define GPYCR (0x3E/2) - -#define GPYDAT (0x0/2) -#define GPYSET (0x2/2) -#define GPYCLEAR (0x4/2) -#define GPYTOGGLE (0x6/2) - -#endif // end of F28004x_GPIO_DEFINES_H definition - -// -// End of file -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h deleted file mode 100644 index 2cd6101..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h +++ /dev/null @@ -1,72 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pie_defines.h -// -// TITLE: #defines used in PIE examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_PIE_DEFINES_H -#define F28004x_PIE_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIEACK_GROUP1 0x0001 -#define PIEACK_GROUP2 0x0002 -#define PIEACK_GROUP3 0x0004 -#define PIEACK_GROUP4 0x0008 -#define PIEACK_GROUP5 0x0010 -#define PIEACK_GROUP6 0x0020 -#define PIEACK_GROUP7 0x0040 -#define PIEACK_GROUP8 0x0080 -#define PIEACK_GROUP9 0x0100 -#define PIEACK_GROUP10 0x0200 -#define PIEACK_GROUP11 0x0400 -#define PIEACK_GROUP12 0x0800 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_PIE_DEFINES_H - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h deleted file mode 100644 index e54a9b9..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h +++ /dev/null @@ -1,59 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl_defines.h -// -// TITLE: f28004x LPM support definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_SYSCTRL_DEFINES_H -#define F28004x_SYSCTRL_DEFINES_H - -// -// Defines -// -#define LPM_IDLE 0x0 -#define LPM_HALT 0x2 -#define LPM_HIB 0x3 - -#endif // end of F28004x_SYSCTRL_DEFINES_H definition - -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c b/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c deleted file mode 100644 index 1c99c84..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c +++ /dev/null @@ -1,102 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc.c -// -// TITLE: F28004x ADC Support Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Header File Include File -#include "f28004x_examples.h" // Examples Include File - -// -// SetVREF - Set Vref mode. Function to select reference mode and offset trim. -// Offset trim for Internal VREF 3.3 is unique. All other modes use the same -// offset trim. Also note that when the mode parameter is ADC_EXTERNAL, the -// ref parameter has no effect. -// -void SetVREF(int module, int mode, int ref) -{ - Uint16 *offset, offval; - - // - // Define offset locations from OTP - // - offset = (Uint16 *)(0x70594 + (module * 6)); - - if((mode == ADC_INTERNAL) && (ref == ADC_VREF3P3)) - { - offval = (*offset) >> 8; // Internal / 1.65v mode offset - } - else - { - offval = (*offset) & 0xFF; // All other modes - } - - // - // Write offset trim values and configure reference modes - // - EALLOW; - switch(module) - { - case 0: - AdcaRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFASEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFA2P5SEL = ref; - break; - case 1: - AdcbRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFBSEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFB2P5SEL = ref; - break; - case 2: - AdccRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFCSEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFC2P5SEL = ref; - break; - default: - break; - } - EDIS; -} - -// -// End of File -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm deleted file mode 100644 index e34559f..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm +++ /dev/null @@ -1,111 +0,0 @@ -;//########################################################################### -;// -;// FILE: f28004x_codestartbranch.asm -;// -;// TITLE: Branch for redirecting code execution after boot. -;// -;// For these examples, code_start is the first code that is executed after -;// exiting the boot ROM code. -;// -;// The codestart section in the linker cmd file is used to physically place -;// this code at the correct memory location. This section should be placed -;// at the location the BOOT ROM will re-direct the code to. For example, -;// for boot to FLASH this code will be located at 0x80000. -;// -;// In addition, the example f28004x projects are setup such that the codegen -;// entry point is also set to the codestart label. This is done by linker -;// option -e in the project build options. When the debugger loads the code, -;// it will automatically set the PC to the "entry point" address indicated by -;// the -e linker option. In this case the debugger is simply assigning the PC, -;// it is not the same as a full reset of the device. -;// -;// The compiler may warn that the entry point for the project is other then -;// _c_init00. _c_init00 is the C environment setup and is run before -;// main() is entered. The codestart code will re-direct the execution -;// to _c_init00 and thus there is no worry and this warning can be ignored. -;// -;//########################################################################### -;// $TI Release: F28004x Support Library v1.05.00.00 $ -;// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;// $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;//########################################################################### - -*********************************************************************** - -WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 - - .ref _c_int00 - .global code_start - -*********************************************************************** -* Function: codestart section -* -* Description: Branch to code starting point -*********************************************************************** - - .sect "codestart" - -code_start: - .if WD_DISABLE == 1 - LB wd_disable ;Branch to watchdog disable code - .else - LB _c_int00 ;Branch to start of boot._asm in RTS library - .endif - -;end codestart section - -*********************************************************************** -* Function: wd_disable -* -* Description: Disables the watchdog timer -*********************************************************************** - .if WD_DISABLE == 1 - - .text -wd_disable: - SETC OBJMODE ;Set OBJMODE for 28x object code - EALLOW ;Enable EALLOW protected register access - MOVZ DP, #7029h>>6 ;Set data page for WDCR register - MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD - EDIS ;Disable EALLOW protected register access - LB _c_int00 ;Branch to start of boot._asm in RTS library - - .endif - -;end wd_disable - - .end - -;// -;// End of file. -;// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c b/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c deleted file mode 100644 index a4583a3..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c +++ /dev/null @@ -1,194 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimers.c -// -// TITLE: f28004x CPU 32-bit Timers Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File - -// -// Globals -// -struct CPUTIMER_VARS CpuTimer0; -struct CPUTIMER_VARS CpuTimer1; -struct CPUTIMER_VARS CpuTimer2; - -// -// InitCpuTimers - This function initializes all three CPU timers -// to a known state. -// -void -InitCpuTimers(void) -{ - // - // CPU Timer 0 - // Initialize address pointers to respective timer registers - // - CpuTimer0.RegsAddr = &CpuTimer0Regs; - - // - // Initialize timer period to maximum - // - CpuTimer0Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) - // - CpuTimer0Regs.TPR.all = 0; - CpuTimer0Regs.TPRH.all = 0; - - // - // Make sure timer is stopped - // - CpuTimer0Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value - // - CpuTimer0Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters - // - CpuTimer0.InterruptCount = 0; - - // - // CPU Timer 1 and 2 - // Initialize address pointers to respective timer registers - // - CpuTimer1.RegsAddr = &CpuTimer1Regs; - CpuTimer2.RegsAddr = &CpuTimer2Regs; - - // - // Initialize timer period to maximum - // - CpuTimer1Regs.PRD.all = 0xFFFFFFFF; - CpuTimer2Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) - // - CpuTimer1Regs.TPR.all = 0; - CpuTimer1Regs.TPRH.all = 0; - CpuTimer2Regs.TPR.all = 0; - CpuTimer2Regs.TPRH.all = 0; - - // - // Make sure timers are stopped - // - CpuTimer1Regs.TCR.bit.TSS = 1; - CpuTimer2Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value - // - CpuTimer1Regs.TCR.bit.TRB = 1; - CpuTimer2Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters - // - CpuTimer1.InterruptCount = 0; - CpuTimer2.InterruptCount = 0; -} - -// -// ConfigCpuTimer - This function initializes the selected timer to the period -// specified by the "Freq" and "Period" parameters. The "Freq" is entered -// as "MHz" and the "Period" in "uSeconds". The timer is held in the stopped -// state after configuration. -// -void -ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) -{ - Uint32 temp; - - // - // Initialize timer period - // - Timer->CPUFreqInMHz = Freq; - Timer->PeriodInUSec = Period; - temp = (long) (Freq * Period); - Timer->RegsAddr->PRD.all = temp; - - // - // Set pre-scale counter to divide by 1 (SYSCLKOUT) - // - Timer->RegsAddr->TPR.all = 0; - Timer->RegsAddr->TPRH.all = 0; - - // - // Initialize timer control register - // - - // - // 1 = Stop timer, 0 = Start/Restart Timer - // - Timer->RegsAddr->TCR.bit.TSS = 1; - - // - // 1 = reload timer - // - Timer->RegsAddr->TCR.bit.TRB = 1; - Timer->RegsAddr->TCR.bit.SOFT = 0; - - // - // Timer Free Run Disabled - // - Timer->RegsAddr->TCR.bit.FREE = 0; - - // - // 0 = Disable 1 = Enable Timer Interrupt - // - Timer->RegsAddr->TCR.bit.TIE = 1; - - // - // Reset interrupt counter - // - Timer->InterruptCount = 0; -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm deleted file mode 100644 index 151c1d0..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm +++ /dev/null @@ -1,186 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_dcsm_z1otp.asm -;; -;; TITLE: Dual Code Security Module Zone 1 OTP -;; -;; DESCRIPTION: -;; -;; This file is used to specify Z1 DCSM OTP and zone select block -;; values to program. -;; -;; In addition, the 60 reserved values after the zone select block -;; are all programmed to 0x0000 as well. -;; -;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time -;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order -;; to program the below memory sections, user should uncomment the .long words -;; of each section and change the value to what is desired. Additionally, the -;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a -;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section -;; that is being programmed. -;; -;; -;; !!IMPORTANT!! The "bx_dcsm_otp_z1_linkpointer" section contains the -;; Z1 LINKPOINTER which determines the location of the Z1 Zone Select block. -;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z1_linkpointer" -;; section in the *_dcsm_lnk.cmd command linker file must also change to an -;; address decoded from the value specified in the Z1-LINKPOINTER location. -;; -;; -;; The "bx_dcsm_zsel_z1" section contains the actual Z1 Zone Select Block -;; values that will be linked and programmed into to the DCSM Z1 OTP Zone -;; Select block in OTP. -;; These values must be known in order to unlock the CSM module. -;; -;; It is recommended that all values be left as 0xFFFFFFFF during code -;; development. Values of 0xFFFFFFFF do not activate code security and dummy -;; reads of the Z1 DCSM PWL registers is all that is required to unlock the -;; CSM. When code development is complete, modify values to activate the -;; code security module. -;; -;; ******************************WARNING*************************************** -;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users -;; intend to comeback and re-program any of the bits to '0' in future. If user -;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would -;; get programmed to a non erased state and users won't be able to comeback -;; and re-program the OTP location to another value. Please refer to DCSM -;; chapter of device TRM for more details on ECC for the locations in DCSM. -;; -;; Hence TI ships this example commenting out the initialization of all the -;; below locations. -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .sect "b0_dcsm_otp_z1_linkpointer" -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_gpreg" -;; -;; See the ROM Code and Peripheral Booting chapter of TRM for more details. -;; -;; Below is a description of the bit fields of Z1OTP_BOOTPIN_CONFIG -;; used by Boot ROM. -;; -;; | Key (31-24) | BMSP2 (23-16) | BMSP1 (15-8) | BMSP0 (7-0) | -;; -;; Below is a description of the bit fields of Z1OTP_GPREG2 used by -;; Boot ROM. -;; -;; | Key (31-24) | RSVD (23-8) | RSVD (7-6) | ESP (5-4) | RSVD (3-0) | -;; -;; .long 0xFFFFFFFF ;Z1OTP_BOOTPIN_CONFIG -;; .long 0xFFFFFFFF ;Z1OTP_GPREG2 - - .sect "b0_dcsm_otp_z1_pswdlock" -;; .long 0xFFFFFFFF ;Z1OTP_PSWDLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_crclock" -;; .long 0xFFFFFFFF ;Z1OTP_CRCLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_bootctrl" -;; -;; See the ROM Code and Peripheral Booting chapter of TRM for more details. -;; -;; Below is a description of the bit fields of Z1OTP_BOOTDEF_LOW used by -;; Boot ROM. -;; -;; | BOOT_DEF3(31-24) | BOOT_DEF2(23-16) | BOOT_DEF1(15-8) | BOOT_DEF0(7-0) | -;; -;; Below is a description of the bit fields of Z1OTP_BOOTDEF_HIGH -;; used by Boot ROM. -;; -;; | BOOT_DEF7(31-24) | BOOT_DEF6(23-16) | BOOT_DEF5(15-8) | BOOT_DEF4(7-0) | -;; -;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_LOW -;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_HIGH - - .sect "b0_dcsm_zsel_z1" - -;; .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYRAM -;; .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;B0_Z1OTP_GRABRAM -;; .long 0xFFFFFFFF ;B0_Z1OTP_GRABSECT - -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD0 (LSW of 128-bit password) -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD1 -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD2 -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD3 (MSW of 128-bit password) - - .sect "b1_dcsm_otp_z1_linkpointer" -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b1_dcsm_zsel_z1" -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z1OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z1OTP_GRABSECT - -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved - -;;---------------------------------------------------------------------- - -;; For code security operation,after development has completed, prior to -;; production, all other zone select block locations should be programmed -;; to 0x0000 for maximum security. -;; If the first zone select block at offset 0x10 is used, the section -;; "dcsm_rsvd_z1" can be used to program these locations to 0x0000. -;; This code is commented out for development. - -;; .sect "dcsm_rsvd_z1" -;; .loop (1e0h) -;; .int 0x0000 -;; .endloop - - -;;############################################################################# -;; End of file -;;############################################################################# diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm deleted file mode 100644 index 99d093a..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm +++ /dev/null @@ -1,159 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_dcsm_z2otp.asm -;; -;; TITLE: Dual Code Security Module Zone 2 OTP -;; -;; DESCRIPTION: -;; -;; This file is used to specify Z2 DCSM OTP and zone select block -;; values to program. -;; -;; In addition, the 60 reserved values after the zone select block -;; are all programmed to 0x0000 as well. -;; -;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time -;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order -;; to program the below memory sections, user should uncomment the .long words -;; of each section and change the value to what is desired. Additionally, the -;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a -;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section -;; that is being programmed. -;; -;; -;; !!IMPORTANT!! The "bx_dcsm_otp_z2_linkpointer" section contains the -;; Z2 LINKPOINTER which determines the location of the Z2 Zone Select block. -;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z2_linkpointer" -;; section in the *_dcsm_lnk.cmd command linker file must also change to an -;; address decoded from the value specified in the Z2-LINKPOINTER location. -;; -;; -;; The "bx_dcsm_zsel_z2" section contains the actual Z2 Zone Select Block -;; values that will be linked and programmed into to the DCSM Z2 OTP Zone -;; Select block in OTP. -;; These values must be known in order to unlock the CSM module. -;; -;; It is recommended that all values be left as 0xFFFFFFFF during code -;; development. Values of 0xFFFFFFFF do not activate code security and dummy -;; reads of the Z2 DCSM PWL registers is all that is required to unlock the -;; CSM. When code development is complete, modify values to activate the -;; code security module. -;; -;; ******************************WARNING*************************************** -;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users -;; intend to comeback and re-program any of the bits to '0' in future. If user -;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would -;; get programmed to a non erased state and users won't be able to comeback -;; and re-program the OTP location to another value. Please refer to DCSM -;; chapter of device TRM for more details on ECC for the locations in DCSM. -;; -;; Hence TI ships this example commenting out the initialization of all the -;; below locations. -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .sect "b0_dcsm_otp_z2_linkpointer" -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_gpreg" -;; .long 0xFFFFFFFF ;Z2OTP_BOOTPIN_CONFIG -;; .long 0xFFFFFFFF ;Z2OTP_GPREG2 - - .sect "b0_dcsm_otp_z2_pswdlock" -;; .long 0xFFFFFFFF ;Z2OTP_PSWDLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_crclock" -;; .long 0xFFFFFFFF ;Z2OTP_CRCLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_bootctrl" -;; .long 0xFFFFFFFF ;Z2OTP_GPREG3 -;; .long 0xFFFFFFFF ;Z2OTP_BOOTCTRL - - .sect "b0_dcsm_zsel_z2" -;; .long 0xFFFFFFFF ;B0_Z2OTP_EXEONLYRAM -;; .long 0xFFFFFFFF ;B0_Z2OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;B0_Z2OTP_GRABRAM -;; .long 0xFFFFFFFF ;B0_Z2OTP_GRABSECT - -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD0 (LSW of 128-bit password) -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD1 -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD2 -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD3 (MSW of 128-bit password) - - .sect "b1_dcsm_otp_z2_linkpointer" -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b1_dcsm_zsel_z2" -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z2OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z2OTP_GRABSECT - -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved - -;;---------------------------------------------------------------------- - -;; For code security operation,after development has completed, prior to -;; production, all other zone select block locations should be programmed -;; to 0x0000 for maximum security. -;; If the first zone select block at offset 0x10 is used, the section -;; "dcsm_rsvd_z2" can be used to program these locations to 0x0000. -;; This code is commented out for development. - -;; .sect "dcsm_rsvd_z2" -;; .loop (1e0h) -;; .int 0x0000 -;; .endloop - - -;;############################################################################# -;; End of file -;;############################################################################# diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c b/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c deleted file mode 100644 index 06b2643..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c +++ /dev/null @@ -1,2780 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_defaultisr.c -// -// TITLE: f28004x Device Default Interrupt Service Routines -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // F28004x Header File Include File -#include "f28004x_examples.h" // F28004x Examples Include File - -// -// TIMER1_ISR - CPU Timer 1 Interrupt -// -interrupt void -TIMER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// TIMER2_ISR - CPU Timer 2 Interrupt -// -interrupt void -TIMER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DATALOG_ISR - Datalogging Interrupt -// -interrupt void -DATALOG_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RTOS_ISR - RTOS Interrupt -// -interrupt void -RTOS_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EMU_ISR - Emulation Interrupt -// -interrupt void -EMU_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// NMI_ISR - Non-Maskable Interrupt -// -interrupt void -NMI_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ILLEGAL_ISR - Illegal Operation Trap -// -interrupt void -ILLEGAL_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER1_ISR - User Defined Trap 1 -// -interrupt void -USER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER2_ISR - User Defined Trap 2 -// -interrupt void -USER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER3_ISR - User Defined Trap 3 -// -interrupt void -USER3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER4_ISR - User Defined Trap 4 -// -interrupt void -USER4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER5_ISR - User Defined Trap 5 -// -interrupt void -USER5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER6_ISR - User Defined Trap 6 -// -interrupt void -USER6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER7_ISR - User Defined Trap 7 -// -interrupt void -USER7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER8_ISR - User Defined Trap 8 -// -interrupt void -USER8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER9_ISR - User Defined Trap 9 -// -interrupt void -USER9_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER10_ISR - User Defined Trap 10 -// -interrupt void -USER10_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER11_ISR - User Defined Trap 11 -// -interrupt void -USER11_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER12_ISR - User Defined Trap 12 -// -interrupt void -USER12_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA1_ISR - ADCA Interrupt 1 -// -interrupt void -ADCA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB1_ISR - ADCB Interrupt 1 -// -interrupt void -ADCB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC1_ISR - ADCC Interrupt 1 -// -interrupt void -ADCC1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT1_ISR - XINT1 Interrupt -// -interrupt void -XINT1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT2_ISR - XINT2 Interrupt -// -interrupt void -XINT2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// TIMER0_ISR - Timer 0 Interrupt -// -interrupt void -TIMER0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// WAKE_ISR - Halt Wakeup Interrupt -// -interrupt void -WAKE_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM1_TZ_ISR - ePWM1 Trip Zone Interrupt -// -interrupt void -EPWM1_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM2_TZ_ISR - ePWM2 Trip Zone Interrupt -// -interrupt void -EPWM2_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM3_TZ_ISR - ePWM3 Trip Zone Interrupt -// -interrupt void -EPWM3_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM4_TZ_ISR - ePWM4 Trip Zone Interrupt -// -interrupt void -EPWM4_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM5_TZ_ISR - ePWM5 Trip Zone Interrupt -// -interrupt void -EPWM5_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM6_TZ_ISR - ePWM6 Trip Zone Interrupt -// -interrupt void -EPWM6_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM7_TZ_ISR - ePWM7 Trip Zone Interrupt -// -interrupt void -EPWM7_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM8_TZ_ISR - ePWM8 Trip Zone Interrupt -// -interrupt void -EPWM8_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM1_ISR - ePWM1 Interrupt -// -interrupt void -EPWM1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM2_ISR - ePWM2 Interrupt -// -interrupt void -EPWM2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM3_ISR - ePWM3 Interrupt -// -interrupt void -EPWM3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM4_ISR - ePWM4 Interrupt -// -interrupt void -EPWM4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM5_ISR - ePWM5 Interrupt -// -interrupt void -EPWM5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM6_ISR - ePWM6 Interrupt -// -interrupt void -EPWM6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM7_ISR - ePWM7 Interrupt -// -interrupt void -EPWM7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM8_ISR - ePWM8 Interrupt -// -interrupt void -EPWM8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP1_ISR - eCAP1 Interrupt -// -interrupt void -ECAP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP2_ISR - eCAP2 Interrupt -// -interrupt void -ECAP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP3_ISR - eCAP3 Interrupt -// -interrupt void -ECAP3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP4_ISR - eCAP4 Interrupt -// -interrupt void -ECAP4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP5_ISR - eCAP5 Interrupt -// -interrupt void -ECAP5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP6_ISR - eCAP6 Interrupt -// -interrupt void -ECAP6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP7_ISR - eCAP7 Interrupt -// -interrupt void -ECAP7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP6_2_ISR - eCAP6_2 Interrupt -// -interrupt void -ECAP6_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP7_2_ISR - eCAP7_2 Interrupt -// -interrupt void -ECAP7_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EQEP1_ISR - eQEP1 Interrupt -// -interrupt void -EQEP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EQEP2_ISR - eQEP2 Interrupt -// -interrupt void -EQEP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIA_RX_ISR - SPIA Receive Interrupt -// -interrupt void -SPIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIA_TX_ISR - SPIA Transmit Interrupt -// -interrupt void -SPIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIB_RX_ISR - SPIB Receive Interrupt -// -interrupt void -SPIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIB_TX_ISR - SPIB Transmit Interrupt -// -interrupt void -SPIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH1_ISR - DMA Channel 1 Interrupt -// -interrupt void -DMA_CH1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH2_ISR - DMA Channel 2 Interrupt -// -interrupt void -DMA_CH2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH3_ISR - DMA Channel 3 Interrupt -// -interrupt void -DMA_CH3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH4_ISR - DMA Channel 4 Interrupt -// -interrupt void -DMA_CH4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH5_ISR - DMA Channel 5 Interrupt -// -interrupt void -DMA_CH5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH6_ISR - DMA Channel 6 Interrupt -// -interrupt void -DMA_CH6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// I2CA_ISR - I2CA Interrupt 1 -// -interrupt void -I2CA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// I2CA_FIFO_ISR - I2CA Interrupt 2 -// -interrupt void -I2CA_FIFO_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIA_RX_ISR - SCIA Receive Interrupt -// -interrupt void -SCIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIA_TX_ISR - SCIA Transmit Interrupt -// -interrupt void -SCIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIB_RX_ISR - SCIB Receive Interrupt -// -interrupt void -SCIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIB_TX_ISR - SCIB Transmit Interrupt -// -interrupt void -SCIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANA0_ISR - CANA Interrupt 0 -// -interrupt void -CANA0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANA1_ISR - CANA Interrupt 1 -// -interrupt void -CANA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANB0_ISR - CANB Interrupt 0 -// -interrupt void -CANB0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANB1_ISR - CANB Interrupt 1 -// -interrupt void -CANB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA_EVT_ISR - ADCA Event Interrupt -// -interrupt void -ADCA_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA2_ISR - ADCA Interrupt 2 -// -interrupt void -ADCA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA3_ISR - ADCA Interrupt 3 -// -interrupt void -ADCA3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA4_ISR - ADCA Interrupt 4 -// -interrupt void -ADCA4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB_EVT_ISR - ADCB Event Interrupt -// -interrupt void -ADCB_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB2_ISR - ADCB Interrupt 2 -// -interrupt void -ADCB2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB3_ISR - ADCB Interrupt 3 -// -interrupt void -ADCB3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB4_ISR - ADCB Interrupt 4 -// -interrupt void -ADCB4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_1_ISR - CLA1 Interrupt 1 -// -interrupt void -CLA1_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_2_ISR - CLA1 Interrupt 2 -// -interrupt void -CLA1_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_3_ISR - CLA1 Interrupt 3 -// -interrupt void -CLA1_3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_4_ISR - CLA1 Interrupt 4 -// -interrupt void -CLA1_4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_5_ISR - CLA1 Interrupt 5 -// -interrupt void -CLA1_5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_6_ISR - CLA1 Interrupt 6 -// -interrupt void -CLA1_6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_7_ISR - CLA1 Interrupt 7 -// -interrupt void -CLA1_7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_8_ISR - CLA1 Interrupt 8 -// -interrupt void -CLA1_8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT3_ISR - XINT3 Interrupt -// -interrupt void -XINT3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT4_ISR - XINT4 Interrupt -// -interrupt void -XINT4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT5_ISR - XINT5 Interrupt -// -interrupt void -XINT5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FPU_OVERFLOW_ISR - FPU Overflow Interrupt -// -interrupt void -FPU_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FPU_UNDERFLOW_ISR - FPU Underflow Interrupt -// -interrupt void -FPU_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1_ISR - SDFM1 Interrupt -// -interrupt void -SD1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR1_ISR - SDFM1 DR Interrupt 1 -// -interrupt void -SD1DR1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR2_ISR - SDFM1 DR Interrupt 2 -// -interrupt void -SD1DR2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR3_ISR - SDFM1 DR Interrupt 3 -// -interrupt void -SD1DR3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR4_ISR - SDFM1 DR Interrupt 4 -// -interrupt void -SD1DR4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - - -// -// FSITXA1_ISR - FSITXA1_ISR Interrupt -// -interrupt void -FSITXA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSITXA2_ISR - FSITXA2_ISR Interrupt -// -interrupt void -FSITXA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSIRXA1_ISR - FSIRXA1_ISR Interrupt -// -interrupt void -FSIRXA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSIRXA2_ISR - FSIRXA2_ISR Interrupt -// -interrupt void -FSIRXA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1PROMCRC - CLA1PROMCRC Interrupt -// -interrupt void -CLA1PROMCRC_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// LINA_0 - LINA Interrupt 0 -// -interrupt void -LINA_0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// LINA_1 - LINA Interrupt 1 -// -interrupt void -LINA_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// PMBUSA - PMBUSA Interrupt -// -interrupt void -PMBUSA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC_EVT_ISR - ADCC Event Interrupt -// -interrupt void -ADCC_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC2_ISR - ADCC Interrupt 2 -// -interrupt void -ADCC2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC3_ISR - ADCC Interrupt 3 -// -interrupt void -ADCC3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC4_ISR - ADCC Interrupt 4 -// -interrupt void -ADCC4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RAM_CORRECTABLE_ERROR_ISR - RAM Correctable Error Interrupt -// -interrupt void -RAM_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FLASH_CORRECTABLE_ERROR_ISR - Flash Correctable Error Interrupt -// -interrupt void -FLASH_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RAM_ACCESS_VIOLATION_ISR - RAM Access Violation Interrupt -// -interrupt void -RAM_ACCESS_VIOLATION_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SYS_PLL_SLIP_ISR - System PLL Slip Interrupt -// -interrupt void -SYS_PLL_SLIP_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA_OVERFLOW_ISR - CLA Overflow Interrupt -// -interrupt void -CLA_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA_UNDERFLOW_ISR - CLA Underflow Interrupt -// -interrupt void -CLA_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Catch-all Default ISRs -// - -// -// PIE_RESERVED_ISR - Reserved ISR -// -interrupt void -PIE_RESERVED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// EMPTY_ISR - Only does a return -// -interrupt void -EMPTY_ISR(void) -{ - -} - -// -// NOTUSED_ISR - Unused ISR -// -interrupt void -NOTUSED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c b/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c deleted file mode 100644 index 3a245db..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c +++ /dev/null @@ -1,1104 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma.c -// -// TITLE: f28004x DMA Initialization & Support Functions. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "f28004x_device.h" -#include "f28004x_examples.h" - -// -// DMAInitialize - This function initializes the DMA to a known state. -// -void DMAInitialize(void) -{ - EALLOW; - - // - // Perform a hard reset on DMA - // - DmaRegs.DMACTRL.bit.HARDRESET = 1; - __asm (" nop"); // one NOP required after HARDRESET - - // - // Allow DMA to run free on emulation suspend - // - DmaRegs.DEBUGCTRL.bit.FREE = 1; - - EDIS; -} - -// -// DMACH1AddrConfig - DMA Channel 1 Address Configuration -// -void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to - // beginning of - // destination buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH1BurstConfig - DMA Channel 1 Burst size configuration -// -void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) - // x-ferred in a burst. - DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between - // each word x-ferred. - - EDIS; -} - -// -// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration -// -void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored - // when WRAP occurs. - DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored - // when WRAP occurs. - - EDIS; -} - -// -// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration -// -void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap - DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH1ModeConfig - DMA Channel 1 Mode configuration -// -void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; - DmaRegs.CH1.MODE.bit.PERINTSEL = 1; - DmaRegs.CH1.MODE.bit.PERINTE = perinte; - DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH1.MODE.bit.DATASIZE = datasize; - DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH1.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt and sync error flags - // - DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH1 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx1 = 1; - - EDIS; -} - -// -// StartDMACH1 - This function starts DMA Channel 1. -// -void StartDMACH1(void) -{ - EALLOW; - DmaRegs.CH1.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH2AddrConfig - DMA Channel 2 Address Configuration -// -void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer. - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2BurstConfig - DMA Channel 2 Burst size configuration -// -void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration -// -void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration -// -void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH2ModeConfig - DMA Channel 2 Mode configuration -// -void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; - DmaRegs.CH2.MODE.bit.PERINTSEL = 2; - DmaRegs.CH2.MODE.bit.PERINTE = perinte; - DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH2.MODE.bit.DATASIZE = datasize; - DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH2.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH2 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx2 = 1; - - EDIS; -} - -// -// StartDMACH2 - This function starts DMA Channel 2. -// -void StartDMACH2(void) -{ - EALLOW; - DmaRegs.CH2.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH3AddrConfig - DMA Channel 3 Address configuration -// -void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3BurstConfig - DMA Channel 3 burst size configuration -// -void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH3TransferConfig - DMA channel 3 transfer size configuration -// -void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH3WrapConfig - DMA Channel 3 wrap size configuration -// -void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH3ModeConfig - DMA Channel 3 mode configuration -// -void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; - DmaRegs.CH3.MODE.bit.PERINTSEL = 3; - DmaRegs.CH3.MODE.bit.PERINTE = perinte; - DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH3.MODE.bit.DATASIZE = datasize; - DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH3.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt flags and sync error flags - // - DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH3 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx3 = 1; - - EDIS; -} - -// -// StartDMACH3 - This function starts DMA Channel 3. -// -void StartDMACH3(void) -{ - EALLOW; - DmaRegs.CH3.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH4AddrConfig - DMA Channel 4 address configuration -// -void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4BurstConfig - DMA Channel 4 burst size configuration -// -void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH4TransferConfig - DMA channel 4 transfer size configuration -// -void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH4WrapConfig - DMA channel 4 wrap size configuration -// -void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH4ModeConfig - DMA Channel 4 mode configuration -// -void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; - DmaRegs.CH4.MODE.bit.PERINTSEL = 4; - DmaRegs.CH4.MODE.bit.PERINTE = perinte; - DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH4.MODE.bit.DATASIZE = datasize; - DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH4.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH4 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx4 = 1; - - EDIS; -} - -// -// StartDMACH4 - This function starts DMA Channel 4. -// -void StartDMACH4(void) -{ - EALLOW; - DmaRegs.CH4.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH5AddrConfig - DMA channel 5 address configuration -// -void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5BurstConfig - DMA Channel 5 burst size configuration -// -void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH5TransferConfig - DMA channel 5 transfer size configuration -// -void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH5WrapConfig - DMA Channel 5 wrap size configuration -// -void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH5ModeConfig - DMA Channel 5 mode configuration -// -void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; - DmaRegs.CH5.MODE.bit.PERINTSEL = 5; - DmaRegs.CH5.MODE.bit.PERINTE = perinte; - DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH5.MODE.bit.DATASIZE = datasize; - DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH5.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH5 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx5 = 1; - - EDIS; -} - -// -// StartDMACH5 - This function starts DMA Channel 5. -// -void StartDMACH5(void) -{ - EALLOW; - DmaRegs.CH5.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH6AddrConfig - DMA Channel 6 address configuration -// -void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6BurstConfig - DMA Channel 6 burst size configuration -// -void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH6TransferConfig - DMA channel 6 transfer size configuration -// -void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH6WrapConfig - DMA Channel 6 wrap size configuration -// -void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH6ModeConfig - DMA Channel 6 mode configuration -// -void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; - DmaRegs.CH6.MODE.bit.PERINTSEL = 6; - DmaRegs.CH6.MODE.bit.PERINTE = perinte; - DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH6.MODE.bit.DATASIZE = datasize; - DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH6.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH6 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx6 = 1; - - EDIS; -} - -// -// StartDMACH6 - This function starts DMA Channel 6. -// -void StartDMACH6(void) -{ - EALLOW; - DmaRegs.CH6.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit -// -void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit -// -void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit -// -void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit -// -void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; - // Point to beginning - // of destination - // buffer - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit -// -void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; - // Point to beginning - // of destination - // buffer - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit -// -void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c b/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c deleted file mode 100644 index 9f3573e..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c +++ /dev/null @@ -1,441 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio.c -// -// TITLE: f28004x GPIO module support functions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" -#include "f28004x_examples.h" - -// -// Low-level functions for GPIO configuration -// - -// -// InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups -// enabled.Also resets CPU control to CPU1 and disables open drain -// and polarity inversion and sets the qualification to synchronous. -// Also unlocks all GPIOs. Only one CPU should call this function. -// -void -InitGpio() -{ - volatile Uint32 *gpioBaseAddr; - Uint16 regOffset; - - // - // Disable pin locks - // - EALLOW; - GpioCtrlRegs.GPALOCK.all = 0x00000000; - GpioCtrlRegs.GPBLOCK.all = 0x00000000; - GpioCtrlRegs.GPHLOCK.all = 0x00000000; - - // - // Fill all registers with zeros. Writing to each register separately - // for three GPIO modules would make this function *very* long. - // Fortunately, we'd be writing them all with zeros anyway, - // so this saves a lot of space. - // - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; - for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) - { - // - // Must avoid enabling pull-ups on all pins. GPyPUD is offset - // 0x0C in each register group of 0x40 words. Since this is a - // 32-bit pointer, the addresses must be divided by 2. - // - // Also, to avoid changing pin muxing of the emulator pins to regular - // GPIOs, skip GPBMUX1 (0x46) and GPBGMUX1 (0x60). - // - if ((regOffset % (0x40/2) != (0x0C/2)) && (regOffset != (0x46/2)) && - (regOffset != (0x60/2))) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - } - - gpioBaseAddr = (Uint32 *)&GpioDataRegs; - for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - - EDIS; -} - -// -// GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. -// The appropriate parameters can be found in the pinout spreadsheet. -// -void -GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *mux, *gmux, *csel; - Uint16 pin32, pin16, pin8; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pin8 = gpioNumber % 8; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Sanity check for valid cpu and peripheral values - // - if (cpu > GPIO_MUX_CPU1CLA || muxPosition > 0xF) - { - return; - } - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyCSEL1-4. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - mux = gpioBaseAddr + GPYMUX + pin32/16; - gmux = gpioBaseAddr + GPYGMUX + pin32/16; - csel = gpioBaseAddr + GPYCSEL + pin32/8; - - // - // Now for the actual function - // - EALLOW; - - // - // To change the muxing, set the peripheral mux to 0/GPIO first to avoid - // glitches, then change the group mux, then set the peripheral mux to - // its target value. Finally, set the CPU select. This procedure is - // described in the TRM. Unfortunately, since we don't know the pin in - // advance we can't hardcode a bitfield reference, so there's some tricky - // bit twiddling here. - // - *mux &= ~(0x3UL << (2*pin16)); - *gmux &= ~(0x3UL << (2*pin16)); - *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); - *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); - - *csel &= ~(0x3L << (4*pin8)); - *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); - - // - // WARNING: This code does not touch the analog mode select registers. - // - - EDIS; -} - -// -// GPIO_SetupPinOptions - Setup up the GPIO input/output options for the -// specified pin. The flags are a 16-bit mask produced by ORing together -// options. For input pins, the valid flags are: -// GPIO_PULLUP Enable pull-up -// GPIO_INVERT Enable input polarity inversion -// GPIO_SYNC Synchronize the input latch to PLLSYSCLK -// (default -- you don't need to specify this) -// GPIO_QUAL3 Use 3-sample qualification -// GPIO_QUAL6 Use 6-sample qualification -// GPIO_ASYNC Do not use synchronization or qualification -// (Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) -// -// For output pins, the valid flags are: -// GPIO_OPENDRAIN Output in open drain mode -// GPIO_PULLUP If open drain enabled, also enable the pull-up -// and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. -// -// With no flags, the default input state is synchronous with no -// pull-up or polarity inversion. The default output state is -// the standard digital output. -// -void -GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *dir, *pud, *inv, *odr, *qsel; - Uint32 pin32, pin16, pinMask, qual; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyQSEL1-2. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - dir = gpioBaseAddr + GPYDIR; - pud = gpioBaseAddr + GPYPUD; - inv = gpioBaseAddr + GPYINV; - odr = gpioBaseAddr + GPYODR; - qsel = gpioBaseAddr + GPYQSEL + pin32/16; - - EALLOW; - - // - // Set the data direction - // - *dir &= ~pinMask; - if (output == 1) - { - // - // Output, with optional open drain mode and pull-up - // - *dir |= pinMask; - - // - // Enable open drain if necessary - // - if (flags & GPIO_OPENDRAIN) - { - *odr |= pinMask; - } - else - { - *odr &= ~pinMask; - } - - // - // Enable pull-up if necessary. Open drain mode must be active. - // - if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - } - - else - { - // - // Input, with optional pull-up, qualification, and polarity inversion - // - *dir &= ~pinMask; - - // - // Enable pull-up if necessary - // - if (flags & GPIO_PULLUP) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - - // - // Invert polarity if necessary - // - if (flags & GPIO_INVERT) - { - *inv |= pinMask; - } - else - { - *inv &= ~pinMask; - } - } - - // - // Extract the qualification parameter and load it into the register. - // This is also needed for open drain outputs, so we might as well do it - // all the time. - // - qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; - *qsel &= ~(0x3L << (2 * pin16)); - if (qual != 0x0) - { - *qsel |= qual << (2 * pin16); - } - - EDIS; -} - -// -// GPIO_SetupLock - Enable or disable the GPIO register bit lock for the -// specified pin. The valid flags are: -// GPIO_UNLOCK Unlock the pin setup register bits for the specified pin -// GPIO_LOCK Lock the pin setup register bits for the specified pin -// -void -GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *lock; - Uint32 pin32, pinMask; - - pin32 = gpioNumber % 32; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyQSEL1-2. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - lock = gpioBaseAddr + GPYLOCK; - - EALLOW; - - if(flags) - { - // - // Lock the pin - // - *lock |= pinMask; - } - - else - { - // - // Unlock the pin - // - *lock &= ~pinMask; - } - EDIS; -} - -// -// External interrupt setup -// -void -GPIO_SetupXINT1Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT4SELECT = gpioNumber; // Set XINT1 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT2Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT5SELECT = gpioNumber; // Set XINT2 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT3Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT6SELECT = gpioNumber; // Set XINT3 source to GPIO-pin - EDIS; -} -void -GPIO_SetupXINT4Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT13SELECT = gpioNumber; // Set XINT4 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT5Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT14SELECT = gpioNumber; // Set XINT5 source to GPIO-pin - EDIS; -} - -// -// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. -// Note that this returns the actual state of the pin, not the state of the -// output latch. -// -Uint16 -GPIO_ReadPin(Uint16 gpioNumber) -{ - volatile Uint32 *gpioDataReg; - Uint16 pinVal; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; - - return pinVal; -} - -// -// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. -// -void -GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) -{ - volatile Uint32 *gpioDataReg; - Uint32 pinMask; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinMask = 1UL << (gpioNumber % 32); - - if (outVal == 0) - { - gpioDataReg[GPYCLEAR] = pinMask; - } - - else - { - gpioDataReg[GPYSET] = pinMask; - } -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c b/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c deleted file mode 100644 index 624955d..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c +++ /dev/null @@ -1,124 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_piectrl.c -// -// TITLE: f28004x Device PIE Control Register Initialization Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // f28004x Headerfile Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -// -// InitPieCtrl - This function initializes the PIE control registers -// to a known state. -// -void -InitPieCtrl(void) -{ - // - // Disable Interrupts at the CPU level: - // - DINT; - - // - // Disable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 0; - - // - // Clear all PIEIER registers: - // - PieCtrlRegs.PIEIER1.all = 0; - PieCtrlRegs.PIEIER2.all = 0; - PieCtrlRegs.PIEIER3.all = 0; - PieCtrlRegs.PIEIER4.all = 0; - PieCtrlRegs.PIEIER5.all = 0; - PieCtrlRegs.PIEIER6.all = 0; - PieCtrlRegs.PIEIER7.all = 0; - PieCtrlRegs.PIEIER8.all = 0; - PieCtrlRegs.PIEIER9.all = 0; - PieCtrlRegs.PIEIER10.all = 0; - PieCtrlRegs.PIEIER11.all = 0; - PieCtrlRegs.PIEIER12.all = 0; - - // - // Clear all PIEIFR registers: - // - PieCtrlRegs.PIEIFR1.all = 0; - PieCtrlRegs.PIEIFR2.all = 0; - PieCtrlRegs.PIEIFR3.all = 0; - PieCtrlRegs.PIEIFR4.all = 0; - PieCtrlRegs.PIEIFR5.all = 0; - PieCtrlRegs.PIEIFR6.all = 0; - PieCtrlRegs.PIEIFR7.all = 0; - PieCtrlRegs.PIEIFR8.all = 0; - PieCtrlRegs.PIEIFR9.all = 0; - PieCtrlRegs.PIEIFR10.all = 0; - PieCtrlRegs.PIEIFR11.all = 0; - PieCtrlRegs.PIEIFR12.all = 0; -} - -// -// EnableInterrupts - This function enables the PIE module and CPU __interrupts -// -void -EnableInterrupts() -{ - // - // Enable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; - - // - // Enables PIE to drive a pulse into the CPU - // - PieCtrlRegs.PIEACK.all = 0xFFFF; - - // - // Enable Interrupts at the CPU level - // - EINT; -} - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c b/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c deleted file mode 100644 index 467f60f..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c +++ /dev/null @@ -1,315 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pievect.c -// -// TITLE: f28004x Device PIE Vector Initialization Functions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // f28004x Header File Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -// -// Define PIE Vector Table: -// -const struct PIE_VECT_TABLE PieVectTableInit = { - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - TIMER1_ISR, // CPU Timer 1 Interrupt - TIMER2_ISR, // CPU Timer 2 Interrupt - DATALOG_ISR, // Datalogging Interrupt - RTOS_ISR, // RTOS Interrupt - EMU_ISR, // Emulation Interrupt - NMI_ISR, // Non-Maskable Interrupt - ILLEGAL_ISR, // Illegal Operation Trap - USER1_ISR, // User Defined Trap 1 - USER2_ISR, // User Defined Trap 2 - USER3_ISR, // User Defined Trap 3 - USER4_ISR, // User Defined Trap 4 - USER5_ISR, // User Defined Trap 5 - USER6_ISR, // User Defined Trap 6 - USER7_ISR, // User Defined Trap 7 - USER8_ISR, // User Defined Trap 8 - USER9_ISR, // User Defined Trap 9 - USER10_ISR, // User Defined Trap 10 - USER11_ISR, // User Defined Trap 11 - USER12_ISR, // User Defined Trap 12 - ADCA1_ISR, // 1.1 - ADCA Interrupt 1 - ADCB1_ISR, // 1.2 - ADCB Interrupt 1 - ADCC1_ISR, // 1.3 - ADCC Interrupt 1 - XINT1_ISR, // 1.4 - XINT1 Interrupt - XINT2_ISR, // 1.5 - XINT2 Interrupt - PIE_RESERVED_ISR, // 1.6 - Reserved - TIMER0_ISR, // 1.7 - Timer 0 Interrupt - WAKE_ISR, // 1.8 - Halt Wakeup Interrupt - EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt - EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt - EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt - EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt - EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt - EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt - EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt - EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt - EPWM1_ISR, // 3.1 - ePWM1 Interrupt - EPWM2_ISR, // 3.2 - ePWM2 Interrupt - EPWM3_ISR, // 3.3 - ePWM3 Interrupt - EPWM4_ISR, // 3.4 - ePWM4 Interrupt - EPWM5_ISR, // 3.5 - ePWM5 Interrupt - EPWM6_ISR, // 3.6 - ePWM6 Interrupt - EPWM7_ISR, // 3.7 - ePWM7 Interrupt - EPWM8_ISR, // 3.8 - ePWM8 Interrupt - ECAP1_ISR, // 4.1 - eCAP1 Interrupt - ECAP2_ISR, // 4.2 - eCAP2 Interrupt - ECAP3_ISR, // 4.3 - eCAP3 Interrupt - ECAP4_ISR, // 4.4 - eCAP4 Interrupt - ECAP5_ISR, // 4.5 - eCAP5 Interrupt - ECAP6_ISR, // 4.6 - eCAP6 Interrupt - ECAP7_ISR, // 4.7 - eCAP7 Interrupt - PIE_RESERVED_ISR, // 4.8 - Reserved - EQEP1_ISR, // 5.1 - eQEP1 Interrupt - EQEP2_ISR, // 5.2 - eQEP2 Interrupt - PIE_RESERVED_ISR, // 5.3 - Reserved - PIE_RESERVED_ISR, // 5.4 - Reserved - PIE_RESERVED_ISR, // 5.5 - Reserved - PIE_RESERVED_ISR, // 5.6 - Reserved - PIE_RESERVED_ISR, // 5.7 - Reserved - PIE_RESERVED_ISR, // 5.8 - Reserved - SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt - SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt - SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt - SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt - PIE_RESERVED_ISR, // 6.5 - Reserved - PIE_RESERVED_ISR, // 6.6 - Reserved - PIE_RESERVED_ISR, // 6.7 - Reserved - PIE_RESERVED_ISR, // 6.8 - Reserved - DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt - DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt - DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt - DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt - DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt - DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt - PIE_RESERVED_ISR, // 7.7 - Reserved - PIE_RESERVED_ISR, // 7.8 - Reserved - I2CA_ISR, // 8.1 - I2CA Interrupt 1 - I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 - PIE_RESERVED_ISR, // 8.3 - Reserved - PIE_RESERVED_ISR, // 8.4 - Reserved - PIE_RESERVED_ISR, // 8.5 - Reserved - PIE_RESERVED_ISR, // 8.6 - Reserved - PIE_RESERVED_ISR, // 8.7 - Reserved - PIE_RESERVED_ISR, // 8.8 - Reserved - SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt - SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt - SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt - SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt - CANA0_ISR, // 9.5 - CANA Interrupt 0 - CANA1_ISR, // 9.6 - CANA Interrupt 1 - CANB0_ISR, // 9.7 - CANB Interrupt 0 - CANB1_ISR, // 9.8 - CANB Interrupt 1 - ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt - ADCA2_ISR, // 10.2 - ADCA Interrupt 2 - ADCA3_ISR, // 10.3 - ADCA Interrupt 3 - ADCA4_ISR, // 10.4 - ADCA Interrupt 4 - ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt - ADCB2_ISR, // 10.6 - ADCB Interrupt 2 - ADCB3_ISR, // 10.7 - ADCB Interrupt 3 - ADCB4_ISR, // 10.8 - ADCB Interrupt 4 - CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 - CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 - CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 - CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 - CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 - CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 - CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 - CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 - XINT3_ISR, // 12.1 - XINT3 Interrupt - XINT4_ISR, // 12.2 - XINT4 Interrupt - XINT5_ISR, // 12.3 - XINT5 Interrupt - PIE_RESERVED_ISR, // 12.4 - Reserved - PIE_RESERVED_ISR, // 12.5 - Reserved - PIE_RESERVED_ISR, // 12.6 - Reserved - FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt - FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt - PIE_RESERVED_ISR, // 1.9 - Reserved - PIE_RESERVED_ISR, // 1.10 - Reserved - PIE_RESERVED_ISR, // 1.11 - Reserved - PIE_RESERVED_ISR, // 1.12 - Reserved - PIE_RESERVED_ISR, // 1.13 - Reserved - PIE_RESERVED_ISR, // 1.14 - Reserved - PIE_RESERVED_ISR, // 1.15 - Reserved - PIE_RESERVED_ISR, // 1.16 - Reserved - PIE_RESERVED_ISR, // 2.9 - Reserved - PIE_RESERVED_ISR, // 2.10 - Reserved - PIE_RESERVED_ISR, // 2.11 - Reserved - PIE_RESERVED_ISR, // 2.12 - Reserved - PIE_RESERVED_ISR, // 2.13 - Reserved - PIE_RESERVED_ISR, // 2.14 - Reserved - PIE_RESERVED_ISR, // 2.15 - Reserved - PIE_RESERVED_ISR, // 2.16 - Reserved - PIE_RESERVED_ISR, // 3.9 - Reserved - PIE_RESERVED_ISR, // 3.10 - Reserved - PIE_RESERVED_ISR, // 3.11 - Reserved - PIE_RESERVED_ISR, // 3.12 - Reserved - PIE_RESERVED_ISR, // 3.13 - Reserved - PIE_RESERVED_ISR, // 3.14 - Reserved - PIE_RESERVED_ISR, // 3.15 - Reserved - PIE_RESERVED_ISR, // 3.16 - Reserved - PIE_RESERVED_ISR, // 4.9 - Reserved - PIE_RESERVED_ISR, // 4.10 - Reserved - PIE_RESERVED_ISR, // 4.11 - Reserved - PIE_RESERVED_ISR, // 4.12 - Reserved - PIE_RESERVED_ISR, // 4.13 - Reserved - ECAP6_2_ISR, // 4.14 - eCAP6_2 Interrupt - ECAP7_2_ISR, // 4.15 - eCAP7_2 Interrupt - PIE_RESERVED_ISR, // 4.16 - Reserved - SD1_ISR, // 5.9 - SD1 Interrupt - PIE_RESERVED_ISR, // 5.10 - Reserved - PIE_RESERVED_ISR, // 5.11 - Reserved - PIE_RESERVED_ISR, // 5.12 - Reserved - SD1DR1_ISR, // 5.13 - SD1DR1 Interrupt - SD1DR2_ISR, // 5.14 - SD1DR2 Interrupt - SD1DR3_ISR, // 5.15 - SD1DR3 Interrupt - SD1DR4_ISR, // 5.16 - SD1DR4 Interrupt - PIE_RESERVED_ISR, // 6.9 - Reserved - PIE_RESERVED_ISR, // 6.10 - Reserved - PIE_RESERVED_ISR, // 6.11 - Reserved - PIE_RESERVED_ISR, // 6.12 - Reserved - PIE_RESERVED_ISR, // 6.13 - Reserved - PIE_RESERVED_ISR, // 6.14 - Reserved - PIE_RESERVED_ISR, // 6.15 - Reserved - PIE_RESERVED_ISR, // 6.16 - Reserved - PIE_RESERVED_ISR, // 7.9 - Reserved - PIE_RESERVED_ISR, // 7.10 - Reserved - FSITXA1_ISR, // 7.11 - FSITXA1 Interrupt - FSITXA2_ISR, // 7.12 - FSITXA2 Interrupt - FSIRXA1_ISR, // 7.13 - FSIRXA1 Interrupt - FSIRXA2_ISR, // 7.14 - FSIRXA2 Interrupt - CLA1PROMCRC_ISR, // 7.15 - CLA1PROMCRC Interrupt - PIE_RESERVED_ISR, // 7.16 - Reserved - LINA_0_ISR, // 8.9 - LINA Interrupt0 - LINA_1_ISR, // 8.10 - LINA Interrupt1 - PIE_RESERVED_ISR, // 8.11 - Reserved - PIE_RESERVED_ISR, // 8.12 - Reserved - PMBUSA_ISR, // 8.13 - PMBUSA Interrupt - PIE_RESERVED_ISR, // 8.14 - Reserved - PIE_RESERVED_ISR, // 8.15 - Reserved - PIE_RESERVED_ISR, // 8.16 - Reserved - PIE_RESERVED_ISR, // 9.9 - Reserved - PIE_RESERVED_ISR, // 9.10 - Reserved - PIE_RESERVED_ISR, // 9.11 - Reserved - PIE_RESERVED_ISR, // 9.12 - Reserved - PIE_RESERVED_ISR, // 9.13 - Reserved - PIE_RESERVED_ISR, // 9.14 - Reserved - PIE_RESERVED_ISR, // 9.15 - Reserved - PIE_RESERVED_ISR, // 9.16 - Reserved - ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt - ADCC2_ISR, // 10.10 - ADCC Interrupt 2 - ADCC3_ISR, // 10.11 - ADCC Interrupt 3 - ADCC4_ISR, // 10.12 - ADCC Interrupt 4 - PIE_RESERVED_ISR, // 10.13 - Reserved - PIE_RESERVED_ISR, // 10.14 - Reserved - PIE_RESERVED_ISR, // 10.15 - Reserved - PIE_RESERVED_ISR, // 10.16 - Reserved - PIE_RESERVED_ISR, // 11.9 - Reserved - PIE_RESERVED_ISR, // 11.10 - Reserved - PIE_RESERVED_ISR, // 11.11 - Reserved - PIE_RESERVED_ISR, // 11.12 - Reserved - PIE_RESERVED_ISR, // 11.13 - Reserved - PIE_RESERVED_ISR, // 11.14 - Reserved - PIE_RESERVED_ISR, // 11.15 - Reserved - PIE_RESERVED_ISR, // 11.16 - Reserved - PIE_RESERVED_ISR, // 12.9 - Reserved - RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt - FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt - RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt - SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt - PIE_RESERVED_ISR, // 12.14 - Reserved - CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt - CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt -}; - -// -// InitPieVectTable - This function initializes the PIE vector table to a known -// state. This function must be executed after boot time. -// -void -InitPieVectTable(void) -{ - Uint16 i; - Uint32 *Source = (void *) &PieVectTableInit; - Uint32 *Dest = (void *) &PieVectTable; - - // - // Do not write over first 3 32-bit locations (these locations are - // initialized by Boot ROM with boot variables) - // - Source = Source + 3; - Dest = Dest + 3; - - EALLOW; - - for(i = 0; i < 221; i++) - { - *Dest++ = *Source++; - } - - EDIS; - - // - // Enable the PIE Vector Table - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c b/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c deleted file mode 100644 index 75b951c..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c +++ /dev/null @@ -1,177 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_Spi.c -// -// TITLE: f28004x SPI Initialization & Support Functions. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File - -// -// Calculate BRR: 7-bit baud rate register value -// SPI CLK freq = 500 kHz -// LSPCLK freq = CPU freq / 4 (by default) -// BRR = (LSPCLK freq / SPI CLK freq) - 1 -// -#if CPU_FRQ_100MHZ -#define SPI_BRR ((100E6 / 4) / 500E3) - 1 -#endif - -// -// InitSPI - This function initializes the SPI to a known state -// -void InitSpi(void) -{ - // - // Initialize SPI-A - // - // Set reset low before configuration changes - // Clock polarity (0 == rising, 1 == falling) - // 16-bit character - // Enable loop-back - // - SpiaRegs.SPICCR.bit.SPISWRESET = 0; - SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; - SpiaRegs.SPICCR.bit.SPICHAR = (16-1); - SpiaRegs.SPICCR.bit.SPILBK = 1; - - // - // Enable master (0 == slave, 1 == master) - // Enable transmission (Talk) - // Clock phase (0 == normal, 1 == delayed) - // SPI interrupts are disabled - // - SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; - SpiaRegs.SPICTL.bit.TALK = 1; - SpiaRegs.SPICTL.bit.CLK_PHASE = 0; - SpiaRegs.SPICTL.bit.SPIINTENA = 0; - - // - // Set the baud rate - // - SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; - - // - // Set FREE bit - // Halting on a breakpoint will not halt the SPI - // - SpiaRegs.SPIPRI.bit.FREE = 1; - - // - // Release the SPI from reset - // - SpiaRegs.SPICCR.bit.SPISWRESET = 1; -} - -// -// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. -// Each GPIO pin can be configured as a GPIO pin or up to 3 -// different peripheral functional pins. By default all pins come -// up as GPIO inputs after reset. -// -// Caution: -// For each SPI peripheral -// Only one GPIO pin should be enabled for SPISOMO operation. -// Only one GPIO pin should be enabled for SPISOMI operation. -// Only one GPIO pin should be enabled for SPICLK operation. -// Only one GPIO pin should be enabled for SPISTE operation. -// Comment out other unwanted lines. -// -void InitSpiGpio() -{ - InitSpiaGpio(); -} - -// -// InitSpiaGpio - Initialize SPIA GPIOs -// -void InitSpiaGpio() -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) - // GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) - // GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) - GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) - // GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) - // GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) - - // - //Configure SPI-A pins using GPIO regs - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA - // GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA - GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA - // GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA - GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA - GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA - - EDIS; -} - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c b/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c deleted file mode 100644 index 542c0cd..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c +++ /dev/null @@ -1,876 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl.c -// -// TITLE: f28004x Device System Control Initialization & Support Functions. -// -// DESCRIPTION: Example initialization of system resources. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File -#ifdef __cplusplus -using std::memcpy; -#endif - -// -// Functions that will be run from RAM need to be assigned to -// a different section. This section will then be mapped to a load and -// run address using the linker cmd file. -// -// *IMPORTANT* -// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM FLASH -// TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM THROWING -// AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. -// -#ifndef __cplusplus -#pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); -#pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); -#endif - -// -// The following values are used to validate PLL Frequency using DCC -// -#define PLL_RETRIES 100 -#define PLL_LOCK_TIMEOUT 2000 -#define DCC_COUNTER0_WINDOW 100 - -// -// InitSysCtrl - -// -void -InitSysCtrl(void) -{ - // - // Disable the watchdog - // - DisableDog(); - -#ifdef _FLASH - // - // Copy time critical code and Flash setup code to RAM - // This includes the following functions: InitFlash(); - // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart - // symbols are created by the linker. Refer to the device .cmd file. - // - memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); -#endif - - // - // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) - // - InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2); - - // - // Call Flash Initialization to setup flash waitstates - // This function must reside in RAM - // - InitFlash(); - - // - // Turn on all peripherals - // - InitPeripheralClocks(); -} - -// -// InitPeripheralClocks - This function initializes the clocks for the -// peripherals. Note: In order to reduce power consumption, turn off the -// clocks to any peripheral that is not specified for your part-number or is -// not used in the application -// -void -InitPeripheralClocks() -{ - EALLOW; - - CpuSysRegs.PCLKCR0.bit.CLA1 = 1; - CpuSysRegs.PCLKCR0.bit.DMA = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; - CpuSysRegs.PCLKCR0.bit.HRPWM = 1; - CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; - - CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; - - CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP7 = 1; - - CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; - CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; - - CpuSysRegs.PCLKCR6.bit.SD1 = 1; - - CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - CpuSysRegs.PCLKCR7.bit.SCI_B = 1; - - CpuSysRegs.PCLKCR8.bit.SPI_A = 1; - CpuSysRegs.PCLKCR8.bit.SPI_B = 1; - - CpuSysRegs.PCLKCR9.bit.I2C_A = 1; - - CpuSysRegs.PCLKCR10.bit.CAN_A = 1; - CpuSysRegs.PCLKCR10.bit.CAN_B = 1; - - CpuSysRegs.PCLKCR13.bit.ADC_A = 1; - CpuSysRegs.PCLKCR13.bit.ADC_B = 1; - CpuSysRegs.PCLKCR13.bit.ADC_C = 1; - - CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; - - CpuSysRegs.PCLKCR15.bit.PGA1 = 1; - CpuSysRegs.PCLKCR15.bit.PGA2 = 1; - CpuSysRegs.PCLKCR15.bit.PGA3 = 1; - CpuSysRegs.PCLKCR15.bit.PGA4 = 1; - CpuSysRegs.PCLKCR15.bit.PGA5 = 1; - CpuSysRegs.PCLKCR15.bit.PGA6 = 1; - CpuSysRegs.PCLKCR15.bit.PGA7 = 1; - - CpuSysRegs.PCLKCR16.bit.DAC_A = 1; - CpuSysRegs.PCLKCR16.bit.DAC_B = 1; - - CpuSysRegs.PCLKCR19.bit.LIN_A = 1; - - CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1; - - CpuSysRegs.PCLKCR21.bit.DCC_0 = 1; - - EDIS; -} - -// -// DisablePeripheralClocks - -// -void -DisablePeripheralClocks() -{ - EALLOW; - - CpuSysRegs.PCLKCR0.all = 0; - CpuSysRegs.PCLKCR2.all = 0; - CpuSysRegs.PCLKCR3.all = 0; - CpuSysRegs.PCLKCR4.all = 0; - CpuSysRegs.PCLKCR6.all = 0; - CpuSysRegs.PCLKCR7.all = 0; - CpuSysRegs.PCLKCR8.all = 0; - CpuSysRegs.PCLKCR9.all = 0; - CpuSysRegs.PCLKCR10.all = 0; - CpuSysRegs.PCLKCR13.all = 0; - CpuSysRegs.PCLKCR14.all = 0; - CpuSysRegs.PCLKCR15.all = 0; - CpuSysRegs.PCLKCR16.all = 0; - CpuSysRegs.PCLKCR19.all = 0; - CpuSysRegs.PCLKCR20.all = 0; - CpuSysRegs.PCLKCR21.all = 0; - - EDIS; -} - -// -// InitFlash - This function initializes the Flash Control registers -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -#ifdef __cplusplus -#pragma CODE_SECTION(".TI.ramfunc"); -#endif -void -InitFlash(void) -{ - EALLOW; - - // - // At reset bank and pump are in sleep - // A Flash access will power up the bank and pump automatically - // After a Flash access, bank and pump go to low power mode (configurable - // in FBFALLBACK/FPAC1 registers)- if there is no further access to flash - // Power up Flash bank and pump and this also sets the fall back mode of - // flash and pump as active - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0x3; - - // - // Disable Cache and prefetch mechanism before changing wait states - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; - - // - // Set waitstates according to frequency - // CAUTION - // Minimum waitstates required for the flash operating - // at a given CPU rate must be characterized by TI. - // Refer to the datasheet for the latest information. - // -#if CPU_FRQ_100MHZ - if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x0) || - (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x2) || - (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x3)) - { - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x5; - } - else - { - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x4; - } -#endif - - // - // Enable Cache and prefetch mechanism to improve performance - // of code executed from Flash. - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; - - // - // At reset, ECC is enabled. If it is disabled by application software - // and if application again wants to enable ECC - // - Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; - - EDIS; - - // - // Force a pipeline flush to ensure that the write to - // the last register configured occurs before returning. - // - __asm(" RPT #7 || NOP"); -} - -// -// FlashOff - This function powers down the flash -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results. -// Note: a flash access after the flash pump and banks are powered down will -// wake the pump and bank -// -#ifdef __cplusplus -#pragma CODE_SECTION(".TI.ramfunc"); -#endif -void -FlashOff(void) -{ - EALLOW; - - // - // Configure the fallback power mode as sleep - // - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0; - - // - // Configure the fallback power mode as sleep - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; - - EDIS; -} - -// -// ServiceDog - This function resets the watchdog timer. -// Enable this function for using ServiceDog in the application -// -void -ServiceDog(void) -{ - EALLOW; - WdRegs.WDKEY.bit.WDKEY = 0x0055; - WdRegs.WDKEY.bit.WDKEY = 0x00AA; - EDIS; -} - -// -// DisableDog - This function disables the watchdog timer. -// -void -DisableDog(void) -{ - volatile Uint16 temp; - EALLOW; - - // - // Grab the clock config so we don't clobber it - // - temp = WdRegs.WDCR.all & 0x0007; - WdRegs.WDCR.all = 0x0068 | temp; - EDIS; -} - -// -// InitPll - This function initializes the PLL registers. -// -// Note: This function uses the DCC to check that the PLLRAWCLK is running at -// the expected rate. If you are using the DCC, you must back up its -// configuration before calling this function and restore it afterward. -// -void -InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) -{ - Uint32 timeout, retries, temp_syspllmult, pllLockStatus; - bool status; - - if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && - (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && - (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && - (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && - (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) - { - // - // Everything is set as required, so just return - // - return; - } - - if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) || - (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE)) - { - switch (clock_source) - { - case INT_OSC1: - SysIntOsc1Sel(); - break; - - case INT_OSC2: - SysIntOsc2Sel(); - break; - - case XTAL_OSC: - SysXtalOscSel(); - break; - - case XTAL_OSC_SE: - SysXtalOscSESel(); - break; - } - } - - EALLOW; - - // - // First modify the PLL multipliers - // - if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || - fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) - { - // - // Bypass PLL and set dividers to /1 - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; - - // - // Evaluate PLL multipliers - // - temp_syspllmult = ((fmult << 8U) | imult); - - // - // Loop to retry locking the PLL should the DCC module indicate - // that it was not successful. - // - for(retries = 0; (retries < PLL_RETRIES); retries++) - { - // - // Bypass PLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - - // - // Program PLL multipliers - // - ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult; - - // - // Enable SYSPLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; - - timeout = PLL_LOCK_TIMEOUT; - pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; - - // - // Wait for the SYSPLL lock - // - while((pllLockStatus != 1) && (timeout != 0U)) - { - pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; - timeout--; - } - - EDIS; - - status = IsPLLValid(clock_source, imult, fmult); - - // - // Check DCC Status, if no error break the loop - // - if(status) - { - break; - } - } - } - else - { - status = true; - } - - if(status) - { - EALLOW; - // - // Set divider to produce slower output frequency to limit current increase - // - if(divsel != PLLCLK_BY_126) - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; - } - else - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - } - - // - // Enable PLLSYSCLK is fed from system PLL clock - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; - - // - // Small 100 cycle delay - // - asm(" RPT #100 || NOP"); - - // - // Set the divider to user value - // - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - EDIS; - } -} - -// -// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with -// current password for the DSP. -// -Uint16 -CsmUnlock() -{ - // - // Write to the key registers to unlock the device. The 0x0FFFFFFFF's - // are dummmy passwords. User should replace them with the correct password - // for the DSP. - // Note: F28004x has default password keys which are not all 0xFFFFFFFF. - // See DCSM chapter of Technical Reference Manual for default passwords. - EALLOW; - - DcsmBank0Z1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; - - DcsmBank0Z2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; - EDIS; - - return 0; -} - -// -// SysIntOsc1Sel - This function switches to Internal Oscillator 1 and turns -// off all other clock sources to minimize power consumption -// -void -SysIntOsc1Sel (void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 - ClkCfgRegs.XTALCR.bit.OSCOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// SysIntOsc2Sel - This function switches to Internal oscillator 2 from -// External Oscillator and turns off all other clock sources to minimize -// power consumption -// NOTE: If there is no external clock connection, when switching from -// INTOSC1 to INTOSC2, EXTOSC and XLCKIN must be turned OFF prior -// to switching to internal oscillator 1 -// -void -SysIntOsc2Sel (void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 - ClkCfgRegs.XTALCR.bit.OSCOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate -// four times. -// -static void -PollX1Counter(void) -{ - Uint16 loopCount = 0; - - // - // Delay for 1 ms while the XTAL powers up - // - // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles - // - F28x_usDelay(2000); - - // - // Clear and saturate X1CNT 4 times to guarantee operation - // - do - { - // - // Keep clearing the counter until it is no longer saturated - // - while(ClkCfgRegs.X1CNT.all > 0x1FF) - { - ClkCfgRegs.X1CNT.bit.CLR = 1; - } - - // - // Wait for the X1 clock to saturate - // - while(ClkCfgRegs.X1CNT.all != 0x3FFU) - { - ; - } - - // - // Increment the counter - // - loopCount++; - }while(loopCount < 4); -} - -// -// SysXtalOscSel - This function switches to External CRYSTAL oscillator and -// turns off all other clock sources to minimize power consumption. This option -// may not be available on all device packages -// -void -SysXtalOscSel (void) -{ - EALLOW; - ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC - ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTAL as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - - // - // If a missing clock failure was detected, try waiting for the X1 counter - // to saturate again. Consider modifying this code to add a 10ms timeout. - // - while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) - { - EALLOW; - ClkCfgRegs.MCDCR.bit.MCLKCLR = 1; - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTAL as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - } -} - -// -// SysXtalOscSESel - This function switches to external oscillator in -// single-ended mode and turns off all other clock sources to minimize power -// consumption. This option may not be available on all device packages -// -void -SysXtalOscSESel (void) -{ - EALLOW; - ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC - ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTALOSC as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - - // - // If missing clock detected, there is something wrong with the oscillator - // module. - // - if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) - { - ESTOP0; - } -} - -// -// IDLE - Enter IDLE mode -// -void -IDLE() -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; - EDIS; - asm(" IDLE"); -} - -// -// HALT - Enter HALT mode -// -void -HALT() -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - EDIS; - asm(" IDLE"); -} - -//***************************************************************************** -// -// SysCtl_isPLLValid() -// -//***************************************************************************** -bool -IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult) -{ - Uint32 dccCounterSeed0, dccCounterSeed1, dccValidSeed0; - - // - // Setting Counter0 & Valid Seed Value with +/-2% tolerance - // - dccCounterSeed0 = DCC_COUNTER0_WINDOW - 2U; - dccValidSeed0 = 4U; - - // - // Multiplying Counter-0 window with PLL Integer Multiplier - // - dccCounterSeed1 = DCC_COUNTER0_WINDOW * imult; - - // - // Multiplying Counter-0 window with PLL Fractional Multiplier - // - switch(fmult) - { - case FMULT_0pt25: - // - // FMULT * CNTR0 Window = 0.25 * 100 = 25, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 25U; - break; - case FMULT_0pt5: - // - // FMULT * CNTR0 Window = 0.5 * 100 = 50, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 50U; - break; - case FMULT_0pt75: - // - // FMULT * CNTR0 Window = 0.75 * 100 = 75, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 75U; - break; - default: - // - // No fractional multiplier - // - dccCounterSeed1 = dccCounterSeed1; - break; - } - - // - // Enable Peripheral Clock Domain PCLKCR21 for DCC - // - EALLOW; - CpuSysRegs.PCLKCR21.bit.DCC_0 = 1; - - // - // Clear Error & Done Flag - // - Dcc0Regs.DCCSTATUS.bit.ERR = 1; - Dcc0Regs.DCCSTATUS.bit.DONE = 1; - - // - // Disable DCC - // - Dcc0Regs.DCCGCTRL.bit.DCCENA = 0x5; - - // - // Disable Error Signal - // - Dcc0Regs.DCCGCTRL.bit.ERRENA = 0x5; - - // - // Disable Done Signal - // - Dcc0Regs.DCCGCTRL.bit.DONEENA = 0x5; - - // - // Configure Clock Source0 to whatever is set as a clock source for PLL - // - switch(oscSource) - { - case INT_OSC1: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 1; // Clk Src0 = INTOSC1 - break; - - case INT_OSC2: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 2; // Clk Src0 = INTOSC2 - break; - - case XTAL_OSC: - case XTAL_OSC_SE: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 0; // Clk Src0 = XTAL - break; - } - - // - // Configure Clock Source1 to PLL - // - Dcc0Regs.DCCCLKSRC1.bit.KEY = 0xA; // Clk Src1 Key to enable clock source selection for count1 - Dcc0Regs.DCCCLKSRC1.bit.CLKSRC1 = 0; // Clk Src1 = PLL - - // - // Configure COUNTER-0, COUNTER-1 & Valid Window - // - Dcc0Regs.DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value - Dcc0Regs.DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0; // Loaded Valid Value - Dcc0Regs.DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value - - // - // Enable Single Shot Mode - // - Dcc0Regs.DCCGCTRL.bit.SINGLESHOT = 0xA; - - // - // Enable Error Signal - // - Dcc0Regs.DCCGCTRL.bit.ERRENA = 0xA; - - // - // Enable Done Signal - // - Dcc0Regs.DCCGCTRL.bit.DONEENA = 0xA; - - // - // Enable DCC to start counting - // - Dcc0Regs.DCCGCTRL.bit.DCCENA = 0xA; - EDIS; - - // - // Wait until Error or Done Flag is generated - // - while((Dcc0Regs.DCCSTATUS.all & 3) == 0) - { - } - - // - // Returns true if DCC completes without error - // - return((Dcc0Regs.DCCSTATUS.all & 3) == 2); - -} -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm deleted file mode 100644 index b46339d..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm +++ /dev/null @@ -1,92 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_usdelay.asm -;; -;; TITLE: Simple Delay Function -;; -;; DESCRIPTION: -;; -;; This is a simple delay function that can be used to insert a specified -;; delay into code. -;; This function is only accurate if executed from internal zero-waitstate -;; SARAM. If it is executed from waitstate memory then the delay will be -;; longer then specified. -;; To use this function: -;; 1 - update the CPU clock speed in the f28004x_examples.h -;; file. -;; 2 - Call this function by using the DELAY_US(A) macro -;; that is defined in the f28004x_device.h file. This macro -;; will convert the number of microseconds specified -;; into a loop count for use with this function. -;; This count will be based on the CPU frequency you specify. -;; 3 - For the most accurate delay -;; - Execute this function in 0 waitstate RAM. -;; - Disable interrupts before calling the function -;; If you do not disable interrupts, then think of -;; this as an "at least" delay function as the actual -;; delay may be longer. -;; The C assembly call from the DELAY_US(time) macro will -;; look as follows: -;; extern void Delay(long LoopCount); -;; MOV AL,#LowLoopCount -;; MOV AH,#HighLoopCount -;; LCR _Delay -;; Or as follows (if count is less then 16-bits): -;; MOV ACC,#LoopCount -;; LCR _Delay -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .def _F28x_usDelay - .sect ".TI.ramfunc" - - .global __F28x_usDelay -_F28x_usDelay: - SUB ACC,#1 - BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 - LRETR - -;There is a 9/10 cycle overhead and each loop -;takes five cycles. The LoopCount is given by -;the following formula: -; DELAY_CPU_CYCLES = 9 + 5*LoopCount -; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 -; The macro DELAY_US(A) performs this calculation for you - -;;############################################################################# -;; End of file -;;############################################################################# - diff --git a/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd b/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd deleted file mode 100644 index 31cd63d..0000000 --- a/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd +++ /dev/null @@ -1,303 +0,0 @@ -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - - ANALOG_SUBSYS : origin = 0x05D700, length = 0x000100 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000080 /* CLA registers */ - - CLAPROMCRC : origin = 0x0061C0, length = 0x000020 - - CLB_XBAR : origin = 0x007A40, length = 0x000040 - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - - DCC0 : origin = 0x05E700, length = 0x000040 - - DCSM_BANK0_Z1 : origin = 0x05F000, length = 0x000030 - DCSM_BANK0_Z2 : origin = 0x05F040, length = 0x000030 - DCSM_BANK1_Z1 : origin = 0x05F100, length = 0x000030 - DCSM_BANK1_Z2 : origin = 0x05F140, length = 0x000030 - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - - DMA : origin = 0x001000, length = 0x000200 - - ECAP1 : origin = 0x005200, length = 0x000040 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005240, length = 0x000040 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005280, length = 0x000040 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x0052C0, length = 0x000040 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005300, length = 0x000040 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x005340, length = 0x000040 /* Enhanced Capture 6 registers */ - ECAP7 : origin = 0x005380, length = 0x000040 /* Enhanced Capture 7 registers */ - - PGA1 : origin = 0x005B00, length = 0x000010 - PGA2 : origin = 0x005B10, length = 0x000010 - PGA3 : origin = 0x005B20, length = 0x000010 - PGA4 : origin = 0x005B30, length = 0x000010 - PGA5 : origin = 0x005B40, length = 0x000010 - PGA6 : origin = 0x005B50, length = 0x000010 - PGA7 : origin = 0x005B60, length = 0x000010 - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - - EPWM_XBAR : origin = 0x007A00, length = 0x000040 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - FSITXA : origin = 0x006600, length = 0x000080 - FSIRXA : origin = 0x006680, length = 0x000080 - - GPIOCTRL : origin = 0x007C00, length = 0x000200 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000040 /* GPIO data registers */ - - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - - INPUT_XBAR : origin = 0x007900, length = 0x000020 - - LINA : origin = 0x006A00, length = 0x000100 - LINB : origin = 0x006B00, length = 0x000100 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - - PMBUSA : origin = 0x006400, length = 0x000020 - - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - - WD : origin = 0x007000, length = 0x000040 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - DEV_CFG : origin = 0x05D000, length = 0x000180 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - PERIPH_AC : origin = 0x05D500, length = 0x000200 - - ERAD_GLOBAL : origin = 0x05E800, length = 0x000013 - ERAD_HWBP1 : origin = 0x05E900, length = 0x000008 - ERAD_HWBP2 : origin = 0x05E908, length = 0x000008 - ERAD_HWBP3 : origin = 0x05E910, length = 0x000008 - ERAD_HWBP4 : origin = 0x05E918, length = 0x000008 - ERAD_HWBP5 : origin = 0x05E920, length = 0x000008 - ERAD_HWBP6 : origin = 0x05E928, length = 0x000008 - ERAD_HWBP7 : origin = 0x05E930, length = 0x000008 - ERAD_HWBP8 : origin = 0x05E938, length = 0x000008 - ERAD_CTR1 : origin = 0x05E980, length = 0x000010 - ERAD_CTR2 : origin = 0x05E990, length = 0x000010 - ERAD_CTR3 : origin = 0x05E9A0, length = 0x000010 - ERAD_CTR4 : origin = 0x05E9B0, length = 0x000010 - - XBAR : origin = 0x007920, length = 0x000020 - SYNC_SOC : origin = 0x007940, length = 0x000010 - - XINT : origin = 0x007070, length = 0x000010 -} - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile - GROUP - { - EmuKeyVar - EmuBModeVar - FlashCallbackVar - FlashScalingVar - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - - AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - ClaPromCrc0RegsFile : > CLAPROMCRC, PAGE = 1 - - ClbXbarRegsFile : > CLB_XBAR, PAGE = 1 - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - - Dcc0RegsFile : > DCC0 PAGE = 1 - - DcsmBank0Z1RegsFile : > DCSM_BANK0_Z1, PAGE = 1 - DcsmBank0Z2RegsFile : > DCSM_BANK0_Z2, PAGE = 1 - DcsmBank1Z1RegsFile : > DCSM_BANK1_Z1, PAGE = 1 - DcsmBank1Z2RegsFile : > DCSM_BANK1_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA, PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - ECap7RegsFile : > ECAP7, PAGE = 1 - - Pga1RegsFile : > PGA1, PAGE = 1 - Pga2RegsFile : > PGA2, PAGE = 1 - Pga3RegsFile : > PGA3, PAGE = 1 - Pga4RegsFile : > PGA4, PAGE = 1 - Pga5RegsFile : > PGA5, PAGE = 1 - Pga6RegsFile : > PGA6, PAGE = 1 - Pga7RegsFile : > PGA7, PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - - EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - - EnhancedDebugGlobalRegsFile : > ERAD_GLOBAL, PAGE = 1 - EnhancedDebugHWBP1RegsFile : > ERAD_HWBP1, PAGE = 1 - EnhancedDebugHWBP2RegsFile : > ERAD_HWBP2, PAGE = 1 - EnhancedDebugHWBP3RegsFile : > ERAD_HWBP3, PAGE = 1 - EnhancedDebugHWBP4RegsFile : > ERAD_HWBP4, PAGE = 1 - EnhancedDebugHWBP5RegsFile : > ERAD_HWBP5, PAGE = 1 - EnhancedDebugHWBP6RegsFile : > ERAD_HWBP6, PAGE = 1 - EnhancedDebugHWBP7RegsFile : > ERAD_HWBP7, PAGE = 1 - EnhancedDebugHWBP8RegsFile : > ERAD_HWBP8, PAGE = 1 - EnhancedDebugCounter1RegsFile : > ERAD_CTR1, PAGE = 1 - EnhancedDebugCounter2RegsFile : > ERAD_CTR2, PAGE = 1 - EnhancedDebugCounter3RegsFile : > ERAD_CTR3, PAGE = 1 - EnhancedDebugCounter4RegsFile : > ERAD_CTR4, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - FsiTxaRegsFile : > FSITXA PAGE = 1 - FsiRxaRegsFile : > FSIRXA PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - I2caRegsFile : > I2CA, PAGE = 1 - - InputXbarRegsFile : > INPUT_XBAR PAGE = 1 - XbarRegsFile : > XBAR PAGE = 1 - - LinaRegsFile : > LINA, PAGE = 1 - LinbRegsFile : > LINB, PAGE = 1 - - MemCfgRegsFile : > MEMCFG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - - OutputXbarRegsFile : > OUTPUT_XBAR, PAGE = 1 - - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - PmbusaRegsFile : > PMBUSA, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - DevCfgRegsFile : > DEV_CFG, PAGE = 1 - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - SysPeriphAcRegsFile : > PERIPH_AC, PAGE = 1 - - SyncSocRegsFile : > SYNC_SOC, PAGE = 1 - - XintRegsFile : > XINT, PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h deleted file mode 100644 index d064fc1..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h +++ /dev/null @@ -1,1048 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc.h -// -// TITLE: ADC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ADC_H__ -#define __F28004X_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ADC Individual Register Bit Definitions: - -struct ADCCTL1_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position - Uint16 rsvd2:4; // 6:3 Reserved - Uint16 ADCPWDNZ:1; // 7 ADC Power Down - Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel - Uint16 rsvd3:1; // 12 Reserved - Uint16 ADCBSY:1; // 13 ADC Busy - Uint16 rsvd4:2; // 15:14 Reserved -}; - -union ADCCTL1_REG { - Uint16 all; - struct ADCCTL1_BITS bit; -}; - -struct ADCCTL2_BITS { // bits description - Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:5; // 12:8 Reserved - Uint16 rsvd5:3; // 15:13 Reserved -}; - -union ADCCTL2_REG { - Uint16 all; - struct ADCCTL2_BITS bit; -}; - -struct ADCBURSTCTL_BITS { // bits description - Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable -}; - -union ADCBURSTCTL_REG { - Uint16 all; - struct ADCBURSTCTL_BITS bit; -}; - -struct ADCINTFLG_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLG_REG { - Uint16 all; - struct ADCINTFLG_BITS bit; -}; - -struct ADCINTFLGCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLGCLR_REG { - Uint16 all; - struct ADCINTFLGCLR_BITS bit; -}; - -struct ADCINTOVF_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVF_REG { - Uint16 all; - struct ADCINTOVF_BITS bit; -}; - -struct ADCINTOVFCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVFCLR_REG { - Uint16 all; - struct ADCINTOVFCLR_BITS bit; -}; - -struct ADCINTSEL1N2_BITS { // bits description - Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable - Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable - Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL1N2_REG { - Uint16 all; - struct ADCINTSEL1N2_BITS bit; -}; - -struct ADCINTSEL3N4_BITS { // bits description - Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable - Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable - Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL3N4_REG { - Uint16 all; - struct ADCINTSEL3N4_BITS bit; -}; - -struct ADCSOCPRICTL_BITS { // bits description - Uint16 SOCPRIORITY:5; // 4:0 SOC Priority - Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCSOCPRICTL_REG { - Uint16 all; - struct ADCSOCPRICTL_BITS bit; -}; - -struct ADCINTSOCSEL1_BITS { // bits description - Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select - Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select - Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select - Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select - Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select - Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select - Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select - Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL1_REG { - Uint16 all; - struct ADCINTSOCSEL1_BITS bit; -}; - -struct ADCINTSOCSEL2_BITS { // bits description - Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select - Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select - Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select - Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select - Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select - Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select - Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select - Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL2_REG { - Uint16 all; - struct ADCINTSOCSEL2_BITS bit; -}; - -struct ADCSOCFLG1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag -}; - -union ADCSOCFLG1_REG { - Uint16 all; - struct ADCSOCFLG1_BITS bit; -}; - -struct ADCSOCFRC1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit - Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit - Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit - Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit - Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit - Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit - Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit - Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit - Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit - Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit - Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit - Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit - Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit - Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit - Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit - Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit -}; - -union ADCSOCFRC1_REG { - Uint16 all; - struct ADCSOCFRC1_BITS bit; -}; - -struct ADCSOCOVF1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag -}; - -union ADCSOCOVF1_REG { - Uint16 all; - struct ADCSOCOVF1_BITS bit; -}; - -struct ADCSOCOVFCLR1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit - Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit - Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit - Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit - Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit - Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit - Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit - Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit - Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit - Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit - Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit - Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit - Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit - Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit - Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit - Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit -}; - -union ADCSOCOVFCLR1_REG { - Uint16 all; - struct ADCSOCOVFCLR1_BITS bit; -}; - -struct ADCSOC0CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC0 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC0CTL_REG { - Uint32 all; - struct ADCSOC0CTL_BITS bit; -}; - -struct ADCSOC1CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC1 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC1CTL_REG { - Uint32 all; - struct ADCSOC1CTL_BITS bit; -}; - -struct ADCSOC2CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC2 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC2CTL_REG { - Uint32 all; - struct ADCSOC2CTL_BITS bit; -}; - -struct ADCSOC3CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC3 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC3CTL_REG { - Uint32 all; - struct ADCSOC3CTL_BITS bit; -}; - -struct ADCSOC4CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC4 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC4CTL_REG { - Uint32 all; - struct ADCSOC4CTL_BITS bit; -}; - -struct ADCSOC5CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC5 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC5CTL_REG { - Uint32 all; - struct ADCSOC5CTL_BITS bit; -}; - -struct ADCSOC6CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC6 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC6CTL_REG { - Uint32 all; - struct ADCSOC6CTL_BITS bit; -}; - -struct ADCSOC7CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC7 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC7CTL_REG { - Uint32 all; - struct ADCSOC7CTL_BITS bit; -}; - -struct ADCSOC8CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC8 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC8CTL_REG { - Uint32 all; - struct ADCSOC8CTL_BITS bit; -}; - -struct ADCSOC9CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC9 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC9CTL_REG { - Uint32 all; - struct ADCSOC9CTL_BITS bit; -}; - -struct ADCSOC10CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC10 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC10CTL_REG { - Uint32 all; - struct ADCSOC10CTL_BITS bit; -}; - -struct ADCSOC11CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC11 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC11CTL_REG { - Uint32 all; - struct ADCSOC11CTL_BITS bit; -}; - -struct ADCSOC12CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC12 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC12CTL_REG { - Uint32 all; - struct ADCSOC12CTL_BITS bit; -}; - -struct ADCSOC13CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC13 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC13CTL_REG { - Uint32 all; - struct ADCSOC13CTL_BITS bit; -}; - -struct ADCSOC14CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC14 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC14CTL_REG { - Uint32 all; - struct ADCSOC14CTL_BITS bit; -}; - -struct ADCSOC15CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC15 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC15CTL_REG { - Uint32 all; - struct ADCSOC15CTL_BITS bit; -}; - -struct ADCEVTSTAT_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSTAT_REG { - Uint16 all; - struct ADCEVTSTAT_BITS bit; -}; - -struct ADCEVTCLR_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTCLR_REG { - Uint16 all; - struct ADCEVTCLR_BITS bit; -}; - -struct ADCEVTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSEL_REG { - Uint16 all; - struct ADCEVTSEL_BITS bit; -}; - -struct ADCEVTINTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTINTSEL_REG { - Uint16 all; - struct ADCEVTINTSEL_BITS bit; -}; - -struct ADCCOUNTER_BITS { // bits description - Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCCOUNTER_REG { - Uint16 all; - struct ADCCOUNTER_BITS bit; -}; - -struct ADCREV_BITS { // bits description - Uint16 TYPE:8; // 7:0 ADC Type - Uint16 REV:8; // 15:8 ADC Revision -}; - -union ADCREV_REG { - Uint16 all; - struct ADCREV_BITS bit; -}; - -struct ADCOFFTRIM_BITS { // bits description - Uint16 OFFTRIM:12; // 11:0 ADC Offset Trim - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCOFFTRIM_REG { - Uint16 all; - struct ADCOFFTRIM_BITS bit; -}; - -struct ADCPPB1CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB1CONFIG_REG { - Uint16 all; - struct ADCPPB1CONFIG_BITS bit; -}; - -struct ADCPPB1STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB1STAMP_REG { - Uint16 all; - struct ADCPPB1STAMP_BITS bit; -}; - -struct ADCPPB1OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB1OFFCAL_REG { - Uint16 all; - struct ADCPPB1OFFCAL_BITS bit; -}; - -struct ADCPPB1TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB1TRIPHI_REG { - Uint32 all; - struct ADCPPB1TRIPHI_BITS bit; -}; - -struct ADCPPB1TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp -}; - -union ADCPPB1TRIPLO_REG { - Uint32 all; - struct ADCPPB1TRIPLO_BITS bit; -}; - -struct ADCPPB2CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB2CONFIG_REG { - Uint16 all; - struct ADCPPB2CONFIG_BITS bit; -}; - -struct ADCPPB2STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB2STAMP_REG { - Uint16 all; - struct ADCPPB2STAMP_BITS bit; -}; - -struct ADCPPB2OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB2OFFCAL_REG { - Uint16 all; - struct ADCPPB2OFFCAL_BITS bit; -}; - -struct ADCPPB2TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB2TRIPHI_REG { - Uint32 all; - struct ADCPPB2TRIPHI_BITS bit; -}; - -struct ADCPPB2TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp -}; - -union ADCPPB2TRIPLO_REG { - Uint32 all; - struct ADCPPB2TRIPLO_BITS bit; -}; - -struct ADCPPB3CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB3CONFIG_REG { - Uint16 all; - struct ADCPPB3CONFIG_BITS bit; -}; - -struct ADCPPB3STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB3STAMP_REG { - Uint16 all; - struct ADCPPB3STAMP_BITS bit; -}; - -struct ADCPPB3OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB3OFFCAL_REG { - Uint16 all; - struct ADCPPB3OFFCAL_BITS bit; -}; - -struct ADCPPB3TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB3TRIPHI_REG { - Uint32 all; - struct ADCPPB3TRIPHI_BITS bit; -}; - -struct ADCPPB3TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp -}; - -union ADCPPB3TRIPLO_REG { - Uint32 all; - struct ADCPPB3TRIPLO_BITS bit; -}; - -struct ADCPPB4CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB4CONFIG_REG { - Uint16 all; - struct ADCPPB4CONFIG_BITS bit; -}; - -struct ADCPPB4STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB4STAMP_REG { - Uint16 all; - struct ADCPPB4STAMP_BITS bit; -}; - -struct ADCPPB4OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB4OFFCAL_REG { - Uint16 all; - struct ADCPPB4OFFCAL_BITS bit; -}; - -struct ADCPPB4TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB4TRIPHI_REG { - Uint32 all; - struct ADCPPB4TRIPHI_BITS bit; -}; - -struct ADCPPB4TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp -}; - -union ADCPPB4TRIPLO_REG { - Uint32 all; - struct ADCPPB4TRIPLO_BITS bit; -}; - -struct ADC_REGS { - union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register - union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register - union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register - union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register - union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register - union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register - union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register - union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register - union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register - union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register - union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register - union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register - union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register - union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register - union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register - union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register - union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register - union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register - union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register - union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register - union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register - union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register - union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register - union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register - union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register - union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register - union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register - union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register - union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register - union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register - union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register - union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register - union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register - Uint16 rsvd1; // Reserved - union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register - Uint16 rsvd2; // Reserved - union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register - Uint16 rsvd3; // Reserved - union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register - Uint16 rsvd4[2]; // Reserved - union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register - union ADCREV_REG ADCREV; // ADC Revision Register - union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register - Uint16 rsvd5[4]; // Reserved - union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register - union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register - union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register - Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register - union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register - union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register - union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register - union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register - union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register - Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register - union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register - union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register - union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register - union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register - union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register - Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register - union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register - union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register - union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register - union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register - union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register - Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register - union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register - union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register - Uint16 rsvd6[15]; // Reserved - Uint16 ADCINTCYCLE; // ADC Early Interrupt Generation Cycle - Uint16 rsvd7[16]; // Reserved -}; - -struct ADCPPB1RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB1RESULT_REG { - Uint32 all; - struct ADCPPB1RESULT_BITS bit; -}; - -struct ADCPPB2RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB2RESULT_REG { - Uint32 all; - struct ADCPPB2RESULT_BITS bit; -}; - -struct ADCPPB3RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB3RESULT_REG { - Uint32 all; - struct ADCPPB3RESULT_BITS bit; -}; - -struct ADCPPB4RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB4RESULT_REG { - Uint32 all; - struct ADCPPB4RESULT_BITS bit; -}; - -struct ADC_RESULT_REGS { - Uint16 ADCRESULT0; // ADC Result 0 Register - Uint16 ADCRESULT1; // ADC Result 1 Register - Uint16 ADCRESULT2; // ADC Result 2 Register - Uint16 ADCRESULT3; // ADC Result 3 Register - Uint16 ADCRESULT4; // ADC Result 4 Register - Uint16 ADCRESULT5; // ADC Result 5 Register - Uint16 ADCRESULT6; // ADC Result 6 Register - Uint16 ADCRESULT7; // ADC Result 7 Register - Uint16 ADCRESULT8; // ADC Result 8 Register - Uint16 ADCRESULT9; // ADC Result 9 Register - Uint16 ADCRESULT10; // ADC Result 10 Register - Uint16 ADCRESULT11; // ADC Result 11 Register - Uint16 ADCRESULT12; // ADC Result 12 Register - Uint16 ADCRESULT13; // ADC Result 13 Register - Uint16 ADCRESULT14; // ADC Result 14 Register - Uint16 ADCRESULT15; // ADC Result 15 Register - union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register - union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register - union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register - union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register -}; - -//--------------------------------------------------------------------------- -// ADC External References & Function Declarations: -// -extern volatile struct ADC_RESULT_REGS AdcaResultRegs; -extern volatile struct ADC_RESULT_REGS AdcbResultRegs; -extern volatile struct ADC_RESULT_REGS AdccResultRegs; -extern volatile struct ADC_REGS AdcaRegs; -extern volatile struct ADC_REGS AdcbRegs; -extern volatile struct ADC_REGS AdccRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h deleted file mode 100644 index ce95230..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h +++ /dev/null @@ -1,232 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_analogsubsys.h -// -// TITLE: ANALOGSUBSYS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ANALOGSUBSYS_H__ -#define __F28004X_ANALOGSUBSYS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS Individual Register Bit Definitions: - -struct ANAREFPP_BITS { // bits description - Uint16 ANAREFBDIS:1; // 0 Disable ANAREFB - Uint16 ANAREFCDIS:1; // 1 Disable ANAREFC - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union ANAREFPP_REG { - Uint16 all; - struct ANAREFPP_BITS bit; -}; - -struct TSNSCTL_BITS { // bits description - Uint16 ENABLE:1; // 0 Temperature Sensor Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TSNSCTL_REG { - Uint16 all; - struct TSNSCTL_BITS bit; -}; - -struct ANAREFCTL_BITS { // bits description - Uint16 ANAREFASEL:1; // 0 Analog Reference A Select - Uint16 ANAREFBSEL:1; // 1 Analog Reference B Select - Uint16 ANAREFCSEL:1; // 2 Analog Reference C Select - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 ANAREFA2P5SEL:1; // 8 Analog Reference A Select - Uint16 ANAREFB2P5SEL:1; // 9 Analog Reference B Select - Uint16 ANAREFC2P5SEL:1; // 10 Analog Reference B Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union ANAREFCTL_REG { - Uint16 all; - struct ANAREFCTL_BITS bit; -}; - -struct DCDCCTL_BITS { // bits description - Uint16 DCDCEN:1; // 0 DCDC Enable - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:15; // 30:16 Reserved - Uint16 rsvd3:1; // 31 Reserved -}; - -union DCDCCTL_REG { - Uint32 all; - struct DCDCCTL_BITS bit; -}; - -struct DCDCSTS_BITS { // bits description - Uint16 INDDETECT:1; // 0 Inductor Detected - Uint16 SWSEQDONE:1; // 1 Switch sequence to DC-DC done. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:13; // 15:3 Reserved -}; - -union DCDCSTS_REG { - Uint16 all; - struct DCDCSTS_BITS bit; -}; - -struct CMPHPMXSEL_BITS { // bits description - Uint16 CMP1HPMXSEL:3; // 2:0 CMP1HPMXSEL bits - Uint16 CMP2HPMXSEL:3; // 5:3 CMP2HPMXSEL bits - Uint16 CMP3HPMXSEL:3; // 8:6 CMP3HPMXSEL bits - Uint16 CMP4HPMXSEL:3; // 11:9 CMP4HPMXSEL bits - Uint16 CMP5HPMXSEL:3; // 14:12 CMP5HPMXSEL bits - Uint16 rsvd1:1; // 15 Reserved - Uint16 CMP6HPMXSEL:3; // 18:16 CMP6HPMXSEL bits - Uint16 CMP7HPMXSEL:3; // 21:19 CMP7HPMXSEL bits - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union CMPHPMXSEL_REG { - Uint32 all; - struct CMPHPMXSEL_BITS bit; -}; - -struct CMPLPMXSEL_BITS { // bits description - Uint16 CMP1LPMXSEL:3; // 2:0 CMP1LPMXSEL bits - Uint16 CMP2LPMXSEL:3; // 5:3 CMP2LPMXSEL bits - Uint16 CMP3LPMXSEL:3; // 8:6 CMP3LPMXSEL bits - Uint16 CMP4LPMXSEL:3; // 11:9 CMP4LPMXSEL bits - Uint16 CMP5LPMXSEL:3; // 14:12 CMP5LPMXSEL bits - Uint16 rsvd1:1; // 15 Reserved - Uint16 CMP6LPMXSEL:3; // 18:16 CMP6LPMXSEL bits - Uint16 CMP7LPMXSEL:3; // 21:19 CMP7LPMXSEL bits - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union CMPLPMXSEL_REG { - Uint32 all; - struct CMPLPMXSEL_BITS bit; -}; - -struct CMPHNMXSEL_BITS { // bits description - Uint16 CMP1HNMXSEL:1; // 0 CMP1HNMXSEL bits - Uint16 CMP2HNMXSEL:1; // 1 CMP2HNMXSEL bits - Uint16 CMP3HNMXSEL:1; // 2 CMP3HNMXSEL bits - Uint16 CMP4HNMXSEL:1; // 3 CMP4HNMXSEL bits - Uint16 CMP5HNMXSEL:1; // 4 CMP5HNMXSEL bits - Uint16 CMP6HNMXSEL:1; // 5 CMP6HNMXSEL bits - Uint16 CMP7HNMXSEL:1; // 6 CMP7HNMXSEL bits - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union CMPHNMXSEL_REG { - Uint16 all; - struct CMPHNMXSEL_BITS bit; -}; - -struct CMPLNMXSEL_BITS { // bits description - Uint16 CMP1LNMXSEL:1; // 0 CMP1LNMXSEL bits - Uint16 CMP2LNMXSEL:1; // 1 CMP2LNMXSEL bits - Uint16 CMP3LNMXSEL:1; // 2 CMP3LNMXSEL bits - Uint16 CMP4LNMXSEL:1; // 3 CMP4LNMXSEL bits - Uint16 CMP5LNMXSEL:1; // 4 CMP5LNMXSEL bits - Uint16 CMP6LNMXSEL:1; // 5 CMP6LNMXSEL bits - Uint16 CMP7LNMXSEL:1; // 6 CMP7LNMXSEL bits - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union CMPLNMXSEL_REG { - Uint16 all; - struct CMPLNMXSEL_BITS bit; -}; - -struct LOCK_BITS { // bits description - Uint16 TSNSCTL:1; // 0 TSNSCTL Register lock bit - Uint16 ANAREFCTL:1; // 1 ANAREFCTL Register lock bit - Uint16 VMONCTL:1; // 2 VMONCTL Register lock bit - Uint16 DCDCCTL:1; // 3 DCDCCTL Register lock bit - Uint16 ADCINMXSEL:1; // 4 ADCINMXSEL Register lock bit - Uint16 CMPHPMXSEL:1; // 5 CMPHPMXSEL Register lock bit - Uint16 CMPLPMXSEL:1; // 6 CMPLPMXSEL Register lock bit - Uint16 CMPHNMXSEL:1; // 7 CMPHNMXSEL Register lock bit - Uint16 CMPLNMXSEL:1; // 8 CMPLNMXSEL Register lock bit - Uint16 VREGCTL:1; // 9 VREGCTL Register lock bit - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOCK_REG { - Uint32 all; - struct LOCK_BITS bit; -}; - -struct ANALOG_SUBSYS_REGS { - Uint16 rsvd1[30]; // Reserved - union ANAREFPP_REG ANAREFPP; // ADC Analog Reference Peripheral Properties register - Uint16 rsvd2[65]; // Reserved - union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register - Uint16 rsvd3[7]; // Reserved - union ANAREFCTL_REG ANAREFCTL; // Analog Reference Control Register - Uint16 rsvd4[15]; // Reserved - union DCDCCTL_REG DCDCCTL; // DC-DC control register. - union DCDCSTS_REG DCDCSTS; // DC-DC status register. - Uint16 rsvd5[7]; // Reserved - union CMPHPMXSEL_REG CMPHPMXSEL; // Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details. - union CMPLPMXSEL_REG CMPLPMXSEL; // Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details. - union CMPHNMXSEL_REG CMPHNMXSEL; // Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details. - union CMPLNMXSEL_REG CMPLNMXSEL; // Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details. - Uint16 rsvd6[6]; // Reserved - union LOCK_REG LOCK; // Lock Register -}; - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS External References & Function Declarations: -// -extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h deleted file mode 100644 index 6417951..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h +++ /dev/null @@ -1,607 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_can.h -// -// TITLE: CAN Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CAN_H__ -#define __F28004X_CAN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CAN Individual Register Bit Definitions: - -struct CAN_CTL_BITS { // bits description - bp_16 Init:1; // 0 Initialization - bp_16 IE0:1; // 1 Interrupt line 0 Enable - bp_16 SIE:1; // 2 Status Change Interrupt Enable - bp_16 EIE:1; // 3 Error Interrupt Enable - bp_16 rsvd1:1; // 4 Reserved - bp_16 DAR:1; // 5 Disable Automatic Retransmission - bp_16 CCE:1; // 6 Configuration Change Enable - bp_16 Test:1; // 7 Test Mode Enable - bp_16 IDS:1; // 8 Interruption Debug Support Enable - bp_16 ABO:1; // 9 Auto-Bus-On Enable - bp_16 PMD:4; // 13:10 Parity on/off - bp_16 rsvd2:1; // 14 Reserved - bp_16 SWR:1; // 15 SW Reset Enable - bp_32 INITDBG:1; // 16 Debug Mode Status - bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled - bp_32 DE1:1; // 18 Enable DMA request line - bp_32 DE2:1; // 19 Enable DMA request line - bp_32 DE3:1; // 20 Enable DMA request line - bp_32 rsvd3:3; // 23:21 Reserved - bp_32 rsvd4:1; // 24 Reserved - bp_32 rsvd5:1; // 25 Reserved - bp_32 rsvd6:6; // 31:26 Reserved -}; - -union CAN_CTL_REG { - bp_32 all; - struct CAN_CTL_BITS bit; -}; - -struct CAN_ES_BITS { // bits description - bp_16 LEC:3; // 2:0 Last Error Code - bp_16 TxOk:1; // 3 Transmission status - bp_16 RxOk:1; // 4 Reception status - bp_16 EPass:1; // 5 Error Passive State - bp_16 EWarn:1; // 6 Warning State - bp_16 BOff:1; // 7 Bus-Off State - bp_16 PER:1; // 8 Parity Error Detected - bp_16 rsvd1:1; // 9 Reserved - bp_16 rsvd2:1; // 10 Reserved - bp_16 rsvd3:5; // 15:11 Reserved - bp_32 rsvd4:16; // 31:16 Reserved -}; - -union CAN_ES_REG { - bp_32 all; - struct CAN_ES_BITS bit; -}; - -struct CAN_ERRC_BITS { // bits description - bp_16 TEC:8; // 7:0 Transmit Error Counter - bp_16 REC:7; // 14:8 Receive Error Counter - bp_16 RP:1; // 15 Receive Error Passive - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union CAN_ERRC_REG { - bp_32 all; - struct CAN_ERRC_BITS bit; -}; - -struct CAN_BTR_BITS { // bits description - bp_16 BRP:6; // 5:0 Baud Rate Prescaler - bp_16 SJW:2; // 7:6 Synchronization Jump Width - bp_16 TSEG1:4; // 11:8 Time segment - bp_16 TSEG2:3; // 14:12 Time segment - bp_16 rsvd1:1; // 15 Reserved - bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension - bp_32 rsvd2:12; // 31:20 Reserved -}; - -union CAN_BTR_REG { - bp_32 all; - struct CAN_BTR_BITS bit; -}; - -struct CAN_INT_BITS { // bits description - bp_16 INT0ID:16; // 15:0 Interrupt Identifier - bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union CAN_INT_REG { - bp_32 all; - struct CAN_INT_BITS bit; -}; - -struct CAN_TEST_BITS { // bits description - bp_16 rsvd1:3; // 2:0 Reserved - bp_16 SILENT:1; // 3 Silent Mode - bp_16 LBACK:1; // 4 Loopback Mode - bp_16 TX:2; // 6:5 CANTX Pin Control - bp_16 RX:1; // 7 CANRX Pin Status - bp_16 EXL:1; // 8 External Loopback Mode - bp_16 RDA:1; // 9 RAM Direct Access Enable: - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_TEST_REG { - bp_32 all; - struct CAN_TEST_BITS bit; -}; - -struct CAN_PERR_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 WORD_NUM:3; // 10:8 Word Number - bp_16 rsvd1:5; // 15:11 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_PERR_REG { - bp_32 all; - struct CAN_PERR_BITS bit; -}; - -struct CAN_RAM_INIT_BITS { // bits description - bp_16 KEY0:1; // 0 KEY0 - bp_16 KEY1:1; // 1 KEY1 - bp_16 KEY2:1; // 2 KEY2 - bp_16 KEY3:1; // 3 KEY3 - bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM - bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete - bp_16 rsvd1:10; // 15:6 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_RAM_INIT_REG { - bp_32 all; - struct CAN_RAM_INIT_BITS bit; -}; - -struct CAN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_EN_REG { - bp_32 all; - struct CAN_GLB_INT_EN_BITS bit; -}; - -struct CAN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_FLG_REG { - bp_32 all; - struct CAN_GLB_INT_FLG_BITS bit; -}; - -struct CAN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_CLR_REG { - bp_32 all; - struct CAN_GLB_INT_CLR_BITS bit; -}; - -struct CAN_TXRQ_X_BITS { // bits description - bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 - bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_TXRQ_X_REG { - bp_32 all; - struct CAN_TXRQ_X_BITS bit; -}; - -struct CAN_NDAT_X_BITS { // bits description - bp_16 NewDatReg1:2; // 1:0 New Data Register 1 - bp_16 NewDatReg2:2; // 3:2 New Data Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_NDAT_X_REG { - bp_32 all; - struct CAN_NDAT_X_BITS bit; -}; - -struct CAN_IPEN_X_BITS { // bits description - bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 - bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IPEN_X_REG { - bp_32 all; - struct CAN_IPEN_X_BITS bit; -}; - -struct CAN_MVAL_X_BITS { // bits description - bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 - bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_MVAL_X_REG { - bp_32 all; - struct CAN_MVAL_X_BITS bit; -}; - -struct CAN_IF1CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 DMAactive:1; // 14 DMA Status - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TXRQST:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union CAN_IF1CMD_REG { - bp_32 all; - struct CAN_IF1CMD_BITS bit; -}; - -struct CAN_IF1MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF1MSK_REG { - bp_32 all; - struct CAN_IF1MSK_BITS bit; -}; - -struct CAN_IF1ARB_BITS { // bits description - bp_32 ID:29; // 28:0 ` - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF1ARB_REG { - bp_32 all; - struct CAN_IF1ARB_BITS bit; -}; - -struct CAN_IF1MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF1MCTL_REG { - bp_32 all; - struct CAN_IF1MCTL_BITS bit; -}; - -struct CAN_IF1DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF1DATA_REG { - bp_32 all; - struct CAN_IF1DATA_BITS bit; -}; - -struct CAN_IF1DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF1DATB_REG { - bp_32 all; - struct CAN_IF1DATB_BITS bit; -}; - -struct CAN_IF2CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 DMAactive:1; // 14 DMA Status - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TxRqst:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union CAN_IF2CMD_REG { - bp_32 all; - struct CAN_IF2CMD_BITS bit; -}; - -struct CAN_IF2MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF2MSK_REG { - bp_32 all; - struct CAN_IF2MSK_BITS bit; -}; - -struct CAN_IF2ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF2ARB_REG { - bp_32 all; - struct CAN_IF2ARB_BITS bit; -}; - -struct CAN_IF2MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF2MCTL_REG { - bp_32 all; - struct CAN_IF2MCTL_BITS bit; -}; - -struct CAN_IF2DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF2DATA_REG { - bp_32 all; - struct CAN_IF2DATA_BITS bit; -}; - -struct CAN_IF2DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF2DATB_REG { - bp_32 all; - struct CAN_IF2DATB_BITS bit; -}; - -struct CAN_IF3OBS_BITS { // bits description - bp_16 Mask:1; // 0 Mask data read observation - bp_16 Arb:1; // 1 Arbitration data read observation - bp_16 Ctrl:1; // 2 Ctrl read observation - bp_16 Data_A:1; // 3 Data A read observation - bp_16 Data_B:1; // 4 Data B read observation - bp_16 rsvd1:3; // 7:5 Reserved - bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access - bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access - bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access - bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access - bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access - bp_16 rsvd2:2; // 14:13 Reserved - bp_16 IF3Upd:1; // 15 IF3 Update Data - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_IF3OBS_REG { - bp_32 all; - struct CAN_IF3OBS_BITS bit; -}; - -struct CAN_IF3MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF3MSK_REG { - bp_32 all; - struct CAN_IF3MSK_BITS bit; -}; - -struct CAN_IF3ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF3ARB_REG { - bp_32 all; - struct CAN_IF3ARB_BITS bit; -}; - -struct CAN_IF3MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF3MCTL_REG { - bp_32 all; - struct CAN_IF3MCTL_BITS bit; -}; - -struct CAN_IF3DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF3DATA_REG { - bp_32 all; - struct CAN_IF3DATA_BITS bit; -}; - -struct CAN_IF3DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF3DATB_REG { - bp_32 all; - struct CAN_IF3DATB_BITS bit; -}; - -struct CAN_REGS { - union CAN_CTL_REG CAN_CTL; // CAN Control Register - union CAN_ES_REG CAN_ES; // Error and Status Register - union CAN_ERRC_REG CAN_ERRC; // Error Counter Register - union CAN_BTR_REG CAN_BTR; // Bit Timing Register - union CAN_INT_REG CAN_INT; // Interrupt Register - union CAN_TEST_REG CAN_TEST; // Test Register - uint32_t rsvd6[2]; // Reserved - union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register - uint32_t rsvd7[16]; // Reserved - union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register - uint32_t rsvd8[6]; // Reserved - union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register - union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register - union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register - uint32_t rsvd11[18]; // Reserved - bp_32 CAN_ABOTR; // Auto-Bus-On Time Register - union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register - bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register - uint32_t rsvd14[6]; // Reserved - union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register - bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register - uint32_t rsvd16[6]; // Reserved - union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register - bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register - uint32_t rsvd18[6]; // Reserved - union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register - bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register - uint32_t rsvd20[8]; // Reserved - bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register - uint32_t rsvd21[18]; // Reserved - union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register - union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register - union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register - union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register - union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register - union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register - uint32_t rsvd27[4]; // Reserved - union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register - union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register - union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register - union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register - union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register - union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register - uint32_t rsvd33[4]; // Reserved - union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register - union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register - union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register - union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register - union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register - union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register - uint32_t rsvd39[4]; // Reserved - bp_32 CAN_IF3UPD; // IF3 Update Enable Register - uint32_t rsvd40[78]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CAN External References & Function Declarations: -// -extern volatile struct CAN_REGS CanaRegs; -extern volatile struct CAN_REGS CanbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h deleted file mode 100644 index 9a64068..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h +++ /dev/null @@ -1,366 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cla.h -// -// TITLE: CLA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CLA_H__ -#define __F28004X_CLA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA Individual Register Bit Definitions: - -struct MCTL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset - Uint16 SOFTRESET:1; // 1 Soft Reset - Uint16 IACKE:1; // 2 IACK enable - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union MCTL_REG { - Uint16 all; - struct MCTL_BITS bit; -}; - -struct SOFTINTEN_BITS { // bits description - Uint16 TASK1:1; // 0 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK2:1; // 1 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK3:1; // 2 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK4:1; // 3 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK5:1; // 4 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK6:1; // 5 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK7:1; // 6 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK8:1; // 7 Configure Software Interrupt or End of Task interrupt. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SOFTINTEN_REG { - Uint16 all; - struct SOFTINTEN_BITS bit; -}; - -struct _MSTSBGRND_BITS { // bits description - Uint16 RUN:1; // 0 Background task run status bit. - Uint16 _BGINTM:1; // 1 Indicates whether background task can be interrupted. - Uint16 BGOVF:1; // 2 background task harware trigger overflow. - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union _MSTSBGRND_REG { - Uint16 all; - struct _MSTSBGRND_BITS bit; -}; - -struct _MCTLBGRND_BITS { // bits description - Uint16 BGSTART:1; // 0 Background task start bit - Uint16 TRIGEN:1; // 1 Background task hardware trigger enable - Uint16 rsvd1:13; // 14:2 Reserved - Uint16 BGEN:1; // 15 Enable background task -}; - -union _MCTLBGRND_REG { - Uint16 all; - struct _MCTLBGRND_BITS bit; -}; - -struct MIFR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFR_REG { - Uint16 all; - struct MIFR_BITS bit; -}; - -struct MIOVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIOVF_REG { - Uint16 all; - struct MIOVF_BITS bit; -}; - -struct MIFRC_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Force - Uint16 INT2:1; // 1 Task 2 Interrupt Force - Uint16 INT3:1; // 2 Task 3 Interrupt Force - Uint16 INT4:1; // 3 Task 4 Interrupt Force - Uint16 INT5:1; // 4 Task 5 Interrupt Force - Uint16 INT6:1; // 5 Task 6 Interrupt Force - Uint16 INT7:1; // 6 Task 7 Interrupt Force - Uint16 INT8:1; // 7 Task 8 Interrupt Force - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFRC_REG { - Uint16 all; - struct MIFRC_BITS bit; -}; - -struct MICLR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLR_REG { - Uint16 all; - struct MICLR_BITS bit; -}; - -struct MICLROVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLROVF_REG { - Uint16 all; - struct MICLROVF_BITS bit; -}; - -struct MIER_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Enable - Uint16 INT2:1; // 1 Task 2 Interrupt Enable - Uint16 INT3:1; // 2 Task 3 Interrupt Enable - Uint16 INT4:1; // 3 Task 4 Interrupt Enable - Uint16 INT5:1; // 4 Task 5 Interrupt Enable - Uint16 INT6:1; // 5 Task 6 Interrupt Enable - Uint16 INT7:1; // 6 Task 7 Interrupt Enable - Uint16 INT8:1; // 7 Task 8 Interrupt Enable - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIER_REG { - Uint16 all; - struct MIER_BITS bit; -}; - -struct MIRUN_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Run Status - Uint16 INT2:1; // 1 Task 2 Run Status - Uint16 INT3:1; // 2 Task 3 Run Status - Uint16 INT4:1; // 3 Task 4 Run Status - Uint16 INT5:1; // 4 Task 5 Run Status - Uint16 INT6:1; // 5 Task 6 Run Status - Uint16 INT7:1; // 6 Task 7 Run Status - Uint16 INT8:1; // 7 Task 8 Run Status - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIRUN_REG { - Uint16 all; - struct MIRUN_BITS bit; -}; - -struct _MSTF_BITS { // bits description - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint32 _RPC:16; // 27:12 Return PC - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union _MSTF_REG { - Uint32 all; - struct _MSTF_BITS bit; -}; - -struct _MPSACTL_BITS { // bits description - Uint16 MPABSTART:1; // 0 Start logging PAB onto PSA1 - Uint16 MPABCYC:1; // 1 PAB logging into PSA1 is on every cycle or when PAB changes. - Uint16 MDWDBSTART:1; // 2 Start logging DWDB onto PSA2 - Uint16 MDWDBCYC:1; // 3 DWDB logging into PSA2 is on every cycle. - Uint16 MPSA1CLEAR:1; // 4 PSA1 clear - Uint16 MPSA2CLEAR:1; // 5 PSA2 Clear - Uint16 MPSA2CFG:2; // 7:6 PSA2 Polynomial Configuration - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union _MPSACTL_REG { - Uint16 all; - struct _MPSACTL_BITS bit; -}; - -union MR_REG { - Uint32 i32; - float f32; -}; - -struct CLA_REGS { - Uint16 MVECT1; // Task Interrupt Vector - Uint16 MVECT2; // Task Interrupt Vector - Uint16 MVECT3; // Task Interrupt Vector - Uint16 MVECT4; // Task Interrupt Vector - Uint16 MVECT5; // Task Interrupt Vector - Uint16 MVECT6; // Task Interrupt Vector - Uint16 MVECT7; // Task Interrupt Vector - Uint16 MVECT8; // Task Interrupt Vector - Uint16 rsvd1[8]; // Reserved - union MCTL_REG MCTL; // Control Register - Uint16 rsvd2[10]; // Reserved - Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - union _MSTSBGRND_REG _MSTSBGRND; // Status register for the back ground task. - union _MCTLBGRND_REG _MCTLBGRND; // Control register for the back ground task. - Uint16 _MVECTBGRND; // Vector for the back ground task. - union MIFR_REG MIFR; // Interrupt Flag Register - union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register - union MIFRC_REG MIFRC; // Interrupt Force Register - union MICLR_REG MICLR; // Interrupt Flag Clear Register - union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register - union MIER_REG MIER; // Interrupt Enable Register - union MIRUN_REG MIRUN; // Interrupt Run Status Register - Uint16 rsvd3; // Reserved - Uint16 _MPC; // CLA Program Counter - Uint16 rsvd4; // Reserved - Uint16 _MAR0; // CLA Auxiliary Register 0 - Uint16 _MAR1; // CLA Auxiliary Register 1 - Uint16 rsvd5[2]; // Reserved - union _MSTF_REG _MSTF; // CLA Floating-Point Status Register - union MR_REG _MR0; // CLA Floating-Point Result Register 0 - Uint16 rsvd6[2]; // Reserved - union MR_REG _MR1; // CLA Floating-Point Result Register 1 - Uint16 rsvd7[2]; // Reserved - union MR_REG _MR2; // CLA Floating-Point Result Register 2 - Uint16 rsvd8[2]; // Reserved - union MR_REG _MR3; // CLA Floating-Point Result Register 3 - Uint16 rsvd9[4]; // Reserved - union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register - Uint16 rsvd10; // Reserved - Uint32 _MPSA1; // CLA PSA1 Register - Uint32 _MPSA2; // CLA PSA2 Register - Uint16 rsvd11[56]; // Reserved -}; - -struct SOFTINTFRC_BITS { // bits description - Uint16 TASK1:1; // 0 Force CLA software interrupt for the corresponding task. - Uint16 TASK2:1; // 1 Force CLA software interrupt for the corresponding task. - Uint16 TASK3:1; // 2 Force CLA software interrupt for the corresponding task. - Uint16 TASK4:1; // 3 Force CLA software interrupt for the corresponding task. - Uint16 TASK5:1; // 4 Force CLA software interrupt for the corresponding task. - Uint16 TASK6:1; // 5 Force CLA software interrupt for the corresponding task. - Uint16 TASK7:1; // 6 Force CLA software interrupt for the corresponding task. - Uint16 TASK8:1; // 7 Force CLA software interrupt for the corresponding task. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SOFTINTFRC_REG { - Uint16 all; - struct SOFTINTFRC_BITS bit; -}; - -struct CLA_ONLY_REGS { - Uint16 rsvd1[128]; // Reserved - Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. - Uint16 rsvd2[63]; // Reserved - union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register - Uint16 rsvd3; // Reserved - Uint32 _MPSA1; // CLA PSA1 Register - Uint32 _MPSA2; // CLA PSA2 Register - Uint16 rsvd4[26]; // Reserved - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - Uint16 rsvd5; // Reserved - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register - Uint16 rsvd6[12]; // Reserved -}; - -struct CLA_SOFTINT_REGS { - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - Uint16 rsvd1; // Reserved - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register - Uint16 rsvd2[12]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CLA External References & Function Declarations: -// -extern volatile struct CLA_ONLY_REGS Cla1OnlyRegs; -extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; -extern volatile struct CLA_REGS Cla1Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h deleted file mode 100644 index 0409187..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h +++ /dev/null @@ -1,157 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cla_prom_crc32.h -// -// TITLE: CLA_PROM_CRC32 Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CLA_PROM_CRC32_H__ -#define __F28004X_CLA_PROM_CRC32_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA_PROM_CRC32 Individual Register Bit Definitions: - -struct CRC32_CONTROLREG_BITS { // bits description - Uint16 START:1; // 0 Start Bit - Uint16 rsvd1:3; // 3:1 Reserved - Uint16 FREE_SOFT:1; // 4 emulation control bit - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 HALT:1; // 8 Halt Bit - Uint16 rsvd3:7; // 15:9 Reserved - Uint16 BLOCKSIZE:7; // 22:16 Block size of ROM for which CRC is to be calculated - Uint16 rsvd4:9; // 31:23 Reserved -}; - -union CRC32_CONTROLREG_REG { - Uint32 all; - struct CRC32_CONTROLREG_BITS bit; -}; - -struct CRC32_STATUSREG_BITS { // bits description - Uint16 CURRENTADDR:16; // 15:0 Point to the data fetch unit current address - Uint16 rsvd1:7; // 22:16 Reserved - Uint16 CRCCHECKSTATUS:1; // 23 CRC active status - Uint16 rsvd2:7; // 30:24 Reserved - Uint16 RUNSTATUS:1; // 31 CRC active status -}; - -union CRC32_STATUSREG_REG { - Uint32 all; - struct CRC32_STATUSREG_BITS bit; -}; - -struct CRC32_INTEN_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CRCDONE:1; // 1 CRCDONE interrupt enable register - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CRC32_INTEN_REG { - Uint32 all; - struct CRC32_INTEN_BITS bit; -}; - -struct CRC32_FLG_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt status flag - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt status flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CRC32_FLG_REG { - Uint32 all; - struct CRC32_FLG_BITS bit; -}; - -struct CRC32_CLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt clear - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CRC32_CLR_REG { - Uint32 all; - struct CRC32_CLR_BITS bit; -}; - -struct CRC32_FRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt force - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CRC32_FRC_REG { - Uint32 all; - struct CRC32_FRC_BITS bit; -}; - -struct CLA_PROM_CRC32_REGS { - union CRC32_CONTROLREG_REG CRC32_CONTROLREG; // CRC32-Control Register - Uint32 CRC32_STARTADDRESS; // CRC32-Start address register - Uint32 CRC32_SEED; // CRC32-Seed Register - union CRC32_STATUSREG_REG CRC32_STATUSREG; // CRC32-Status Register - Uint32 CRC32_CRCRESULT; // CRC32-CRC result Register - Uint32 CRC32_GOLDENCRC; // CRC32-Golden CRC register - Uint16 rsvd1[12]; // Reserved - union CRC32_INTEN_REG CRC32_INTEN; // CRC32-Interrupt enable register - union CRC32_FLG_REG CRC32_FLG; // CRC32-Interrupt Flag Register - union CRC32_CLR_REG CRC32_CLR; // CRC32-Interrupt Clear Register - union CRC32_FRC_REG CRC32_FRC; // CRC32-Interrupt Force Register -}; - -//--------------------------------------------------------------------------- -// CLA_PROM_CRC32 External References & Function Declarations: -// -extern volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h deleted file mode 100644 index 29c5717..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h +++ /dev/null @@ -1,299 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cmpss.h -// -// TITLE: CMPSS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CMPSS_H__ -#define __F28004X_CMPSS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CMPSS Individual Register Bit Definitions: - -struct COMPCTL_BITS { // bits description - Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select - Uint16 COMPHINV:1; // 1 High Comparator Invert Select - Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select - Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select - Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable - Uint16 rsvd1:1; // 7 Reserved - Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select - Uint16 COMPLINV:1; // 9 Low Comparator Invert Select - Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select - Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select - Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable - Uint16 COMPDACE:1; // 15 Comparator/DAC Enable -}; - -union COMPCTL_REG { - Uint16 all; - struct COMPCTL_BITS bit; -}; - -struct COMPHYSCTL_BITS { // bits description - Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union COMPHYSCTL_REG { - Uint16 all; - struct COMPHYSCTL_BITS bit; -}; - -struct COMPSTS_BITS { // bits description - Uint16 COMPHSTS:1; // 0 High Comparator Status - Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 COMPLSTS:1; // 8 Low Comparator Status - Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status - Uint16 rsvd2:6; // 15:10 Reserved -}; - -union COMPSTS_REG { - Uint16 all; - struct COMPSTS_BITS bit; -}; - -struct COMPSTSCLR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear - Uint16 HSYNCCLREN:1; // 2 High Comparator EPWMSYNCO Clear Enable - Uint16 rsvd2:6; // 8:3 Reserved - Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear - Uint16 LSYNCCLREN:1; // 10 Low Comparator EPWMSYNCO Clear Enable - Uint16 rsvd3:5; // 15:11 Reserved -}; - -union COMPSTSCLR_REG { - Uint16 all; - struct COMPSTSCLR_BITS bit; -}; - -struct COMPDACCTL_BITS { // bits description - Uint16 DACSOURCE:1; // 0 DAC Source Control - Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control - Uint16 SELREF:1; // 5 DAC Reference Select - Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select - Uint16 SWLOADSEL:1; // 7 Software Load Select - Uint16 BLANKSOURCE:4; // 11:8 EPWMBLANK Source Select - Uint16 BLANKEN:1; // 12 EPWMBLANK Enable - Uint16 rsvd1:1; // 13 Reserved - Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits -}; - -union COMPDACCTL_REG { - Uint16 all; - struct COMPDACCTL_BITS bit; -}; - -struct DACHVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALS_REG { - Uint16 all; - struct DACHVALS_BITS bit; -}; - -struct DACHVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALA_REG { - Uint16 all; - struct DACHVALA_BITS bit; -}; - -struct DACLVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALS_REG { - Uint16 all; - struct DACLVALS_BITS bit; -}; - -struct DACLVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALA_REG { - Uint16 all; - struct DACLVALA_BITS bit; -}; - -struct RAMPDLYA_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYA_REG { - Uint16 all; - struct RAMPDLYA_BITS bit; -}; - -struct RAMPDLYS_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYS_REG { - Uint16 all; - struct RAMPDLYS_BITS bit; -}; - -struct CTRIPLFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPLFILCTL_REG { - Uint16 all; - struct CTRIPLFILCTL_BITS bit; -}; - -struct CTRIPLFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPLFILCLKCTL_REG { - Uint16 all; - struct CTRIPLFILCLKCTL_BITS bit; -}; - -struct CTRIPHFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPHFILCTL_REG { - Uint16 all; - struct CTRIPHFILCTL_BITS bit; -}; - -struct CTRIPHFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPHFILCLKCTL_REG { - Uint16 all; - struct CTRIPHFILCLKCTL_BITS bit; -}; - -struct COMPLOCK_BITS { // bits description - Uint16 COMPCTL:1; // 0 COMPCTL Lock - Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock - Uint16 DACCTL:1; // 2 DACCTL Lock - Uint16 CTRIP:1; // 3 CTRIP Lock - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union COMPLOCK_REG { - Uint16 all; - struct COMPLOCK_BITS bit; -}; - -struct CMPSS_REGS { - union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register - union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register - union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register - union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register - union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register - Uint16 rsvd1; // Reserved - union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register - union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register - Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register - Uint16 rsvd2; // Reserved - Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register - Uint16 rsvd3; // Reserved - Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register - Uint16 rsvd4; // Reserved - Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register - Uint16 rsvd5; // Reserved - Uint16 RAMPSTS; // CMPSS Ramp Status Register - Uint16 rsvd6; // Reserved - union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register - union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register - union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register - union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register - union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register - union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register - union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register - union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register - union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register - Uint16 rsvd7[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CMPSS External References & Function Declarations: -// -extern volatile struct CMPSS_REGS Cmpss1Regs; -extern volatile struct CMPSS_REGS Cmpss2Regs; -extern volatile struct CMPSS_REGS Cmpss3Regs; -extern volatile struct CMPSS_REGS Cmpss4Regs; -extern volatile struct CMPSS_REGS Cmpss5Regs; -extern volatile struct CMPSS_REGS Cmpss6Regs; -extern volatile struct CMPSS_REGS Cmpss7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h deleted file mode 100644 index 378c166..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h +++ /dev/null @@ -1,134 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimer.h -// -// TITLE: CPUTIMER Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CPUTIMER_H__ -#define __F28004X_CPUTIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CPUTIMER Individual Register Bit Definitions: - -struct TIM_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers - Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High -}; - -union TIM_REG { - Uint32 all; - struct TIM_BITS bit; -}; - -struct PRD_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Period Registers - Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High -}; - -union PRD_REG { - Uint32 all; - struct PRD_BITS bit; -}; - -struct TCR_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 TSS:1; // 4 CPU-Timer stop status bit. - Uint16 TRB:1; // 5 Timer reload - Uint16 rsvd2:4; // 9:6 Reserved - Uint16 SOFT:1; // 10 Emulation modes - Uint16 FREE:1; // 11 Emulation modes - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. - Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. -}; - -union TCR_REG { - Uint16 all; - struct TCR_BITS bit; -}; - -struct TPR_BITS { // bits description - Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPR_REG { - Uint16 all; - struct TPR_BITS bit; -}; - -struct TPRH_BITS { // bits description - Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPRH_REG { - Uint16 all; - struct TPRH_BITS bit; -}; - -struct CPUTIMER_REGS { - union TIM_REG TIM; // CPU-Timer, Counter Register - union PRD_REG PRD; // CPU-Timer, Period Register - union TCR_REG TCR; // CPU-Timer, Control Register - Uint16 rsvd1; // Reserved - union TPR_REG TPR; // CPU-Timer, Prescale Register - union TPRH_REG TPRH; // CPU-Timer, Prescale Register High -}; - -//--------------------------------------------------------------------------- -// CPUTIMER External References & Function Declarations: -// -extern volatile struct CPUTIMER_REGS CpuTimer0Regs; -extern volatile struct CPUTIMER_REGS CpuTimer1Regs; -extern volatile struct CPUTIMER_REGS CpuTimer2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h deleted file mode 100644 index d76444d..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h +++ /dev/null @@ -1,156 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dac.h -// -// TITLE: DAC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DAC_H__ -#define __F28004X_DAC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DAC Individual Register Bit Definitions: - -struct DACREV_BITS { // bits description - Uint16 REV:8; // 7:0 DAC Revision Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union DACREV_REG { - Uint16 all; - struct DACREV_BITS bit; -}; - -struct DACCTL_BITS { // bits description - Uint16 DACREFSEL:1; // 0 DAC Reference Select - Uint16 MODE:1; // 1 DAC Mode Select - Uint16 LOADMODE:1; // 2 DACVALA Load Mode - Uint16 rsvd1:1; // 3 Reserved - Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union DACCTL_REG { - Uint16 all; - struct DACCTL_BITS bit; -}; - -struct DACVALA_BITS { // bits description - Uint16 DACVALA:12; // 11:0 DAC Active Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALA_REG { - Uint16 all; - struct DACVALA_BITS bit; -}; - -struct DACVALS_BITS { // bits description - Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALS_REG { - Uint16 all; - struct DACVALS_BITS bit; -}; - -struct DACOUTEN_BITS { // bits description - Uint16 DACOUTEN:1; // 0 DAC Output Code - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union DACOUTEN_REG { - Uint16 all; - struct DACOUTEN_BITS bit; -}; - -struct DACLOCK_BITS { // bits description - Uint16 DACCTL:1; // 0 DAC Control Register Lock - Uint16 DACVAL:1; // 1 DAC Value Register Lock - Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock - Uint16 rsvd1:9; // 11:3 Reserved - Uint16 KEY:4; // 15:12 DAC Register Lock Key -}; - -union DACLOCK_REG { - Uint16 all; - struct DACLOCK_BITS bit; -}; - -struct DACTRIM_BITS { // bits description - Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim - Uint16 rsvd1:4; // 11:8 Reserved - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union DACTRIM_REG { - Uint16 all; - struct DACTRIM_BITS bit; -}; - -struct DAC_REGS { - union DACREV_REG DACREV; // DAC Revision Register - union DACCTL_REG DACCTL; // DAC Control Register - union DACVALA_REG DACVALA; // DAC Value Register - Active - union DACVALS_REG DACVALS; // DAC Value Register - Shadow - union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register - union DACLOCK_REG DACLOCK; // DAC Lock Register - union DACTRIM_REG DACTRIM; // DAC Trim Register - Uint16 rsvd1; // Reserved -}; - -//--------------------------------------------------------------------------- -// DAC External References & Function Declarations: -// -extern volatile struct DAC_REGS DacaRegs; -extern volatile struct DAC_REGS DacbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h deleted file mode 100644 index e422cf2..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h +++ /dev/null @@ -1,203 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dcc.h -// -// TITLE: DCC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DCC_H__ -#define __F28004X_DCC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCC Individual Register Bit Definitions: - -struct DCCGCTRL_BITS { // bits description - bp_16 DCCENA:4; // 3:0 DCC Enable - bp_16 ERRENA:4; // 7:4 Error Enable - bp_16 SINGLESHOT:4; // 11:8 Single-Shot Enable - bp_16 DONEENA:4; // 15:12 DONE Enable - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCGCTRL_REG { - bp_32 all; - struct DCCGCTRL_BITS bit; -}; - -struct DCCREV_BITS { // bits description - bp_16 MINOR:6; // 5:0 Minor Revision Number - bp_16 CUSTOM:2; // 7:6 Custom Module Number - bp_16 MAJOR:3; // 10:8 Major Revision Number - bp_16 RTL:5; // 15:11 Design Release Number - bp_32 FUNC:12; // 27:16 Functional Release Number - bp_32 rsvd1:2; // 29:28 Reserved - bp_32 SCHEME:2; // 31:30 Defines Scheme for Module -}; - -union DCCREV_REG { - bp_32 all; - struct DCCREV_BITS bit; -}; - -struct DCCCNTSEED0_BITS { // bits description - bp_32 COUNTSEED0:20; // 19:0 Seed Value for Counter 0 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNTSEED0_REG { - bp_32 all; - struct DCCCNTSEED0_BITS bit; -}; - -struct DCCVALIDSEED0_BITS { // bits description - bp_16 VALIDSEED:16; // 15:0 Seed Value for Valid Duration Counter 0 - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCVALIDSEED0_REG { - bp_32 all; - struct DCCVALIDSEED0_BITS bit; -}; - -struct DCCCNTSEED1_BITS { // bits description - bp_32 COUNTSEED1:20; // 19:0 Seed Value for Counter 1 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNTSEED1_REG { - bp_32 all; - struct DCCCNTSEED1_BITS bit; -}; - -struct DCCSTATUS_BITS { // bits description - bp_16 ERR:1; // 0 Error Flag - bp_16 DONE:1; // 1 Single-Shot Done Flag - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCSTATUS_REG { - bp_32 all; - struct DCCSTATUS_BITS bit; -}; - -struct DCCCNT0_BITS { // bits description - bp_32 COUNT0:20; // 19:0 Current Value of Counter 0 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNT0_REG { - bp_32 all; - struct DCCCNT0_BITS bit; -}; - -struct DCCVALID0_BITS { // bits description - bp_16 VALID0:16; // 15:0 Current Value of Valid 0 - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCVALID0_REG { - bp_32 all; - struct DCCVALID0_BITS bit; -}; - -struct DCCCNT1_BITS { // bits description - bp_32 COUNT1:20; // 19:0 Current Value of Counter 1 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNT1_REG { - bp_32 all; - struct DCCCNT1_BITS bit; -}; - -struct DCCCLKSRC1_BITS { // bits description - bp_16 CLKSRC1:4; // 3:0 Clock Source Select for Counter 1 - bp_16 rsvd1:8; // 11:4 Reserved - bp_16 KEY:4; // 15:12 Enables or Disables Clock Source Selection for COUNT1 - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCCLKSRC1_REG { - bp_32 all; - struct DCCCLKSRC1_BITS bit; -}; - -struct DCCCLKSRC0_BITS { // bits description - bp_16 CLKSRC0:4; // 3:0 Clock Source Select for Counter 0 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCCLKSRC0_REG { - bp_32 all; - struct DCCCLKSRC0_BITS bit; -}; - -struct DCC_REGS { - union DCCGCTRL_REG DCCGCTRL; // Global Control Register - union DCCREV_REG DCCREV; // DCC Revision Register - union DCCCNTSEED0_REG DCCCNTSEED0; // Counter 0 seed value - union DCCVALIDSEED0_REG DCCVALIDSEED0; // Valid 0 seed value - union DCCCNTSEED1_REG DCCCNTSEED1; // Counter 1 Seed Value - union DCCSTATUS_REG DCCSTATUS; // DCC Status - union DCCCNT0_REG DCCCNT0; // Counter 0 Value - union DCCVALID0_REG DCCVALID0; // Valid Value 0 - union DCCCNT1_REG DCCCNT1; // Counter 1 Value - union DCCCLKSRC1_REG DCCCLKSRC1; // Clock Source 1 - union DCCCLKSRC0_REG DCCCLKSRC0; // Clock Source 0 -}; - -//--------------------------------------------------------------------------- -// DCC External References & Function Declarations: -// -extern volatile struct DCC_REGS Dcc0Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h deleted file mode 100644 index 87c1033..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h +++ /dev/null @@ -1,658 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dcsm.h -// -// TITLE: DCSM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DCSM_H__ -#define __F28004X_DCSM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCSM Individual Register Bit Definitions: - -struct B0_Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer for zone Flash BANK0 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z1_LINKPOINTER_REG { - Uint32 all; - struct B0_Z1_LINKPOINTER_BITS bit; -}; - -struct Z1_OTPSECLOCK_BITS { // bits description - Uint16 JTAGLOCK:4; // 3:0 Zone1 JTAG Lock. - Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_OTPSECLOCK_REG { - Uint32 all; - struct Z1_OTPSECLOCK_BITS bit; -}; - -struct B0_Z1_LINKPOINTERERR_BITS { // bits description - Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z1_LINKPOINTERERR_REG { - Uint32 all; - struct B0_Z1_LINKPOINTERERR_BITS bit; -}; - -struct Z1_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Passwords Read Status - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z1_CR_REG { - Uint16 all; - struct Z1_CR_BITS bit; -}; - -struct B0_Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK0 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK0 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK0 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK0 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK0 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK0 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK0 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK0 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK0 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK0 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK0 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK0 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK0 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK0 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK0 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK0 -}; - -union B0_Z1_GRABSECTR_REG { - Uint32 all; - struct B0_Z1_GRABSECTR_BITS bit; -}; - -struct Z1_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union Z1_GRABRAMR_REG { - Uint32 all; - struct Z1_GRABRAMR_BITS bit; -}; - -struct B0_Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B0_Z1_EXEONLYSECTR_REG { - Uint32 all; - struct B0_Z1_EXEONLYSECTR_BITS bit; -}; - -struct Z1_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_EXEONLYRAMR_REG { - Uint32 all; - struct Z1_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_BANK0_Z1_REGS { - union B0_Z1_LINKPOINTER_REG B0_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK0 - union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock - Uint32 Z1_BOOTDEF_HIGH; // Boot definition (high 32bit) - union B0_Z1_LINKPOINTERERR_REG B0_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK0 - Uint32 Z1_BOOTPIN_CONFIG; // Boot Pin Configuration - Uint32 Z1_GPREG2; // Zone1 General Purpose Register-2 - Uint32 Z1_BOOTDEF_LOW; // Boot definition (low 32bit) - Uint16 rsvd1[2]; // Reserved - Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 - Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 - Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 - Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 - Uint16 rsvd2; // Reserved - union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register - union B0_Z1_GRABSECTR_REG B0_Z1_GRABSECTR; // Zone 1 Grab Flash BANK0 Sectors Register - union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register - union B0_Z1_EXEONLYSECTR_REG B0_Z1_EXEONLYSECTR; // Zone 1 Flash BANK0 Execute_Only Sector Register - union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register - Uint16 rsvd3; // Reserved -}; - -struct B0_Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK0 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z2_LINKPOINTER_REG { - Uint32 all; - struct B0_Z2_LINKPOINTER_BITS bit; -}; - -struct Z2_OTPSECLOCK_BITS { // bits description - Uint16 JTAGLOCK:4; // 3:0 Zone2 JTAG Lock. - Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_OTPSECLOCK_REG { - Uint32 all; - struct Z2_OTPSECLOCK_BITS bit; -}; - -struct B0_Z2_LINKPOINTERERR_BITS { // bits description - Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z2_LINKPOINTERERR_REG { - Uint32 all; - struct B0_Z2_LINKPOINTERERR_BITS bit; -}; - -struct Z2_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Passwords Read Status - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z2_CR_REG { - Uint16 all; - struct Z2_CR_BITS bit; -}; - -struct B0_Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK0 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK0 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK0 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK0 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK0 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK0 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK0 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK0 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK0 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK0 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK0 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK0 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK0 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK0 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK0 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK0 -}; - -union B0_Z2_GRABSECTR_REG { - Uint32 all; - struct B0_Z2_GRABSECTR_BITS bit; -}; - -struct Z2_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union Z2_GRABRAMR_REG { - Uint32 all; - struct Z2_GRABRAMR_BITS bit; -}; - -struct B0_Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B0_Z2_EXEONLYSECTR_REG { - Uint32 all; - struct B0_Z2_EXEONLYSECTR_BITS bit; -}; - -struct Z2_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_EXEONLYRAMR_REG { - Uint32 all; - struct Z2_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_BANK0_Z2_REGS { - union B0_Z2_LINKPOINTER_REG B0_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK0 - union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock - Uint16 rsvd1[2]; // Reserved - union B0_Z2_LINKPOINTERERR_REG B0_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK0 - Uint16 rsvd2[8]; // Reserved - Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 - Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 - Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 - Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 - Uint16 rsvd3; // Reserved - union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register - union B0_Z2_GRABSECTR_REG B0_Z2_GRABSECTR; // Zone 2 Grab Flash BANK0 Sectors Register - union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register - union B0_Z2_EXEONLYSECTR_REG B0_Z2_EXEONLYSECTR; // Zone 2 Flash BANK0 Execute_Only Sector Register - union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register - Uint16 rsvd4; // Reserved -}; - -struct FLSEM_BITS { // bits description - Uint16 SEM:2; // 1:0 Flash Semaphore Bit - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Semaphore Key - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FLSEM_REG { - Uint32 all; - struct FLSEM_BITS bit; -}; - -struct B0_SECTSTAT_BITS { // bits description - Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK0 Sector 0 - Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK0 sector 1 - Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK0 Sector 2 - Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK0 Sector 3 - Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK0 Sector 4 - Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK0 Sector 5 - Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK0 Sector 6 - Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK0 Sector 7 - Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK0 sector 8 - Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK0 Sector 9 - Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK0 Sector 10 - Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK0 Sector 11 - Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK0 Sector 12 - Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK0 Sector 13 - Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK0 Sector 14 - Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK0 Sector 15 -}; - -union B0_SECTSTAT_REG { - Uint32 all; - struct B0_SECTSTAT_BITS bit; -}; - -struct RAMSTAT_BITS { // bits description - Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 - Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 - Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 - Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 - Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 - Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 - Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM LS6 - Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union RAMSTAT_REG { - Uint32 all; - struct RAMSTAT_BITS bit; -}; - -struct B1_SECTSTAT_BITS { // bits description - Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK1 Sector 0 - Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK1 sector 1 - Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK1 Sector 2 - Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK1 Sector 3 - Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK1 Sector 4 - Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK1 Sector 5 - Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK1 Sector 6 - Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK1 Sector 7 - Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK1 sector 8 - Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK1 Sector 9 - Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK1 Sector 10 - Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK1 Sector 11 - Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK1 Sector 12 - Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK1 Sector 13 - Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK1 Sector 14 - Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK1 Sector 15 -}; - -union B1_SECTSTAT_REG { - Uint32 all; - struct B1_SECTSTAT_BITS bit; -}; - -struct SECERRSTAT_BITS { // bits description - Uint16 ERR:1; // 0 Security Configuration load Error Status - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRSTAT_REG { - Uint32 all; - struct SECERRSTAT_BITS bit; -}; - -struct SECERRCLR_BITS { // bits description - Uint16 ERR:1; // 0 Clear Security Configuration Load Error Status Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRCLR_REG { - Uint32 all; - struct SECERRCLR_BITS bit; -}; - -struct SECERRFRC_BITS { // bits description - Uint16 ERR:1; // 0 Set Security Configuration Load Error Status Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRFRC_REG { - Uint32 all; - struct SECERRFRC_BITS bit; -}; - -struct DCSM_COMMON_REGS { - union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register - union B0_SECTSTAT_REG B0_SECTSTAT; // Flash BANK0 Sectors Status Register - union RAMSTAT_REG RAMSTAT; // RAM Status Register - Uint16 rsvd1[2]; // Reserved - union B1_SECTSTAT_REG B1_SECTSTAT; // Flash BANK1 Sectors Status Register - union SECERRSTAT_REG SECERRSTAT; // Security Error Status Register - union SECERRCLR_REG SECERRCLR; // Security Error Clear Register - union SECERRFRC_REG SECERRFRC; // Security Error Force Register -}; - -struct B1_Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer in Flash BANK1 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z1_LINKPOINTER_REG { - Uint32 all; - struct B1_Z1_LINKPOINTER_BITS bit; -}; - -struct B1_Z1_LINKPOINTERERR_BITS { // bits description - Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z1_LINKPOINTERERR_REG { - Uint32 all; - struct B1_Z1_LINKPOINTERERR_BITS bit; -}; - -struct B1_Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK1 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK1 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK1 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK1 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK1 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK1 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK1 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK1 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK1 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK1 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK1 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK1 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK1 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK1 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK1 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK1 -}; - -union B1_Z1_GRABSECTR_REG { - Uint32 all; - struct B1_Z1_GRABSECTR_BITS bit; -}; - -struct B1_Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B1_Z1_EXEONLYSECTR_REG { - Uint32 all; - struct B1_Z1_EXEONLYSECTR_BITS bit; -}; - -struct DCSM_BANK1_Z1_REGS { - union B1_Z1_LINKPOINTER_REG B1_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK1 - Uint16 rsvd1[4]; // Reserved - union B1_Z1_LINKPOINTERERR_REG B1_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK1 - Uint16 rsvd2[18]; // Reserved - union B1_Z1_GRABSECTR_REG B1_Z1_GRABSECTR; // Zone 1 Grab Flash BANK1 Sectors Register - Uint16 rsvd3[2]; // Reserved - union B1_Z1_EXEONLYSECTR_REG B1_Z1_EXEONLYSECTR; // Zone 1 Flash BANK1 Execute_Only Sector Register - Uint16 rsvd4[3]; // Reserved -}; - -struct B1_Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK1 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z2_LINKPOINTER_REG { - Uint32 all; - struct B1_Z2_LINKPOINTER_BITS bit; -}; - -struct B1_Z2_LINKPOINTERERR_BITS { // bits description - Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z2_LINKPOINTERERR_REG { - Uint32 all; - struct B1_Z2_LINKPOINTERERR_BITS bit; -}; - -struct B1_Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK1 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK1 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK1 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK1 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK1 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK1 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK1 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK1 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK1 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK1 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK1 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK1 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK1 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK1 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK1 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK1 -}; - -union B1_Z2_GRABSECTR_REG { - Uint32 all; - struct B1_Z2_GRABSECTR_BITS bit; -}; - -struct B1_Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B1_Z2_EXEONLYSECTR_REG { - Uint32 all; - struct B1_Z2_EXEONLYSECTR_BITS bit; -}; - -struct DCSM_BANK1_Z2_REGS { - union B1_Z2_LINKPOINTER_REG B1_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK1 - Uint16 rsvd1[4]; // Reserved - union B1_Z2_LINKPOINTERERR_REG B1_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK1 - Uint16 rsvd2[18]; // Reserved - union B1_Z2_GRABSECTR_REG B1_Z2_GRABSECTR; // Zone 2 Grab Flash BANK1 Sectors Register - Uint16 rsvd3[2]; // Reserved - union B1_Z2_EXEONLYSECTR_REG B1_Z2_EXEONLYSECTR; // Zone 2 Flash BANK1 Execute_Only Sector Register - Uint16 rsvd4[3]; // Reserved -}; - -//--------------------------------------------------------------------------- -// DCSM External References & Function Declarations: -// -extern volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; -extern volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; -extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; -extern volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; -extern volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h deleted file mode 100644 index 9548456..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h +++ /dev/null @@ -1,276 +0,0 @@ -//########################################################################### -// -// FILE: F28004x_device.h -// -// TITLE: F28004x Device Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_DEVICE_H -#define F28004X_DEVICE_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Common CPU Definitions: -// -#ifdef __TMS320C28XX_CLA__ -// -// There are only two assembly instructions that can access the MSTF register -// - MMOV32 mem32, MSTF -// - MMOV32 mem32, MSTF -// The CLA C compiler allows 'C' access to this control register through the __cregister -// keyword. In order to access the register's contents, the user must copy it to the -// shadow object defined below -// Note that _MSTF is the only __cregister recognized by the CLA C compiler; IER and IFR -// are not accessible (therefore not recognized), therefore __cregister must be redefined to -// null to prevent a cla C compiler error -// -struct MSTF_SHADOW_BITS { // bits description - unsigned short LVF:1; // 0 Latched Overflow Flag - unsigned short LUF:1; // 1 Latched Underflow Flag - unsigned short NF:1; // 2 Negative Float Flag - unsigned short ZF:1; // 3 Zero Float Flag - unsigned short rsvd1:2; // 5:4 Reserved - unsigned short TF:1; // 6 Test Flag - unsigned short rsvd2:2; // 8:7 Reserved - unsigned short RNDF32:1; // 9 Rounding Mode - unsigned short rsvd3:1; // 10 Reserved - unsigned short MEALLOW:1; // 11 MEALLOW Status - unsigned short RPCL:4; // 15:12 Return PC: Low Portion - unsigned short RPCH:12; // 27:16 Return PC: High Portion - unsigned short rsvd4:4; // 31:28 Reserved -}; -extern __cregister volatile unsigned int MSTF; -#endif //__TMS320C28XX_CLA__ - -#ifndef __TMS320C28XX__ -#define __cregister -#endif //__TMS320C28xx__ - -extern __cregister volatile unsigned int IFR; -extern __cregister volatile unsigned int IER; - -#define EINT __asm(" clrc INTM") -#define DINT __asm(" setc INTM") -#define ERTM __asm(" clrc DBGM") -#define DRTM __asm(" setc DBGM") -#define EALLOW __eallow() -#define EDIS __edis() -#define ESTOP0 __asm(" ESTOP0") - -#define M_INT1 0x0001 -#define M_INT2 0x0002 -#define M_INT3 0x0004 -#define M_INT4 0x0008 -#define M_INT5 0x0010 -#define M_INT6 0x0020 -#define M_INT7 0x0040 -#define M_INT8 0x0080 -#define M_INT9 0x0100 -#define M_INT10 0x0200 -#define M_INT11 0x0400 -#define M_INT12 0x0800 -#define M_INT13 0x1000 -#define M_INT14 0x2000 -#define M_DLOG 0x4000 -#define M_RTOS 0x8000 - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -// -// For Portability, User Is Recommended To Use the C99 Standard integer types -// -#if !defined(__TMS320C28XX_CLA__) -#include -#include -#endif //__TMS320C28XX_CLA__ -#include -#include -#include - -#if defined(__cplusplus) -typedef bool _Bool; -#endif - -// -// C99 defines boolean type to be _Bool, but this doesn't match the format of -// the other standard integer types. bool_t has been defined to fill this gap. -// -typedef _Bool bool_t; - -// -// Used for a bool function return status -// -typedef _Bool status_t; - -#ifndef SUCCESS -#define SUCCESS true -#endif - -#ifndef FAIL -#define FAIL false -#endif - -// -// The following data types are included for compatibility with legacy code, -// they are not recommended for use in new software. Please use the C99 -// types included above -// -#if (!defined(DSP28_DATA_TYPES) && !defined(F28_DATA_TYPES)) -#define DSP28_DATA_TYPES -#define F28_DATA_TYPES - -#ifdef __TMS320C28XX_CLA__ -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else // __TMS320C28XX__ -typedef int int16; -typedef long int32; -typedef long long int64; -typedef unsigned int Uint16; -typedef unsigned long Uint32; -typedef unsigned long long Uint64; -typedef float float32; -typedef long double float64; -#endif //__TMS320C28XX_CLA__ - -#endif //(!defined(DSP28_DATA_TYPES) && !defined(F28_DATA_TYPES)) - -// -// The following data types are for use with byte addressable peripherals. -// See compiler documentation on the byte_peripheral type attribute. -// -#ifndef __TMS320C28XX_CLA__ -typedef unsigned int bp_16 __attribute__((byte_peripheral)); -typedef unsigned long bp_32 __attribute__((byte_peripheral)); -#endif - -// -// Include All Peripheral Header Files: -// -#include "f28004x_adc.h" -#include "f28004x_analogsubsys.h" -#include "f28004x_cla.h" -#include "f28004x_cla_prom_crc32.h" -#include "f28004x_cmpss.h" -#include "f28004x_cputimer.h" -#include "f28004x_dac.h" -#include "f28004x_dcsm.h" -#include "f28004x_dma.h" -#include "f28004x_ecap.h" -#include "f28004x_epwm.h" -#include "f28004x_epwm_xbar.h" -#include "f28004x_eqep.h" -#include "f28004x_erad.h" -#include "f28004x_flash.h" -#include "f28004x_fsi.h" -#include "f28004x_gpio.h" -#include "f28004x_i2c.h" -#include "f28004x_input_xbar.h" -#include "f28004x_memconfig.h" -#include "f28004x_nmiintrupt.h" -#include "f28004x_output_xbar.h" -#include "f28004x_pga.h" -#include "f28004x_piectrl.h" -#include "f28004x_pievect.h" -#include "f28004x_pmbus.h" -#include "f28004x_sci.h" -#include "f28004x_sdfm.h" -#include "f28004x_spi.h" -#include "f28004x_sysctrl.h" -#include "f28004x_xbar.h" -#include "f28004x_xint.h" - -// -// byte_peripheral attribute is only supported on the C28 -// -#ifndef __TMS320C28XX_CLA__ -#include "f28004x_can.h" -#include "f28004x_dcc.h" -#include "f28004x_lin.h" -#endif - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F28004X_DEVICE_H definition - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h deleted file mode 100644 index ffc9ec8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h +++ /dev/null @@ -1,214 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma.h -// -// TITLE: F28004x Device DMA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DMA_H__ -#define __F28004X_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DMA Individual Register Bit Definitions: - -struct MODE_BITS { // bits description - Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable - Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable - Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode - Uint16 ONESHOT:1; // 10 One Shot Mode Bit - Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 DATASIZE:1; // 14 Data Size Mode Bit - Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit -}; - -union MODE_REG { - Uint16 all; - struct MODE_BITS bit; -}; - -struct CONTROL_BITS { // bits description - Uint16 RUN:1; // 0 Run Bit - Uint16 HALT:1; // 1 Halt Bit - Uint16 SOFTRESET:1; // 2 Soft Reset Bit - Uint16 PERINTFRC:1; // 3 Interrupt Force Bit - Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 ERRCLR:1; // 7 Error Clear Bit - Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit - Uint16 SYNCFLG:1; // 9 Sync Flag Bit - Uint16 SYNCERR:1; // 10 Sync Error Flag Bit - Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit - Uint16 BURSTSTS:1; // 12 Burst Status Bit - Uint16 RUNSTS:1; // 13 Run Status Bit - Uint16 OVRFLG:1; // 14 Overflow Flag Bit - Uint16 rsvd1:1; // 15 Reserved -}; - -union CONTROL_REG { - Uint16 all; - struct CONTROL_BITS bit; -}; - -struct DMACTRL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset Bit - Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union DMACTRL_REG { - Uint16 all; - struct DMACTRL_BITS bit; -}; - -struct DEBUGCTRL_BITS { // bits description - Uint16 rsvd1:15; // 14:0 Reserved - Uint16 FREE:1; // 15 Debug Mode Bit -}; - -union DEBUGCTRL_REG { - Uint16 all; - struct DEBUGCTRL_BITS bit; -}; - -struct PRIORITYCTRL1_BITS { // bits description - Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union PRIORITYCTRL1_REG { - Uint16 all; - struct PRIORITYCTRL1_BITS bit; -}; - -struct PRIORITYSTAT_BITS { // bits description - Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits - Uint16 rsvd1:1; // 3 Reserved - Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union PRIORITYSTAT_REG { - Uint16 all; - struct PRIORITYSTAT_BITS bit; -}; - -struct BURST_SIZE_BITS { // bits description - Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_SIZE_REG { - Uint16 all; - struct BURST_SIZE_BITS bit; -}; - -struct BURST_COUNT_BITS { // bits description - Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_COUNT_REG { - Uint16 all; - struct BURST_COUNT_BITS bit; -}; - -struct CH_REGS { - union MODE_REG MODE; // Mode Register - union CONTROL_REG CONTROL; // Control Register - union BURST_SIZE_REG BURST_SIZE; // Burst Size Register - union BURST_COUNT_REG BURST_COUNT; // Burst Count Register - int16 SRC_BURST_STEP; // Source Burst Step Register - int16 DST_BURST_STEP; // Destination Burst Step Register - Uint16 TRANSFER_SIZE; // Transfer Size Register - Uint16 TRANSFER_COUNT; // Transfer Count Register - int16 SRC_TRANSFER_STEP; // Source Transfer Step Register - int16 DST_TRANSFER_STEP; // Destination Transfer Step Register - Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register - Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register - int16 SRC_WRAP_STEP; // Source Wrap Step Register - Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register - Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register - int16 DST_WRAP_STEP; // Destination Wrap Step Register - Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register - Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register - Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register - Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register - Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register - Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register - Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register - Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register -}; - -struct DMA_REGS { - union DMACTRL_REG DMACTRL; // DMA Control Register - union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register - Uint16 rsvd0; // Reserved - Uint16 rsvd1; // Reserved - union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register - Uint16 rsvd2; // Reserved - union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register - Uint16 rsvd3[25]; // Reserved - struct CH_REGS CH1; // DMA Channel 1 Registers - struct CH_REGS CH2; // DMA Channel 2 Registers - struct CH_REGS CH3; // DMA Channel 3 Registers - struct CH_REGS CH4; // DMA Channel 4 Registers - struct CH_REGS CH5; // DMA Channel 5 Registers - struct CH_REGS CH6; // DMA Channel 6 Registers -}; - -//--------------------------------------------------------------------------- -// DMA External References & Function Declarations: -// -extern volatile struct DMA_REGS DmaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h deleted file mode 100644 index a6e3605..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h +++ /dev/null @@ -1,309 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_ecap.h -// -// TITLE: ECAP Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ECAP_H__ -#define __F28004X_ECAP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ECAP Individual Register Bit Definitions: - -struct ECCTL0_BITS { // bits description - Uint16 INPUTSEL:7; // 6:0 INPUT source select - Uint16 rsvd1:9; // 15:7 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECCTL0_REG { - Uint32 all; - struct ECCTL0_BITS bit; -}; - -struct ECCTL1_BITS { // bits description - Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select - Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 - Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select - Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 - Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select - Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 - Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select - Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 - Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event - Uint16 PRESCALE:5; // 13:9 Event Filter prescale select - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union ECCTL1_REG { - Uint16 all; - struct ECCTL1_BITS bit; -}; - -struct ECCTL2_BITS { // bits description - Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot - Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous - Uint16 REARM:1; // 3 One-shot re-arm - Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop - Uint16 SYNCI_EN:1; // 5 Counter sync-in select - Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode - Uint16 SWSYNC:1; // 8 SW forced counter sync - Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select - Uint16 APWMPOL:1; // 10 APWM output polarity select - Uint16 CTRFILTRESET:1; // 11 Reset event filter, modulus counter, and interrupt flags. - Uint16 DMAEVTSEL:2; // 13:12 DMA event select - Uint16 MODCNTRSTS:2; // 15:14 modulo counter status -}; - -union ECCTL2_REG { - Uint16 all; - struct ECCTL2_BITS bit; -}; - -struct ECEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable - Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable - Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:7; // 15:9 Reserved -}; - -union ECEINT_REG { - Uint16 all; - struct ECEINT_BITS bit; -}; - -struct ECFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Flag - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag - Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag - Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union ECFLG_REG { - Uint16 all; - struct ECFLG_BITS bit; -}; - -struct ECCLR_BITS { // bits description - Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear - Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear - Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear - Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear - Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear - Uint16 CTROVF:1; // 5 Counter Overflow Status Clear - Uint16 CTR_PRD:1; // 6 Period Equal Status Clear - Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union ECCLR_REG { - Uint16 all; - struct ECCLR_BITS bit; -}; - -struct ECFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt - Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt - Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt - Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt - Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt - Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt - Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:7; // 15:9 Reserved -}; - -union ECFRC_REG { - Uint16 all; - struct ECFRC_BITS bit; -}; - -struct ECAPSYNCINSEL_BITS { // bits description - Uint16 SEL:5; // 4:0 SYNCIN source select - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAPSYNCINSEL_REG { - Uint32 all; - struct ECAPSYNCINSEL_BITS bit; -}; - -struct ECAP_REGS { - Uint32 TSCTR; // Time-Stamp Counter - Uint32 CTRPHS; // Counter Phase Offset Value Register - Uint32 CAP1; // Capture 1 Register - Uint32 CAP2; // Capture 2 Register - Uint32 CAP3; // Capture 3 Register - Uint32 CAP4; // Capture 4 Register - Uint16 rsvd1[6]; // Reserved - union ECCTL0_REG ECCTL0; // Capture Control Register 0 - union ECCTL1_REG ECCTL1; // Capture Control Register 1 - union ECCTL2_REG ECCTL2; // Capture Control Register 2 - union ECEINT_REG ECEINT; // Capture Interrupt Enable Register - union ECFLG_REG ECFLG; // Capture Interrupt Flag Register - union ECCLR_REG ECCLR; // Capture Interrupt Clear Register - union ECFRC_REG ECFRC; // Capture Interrupt Force Register - Uint16 rsvd2[4]; // Reserved - union ECAPSYNCINSEL_REG ECAPSYNCINSEL; // SYNC source select register -}; - -struct HRCTL_BITS { // bits description - Uint16 HRE:1; // 0 High Resolution Enable - Uint16 HRCLKE:1; // 1 High Resolution Clock Enable - Uint16 PRDSEL:1; // 2 Calibration Period Match - Uint16 CALIBSTART:1; // 3 Calibration start - Uint16 CALIBSTS:1; // 4 Calibration status - Uint16 CALIBCONT:1; // 5 Continuous mode Calibration Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRCTL_REG { - Uint32 all; - struct HRCTL_BITS bit; -}; - -struct HRINTEN_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CALIBDONE:1; // 1 Calibration doe interrupt enable - Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status enable - Uint16 rsvd2:13; // 15:3 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union HRINTEN_REG { - Uint32 all; - struct HRINTEN_BITS bit; -}; - -struct HRFLG_BITS { // bits description - Uint16 CALIBINT:1; // 0 Global calibration Interrupt Status Flag - Uint16 CALIBDONE:1; // 1 Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status Flag Bi - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRFLG_REG { - Uint32 all; - struct HRFLG_BITS bit; -}; - -struct HRCLR_BITS { // bits description - Uint16 CALIBINT:1; // 0 Clear Global calibration Interrupt Flag - Uint16 CALIBDONE:1; // 1 Clear Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Clear Calibration period check status Flag Bit: - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRCLR_REG { - Uint32 all; - struct HRCLR_BITS bit; -}; - -struct HRFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CALIBDONE:1; // 1 Force Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Force Calibration period check status Flag Bit: - Uint16 rsvd2:13; // 15:3 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union HRFRC_REG { - Uint32 all; - struct HRFRC_BITS bit; -}; - -struct HRCAP_REGS { - union HRCTL_REG HRCTL; // High-Res Control Register - Uint16 rsvd1[2]; // Reserved - union HRINTEN_REG HRINTEN; // High-Res Calibration Interrupt Enable Register - union HRFLG_REG HRFLG; // High-Res Calibration Interrupt Flag Register - union HRCLR_REG HRCLR; // High-Res Calibration Interrupt Clear Register - union HRFRC_REG HRFRC; // High-Res Calibration Interrupt Force Register - Uint32 HRCALPRD; // High-Res Calibration Period Register - Uint32 HRSYSCLKCTR; // High-Res Calibration SYSCLK Counter Register - Uint32 HRSYSCLKCAP; // High-Res Calibration SYSCLK Capture Register - Uint32 HRCLKCTR; // High-Res Calibration HRCLK Counter Register - Uint32 HRCLKCAP; // High-Res Calibration HRCLK Capture Register - Uint16 rsvd2[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ECAP External References & Function Declarations: -// -extern volatile struct ECAP_REGS ECap1Regs; -extern volatile struct ECAP_REGS ECap2Regs; -extern volatile struct ECAP_REGS ECap3Regs; -extern volatile struct ECAP_REGS ECap4Regs; -extern volatile struct ECAP_REGS ECap5Regs; -extern volatile struct ECAP_REGS ECap6Regs; -extern volatile struct ECAP_REGS ECap7Regs; -extern volatile struct HRCAP_REGS HRCap6Regs; -extern volatile struct HRCAP_REGS HRCap7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h deleted file mode 100644 index e7219dc..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h +++ /dev/null @@ -1,1237 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm.h -// -// TITLE: EPWM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EPWM_H__ -#define __F28004X_EPWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM Individual Register Bit Definitions: - -struct TBCTL_BITS { // bits description - Uint16 CTRMODE:2; // 1:0 Counter Mode - Uint16 PHSEN:1; // 2 Phase Load Enable - Uint16 PRDLD:1; // 3 Active Period Load - Uint16 SYNCOSEL:2; // 5:4 Sync Output Select - Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse - Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler - Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler - Uint16 PHSDIR:1; // 13 Phase Direction Bit - Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits -}; - -union TBCTL_REG { - Uint16 all; - struct TBCTL_BITS bit; -}; - -struct TBCTL2_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode - Uint16 OSHTSYNC:1; // 7 One shot sync - Uint16 rsvd3:4; // 11:8 Reserved - Uint16 SYNCOSELX:2; // 13:12 Syncout selection - Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event -}; - -union TBCTL2_REG { - Uint16 all; - struct TBCTL2_BITS bit; -}; - -struct TBSTS_BITS { // bits description - Uint16 CTRDIR:1; // 0 Counter Direction Status - Uint16 SYNCI:1; // 1 External Input Sync Status - Uint16 CTRMAX:1; // 2 Counter Max Latched Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union TBSTS_REG { - Uint16 all; - struct TBSTS_BITS bit; -}; - -struct CMPCTL_BITS { // bits description - Uint16 LOADAMODE:2; // 1:0 Active Compare A Load - Uint16 LOADBMODE:2; // 3:2 Active Compare B Load - Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status - Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status - Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC - Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL_REG { - Uint16 all; - struct CMPCTL_BITS bit; -}; - -struct CMPCTL2_BITS { // bits description - Uint16 LOADCMODE:2; // 1:0 Active Compare C Load - Uint16 LOADDMODE:2; // 3:2 Active Compare D load - Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode - Uint16 rsvd2:3; // 9:7 Reserved - Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC - Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL2_REG { - Uint16 all; - struct CMPCTL2_BITS bit; -}; - -struct DBCTL_BITS { // bits description - Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control - Uint16 POLSEL:2; // 3:2 Polarity Select Control - Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control - Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode - Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode - Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode - Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode - Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control - Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control - Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable -}; - -union DBCTL_REG { - Uint16 all; - struct DBCTL_BITS bit; -}; - -struct DBCTL2_BITS { // bits description - Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select - Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union DBCTL2_REG { - Uint16 all; - struct DBCTL2_BITS bit; -}; - -struct AQCTL_BITS { // bits description - Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select - Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select - Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC - Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC - Uint16 rsvd3:4; // 15:12 Reserved -}; - -union AQCTL_REG { - Uint16 all; - struct AQCTL_BITS bit; -}; - -struct AQTSRCSEL_BITS { // bits description - Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits - Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQTSRCSEL_REG { - Uint16 all; - struct AQTSRCSEL_BITS bit; -}; - -struct PCCTL_BITS { // bits description - Uint16 CHPEN:1; // 0 PWM chopping enable - Uint16 OSHTWTH:4; // 4:1 One-shot pulse width - Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency - Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union PCCTL_REG { - Uint16 all; - struct PCCTL_BITS bit; -}; - -struct VCAPCTL_BITS { // bits description - Uint16 VCAPE:1; // 0 Valley Capture mode - Uint16 VCAPSTART:1; // 1 Valley Capture Start - Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable - Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union VCAPCTL_REG { - Uint16 all; - struct VCAPCTL_BITS bit; -}; - -struct VCNTCFG_BITS { // bits description - Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection - Uint16 rsvd1:3; // 6:4 Reserved - Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit - Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit -}; - -union VCNTCFG_REG { - Uint16 all; - struct VCNTCFG_BITS bit; -}; - -struct HRCNFG_BITS { // bits description - Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits - Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits - Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits - Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit - Uint16 AUTOCONV:1; // 6 Autoconversion Bit - Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit - Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits - Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits - Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits - Uint16 rsvd1:1; // 13 Reserved - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union HRCNFG_REG { - Uint16 all; - struct HRCNFG_BITS bit; -}; - -struct HRPWR_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:4; // 9:6 Reserved - Uint16 rsvd7:5; // 14:10 Reserved - Uint16 CALPWRON:1; // 15 Calibration Power On -}; - -union HRPWR_REG { - Uint16 all; - struct HRPWR_BITS bit; -}; - -struct HRMSTEP_BITS { // bits description - Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union HRMSTEP_REG { - Uint16 all; - struct HRMSTEP_BITS bit; -}; - -struct HRCNFG2_BITS { // bits description - Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits - Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits - Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits - Uint16 rsvd1:8; // 13:6 Reserved - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union HRCNFG2_REG { - Uint16 all; - struct HRCNFG2_BITS bit; -}; - -struct HRPCTL_BITS { // bits description - Uint16 HRPE:1; // 0 High Resolution Period Enable - Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select - Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union HRPCTL_REG { - Uint16 all; - struct HRPCTL_BITS bit; -}; - -struct TRREM_BITS { // bits description - Uint16 TRREM:11; // 10:0 Translator Remainder Bits - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union TRREM_REG { - Uint16 all; - struct TRREM_BITS bit; -}; - -struct GLDCTL_BITS { // bits description - Uint16 GLD:1; // 0 Global Shadow to Active load event control - Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection - Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register - Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union GLDCTL_REG { - Uint16 all; - struct GLDCTL_BITS bit; -}; - -struct GLDCFG_BITS { // bits description - Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR - Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR - Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR - Uint16 CMPC:1; // 3 Global load event configuration for CMPC - Uint16 CMPD:1; // 4 Global load event configuration for CMPD - Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR - Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR - Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL - Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 - Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 - Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union GLDCFG_REG { - Uint16 all; - struct GLDCFG_BITS bit; -}; - -struct EPWMXLINK_BITS { // bits description - Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link - Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link - Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link - Uint16 CMPCLINK:4; // 15:12 CMPC Link - Uint16 CMPDLINK:4; // 19:16 CMPD Link - Uint16 rsvd1:8; // 27:20 Reserved - Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link -}; - -union EPWMXLINK_REG { - Uint32 all; - struct EPWMXLINK_BITS bit; -}; - -struct EPWMREV_BITS { // bits description - Uint16 REV:8; // 7:0 EPWM Silicon Revision bits - Uint16 TYPE:8; // 15:8 EPWM Type Bits -}; - -union EPWMREV_REG { - Uint16 all; - struct EPWMREV_BITS bit; -}; - -struct AQCTLA_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLA_REG { - Uint16 all; - struct AQCTLA_BITS bit; -}; - -struct AQCTLA2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLA2_REG { - Uint16 all; - struct AQCTLA2_BITS bit; -}; - -struct AQCTLB_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLB_REG { - Uint16 all; - struct AQCTLB_BITS bit; -}; - -struct AQCTLB2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLB2_REG { - Uint16 all; - struct AQCTLB2_BITS bit; -}; - -struct AQSFRC_BITS { // bits description - Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked - Uint16 OTSFA:1; // 2 One-time SW Force A Output - Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked - Uint16 OTSFB:1; // 5 One-time SW Force A Output - Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQSFRC_REG { - Uint16 all; - struct AQSFRC_BITS bit; -}; - -struct AQCSFRC_BITS { // bits description - Uint16 CSFA:2; // 1:0 Continuous Software Force on output A - Uint16 CSFB:2; // 3:2 Continuous Software Force on output B - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union AQCSFRC_REG { - Uint16 all; - struct AQCSFRC_BITS bit; -}; - -struct DBREDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits -}; - -union DBREDHR_REG { - Uint16 all; - struct DBREDHR_BITS bit; -}; - -struct DBRED_BITS { // bits description - Uint16 DBRED:14; // 13:0 Rising edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBRED_REG { - Uint16 all; - struct DBRED_BITS bit; -}; - -struct DBFEDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits -}; - -union DBFEDHR_REG { - Uint16 all; - struct DBFEDHR_BITS bit; -}; - -struct DBFED_BITS { // bits description - Uint16 DBFED:14; // 13:0 Falling edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBFED_REG { - Uint16 all; - struct DBFED_BITS bit; -}; - -struct TBPHS_BITS { // bits description - Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) - Uint16 TBPHS:16; // 31:16 Phase Offset Register -}; - -union TBPHS_REG { - Uint32 all; - struct TBPHS_BITS bit; -}; - -struct CMPA_BITS { // bits description - Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register - Uint16 CMPA:16; // 31:16 Compare A Register -}; - -union CMPA_REG { - Uint32 all; - struct CMPA_BITS bit; -}; - -struct CMPB_BITS { // bits description - Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits - Uint16 CMPB:16; // 31:16 Compare B Register -}; - -union CMPB_REG { - Uint32 all; - struct CMPB_BITS bit; -}; - -struct GLDCTL2_BITS { // bits description - Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode - Uint16 GFRCLD:1; // 1 Force reload event in one shot mode - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLDCTL2_REG { - Uint16 all; - struct GLDCTL2_BITS bit; -}; - -struct TZSEL_BITS { // bits description - Uint16 CBC1:1; // 0 TZ1 CBC select - Uint16 CBC2:1; // 1 TZ2 CBC select - Uint16 CBC3:1; // 2 TZ3 CBC select - Uint16 CBC4:1; // 3 TZ4 CBC select - Uint16 CBC5:1; // 4 TZ5 CBC select - Uint16 CBC6:1; // 5 TZ6 CBC select - Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select - Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select - Uint16 OSHT1:1; // 8 One-shot TZ1 select - Uint16 OSHT2:1; // 9 One-shot TZ2 select - Uint16 OSHT3:1; // 10 One-shot TZ3 select - Uint16 OSHT4:1; // 11 One-shot TZ4 select - Uint16 OSHT5:1; // 12 One-shot TZ5 select - Uint16 OSHT6:1; // 13 One-shot TZ6 select - Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select - Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select -}; - -union TZSEL_REG { - Uint16 all; - struct TZSEL_BITS bit; -}; - -struct TZDCSEL_BITS { // bits description - Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 - Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 - Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 - Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZDCSEL_REG { - Uint16 all; - struct TZDCSEL_BITS bit; -}; - -struct TZCTL_BITS { // bits description - Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA - Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB - Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 - Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 - Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 - Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTL_REG { - Uint16 all; - struct TZCTL_BITS bit; -}; - -struct TZCTL2_BITS { // bits description - Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP - Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN - Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP - Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN - Uint16 rsvd1:3; // 14:12 Reserved - Uint16 ETZE:1; // 15 TZCTL2 Enable -}; - -union TZCTL2_REG { - Uint16 all; - struct TZCTL2_BITS bit; -}; - -struct TZCTLDCA_BITS { // bits description - Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCA_REG { - Uint16 all; - struct TZCTLDCA_BITS bit; -}; - -struct TZCTLDCB_BITS { // bits description - Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCB_REG { - Uint16 all; - struct TZCTLDCB_BITS bit; -}; - -struct TZEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable - Uint16 OST:1; // 2 Trip Zones One Shot Int Enable - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZEINT_REG { - Uint16 all; - struct TZEINT_BITS bit; -}; - -struct TZFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Int Status Flag - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag - Uint16 OST:1; // 2 Trip Zones One Shot Flag - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TZFLG_REG { - Uint16 all; - struct TZFLG_BITS bit; -}; - -struct TZCBCFLG_BITS { // bits description - Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch - Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch - Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch - Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch - Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch - Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch - Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 - Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCFLG_REG { - Uint16 all; - struct TZCBCFLG_BITS bit; -}; - -struct TZOSTFLG_BITS { // bits description - Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch - Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch - Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch - Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch - Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch - Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch - Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 - Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTFLG_REG { - Uint16 all; - struct TZOSTFLG_BITS bit; -}; - -struct TZCLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt Clear Flag - Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear - Uint16 OST:1; // 2 One-Shot Flag Clear - Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear - Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear - Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear - Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear - Uint16 rsvd1:7; // 13:7 Reserved - Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch -}; - -union TZCLR_REG { - Uint16 all; - struct TZCLR_BITS bit; -}; - -struct TZCBCCLR_BITS { // bits description - Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch - Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch - Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch - Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch - Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch - Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch - Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC - Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCCLR_REG { - Uint16 all; - struct TZCBCCLR_BITS bit; -}; - -struct TZOSTCLR_BITS { // bits description - Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch - Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch - Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch - Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch - Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch - Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch - Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST - Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTCLR_REG { - Uint16 all; - struct TZOSTCLR_BITS bit; -}; - -struct TZFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event - Uint16 OST:1; // 2 Force Trip Zones One Shot Event - Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 - Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 - Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 - Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZFRC_REG { - Uint16 all; - struct TZFRC_BITS bit; -}; - -struct ETSEL_BITS { // bits description - Uint16 INTSEL:3; // 2:0 EPWMxINTn Select - Uint16 INTEN:1; // 3 EPWMxINTn Enable - Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select - Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select - Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select - Uint16 SOCAEN:1; // 11 Start of Conversion A Enable - Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select - Uint16 SOCBEN:1; // 15 Start of Conversion B Enable -}; - -union ETSEL_REG { - Uint16 all; - struct ETSEL_BITS bit; -}; - -struct ETPS_BITS { // bits description - Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select - Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register - Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits - Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select - Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register - Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select - Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter -}; - -union ETPS_REG { - Uint16 all; - struct ETPS_BITS bit; -}; - -struct ETFLG_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Flag - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Flag - Uint16 SOCB:1; // 3 EPWMxSOCB Flag - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFLG_REG { - Uint16 all; - struct ETFLG_BITS bit; -}; - -struct ETCLR_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Clear - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Clear - Uint16 SOCB:1; // 3 EPWMxSOCB Clear - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETCLR_REG { - Uint16 all; - struct ETCLR_BITS bit; -}; - -struct ETFRC_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Force - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Force - Uint16 SOCB:1; // 3 EPWMxSOCB Force - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFRC_REG { - Uint16 all; - struct ETFRC_BITS bit; -}; - -struct ETINTPS_BITS { // bits description - Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select - Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ETINTPS_REG { - Uint16 all; - struct ETINTPS_BITS bit; -}; - -struct ETSOCPS_BITS { // bits description - Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select - Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register - Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select - Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register -}; - -union ETSOCPS_REG { - Uint16 all; - struct ETSOCPS_BITS bit; -}; - -struct ETCNTINITCTL_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force - Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force - Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force - Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable - Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable - Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable -}; - -union ETCNTINITCTL_REG { - Uint16 all; - struct ETCNTINITCTL_BITS bit; -}; - -struct ETCNTINIT_BITS { // bits description - Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits - Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits - Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ETCNTINIT_REG { - Uint16 all; - struct ETCNTINIT_BITS bit; -}; - -struct DCTRIPSEL_BITS { // bits description - Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select - Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select - Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select - Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select -}; - -union DCTRIPSEL_REG { - Uint16 all; - struct DCTRIPSEL_BITS bit; -}; - -struct DCACTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCACTL_REG { - Uint16 all; - struct DCACTL_BITS bit; -}; - -struct DCBCTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCBCTL_REG { - Uint16 all; - struct DCBCTL_BITS bit; -}; - -struct DCFCTL_BITS { // bits description - Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select - Uint16 BLANKE:1; // 2 Blanking Enable/Disable - Uint16 BLANKINV:1; // 3 Blanking Window Inversion - Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment - Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 EDGEMODE:2; // 9:8 Edge Mode - Uint16 EDGECOUNT:3; // 12:10 Edge Count - Uint16 EDGESTATUS:3; // 15:13 Edge Status -}; - -union DCFCTL_REG { - Uint16 all; - struct DCFCTL_BITS bit; -}; - -struct DCCAPCTL_BITS { // bits description - Uint16 CAPE:1; // 0 Counter Capture Enable - Uint16 SHDWMODE:1; // 1 Counter Capture Mode - Uint16 rsvd1:11; // 12:2 Reserved - Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event - Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag - Uint16 CAPMODE:1; // 15 Counter Capture Mode -}; - -union DCCAPCTL_REG { - Uint16 all; - struct DCCAPCTL_BITS bit; -}; - -struct DCAHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCAHTRIPSEL_REG { - Uint16 all; - struct DCAHTRIPSEL_BITS bit; -}; - -struct DCALTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCALTRIPSEL_REG { - Uint16 all; - struct DCALTRIPSEL_BITS bit; -}; - -struct DCBHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBHTRIPSEL_REG { - Uint16 all; - struct DCBHTRIPSEL_BITS bit; -}; - -struct DCBLTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBLTRIPSEL_REG { - Uint16 all; - struct DCBLTRIPSEL_BITS bit; -}; - -struct EPWMLOCK_BITS { // bits description - Uint16 HRLOCK:1; // 0 HRPWM Register Set Lock - Uint16 GLLOCK:1; // 1 Global Load Register Set Lock - Uint16 TZCFGLOCK:1; // 2 TripZone Register Set Lock - Uint16 TZCLRLOCK:1; // 3 TripZone Clear Register Set Lock - Uint16 DCLOCK:1; // 4 Digital Compare Register Set Lock - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 KEY:16; // 31:16 Key to write to this register -}; - -union EPWMLOCK_REG { - Uint32 all; - struct EPWMLOCK_BITS bit; -}; - -struct EPWM_REGS { - union TBCTL_REG TBCTL; // Time Base Control Register - union TBCTL2_REG TBCTL2; // Time Base Control Register 2 - Uint16 rsvd1[2]; // Reserved - Uint16 TBCTR; // Time Base Counter Register - union TBSTS_REG TBSTS; // Time Base Status Register - Uint16 rsvd2[2]; // Reserved - union CMPCTL_REG CMPCTL; // Counter Compare Control Register - union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 - Uint16 rsvd3[2]; // Reserved - union DBCTL_REG DBCTL; // Dead-Band Generator Control Register - union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 - Uint16 rsvd4[2]; // Reserved - union AQCTL_REG AQCTL; // Action Qualifier Control Register - union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register - Uint16 rsvd5[2]; // Reserved - union PCCTL_REG PCCTL; // PWM Chopper Control Register - Uint16 rsvd6[3]; // Reserved - union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register - union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register - Uint16 rsvd7[6]; // Reserved - union HRCNFG_REG HRCNFG; // HRPWM Configuration Register - union HRPWR_REG HRPWR; // HRPWM Power Register - Uint16 rsvd8[4]; // Reserved - union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register - union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register - Uint16 rsvd9[5]; // Reserved - union HRPCTL_REG HRPCTL; // High Resolution Period Control Register - union TRREM_REG TRREM; // Translator High Resolution Remainder Register - Uint16 rsvd10[5]; // Reserved - union GLDCTL_REG GLDCTL; // Global PWM Load Control Register - union GLDCFG_REG GLDCFG; // Global PWM Load Config Register - Uint16 rsvd11[2]; // Reserved - union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register - Uint16 rsvd12[4]; // Reserved - union EPWMREV_REG EPWMREV; // EPWM Revision Register - Uint16 rsvd13; // Reserved - union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A - union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A - union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B - union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B - Uint16 rsvd14[3]; // Reserved - union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register - Uint16 rsvd15; // Reserved - union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register - Uint16 rsvd16[6]; // Reserved - union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register - union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register - Uint16 rsvd17[12]; // Reserved - union TBPHS_REG TBPHS; // Time Base Phase High - Uint16 TBPRDHR; // Time Base Period High Resolution Register - Uint16 TBPRD; // Time Base Period Register - Uint16 rsvd18[6]; // Reserved - union CMPA_REG CMPA; // Counter Compare A Register - union CMPB_REG CMPB; // Compare B Register - Uint16 rsvd19; // Reserved - Uint16 CMPC; // Counter Compare C Register - Uint16 rsvd20; // Reserved - Uint16 CMPD; // Counter Compare D Register - Uint16 rsvd21[2]; // Reserved - union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 - Uint16 rsvd22[2]; // Reserved - Uint16 SWVDELVAL; // Software Valley Mode Delay Register - Uint16 rsvd23[8]; // Reserved - union TZSEL_REG TZSEL; // Trip Zone Select Register - Uint16 rsvd24; // Reserved - union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register - Uint16 rsvd25; // Reserved - union TZCTL_REG TZCTL; // Trip Zone Control Register - union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register - union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A - union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B - Uint16 rsvd26[5]; // Reserved - union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register - Uint16 rsvd27[5]; // Reserved - union TZFLG_REG TZFLG; // Trip Zone Flag Register - union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register - union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register - Uint16 rsvd28; // Reserved - union TZCLR_REG TZCLR; // Trip Zone Clear Register - union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register - union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register - Uint16 rsvd29; // Reserved - union TZFRC_REG TZFRC; // Trip Zone Force Register - Uint16 rsvd30[8]; // Reserved - union ETSEL_REG ETSEL; // Event Trigger Selection Register - Uint16 rsvd31; // Reserved - union ETPS_REG ETPS; // Event Trigger Pre-Scale Register - Uint16 rsvd32; // Reserved - union ETFLG_REG ETFLG; // Event Trigger Flag Register - Uint16 rsvd33; // Reserved - union ETCLR_REG ETCLR; // Event Trigger Clear Register - Uint16 rsvd34; // Reserved - union ETFRC_REG ETFRC; // Event Trigger Force Register - Uint16 rsvd35; // Reserved - union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register - Uint16 rsvd36; // Reserved - union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register - Uint16 rsvd37; // Reserved - union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register - Uint16 rsvd38; // Reserved - union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register - Uint16 rsvd39[11]; // Reserved - union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register - Uint16 rsvd40[2]; // Reserved - union DCACTL_REG DCACTL; // Digital Compare A Control Register - union DCBCTL_REG DCBCTL; // Digital Compare B Control Register - Uint16 rsvd41[2]; // Reserved - union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register - union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register - Uint16 DCFOFFSET; // Digital Compare Filter Offset Register - Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register - Uint16 DCFWINDOW; // Digital Compare Filter Window Register - Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register - Uint16 rsvd42[2]; // Reserved - Uint16 DCCAP; // Digital Compare Counter Capture Register - Uint16 rsvd43[2]; // Reserved - union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select - union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select - union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select - union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select - Uint16 rsvd44[36]; // Reserved - union EPWMLOCK_REG EPWMLOCK; // EPWM Lock Register - Uint16 rsvd45; // Reserved - Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register - Uint16 VCNTVAL; // Hardware Valley Counter Register - Uint16 rsvd46; // Reserved -}; - -//--------------------------------------------------------------------------- -// EPWM External References & Function Declarations: -// -extern volatile struct EPWM_REGS EPwm1Regs; -extern volatile struct EPWM_REGS EPwm2Regs; -extern volatile struct EPWM_REGS EPwm3Regs; -extern volatile struct EPWM_REGS EPwm4Regs; -extern volatile struct EPWM_REGS EPwm5Regs; -extern volatile struct EPWM_REGS EPwm6Regs; -extern volatile struct EPWM_REGS EPwm7Regs; -extern volatile struct EPWM_REGS EPwm8Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h deleted file mode 100644 index d0ebfd7..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h +++ /dev/null @@ -1,830 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm_xbar.h -// -// TITLE: EPWM_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EPWM_XBAR_H__ -#define __F28004X_EPWM_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM_XBAR Individual Register Bit Definitions: - -struct TRIP4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX0TO15CFG_REG { - Uint32 all; - struct TRIP4MUX0TO15CFG_BITS bit; -}; - -struct TRIP4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX16TO31CFG_REG { - Uint32 all; - struct TRIP4MUX16TO31CFG_BITS bit; -}; - -struct TRIP5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX0TO15CFG_REG { - Uint32 all; - struct TRIP5MUX0TO15CFG_BITS bit; -}; - -struct TRIP5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX16TO31CFG_REG { - Uint32 all; - struct TRIP5MUX16TO31CFG_BITS bit; -}; - -struct TRIP7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX0TO15CFG_REG { - Uint32 all; - struct TRIP7MUX0TO15CFG_BITS bit; -}; - -struct TRIP7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX16TO31CFG_REG { - Uint32 all; - struct TRIP7MUX16TO31CFG_BITS bit; -}; - -struct TRIP8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX0TO15CFG_REG { - Uint32 all; - struct TRIP8MUX0TO15CFG_BITS bit; -}; - -struct TRIP8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX16TO31CFG_REG { - Uint32 all; - struct TRIP8MUX16TO31CFG_BITS bit; -}; - -struct TRIP9MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX0TO15CFG_REG { - Uint32 all; - struct TRIP9MUX0TO15CFG_BITS bit; -}; - -struct TRIP9MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX16TO31CFG_REG { - Uint32 all; - struct TRIP9MUX16TO31CFG_BITS bit; -}; - -struct TRIP10MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX0TO15CFG_REG { - Uint32 all; - struct TRIP10MUX0TO15CFG_BITS bit; -}; - -struct TRIP10MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX16TO31CFG_REG { - Uint32 all; - struct TRIP10MUX16TO31CFG_BITS bit; -}; - -struct TRIP11MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX0TO15CFG_REG { - Uint32 all; - struct TRIP11MUX0TO15CFG_BITS bit; -}; - -struct TRIP11MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX16TO31CFG_REG { - Uint32 all; - struct TRIP11MUX16TO31CFG_BITS bit; -}; - -struct TRIP12MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX0TO15CFG_REG { - Uint32 all; - struct TRIP12MUX0TO15CFG_BITS bit; -}; - -struct TRIP12MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX16TO31CFG_REG { - Uint32 all; - struct TRIP12MUX16TO31CFG_BITS bit; -}; - -struct TRIP4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR -}; - -union TRIP4MUXENABLE_REG { - Uint32 all; - struct TRIP4MUXENABLE_BITS bit; -}; - -struct TRIP5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR -}; - -union TRIP5MUXENABLE_REG { - Uint32 all; - struct TRIP5MUXENABLE_BITS bit; -}; - -struct TRIP7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR -}; - -union TRIP7MUXENABLE_REG { - Uint32 all; - struct TRIP7MUXENABLE_BITS bit; -}; - -struct TRIP8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR -}; - -union TRIP8MUXENABLE_REG { - Uint32 all; - struct TRIP8MUXENABLE_BITS bit; -}; - -struct TRIP9MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR -}; - -union TRIP9MUXENABLE_REG { - Uint32 all; - struct TRIP9MUXENABLE_BITS bit; -}; - -struct TRIP10MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR -}; - -union TRIP10MUXENABLE_REG { - Uint32 all; - struct TRIP10MUXENABLE_BITS bit; -}; - -struct TRIP11MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR -}; - -union TRIP11MUXENABLE_REG { - Uint32 all; - struct TRIP11MUXENABLE_BITS bit; -}; - -struct TRIP12MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR -}; - -union TRIP12MUXENABLE_REG { - Uint32 all; - struct TRIP12MUXENABLE_BITS bit; -}; - -struct TRIPOUTINV_BITS { // bits description - Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR - Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR - Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR - Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR - Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR - Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR - Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR - Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TRIPOUTINV_REG { - Uint32 all; - struct TRIPOUTINV_BITS bit; -}; - -struct TRIPLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write protection KEY -}; - -union TRIPLOCK_REG { - Uint32 all; - struct TRIPLOCK_BITS bit; -}; - -struct EPWM_XBAR_REGS { - union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 - union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 - union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 - union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 - union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 - union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 - union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 - union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 - Uint16 rsvd1[8]; // Reserved - union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register - Uint16 rsvd2[4]; // Reserved - union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// EPWM_XBAR External References & Function Declarations: -// -extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h deleted file mode 100644 index e14b9c8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h +++ /dev/null @@ -1,301 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_eqep.h -// -// TITLE: EQEP Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EQEP_H__ -#define __F28004X_EQEP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EQEP Individual Register Bit Definitions: - -struct QDECCTL_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 QSP:1; // 5 QEPS input polarity - Uint16 QIP:1; // 6 QEPI input polarity - Uint16 QBP:1; // 7 QEPB input polarity - Uint16 QAP:1; // 8 QEPA input polarity - Uint16 IGATE:1; // 9 Index pulse gating option - Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter - Uint16 XCR:1; // 11 External Clock Rate - Uint16 SPSEL:1; // 12 Sync output pin selection - Uint16 SOEN:1; // 13 Sync output-enable - Uint16 QSRC:2; // 15:14 Position-counter source selection -}; - -union QDECCTL_REG { - Uint16 all; - struct QDECCTL_BITS bit; -}; - -struct QEPCTL_BITS { // bits description - Uint16 WDE:1; // 0 QEP watchdog enable - Uint16 UTE:1; // 1 QEP unit timer enable - Uint16 QCLM:1; // 2 QEP capture latch mode - Uint16 QPEN:1; // 3 Quadrature postotion counter enable - Uint16 IEL:2; // 5:4 Index event latch - Uint16 SEL:1; // 6 Strobe event latch - Uint16 SWI:1; // 7 Software init position counter - Uint16 IEI:2; // 9:8 Index event init of position count - Uint16 SEI:2; // 11:10 Strobe event init - Uint16 PCRM:2; // 13:12 Postion counter reset - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union QEPCTL_REG { - Uint16 all; - struct QEPCTL_BITS bit; -}; - -struct QCAPCTL_BITS { // bits description - Uint16 UPPS:4; // 3:0 Unit position event prescaler - Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler - Uint16 rsvd1:8; // 14:7 Reserved - Uint16 CEN:1; // 15 Enable eQEP capture -}; - -union QCAPCTL_REG { - Uint16 all; - struct QCAPCTL_BITS bit; -}; - -struct QPOSCTL_BITS { // bits description - Uint16 PCSPW:12; // 11:0 Position compare sync pulse width - Uint16 PCE:1; // 12 Position compare enable/disable - Uint16 PCPOL:1; // 13 Polarity of sync output - Uint16 PCLOAD:1; // 14 Position compare of shadow load - Uint16 PCSHDW:1; // 15 Position compare of shadow enable -}; - -union QPOSCTL_REG { - Uint16 all; - struct QPOSCTL_BITS bit; -}; - -struct QEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Position counter error interrupt enable - Uint16 QPE:1; // 2 Quadrature phase error interrupt enable - Uint16 QDC:1; // 3 Quadrature direction change interrupt enable - Uint16 WTO:1; // 4 Watchdog time out interrupt enable - Uint16 PCU:1; // 5 Position counter underflow interrupt enable - Uint16 PCO:1; // 6 Position counter overflow interrupt enable - Uint16 PCR:1; // 7 Position-compare ready interrupt enable - Uint16 PCM:1; // 8 Position-compare match interrupt enable - Uint16 SEL:1; // 9 Strobe event latch interrupt enable - Uint16 IEL:1; // 10 Index event latch interrupt enable - Uint16 UTO:1; // 11 Unit time out interrupt enable - Uint16 QMAE:1; // 12 QMA error interrupt enable - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union QEINT_REG { - Uint16 all; - struct QEINT_BITS bit; -}; - -struct QFLG_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt status flag - Uint16 PCE:1; // 1 Position counter error interrupt flag - Uint16 PHE:1; // 2 Quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Position counter underflow interrupt flag - Uint16 PCO:1; // 6 Position counter overflow interrupt flag - Uint16 PCR:1; // 7 Position-compare ready interrupt flag - Uint16 PCM:1; // 8 eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Strobe event latch interrupt flag - Uint16 IEL:1; // 10 Index event latch interrupt flag - Uint16 UTO:1; // 11 Unit time out interrupt flag - Uint16 QMAE:1; // 12 QMA error interrupt flag - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union QFLG_REG { - Uint16 all; - struct QFLG_BITS bit; -}; - -struct QCLR_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt clear flag - Uint16 PCE:1; // 1 Clear position counter error interrupt flag - Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag - Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag - Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag - Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag - Uint16 IEL:1; // 10 Clear index event latch interrupt flag - Uint16 UTO:1; // 11 Clear unit time out interrupt flag - Uint16 QMAE:1; // 12 Clear QMA error interrupt flag - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union QCLR_REG { - Uint16 all; - struct QCLR_BITS bit; -}; - -struct QFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Force position counter error interrupt - Uint16 PHE:1; // 2 Force quadrature phase error interrupt - Uint16 QDC:1; // 3 Force quadrature direction change interrupt - Uint16 WTO:1; // 4 Force watchdog time out interrupt - Uint16 PCU:1; // 5 Force position counter underflow interrupt - Uint16 PCO:1; // 6 Force position counter overflow interrupt - Uint16 PCR:1; // 7 Force position-compare ready interrupt - Uint16 PCM:1; // 8 Force position-compare match interrupt - Uint16 SEL:1; // 9 Force strobe event latch interrupt - Uint16 IEL:1; // 10 Force index event latch interrupt - Uint16 UTO:1; // 11 Force unit time out interrupt - Uint16 QMAE:1; // 12 Force QMA error interrupt - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union QFRC_REG { - Uint16 all; - struct QFRC_BITS bit; -}; - -struct QEPSTS_BITS { // bits description - Uint16 PCEF:1; // 0 Position counter error flag. - Uint16 FIMF:1; // 1 First index marker flag - Uint16 CDEF:1; // 2 Capture direction error flag - Uint16 COEF:1; // 3 Capture overflow error flag - Uint16 QDLF:1; // 4 eQEP direction latch flag - Uint16 QDF:1; // 5 Quadrature direction flag - Uint16 FIDF:1; // 6 The first index marker - Uint16 UPEVNT:1; // 7 Unit position event flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union QEPSTS_REG { - Uint16 all; - struct QEPSTS_BITS bit; -}; - -struct REV_BITS { // bits description - Uint16 MAJOR:3; // 2:0 Major Revision Number - Uint16 MINOR:3; // 5:3 Minor Revision Number - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union REV_REG { - Uint32 all; - struct REV_BITS bit; -}; - -struct QEPSTROBESEL_BITS { // bits description - Uint16 STROBESEL:2; // 1:0 QMA Mode Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union QEPSTROBESEL_REG { - Uint32 all; - struct QEPSTROBESEL_BITS bit; -}; - -struct QMACTRL_BITS { // bits description - Uint16 MODE:3; // 2:0 QMA Mode Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union QMACTRL_REG { - Uint32 all; - struct QMACTRL_BITS bit; -}; - -struct EQEP_REGS { - Uint32 QPOSCNT; // Position Counter - Uint32 QPOSINIT; // Position Counter Init - Uint32 QPOSMAX; // Maximum Position Count - Uint32 QPOSCMP; // Position Compare - Uint32 QPOSILAT; // Index Position Latch - Uint32 QPOSSLAT; // Strobe Position Latch - Uint32 QPOSLAT; // Position Latch - Uint32 QUTMR; // QEP Unit Timer - Uint32 QUPRD; // QEP Unit Period - Uint16 QWDTMR; // QEP Watchdog Timer - Uint16 QWDPRD; // QEP Watchdog Period - union QDECCTL_REG QDECCTL; // Quadrature Decoder Control - union QEPCTL_REG QEPCTL; // QEP Control - union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control - union QPOSCTL_REG QPOSCTL; // Position Compare Control - union QEINT_REG QEINT; // QEP Interrupt Control - union QFLG_REG QFLG; // QEP Interrupt Flag - union QCLR_REG QCLR; // QEP Interrupt Clear - union QFRC_REG QFRC; // QEP Interrupt Force - union QEPSTS_REG QEPSTS; // QEP Status - Uint16 QCTMR; // QEP Capture Timer - Uint16 QCPRD; // QEP Capture Period - Uint16 QCTMRLAT; // QEP Capture Latch - Uint16 QCPRDLAT; // QEP Capture Period Latch - Uint16 rsvd1[15]; // Reserved - union REV_REG REV; // QEP Revision Number - union QEPSTROBESEL_REG QEPSTROBESEL; // QEP Strobe select register - union QMACTRL_REG QMACTRL; // QMA Control register - Uint16 rsvd2[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// EQEP External References & Function Declarations: -// -extern volatile struct EQEP_REGS EQep1Regs; -extern volatile struct EQEP_REGS EQep2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h deleted file mode 100644 index e113533..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h +++ /dev/null @@ -1,306 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_erad.h -// -// TITLE: ERAD Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ERAD_H__ -#define __F28004X_ERAD_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ERAD Individual Register Bit Definitions: - -struct GLBL_EVENT_STAT_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Event Status - Uint16 HWBP2:1; // 1 Bus Comparator Module Event Status - Uint16 HWBP3:1; // 2 Bus Comparator Module Event Status - Uint16 HWBP4:1; // 3 Bus Comparator Module Event Status - Uint16 HWBP5:1; // 4 Bus Comparator Module Event Status - Uint16 HWBP6:1; // 5 Bus Comparator Module Event Status - Uint16 HWBP7:1; // 6 Bus Comparator Module Event Status - Uint16 HWBP8:1; // 7 Bus Comparator Module Event Status - Uint16 CTM1:1; // 8 Counter Module Event Status - Uint16 CTM2:1; // 9 Counter Module Event Status - Uint16 CTM3:1; // 10 Counter Module Event Status - Uint16 CTM4:1; // 11 Counter Module Event Status - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_EVENT_STAT_REG { - Uint16 all; - struct GLBL_EVENT_STAT_BITS bit; -}; - -struct GLBL_HALT_STAT_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Halt Status - Uint16 HWBP2:1; // 1 Bus Comparator Module Halt Status - Uint16 HWBP3:1; // 2 Bus Comparator Module Halt Status - Uint16 HWBP4:1; // 3 Bus Comparator Module Halt Status - Uint16 HWBP5:1; // 4 Bus Comparator Module Halt Status - Uint16 HWBP6:1; // 5 Bus Comparator Module Halt Status - Uint16 HWBP7:1; // 6 Bus Comparator Module Halt Status - Uint16 HWBP8:1; // 7 Bus Comparator Module Halt Status - Uint16 CTM1:1; // 8 Counter Module Halt Status - Uint16 CTM2:1; // 9 Counter Module Halt Status - Uint16 CTM3:1; // 10 Counter Module Halt Status - Uint16 CTM4:1; // 11 Counter Module Halt Status - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_HALT_STAT_REG { - Uint16 all; - struct GLBL_HALT_STAT_BITS bit; -}; - -struct GLBL_ENABLE_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Global Enable - Uint16 HWBP2:1; // 1 Bus Comparator Module Global Enable - Uint16 HWBP3:1; // 2 Bus Comparator Module Global Enable - Uint16 HWBP4:1; // 3 Bus Comparator Module Global Enable - Uint16 HWBP5:1; // 4 Bus Comparator Module Global Enable - Uint16 HWBP6:1; // 5 Bus Comparator Module Global Enable - Uint16 HWBP7:1; // 6 Bus Comparator Module Global Enable - Uint16 HWBP8:1; // 7 Bus Comparator Module Global Enable - Uint16 CTM1:1; // 8 Counter Module Global Enable - Uint16 CTM2:1; // 9 Counter Module Global Enable - Uint16 CTM3:1; // 10 Counter Module Global Enable - Uint16 CTM4:1; // 11 Counter Module Global Enable - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_ENABLE_REG { - Uint16 all; - struct GLBL_ENABLE_BITS bit; -}; - -struct GLBL_CTM_RESET_BITS { // bits description - Uint16 CTM1:1; // 0 Global Reset for the counters - Uint16 CTM2:1; // 1 Global Reset for the counters - Uint16 CTM3:1; // 2 Global Reset for the counters - Uint16 CTM4:1; // 3 Global Reset for the counters - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union GLBL_CTM_RESET_REG { - Uint16 all; - struct GLBL_CTM_RESET_BITS bit; -}; - -struct GLBL_OWNER_BITS { // bits description - Uint16 OWNER:2; // 1:0 Global Ownership Bits - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLBL_OWNER_REG { - Uint16 all; - struct GLBL_OWNER_BITS bit; -}; - -struct ERAD_GLOBAL_REGS { - union GLBL_EVENT_STAT_REG GLBL_EVENT_STAT; // Global Event Status Register - Uint16 rsvd1; // Reserved - union GLBL_HALT_STAT_REG GLBL_HALT_STAT; // Global Halt Status Register - Uint16 rsvd2; // Reserved - union GLBL_ENABLE_REG GLBL_ENABLE; // Global Enable Register - Uint16 rsvd3; // Reserved - union GLBL_CTM_RESET_REG GLBL_CTM_RESET; // Global Counter Reset - Uint16 rsvd4[3]; // Reserved - union GLBL_OWNER_REG GLBL_OWNER; // Global Ownership - Uint16 rsvd5[8]; // Reserved -}; - -struct HWBP_CLEAR_BITS { // bits description - Uint16 EVENT_CLR:1; // 0 Event Clear register - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union HWBP_CLEAR_REG { - Uint16 all; - struct HWBP_CLEAR_BITS bit; -}; - -struct HWBP_CNTL_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 BUS_SEL:3; // 4:2 Bus select bits - Uint16 STOP:1; // 5 Stop bit (Halt/No Halt of CPU) - Uint16 RTOSINT:1; // 6 RTOSINT bit - Uint16 COMP_MODE:3; // 9:7 Compare mode - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union HWBP_CNTL_REG { - Uint16 all; - struct HWBP_CNTL_BITS bit; -}; - -struct HWBP_STATUS_BITS { // bits description - Uint16 EVENT_FIRED:1; // 0 HWBP Event Fired bits - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 MODULE_ID:6; // 13:8 Identification bits - Uint16 STATUS:2; // 15:14 Status bits -}; - -union HWBP_STATUS_REG { - Uint16 all; - struct HWBP_STATUS_BITS bit; -}; - -struct ERAD_HWBP_REGS { - Uint32 HWBP_MASK; // HWBP Mask Register - Uint32 HWBP_REF; // HWBP Reference Register - union HWBP_CLEAR_REG HWBP_CLEAR; // HWBP Clear Register - Uint16 rsvd1; // Reserved - union HWBP_CNTL_REG HWBP_CNTL; // HWBP Control Register - union HWBP_STATUS_REG HWBP_STATUS; // HWBP Status Register -}; - -struct CTM_CNTL_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 START_STOP_MODE:1; // 2 Start_stop mode bit - Uint16 EVENT_MODE:1; // 3 Event mode bit - Uint16 RST_ON_MATCH:1; // 4 Reset_on_match bit - Uint16 rsvd2:1; // 5 Reserved - Uint16 STOP:1; // 6 Stop bit (Halt/No Halt of CPU) - Uint16 RTOSINT:1; // 7 RTOSINT bit - Uint16 START_STOP_CUMULATIVE:1; // 8 Start stop cumulative bit - Uint16 rsvd3:1; // 9 Reserved - Uint16 RST_EN:1; // 10 Enable Reset - Uint16 RST_INP_SEL:5; // 15:11 Reset Input select -}; - -union CTM_CNTL_REG { - Uint16 all; - struct CTM_CNTL_BITS bit; -}; - -struct CTM_STATUS_BITS { // bits description - Uint16 EVENT_FIRED:1; // 0 Counter Event Fired bits - Uint16 OVERFLOW:1; // 1 Counter Overflowed - Uint16 MODULE_ID:10; // 11:2 Identification bits - Uint16 STATUS:4; // 15:12 Status bits -}; - -union CTM_STATUS_REG { - Uint16 all; - struct CTM_STATUS_BITS bit; -}; - -struct CTM_INPUT_SEL_BITS { // bits description - Uint16 CTM_INP_SEL_EN:1; // 0 Count input select enable - Uint16 CNT_INP_SEL:5; // 5:1 Count input select - Uint16 STA_INP_SEL:5; // 10:6 Start input select - Uint16 STO_INP_SEL:5; // 15:11 Stop input select -}; - -union CTM_INPUT_SEL_REG { - Uint16 all; - struct CTM_INPUT_SEL_BITS bit; -}; - -struct CTM_CLEAR_BITS { // bits description - Uint16 EVENT_CLEAR:1; // 0 Clear EVENT_FIRED - Uint16 OVERFLOW_CLEAR:1; // 1 Clear OVERFLOW - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union CTM_CLEAR_REG { - Uint16 all; - struct CTM_CLEAR_BITS bit; -}; - -struct CTM_INPUT_SEL_MSB_BITS { // bits description - Uint16 CTM_INP_SEL_MSB:1; // 0 Count input select - Uint16 rsvd1:3; // 3:1 Reserved - Uint16 STA_INP_SEL_MSB:1; // 4 Start input select - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 STO_INP_SEL_MSB:1; // 8 Stop input select - Uint16 rsvd3:3; // 11:9 Reserved - Uint16 RST_INP_SEL_MSB:1; // 12 Reset Input Select - Uint16 rsvd4:3; // 15:13 Reserved -}; - -union CTM_INPUT_SEL_MSB_REG { - Uint16 all; - struct CTM_INPUT_SEL_MSB_BITS bit; -}; - -struct ERAD_COUNTER_REGS { - union CTM_CNTL_REG CTM_CNTL; // Counter Control Register - union CTM_STATUS_REG CTM_STATUS; // Counter Status Register - Uint32 CTM_REF; // Counter Reference Register - Uint32 CTM_COUNT; // Counter Current Value Register - Uint32 CTM_MAX_COUNT; // Counter Max Count Value Register - union CTM_INPUT_SEL_REG CTM_INPUT_SEL; // Counter Input Select Register - union CTM_CLEAR_REG CTM_CLEAR; // Counter Clear Register - union CTM_INPUT_SEL_MSB_REG CTM_INPUT_SEL_MSB; // Counter Input Select Extension Register - Uint16 rsvd1[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ERAD External References & Function Declarations: -// -extern volatile struct ERAD_GLOBAL_REGS EnhancedDebugGlobalRegs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP1Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP2Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP3Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP4Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP5Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP6Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP7Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP8Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter1Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter2Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter3Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter4Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h deleted file mode 100644 index c91a491..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h +++ /dev/null @@ -1,366 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_flash.h -// -// TITLE: FLASH Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_FLASH_H__ -#define __F28004X_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FLASH Individual Register Bit Definitions: - -struct FRDCNTL_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 RWAIT:4; // 11:8 Random Read Waitstate - Uint16 rsvd2:4; // 15:12 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union FRDCNTL_REG { - Uint32 all; - struct FRDCNTL_BITS bit; -}; - -struct FBAC_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 BAGP:8; // 15:8 Bank Active Grace Period - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBAC_REG { - Uint32 all; - struct FBAC_BITS bit; -}; - -struct FBFALLBACK_BITS { // bits description - Uint16 BNKPWR0:2; // 1:0 Bank Power Mode of BANK0 - Uint16 BNKPWR1:2; // 3:2 Bank Power Mode of BANK1 - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBFALLBACK_REG { - Uint32 all; - struct FBFALLBACK_BITS bit; -}; - -struct FBPRDY_BITS { // bits description - Uint16 BANK0RDY:1; // 0 Flash Bank Active Power State - Uint16 BANK1RDY:1; // 1 Flash Bank Active Power State - Uint16 rsvd1:13; // 14:2 Reserved - Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBPRDY_REG { - Uint32 all; - struct FBPRDY_BITS bit; -}; - -struct FPAC1_BITS { // bits description - Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count - Uint16 rsvd2:4; // 31:28 Reserved -}; - -union FPAC1_REG { - Uint32 all; - struct FPAC1_BITS bit; -}; - -struct FPAC2_BITS { // bits description - Uint16 PAGP:16; // 15:0 Pump Active Grace Period - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union FPAC2_REG { - Uint32 all; - struct FPAC2_BITS bit; -}; - -struct FMSTAT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status - Uint16 CSTAT:1; // 4 Command Fail Status - Uint16 INVDAT:1; // 5 Invalid Data - Uint16 PGM:1; // 6 Program Operation Status - Uint16 ERS:1; // 7 Erase Operation Status - Uint16 BUSY:1; // 8 Busy Bit - Uint16 rsvd4:1; // 9 Reserved - Uint16 EV:1; // 10 Erase Verify Status - Uint16 rsvd5:1; // 11 Reserved - Uint16 PGV:1; // 12 Programming Verify Status - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:1; // 16 Reserved - Uint16 rsvd10:1; // 17 Reserved - Uint16 rsvd11:14; // 31:18 Reserved -}; - -union FMSTAT_REG { - Uint32 all; - struct FMSTAT_BITS bit; -}; - -struct FRD_INTF_CTRL_BITS { // bits description - Uint16 PREFETCH_EN:1; // 0 Prefetch Enable - Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FRD_INTF_CTRL_REG { - Uint32 all; - struct FRD_INTF_CTRL_BITS bit; -}; - -struct FLASH_CTRL_REGS { - union FRDCNTL_REG FRDCNTL; // Flash Read Control Register - Uint16 rsvd1[28]; // Reserved - union FBAC_REG FBAC; // Flash Bank Access Control Register - union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register - union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register - union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 - union FPAC2_REG FPAC2; // Flash Pump Access Control Register 2 - Uint16 rsvd2[2]; // Reserved - union FMSTAT_REG FMSTAT; // Flash Module Status Register - Uint16 rsvd3[340]; // Reserved - union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register -}; - -struct ECC_ENABLE_BITS { // bits description - Uint16 ENABLE:4; // 3:0 Enable ECC - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECC_ENABLE_REG { - Uint32 all; - struct ECC_ENABLE_BITS bit; -}; - -struct ERR_STATUS_BITS { // bits description - Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_REG { - Uint32 all; - struct ERR_STATUS_BITS bit; -}; - -struct ERR_POS_BITS { // bits description - Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits - Uint16 rsvd2:7; // 15:9 Reserved - Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits - Uint16 rsvd4:7; // 31:25 Reserved -}; - -union ERR_POS_REG { - Uint32 all; - struct ERR_POS_BITS bit; -}; - -struct ERR_STATUS_CLR_BITS { // bits description - Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_CLR_REG { - Uint32 all; - struct ERR_STATUS_CLR_BITS bit; -}; - -struct ERR_CNT_BITS { // bits description - Uint16 ERR_CNT:16; // 15:0 Error counter - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_CNT_REG { - Uint32 all; - struct ERR_CNT_BITS bit; -}; - -struct ERR_THRESHOLD_BITS { // bits description - Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_THRESHOLD_REG { - Uint32 all; - struct ERR_THRESHOLD_BITS bit; -}; - -struct ERR_INTFLG_BITS { // bits description - Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag - Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTFLG_REG { - Uint32 all; - struct ERR_INTFLG_BITS bit; -}; - -struct ERR_INTCLR_BITS { // bits description - Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear - Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTCLR_REG { - Uint32 all; - struct ERR_INTCLR_BITS bit; -}; - -struct FADDR_TEST_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ADDRL:13; // 15:3 ECC Address Low - Uint16 ADDRH:6; // 21:16 ECC Address High - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union FADDR_TEST_REG { - Uint32 all; - struct FADDR_TEST_BITS bit; -}; - -struct FECC_TEST_BITS { // bits description - Uint16 ECC:8; // 7:0 ECC Control Bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_TEST_REG { - Uint32 all; - struct FECC_TEST_BITS bit; -}; - -struct FECC_CTRL_BITS { // bits description - Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic - Uint16 ECC_SELECT:1; // 1 ECC Bit Select - Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_CTRL_REG { - Uint32 all; - struct FECC_CTRL_BITS bit; -}; - -struct FECC_STATUS_BITS { // bits description - Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error - Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error - Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error - Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error - Uint16 rsvd1:7; // 15:9 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_STATUS_REG { - Uint32 all; - struct FECC_STATUS_BITS bit; -}; - -struct FLASH_ECC_REGS { - union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable - Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low - Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High - Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low - Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High - union ERR_STATUS_REG ERR_STATUS; // Error Status - union ERR_POS_REG ERR_POS; // Error Position - union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear - union ERR_CNT_REG ERR_CNT; // Error Control - union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold - union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag - union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear - Uint32 FDATAH_TEST; // Data High Test - Uint32 FDATAL_TEST; // Data Low Test - union FADDR_TEST_REG FADDR_TEST; // ECC Test Address - union FECC_TEST_REG FECC_TEST; // ECC Test Address - union FECC_CTRL_REG FECC_CTRL; // ECC Control - Uint32 FOUTH_TEST; // Test Data Out High - Uint32 FOUTL_TEST; // Test Data Out Low - union FECC_STATUS_REG FECC_STATUS; // ECC Status -}; - -//--------------------------------------------------------------------------- -// FLASH External References & Function Declarations: -// -extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; -extern volatile struct FLASH_ECC_REGS Flash0EccRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h deleted file mode 100644 index 3b7a7e9..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h +++ /dev/null @@ -1,660 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_fsi.h -// -// TITLE: FSI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_FSI_H__ -#define __F28004X_FSI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FSI Individual Register Bit Definitions: - -struct TX_MASTER_CTRL_BITS { // bits description - Uint16 CORE_RST:1; // 0 Transmitter Master Core Reset - Uint16 FLUSH:1; // 1 Flush Operation Start - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union TX_MASTER_CTRL_REG { - Uint16 all; - struct TX_MASTER_CTRL_BITS bit; -}; - -struct TX_CLK_CTRL_BITS { // bits description - Uint16 CLK_RST:1; // 0 Soft Reset for the Clock Divider - Uint16 CLK_EN:1; // 1 Clock Divider Enable - Uint16 PRESCALE_VAL:8; // 9:2 Prescale value - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union TX_CLK_CTRL_REG { - Uint16 all; - struct TX_CLK_CTRL_BITS bit; -}; - -struct TX_OPER_CTRL_LO_BITS { // bits description - Uint16 DATA_WIDTH:2; // 1:0 Transmit Data width - Uint16 rsvd1:1; // 2 Reserved - Uint16 START_MODE:3; // 5:3 Transmission Start Mode Select - Uint16 SW_CRC:1; // 6 CRC Source Select - Uint16 PING_TO_MODE:1; // 7 Ping Counter Reset Mode Select - Uint16 SEL_PLLCLK:1; // 8 Input Clock Select - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union TX_OPER_CTRL_LO_REG { - Uint16 all; - struct TX_OPER_CTRL_LO_BITS bit; -}; - -struct TX_OPER_CTRL_HI_BITS { // bits description - Uint16 EXT_TRIG_SEL:5; // 4:0 External Trigger Select - Uint16 FORCE_ERR:1; // 5 Error Frame Force - Uint16 ECC_SEL:1; // 6 ECC Data Width Select - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TX_OPER_CTRL_HI_REG { - Uint16 all; - struct TX_OPER_CTRL_HI_BITS bit; -}; - -struct TX_FRAME_CTRL_BITS { // bits description - Uint16 FRAME_TYPE:4; // 3:0 Transmit Frame Type - Uint16 N_WORDS:4; // 7:4 Number of Words to be Transmitted - Uint16 rsvd1:7; // 14:8 Reserved - Uint16 START:1; // 15 Start Transmission -}; - -union TX_FRAME_CTRL_REG { - Uint16 all; - struct TX_FRAME_CTRL_BITS bit; -}; - -struct TX_FRAME_TAG_UDATA_BITS { // bits description - Uint16 FRAME_TAG:4; // 3:0 Frame Tag - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 USER_DATA:8; // 15:8 User Data -}; - -union TX_FRAME_TAG_UDATA_REG { - Uint16 all; - struct TX_FRAME_TAG_UDATA_BITS bit; -}; - -struct TX_BUF_PTR_LOAD_BITS { // bits description - Uint16 BUF_PTR_LOAD:4; // 3:0 Buffer Pointer Force Load - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_BUF_PTR_LOAD_REG { - Uint16 all; - struct TX_BUF_PTR_LOAD_BITS bit; -}; - -struct TX_BUF_PTR_STS_BITS { // bits description - Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 CURR_WORD_CNT:5; // 12:8 Remaining Words in Buffer - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union TX_BUF_PTR_STS_REG { - Uint16 all; - struct TX_BUF_PTR_STS_BITS bit; -}; - -struct TX_PING_CTRL_BITS { // bits description - Uint16 CNT_RST:1; // 0 Ping Counter Reset - Uint16 TIMER_EN:1; // 1 Ping Counter Enable - Uint16 EXT_TRIG_EN:1; // 2 External Trigger Enable - Uint16 EXT_TRIG_SEL:5; // 7:3 External Trigger Select - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_PING_CTRL_REG { - Uint16 all; - struct TX_PING_CTRL_BITS bit; -}; - -struct TX_PING_TAG_BITS { // bits description - Uint16 TAG:4; // 3:0 Ping Frame Tag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_PING_TAG_REG { - Uint16 all; - struct TX_PING_TAG_BITS bit; -}; - -struct TX_INT_CTRL_BITS { // bits description - Uint16 INT1_EN_FRAME_DONE:1; // 0 Enable Frame Done Interrupt to INT1 - Uint16 INT1_EN_BUF_UNDERRUN:1; // 1 Enable Buffer Underrun Interrupt to INT1 - Uint16 INT1_EN_BUF_OVERRUN:1; // 2 Enable Buffer Overrun Interrupt to INT1 - Uint16 INT1_EN_PING_TO:1; // 3 Enable Ping Timer Interrupt to INT1 - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 INT2_EN_FRAME_DONE:1; // 8 Enable Frame Done Interrupt to INT2 - Uint16 INT2_EN_BUF_UNDERRUN:1; // 9 Enable Buffer Underrun Interrupt to INT2 - Uint16 INT2_EN_BUF_OVERRUN:1; // 10 Enable Buffer Overrun Interrupt to INT2 - Uint16 INT2_EN_PING_TO:1; // 11 Enable Ping Timer Interrupt to INT2 - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union TX_INT_CTRL_REG { - Uint16 all; - struct TX_INT_CTRL_BITS bit; -}; - -struct TX_DMA_CTRL_BITS { // bits description - Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TX_DMA_CTRL_REG { - Uint16 all; - struct TX_DMA_CTRL_BITS bit; -}; - -struct TX_LOCK_CTRL_BITS { // bits description - Uint16 LOCK:1; // 0 Control Register Lock Enable - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union TX_LOCK_CTRL_REG { - Uint16 all; - struct TX_LOCK_CTRL_BITS bit; -}; - -struct TX_EVT_STS_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_STS_REG { - Uint16 all; - struct TX_EVT_STS_BITS bit; -}; - -struct TX_EVT_CLR_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag Clear - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Clear - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Clear - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_CLR_REG { - Uint16 all; - struct TX_EVT_CLR_BITS bit; -}; - -struct TX_EVT_FRC_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag Force - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Force - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Force - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Force - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_FRC_REG { - Uint16 all; - struct TX_EVT_FRC_BITS bit; -}; - -struct TX_USER_CRC_BITS { // bits description - Uint16 USER_CRC:8; // 7:0 User-defined CRC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_USER_CRC_REG { - Uint16 all; - struct TX_USER_CRC_BITS bit; -}; - -struct TX_ECC_DATA_BITS { // bits description - Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits - Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits -}; - -union TX_ECC_DATA_REG { - Uint32 all; - struct TX_ECC_DATA_BITS bit; -}; - -struct TX_ECC_VAL_BITS { // bits description - Uint16 ECC_VAL:8; // 7:0 Computed ECC Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_ECC_VAL_REG { - Uint16 all; - struct TX_ECC_VAL_BITS bit; -}; - -struct FSI_TX_REGS { - union TX_MASTER_CTRL_REG TX_MASTER_CTRL; // Transmit master control register - Uint16 rsvd1; // Reserved - union TX_CLK_CTRL_REG TX_CLK_CTRL; // Transmit clock control register - Uint16 rsvd2; // Reserved - union TX_OPER_CTRL_LO_REG TX_OPER_CTRL_LO; // Transmit operation control register low - union TX_OPER_CTRL_HI_REG TX_OPER_CTRL_HI; // Transmit operation control register high - union TX_FRAME_CTRL_REG TX_FRAME_CTRL; // Transmit frame control register - union TX_FRAME_TAG_UDATA_REG TX_FRAME_TAG_UDATA; // Transmit frame tag and user data register - union TX_BUF_PTR_LOAD_REG TX_BUF_PTR_LOAD; // Transmit buffer pointer control load register - union TX_BUF_PTR_STS_REG TX_BUF_PTR_STS; // Transmit buffer pointer control status register - union TX_PING_CTRL_REG TX_PING_CTRL; // Transmit ping control register - union TX_PING_TAG_REG TX_PING_TAG; // Transmit ping tag register - Uint32 TX_PING_TO_REF; // Transmit ping timeout counter reference - Uint32 TX_PING_TO_CNT; // Transmit ping timeout current count - union TX_INT_CTRL_REG TX_INT_CTRL; // Transmit interrupt event control register - union TX_DMA_CTRL_REG TX_DMA_CTRL; // Transmit DMA event control register - union TX_LOCK_CTRL_REG TX_LOCK_CTRL; // Transmit lock control register - Uint16 rsvd3; // Reserved - union TX_EVT_STS_REG TX_EVT_STS; // Transmit event and error status flag register - Uint16 rsvd4; // Reserved - union TX_EVT_CLR_REG TX_EVT_CLR; // Transmit event and error clear register - union TX_EVT_FRC_REG TX_EVT_FRC; // Transmit event and error flag force register - union TX_USER_CRC_REG TX_USER_CRC; // Transmit user-defined CRC register - Uint16 rsvd5[7]; // Reserved - union TX_ECC_DATA_REG TX_ECC_DATA; // Transmit ECC data register - union TX_ECC_VAL_REG TX_ECC_VAL; // Transmit ECC value register - Uint16 rsvd6[29]; // Reserved - Uint16 TX_BUF_BASE; // Base address for transmit buffer -}; - -struct RX_MASTER_CTRL_BITS { // bits description - Uint16 CORE_RST:1; // 0 Receiver Master Core Reset - Uint16 INT_LOOPBACK:1; // 1 Internal Loopback Enable - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:5; // 7:3 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union RX_MASTER_CTRL_REG { - Uint16 all; - struct RX_MASTER_CTRL_BITS bit; -}; - -struct RX_OPER_CTRL_BITS { // bits description - Uint16 DATA_WIDTH:2; // 1:0 Receive Data Width Select - Uint16 rsvd1:1; // 2 Reserved - Uint16 N_WORDS:4; // 6:3 Number of Words to be Received - Uint16 ECC_SEL:1; // 7 ECC Data Width Select - Uint16 PING_WD_RST_MODE:1; // 8 Ping Watchdog Timeout Mode Select - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union RX_OPER_CTRL_REG { - Uint16 all; - struct RX_OPER_CTRL_BITS bit; -}; - -struct RX_FRAME_INFO_BITS { // bits description - Uint16 FRAME_TYPE:4; // 3:0 Received Frame Type - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RX_FRAME_INFO_REG { - Uint16 all; - struct RX_FRAME_INFO_BITS bit; -}; - -struct RX_FRAME_TAG_UDATA_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 FRAME_TAG:4; // 4:1 Received Frame Tag - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 USER_DATA:8; // 15:8 Received User Data -}; - -union RX_FRAME_TAG_UDATA_REG { - Uint16 all; - struct RX_FRAME_TAG_UDATA_BITS bit; -}; - -struct RX_DMA_CTRL_BITS { // bits description - Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union RX_DMA_CTRL_REG { - Uint16 all; - struct RX_DMA_CTRL_BITS bit; -}; - -struct RX_EVT_STS_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag. - Uint16 CRC_ERR:1; // 2 CRC Error Flag - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag - Uint16 FRAME_DONE:1; // 6 Frame Done Flag - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag - Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_STS_REG { - Uint16 all; - struct RX_EVT_STS_BITS bit; -}; - -struct RX_CRC_INFO_BITS { // bits description - Uint16 RX_CRC:8; // 7:0 Received CRC Value - Uint16 CALC_CRC:8; // 15:8 Hardware Calculated CRC -}; - -union RX_CRC_INFO_REG { - Uint16 all; - struct RX_CRC_INFO_BITS bit; -}; - -struct RX_EVT_CLR_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Clear - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Clear - Uint16 CRC_ERR:1; // 2 CRC Error Flag Clear - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Clear - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Clear - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Clear - Uint16 FRAME_DONE:1; // 6 Frame Done Flag Clear - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Clear - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Clear - Uint16 PING_FRAME:1; // 9 PING Frame Received Flag Clear - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Clear - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Clear - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_CLR_REG { - Uint16 all; - struct RX_EVT_CLR_BITS bit; -}; - -struct RX_EVT_FRC_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Force - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Force - Uint16 CRC_ERR:1; // 2 CRC Error Flag Force - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Force - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Force - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Force - Uint16 FRAME_DONE:1; // 6 Frame Done Flag Force - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Force - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Force - Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Force - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Force - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Force - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_FRC_REG { - Uint16 all; - struct RX_EVT_FRC_BITS bit; -}; - -struct RX_BUF_PTR_LOAD_BITS { // bits description - Uint16 BUF_PTR_LOAD:4; // 3:0 Load value for receive buffer pointer - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RX_BUF_PTR_LOAD_REG { - Uint16 all; - struct RX_BUF_PTR_LOAD_BITS bit; -}; - -struct RX_BUF_PTR_STS_BITS { // bits description - Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 CURR_WORD_CNT:5; // 12:8 Available Words in Buffer - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union RX_BUF_PTR_STS_REG { - Uint16 all; - struct RX_BUF_PTR_STS_BITS bit; -}; - -struct RX_FRAME_WD_CTRL_BITS { // bits description - Uint16 FRAME_WD_CNT_RST:1; // 0 Frame Watchdog Counter Reset - Uint16 FRAME_WD_EN:1; // 1 Frame Watchdog Counter Enable - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_FRAME_WD_CTRL_REG { - Uint16 all; - struct RX_FRAME_WD_CTRL_BITS bit; -}; - -struct RX_PING_WD_CTRL_BITS { // bits description - Uint16 PING_WD_RST:1; // 0 Ping Watchdog Counter Reset - Uint16 PING_WD_EN:1; // 1 Ping Watchdog Counter Enable - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_PING_WD_CTRL_REG { - Uint16 all; - struct RX_PING_WD_CTRL_BITS bit; -}; - -struct RX_PING_TAG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PING_TAG:4; // 4:1 Ping Frame Tag - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union RX_PING_TAG_REG { - Uint16 all; - struct RX_PING_TAG_BITS bit; -}; - -struct RX_INT1_CTRL_BITS { // bits description - Uint16 INT1_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT1 - Uint16 INT1_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT1 - Uint16 INT1_EN_CRC_ERR:1; // 2 Enable CRC Error Interrupt to INT1 - Uint16 INT1_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT1 - Uint16 INT1_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT1 - Uint16 INT1_EN_OVERRUN:1; // 5 Enable Receive Buffer Overrun Interrupt to INT1 - Uint16 INT1_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT1 - Uint16 INT1_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT1 - Uint16 INT1_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT1 - Uint16 INT1_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT1 - Uint16 INT1_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT1 - Uint16 INT1_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT1 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_INT1_CTRL_REG { - Uint16 all; - struct RX_INT1_CTRL_BITS bit; -}; - -struct RX_INT2_CTRL_BITS { // bits description - Uint16 INT2_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT2 - Uint16 INT2_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT2 - Uint16 INT2_EN_CRC_ERR:1; // 2 Enable CRC Errror Interrupt to INT2 - Uint16 INT2_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT2 - Uint16 INT2_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT2 - Uint16 INT2_EN_OVERRUN:1; // 5 Enable Buffer Overrun Interrupt to INT2 - Uint16 INT2_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT2 - Uint16 INT2_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT2 - Uint16 INT2_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT2 - Uint16 INT2_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT2 - Uint16 INT2_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT2 - Uint16 INT2_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_INT2_CTRL_REG { - Uint16 all; - struct RX_INT2_CTRL_BITS bit; -}; - -struct RX_LOCK_CTRL_BITS { // bits description - Uint16 LOCK:1; // 0 Control Register Lock Enable - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union RX_LOCK_CTRL_REG { - Uint16 all; - struct RX_LOCK_CTRL_BITS bit; -}; - -struct RX_ECC_DATA_BITS { // bits description - Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits - Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits -}; - -union RX_ECC_DATA_REG { - Uint32 all; - struct RX_ECC_DATA_BITS bit; -}; - -struct RX_ECC_VAL_BITS { // bits description - Uint16 ECC_VAL:8; // 7:0 Computed ECC Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union RX_ECC_VAL_REG { - Uint16 all; - struct RX_ECC_VAL_BITS bit; -}; - -struct RX_ECC_LOG_BITS { // bits description - Uint16 SBE:1; // 0 Single Bit Error Detected - Uint16 MBE:1; // 1 Multiple Bit Errors Detected - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_ECC_LOG_REG { - Uint16 all; - struct RX_ECC_LOG_BITS bit; -}; - -struct RX_DLYLINE_CTRL_BITS { // bits description - Uint16 RXCLK_DLY:5; // 4:0 Delay Line Tap Select for RXCLK - Uint16 RXD0_DLY:5; // 9:5 Delay Line Tap Select for RXD0 - Uint16 RXD1_DLY:5; // 14:10 Delay Line Tap Select for RXD1 - Uint16 rsvd1:1; // 15 Reserved -}; - -union RX_DLYLINE_CTRL_REG { - Uint16 all; - struct RX_DLYLINE_CTRL_BITS bit; -}; - -struct RX_VIS_1_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 RX_CORE_STS:1; // 3 Receiver Core Status - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union RX_VIS_1_REG { - Uint32 all; - struct RX_VIS_1_BITS bit; -}; - -struct FSI_RX_REGS { - union RX_MASTER_CTRL_REG RX_MASTER_CTRL; // Receive master control register - Uint16 rsvd1[3]; // Reserved - union RX_OPER_CTRL_REG RX_OPER_CTRL; // Receive operation control register - Uint16 rsvd2; // Reserved - union RX_FRAME_INFO_REG RX_FRAME_INFO; // Receive frame control register - union RX_FRAME_TAG_UDATA_REG RX_FRAME_TAG_UDATA; // Receive frame tag and user data register - union RX_DMA_CTRL_REG RX_DMA_CTRL; // Receive DMA event control register - Uint16 rsvd3; // Reserved - union RX_EVT_STS_REG RX_EVT_STS; // Receive event and error status flag register - union RX_CRC_INFO_REG RX_CRC_INFO; // Receive CRC info of received and computed CRC - union RX_EVT_CLR_REG RX_EVT_CLR; // Receive event and error clear register - union RX_EVT_FRC_REG RX_EVT_FRC; // Receive event and error flag force register - union RX_BUF_PTR_LOAD_REG RX_BUF_PTR_LOAD; // Receive buffer pointer load register - union RX_BUF_PTR_STS_REG RX_BUF_PTR_STS; // Receive buffer pointer status register - union RX_FRAME_WD_CTRL_REG RX_FRAME_WD_CTRL; // Receive frame watchdog control register - Uint16 rsvd4; // Reserved - Uint32 RX_FRAME_WD_REF; // Receive frame watchdog counter reference - Uint32 RX_FRAME_WD_CNT; // Receive frame watchdog current count - union RX_PING_WD_CTRL_REG RX_PING_WD_CTRL; // Receive ping watchdog control register - union RX_PING_TAG_REG RX_PING_TAG; // Receive ping tag register - Uint32 RX_PING_WD_REF; // Receive ping watchdog counter reference - Uint32 RX_PING_WD_CNT; // Receive pingwatchdog current count - union RX_INT1_CTRL_REG RX_INT1_CTRL; // Receive interrupt control register for RX_INT1 - union RX_INT2_CTRL_REG RX_INT2_CTRL; // Receive interrupt control register for RX_INT2 - union RX_LOCK_CTRL_REG RX_LOCK_CTRL; // Receive lock control register - Uint16 rsvd5; // Reserved - union RX_ECC_DATA_REG RX_ECC_DATA; // Receive ECC data register - union RX_ECC_VAL_REG RX_ECC_VAL; // Receive ECC value register - Uint16 rsvd6; // Reserved - Uint32 RX_ECC_SEC_DATA; // Receive ECC corrected data register - union RX_ECC_LOG_REG RX_ECC_LOG; // Receive ECC log and status register - Uint16 rsvd7[9]; // Reserved - union RX_DLYLINE_CTRL_REG RX_DLYLINE_CTRL; // Receive delay line control register - Uint16 rsvd8[7]; // Reserved - union RX_VIS_1_REG RX_VIS_1; // Receive debug visibility register 1 - Uint16 rsvd9[6]; // Reserved - Uint16 RX_BUF_BASE; // Base address for receive data buffer -}; - -//--------------------------------------------------------------------------- -// FSI External References & Function Declarations: -// -extern volatile struct FSI_TX_REGS FsiTxaRegs; -extern volatile struct FSI_RX_REGS FsiRxaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h deleted file mode 100644 index 0c05ef1..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h +++ /dev/null @@ -1,1678 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio.h -// -// TITLE: GPIO Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_GPIO_H__ -#define __F28004X_GPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// GPIO Individual Register Bit Definitions: - -struct GPACTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 -}; - -union GPACTRL_REG { - Uint32 all; - struct GPACTRL_BITS bit; -}; - -struct GPAQSEL1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 - Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 - Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 - Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 - Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 - Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 - Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 - Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 - Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 - Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 - Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 - Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 - Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 - Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 - Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 - Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 -}; - -union GPAQSEL1_REG { - Uint32 all; - struct GPAQSEL1_BITS bit; -}; - -struct GPAQSEL2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 - Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 - Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 - Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 - Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 - Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 - Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 - Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 - Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 - Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 - Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 - Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 - Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 - Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 - Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 - Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 -}; - -union GPAQSEL2_REG { - Uint32 all; - struct GPAQSEL2_BITS bit; -}; - -struct GPAMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAMUX1_REG { - Uint32 all; - struct GPAMUX1_BITS bit; -}; - -struct GPAMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAMUX2_REG { - Uint32 all; - struct GPAMUX2_BITS bit; -}; - -struct GPADIR_BITS { // bits description - Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPADIR_REG { - Uint32 all; - struct GPADIR_BITS bit; -}; - -struct GPAPUD_BITS { // bits description - Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin -}; - -union GPAPUD_REG { - Uint32 all; - struct GPAPUD_BITS bit; -}; - -struct GPAINV_BITS { // bits description - Uint16 GPIO0:1; // 0 Input inversion control for this pin - Uint16 GPIO1:1; // 1 Input inversion control for this pin - Uint16 GPIO2:1; // 2 Input inversion control for this pin - Uint16 GPIO3:1; // 3 Input inversion control for this pin - Uint16 GPIO4:1; // 4 Input inversion control for this pin - Uint16 GPIO5:1; // 5 Input inversion control for this pin - Uint16 GPIO6:1; // 6 Input inversion control for this pin - Uint16 GPIO7:1; // 7 Input inversion control for this pin - Uint16 GPIO8:1; // 8 Input inversion control for this pin - Uint16 GPIO9:1; // 9 Input inversion control for this pin - Uint16 GPIO10:1; // 10 Input inversion control for this pin - Uint16 GPIO11:1; // 11 Input inversion control for this pin - Uint16 GPIO12:1; // 12 Input inversion control for this pin - Uint16 GPIO13:1; // 13 Input inversion control for this pin - Uint16 GPIO14:1; // 14 Input inversion control for this pin - Uint16 GPIO15:1; // 15 Input inversion control for this pin - Uint16 GPIO16:1; // 16 Input inversion control for this pin - Uint16 GPIO17:1; // 17 Input inversion control for this pin - Uint16 GPIO18:1; // 18 Input inversion control for this pin - Uint16 GPIO19:1; // 19 Input inversion control for this pin - Uint16 GPIO20:1; // 20 Input inversion control for this pin - Uint16 GPIO21:1; // 21 Input inversion control for this pin - Uint16 GPIO22:1; // 22 Input inversion control for this pin - Uint16 GPIO23:1; // 23 Input inversion control for this pin - Uint16 GPIO24:1; // 24 Input inversion control for this pin - Uint16 GPIO25:1; // 25 Input inversion control for this pin - Uint16 GPIO26:1; // 26 Input inversion control for this pin - Uint16 GPIO27:1; // 27 Input inversion control for this pin - Uint16 GPIO28:1; // 28 Input inversion control for this pin - Uint16 GPIO29:1; // 29 Input inversion control for this pin - Uint16 GPIO30:1; // 30 Input inversion control for this pin - Uint16 GPIO31:1; // 31 Input inversion control for this pin -}; - -union GPAINV_REG { - Uint32 all; - struct GPAINV_BITS bit; -}; - -struct GPAODR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Open-Drain control for this pin - Uint16 GPIO1:1; // 1 Output Open-Drain control for this pin - Uint16 GPIO2:1; // 2 Output Open-Drain control for this pin - Uint16 GPIO3:1; // 3 Output Open-Drain control for this pin - Uint16 GPIO4:1; // 4 Output Open-Drain control for this pin - Uint16 GPIO5:1; // 5 Output Open-Drain control for this pin - Uint16 GPIO6:1; // 6 Output Open-Drain control for this pin - Uint16 GPIO7:1; // 7 Output Open-Drain control for this pin - Uint16 GPIO8:1; // 8 Output Open-Drain control for this pin - Uint16 GPIO9:1; // 9 Output Open-Drain control for this pin - Uint16 GPIO10:1; // 10 Output Open-Drain control for this pin - Uint16 GPIO11:1; // 11 Output Open-Drain control for this pin - Uint16 GPIO12:1; // 12 Output Open-Drain control for this pin - Uint16 GPIO13:1; // 13 Output Open-Drain control for this pin - Uint16 GPIO14:1; // 14 Output Open-Drain control for this pin - Uint16 GPIO15:1; // 15 Output Open-Drain control for this pin - Uint16 GPIO16:1; // 16 Output Open-Drain control for this pin - Uint16 GPIO17:1; // 17 Output Open-Drain control for this pin - Uint16 GPIO18:1; // 18 Output Open-Drain control for this pin - Uint16 GPIO19:1; // 19 Output Open-Drain control for this pin - Uint16 GPIO20:1; // 20 Output Open-Drain control for this pin - Uint16 GPIO21:1; // 21 Output Open-Drain control for this pin - Uint16 GPIO22:1; // 22 Output Open-Drain control for this pin - Uint16 GPIO23:1; // 23 Output Open-Drain control for this pin - Uint16 GPIO24:1; // 24 Output Open-Drain control for this pin - Uint16 GPIO25:1; // 25 Output Open-Drain control for this pin - Uint16 GPIO26:1; // 26 Output Open-Drain control for this pin - Uint16 GPIO27:1; // 27 Output Open-Drain control for this pin - Uint16 GPIO28:1; // 28 Output Open-Drain control for this pin - Uint16 GPIO29:1; // 29 Output Open-Drain control for this pin - Uint16 GPIO30:1; // 30 Output Open-Drain control for this pin - Uint16 GPIO31:1; // 31 Output Open-Drain control for this pin -}; - -union GPAODR_REG { - Uint32 all; - struct GPAODR_BITS bit; -}; - -struct GPAAMSEL_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:1; // 8 Reserved - Uint16 rsvd10:1; // 9 Reserved - Uint16 rsvd11:1; // 10 Reserved - Uint16 rsvd12:1; // 11 Reserved - Uint16 rsvd13:1; // 12 Reserved - Uint16 rsvd14:1; // 13 Reserved - Uint16 rsvd15:1; // 14 Reserved - Uint16 rsvd16:1; // 15 Reserved - Uint16 rsvd17:1; // 16 Reserved - Uint16 rsvd18:1; // 17 Reserved - Uint16 rsvd19:1; // 18 Reserved - Uint16 rsvd20:1; // 19 Reserved - Uint16 rsvd21:1; // 20 Reserved - Uint16 rsvd22:1; // 21 Reserved - Uint16 GPIO22:1; // 22 Analog Mode select for this pin - Uint16 GPIO23:1; // 23 Analog Mode select for this pin - Uint16 rsvd23:1; // 24 Reserved - Uint16 rsvd24:1; // 25 Reserved - Uint16 rsvd25:1; // 26 Reserved - Uint16 rsvd26:1; // 27 Reserved - Uint16 rsvd27:1; // 28 Reserved - Uint16 rsvd28:1; // 29 Reserved - Uint16 rsvd29:1; // 30 Reserved - Uint16 rsvd30:1; // 31 Reserved -}; - -union GPAAMSEL_REG { - Uint32 all; - struct GPAAMSEL_BITS bit; -}; - -struct GPAGMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAGMUX1_REG { - Uint32 all; - struct GPAGMUX1_BITS bit; -}; - -struct GPAGMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAGMUX2_REG { - Uint32 all; - struct GPAGMUX2_BITS bit; -}; - -struct GPACSEL1_BITS { // bits description - Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select - Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select - Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select - Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select - Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select - Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select - Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select - Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select -}; - -union GPACSEL1_REG { - Uint32 all; - struct GPACSEL1_BITS bit; -}; - -struct GPACSEL2_BITS { // bits description - Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select - Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select - Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select - Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select - Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select - Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select - Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select - Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select -}; - -union GPACSEL2_REG { - Uint32 all; - struct GPACSEL2_BITS bit; -}; - -struct GPACSEL3_BITS { // bits description - Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select - Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select - Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select - Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select - Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select - Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select - Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select - Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select -}; - -union GPACSEL3_REG { - Uint32 all; - struct GPACSEL3_BITS bit; -}; - -struct GPACSEL4_BITS { // bits description - Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select - Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select - Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select - Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select - Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select - Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select - Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select - Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select -}; - -union GPACSEL4_REG { - Uint32 all; - struct GPACSEL4_BITS bit; -}; - -struct GPALOCK_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin -}; - -union GPALOCK_REG { - Uint32 all; - struct GPALOCK_BITS bit; -}; - -struct GPACR_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin -}; - -union GPACR_REG { - Uint32 all; - struct GPACR_BITS bit; -}; - -struct GPBCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 -}; - -union GPBCTRL_REG { - Uint32 all; - struct GPBCTRL_BITS bit; -}; - -struct GPBQSEL1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 - Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 - Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 - Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 - Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 - Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 - Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 - Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 - Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 - Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 - Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 - Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 -}; - -union GPBQSEL1_REG { - Uint32 all; - struct GPBQSEL1_BITS bit; -}; - -struct GPBQSEL2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 - Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 - Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 - Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 - Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 - Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 - Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 - Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 - Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 - Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 - Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 - Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBQSEL2_REG { - Uint32 all; - struct GPBQSEL2_BITS bit; -}; - -struct GPBMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBMUX1_REG { - Uint32 all; - struct GPBMUX1_BITS bit; -}; - -struct GPBMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBMUX2_REG { - Uint32 all; - struct GPBMUX2_BITS bit; -}; - -struct GPBDIR_BITS { // bits description - Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBDIR_REG { - Uint32 all; - struct GPBDIR_BITS bit; -}; - -struct GPBPUD_BITS { // bits description - Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBPUD_REG { - Uint32 all; - struct GPBPUD_BITS bit; -}; - -struct GPBINV_BITS { // bits description - Uint16 GPIO32:1; // 0 Input inversion control for this pin - Uint16 GPIO33:1; // 1 Input inversion control for this pin - Uint16 GPIO34:1; // 2 Input inversion control for this pin - Uint16 GPIO35:1; // 3 Input inversion control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Input inversion control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Input inversion control for this pin - Uint16 GPIO40:1; // 8 Input inversion control for this pin - Uint16 GPIO41:1; // 9 Input inversion control for this pin - Uint16 GPIO42:1; // 10 Input inversion control for this pin - Uint16 GPIO43:1; // 11 Input inversion control for this pin - Uint16 GPIO44:1; // 12 Input inversion control for this pin - Uint16 GPIO45:1; // 13 Input inversion control for this pin - Uint16 GPIO46:1; // 14 Input inversion control for this pin - Uint16 GPIO47:1; // 15 Input inversion control for this pin - Uint16 GPIO48:1; // 16 Input inversion control for this pin - Uint16 GPIO49:1; // 17 Input inversion control for this pin - Uint16 GPIO50:1; // 18 Input inversion control for this pin - Uint16 GPIO51:1; // 19 Input inversion control for this pin - Uint16 GPIO52:1; // 20 Input inversion control for this pin - Uint16 GPIO53:1; // 21 Input inversion control for this pin - Uint16 GPIO54:1; // 22 Input inversion control for this pin - Uint16 GPIO55:1; // 23 Input inversion control for this pin - Uint16 GPIO56:1; // 24 Input inversion control for this pin - Uint16 GPIO57:1; // 25 Input inversion control for this pin - Uint16 GPIO58:1; // 26 Input inversion control for this pin - Uint16 GPIO59:1; // 27 Input inversion control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBINV_REG { - Uint32 all; - struct GPBINV_BITS bit; -}; - -struct GPBODR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Open-Drain control for this pin - Uint16 GPIO33:1; // 1 Output Open-Drain control for this pin - Uint16 GPIO34:1; // 2 Output Open-Drain control for this pin - Uint16 GPIO35:1; // 3 Output Open-Drain control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Open-Drain control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Open-Drain control for this pin - Uint16 GPIO40:1; // 8 Output Open-Drain control for this pin - Uint16 GPIO41:1; // 9 Output Open-Drain control for this pin - Uint16 GPIO42:1; // 10 Output Open-Drain control for this pin - Uint16 GPIO43:1; // 11 Output Open-Drain control for this pin - Uint16 GPIO44:1; // 12 Output Open-Drain control for this pin - Uint16 GPIO45:1; // 13 Output Open-Drain control for this pin - Uint16 GPIO46:1; // 14 Output Open-Drain control for this pin - Uint16 GPIO47:1; // 15 Output Open-Drain control for this pin - Uint16 GPIO48:1; // 16 Output Open-Drain control for this pin - Uint16 GPIO49:1; // 17 Output Open-Drain control for this pin - Uint16 GPIO50:1; // 18 Output Open-Drain control for this pin - Uint16 GPIO51:1; // 19 Output Open-Drain control for this pin - Uint16 GPIO52:1; // 20 Output Open-Drain control for this pin - Uint16 GPIO53:1; // 21 Output Open-Drain control for this pin - Uint16 GPIO54:1; // 22 Output Open-Drain control for this pin - Uint16 GPIO55:1; // 23 Output Open-Drain control for this pin - Uint16 GPIO56:1; // 24 Output Open-Drain control for this pin - Uint16 GPIO57:1; // 25 Output Open-Drain control for this pin - Uint16 GPIO58:1; // 26 Output Open-Drain control for this pin - Uint16 GPIO59:1; // 27 Output Open-Drain control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBODR_REG { - Uint32 all; - struct GPBODR_BITS bit; -}; - -struct GPBGMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBGMUX1_REG { - Uint32 all; - struct GPBGMUX1_BITS bit; -}; - -struct GPBGMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBGMUX2_REG { - Uint32 all; - struct GPBGMUX2_BITS bit; -}; - -struct GPBCSEL1_BITS { // bits description - Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select - Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select - Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select - Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select - Uint16 rsvd1:4; // 19:16 Reserved - Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select - Uint16 rsvd2:4; // 27:24 Reserved - Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select -}; - -union GPBCSEL1_REG { - Uint32 all; - struct GPBCSEL1_BITS bit; -}; - -struct GPBCSEL2_BITS { // bits description - Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select - Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select - Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select - Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select - Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select - Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select - Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select - Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select -}; - -union GPBCSEL2_REG { - Uint32 all; - struct GPBCSEL2_BITS bit; -}; - -struct GPBCSEL3_BITS { // bits description - Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select - Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select - Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select - Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select - Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select - Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select - Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select - Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select -}; - -union GPBCSEL3_REG { - Uint32 all; - struct GPBCSEL3_BITS bit; -}; - -struct GPBCSEL4_BITS { // bits description - Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select - Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select - Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select - Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select - Uint16 rsvd1:4; // 19:16 Reserved - Uint16 rsvd2:4; // 23:20 Reserved - Uint16 rsvd3:4; // 27:24 Reserved - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union GPBCSEL4_REG { - Uint32 all; - struct GPBCSEL4_BITS bit; -}; - -struct GPBLOCK_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBLOCK_REG { - Uint32 all; - struct GPBLOCK_BITS bit; -}; - -struct GPBCR_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBCR_REG { - Uint32 all; - struct GPBCR_BITS bit; -}; - -struct GPHCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO224 to GPIO231 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO232 to GPIO239 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO240 to GPIO247 - Uint16 rsvd1:8; // 31:24 Reserved -}; - -union GPHCTRL_REG { - Uint32 all; - struct GPHCTRL_BITS bit; -}; - -struct GPHQSEL1_BITS { // bits description - Uint16 GPIO224:2; // 1:0 Select input qualification type for this GPIO Pin - Uint16 GPIO225:2; // 3:2 Select input qualification type for this GPIO Pin - Uint16 GPIO226:2; // 5:4 Select input qualification type for this GPIO Pin - Uint16 GPIO227:2; // 7:6 Select input qualification type for this GPIO Pin - Uint16 GPIO228:2; // 9:8 Select input qualification type for this GPIO Pin - Uint16 GPIO229:2; // 11:10 Select input qualification type for this GPIO Pin - Uint16 GPIO230:2; // 13:12 Select input qualification type for this GPIO Pin - Uint16 GPIO231:2; // 15:14 Select input qualification type for this GPIO Pin - Uint16 GPIO232:2; // 17:16 Select input qualification type for this GPIO Pin - Uint16 GPIO233:2; // 19:18 Select input qualification type for this GPIO Pin - Uint16 GPIO234:2; // 21:20 Select input qualification type for this GPIO Pin - Uint16 GPIO235:2; // 23:22 Select input qualification type for this GPIO Pin - Uint16 GPIO236:2; // 25:24 Select input qualification type for this GPIO Pin - Uint16 GPIO237:2; // 27:26 Select input qualification type for this GPIO Pin - Uint16 GPIO238:2; // 29:28 Select input qualification type for this GPIO Pin - Uint16 GPIO239:2; // 31:30 Select input qualification type for this GPIO Pin -}; - -union GPHQSEL1_REG { - Uint32 all; - struct GPHQSEL1_BITS bit; -}; - -struct GPHQSEL2_BITS { // bits description - Uint16 GPIO240:2; // 1:0 Select input qualification type for this GPIO Pin - Uint16 GPIO241:2; // 3:2 Select input qualification type for this GPIO Pin - Uint16 GPIO242:2; // 5:4 Select input qualification type for this GPIO Pin - Uint16 GPIO243:2; // 7:6 Select input qualification type for this GPIO Pin - Uint16 GPIO244:2; // 9:8 Select input qualification type for this GPIO Pin - Uint16 GPIO245:2; // 11:10 Select input qualification type for this GPIO Pin - Uint16 GPIO246:2; // 13:12 Select input qualification type for this GPIO Pin - Uint16 GPIO247:2; // 15:14 Select input qualification type for this GPIO Pin - Uint16 rsvd1:2; // 17:16 Reserved - Uint16 rsvd2:2; // 19:18 Reserved - Uint16 rsvd3:2; // 21:20 Reserved - Uint16 rsvd4:2; // 23:22 Reserved - Uint16 rsvd5:2; // 25:24 Reserved - Uint16 rsvd6:2; // 27:26 Reserved - Uint16 rsvd7:2; // 29:28 Reserved - Uint16 rsvd8:2; // 31:30 Reserved -}; - -union GPHQSEL2_REG { - Uint32 all; - struct GPHQSEL2_BITS bit; -}; - -struct GPHINV_BITS { // bits description - Uint16 GPIO224:1; // 0 Input inversion control for this pin - Uint16 GPIO225:1; // 1 Input inversion control for this pin - Uint16 GPIO226:1; // 2 Input inversion control for this pin - Uint16 GPIO227:1; // 3 Input inversion control for this pin - Uint16 GPIO228:1; // 4 Input inversion control for this pin - Uint16 GPIO229:1; // 5 Input inversion control for this pin - Uint16 GPIO230:1; // 6 Input inversion control for this pin - Uint16 GPIO231:1; // 7 Input inversion control for this pin - Uint16 GPIO232:1; // 8 Input inversion control for this pin - Uint16 GPIO233:1; // 9 Input inversion control for this pin - Uint16 GPIO234:1; // 10 Input inversion control for this pin - Uint16 GPIO235:1; // 11 Input inversion control for this pin - Uint16 GPIO236:1; // 12 Input inversion control for this pin - Uint16 GPIO237:1; // 13 Input inversion control for this pin - Uint16 GPIO238:1; // 14 Input inversion control for this pin - Uint16 GPIO239:1; // 15 Input inversion control for this pin - Uint16 GPIO240:1; // 16 Input inversion control for this pin - Uint16 GPIO241:1; // 17 Input inversion control for this pin - Uint16 GPIO242:1; // 18 Input inversion control for this pin - Uint16 GPIO243:1; // 19 Input inversion control for this pin - Uint16 GPIO244:1; // 20 Input inversion control for this pin - Uint16 GPIO245:1; // 21 Input inversion control for this pin - Uint16 GPIO246:1; // 22 Input inversion control for this pin - Uint16 GPIO247:1; // 23 Input inversion control for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHINV_REG { - Uint32 all; - struct GPHINV_BITS bit; -}; - -struct GPHAMSEL_BITS { // bits description - Uint16 GPIO224:1; // 0 Analog Mode select for this pin - Uint16 GPIO225:1; // 1 Analog Mode select for this pin - Uint16 GPIO226:1; // 2 Analog Mode select for this pin - Uint16 GPIO227:1; // 3 Analog Mode select for this pin - Uint16 GPIO228:1; // 4 Analog Mode select for this pin - Uint16 GPIO229:1; // 5 Analog Mode select for this pin - Uint16 GPIO230:1; // 6 Analog Mode select for this pin - Uint16 GPIO231:1; // 7 Analog Mode select for this pin - Uint16 GPIO232:1; // 8 Analog Mode select for this pin - Uint16 GPIO233:1; // 9 Analog Mode select for this pin - Uint16 GPIO234:1; // 10 Analog Mode select for this pin - Uint16 GPIO235:1; // 11 Analog Mode select for this pin - Uint16 GPIO236:1; // 12 Analog Mode select for this pin - Uint16 GPIO237:1; // 13 Analog Mode select for this pin - Uint16 GPIO238:1; // 14 Analog Mode select for this pin - Uint16 GPIO239:1; // 15 Analog Mode select for this pin - Uint16 GPIO240:1; // 16 Analog Mode select for this pin - Uint16 GPIO241:1; // 17 Analog Mode select for this pin - Uint16 GPIO242:1; // 18 Analog Mode select for this pin - Uint16 GPIO243:1; // 19 Analog Mode select for this pin - Uint16 GPIO244:1; // 20 Analog Mode select for this pin - Uint16 GPIO245:1; // 21 Analog Mode select for this pin - Uint16 GPIO246:1; // 22 Analog Mode select for this pin - Uint16 GPIO247:1; // 23 Analog Mode select for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHAMSEL_REG { - Uint32 all; - struct GPHAMSEL_BITS bit; -}; - -struct GPHLOCK_BITS { // bits description - Uint16 GPIO224:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO225:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO226:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO227:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO228:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO229:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO230:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO231:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO232:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO233:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO234:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO235:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO236:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO237:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO238:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO239:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO240:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO241:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO242:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO243:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO244:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO245:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO246:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO247:1; // 23 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHLOCK_REG { - Uint32 all; - struct GPHLOCK_BITS bit; -}; - -struct GPHCR_BITS { // bits description - Uint16 GPIO224:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO225:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO226:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO227:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO228:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO229:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO230:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO231:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO232:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO233:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO234:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO235:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO236:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO237:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO238:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO239:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO240:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO241:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO242:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO243:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO244:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO245:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO246:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO247:1; // 23 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHCR_REG { - Uint32 all; - struct GPHCR_BITS bit; -}; - -struct GPIO_CTRL_REGS { - union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period (GPIO0 to GPIO31) - union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualification Type (GPIO0 to GPIO15) - union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualification Type (GPIO16 to GPIO31) - union GPAMUX1_REG GPAMUX1; // GPIO A Peripheral Mux (GPIO0 to GPIO15) - union GPAMUX2_REG GPAMUX2; // GPIO A Peripheral Mux (GPIO16 to GPIO31) - union GPADIR_REG GPADIR; // GPIO A Direction (GPIO0 to GPIO31) - union GPAPUD_REG GPAPUD; // GPIO A Pull-Up Disable (GPIO0 to GPIO31) - Uint16 rsvd1[2]; // Reserved - union GPAINV_REG GPAINV; // GPIO A Input Inversion (GPIO0 to GPIO31) - union GPAODR_REG GPAODR; // GPIO A Open Drain Output Mode (GPIO0 to GPIO31) - union GPAAMSEL_REG GPAAMSEL; // GPIO A Analog Mode Select (GPIO0 to GPIO31) - Uint16 rsvd2[10]; // Reserved - union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to GPIO15) - union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to GPIO31) - Uint16 rsvd3[4]; // Reserved - union GPACSEL1_REG GPACSEL1; // GPIO A Master Core Select (GPIO0 to GPIO7) - union GPACSEL2_REG GPACSEL2; // GPIO A Master Core Select (GPIO8 to GPIO15) - union GPACSEL3_REG GPACSEL3; // GPIO A Master Core Select (GPIO16 to GPIO23) - union GPACSEL4_REG GPACSEL4; // GPIO A Master Core Select (GPIO24 to GPIO31) - Uint16 rsvd4[12]; // Reserved - union GPALOCK_REG GPALOCK; // GPIO A Lock Register (GPIO0 to GPIO31) - union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to GPIO31) - union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period (GPIO32 to GPIO63) - union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualification Type (GPIO32 to GPIO47) - union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualification Type (GPIO48 to GPIO63) - union GPBMUX1_REG GPBMUX1; // GPIO B Peripheral Mux (GPIO32 to GPIO47) - union GPBMUX2_REG GPBMUX2; // GPIO B Peripheral Mux (GPIO48 to GPIO63) - union GPBDIR_REG GPBDIR; // GPIO B Direction (GPIO32 to GPIO63) - union GPBPUD_REG GPBPUD; // GPIO B Pull-Up Disable (GPIO32 to GPIO63) - Uint16 rsvd5[2]; // Reserved - union GPBINV_REG GPBINV; // GPIO B Input Inversion (GPIO32 to GPIO63) - union GPBODR_REG GPBODR; // GPIO B Open Drain Output Mode (GPIO32 to GPIO63) - Uint16 rsvd6[12]; // Reserved - union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to GPIO47) - union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to GPIO63) - Uint16 rsvd7[4]; // Reserved - union GPBCSEL1_REG GPBCSEL1; // GPIO B Master Core Select (GPIO32 to GPIO39) - union GPBCSEL2_REG GPBCSEL2; // GPIO B Master Core Select (GPIO40 to GPIO47) - union GPBCSEL3_REG GPBCSEL3; // GPIO B Master Core Select (GPIO48 to GPIO55) - union GPBCSEL4_REG GPBCSEL4; // GPIO B Master Core Select (GPIO56 to GPIO63) - Uint16 rsvd8[12]; // Reserved - union GPBLOCK_REG GPBLOCK; // GPIO B Lock Register (GPIO32 to GPIO63) - union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to GPIO63) - Uint16 rsvd9[320]; // Reserved - union GPHCTRL_REG GPHCTRL; // GPIO H Qualification Sampling Period (GPIO224 to GPIO255) - union GPHQSEL1_REG GPHQSEL1; // GPIO H Qualification Type (GPIO224 to GPIO239) - union GPHQSEL2_REG GPHQSEL2; // GPIO H Qualification Type (GPIO240 to GPIO255) - Uint16 rsvd10[10]; // Reserved - union GPHINV_REG GPHINV; // GPIO H Input Inversion (GPIO224 to GPIO255) - Uint16 rsvd11[2]; // Reserved - union GPHAMSEL_REG GPHAMSEL; // GPIO H Analog Mode Select (GPIO224 to GPIO255) - Uint16 rsvd12[38]; // Reserved - union GPHLOCK_REG GPHLOCK; // GPIO H Lock Register (GPIO224 to GPIO255) - union GPHCR_REG GPHCR; // GPIO H Lock Commit Register (GPIO224 to GPIO255) -}; - -struct GPADAT_BITS { // bits description - Uint16 GPIO0:1; // 0 Data Register for this pin - Uint16 GPIO1:1; // 1 Data Register for this pin - Uint16 GPIO2:1; // 2 Data Register for this pin - Uint16 GPIO3:1; // 3 Data Register for this pin - Uint16 GPIO4:1; // 4 Data Register for this pin - Uint16 GPIO5:1; // 5 Data Register for this pin - Uint16 GPIO6:1; // 6 Data Register for this pin - Uint16 GPIO7:1; // 7 Data Register for this pin - Uint16 GPIO8:1; // 8 Data Register for this pin - Uint16 GPIO9:1; // 9 Data Register for this pin - Uint16 GPIO10:1; // 10 Data Register for this pin - Uint16 GPIO11:1; // 11 Data Register for this pin - Uint16 GPIO12:1; // 12 Data Register for this pin - Uint16 GPIO13:1; // 13 Data Register for this pin - Uint16 GPIO14:1; // 14 Data Register for this pin - Uint16 GPIO15:1; // 15 Data Register for this pin - Uint16 GPIO16:1; // 16 Data Register for this pin - Uint16 GPIO17:1; // 17 Data Register for this pin - Uint16 GPIO18:1; // 18 Data Register for this pin - Uint16 GPIO19:1; // 19 Data Register for this pin - Uint16 GPIO20:1; // 20 Data Register for this pin - Uint16 GPIO21:1; // 21 Data Register for this pin - Uint16 GPIO22:1; // 22 Data Register for this pin - Uint16 GPIO23:1; // 23 Data Register for this pin - Uint16 GPIO24:1; // 24 Data Register for this pin - Uint16 GPIO25:1; // 25 Data Register for this pin - Uint16 GPIO26:1; // 26 Data Register for this pin - Uint16 GPIO27:1; // 27 Data Register for this pin - Uint16 GPIO28:1; // 28 Data Register for this pin - Uint16 GPIO29:1; // 29 Data Register for this pin - Uint16 GPIO30:1; // 30 Data Register for this pin - Uint16 GPIO31:1; // 31 Data Register for this pin -}; - -union GPADAT_REG { - Uint32 all; - struct GPADAT_BITS bit; -}; - -struct GPASET_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Set bit for this pin - Uint16 GPIO1:1; // 1 Output Set bit for this pin - Uint16 GPIO2:1; // 2 Output Set bit for this pin - Uint16 GPIO3:1; // 3 Output Set bit for this pin - Uint16 GPIO4:1; // 4 Output Set bit for this pin - Uint16 GPIO5:1; // 5 Output Set bit for this pin - Uint16 GPIO6:1; // 6 Output Set bit for this pin - Uint16 GPIO7:1; // 7 Output Set bit for this pin - Uint16 GPIO8:1; // 8 Output Set bit for this pin - Uint16 GPIO9:1; // 9 Output Set bit for this pin - Uint16 GPIO10:1; // 10 Output Set bit for this pin - Uint16 GPIO11:1; // 11 Output Set bit for this pin - Uint16 GPIO12:1; // 12 Output Set bit for this pin - Uint16 GPIO13:1; // 13 Output Set bit for this pin - Uint16 GPIO14:1; // 14 Output Set bit for this pin - Uint16 GPIO15:1; // 15 Output Set bit for this pin - Uint16 GPIO16:1; // 16 Output Set bit for this pin - Uint16 GPIO17:1; // 17 Output Set bit for this pin - Uint16 GPIO18:1; // 18 Output Set bit for this pin - Uint16 GPIO19:1; // 19 Output Set bit for this pin - Uint16 GPIO20:1; // 20 Output Set bit for this pin - Uint16 GPIO21:1; // 21 Output Set bit for this pin - Uint16 GPIO22:1; // 22 Output Set bit for this pin - Uint16 GPIO23:1; // 23 Output Set bit for this pin - Uint16 GPIO24:1; // 24 Output Set bit for this pin - Uint16 GPIO25:1; // 25 Output Set bit for this pin - Uint16 GPIO26:1; // 26 Output Set bit for this pin - Uint16 GPIO27:1; // 27 Output Set bit for this pin - Uint16 GPIO28:1; // 28 Output Set bit for this pin - Uint16 GPIO29:1; // 29 Output Set bit for this pin - Uint16 GPIO30:1; // 30 Output Set bit for this pin - Uint16 GPIO31:1; // 31 Output Set bit for this pin -}; - -union GPASET_REG { - Uint32 all; - struct GPASET_BITS bit; -}; - -struct GPACLEAR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Clear bit for this pin - Uint16 GPIO1:1; // 1 Output Clear bit for this pin - Uint16 GPIO2:1; // 2 Output Clear bit for this pin - Uint16 GPIO3:1; // 3 Output Clear bit for this pin - Uint16 GPIO4:1; // 4 Output Clear bit for this pin - Uint16 GPIO5:1; // 5 Output Clear bit for this pin - Uint16 GPIO6:1; // 6 Output Clear bit for this pin - Uint16 GPIO7:1; // 7 Output Clear bit for this pin - Uint16 GPIO8:1; // 8 Output Clear bit for this pin - Uint16 GPIO9:1; // 9 Output Clear bit for this pin - Uint16 GPIO10:1; // 10 Output Clear bit for this pin - Uint16 GPIO11:1; // 11 Output Clear bit for this pin - Uint16 GPIO12:1; // 12 Output Clear bit for this pin - Uint16 GPIO13:1; // 13 Output Clear bit for this pin - Uint16 GPIO14:1; // 14 Output Clear bit for this pin - Uint16 GPIO15:1; // 15 Output Clear bit for this pin - Uint16 GPIO16:1; // 16 Output Clear bit for this pin - Uint16 GPIO17:1; // 17 Output Clear bit for this pin - Uint16 GPIO18:1; // 18 Output Clear bit for this pin - Uint16 GPIO19:1; // 19 Output Clear bit for this pin - Uint16 GPIO20:1; // 20 Output Clear bit for this pin - Uint16 GPIO21:1; // 21 Output Clear bit for this pin - Uint16 GPIO22:1; // 22 Output Clear bit for this pin - Uint16 GPIO23:1; // 23 Output Clear bit for this pin - Uint16 GPIO24:1; // 24 Output Clear bit for this pin - Uint16 GPIO25:1; // 25 Output Clear bit for this pin - Uint16 GPIO26:1; // 26 Output Clear bit for this pin - Uint16 GPIO27:1; // 27 Output Clear bit for this pin - Uint16 GPIO28:1; // 28 Output Clear bit for this pin - Uint16 GPIO29:1; // 29 Output Clear bit for this pin - Uint16 GPIO30:1; // 30 Output Clear bit for this pin - Uint16 GPIO31:1; // 31 Output Clear bit for this pin -}; - -union GPACLEAR_REG { - Uint32 all; - struct GPACLEAR_BITS bit; -}; - -struct GPATOGGLE_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Toggle bit for this pin - Uint16 GPIO1:1; // 1 Output Toggle bit for this pin - Uint16 GPIO2:1; // 2 Output Toggle bit for this pin - Uint16 GPIO3:1; // 3 Output Toggle bit for this pin - Uint16 GPIO4:1; // 4 Output Toggle bit for this pin - Uint16 GPIO5:1; // 5 Output Toggle bit for this pin - Uint16 GPIO6:1; // 6 Output Toggle bit for this pin - Uint16 GPIO7:1; // 7 Output Toggle bit for this pin - Uint16 GPIO8:1; // 8 Output Toggle bit for this pin - Uint16 GPIO9:1; // 9 Output Toggle bit for this pin - Uint16 GPIO10:1; // 10 Output Toggle bit for this pin - Uint16 GPIO11:1; // 11 Output Toggle bit for this pin - Uint16 GPIO12:1; // 12 Output Toggle bit for this pin - Uint16 GPIO13:1; // 13 Output Toggle bit for this pin - Uint16 GPIO14:1; // 14 Output Toggle bit for this pin - Uint16 GPIO15:1; // 15 Output Toggle bit for this pin - Uint16 GPIO16:1; // 16 Output Toggle bit for this pin - Uint16 GPIO17:1; // 17 Output Toggle bit for this pin - Uint16 GPIO18:1; // 18 Output Toggle bit for this pin - Uint16 GPIO19:1; // 19 Output Toggle bit for this pin - Uint16 GPIO20:1; // 20 Output Toggle bit for this pin - Uint16 GPIO21:1; // 21 Output Toggle bit for this pin - Uint16 GPIO22:1; // 22 Output Toggle bit for this pin - Uint16 GPIO23:1; // 23 Output Toggle bit for this pin - Uint16 GPIO24:1; // 24 Output Toggle bit for this pin - Uint16 GPIO25:1; // 25 Output Toggle bit for this pin - Uint16 GPIO26:1; // 26 Output Toggle bit for this pin - Uint16 GPIO27:1; // 27 Output Toggle bit for this pin - Uint16 GPIO28:1; // 28 Output Toggle bit for this pin - Uint16 GPIO29:1; // 29 Output Toggle bit for this pin - Uint16 GPIO30:1; // 30 Output Toggle bit for this pin - Uint16 GPIO31:1; // 31 Output Toggle bit for this pin -}; - -union GPATOGGLE_REG { - Uint32 all; - struct GPATOGGLE_BITS bit; -}; - -struct GPBDAT_BITS { // bits description - Uint16 GPIO32:1; // 0 Data Register for this pin - Uint16 GPIO33:1; // 1 Data Register for this pin - Uint16 GPIO34:1; // 2 Data Register for this pin - Uint16 GPIO35:1; // 3 Data Register for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Data Register for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Data Register for this pin - Uint16 GPIO40:1; // 8 Data Register for this pin - Uint16 GPIO41:1; // 9 Data Register for this pin - Uint16 GPIO42:1; // 10 Data Register for this pin - Uint16 GPIO43:1; // 11 Data Register for this pin - Uint16 GPIO44:1; // 12 Data Register for this pin - Uint16 GPIO45:1; // 13 Data Register for this pin - Uint16 GPIO46:1; // 14 Data Register for this pin - Uint16 GPIO47:1; // 15 Data Register for this pin - Uint16 GPIO48:1; // 16 Data Register for this pin - Uint16 GPIO49:1; // 17 Data Register for this pin - Uint16 GPIO50:1; // 18 Data Register for this pin - Uint16 GPIO51:1; // 19 Data Register for this pin - Uint16 GPIO52:1; // 20 Data Register for this pin - Uint16 GPIO53:1; // 21 Data Register for this pin - Uint16 GPIO54:1; // 22 Data Register for this pin - Uint16 GPIO55:1; // 23 Data Register for this pin - Uint16 GPIO56:1; // 24 Data Register for this pin - Uint16 GPIO57:1; // 25 Data Register for this pin - Uint16 GPIO58:1; // 26 Data Register for this pin - Uint16 GPIO59:1; // 27 Data Register for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBDAT_REG { - Uint32 all; - struct GPBDAT_BITS bit; -}; - -struct GPBSET_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Set bit for this pin - Uint16 GPIO33:1; // 1 Output Set bit for this pin - Uint16 GPIO34:1; // 2 Output Set bit for this pin - Uint16 GPIO35:1; // 3 Output Set bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Set bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Set bit for this pin - Uint16 GPIO40:1; // 8 Output Set bit for this pin - Uint16 GPIO41:1; // 9 Output Set bit for this pin - Uint16 GPIO42:1; // 10 Output Set bit for this pin - Uint16 GPIO43:1; // 11 Output Set bit for this pin - Uint16 GPIO44:1; // 12 Output Set bit for this pin - Uint16 GPIO45:1; // 13 Output Set bit for this pin - Uint16 GPIO46:1; // 14 Output Set bit for this pin - Uint16 GPIO47:1; // 15 Output Set bit for this pin - Uint16 GPIO48:1; // 16 Output Set bit for this pin - Uint16 GPIO49:1; // 17 Output Set bit for this pin - Uint16 GPIO50:1; // 18 Output Set bit for this pin - Uint16 GPIO51:1; // 19 Output Set bit for this pin - Uint16 GPIO52:1; // 20 Output Set bit for this pin - Uint16 GPIO53:1; // 21 Output Set bit for this pin - Uint16 GPIO54:1; // 22 Output Set bit for this pin - Uint16 GPIO55:1; // 23 Output Set bit for this pin - Uint16 GPIO56:1; // 24 Output Set bit for this pin - Uint16 GPIO57:1; // 25 Output Set bit for this pin - Uint16 GPIO58:1; // 26 Output Set bit for this pin - Uint16 GPIO59:1; // 27 Output Set bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBSET_REG { - Uint32 all; - struct GPBSET_BITS bit; -}; - -struct GPBCLEAR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Clear bit for this pin - Uint16 GPIO33:1; // 1 Output Clear bit for this pin - Uint16 GPIO34:1; // 2 Output Clear bit for this pin - Uint16 GPIO35:1; // 3 Output Clear bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Clear bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Clear bit for this pin - Uint16 GPIO40:1; // 8 Output Clear bit for this pin - Uint16 GPIO41:1; // 9 Output Clear bit for this pin - Uint16 GPIO42:1; // 10 Output Clear bit for this pin - Uint16 GPIO43:1; // 11 Output Clear bit for this pin - Uint16 GPIO44:1; // 12 Output Clear bit for this pin - Uint16 GPIO45:1; // 13 Output Clear bit for this pin - Uint16 GPIO46:1; // 14 Output Clear bit for this pin - Uint16 GPIO47:1; // 15 Output Clear bit for this pin - Uint16 GPIO48:1; // 16 Output Clear bit for this pin - Uint16 GPIO49:1; // 17 Output Clear bit for this pin - Uint16 GPIO50:1; // 18 Output Clear bit for this pin - Uint16 GPIO51:1; // 19 Output Clear bit for this pin - Uint16 GPIO52:1; // 20 Output Clear bit for this pin - Uint16 GPIO53:1; // 21 Output Clear bit for this pin - Uint16 GPIO54:1; // 22 Output Clear bit for this pin - Uint16 GPIO55:1; // 23 Output Clear bit for this pin - Uint16 GPIO56:1; // 24 Output Clear bit for this pin - Uint16 GPIO57:1; // 25 Output Clear bit for this pin - Uint16 GPIO58:1; // 26 Output Clear bit for this pin - Uint16 GPIO59:1; // 27 Output Clear bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBCLEAR_REG { - Uint32 all; - struct GPBCLEAR_BITS bit; -}; - -struct GPBTOGGLE_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Toggle bit for this pin - Uint16 GPIO33:1; // 1 Output Toggle bit for this pin - Uint16 GPIO34:1; // 2 Output Toggle bit for this pin - Uint16 GPIO35:1; // 3 Output Toggle bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Toggle bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Toggle bit for this pin - Uint16 GPIO40:1; // 8 Output Toggle bit for this pin - Uint16 GPIO41:1; // 9 Output Toggle bit for this pin - Uint16 GPIO42:1; // 10 Output Toggle bit for this pin - Uint16 GPIO43:1; // 11 Output Toggle bit for this pin - Uint16 GPIO44:1; // 12 Output Toggle bit for this pin - Uint16 GPIO45:1; // 13 Output Toggle bit for this pin - Uint16 GPIO46:1; // 14 Output Toggle bit for this pin - Uint16 GPIO47:1; // 15 Output Toggle bit for this pin - Uint16 GPIO48:1; // 16 Output Toggle bit for this pin - Uint16 GPIO49:1; // 17 Output Toggle bit for this pin - Uint16 GPIO50:1; // 18 Output Toggle bit for this pin - Uint16 GPIO51:1; // 19 Output Toggle bit for this pin - Uint16 GPIO52:1; // 20 Output Toggle bit for this pin - Uint16 GPIO53:1; // 21 Output Toggle bit for this pin - Uint16 GPIO54:1; // 22 Output Toggle bit for this pin - Uint16 GPIO55:1; // 23 Output Toggle bit for this pin - Uint16 GPIO56:1; // 24 Output Toggle bit for this pin - Uint16 GPIO57:1; // 25 Output Toggle bit for this pin - Uint16 GPIO58:1; // 26 Output Toggle bit for this pin - Uint16 GPIO59:1; // 27 Output Toggle bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBTOGGLE_REG { - Uint32 all; - struct GPBTOGGLE_BITS bit; -}; - -struct GPHDAT_BITS { // bits description - Uint16 GPIO224:1; // 0 Data Register for this pin - Uint16 GPIO225:1; // 1 Data Register for this pin - Uint16 GPIO226:1; // 2 Data Register for this pin - Uint16 GPIO227:1; // 3 Data Register for this pin - Uint16 GPIO228:1; // 4 Data Register for this pin - Uint16 GPIO229:1; // 5 Data Register for this pin - Uint16 GPIO230:1; // 6 Data Register for this pin - Uint16 GPIO231:1; // 7 Data Register for this pin - Uint16 GPIO232:1; // 8 Data Register for this pin - Uint16 GPIO233:1; // 9 Data Register for this pin - Uint16 GPIO234:1; // 10 Data Register for this pin - Uint16 GPIO235:1; // 11 Data Register for this pin - Uint16 GPIO236:1; // 12 Data Register for this pin - Uint16 GPIO237:1; // 13 Data Register for this pin - Uint16 GPIO238:1; // 14 Data Register for this pin - Uint16 GPIO239:1; // 15 Data Register for this pin - Uint16 GPIO240:1; // 16 Data Register for this pin - Uint16 GPIO241:1; // 17 Data Register for this pin - Uint16 GPIO242:1; // 18 Data Register for this pin - Uint16 GPIO243:1; // 19 Data Register for this pin - Uint16 GPIO244:1; // 20 Data Register for this pin - Uint16 GPIO245:1; // 21 Data Register for this pin - Uint16 GPIO246:1; // 22 Data Register for this pin - Uint16 GPIO247:1; // 23 Data Register for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHDAT_REG { - Uint32 all; - struct GPHDAT_BITS bit; -}; - -struct GPIO_DATA_REGS { - union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to GPIO31) - union GPASET_REG GPASET; // GPIO A Output Set (GPIO0 to GPIO31) - union GPACLEAR_REG GPACLEAR; // GPIO A Output Clear (GPIO0 to GPIO31) - union GPATOGGLE_REG GPATOGGLE; // GPIO A Output Toggle (GPIO0 to GPIO31) - union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to GPIO64) - union GPBSET_REG GPBSET; // GPIO B Output Set (GPIO32 to GPIO64) - union GPBCLEAR_REG GPBCLEAR; // GPIO B Output Clear (GPIO32 to GPIO64) - union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Output Toggle (GPIO32 to GPIO64) - Uint16 rsvd1[40]; // Reserved - union GPHDAT_REG GPHDAT; // GPIO H Data Register (GPIO0 to GPIO255) - Uint16 rsvd2[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// GPIO External References & Function Declarations: -// -extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; -extern volatile struct GPIO_DATA_REGS GpioDataRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h deleted file mode 100644 index ee13416..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h +++ /dev/null @@ -1,251 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_i2c.h -// -// TITLE: I2C Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_I2C_H__ -#define __F28004X_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// I2C Individual Register Bit Definitions: - -struct I2COAR_BITS { // bits description - Uint16 OAR:10; // 9:0 I2C Own address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2COAR_REG { - Uint16 all; - struct I2COAR_BITS bit; -}; - -struct I2CIER_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable - Uint16 NACK:1; // 1 No-acknowledgment interrupt enable - Uint16 ARDY:1; // 2 Register-access-ready interrupt enable - Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable - Uint16 SCD:1; // 5 Stop condition detected interrupt enable - Uint16 AAS:1; // 6 Addressed as slave interrupt enable - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union I2CIER_REG { - Uint16 all; - struct I2CIER_BITS bit; -}; - -struct I2CSTR_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit - Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. - Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit - Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. - Uint16 SCD:1; // 5 Stop condition detected bit. - Uint16 BYTESENT:1; // 6 Byte transmit over indication - Uint16 rsvd1:1; // 7 Reserved - Uint16 AD0:1; // 8 Address 0 bits - Uint16 AAS:1; // 9 Addressed-as-slave bit - Uint16 XSMT:1; // 10 Transmit shift register empty bit. - Uint16 RSFULL:1; // 11 Receive shift register full bit. - Uint16 BB:1; // 12 Bus busy bit. - Uint16 NACKSNT:1; // 13 NACK sent bit. - Uint16 SDIR:1; // 14 Slave direction bit - Uint16 rsvd2:1; // 15 Reserved -}; - -union I2CSTR_REG { - Uint16 all; - struct I2CSTR_BITS bit; -}; - -struct I2CDRR_BITS { // bits description - Uint16 DATA:8; // 7:0 Receive data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDRR_REG { - Uint16 all; - struct I2CDRR_BITS bit; -}; - -struct I2CSAR_BITS { // bits description - Uint16 SAR:10; // 9:0 Slave Address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2CSAR_REG { - Uint16 all; - struct I2CSAR_BITS bit; -}; - -struct I2CDXR_BITS { // bits description - Uint16 DATA:8; // 7:0 Transmit data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDXR_REG { - Uint16 all; - struct I2CDXR_BITS bit; -}; - -struct I2CMDR_BITS { // bits description - Uint16 BC:3; // 2:0 Bit count bits. - Uint16 FDF:1; // 3 Free Data Format - Uint16 STB:1; // 4 START Byte Mode - Uint16 IRS:1; // 5 I2C Module Reset - Uint16 DLB:1; // 6 Digital Loopback Mode - Uint16 RM:1; // 7 Repeat Mode - Uint16 XA:1; // 8 Expanded Address Mode - Uint16 TRX:1; // 9 Transmitter Mode - Uint16 MST:1; // 10 Master Mode - Uint16 STP:1; // 11 STOP Condition - Uint16 rsvd1:1; // 12 Reserved - Uint16 STT:1; // 13 START condition bit - Uint16 FREE:1; // 14 Debug Action - Uint16 NACKMOD:1; // 15 NACK mode bit -}; - -union I2CMDR_REG { - Uint16 all; - struct I2CMDR_BITS bit; -}; - -struct I2CISRC_BITS { // bits description - Uint16 INTCODE:3; // 2:0 Interrupt code bits. - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 WRITE_ZEROS:4; // 11:8 Always write all 0s to this field - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union I2CISRC_REG { - Uint16 all; - struct I2CISRC_BITS bit; -}; - -struct I2CEMDR_BITS { // bits description - Uint16 BC:1; // 0 Backwards compatibility mode - Uint16 FCM:1; // 1 Forward Compatibility for Tx behav in Type1 - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union I2CEMDR_REG { - Uint16 all; - struct I2CEMDR_BITS bit; -}; - -struct I2CPSC_BITS { // bits description - Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CPSC_REG { - Uint16 all; - struct I2CPSC_BITS bit; -}; - -struct I2CFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear - Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFFRST:1; // 13 Transmit FIFO Reset - Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable - Uint16 rsvd1:1; // 15 Reserved -}; - -union I2CFFTX_REG { - Uint16 all; - struct I2CFFTX_BITS bit; -}; - -struct I2CFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear - Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFFRST:1; // 13 Receive FIFO Reset - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union I2CFFRX_REG { - Uint16 all; - struct I2CFFRX_BITS bit; -}; - -struct I2C_REGS { - union I2COAR_REG I2COAR; // I2C Own address - union I2CIER_REG I2CIER; // I2C Interrupt Enable - union I2CSTR_REG I2CSTR; // I2C Status - Uint16 I2CCLKL; // I2C Clock low-time divider - Uint16 I2CCLKH; // I2C Clock high-time divider - Uint16 I2CCNT; // I2C Data count - union I2CDRR_REG I2CDRR; // I2C Data receive - union I2CSAR_REG I2CSAR; // I2C Slave address - union I2CDXR_REG I2CDXR; // I2C Data Transmit - union I2CMDR_REG I2CMDR; // I2C Mode - union I2CISRC_REG I2CISRC; // I2C Interrupt Source - union I2CEMDR_REG I2CEMDR; // I2C Extended Mode - union I2CPSC_REG I2CPSC; // I2C Prescaler - Uint16 rsvd1[19]; // Reserved - union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit - union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive -}; - -//--------------------------------------------------------------------------- -// I2C External References & Function Declarations: -// -extern volatile struct I2C_REGS I2caRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h deleted file mode 100644 index 856c66a..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h +++ /dev/null @@ -1,112 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_input_xbar.h -// -// TITLE: INPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_INPUT_XBAR_H__ -#define __F28004X_INPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// INPUT_XBAR Individual Register Bit Definitions: - -struct INPUTSELECTLOCK_BITS { // bits description - Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register - Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register - Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register - Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register - Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register - Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register - Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register - Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register - Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register - Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register - Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register - Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register - Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register - Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register - Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register - Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union INPUTSELECTLOCK_REG { - Uint32 all; - struct INPUTSELECTLOCK_BITS bit; -}; - -struct INPUT_XBAR_REGS { - Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) - Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) - Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) - Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) - Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) - Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) - Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) - Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) - Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) - Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) - Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) - Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) - Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) - Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) - Uint16 INPUT15SELECT; // INPUT15 Input Select Register (GPIO0 to x) - Uint16 INPUT16SELECT; // INPUT16 Input Select Register (GPIO0 to x) - Uint16 rsvd1[14]; // Reserved - union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register -}; - -//--------------------------------------------------------------------------- -// INPUT_XBAR External References & Function Declarations: -// -extern volatile struct INPUT_XBAR_REGS InputXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h deleted file mode 100644 index 88e1971..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h +++ /dev/null @@ -1,576 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_lin.h -// -// TITLE: LIN Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_LIN_H__ -#define __F28004X_LIN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// LIN Individual Register Bit Definitions: - -struct SCIGCR0_BITS { // bits description - bp_16 RESET:1; // 0 LIN Module reset bit - bp_16 rsvd1:15; // 15:1 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIGCR0_REG { - bp_32 all; - struct SCIGCR0_BITS bit; -}; - -struct SCIGCR1_BITS { // bits description - bp_16 COMMMODE:1; // 0 SCI/LIN communications mode bit - bp_16 TIMINGMODE:1; // 1 SCI timing mode bit. Should be set to 1 for SCI mode. - bp_16 PARITYENA:1; // 2 Parity enable - bp_16 PARITY:1; // 3 SCI parity odd/even selection - bp_16 STOP:1; // 4 SCI number of stop bits - bp_16 CLK_MASTER:1; // 5 LIN Master/Slave selection and SCI clock enable - bp_16 LINMODE:1; // 6 LIN Mode enable/disable - bp_16 SWnRST:1; // 7 Software reset - bp_16 SLEEP:1; // 8 SCI sleep (SCI compatibility mode) - bp_16 ADAPT:1; // 9 Automatic baudrate adjustment control(LIN mode) - bp_16 MBUFMODE:1; // 10 Multi-buffer mode - bp_16 CTYPE:1; // 11 Checksum type (LIN mode) - bp_16 HGENCTRL:1; // 12 Mask filtering comparison control (LIN mode) - bp_16 STOPEXTFRAME:1; // 13 Stop extended frame communication (LIN mode) - bp_16 rsvd1:2; // 15:14 Reserved - bp_32 LOOPBACK:1; // 16 Digital loopback mode - bp_32 CONT:1; // 17 Continue on suspend - bp_32 rsvd2:6; // 23:18 Reserved - bp_32 RXENA:1; // 24 SCI mode receiver enable - bp_32 TXENA:1; // 25 SCI mode transmitter enable - bp_32 rsvd3:6; // 31:26 Reserved -}; - -union SCIGCR1_REG { - bp_32 all; - struct SCIGCR1_BITS bit; -}; - -struct SCIGCR2_BITS { // bits description - bp_16 POWERDOWN:1; // 0 Low-power mode PowerDown bit - bp_16 rsvd1:7; // 7:1 Reserved - bp_16 GENWU:1; // 8 Generate Wakeup - bp_16 rsvd2:7; // 15:9 Reserved - bp_32 SC:1; // 16 Send Checksum (LIN mode) - bp_32 CC:1; // 17 Compare Checksum (LIN mode) - bp_32 rsvd3:14; // 31:18 Reserved -}; - -union SCIGCR2_REG { - bp_32 all; - struct SCIGCR2_BITS bit; -}; - -struct SCISETINT_BITS { // bits description - bp_16 SETBRKDTINT:1; // 0 Set Break-detect Interrupt (SCI compatible mode) - bp_16 SETWAKEUPINT:1; // 1 Set Wake-up Interrupt - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 SETTIMEOUTINT:1; // 4 Set Timeout Interrupt (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 SETTOAWUSINT:1; // 6 Set Timeout After Wakeup Signal Interrupt (LIN only) - bp_16 SETTOA3WUSINT:1; // 7 Set Timeout After 3 Wakeup Signals Interrupt (LIN only) - bp_16 SETTXINT:1; // 8 Set Transmitter Interrupt - bp_16 SETRXINT:1; // 9 Receiver Interrupt Enable - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 SETIDINT:1; // 13 Set Identifier Interrupt (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 SETPEINT:1; // 24 Set Parity Interrupt - bp_32 SETOEINT:1; // 25 Set Overrun-Error Interrupt - bp_32 SETFEINT:1; // 26 Set Framing-Error Interrupt - bp_32 SETNREINT:1; // 27 Set No-Response-Error Interrupt (LIN only) - bp_32 SETISFEINT:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt (LIN only) - bp_32 SETCEINT:1; // 29 Set Checksum-error Interrupt (LIN only) - bp_32 SETPBEINT:1; // 30 Set Physical Bus Error Interrupt (LIN only) - bp_32 SETBEINT:1; // 31 Set Bit Error Interrupt (LIN only) -}; - -union SCISETINT_REG { - bp_32 all; - struct SCISETINT_BITS bit; -}; - -struct SCICLEARINT_BITS { // bits description - bp_16 CLRBRKDTINT:1; // 0 Clear Break-detect Interrupt (SCI compatible mode - bp_16 CLRWAKEUPINT:1; // 1 Clear Wake-up Interrupt - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 CLRTIMEOUTINT:1; // 4 Clear Timeout Interrupt (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 CLRTOAWUSINT:1; // 6 Clear Timeout After Wakeup Signal Interrupt (LIN only) - bp_16 CLRTOA3WUSINT:1; // 7 Clear Timeout After 3 Wakeup Signals Interrupt (LIN only) - bp_16 CLRTXINT:1; // 8 Clear Transmitter Interrupt - bp_16 CLRRXINT:1; // 9 Clear Receiver Interrupt - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 CLRIDINT:1; // 13 Clear Identifier Interrupt (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 CLRPEINT:1; // 24 Clear Parity Interrupt - bp_32 CLROEINT:1; // 25 Clear Overrun-Error Interrupt - bp_32 CLRFEINT:1; // 26 Clear Framing-Error Interrupt - bp_32 CLRNREINT:1; // 27 Clear No-Response-Error Interrupt (LIN only) - bp_32 CLRISFEINT:1; // 28 Clear Inconsistent-Synch-Field-Error Interrupt (LIN only) - bp_32 CLRCEINT:1; // 29 Clear Checksum-error Interrupt (LIN only) - bp_32 CLRPBEINT:1; // 30 Clear Physical Bus Error Interrupt (LIN only) - bp_32 CLRBEINT:1; // 31 Clear Bit Error Interrupt (LIN only) -}; - -union SCICLEARINT_REG { - bp_32 all; - struct SCICLEARINT_BITS bit; -}; - -struct SCISETINTLVL_BITS { // bits description - bp_16 SETBRKDTINTLVL:1; // 0 Set Break-detect Interrupt Level (SCI compatible mode) - bp_16 SETWAKEUPINTLVL:1; // 1 Set Wake-up Interrupt Level - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 SETTIMEOUTINTLVL:1; // 4 Set Timeout Interrupt Level (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 SETTOAWUSINTLVL:1; // 6 Set Timeout After Wakeup Signal Interrupt Level (LIN only) - bp_16 SETTOA3WUSINTLVL:1; // 7 Set Timeout After 3 Wakeup Signals - bp_16 SETTXINTLVL:1; // 8 Set Transmitter Interrupt Level - bp_16 SETRXINTOVO:1; // 9 Receiver Interrupt Enable Level - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 SETIDINTLVL:1; // 13 Set Identifier Interrupt Level (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 SETPEINTLVL:1; // 24 Set Parity Interrupt Level - bp_32 SETOEINTLVL:1; // 25 Set Overrun-Error Interrupt Level - bp_32 SETFEINTLVL:1; // 26 Set Framing-Error Interrupt Level - bp_32 SETNREINTLVL:1; // 27 Set No-Response-Error Interrupt Level (LIN only) - bp_32 SETISFEINTLVL:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt Level - bp_32 SETCEINTLVL:1; // 29 Set Checksum-error Interrupt Level (LIN only) - bp_32 SETPBEINTLVL:1; // 30 Set Physical Bus Error Interrupt Level (LIN only) - bp_32 SETBEINTLVL:1; // 31 Set Bit Error Interrupt Level(LIN only) -}; - -union SCISETINTLVL_REG { - bp_32 all; - struct SCISETINTLVL_BITS bit; -}; - -struct SCICLEARINTLVL_BITS { // bits description - bp_16 CLRBRKDTINTLVL:1; // 0 Clear Break-detect Interrupt Level (SCI compatible mode) - bp_16 CLRWAKEUPINTLVL:1; // 1 Clear Wake-up Interrupt Level - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 CLRTIMEOUTINTLVL:1; // 4 Clear Timeout Interrupt Level (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 CLRTOAWUSINTLVL:1; // 6 Clear Timeout After Wakeup Signal Interrupt Level (LIN only) - bp_16 CLRTOA3WUSINTLVL:1; // 7 Clear Timeout After 3 Wakeup Signals - bp_16 CLRTXINTLVL:1; // 8 Clear Transmitter Interrupt Level - bp_16 CLRRXINTLVL:1; // 9 Clear Receiver interrupt Level. - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 CLRIDINTLVL:1; // 13 Clear Identifier Interrupt Level (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 CLRPEINTLVL:1; // 24 Clear Parity Interrupt Level - bp_32 CLROEINTLVL:1; // 25 Clear Overrun-Error Interrupt Level - bp_32 CLRFEINTLVL:1; // 26 Clear Framing-Error Interrupt Level - bp_32 CLRNREINTLVL:1; // 27 Clear No-Response-Error Interrupt Level (LIN only) - bp_32 CLRISFEINTLVL:1; // 28 Clear Inconsistent-Synch-Field-Error - bp_32 CLRCEINTLVL:1; // 29 Clear Checksum-error Interrupt Level (LIN only) - bp_32 CLRPBEINTLVL:1; // 30 Clear Physical Bus Error Interrupt Level (LIN only) - bp_32 CLRBEINTLVL:1; // 31 Clear Bit Error Interrupt Level (LIN only) -}; - -union SCICLEARINTLVL_REG { - bp_32 all; - struct SCICLEARINTLVL_BITS bit; -}; - -struct SCIFLR_BITS { // bits description - bp_16 BRKDT:1; // 0 Break-detect Flag (SCI compatible mode) - bp_16 WAKEUP:1; // 1 Wake-up Flag - bp_16 IDLE:1; // 2 SCI receiver in idle state (SCI compatible mode) - bp_16 BUSY:1; // 3 Busy Flag - bp_16 TIMEOUT:1; // 4 LIN Bus IDLE timeout Flag (LIN only) - bp_16 rsvd1:1; // 5 Reserved - bp_16 TOAWUS:1; // 6 Timeout After Wakeup Signal Flag (LIN only) - bp_16 TOA3WUS:1; // 7 Timeout After 3 Wakeup Signals Flag (LIN only) - bp_16 TXRDY:1; // 8 Transmitter Buffer Ready Flag - bp_16 RXRDY:1; // 9 Receiver Buffer Ready Flag - bp_16 TXWAKE:1; // 10 SCI Transmitter Wakeup Method Select - bp_16 TXEMPTY:1; // 11 Transmitter Empty Clag - bp_16 RXWAKE:1; // 12 Receiver Wakeup Detect Flag - bp_16 IDTXFLAG:1; // 13 Identifier On Transmit Flag (LIN only) - bp_16 IDRXFLAG:1; // 14 Identifier on Receive Flag - bp_16 rsvd2:1; // 15 Reserved - bp_32 rsvd3:8; // 23:16 Reserved - bp_32 PE:1; // 24 Parity Error Flag - bp_32 OE:1; // 25 Overrun Error Flag - bp_32 FE:1; // 26 Framing Error Flag - bp_32 NRE:1; // 27 No-Response Error Flag (LIN only) - bp_32 ISFE:1; // 28 Inconsistent Synch Field Error Flag (LIN only) - bp_32 CE:1; // 29 Checksum Error Flag (LIN only) - bp_32 PBE:1; // 30 Physical Bus Error Flag (LIN only) - bp_32 BE:1; // 31 Bit Error Flag (LIN only) -}; - -union SCIFLR_REG { - bp_32 all; - struct SCIFLR_BITS bit; -}; - -struct SCIINTVECT0_BITS { // bits description - bp_16 INTVECT0:5; // 4:0 LIN Module reset bit - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIINTVECT0_REG { - bp_32 all; - struct SCIINTVECT0_BITS bit; -}; - -struct SCIINTVECT1_BITS { // bits description - bp_16 INTVECT1:5; // 4:0 LIN Module reset bit - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIINTVECT1_REG { - bp_32 all; - struct SCIINTVECT1_BITS bit; -}; - -struct SCIFORMAT_BITS { // bits description - bp_16 CHAR:5; // 4:0 Character Length Control Bits - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 LENGTH:3; // 18:16 Frame Length Control Bits - bp_32 rsvd2:13; // 31:19 Reserved -}; - -union SCIFORMAT_REG { - bp_32 all; - struct SCIFORMAT_BITS bit; -}; - -struct BRSR_BITS { // bits description - bp_16 SCI_LIN_PSL:16; // 15:0 Character Length Control Bits - bp_32 SCI_LIN_PSH:8; // 23:16 24-Bit Integer Prescaler Select - bp_32 M:4; // 27:24 Frame Length Control Bits - bp_32 rsvd1:4; // 31:28 Reserved -}; - -union BRSR_REG { - bp_32 all; - struct BRSR_BITS bit; -}; - -struct SCIED_BITS { // bits description - bp_16 ED:8; // 7:0 Receiver Emulation Data. - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIED_REG { - bp_32 all; - struct SCIED_BITS bit; -}; - -struct SCIRD_BITS { // bits description - bp_16 RD:8; // 7:0 Received Data. - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIRD_REG { - bp_32 all; - struct SCIRD_BITS bit; -}; - -struct SCITD_BITS { // bits description - bp_16 TD:8; // 7:0 Transmit data - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCITD_REG { - bp_32 all; - struct SCITD_BITS bit; -}; - -struct SCIPIO0_BITS { // bits description - bp_16 rsvd1:1; // 0 Reserved - bp_16 RXFUNC:1; // 1 LINRX pin function - bp_16 TXFUNC:1; // 2 LINTX pin function - bp_16 rsvd2:13; // 15:3 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union SCIPIO0_REG { - bp_32 all; - struct SCIPIO0_BITS bit; -}; - -struct SCIPIO2_BITS { // bits description - bp_16 rsvd1:1; // 0 Reserved - bp_16 RXIN:1; // 1 SCIRX pin value - bp_16 TXIN:1; // 2 SCITX pin value - bp_16 rsvd2:13; // 15:3 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union SCIPIO2_REG { - bp_32 all; - struct SCIPIO2_BITS bit; -}; - -struct LINCOMP_BITS { // bits description - bp_16 SBREAK:3; // 2:0 Synch Break Extend - bp_16 rsvd1:5; // 7:3 Reserved - bp_16 SDEL:2; // 9:8 Sync Delimiter Compare - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union LINCOMP_REG { - bp_32 all; - struct LINCOMP_BITS bit; -}; - -struct LINRD0_BITS { // bits description - bp_16 RD3:8; // 7:0 Receive Buffer 3 - bp_16 RD2:8; // 15:8 Receive Buffer 2 - bp_32 RD1:8; // 23:16 Receive Buffer 1 - bp_32 RD0:8; // 31:24 Receive Buffer 0 -}; - -union LINRD0_REG { - bp_32 all; - struct LINRD0_BITS bit; -}; - -struct LINRD1_BITS { // bits description - bp_16 RD7:8; // 7:0 Receive Buffer 3 - bp_16 RD6:8; // 15:8 Receive Buffer 2 - bp_32 RD5:8; // 23:16 Receive Buffer 1 - bp_32 RD4:8; // 31:24 Receive Buffer 0 -}; - -union LINRD1_REG { - bp_32 all; - struct LINRD1_BITS bit; -}; - -struct LINMASK_BITS { // bits description - bp_16 TXIDMASK:8; // 7:0 TX ID Mask bits (LIN only) - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 RXIDMASK:8; // 23:16 RX ID Mask bits (LIN only) - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union LINMASK_REG { - bp_32 all; - struct LINMASK_BITS bit; -}; - -struct LINID_BITS { // bits description - bp_16 IDBYTE:8; // 7:0 LIN message ID (LIN only) - bp_16 IDSLAVETASKBYTE:8; // 15:8 Received ID comparison ID (LIN only) - bp_32 RECEIVEDID:8; // 23:16 Current Message ID (LIN only) - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union LINID_REG { - bp_32 all; - struct LINID_BITS bit; -}; - -struct LINTD0_BITS { // bits description - bp_16 TD3:8; // 7:0 TRANSMIT Buffer 3 - bp_16 TD2:8; // 15:8 TRANSMIT Buffer 2 - bp_32 TD1:8; // 23:16 TRANSMIT Buffer 1 - bp_32 TD0:8; // 31:24 TRANSMIT Buffer 0 -}; - -union LINTD0_REG { - bp_32 all; - struct LINTD0_BITS bit; -}; - -struct LINTD1_BITS { // bits description - bp_16 TD7:8; // 7:0 TRANSMIT Buffer 7 - bp_16 TD6:8; // 15:8 TRANSMIT Buffer 6 - bp_32 TD5:8; // 23:16 TRANSMIT Buffer 5 - bp_32 TD4:8; // 31:24 TRANSMIT Buffer 4 -}; - -union LINTD1_REG { - bp_32 all; - struct LINTD1_BITS bit; -}; - -struct MBRSR_BITS { // bits description - bp_16 MBR:13; // 12:0 Received Data. - bp_16 rsvd1:3; // 15:13 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union MBRSR_REG { - bp_32 all; - struct MBRSR_BITS bit; -}; - -struct IODFTCTRL_BITS { // bits description - bp_16 RXPENA:1; // 0 Analog Loopback Via Receive Pin Enable - bp_16 LPBENA:1; // 1 Module Loopback Enable - bp_16 rsvd1:6; // 7:2 Reserved - bp_16 IODFTENA:4; // 11:8 IO DFT Enable Key - bp_16 rsvd2:4; // 15:12 Reserved - bp_32 TXSHIFT:3; // 18:16 Transmit Delay Shift - bp_32 PINSAMPLEMASK:2; // 20:19 TX Pin Sample Mask - bp_32 rsvd3:3; // 23:21 Reserved - bp_32 BRKDTERRENA:1; // 24 Break Detect Error Enable (SCI compatibility mode) - bp_32 PERRENA:1; // 25 Parity Error Enable (SCI compatibility mode) - bp_32 FERRENA:1; // 26 Frame Error Enable (SCI compatibility mode) - bp_32 rsvd4:1; // 27 Reserved - bp_32 ISFERRENA:1; // 28 Inconsistent Synch Field Error Enable (LIN mode) - bp_32 CERRENA:1; // 29 Checksum Error Enable(LIN mode) - bp_32 PBERRENA:1; // 30 Physical Bus Error Enable (LIN mode) - bp_32 BERRENA:1; // 31 Bit Error Enable (LIN mode) -}; - -union IODFTCTRL_REG { - bp_32 all; - struct IODFTCTRL_BITS bit; -}; - -struct LIN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for LIN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_EN_REG { - bp_32 all; - struct LIN_GLB_INT_EN_BITS bit; -}; - -struct LIN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for LIN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_FLG_REG { - bp_32 all; - struct LIN_GLB_INT_FLG_BITS bit; -}; - -struct LIN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for LIN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_CLR_REG { - bp_32 all; - struct LIN_GLB_INT_CLR_BITS bit; -}; - -struct LIN_REGS { - union SCIGCR0_REG SCIGCR0; // Global Control Register 0 - union SCIGCR1_REG SCIGCR1; // Global Control Register 1 - union SCIGCR2_REG SCIGCR2; // Global Control Register 2 - union SCISETINT_REG SCISETINT; // Interrupt Enable Register - union SCICLEARINT_REG SCICLEARINT; // Interrupt Disable Register - union SCISETINTLVL_REG SCISETINTLVL; // Set Interrupt Level Register - union SCICLEARINTLVL_REG SCICLEARINTLVL; // Clear Interrupt Level Register - union SCIFLR_REG SCIFLR; // Flag Register - union SCIINTVECT0_REG SCIINTVECT0; // Interrupt Vector Offset Register 0 - union SCIINTVECT1_REG SCIINTVECT1; // Interrupt Vector Offset Register 1 - union SCIFORMAT_REG SCIFORMAT; // Length Control Register - union BRSR_REG BRSR; // Baud Rate Selection Register - union SCIED_REG SCIED; // Emulation buffer Register - union SCIRD_REG SCIRD; // Receiver data buffer Register - union SCITD_REG SCITD; // Transmit data buffer Register - union SCIPIO0_REG SCIPIO0; // Pin control Register 0 - uint32_t rsvd1[2]; // Reserved - union SCIPIO2_REG SCIPIO2; // Pin control Register 2 - uint32_t rsvd2[12]; // Reserved - union LINCOMP_REG LINCOMP; // Compare register - union LINRD0_REG LINRD0; // Receive data register 0 - union LINRD1_REG LINRD1; // Receive data register 1 - union LINMASK_REG LINMASK; // Acceptance mask register - union LINID_REG LINID; // LIN ID Register - union LINTD0_REG LINTD0; // Transmit Data Register 0 - union LINTD1_REG LINTD1; // Transmit Data Register 1 - union MBRSR_REG MBRSR; // Baud Rate Selection Register - uint32_t rsvd3[8]; // Reserved - union IODFTCTRL_REG IODFTCTRL; // IODFT for LIN - uint32_t rsvd4[38]; // Reserved - union LIN_GLB_INT_EN_REG LIN_GLB_INT_EN; // LIN Global Interrupt Enable Register - union LIN_GLB_INT_FLG_REG LIN_GLB_INT_FLG; // LIN Global Interrupt Flag Register - union LIN_GLB_INT_CLR_REG LIN_GLB_INT_CLR; // LIN Global Interrupt Clear Register -}; - -//--------------------------------------------------------------------------- -// LIN External References & Function Declarations: -// -extern volatile struct LIN_REGS LinaRegs; -extern volatile struct LIN_REGS LinbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h deleted file mode 100644 index 7debf52..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h +++ /dev/null @@ -1,867 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_memconfig.h -// -// TITLE: MEMCONFIG Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_MEMCONFIG_H__ -#define __F28004X_MEMCONFIG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// MEMCONFIG Individual Register Bit Definitions: - -struct DxLOCK_BITS { // bits description - Uint16 LOCK_M0:1; // 0 M0 RAM Lock bits - Uint16 LOCK_M1:1; // 1 M1 RAM Lock bits - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxLOCK_REG { - Uint32 all; - struct DxLOCK_BITS bit; -}; - -struct DxCOMMIT_BITS { // bits description - Uint16 COMMIT_M0:1; // 0 M0 RAM Permanent Lock bits - Uint16 COMMIT_M1:1; // 1 M1 RAM Permanent Lock bits - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxCOMMIT_REG { - Uint32 all; - struct DxCOMMIT_BITS bit; -}; - -struct DxTEST_BITS { // bits description - Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM - Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxTEST_REG { - Uint32 all; - struct DxTEST_BITS bit; -}; - -struct DxINIT_BITS { // bits description - Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. - Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxINIT_REG { - Uint32 all; - struct DxINIT_BITS bit; -}; - -struct DxINITDONE_BITS { // bits description - Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. - Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxINITDONE_REG { - Uint32 all; - struct DxINITDONE_BITS bit; -}; - -struct LSxLOCK_BITS { // bits description - Uint16 LOCK_LS0:1; // 0 LS0 RAM Lock bits - Uint16 LOCK_LS1:1; // 1 LS1 RAM Lock bits - Uint16 LOCK_LS2:1; // 2 LS2 RAM Lock bits - Uint16 LOCK_LS3:1; // 3 LS3 RAM Lock bits - Uint16 LOCK_LS4:1; // 4 LS4 RAM Lock bits - Uint16 LOCK_LS5:1; // 5 LS5 RAM Lock bits - Uint16 LOCK_LS6:1; // 6 LS6 RAM Lock bits - Uint16 LOCK_LS7:1; // 7 LS7 RAM Lock bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxLOCK_REG { - Uint32 all; - struct LSxLOCK_BITS bit; -}; - -struct LSxCOMMIT_BITS { // bits description - Uint16 COMMIT_LS0:1; // 0 LS0 RAM Permanent Lock bits - Uint16 COMMIT_LS1:1; // 1 LS1 RAM Permanent Lock bits - Uint16 COMMIT_LS2:1; // 2 LS2 RAM Permanent Lock bits - Uint16 COMMIT_LS3:1; // 3 LS3 RAM Permanent Lock bits - Uint16 COMMIT_LS4:1; // 4 LS4 RAM Permanent Lock bits - Uint16 COMMIT_LS5:1; // 5 LS5 RAM Permanent Lock bits - Uint16 COMMIT_LS6:1; // 6 LS6 RAM Permanent Lock bits - Uint16 COMMIT_LS7:1; // 7 LS7 RAM Permanent Lock bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCOMMIT_REG { - Uint32 all; - struct LSxCOMMIT_BITS bit; -}; - -struct LSxMSEL_BITS { // bits description - Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM - Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM - Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM - Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM - Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM - Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM - Uint16 MSEL_LS6:2; // 13:12 Master Select for LS6 RAM - Uint16 MSEL_LS7:2; // 15:14 Master Select for LS7 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union LSxMSEL_REG { - Uint32 all; - struct LSxMSEL_BITS bit; -}; - -struct LSxCLAPGM_BITS { // bits description - Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS6:1; // 6 Selects LS6 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS7:1; // 7 Selects LS7 RAM as program vs data memory for CLA - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCLAPGM_REG { - Uint32 all; - struct LSxCLAPGM_BITS bit; -}; - -struct LSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM - Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM - Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM - Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM - Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT0_REG { - Uint32 all; - struct LSxACCPROT0_BITS bit; -}; - -struct LSxACCPROT1_BITS { // bits description - Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM - Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM - Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS6:1; // 16 Fetch Protection For LS6 RAM - Uint16 CPUWRPROT_LS6:1; // 17 CPU WR Protection For LS6 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS7:1; // 24 Fetch Protection For LS7 RAM - Uint16 CPUWRPROT_LS7:1; // 25 CPU WR Protection For LS7 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT1_REG { - Uint32 all; - struct LSxACCPROT1_BITS bit; -}; - -struct LSxTEST_BITS { // bits description - Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM - Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM - Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM - Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM - Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM - Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM - Uint16 TEST_LS6:2; // 13:12 Selects the different modes for LS6 RAM - Uint16 TEST_LS7:2; // 15:14 Selects the different modes for LS7 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union LSxTEST_REG { - Uint32 all; - struct LSxTEST_BITS bit; -}; - -struct LSxINIT_BITS { // bits description - Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. - Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. - Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. - Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. - Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. - Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. - Uint16 INIT_LS6:1; // 6 RAM Initialization control for LS6 RAM. - Uint16 INIT_LS7:1; // 7 RAM Initialization control for LS7 RAM. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINIT_REG { - Uint32 all; - struct LSxINIT_BITS bit; -}; - -struct LSxINITDONE_BITS { // bits description - Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. - Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. - Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. - Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. - Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. - Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. - Uint16 INITDONE_LS6:1; // 6 RAM Initialization status for LS6 RAM. - Uint16 INITDONE_LS7:1; // 7 RAM Initialization status for LS7 RAM. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINITDONE_REG { - Uint32 all; - struct LSxINITDONE_BITS bit; -}; - -struct GSxLOCK_BITS { // bits description - Uint16 LOCK_GS0:1; // 0 GS0 RAM Lock bits - Uint16 LOCK_GS1:1; // 1 GS1 RAM Lock bits - Uint16 LOCK_GS2:1; // 2 GS2 RAM Lock bits - Uint16 LOCK_GS3:1; // 3 GS3 RAM Lock bits - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxLOCK_REG { - Uint32 all; - struct GSxLOCK_BITS bit; -}; - -struct GSxCOMMIT_BITS { // bits description - Uint16 COMMIT_GS0:1; // 0 GS0 RAM Permanent Lock bits - Uint16 COMMIT_GS1:1; // 1 GS1 RAM Permanent Lock bits - Uint16 COMMIT_GS2:1; // 2 GS2 RAM Permanent Lock bits - Uint16 COMMIT_GS3:1; // 3 GS3 RAM Permanent Lock bits - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxCOMMIT_REG { - Uint32 all; - struct GSxCOMMIT_BITS bit; -}; - -struct GSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM - Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM - Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM - Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM - Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM - Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM - Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM - Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM - Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT0_REG { - Uint32 all; - struct GSxACCPROT0_BITS bit; -}; - -struct GSxTEST_BITS { // bits description - Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM - Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM - Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM - Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 rsvd2:2; // 11:10 Reserved - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 rsvd4:2; // 15:14 Reserved - Uint16 rsvd5:2; // 17:16 Reserved - Uint16 rsvd6:2; // 19:18 Reserved - Uint16 rsvd7:2; // 21:20 Reserved - Uint16 rsvd8:2; // 23:22 Reserved - Uint16 rsvd9:2; // 25:24 Reserved - Uint16 rsvd10:2; // 27:26 Reserved - Uint16 rsvd11:2; // 29:28 Reserved - Uint16 rsvd12:2; // 31:30 Reserved -}; - -union GSxTEST_REG { - Uint32 all; - struct GSxTEST_BITS bit; -}; - -struct GSxINIT_BITS { // bits description - Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. - Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. - Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. - Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxINIT_REG { - Uint32 all; - struct GSxINIT_BITS bit; -}; - -struct GSxINITDONE_BITS { // bits description - Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. - Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. - Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. - Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxINITDONE_REG { - Uint32 all; - struct GSxINITDONE_BITS bit; -}; - -struct MSGxLOCK_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 LOCK_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM Lock bits - Uint16 LOCK_CLA1TOCPU:1; // 2 CLA1TOCPU RAM Lock bits - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxLOCK_REG { - Uint32 all; - struct MSGxLOCK_BITS bit; -}; - -struct MSGxCOMMIT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 COMMIT_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM control fields COMMIT bit - Uint16 COMMIT_CLA1TOCPU:1; // 2 CLA1TOCPU RAM control fields COMMIT bit - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxCOMMIT_REG { - Uint32 all; - struct MSGxCOMMIT_BITS bit; -}; - -struct MSGxTEST_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select - Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxTEST_REG { - Uint32 all; - struct MSGxTEST_BITS bit; -}; - -struct MSGxINIT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM - Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxINIT_REG { - Uint32 all; - struct MSGxINIT_BITS bit; -}; - -struct MSGxINITDONE_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM - Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxINITDONE_REG { - Uint32 all; - struct MSGxINITDONE_BITS bit; -}; - -struct MEM_CFG_REGS { - union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register - union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register - Uint16 rsvd1[12]; // Reserved - union DxTEST_REG DxTEST; // Dedicated RAM TEST Register - union DxINIT_REG DxINIT; // Dedicated RAM Init Register - union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register - Uint16 rsvd2[10]; // Reserved - union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register - union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register - union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register - union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register - union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 - union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 - Uint16 rsvd3[4]; // Reserved - union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register - union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register - union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register - Uint16 rsvd4[10]; // Reserved - union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register - union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register - Uint16 rsvd5[4]; // Reserved - union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 - Uint16 rsvd6[6]; // Reserved - union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register - union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register - union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register - Uint16 rsvd7[10]; // Reserved - union MSGxLOCK_REG MSGxLOCK; // Message RAM Config Lock Register - union MSGxCOMMIT_REG MSGxCOMMIT; // Message RAM Config Lock Commit Register - Uint16 rsvd8[12]; // Reserved - union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register - union MSGxINIT_REG MSGxINIT; // Message RAM Init Register - union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register - Uint16 rsvd9[10]; // Reserved -}; - -struct NMAVFLG_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVFLG_REG { - Uint32 all; - struct NMAVFLG_BITS bit; -}; - -struct NMAVSET_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVSET_REG { - Uint32 all; - struct NMAVSET_BITS bit; -}; - -struct NMAVCLR_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVCLR_REG { - Uint32 all; - struct NMAVCLR_BITS bit; -}; - -struct NMAVINTEN_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:6; // 15:10 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union NMAVINTEN_REG { - Uint32 all; - struct NMAVINTEN_BITS bit; -}; - -struct MAVFLG_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVFLG_REG { - Uint32 all; - struct MAVFLG_BITS bit; -}; - -struct MAVSET_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVSET_REG { - Uint32 all; - struct MAVSET_BITS bit; -}; - -struct MAVCLR_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVCLR_REG { - Uint32 all; - struct MAVCLR_BITS bit; -}; - -struct MAVINTEN_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVINTEN_REG { - Uint32 all; - struct MAVINTEN_BITS bit; -}; - -struct ACCESS_PROTECTION_REGS { - union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register - union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register - union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register - union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register - Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address - Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address - Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address - Uint16 rsvd1[2]; // Reserved - Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address - Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address - Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address - Uint16 rsvd2[10]; // Reserved - union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register - union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register - union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register - union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register - Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address - Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address - Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address - Uint16 rsvd3[18]; // Reserved -}; - -struct UCERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRFLG_REG { - Uint32 all; - struct UCERRFLG_BITS bit; -}; - -struct UCERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRSET_REG { - Uint32 all; - struct UCERRSET_BITS bit; -}; - -struct UCERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRCLR_REG { - Uint32 all; - struct UCERRCLR_BITS bit; -}; - -struct CERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRFLG_REG { - Uint32 all; - struct CERRFLG_BITS bit; -}; - -struct CERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRSET_REG { - Uint32 all; - struct CERRSET_BITS bit; -}; - -struct CERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRCLR_REG { - Uint32 all; - struct CERRCLR_BITS bit; -}; - -struct CEINTFLG_BITS { // bits description - Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTFLG_REG { - Uint32 all; - struct CEINTFLG_BITS bit; -}; - -struct CEINTCLR_BITS { // bits description - Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTCLR_REG { - Uint32 all; - struct CEINTCLR_BITS bit; -}; - -struct CEINTSET_BITS { // bits description - Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTSET_REG { - Uint32 all; - struct CEINTSET_BITS bit; -}; - -struct CEINTEN_BITS { // bits description - Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTEN_REG { - Uint32 all; - struct CEINTEN_BITS bit; -}; - -struct MEMORY_ERROR_REGS { - union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register - union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register - union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register - Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address - Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address - Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address - Uint16 rsvd1[20]; // Reserved - union CERRFLG_REG CERRFLG; // Correctable Error Flag Register - union CERRSET_REG CERRSET; // Correctable Error Flag Set Register - union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register - Uint32 CCPUREADDR; // Correctable CPU Read Error Address - Uint16 rsvd2[6]; // Reserved - Uint32 CERRCNT; // Correctable Error Count Register - Uint32 CERRTHRES; // Correctable Error Threshold Value Register - union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register - union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register - union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register - union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register - Uint16 rsvd3[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// MEMCONFIG External References & Function Declarations: -// -extern volatile struct MEM_CFG_REGS MemCfgRegs; -extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; -extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h deleted file mode 100644 index 73c40c6..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h +++ /dev/null @@ -1,178 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_nmiintrupt.h -// -// TITLE: NMIINTRUPT Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_NMIINTRUPT_H__ -#define __F28004X_NMIINTRUPT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// NMIINTRUPT Individual Register Bit Definitions: - -struct NMICFG_BITS { // bits description - Uint16 NMIE:1; // 0 Global NMI Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union NMICFG_REG { - Uint16 all; - struct NMICFG_BITS bit; -}; - -struct NMIFLG_BITS { // bits description - Uint16 NMIINT:1; // 0 NMI Interrupt Flag - Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag - Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag - Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 rsvd7:1; // 11 Reserved - Uint16 rsvd8:1; // 12 Reserved - Uint16 SWERR:1; // 13 SW Error Force NMI Flag - Uint16 rsvd9:2; // 15:14 Reserved -}; - -union NMIFLG_REG { - Uint16 all; - struct NMIFLG_BITS bit; -}; - -struct NMIFLGCLR_BITS { // bits description - Uint16 NMIINT:1; // 0 NMIINT Flag Clear - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 rsvd7:1; // 11 Reserved - Uint16 rsvd8:1; // 12 Reserved - Uint16 SWERR:1; // 13 SWERR Flag Clear - Uint16 rsvd9:2; // 15:14 Reserved -}; - -union NMIFLGCLR_REG { - Uint16 all; - struct NMIFLGCLR_BITS bit; -}; - -struct NMIFLGFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 SWERR:1; // 13 SWERR Flag Force - Uint16 rsvd10:2; // 15:14 Reserved -}; - -union NMIFLGFRC_REG { - Uint16 all; - struct NMIFLGFRC_BITS bit; -}; - -struct NMISHDFLG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag - Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag - Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 SWERR:1; // 13 SW Error Force NMI Flag - Uint16 rsvd10:2; // 15:14 Reserved -}; - -union NMISHDFLG_REG { - Uint16 all; - struct NMISHDFLG_BITS bit; -}; - -struct NMI_INTRUPT_REGS { - union NMICFG_REG NMICFG; // NMI Configuration Register - union NMIFLG_REG NMIFLG; // NMI Flag Register (SYSRsn Clear) - union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register - union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register - Uint16 NMIWDCNT; // NMI Watchdog Counter Register - Uint16 NMIWDPRD; // NMI Watchdog Period Register - union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register -}; - -//--------------------------------------------------------------------------- -// NMIINTRUPT External References & Function Declarations: -// -extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h deleted file mode 100644 index 461cfdf..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h +++ /dev/null @@ -1,905 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_output_xbar.h -// -// TITLE: OUTPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_OUTPUT_XBAR_H__ -#define __F28004X_OUTPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR Individual Register Bit Definitions: - -struct OUTPUT1MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT1MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT1MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT1MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT2MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT2MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT2MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT2MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT3MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT3MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT3MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT3MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT4MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT4MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT5MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT5MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT6MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT6MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT6MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT6MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT7MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT7MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT8MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT8MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT1MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUXENABLE_REG { - Uint32 all; - struct OUTPUT1MUXENABLE_BITS bit; -}; - -struct OUTPUT2MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUXENABLE_REG { - Uint32 all; - struct OUTPUT2MUXENABLE_BITS bit; -}; - -struct OUTPUT3MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUXENABLE_REG { - Uint32 all; - struct OUTPUT3MUXENABLE_BITS bit; -}; - -struct OUTPUT4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUXENABLE_REG { - Uint32 all; - struct OUTPUT4MUXENABLE_BITS bit; -}; - -struct OUTPUT5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUXENABLE_REG { - Uint32 all; - struct OUTPUT5MUXENABLE_BITS bit; -}; - -struct OUTPUT6MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUXENABLE_REG { - Uint32 all; - struct OUTPUT6MUXENABLE_BITS bit; -}; - -struct OUTPUT7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUXENABLE_REG { - Uint32 all; - struct OUTPUT7MUXENABLE_BITS bit; -}; - -struct OUTPUT8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUXENABLE_REG { - Uint32 all; - struct OUTPUT8MUXENABLE_BITS bit; -}; - -struct OUTPUTLATCH_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCH_REG { - Uint32 all; - struct OUTPUTLATCH_BITS bit; -}; - -struct OUTPUTLATCHCLR_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHCLR_REG { - Uint32 all; - struct OUTPUTLATCHCLR_BITS bit; -}; - -struct OUTPUTLATCHFRC_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHFRC_REG { - Uint32 all; - struct OUTPUTLATCHFRC_BITS bit; -}; - -struct OUTPUTLATCHENABLE_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHENABLE_REG { - Uint32 all; - struct OUTPUTLATCHENABLE_BITS bit; -}; - -struct OUTPUTINV_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTINV_REG { - Uint32 all; - struct OUTPUTINV_BITS bit; -}; - -struct OUTPUTLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write Protection KEY -}; - -union OUTPUTLOCK_REG { - Uint32 all; - struct OUTPUTLOCK_BITS bit; -}; - -struct OUTPUT_XBAR_REGS { - union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 - union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 - union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 - union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 - union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 - union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 - union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 - union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 - union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch - union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear - union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear - union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable - union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion - Uint16 rsvd1[4]; // Reserved - union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR External References & Function Declarations: -// -extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h deleted file mode 100644 index d4adbd8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h +++ /dev/null @@ -1,164 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pga.h -// -// TITLE: PGA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PGA_H__ -#define __F28004X_PGA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PGA Individual Register Bit Definitions: - -struct PGACTL_BITS { // bits description - Uint16 PGAEN:1; // 0 PGA Enable - Uint16 FILTRESSEL:4; // 4:1 Filter Resistor Select - Uint16 GAIN:3; // 7:5 PGA gain setting - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGACTL_REG { - Uint32 all; - struct PGACTL_BITS bit; -}; - -struct PGALOCK_BITS { // bits description - Uint16 PGACTL:1; // 0 Lock bit for PGACTL. - Uint16 rsvd1:1; // 1 Reserved - Uint16 PGAGAIN3TRIM:1; // 2 Lock bit for PGAGAIN3TRIM. - Uint16 PGAGAIN6TRIM:1; // 3 Lock bit for PGAGAIN6TRIM. - Uint16 PGAGAIN12TRIM:1; // 4 Lock bit for PGAGAIN12TRIM. - Uint16 PGAGAIN24TRIM:1; // 5 Lock bit for PGAGAIN24TRIM. - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:8; // 15:8 Reserved -}; - -union PGALOCK_REG { - Uint16 all; - struct PGALOCK_BITS bit; -}; - -struct PGAGAIN3TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 3 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 3 -}; - -union PGAGAIN3TRIM_REG { - Uint16 all; - struct PGAGAIN3TRIM_BITS bit; -}; - -struct PGAGAIN6TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 6 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 6 -}; - -union PGAGAIN6TRIM_REG { - Uint16 all; - struct PGAGAIN6TRIM_BITS bit; -}; - -struct PGAGAIN12TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 12 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 12 -}; - -union PGAGAIN12TRIM_REG { - Uint16 all; - struct PGAGAIN12TRIM_BITS bit; -}; - -struct PGAGAIN24TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 24 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 24 -}; - -union PGAGAIN24TRIM_REG { - Uint16 all; - struct PGAGAIN24TRIM_BITS bit; -}; - -struct PGATYPE_BITS { // bits description - Uint16 REV:8; // 7:0 PGA Revision Field - Uint16 TYPE:8; // 15:8 PGA Type Field -}; - -union PGATYPE_REG { - Uint16 all; - struct PGATYPE_BITS bit; -}; - -struct PGA_REGS { - union PGACTL_REG PGACTL; // PGA Control Register - union PGALOCK_REG PGALOCK; // PGA Lock Register - Uint16 rsvd1; // Reserved - union PGAGAIN3TRIM_REG PGAGAIN3TRIM; // PGA Gain Trim Register for a gain setting of 3 - union PGAGAIN6TRIM_REG PGAGAIN6TRIM; // PGA Gain Trim Register for a gain setting of 6 - union PGAGAIN12TRIM_REG PGAGAIN12TRIM; // PGA Gain Trim Register for a gain setting of 12 - union PGAGAIN24TRIM_REG PGAGAIN24TRIM; // PGA Gain Trim Register for a gain setting of 24 - union PGATYPE_REG PGATYPE; // PGA Type Register - Uint16 rsvd2[7]; // Reserved -}; - -//--------------------------------------------------------------------------- -// PGA External References & Function Declarations: -// -extern volatile struct PGA_REGS Pga1Regs; -extern volatile struct PGA_REGS Pga2Regs; -extern volatile struct PGA_REGS Pga3Regs; -extern volatile struct PGA_REGS Pga4Regs; -extern volatile struct PGA_REGS Pga5Regs; -extern volatile struct PGA_REGS Pga6Regs; -extern volatile struct PGA_REGS Pga7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h deleted file mode 100644 index 2c44154..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h +++ /dev/null @@ -1,702 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_piectrl.h -// -// TITLE: PIECTRL Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PIECTRL_H__ -#define __F28004X_PIECTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PIECTRL Individual Register Bit Definitions: - -struct PIECTRL_BITS { // bits description - Uint16 ENPIE:1; // 0 PIE Enable - Uint16 PIEVECT:15; // 15:1 PIE Vector Address -}; - -union PIECTRL_REG { - Uint16 all; - struct PIECTRL_BITS bit; -}; - -struct PIEACK_BITS { // bits description - Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 - Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 - Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 - Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 - Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 - Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 - Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 - Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 - Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 - Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 - Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 - Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union PIEACK_REG { - Uint16 all; - struct PIEACK_BITS bit; -}; - -struct PIEIER1_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 -}; - -union PIEIER1_REG { - Uint16 all; - struct PIEIER1_BITS bit; -}; - -struct PIEIFR1_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 -}; - -union PIEIFR1_REG { - Uint16 all; - struct PIEIFR1_BITS bit; -}; - -struct PIEIER2_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 -}; - -union PIEIER2_REG { - Uint16 all; - struct PIEIER2_BITS bit; -}; - -struct PIEIFR2_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 -}; - -union PIEIFR2_REG { - Uint16 all; - struct PIEIFR2_BITS bit; -}; - -struct PIEIER3_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 -}; - -union PIEIER3_REG { - Uint16 all; - struct PIEIER3_BITS bit; -}; - -struct PIEIFR3_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 -}; - -union PIEIFR3_REG { - Uint16 all; - struct PIEIFR3_BITS bit; -}; - -struct PIEIER4_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 -}; - -union PIEIER4_REG { - Uint16 all; - struct PIEIER4_BITS bit; -}; - -struct PIEIFR4_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 -}; - -union PIEIFR4_REG { - Uint16 all; - struct PIEIFR4_BITS bit; -}; - -struct PIEIER5_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 -}; - -union PIEIER5_REG { - Uint16 all; - struct PIEIER5_BITS bit; -}; - -struct PIEIFR5_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 -}; - -union PIEIFR5_REG { - Uint16 all; - struct PIEIFR5_BITS bit; -}; - -struct PIEIER6_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 -}; - -union PIEIER6_REG { - Uint16 all; - struct PIEIER6_BITS bit; -}; - -struct PIEIFR6_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 -}; - -union PIEIFR6_REG { - Uint16 all; - struct PIEIFR6_BITS bit; -}; - -struct PIEIER7_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 -}; - -union PIEIER7_REG { - Uint16 all; - struct PIEIER7_BITS bit; -}; - -struct PIEIFR7_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 -}; - -union PIEIFR7_REG { - Uint16 all; - struct PIEIFR7_BITS bit; -}; - -struct PIEIER8_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 -}; - -union PIEIER8_REG { - Uint16 all; - struct PIEIER8_BITS bit; -}; - -struct PIEIFR8_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 -}; - -union PIEIFR8_REG { - Uint16 all; - struct PIEIFR8_BITS bit; -}; - -struct PIEIER9_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 -}; - -union PIEIER9_REG { - Uint16 all; - struct PIEIER9_BITS bit; -}; - -struct PIEIFR9_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 -}; - -union PIEIFR9_REG { - Uint16 all; - struct PIEIFR9_BITS bit; -}; - -struct PIEIER10_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 -}; - -union PIEIER10_REG { - Uint16 all; - struct PIEIER10_BITS bit; -}; - -struct PIEIFR10_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 -}; - -union PIEIFR10_REG { - Uint16 all; - struct PIEIFR10_BITS bit; -}; - -struct PIEIER11_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 -}; - -union PIEIER11_REG { - Uint16 all; - struct PIEIER11_BITS bit; -}; - -struct PIEIFR11_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 -}; - -union PIEIFR11_REG { - Uint16 all; - struct PIEIFR11_BITS bit; -}; - -struct PIEIER12_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 -}; - -union PIEIER12_REG { - Uint16 all; - struct PIEIER12_BITS bit; -}; - -struct PIEIFR12_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 -}; - -union PIEIFR12_REG { - Uint16 all; - struct PIEIFR12_BITS bit; -}; - -struct PIE_CTRL_REGS { - union PIECTRL_REG PIECTRL; // ePIE Control Register - union PIEACK_REG PIEACK; // Interrupt Acknowledge Register - union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register - union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register - union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register - union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register - union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register - union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register - union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register - union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register - union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register - union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register - union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register - union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register - union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register - union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register - union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register - union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register - union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register - union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register - union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register - union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register - union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register - union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register - union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register - union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register -}; - -//--------------------------------------------------------------------------- -// PIECTRL External References & Function Declarations: -// -extern volatile struct PIE_CTRL_REGS PieCtrlRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h deleted file mode 100644 index 54899af..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h +++ /dev/null @@ -1,297 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pievect.h -// -// TITLE: F28004x Device PIE Vector Table Definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_PIEVECT_H -#define F28004X_PIEVECT_H -#ifdef __cplusplus -extern "C" { -#endif - -//--------------------------------------------------------------------------- -// PIE Interrupt Vector Table Definition: -// Create a user type called PINT (pointer to interrupt): - -typedef __interrupt void (*PINT)(void); - -// Define Vector Table: -struct PIE_VECT_TABLE { - PINT PIE1_RESERVED_INT; // Reserved - PINT PIE2_RESERVED_INT; // Reserved - PINT PIE3_RESERVED_INT; // Reserved - PINT PIE4_RESERVED_INT; // Reserved - PINT PIE5_RESERVED_INT; // Reserved - PINT PIE6_RESERVED_INT; // Reserved - PINT PIE7_RESERVED_INT; // Reserved - PINT PIE8_RESERVED_INT; // Reserved - PINT PIE9_RESERVED_INT; // Reserved - PINT PIE10_RESERVED_INT; // Reserved - PINT PIE11_RESERVED_INT; // Reserved - PINT PIE12_RESERVED_INT; // Reserved - PINT PIE13_RESERVED_INT; // Reserved - PINT TIMER1_INT; // CPU Timer 1 Interrupt - PINT TIMER2_INT; // CPU Timer 2 Interrupt - PINT DATALOG_INT; // Datalogging Interrupt - PINT RTOS_INT; // RTOS Interrupt - PINT EMU_INT; // Emulation Interrupt - PINT NMI_INT; // Non-Maskable Interrupt - PINT ILLEGAL_INT; // Illegal Operation Trap - PINT USER1_INT; // User Defined Trap 1 - PINT USER2_INT; // User Defined Trap 2 - PINT USER3_INT; // User Defined Trap 3 - PINT USER4_INT; // User Defined Trap 4 - PINT USER5_INT; // User Defined Trap 5 - PINT USER6_INT; // User Defined Trap 6 - PINT USER7_INT; // User Defined Trap 7 - PINT USER8_INT; // User Defined Trap 8 - PINT USER9_INT; // User Defined Trap 9 - PINT USER10_INT; // User Defined Trap 10 - PINT USER11_INT; // User Defined Trap 11 - PINT USER12_INT; // User Defined Trap 12 - PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 - PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 - PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 - PINT XINT1_INT; // 1.4 - XINT1 Interrupt - PINT XINT2_INT; // 1.5 - XINT2 Interrupt - PINT PIE14_RESERVED_INT; // 1.6 - Reserved - PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt - PINT WAKE_INT; // 1.8 - Halt Wakeup Interrupt - PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt - PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt - PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt - PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt - PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt - PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt - PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt - PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt - PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt - PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt - PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt - PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt - PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt - PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt - PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt - PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt - PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt - PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt - PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt - PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt - PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt - PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt - PINT ECAP7_INT; // 4.7 - eCAP7 Interrupt - PINT PIE15_RESERVED_INT; // 4.8 - Reserved - PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt - PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt - PINT PIE16_RESERVED_INT; // 5.3 - Reserved - PINT PIE17_RESERVED_INT; // 5.4 - Reserved - PINT PIE18_RESERVED_INT; // 5.5 - Reserved - PINT PIE19_RESERVED_INT; // 5.6 - Reserved - PINT PIE20_RESERVED_INT; // 5.7 - Reserved - PINT PIE21_RESERVED_INT; // 5.8 - Reserved - PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt - PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt - PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt - PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt - PINT PIE22_RESERVED_INT; // 6.5 - Reserved - PINT PIE23_RESERVED_INT; // 6.6 - Reserved - PINT PIE24_RESERVED_INT; // 6.7 - Reserved - PINT PIE25_RESERVED_INT; // 6.8 - Reserved - PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt - PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt - PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt - PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt - PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt - PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt - PINT PIE26_RESERVED_INT; // 7.7 - Reserved - PINT PIE27_RESERVED_INT; // 7.8 - Reserved - PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 - PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 - PINT PIE28_RESERVED_INT; // 8.3 - Reserved - PINT PIE29_RESERVED_INT; // 8.4 - Reserved - PINT PIE30_RESERVED_INT; // 8.5 - Reserved - PINT PIE31_RESERVED_INT; // 8.6 - Reserved - PINT PIE32_RESERVED_INT; // 8.7 - Reserved - PINT PIE33_RESERVED_INT; // 8.8 - Reserved - PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt - PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt - PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt - PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt - PINT CANA0_INT; // 9.5 - CANA Interrupt 0 - PINT CANA1_INT; // 9.6 - CANA Interrupt 1 - PINT CANB0_INT; // 9.7 - CANB Interrupt 0 - PINT CANB1_INT; // 9.8 - CANB Interrupt 1 - PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt - PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 - PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 - PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 - PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt - PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 - PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 - PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 - PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 - PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 - PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 - PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 - PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 - PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 - PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 - PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 - PINT XINT3_INT; // 12.1 - XINT3 Interrupt - PINT XINT4_INT; // 12.2 - XINT4 Interrupt - PINT XINT5_INT; // 12.3 - XINT5 Interrupt - PINT PIE34_RESERVED_INT; // 12.4 - Reserved - PINT PIE35_RESERVED_INT; // 12.5 - Reserved - PINT PIE36_RESERVED_INT; // 12.6 - Reserved - PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt - PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt - PINT PIE37_RESERVED_INT; // 1.9 - Reserved - PINT PIE38_RESERVED_INT; // 1.10 - Reserved - PINT PIE39_RESERVED_INT; // 1.11 - Reserved - PINT PIE40_RESERVED_INT; // 1.12 - Reserved - PINT PIE41_RESERVED_INT; // 1.13 - Reserved - PINT PIE42_RESERVED_INT; // 1.14 - Reserved - PINT PIE43_RESERVED_INT; // 1.15 - Reserved - PINT PIE44_RESERVED_INT; // 1.16 - Reserved - PINT PIE45_RESERVED_INT; // 2.9 - Reserved - PINT PIE46_RESERVED_INT; // 2.10 - Reserved - PINT PIE47_RESERVED_INT; // 2.11 - Reserved - PINT PIE48_RESERVED_INT; // 2.12 - Reserved - PINT PIE49_RESERVED_INT; // 2.13 - Reserved - PINT PIE50_RESERVED_INT; // 2.14 - Reserved - PINT PIE51_RESERVED_INT; // 2.15 - Reserved - PINT PIE52_RESERVED_INT; // 2.16 - Reserved - PINT PIE53_RESERVED_INT; // 3.9 - Reserved - PINT PIE54_RESERVED_INT; // 3.10 - Reserved - PINT PIE55_RESERVED_INT; // 3.11 - Reserved - PINT PIE56_RESERVED_INT; // 3.12 - Reserved - PINT PIE57_RESERVED_INT; // 3.13 - Reserved - PINT PIE58_RESERVED_INT; // 3.14 - Reserved - PINT PIE59_RESERVED_INT; // 3.15 - Reserved - PINT PIE60_RESERVED_INT; // 3.16 - Reserved - PINT PIE61_RESERVED_INT; // 4.9 - Reserved - PINT PIE62_RESERVED_INT; // 4.10 - Reserved - PINT PIE63_RESERVED_INT; // 4.11 - Reserved - PINT PIE64_RESERVED_INT; // 4.12 - Reserved - PINT PIE65_RESERVED_INT; // 4.13 - Reserved - PINT ECAP6_2_INT; // 4.14 - eCAP6_2 Interrupt - PINT ECAP7_2_INT; // 4.15 - eCAP7_2 Interrupt - PINT PIE66_RESERVED_INT; // 4.16 - Reserved - PINT SD1_INT; // 5.9 - SD1 Interrupt - PINT PIE67_RESERVED_INT; // 5.10 - Reserved - PINT PIE68_RESERVED_INT; // 5.11 - Reserved - PINT PIE69_RESERVED_INT; // 5.12 - Reserved - PINT SD1DR1_INT; // 5.13 - SD1DR1 Interrupt - PINT SD1DR2_INT; // 5.14 - SD1DR2 Interrupt - PINT SD1DR3_INT; // 5.15 - SD1DR3 Interrupt - PINT SD1DR4_INT; // 5.16 - SD1DR4 Interrupt - PINT PIE70_RESERVED_INT; // 6.9 - Reserved - PINT PIE71_RESERVED_INT; // 6.10 - Reserved - PINT PIE72_RESERVED_INT; // 6.11 - Reserved - PINT PIE73_RESERVED_INT; // 6.12 - Reserved - PINT PIE74_RESERVED_INT; // 6.13 - Reserved - PINT PIE75_RESERVED_INT; // 6.14 - Reserved - PINT PIE76_RESERVED_INT; // 6.15 - Reserved - PINT PIE77_RESERVED_INT; // 6.16 - Reserved - PINT PIE78_RESERVED_INT; // 7.9 - Reserved - PINT PIE79_RESERVED_INT; // 7.10 - Reserved - PINT PIE80_RESERVED_INT; // 7.11 - Reserved - PINT PIE81_RESERVED_INT; // 7.12 - Reserved - PINT PIE82_RESERVED_INT; // 7.13 - Reserved - PINT PIE83_RESERVED_INT; // 7.14 - Reserved - PINT CLA1PROMCRC_INT; // 7.15 - CLA1PROMCRC Interrupt - PINT PIE84_RESERVED_INT; // 7.16 - Reserved - PINT LINA_0_INT; // 8.9 - LINA Interrupt0 - PINT LINA_1_INT; // 8.10 - LINA Interrupt1 - PINT PIE85_RESERVED_INT; // 8.11 - Reserved - PINT PIE86_RESERVED_INT; // 8.12 - Reserved - PINT PMBUSA_INT; // 8.13 - PMBUSA Interrupt - PINT PIE87_RESERVED_INT; // 8.14 - Reserved - PINT PIE88_RESERVED_INT; // 8.15 - Reserved - PINT PIE89_RESERVED_INT; // 8.16 - Reserved - PINT PIE90_RESERVED_INT; // 9.9 - Reserved - PINT PIE91_RESERVED_INT; // 9.10 - Reserved - PINT PIE92_RESERVED_INT; // 9.11 - Reserved - PINT PIE93_RESERVED_INT; // 9.12 - Reserved - PINT PIE94_RESERVED_INT; // 9.13 - Reserved - PINT PIE95_RESERVED_INT; // 9.14 - Reserved - PINT PIE96_RESERVED_INT; // 9.15 - Reserved - PINT PIE97_RESERVED_INT; // 9.16 - Reserved - PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt - PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 - PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 - PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 - PINT PIE98_RESERVED_INT; // 10.13 - Reserved - PINT PIE99_RESERVED_INT; // 10.14 - Reserved - PINT PIE100_RESERVED_INT; // 10.15 - Reserved - PINT PIE101_RESERVED_INT; // 10.16 - Reserved - PINT PIE102_RESERVED_INT; // 11.9 - Reserved - PINT PIE103_RESERVED_INT; // 11.10 - Reserved - PINT PIE104_RESERVED_INT; // 11.11 - Reserved - PINT PIE105_RESERVED_INT; // 11.12 - Reserved - PINT PIE106_RESERVED_INT; // 11.13 - Reserved - PINT PIE107_RESERVED_INT; // 11.14 - Reserved - PINT PIE108_RESERVED_INT; // 11.15 - Reserved - PINT PIE109_RESERVED_INT; // 11.16 - Reserved - PINT PIE110_RESERVED_INT; // 12.9 - Reserved - PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt - PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt - PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt - PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt - PINT PIE111_RESERVED_INT; // 12.14 - Reserved - PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt - PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt -}; - -//--------------------------------------------------------------------------- -// PieVect External References & Function Declarations: -// - -extern volatile struct PIE_VECT_TABLE PieVectTable; - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F28004X_PIEVECT_H definition -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h deleted file mode 100644 index 0f55745..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h +++ /dev/null @@ -1,291 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pmbus.h -// -// TITLE: PMBUS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PMBUS_H__ -#define __F28004X_PMBUS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PMBUS Individual Register Bit Definitions: - -struct PMBMC_BITS { // bits description - Uint16 RW:1; // 0 RnW bit of the Message - Uint16 SLAVE_ADDR:7; // 7:1 Slave Address - Uint16 BYTE_COUNT:8; // 15:8 Number of Bytes Transmitted - Uint16 CMD_ENA:1; // 16 Master Command Code Enable - Uint16 EXT_CMD:1; // 17 Master Extended Command Code Enable - Uint16 PEC_ENA:1; // 18 Master PEC Processing Enable - Uint16 GRP_CMD:1; // 19 Master Group Command Message Enable - Uint16 PRC_CALL:1; // 20 Master Process Call Message Enable - Uint16 rsvd1:11; // 31:21 Reserved -}; - -union PMBMC_REG { - Uint32 all; - struct PMBMC_BITS bit; -}; - -struct PMBACK_BITS { // bits description - Uint16 ACK:1; // 0 Allows firmware to ack/nack received data - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBACK_REG { - Uint32 all; - struct PMBACK_BITS bit; -}; - -struct PMBSTS_BITS { // bits description - Uint16 RD_BYTE_COUNT:3; // 2:0 Number of Data Bytes available in Receive Data Register - Uint16 DATA_READY:1; // 3 Data Ready Flag - Uint16 DATA_REQUEST:1; // 4 Data Request Flag - Uint16 EOM:1; // 5 End of Message Indicator - Uint16 NACK:1; // 6 Not Acknowledge Flag Status - Uint16 PEC_VALID:1; // 7 PEC Valid Indicator - Uint16 CLK_LOW_TIMEOUT:1; // 8 Clock Low Timeout Status - Uint16 CLK_HIGH_DETECTED:1; // 9 Clock High Detection Status - Uint16 SLAVE_ADDR_READY:1; // 10 Slave Address Ready - Uint16 RPT_START:1; // 11 Repeated Start Flag - Uint16 UNIT_BUSY:1; // 12 PMBus Busy Indicator - Uint16 BUS_FREE:1; // 13 PMBus Free Indicator - Uint16 LOST_ARB:1; // 14 Lost Arbitration Flag - Uint16 MASTER:1; // 15 Master Indicator - Uint16 ALERT_EDGE:1; // 16 Alert Edge Detection Status - Uint16 CONTROL_EDGE:1; // 17 Control Edge Detection Status - Uint16 ALERT_RAW:1; // 18 Alert Pin Real Time Status - Uint16 CONTROL_RAW:1; // 19 Control Pin Real Time Status - Uint16 SDA_RAW:1; // 20 PMBus Data Pin Real Time Status - Uint16 SCL_RAW:1; // 21 PMBus Clock Pin Real Time Status - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PMBSTS_REG { - Uint32 all; - struct PMBSTS_BITS bit; -}; - -struct PMBINTM_BITS { // bits description - Uint16 BUS_FREE:1; // 0 Bus Free Interrupt Mask - Uint16 BUS_LOW_TIMEOUT:1; // 1 Clock Low Timeout Interrupt Mask - Uint16 DATA_READY:1; // 2 Data Ready Interrupt Mask - Uint16 DATA_REQUEST:1; // 3 Data Request Interrupt Mask - Uint16 SLAVE_ADDR_READY:1; // 4 Slave Address Ready Interrupt Mask - Uint16 EOM:1; // 5 End of Message Interrupt Mask - Uint16 ALERT:1; // 6 Alert Detection Interrupt Mask - Uint16 CONTROL:1; // 7 Control Detection Interrupt Mask - Uint16 LOST_ARB:1; // 8 Lost Arbitration Interrupt Mask - Uint16 CLK_HIGH_DETECT:1; // 9 Clock High Detection Interrupt Mask - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBINTM_REG { - Uint32 all; - struct PMBINTM_BITS bit; -}; - -struct PMBSC_BITS { // bits description - Uint16 SLAVE_ADDR:7; // 6:0 Configures the current device address of the slave. - Uint16 MAN_SLAVE_ACK:1; // 7 Manual Slave Address Acknowledgement Mode - Uint16 SLAVE_MASK:7; // 14:8 Slave address mask - Uint16 PEC_ENA:1; // 15 PEC Processing Enable - Uint16 TX_COUNT:3; // 18:16 Number of valid bytes in Transmit Data Register - Uint16 TX_PEC:1; // 19 send a PEC byte at end of message - Uint16 MAN_CMD:1; // 20 Manual Command Acknowledgement Mode - Uint16 RX_BYTE_ACK_CNT:2; // 22:21 Number of data bytes to automatically acknowledge - Uint16 rsvd1:9; // 31:23 Reserved -}; - -union PMBSC_REG { - Uint32 all; - struct PMBSC_BITS bit; -}; - -struct PMBHSA_BITS { // bits description - Uint16 SLAVE_RW:1; // 0 Stored R/W bit - Uint16 SLAVE_ADDR:7; // 7:1 Stored device address - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBHSA_REG { - Uint32 all; - struct PMBHSA_BITS bit; -}; - -struct PMBCTRL_BITS { // bits description - Uint16 RESET:1; // 0 PMBus Interface Synchronous Reset - Uint16 ALERT_EN:1; // 1 Slave Alert Enable - Uint16 BUS_LO_INT_EDGE:1; // 2 Clock Low Timeout Interrupt Edge Select - Uint16 FAST_MODE:1; // 3 Fast Mode Enable - Uint16 FAST_MODE_PLUS:1; // 4 Fast Mode Plus Enable - Uint16 CNTL_INT_EDGE:1; // 5 Control Interrupt Edge Select - Uint16 ALERT_MODE:1; // 6 Configures mode of Alert pin - Uint16 ALERT_VALUE:1; // 7 Configures output value of Alert pin in GPIO Mode - Uint16 ALERT_DIR:1; // 8 Configures direction of Alert pin in GPIO mode - Uint16 CNTL_MODE:1; // 9 Configures mode of Control pin - Uint16 CNTL_VALUE:1; // 10 Configures output value of Control pin in GPIO Mode - Uint16 CNTL_DIR:1; // 11 Configures direction of Control pin in GPIO mode - Uint16 SDA_MODE:1; // 12 Configures mode of PMBus Data pin - Uint16 SDA_VALUE:1; // 13 Configures output value of PMBus data pin in GPIO Mode - Uint16 SDA_DIR:1; // 14 Configures direction of PMBus data pin in GPIO mode - Uint16 SCL_MODE:1; // 15 Configures mode of PMBus Clock pin - Uint16 SCL_VALUE:1; // 16 Configures output value of PMBus clock pin in GPIO Mode - Uint16 SCL_DIR:1; // 17 Configures direction of PMBus clock pin in GPIO mode - Uint16 IBIAS_A_EN:1; // 18 PMBus Current Source A Control - Uint16 IBIAS_B_EN:1; // 19 PMBus Current Source B Control - Uint16 CLK_LO_DIS:1; // 20 Clock Low Timeout Disable - Uint16 SLAVE_EN:1; // 21 PMBus Slave Enable - Uint16 MASTER_EN:1; // 22 PMBus Master Enable - Uint16 CLKDIV:5; // 27:23 PMBUS IP Clock Divide Value - Uint16 rsvd1:3; // 30:28 Reserved - Uint16 I2CMODE:1; // 31 Bit to enable I2C mode -}; - -union PMBCTRL_REG { - Uint32 all; - struct PMBCTRL_BITS bit; -}; - -struct PMBTIMCTL_BITS { // bits description - Uint16 TIM_OVERRIDE:1; // 0 Overide the default settings of the timing parameters. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMCTL_REG { - Uint32 all; - struct PMBTIMCTL_BITS bit; -}; - -struct PMBTIMCLK_BITS { // bits description - Uint16 CLK_HIGH_LIMIT:8; // 7:0 Determines the PMBUS master clock high pulse width. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 CLK_FREQ:8; // 23:16 Determines the PMBUS master clock frequency. - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union PMBTIMCLK_REG { - Uint32 all; - struct PMBTIMCLK_BITS bit; -}; - -struct PMBTIMSTSETUP_BITS { // bits description - Uint16 TSU_STA:8; // 7:0 Setup time, rise edge of PMBUS master clock to start edge. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMSTSETUP_REG { - Uint32 all; - struct PMBTIMSTSETUP_BITS bit; -}; - -struct PMBTIMBIDLE_BITS { // bits description - Uint16 BUSIDLE:10; // 9:0 Determines the Bus Idle Limit - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMBIDLE_REG { - Uint32 all; - struct PMBTIMBIDLE_BITS bit; -}; - -struct PMBTIMLOWTIMOUT_BITS { // bits description - Uint32 CLKLOWTIMOUT:20; // 19:0 Determines the clock low timeout value - Uint16 rsvd1:12; // 31:20 Reserved -}; - -union PMBTIMLOWTIMOUT_REG { - Uint32 all; - struct PMBTIMLOWTIMOUT_BITS bit; -}; - -struct PMBTIMHIGHTIMOUT_BITS { // bits description - Uint16 CLKHIGHTIMOUT:10; // 9:0 Determines the clock high timeout value - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMHIGHTIMOUT_REG { - Uint32 all; - struct PMBTIMHIGHTIMOUT_BITS bit; -}; - -struct PMBUS_REGS { - union PMBMC_REG PMBMC; // PMBUS Master Mode Control Register - Uint32 PMBTXBUF; // PMBUS Transmit Buffer - Uint32 PMBRXBUF; // PMBUS Receive buffer - union PMBACK_REG PMBACK; // PMBUS Acknowledge Register - union PMBSTS_REG PMBSTS; // PMBUS Status Register - union PMBINTM_REG PMBINTM; // PMBUS Interrupt Mask Register - union PMBSC_REG PMBSC; // PMBUS Slave Mode Configuration Register - union PMBHSA_REG PMBHSA; // PMBUS Hold Slave Address Register - union PMBCTRL_REG PMBCTRL; // PMBUS Control Register - union PMBTIMCTL_REG PMBTIMCTL; // PMBUS Timing Control Register - union PMBTIMCLK_REG PMBTIMCLK; // PMBUS Clock Timing Register - union PMBTIMSTSETUP_REG PMBTIMSTSETUP; // PMBUS Start Setup Time Register - union PMBTIMBIDLE_REG PMBTIMBIDLE; // PMBUS Bus Idle Time Register - union PMBTIMLOWTIMOUT_REG PMBTIMLOWTIMOUT; // PMBUS Clock Low Timeout Value Register - union PMBTIMHIGHTIMOUT_REG PMBTIMHIGHTIMOUT; // PMBUS Clock High Timeout Value Register - Uint16 rsvd1[2]; // Reserved -}; - -//--------------------------------------------------------------------------- -// PMBUS External References & Function Declarations: -// -extern volatile struct PMBUS_REGS PmbusaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h deleted file mode 100644 index cbb8c2c..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sci.h -// -// TITLE: SCI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SCI_H__ -#define __F28004X_SCI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SCI Individual Register Bit Definitions: - -struct SCICCR_BITS { // bits description - Uint16 SCICHAR:3; // 2:0 Character length control - Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control - Uint16 LOOPBKENA:1; // 4 Loop Back enable - Uint16 PARITYENA:1; // 5 Parity enable - Uint16 PARITY:1; // 6 Even or Odd Parity - Uint16 STOPBITS:1; // 7 Number of Stop Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCICCR_REG { - Uint16 all; - struct SCICCR_BITS bit; -}; - -struct SCICTL1_BITS { // bits description - Uint16 RXENA:1; // 0 SCI receiver enable - Uint16 TXENA:1; // 1 SCI transmitter enable - Uint16 SLEEP:1; // 2 SCI sleep - Uint16 TXWAKE:1; // 3 Transmitter wakeup method - Uint16 rsvd1:1; // 4 Reserved - Uint16 SWRESET:1; // 5 Software reset - Uint16 RXERRINTENA:1; // 6 Receive __interrupt enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union SCICTL1_REG { - Uint16 all; - struct SCICTL1_BITS bit; -}; - -struct SCIHBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIHBAUD_REG { - Uint16 all; - struct SCIHBAUD_BITS bit; -}; - -struct SCILBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCILBAUD_REG { - Uint16 all; - struct SCILBAUD_BITS bit; -}; - -struct SCICTL2_BITS { // bits description - Uint16 TXINTENA:1; // 0 Transmit __interrupt enable - Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable - Uint16 rsvd1:4; // 5:2 Reserved - Uint16 TXEMPTY:1; // 6 Transmitter empty flag - Uint16 TXRDY:1; // 7 Transmitter ready flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCICTL2_REG { - Uint16 all; - struct SCICTL2_BITS bit; -}; - -struct SCIRXST_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag - Uint16 PE:1; // 2 Parity error flag - Uint16 OE:1; // 3 Overrun error flag - Uint16 FE:1; // 4 Framing error flag - Uint16 BRKDT:1; // 5 Break-detect flag - Uint16 RXRDY:1; // 6 Receiver ready flag - Uint16 RXERROR:1; // 7 Receiver error flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCIRXST_REG { - Uint16 all; - struct SCIRXST_BITS bit; -}; - -struct SCIRXEMU_BITS { // bits description - Uint16 ERXDT:8; // 7:0 Receive emulation buffer data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIRXEMU_REG { - Uint16 all; - struct SCIRXEMU_BITS bit; -}; - -struct SCIRXBUF_BITS { // bits description - Uint16 SAR:8; // 7:0 Receive Character bits - Uint16 rsvd1:6; // 13:8 Reserved - Uint16 SCIFFPE:1; // 14 Receiver error flag - Uint16 SCIFFFE:1; // 15 Receiver error flag -}; - -union SCIRXBUF_REG { - Uint16 all; - struct SCIRXBUF_BITS bit; -}; - -struct SCITXBUF_BITS { // bits description - Uint16 TXDT:8; // 7:0 Transmit data buffer - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCITXBUF_REG { - Uint16 all; - struct SCITXBUF_BITS bit; -}; - -struct SCIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Interrupt level - Uint16 TXFFIENA:1; // 5 Interrupt enable - Uint16 TXFFINTCLR:1; // 6 Clear INT flag - Uint16 TXFFINT:1; // 7 INT flag - Uint16 TXFFST:5; // 12:8 FIFO status - Uint16 TXFIFORESET:1; // 13 FIFO reset - Uint16 SCIFFENA:1; // 14 Enhancement enable - Uint16 SCIRST:1; // 15 SCI reset rx/tx channels -}; - -union SCIFFTX_REG { - Uint16 all; - struct SCIFFTX_BITS bit; -}; - -struct SCIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Interrupt level - Uint16 RXFFIENA:1; // 5 Interrupt enable - Uint16 RXFFINTCLR:1; // 6 Clear INT flag - Uint16 RXFFINT:1; // 7 INT flag - Uint16 RXFFST:5; // 12:8 FIFO status - Uint16 RXFIFORESET:1; // 13 FIFO reset - Uint16 RXFFOVRCLR:1; // 14 Clear overflow - Uint16 RXFFOVF:1; // 15 FIFO overflow -}; - -union SCIFFRX_REG { - Uint16 all; - struct SCIFFRX_BITS bit; -}; - -struct SCIFFCT_BITS { // bits description - Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay - Uint16 rsvd1:5; // 12:8 Reserved - Uint16 CDC:1; // 13 Auto baud mode enable - Uint16 ABDCLR:1; // 14 Auto baud clear - Uint16 ABD:1; // 15 Auto baud detect -}; - -union SCIFFCT_REG { - Uint16 all; - struct SCIFFCT_BITS bit; -}; - -struct SCIPRI_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 FREESOFT:2; // 4:3 Emulation modes - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 rsvd3:8; // 15:8 Reserved -}; - -union SCIPRI_REG { - Uint16 all; - struct SCIPRI_BITS bit; -}; - -struct SCI_REGS { - union SCICCR_REG SCICCR; // Communications control register - union SCICTL1_REG SCICTL1; // Control register 1 - union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register - union SCILBAUD_REG SCILBAUD; // Baud rate (low) register - union SCICTL2_REG SCICTL2; // Control register 2 - union SCIRXST_REG SCIRXST; // Receive status register - union SCIRXEMU_REG SCIRXEMU; // Receive emulation buffer register - union SCIRXBUF_REG SCIRXBUF; // Receive data buffer - Uint16 rsvd1; // Reserved - union SCITXBUF_REG SCITXBUF; // Transmit data buffer - union SCIFFTX_REG SCIFFTX; // FIFO transmit register - union SCIFFRX_REG SCIFFRX; // FIFO Receive register - union SCIFFCT_REG SCIFFCT; // FIFO control register - Uint16 rsvd2[2]; // Reserved - union SCIPRI_REG SCIPRI; // SCI Priority control -}; - -//--------------------------------------------------------------------------- -// SCI External References & Function Declarations: -// -extern volatile struct SCI_REGS SciaRegs; -extern volatile struct SCI_REGS ScibRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h deleted file mode 100644 index 340903e..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h +++ /dev/null @@ -1,797 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sdfm.h -// -// TITLE: SDFM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SDFM_H__ -#define __F28004X_SDFM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SDFM Individual Register Bit Definitions: - -struct SDIFLG_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 - Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 - Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 - Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 - Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 - Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 - Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 - Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 SDFFOVF1:1; // 16 FIFO Overflow Flag for Ch1. - Uint16 SDFFOVF2:1; // 17 FIFO Overflow Flag for Ch2 - Uint16 SDFFOVF3:1; // 18 FIFO Overflow Flag for Ch3 - Uint16 SDFFOVF4:1; // 19 FIFO Overflow Flag for Ch4 - Uint16 SDFFINT1:1; // 20 SDFIFO interrupt for Ch1 - Uint16 SDFFINT2:1; // 21 SDFIFO interrupt for Ch2 - Uint16 SDFFINT3:1; // 22 SDFIFO interrupt for Ch3 - Uint16 SDFFINT4:1; // 23 SDFIFO interrupt for Ch4 - Uint16 rsvd1:7; // 30:24 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLG_REG { - Uint32 all; - struct SDIFLG_BITS bit; -}; - -struct SDIFLGCLR_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 - Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 - Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 - Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 - Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 - Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 - Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 - Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 SDFFOVF1:1; // 16 SDFIFO overflow clear Ch1 - Uint16 SDFFOVF2:1; // 17 SDFIFO overflow clear Ch2 - Uint16 SDFFOVF3:1; // 18 SDFIFO overflow clear Ch3 - Uint16 SDFFOVF4:1; // 19 SDFIFO overflow clear Ch4 - Uint16 SDFFINT1:1; // 20 SDFIFO Interrupt flag-clear bit for Ch1 - Uint16 SDFFINT2:1; // 21 SDFIFO Interrupt flag-clear bit for Ch2 - Uint16 SDFFINT3:1; // 22 SDFIFO Interrupt flag-clear bit for Ch3 - Uint16 SDFFINT4:1; // 23 SDFIFO Interrupt flag-clear bit for Ch4 - Uint16 rsvd1:7; // 30:24 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLGCLR_REG { - Uint32 all; - struct SDIFLGCLR_BITS bit; -}; - -struct SDCTL_BITS { // bits description - Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 - Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 - Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 - Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 - Uint16 rsvd1:9; // 12:4 Reserved - Uint16 MIE:1; // 13 Master SDy_ERR Interrupt enable - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union SDCTL_REG { - Uint16 all; - struct SDCTL_BITS bit; -}; - -struct SDMFILEN_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:3; // 6:4 Reserved - Uint16 rsvd3:2; // 8:7 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:1; // 10 Reserved - Uint16 MFE:1; // 11 Master Filter Enable. - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:3; // 15:13 Reserved -}; - -union SDMFILEN_REG { - Uint16 all; - struct SDMFILEN_BITS bit; -}; - -struct SDSTATUS_BITS { // bits description - Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 - Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 - Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 - Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:1; // 10 Reserved - Uint16 rsvd5:1; // 11 Reserved - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:1; // 13 Reserved - Uint16 rsvd8:1; // 14 Reserved - Uint16 rsvd9:1; // 15 Reserved -}; - -union SDSTATUS_REG { - Uint16 all; - struct SDSTATUS_BITS bit; -}; - -struct SDCTLPARM1_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM1_REG { - Uint16 all; - struct SDCTLPARM1_BITS bit; -}; - -struct SDDFPARM1_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM1_REG { - Uint16 all; - struct SDDFPARM1_BITS bit; -}; - -struct SDDPARM1_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM1_REG { - Uint16 all; - struct SDDPARM1_BITS bit; -}; - -struct SDCMPH1_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH1_REG { - Uint16 all; - struct SDCMPH1_BITS bit; -}; - -struct SDCMPL1_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL1_REG { - Uint16 all; - struct SDCMPL1_BITS bit; -}; - -struct SDCPARM1_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM1_REG { - Uint16 all; - struct SDCPARM1_BITS bit; -}; - -struct SDDATA1_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA1_REG { - Uint32 all; - struct SDDATA1_BITS bit; -}; - -struct SDDATFIFO1_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO1_REG { - Uint32 all; - struct SDDATFIFO1_BITS bit; -}; - -struct SDCMPHZ1_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ1_REG { - Uint16 all; - struct SDCMPHZ1_BITS bit; -}; - -struct SDFIFOCTL1_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL1_REG { - Uint16 all; - struct SDFIFOCTL1_BITS bit; -}; - -struct SDSYNC1_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC1_REG { - Uint16 all; - struct SDSYNC1_BITS bit; -}; - -struct SDCTLPARM2_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM2_REG { - Uint16 all; - struct SDCTLPARM2_BITS bit; -}; - -struct SDDFPARM2_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM2_REG { - Uint16 all; - struct SDDFPARM2_BITS bit; -}; - -struct SDDPARM2_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM2_REG { - Uint16 all; - struct SDDPARM2_BITS bit; -}; - -struct SDCMPH2_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH2_REG { - Uint16 all; - struct SDCMPH2_BITS bit; -}; - -struct SDCMPL2_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL2_REG { - Uint16 all; - struct SDCMPL2_BITS bit; -}; - -struct SDCPARM2_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM2_REG { - Uint16 all; - struct SDCPARM2_BITS bit; -}; - -struct SDDATA2_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA2_REG { - Uint32 all; - struct SDDATA2_BITS bit; -}; - -struct SDDATFIFO2_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO2_REG { - Uint32 all; - struct SDDATFIFO2_BITS bit; -}; - -struct SDCMPHZ2_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ2_REG { - Uint16 all; - struct SDCMPHZ2_BITS bit; -}; - -struct SDFIFOCTL2_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL2_REG { - Uint16 all; - struct SDFIFOCTL2_BITS bit; -}; - -struct SDSYNC2_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC2_REG { - Uint16 all; - struct SDSYNC2_BITS bit; -}; - -struct SDCTLPARM3_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM3_REG { - Uint16 all; - struct SDCTLPARM3_BITS bit; -}; - -struct SDDFPARM3_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM3_REG { - Uint16 all; - struct SDDFPARM3_BITS bit; -}; - -struct SDDPARM3_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM3_REG { - Uint16 all; - struct SDDPARM3_BITS bit; -}; - -struct SDCMPH3_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH3_REG { - Uint16 all; - struct SDCMPH3_BITS bit; -}; - -struct SDCMPL3_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL3_REG { - Uint16 all; - struct SDCMPL3_BITS bit; -}; - -struct SDCPARM3_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM3_REG { - Uint16 all; - struct SDCPARM3_BITS bit; -}; - -struct SDDATA3_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA3_REG { - Uint32 all; - struct SDDATA3_BITS bit; -}; - -struct SDDATFIFO3_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO3_REG { - Uint32 all; - struct SDDATFIFO3_BITS bit; -}; - -struct SDCMPHZ3_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ3_REG { - Uint16 all; - struct SDCMPHZ3_BITS bit; -}; - -struct SDFIFOCTL3_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL3_REG { - Uint16 all; - struct SDFIFOCTL3_BITS bit; -}; - -struct SDSYNC3_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC3_REG { - Uint16 all; - struct SDSYNC3_BITS bit; -}; - -struct SDCTLPARM4_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM4_REG { - Uint16 all; - struct SDCTLPARM4_BITS bit; -}; - -struct SDDFPARM4_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM4_REG { - Uint16 all; - struct SDDFPARM4_BITS bit; -}; - -struct SDDPARM4_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM4_REG { - Uint16 all; - struct SDDPARM4_BITS bit; -}; - -struct SDCMPH4_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH4_REG { - Uint16 all; - struct SDCMPH4_BITS bit; -}; - -struct SDCMPL4_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL4_REG { - Uint16 all; - struct SDCMPL4_BITS bit; -}; - -struct SDCPARM4_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM4_REG { - Uint16 all; - struct SDCPARM4_BITS bit; -}; - -struct SDDATA4_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA4_REG { - Uint32 all; - struct SDDATA4_BITS bit; -}; - -struct SDDATFIFO4_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO4_REG { - Uint32 all; - struct SDDATFIFO4_BITS bit; -}; - -struct SDCMPHZ4_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ4_REG { - Uint16 all; - struct SDCMPHZ4_BITS bit; -}; - -struct SDFIFOCTL4_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL4_REG { - Uint16 all; - struct SDFIFOCTL4_BITS bit; -}; - -struct SDSYNC4_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC4_REG { - Uint16 all; - struct SDSYNC4_BITS bit; -}; - -struct SDFM_REGS { - union SDIFLG_REG SDIFLG; // SD Interrupt Flag Register - union SDIFLGCLR_REG SDIFLGCLR; // SD Interrupt Flag Clear Register - union SDCTL_REG SDCTL; // SD Control Register - Uint16 rsvd1; // Reserved - union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable - union SDSTATUS_REG SDSTATUS; // SD Status Register - Uint16 rsvd2[8]; // Reserved - union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 - union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 - union SDDPARM1_REG SDDPARM1; // Data Parameter Register for Ch1 - union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 - union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 - union SDCPARM1_REG SDCPARM1; // Comparator Filter Parameter Register for Ch1 - union SDDATA1_REG SDDATA1; // Data Filter Data Register (16 or 32bit) for Ch1 - union SDDATFIFO1_REG SDDATFIFO1; // Filter Data FIFO Output(32b) for Ch1 - Uint16 SDCDATA1; // Comparator Filter Data Register (16b) for Ch1 - Uint16 rsvd3; // Reserved - union SDCMPHZ1_REG SDCMPHZ1; // High-level (Z) Threshold Register for Ch1 - union SDFIFOCTL1_REG SDFIFOCTL1; // FIFO Control Register for Ch1 - union SDSYNC1_REG SDSYNC1; // SD Filter Sync control for Ch1 - Uint16 rsvd4; // Reserved - union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 - union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 - union SDDPARM2_REG SDDPARM2; // Data Parameter Register for Ch2 - union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 - union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 - union SDCPARM2_REG SDCPARM2; // Comparator Filter Parameter Register for Ch2 - union SDDATA2_REG SDDATA2; // Data Filter Data Register (16 or 32bit) for Ch2 - union SDDATFIFO2_REG SDDATFIFO2; // Filter Data FIFO Output(32b) for Ch2 - Uint16 SDCDATA2; // Comparator Filter Data Register (16b) for Ch2 - Uint16 rsvd5; // Reserved - union SDCMPHZ2_REG SDCMPHZ2; // High-level (Z) Threshold Register for Ch2 - union SDFIFOCTL2_REG SDFIFOCTL2; // FIFO Control Register for Ch2 - union SDSYNC2_REG SDSYNC2; // SD Filter Sync control for Ch2 - Uint16 rsvd6; // Reserved - union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 - union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 - union SDDPARM3_REG SDDPARM3; // Data Parameter Register for Ch3 - union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 - union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 - union SDCPARM3_REG SDCPARM3; // Comparator Filter Parameter Register for Ch3 - union SDDATA3_REG SDDATA3; // Data Filter Data Register (16 or 32bit) for Ch3 - union SDDATFIFO3_REG SDDATFIFO3; // Filter Data FIFO Output(32b) for Ch3 - Uint16 SDCDATA3; // Comparator Filter Data Register (16b) for Ch3 - Uint16 rsvd7; // Reserved - union SDCMPHZ3_REG SDCMPHZ3; // High-level (Z) Threshold Register for Ch3 - union SDFIFOCTL3_REG SDFIFOCTL3; // FIFO Control Register for Ch3 - union SDSYNC3_REG SDSYNC3; // SD Filter Sync control for Ch3 - Uint16 rsvd8; // Reserved - union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 - union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 - union SDDPARM4_REG SDDPARM4; // Data Parameter Register for Ch4 - union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 - union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 - union SDCPARM4_REG SDCPARM4; // Comparator Filter Parameter Register for Ch4 - union SDDATA4_REG SDDATA4; // Data Filter Data Register (16 or 32bit) for Ch4 - union SDDATFIFO4_REG SDDATFIFO4; // Filter Data FIFO Output(32b) for Ch4 - Uint16 SDCDATA4; // Comparator Filter Data Register (16b) for Ch4 - Uint16 rsvd9; // Reserved - union SDCMPHZ4_REG SDCMPHZ4; // High-level (Z) Threshold Register for Ch4 - union SDFIFOCTL4_REG SDFIFOCTL4; // FIFO Control Register for Ch4 - union SDSYNC4_REG SDSYNC4; // SD Filter Sync control for Ch4 - Uint16 rsvd10[33]; // Reserved -}; - -//--------------------------------------------------------------------------- -// SDFM External References & Function Declarations: -// -extern volatile struct SDFM_REGS Sdfm1Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h deleted file mode 100644 index 27721ed..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h +++ /dev/null @@ -1,193 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_spi.h -// -// TITLE: SPI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SPI_H__ -#define __F28004X_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SPI Individual Register Bit Definitions: - -struct SPICCR_BITS { // bits description - Uint16 SPICHAR:4; // 3:0 Character Length Control - Uint16 SPILBK:1; // 4 SPI Loopback - Uint16 HS_MODE:1; // 5 High Speed mode control - Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity - Uint16 SPISWRESET:1; // 7 SPI Software Reset - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPICCR_REG { - Uint16 all; - struct SPICCR_BITS bit; -}; - -struct SPICTL_BITS { // bits description - Uint16 SPIINTENA:1; // 0 SPI Interupt Enable - Uint16 TALK:1; // 1 Master/Slave Transmit Enable - Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control - Uint16 CLK_PHASE:1; // 3 SPI Clock Phase - Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union SPICTL_REG { - Uint16 all; - struct SPICTL_BITS bit; -}; - -struct SPISTS_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag - Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag - Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SPISTS_REG { - Uint16 all; - struct SPISTS_BITS bit; -}; - -struct SPIBRR_BITS { // bits description - Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union SPIBRR_REG { - Uint16 all; - struct SPIBRR_BITS bit; -}; - -struct SPIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear - Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFIFO:1; // 13 TXFIFO Reset - Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable - Uint16 SPIRST:1; // 15 SPI Reset -}; - -union SPIFFTX_REG { - Uint16 all; - struct SPIFFTX_BITS bit; -}; - -struct SPIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear - Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFIFORESET:1; // 13 RXFIFO Reset - Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear - Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag -}; - -union SPIFFRX_REG { - Uint16 all; - struct SPIFFRX_BITS bit; -}; - -struct SPIFFCT_BITS { // bits description - Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPIFFCT_REG { - Uint16 all; - struct SPIFFCT_BITS bit; -}; - -struct SPIPRI_BITS { // bits description - Uint16 TRIWIRE:1; // 0 3-wire mode select bit - Uint16 STEINV:1; // 1 SPISTE inversion bit - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 FREE:1; // 4 Free emulation mode - Uint16 SOFT:1; // 5 Soft emulation mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:9; // 15:7 Reserved -}; - -union SPIPRI_REG { - Uint16 all; - struct SPIPRI_BITS bit; -}; - -struct SPI_REGS { - union SPICCR_REG SPICCR; // SPI Configuration Control Register - union SPICTL_REG SPICTL; // SPI Operation Control Register - union SPISTS_REG SPISTS; // SPI Status Register - Uint16 rsvd1; // Reserved - union SPIBRR_REG SPIBRR; // SPI Baud Rate Register - Uint16 rsvd2; // Reserved - Uint16 SPIRXEMU; // SPI Emulation Buffer Register - Uint16 SPIRXBUF; // SPI Serial Input Buffer Register - Uint16 SPITXBUF; // SPI Serial Output Buffer Register - Uint16 SPIDAT; // SPI Serial Data Register - union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register - union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register - union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register - Uint16 rsvd3[2]; // Reserved - union SPIPRI_REG SPIPRI; // SPI Priority Control Register -}; - -//--------------------------------------------------------------------------- -// SPI External References & Function Declarations: -// -extern volatile struct SPI_REGS SpiaRegs; -extern volatile struct SPI_REGS SpibRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h deleted file mode 100644 index adbdf64..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h +++ /dev/null @@ -1,2062 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl.h -// -// TITLE: SYSCTRL Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SYSCTRL_H__ -#define __F28004X_SYSCTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SYSCTRL Individual Register Bit Definitions: - -struct PARTIDL_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 rsvd2:2; // 4:3 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 QUAL:2; // 7:6 Qualification Status - Uint16 PIN_COUNT:3; // 10:8 Device Pin Count - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 INSTASPIN:2; // 14:13 Instaspin feature set - Uint16 rsvd6:1; // 15 Reserved - Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB - Uint16 rsvd7:4; // 27:24 Reserved - Uint16 rsvd8:4; // 31:28 Reserved -}; - -union PARTIDL_REG { - Uint32 all; - struct PARTIDL_BITS bit; -}; - -struct PARTIDH_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:4; // 7:4 Reserved - Uint16 FAMILY:8; // 15:8 Device family - Uint16 PARTNO:8; // 23:16 Device part number - Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID -}; - -union PARTIDH_REG { - Uint32 all; - struct PARTIDH_BITS bit; -}; - -struct REVID_BITS { // bits description - Uint16 REVID:16; // 15:0 Device Revision ID. This is specific to the Device - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union REVID_REG { - Uint32 all; - struct REVID_BITS bit; -}; - -struct FUSEERR_BITS { // bits description - Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status - Uint16 ERR:1; // 5 Efuse Self Test Error Status - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FUSEERR_REG { - Uint32 all; - struct FUSEERR_BITS bit; -}; - -struct SOFTPRES0_BITS { // bits description - Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES0_REG { - Uint32 all; - struct SOFTPRES0_BITS bit; -}; - -struct SOFTPRES2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 software reset bit - Uint16 EPWM2:1; // 1 EPWM2 software reset bit - Uint16 EPWM3:1; // 2 EPWM3 software reset bit - Uint16 EPWM4:1; // 3 EPWM4 software reset bit - Uint16 EPWM5:1; // 4 EPWM5 software reset bit - Uint16 EPWM6:1; // 5 EPWM6 software reset bit - Uint16 EPWM7:1; // 6 EPWM7 software reset bit - Uint16 EPWM8:1; // 7 EPWM8 software reset bit - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union SOFTPRES2_REG { - Uint32 all; - struct SOFTPRES2_BITS bit; -}; - -struct SOFTPRES3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 software reset bit - Uint16 ECAP2:1; // 1 ECAP2 software reset bit - Uint16 ECAP3:1; // 2 ECAP3 software reset bit - Uint16 ECAP4:1; // 3 ECAP4 software reset bit - Uint16 ECAP5:1; // 4 ECAP5 software reset bit - Uint16 ECAP6:1; // 5 ECAP6 software reset bit - Uint16 ECAP7:1; // 6 ECAP7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES3_REG { - Uint32 all; - struct SOFTPRES3_BITS bit; -}; - -struct SOFTPRES4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 software reset bit - Uint16 EQEP2:1; // 1 EQEP2 software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES4_REG { - Uint32 all; - struct SOFTPRES4_BITS bit; -}; - -struct SOFTPRES6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint16 rsvd7:1; // 7 Reserved - Uint16 rsvd8:8; // 15:8 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union SOFTPRES6_REG { - Uint32 all; - struct SOFTPRES6_BITS bit; -}; - -struct SOFTPRES7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A software reset bit - Uint16 SCI_B:1; // 1 SCI_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES7_REG { - Uint32 all; - struct SOFTPRES7_BITS bit; -}; - -struct SOFTPRES8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A software reset bit - Uint16 SPI_B:1; // 1 SPI_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:1; // 16 Reserved - Uint16 rsvd5:1; // 17 Reserved - Uint16 rsvd6:14; // 31:18 Reserved -}; - -union SOFTPRES8_REG { - Uint32 all; - struct SOFTPRES8_BITS bit; -}; - -struct SOFTPRES9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES9_REG { - Uint32 all; - struct SOFTPRES9_BITS bit; -}; - -struct SOFTPRES10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A software reset bit - Uint16 CAN_B:1; // 1 CAN_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES10_REG { - Uint32 all; - struct SOFTPRES10_BITS bit; -}; - -struct SOFTPRES13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A software reset bit - Uint16 ADC_B:1; // 1 ADC_B software reset bit - Uint16 ADC_C:1; // 2 ADC_C software reset bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES13_REG { - Uint32 all; - struct SOFTPRES13_BITS bit; -}; - -struct SOFTPRES14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit - Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit - Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit - Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit - Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit - Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit - Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES14_REG { - Uint32 all; - struct SOFTPRES14_BITS bit; -}; - -struct SOFTPRES15_BITS { // bits description - Uint16 PGA1:1; // 0 PGA1 software reset bit - Uint16 PGA2:1; // 1 PGA2 software reset bit - Uint16 PGA3:1; // 2 PGA3 software reset bit - Uint16 PGA4:1; // 3 PGA4 software reset bit - Uint16 PGA5:1; // 4 PGA5 software reset bit - Uint16 PGA6:1; // 5 PGA6 software reset bit - Uint16 PGA7:1; // 6 PGA7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES15_REG { - Uint32 all; - struct SOFTPRES15_BITS bit; -}; - -struct SOFTPRES16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit - Uint16 rsvd6:1; // 18 Reserved - Uint16 rsvd7:1; // 19 Reserved - Uint16 rsvd8:12; // 31:20 Reserved -}; - -union SOFTPRES16_REG { - Uint32 all; - struct SOFTPRES16_BITS bit; -}; - -struct SOFTPRES19_BITS { // bits description - Uint16 LIN_A:1; // 0 LIN_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES19_REG { - Uint32 all; - struct SOFTPRES19_BITS bit; -}; - -struct SOFTPRES20_BITS { // bits description - Uint16 PMBUS_A:1; // 0 PMBUS_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES20_REG { - Uint32 all; - struct SOFTPRES20_BITS bit; -}; - -struct TAP_STATUS_BITS { // bits description - Uint16 TAP_STATE:16; // 15:0 Present TAP State - Uint16 rsvd1:15; // 30:16 Reserved - Uint16 DCON:1; // 31 Debugger Connect Indication -}; - -union TAP_STATUS_REG { - Uint32 all; - struct TAP_STATUS_BITS bit; -}; - -struct DEV_CFG_REGS { - Uint16 rsvd1[8]; // Reserved - union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number - union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number - union REVID_REG REVID; // Device Revision Number - Uint16 rsvd2[102]; // Reserved - union FUSEERR_REG FUSEERR; // e-Fuse error Status register - Uint16 rsvd3[12]; // Reserved - union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register - Uint16 rsvd4[2]; // Reserved - union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register - union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register - union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register - Uint16 rsvd5[2]; // Reserved - union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register - union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register - union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register - union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register - union SOFTPRES10_REG SOFTPRES10; // Peripheral Software Reset register - Uint16 rsvd6[4]; // Reserved - union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register - union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register - union SOFTPRES15_REG SOFTPRES15; // Peripheral Software Reset register - union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register - Uint16 rsvd7[4]; // Reserved - union SOFTPRES19_REG SOFTPRES19; // Peripheral Software Reset register - union SOFTPRES20_REG SOFTPRES20; // Peripheral Software Reset register - Uint16 rsvd8[132]; // Reserved - union TAP_STATUS_REG TAP_STATUS; // Status of JTAG State machine & Debugger Connect - Uint16 rsvd9[78]; // Reserved -}; - -struct CLKCFGLOCK1_BITS { // bits description - Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register - Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register - Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register - Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register - Uint16 rsvd7:1; // 12 Reserved - Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register - Uint16 rsvd8:1; // 14 Reserved - Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register - Uint16 XTALCR:1; // 16 Lock bit for XTALCR register - Uint16 rsvd9:15; // 31:17 Reserved -}; - -union CLKCFGLOCK1_REG { - Uint32 all; - struct CLKCFGLOCK1_BITS bit; -}; - -struct CLKSRCCTL1_BITS { // bits description - Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit - Uint16 rsvd2:1; // 4 Reserved - Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit - Uint16 rsvd3:10; // 15:6 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CLKSRCCTL1_REG { - Uint32 all; - struct CLKSRCCTL1_BITS bit; -}; - -struct CLKSRCCTL2_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit - Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union CLKSRCCTL2_REG { - Uint32 all; - struct CLKSRCCTL2_BITS bit; -}; - -struct CLKSRCCTL3_BITS { // bits description - Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLKSRCCTL3_REG { - Uint32 all; - struct CLKSRCCTL3_BITS bit; -}; - -struct SYSPLLCTL1_BITS { // bits description - Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit - Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLCTL1_REG { - Uint32 all; - struct SYSPLLCTL1_BITS bit; -}; - -struct SYSPLLMULT_BITS { // bits description - Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier - Uint16 rsvd1:1; // 7 Reserved - Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 ODIV:3; // 18:16 Output Clock Divider - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 rsvd4:6; // 29:24 Reserved - Uint16 rsvd5:2; // 31:30 Reserved -}; - -union SYSPLLMULT_REG { - Uint32 all; - struct SYSPLLMULT_BITS bit; -}; - -struct SYSPLLSTS_BITS { // bits description - Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit - Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLSTS_REG { - Uint32 all; - struct SYSPLLSTS_BITS bit; -}; - -struct SYSCLKDIVSEL_BITS { // bits description - Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSCLKDIVSEL_REG { - Uint32 all; - struct SYSCLKDIVSEL_BITS bit; -}; - -struct XCLKOUTDIVSEL_BITS { // bits description - Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XCLKOUTDIVSEL_REG { - Uint32 all; - struct XCLKOUTDIVSEL_BITS bit; -}; - -struct LOSPCP_BITS { // bits description - Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOSPCP_REG { - Uint32 all; - struct LOSPCP_BITS bit; -}; - -struct MCDCR_BITS { // bits description - Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit - Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit - Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit - Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MCDCR_REG { - Uint32 all; - struct MCDCR_BITS bit; -}; - -struct X1CNT_BITS { // bits description - Uint16 X1CNT:10; // 9:0 X1 Counter - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 CLR:1; // 16 X1 Counter Clear - Uint16 rsvd2:15; // 31:17 Reserved -}; - -union X1CNT_REG { - Uint32 all; - struct X1CNT_BITS bit; -}; - -struct XTALCR_BITS { // bits description - Uint16 OSCOFF:1; // 0 XTAL Oscillator powered-down - Uint16 SE:1; // 1 XTAL Oscilator in Single-Ended mode - Uint16 SWH:1; // 2 XTAL Oscilator Operation range - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XTALCR_REG { - Uint32 all; - struct XTALCR_BITS bit; -}; - -struct CLK_CFG_REGS { - Uint16 rsvd1[2]; // Reserved - union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers - Uint16 rsvd2[4]; // Reserved - union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 - union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 - union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 - union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 - Uint16 rsvd3[4]; // Reserved - union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register - union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register - Uint16 rsvd4[10]; // Reserved - union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register - Uint16 rsvd5[4]; // Reserved - union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register - Uint16 rsvd6[2]; // Reserved - union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar - union MCDCR_REG MCDCR; // Missing Clock Detect Control Register - union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock - union XTALCR_REG XTALCR; // XTAL Control Register - Uint16 rsvd7[2]; // Reserved -}; - -struct CPUSYSLOCK1_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register - Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register - Uint16 rsvd3:1; // 4 Reserved - Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register - Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register - Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register - Uint16 rsvd4:1; // 8 Reserved - Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register - Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register - Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register - Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register - Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register - Uint16 rsvd5:1; // 14 Reserved - Uint16 rsvd6:1; // 15 Reserved - Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register - Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register - Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register - Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register - Uint16 rsvd7:1; // 20 Reserved - Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register - Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register - Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register - Uint16 PCLKCR17:1; // 24 Lock bit for PCLKCR17 Register - Uint16 PCLKCR18:1; // 25 Lock bit for PCLKCR18 Register - Uint16 PCLKCR19:1; // 26 Lock bit for PCLKCR19 Register - Uint16 PCLKCR20:1; // 27 Lock bit for PCLKCR20 Register - Uint16 PCLKCR21:1; // 28 Lock bit for PCLKCR21 Register - Uint16 rsvd8:1; // 29 Reserved - Uint16 rsvd9:1; // 30 Reserved - Uint16 rsvd10:1; // 31 Reserved -}; - -union CPUSYSLOCK1_REG { - Uint32 all; - struct CPUSYSLOCK1_BITS bit; -}; - -struct PIEVERRADDR_BITS { // bits description - Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PIEVERRADDR_REG { - Uint32 all; - struct PIEVERRADDR_BITS bit; -}; - -struct PCLKCR0_BITS { // bits description - Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 DMA:1; // 2 DMA Clock Enable bit - Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit - Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit - Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit - Uint16 rsvd3:1; // 17 Reserved - Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync - Uint16 rsvd4:1; // 19 Reserved - Uint16 rsvd5:12; // 31:20 Reserved -}; - -union PCLKCR0_REG { - Uint32 all; - struct PCLKCR0_BITS bit; -}; - -struct PCLKCR2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit - Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit - Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit - Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit - Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit - Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit - Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit - Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union PCLKCR2_REG { - Uint32 all; - struct PCLKCR2_BITS bit; -}; - -struct PCLKCR3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit - Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit - Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit - Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit - Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit - Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit - Uint16 ECAP7:1; // 6 ECAP7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR3_REG { - Uint32 all; - struct PCLKCR3_BITS bit; -}; - -struct PCLKCR4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit - Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR4_REG { - Uint32 all; - struct PCLKCR4_BITS bit; -}; - -struct PCLKCR6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint16 rsvd7:1; // 7 Reserved - Uint16 rsvd8:8; // 15:8 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union PCLKCR6_REG { - Uint32 all; - struct PCLKCR6_BITS bit; -}; - -struct PCLKCR7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit - Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR7_REG { - Uint32 all; - struct PCLKCR7_BITS bit; -}; - -struct PCLKCR8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit - Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:1; // 16 Reserved - Uint16 rsvd5:1; // 17 Reserved - Uint16 rsvd6:14; // 31:18 Reserved -}; - -union PCLKCR8_REG { - Uint32 all; - struct PCLKCR8_BITS bit; -}; - -struct PCLKCR9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR9_REG { - Uint32 all; - struct PCLKCR9_BITS bit; -}; - -struct PCLKCR10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit - Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR10_REG { - Uint32 all; - struct PCLKCR10_BITS bit; -}; - -struct PCLKCR13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit - Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit - Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR13_REG { - Uint32 all; - struct PCLKCR13_BITS bit; -}; - -struct PCLKCR14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit - Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit - Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit - Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit - Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit - Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit - Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR14_REG { - Uint32 all; - struct PCLKCR14_BITS bit; -}; - -struct PCLKCR15_BITS { // bits description - Uint16 PGA1:1; // 0 PGA1 Clock Enable bit - Uint16 PGA2:1; // 1 PGA2 Clock Enable bit - Uint16 PGA3:1; // 2 PGA3 Clock Enable bit - Uint16 PGA4:1; // 3 PGA4 Clock Enable bit - Uint16 PGA5:1; // 4 PGA5 Clock Enable bit - Uint16 PGA6:1; // 5 PGA6 Clock Enable bit - Uint16 PGA7:1; // 6 PGA7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR15_REG { - Uint32 all; - struct PCLKCR15_BITS bit; -}; - -struct PCLKCR16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit - Uint16 rsvd6:1; // 18 Reserved - Uint16 rsvd7:1; // 19 Reserved - Uint16 rsvd8:12; // 31:20 Reserved -}; - -union PCLKCR16_REG { - Uint32 all; - struct PCLKCR16_BITS bit; -}; - -struct PCLKCR19_BITS { // bits description - Uint16 LIN_A:1; // 0 LIN_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union PCLKCR19_REG { - Uint32 all; - struct PCLKCR19_BITS bit; -}; - -struct PCLKCR20_BITS { // bits description - Uint16 PMBUS_A:1; // 0 PMBUS_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR20_REG { - Uint32 all; - struct PCLKCR20_BITS bit; -}; - -struct PCLKCR21_BITS { // bits description - Uint16 DCC_0:1; // 0 DCC_0 Clock Enable Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR21_REG { - Uint32 all; - struct PCLKCR21_BITS bit; -}; - -struct LPMCR_BITS { // bits description - Uint16 LPM:2; // 1:0 Low Power Mode setting - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 rsvd2:7; // 14:8 Reserved - Uint16 rsvd3:1; // 15 Reserved - Uint16 rsvd4:2; // 17:16 Reserved - Uint16 rsvd5:13; // 30:18 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union LPMCR_REG { - Uint32 all; - struct LPMCR_BITS bit; -}; - -struct GPIOLPMSEL0_BITS { // bits description - Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup - Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup - Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup - Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup - Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup - Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup - Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup - Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup - Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup - Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup - Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup - Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup - Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup - Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup - Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup - Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup - Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup - Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup - Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup - Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup - Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup - Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup - Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup - Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup - Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup - Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup - Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup - Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup - Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup - Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup - Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup - Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup -}; - -union GPIOLPMSEL0_REG { - Uint32 all; - struct GPIOLPMSEL0_BITS bit; -}; - -struct GPIOLPMSEL1_BITS { // bits description - Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup - Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup - Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup - Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup - Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup - Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup - Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup - Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup - Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup - Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup - Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup - Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup - Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup - Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup - Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup - Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup - Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup - Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup - Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup - Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup - Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup - Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup - Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup - Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup - Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup - Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup - Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup - Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup - Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup - Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup - Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup - Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup -}; - -union GPIOLPMSEL1_REG { - Uint32 all; - struct GPIOLPMSEL1_BITS bit; -}; - -struct TMR2CLKCTL_BITS { // bits description - Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit - Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TMR2CLKCTL_REG { - Uint32 all; - struct TMR2CLKCTL_BITS bit; -}; - -struct RESCCLR_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd5:7; // 15:9 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union RESCCLR_REG { - Uint32 all; - struct RESCCLR_BITS bit; -}; - -struct RESC_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd5:7; // 15:9 Reserved - Uint16 rsvd6:14; // 29:16 Reserved - Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status - Uint16 DCON:1; // 31 Debugger conntion status to C28x -}; - -union RESC_REG { - Uint32 all; - struct RESC_BITS bit; -}; - -struct CPU_SYS_REGS { - union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers - Uint16 rsvd1[8]; // Reserved - union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register - Uint16 rsvd2[22]; // Reserved - union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers - Uint16 rsvd3[2]; // Reserved - union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers - union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers - union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers - Uint16 rsvd4[2]; // Reserved - union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers - union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers - union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers - union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers - union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers - Uint16 rsvd5[4]; // Reserved - union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers - union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers - union PCLKCR15_REG PCLKCR15; // Peripheral Clock Gating Registers - union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers - Uint16 rsvd6[4]; // Reserved - union PCLKCR19_REG PCLKCR19; // Peripheral Clock Gating Registers - union PCLKCR20_REG PCLKCR20; // Peripheral Clock Gating Registers - union PCLKCR21_REG PCLKCR21; // Peripheral Clock Gating Registers - Uint16 rsvd7[40]; // Reserved - union LPMCR_REG LPMCR; // LPM Control Register - union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers - union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers - union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register - union RESCCLR_REG RESCCLR; // Reset Cause Clear Register - union RESC_REG RESC; // Reset Cause register -}; - -struct SCSR_BITS { // bits description - Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit - Uint16 WDENINT:1; // 1 WD Interrupt Enable - Uint16 WDINTS:1; // 2 WD Interrupt Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union SCSR_REG { - Uint16 all; - struct SCSR_BITS bit; -}; - -struct WDCNTR_BITS { // bits description - Uint16 WDCNTR:8; // 7:0 WD Counter - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDCNTR_REG { - Uint16 all; - struct WDCNTR_BITS bit; -}; - -struct WDKEY_BITS { // bits description - Uint16 WDKEY:8; // 7:0 Key to pet the watchdog timer. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDKEY_REG { - Uint16 all; - struct WDKEY_BITS bit; -}; - -struct WDCR_BITS { // bits description - Uint16 WDPS:3; // 2:0 WD Clock Prescalar - Uint16 WDCHK:3; // 5:3 WD Check Bits - Uint16 WDDIS:1; // 6 WD Disable - Uint16 rsvd1:1; // 7 Reserved - Uint16 WDPRECLKDIV:4; // 11:8 WD Pre Clock Divider - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union WDCR_REG { - Uint16 all; - struct WDCR_BITS bit; -}; - -struct WDWCR_BITS { // bits description - Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union WDWCR_REG { - Uint16 all; - struct WDWCR_BITS bit; -}; - -struct WD_REGS { - Uint16 rsvd1[34]; // Reserved - union SCSR_REG SCSR; // System Control & Status Register - union WDCNTR_REG WDCNTR; // Watchdog Counter Register - Uint16 rsvd2; // Reserved - union WDKEY_REG WDKEY; // Watchdog Reset Key Register - Uint16 rsvd3[3]; // Reserved - union WDCR_REG WDCR; // Watchdog Control Register - union WDWCR_REG WDWCR; // Watchdog Windowed Control Register -}; - -struct CLA1TASKSRCSELLOCK_BITS { // bits description - Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit - Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLA1TASKSRCSELLOCK_REG { - Uint32 all; - struct CLA1TASKSRCSELLOCK_BITS bit; -}; - -struct DMACHSRCSELLOCK_BITS { // bits description - Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit - Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DMACHSRCSELLOCK_REG { - Uint32 all; - struct DMACHSRCSELLOCK_BITS bit; -}; - -struct CLA1TASKSRCSEL1_BITS { // bits description - Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 - Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 - Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 - Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 -}; - -union CLA1TASKSRCSEL1_REG { - Uint32 all; - struct CLA1TASKSRCSEL1_BITS bit; -}; - -struct CLA1TASKSRCSEL2_BITS { // bits description - Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 - Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 - Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 - Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 -}; - -union CLA1TASKSRCSEL2_REG { - Uint32 all; - struct CLA1TASKSRCSEL2_BITS bit; -}; - -struct DMACHSRCSEL1_BITS { // bits description - Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA - Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA - Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA - Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA -}; - -union DMACHSRCSEL1_REG { - Uint32 all; - struct DMACHSRCSEL1_BITS bit; -}; - -struct DMACHSRCSEL2_BITS { // bits description - Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA - Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union DMACHSRCSEL2_REG { - Uint32 all; - struct DMACHSRCSEL2_BITS bit; -}; - -struct DMA_CLA_SRC_SEL_REGS { - union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register - Uint16 rsvd1[2]; // Reserved - union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register - union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 - union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 - Uint16 rsvd2[12]; // Reserved - union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 - union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 -}; - -struct ADCA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCA_AC_REG { - Uint32 all; - struct ADCA_AC_BITS bit; -}; - -struct ADCB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCB_AC_REG { - Uint32 all; - struct ADCB_AC_BITS bit; -}; - -struct ADCC_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCC_AC_REG { - Uint32 all; - struct ADCC_AC_BITS bit; -}; - -struct CMPSS1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS1_AC_REG { - Uint32 all; - struct CMPSS1_AC_BITS bit; -}; - -struct CMPSS2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS2_AC_REG { - Uint32 all; - struct CMPSS2_AC_BITS bit; -}; - -struct CMPSS3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS3_AC_REG { - Uint32 all; - struct CMPSS3_AC_BITS bit; -}; - -struct CMPSS4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS4_AC_REG { - Uint32 all; - struct CMPSS4_AC_BITS bit; -}; - -struct CMPSS5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS5_AC_REG { - Uint32 all; - struct CMPSS5_AC_BITS bit; -}; - -struct CMPSS6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS6_AC_REG { - Uint32 all; - struct CMPSS6_AC_BITS bit; -}; - -struct CMPSS7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS7_AC_REG { - Uint32 all; - struct CMPSS7_AC_BITS bit; -}; - -struct DACA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DACA_AC_REG { - Uint32 all; - struct DACA_AC_BITS bit; -}; - -struct DACB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DACB_AC_REG { - Uint32 all; - struct DACB_AC_BITS bit; -}; - -struct PGA1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA1_AC_REG { - Uint32 all; - struct PGA1_AC_BITS bit; -}; - -struct PGA2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA2_AC_REG { - Uint32 all; - struct PGA2_AC_BITS bit; -}; - -struct PGA3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA3_AC_REG { - Uint32 all; - struct PGA3_AC_BITS bit; -}; - -struct PGA4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA4_AC_REG { - Uint32 all; - struct PGA4_AC_BITS bit; -}; - -struct PGA5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA5_AC_REG { - Uint32 all; - struct PGA5_AC_BITS bit; -}; - -struct PGA6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA6_AC_REG { - Uint32 all; - struct PGA6_AC_BITS bit; -}; - -struct PGA7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA7_AC_REG { - Uint32 all; - struct PGA7_AC_BITS bit; -}; - -struct EPWM1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM1_AC_REG { - Uint32 all; - struct EPWM1_AC_BITS bit; -}; - -struct EPWM2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM2_AC_REG { - Uint32 all; - struct EPWM2_AC_BITS bit; -}; - -struct EPWM3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM3_AC_REG { - Uint32 all; - struct EPWM3_AC_BITS bit; -}; - -struct EPWM4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM4_AC_REG { - Uint32 all; - struct EPWM4_AC_BITS bit; -}; - -struct EPWM5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM5_AC_REG { - Uint32 all; - struct EPWM5_AC_BITS bit; -}; - -struct EPWM6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM6_AC_REG { - Uint32 all; - struct EPWM6_AC_BITS bit; -}; - -struct EPWM7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM7_AC_REG { - Uint32 all; - struct EPWM7_AC_BITS bit; -}; - -struct EPWM8_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM8_AC_REG { - Uint32 all; - struct EPWM8_AC_BITS bit; -}; - -struct EQEP1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EQEP1_AC_REG { - Uint32 all; - struct EQEP1_AC_BITS bit; -}; - -struct EQEP2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EQEP2_AC_REG { - Uint32 all; - struct EQEP2_AC_BITS bit; -}; - -struct ECAP1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP1_AC_REG { - Uint32 all; - struct ECAP1_AC_BITS bit; -}; - -struct ECAP2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP2_AC_REG { - Uint32 all; - struct ECAP2_AC_BITS bit; -}; - -struct ECAP3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP3_AC_REG { - Uint32 all; - struct ECAP3_AC_BITS bit; -}; - -struct ECAP4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP4_AC_REG { - Uint32 all; - struct ECAP4_AC_BITS bit; -}; - -struct ECAP5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP5_AC_REG { - Uint32 all; - struct ECAP5_AC_BITS bit; -}; - -struct ECAP6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP6_AC_REG { - Uint32 all; - struct ECAP6_AC_BITS bit; -}; - -struct ECAP7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP7_AC_REG { - Uint32 all; - struct ECAP7_AC_BITS bit; -}; - -struct SDFM1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SDFM1_AC_REG { - Uint32 all; - struct SDFM1_AC_BITS bit; -}; - -struct CLB1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB1_AC_REG { - Uint32 all; - struct CLB1_AC_BITS bit; -}; - -struct CLB2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB2_AC_REG { - Uint32 all; - struct CLB2_AC_BITS bit; -}; - -struct CLB3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB3_AC_REG { - Uint32 all; - struct CLB3_AC_BITS bit; -}; - -struct CLB4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB4_AC_REG { - Uint32 all; - struct CLB4_AC_BITS bit; -}; - -struct CLA1PROMCRC_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLA1PROMCRC_AC_REG { - Uint32 all; - struct CLA1PROMCRC_AC_BITS bit; -}; - -struct SPIA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SPIA_AC_REG { - Uint32 all; - struct SPIA_AC_BITS bit; -}; - -struct SPIB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SPIB_AC_REG { - Uint32 all; - struct SPIB_AC_BITS bit; -}; - -struct PMBUS_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBUS_A_AC_REG { - Uint32 all; - struct PMBUS_A_AC_BITS bit; -}; - -struct LIN_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LIN_A_AC_REG { - Uint32 all; - struct LIN_A_AC_BITS bit; -}; - -struct DCANA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DCANA_AC_REG { - Uint32 all; - struct DCANA_AC_BITS bit; -}; - -struct DCANB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DCANB_AC_REG { - Uint32 all; - struct DCANB_AC_BITS bit; -}; - -struct FSIATX_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FSIATX_AC_REG { - Uint32 all; - struct FSIATX_AC_BITS bit; -}; - -struct FSIARX_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FSIARX_AC_REG { - Uint32 all; - struct FSIARX_AC_BITS bit; -}; - -struct HRPWM_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRPWM_A_AC_REG { - Uint32 all; - struct HRPWM_A_AC_BITS bit; -}; - -struct PERIPH_AC_LOCK_BITS { // bits description - Uint16 LOCK_AC_WR:1; // 0 Lock control for Access control registers write. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PERIPH_AC_LOCK_REG { - Uint32 all; - struct PERIPH_AC_LOCK_BITS bit; -}; - -struct PERIPH_AC_REGS { - union ADCA_AC_REG ADCA_AC; // ADCA Master Access Control Register - union ADCB_AC_REG ADCB_AC; // ADCB Master Access Control Register - union ADCC_AC_REG ADCC_AC; // ADCC Master Access Control Register - Uint16 rsvd1[10]; // Reserved - union CMPSS1_AC_REG CMPSS1_AC; // CMPSS1 Master Access Control Register - union CMPSS2_AC_REG CMPSS2_AC; // CMPSS2 Master Access Control Register - union CMPSS3_AC_REG CMPSS3_AC; // CMPSS3 Master Access Control Register - union CMPSS4_AC_REG CMPSS4_AC; // CMPSS4 Master Access Control Register - union CMPSS5_AC_REG CMPSS5_AC; // CMPSS5 Master Access Control Register - union CMPSS6_AC_REG CMPSS6_AC; // CMPSS6 Master Access Control Register - union CMPSS7_AC_REG CMPSS7_AC; // CMPSS7 Master Access Control Register - Uint16 rsvd2[10]; // Reserved - union DACA_AC_REG DACA_AC; // DACA Master Access Control Register - union DACB_AC_REG DACB_AC; // DACB Master Access Control Register - Uint16 rsvd3[12]; // Reserved - union PGA1_AC_REG PGA1_AC; // PGAA Master Access Control Register - union PGA2_AC_REG PGA2_AC; // PGAB Master Access Control Register - union PGA3_AC_REG PGA3_AC; // PGAC Master Access Control Register - union PGA4_AC_REG PGA4_AC; // PGAD Master Access Control Register - union PGA5_AC_REG PGA5_AC; // PGAE Master Access Control Register - union PGA6_AC_REG PGA6_AC; // PGAF Master Access Control Register - union PGA7_AC_REG PGA7_AC; // PGAG Master Access Control Register - Uint16 rsvd4[2]; // Reserved - union EPWM1_AC_REG EPWM1_AC; // EPWM1 Master Access Control Register - union EPWM2_AC_REG EPWM2_AC; // EPWM2 Master Access Control Register - union EPWM3_AC_REG EPWM3_AC; // EPWM3 Master Access Control Register - union EPWM4_AC_REG EPWM4_AC; // EPWM4 Master Access Control Register - union EPWM5_AC_REG EPWM5_AC; // EPWM5 Master Access Control Register - union EPWM6_AC_REG EPWM6_AC; // EPWM6 Master Access Control Register - union EPWM7_AC_REG EPWM7_AC; // EPWM7 Master Access Control Register - union EPWM8_AC_REG EPWM8_AC; // EPWM8 Master Access Control Register - Uint16 rsvd5[24]; // Reserved - union EQEP1_AC_REG EQEP1_AC; // EQEP1 Master Access Control Register - union EQEP2_AC_REG EQEP2_AC; // EQEP2 Master Access Control Register - Uint16 rsvd6[12]; // Reserved - union ECAP1_AC_REG ECAP1_AC; // ECAP1 Master Access Control Register - union ECAP2_AC_REG ECAP2_AC; // ECAP2 Master Access Control Register - union ECAP3_AC_REG ECAP3_AC; // ECAP3 Master Access Control Register - union ECAP4_AC_REG ECAP4_AC; // ECAP4 Master Access Control Register - union ECAP5_AC_REG ECAP5_AC; // ECAP5 Master Access Control Register - union ECAP6_AC_REG ECAP6_AC; // ECAP6 Master Access Control Register - union ECAP7_AC_REG ECAP7_AC; // ECAP7 Master Access Control Register - Uint16 rsvd7[26]; // Reserved - union SDFM1_AC_REG SDFM1_AC; // SDFM1 Master Access Control Register - Uint16 rsvd8[6]; // Reserved - union CLB1_AC_REG CLB1_AC; // CLB1 Master Access Control Register - union CLB2_AC_REG CLB2_AC; // CLB2 Master Access Control Register - union CLB3_AC_REG CLB3_AC; // CLB3 Master Access Control Register - union CLB4_AC_REG CLB4_AC; // CLB4 Master Access Control Register - Uint16 rsvd9[8]; // Reserved - union CLA1PROMCRC_AC_REG CLA1PROMCRC_AC; // CLA1PROMCRC Master Access Control Register - Uint16 rsvd10[78]; // Reserved - union SPIA_AC_REG SPIA_AC; // SPIA Master Access Control Register - union SPIB_AC_REG SPIB_AC; // SPIB Master Access Control Register - Uint16 rsvd11[28]; // Reserved - union PMBUS_A_AC_REG PMBUS_A_AC; // PMBUSA Master Access Control Register - Uint16 rsvd12[6]; // Reserved - union LIN_A_AC_REG LIN_A_AC; // LINA Master Access Control Register - Uint16 rsvd13[6]; // Reserved - union DCANA_AC_REG DCANA_AC; // DCANA Master Access Control Register - union DCANB_AC_REG DCANB_AC; // DCANB Master Access Control Register - Uint16 rsvd14[20]; // Reserved - union FSIATX_AC_REG FSIATX_AC; // FSIA Master Access Control Register - union FSIARX_AC_REG FSIARX_AC; // FSIB Master Access Control Register - Uint16 rsvd15[78]; // Reserved - union HRPWM_A_AC_REG HRPWM_A_AC; // HRPWM Master Access Control Register - Uint16 rsvd16[82]; // Reserved - union PERIPH_AC_LOCK_REG PERIPH_AC_LOCK; // Lock Register to stop Write access to peripheral Access register. -}; - -struct SYNCSELECT_BITS { // bits description - Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 - Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 - Uint16 rsvd1:3; // 8:6 Reserved - Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 - Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 - Uint32 ECAP6SYNCIN:3; // 17:15 Selects Sync Input Source for ECAP6 - Uint16 rsvd2:9; // 26:18 Reserved - Uint16 SYNCOUT:2; // 28:27 Select Syncout Source - Uint16 EPWM1SYNCIN:3; // 31:29 Selects Sync Input Source for EPWM1 -}; - -union SYNCSELECT_REG { - Uint32 all; - struct SYNCSELECT_BITS bit; -}; - -struct ADCSOCOUTSELECT_BITS { // bits description - Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAOn - Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAOn - Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAOn - Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAOn - Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAOn - Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAOn - Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAOn - Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAOn - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:4; // 15:12 Reserved - Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBOn - Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBOn - Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBOn - Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBOn - Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBOn - Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBOn - Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBOn - Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBOn - Uint16 rsvd6:1; // 24 Reserved - Uint16 rsvd7:1; // 25 Reserved - Uint16 rsvd8:1; // 26 Reserved - Uint16 rsvd9:1; // 27 Reserved - Uint16 rsvd10:4; // 31:28 Reserved -}; - -union ADCSOCOUTSELECT_REG { - Uint32 all; - struct ADCSOCOUTSELECT_BITS bit; -}; - -struct SYNCSOCLOCK_BITS { // bits description - Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit - Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYNCSOCLOCK_REG { - Uint32 all; - struct SYNCSOCLOCK_BITS bit; -}; - -struct SYNC_SOC_REGS { - union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register - union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADCSOC Select Register - union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register -}; - -//--------------------------------------------------------------------------- -// SYSCTRL External References & Function Declarations: -// -extern volatile struct WD_REGS WdRegs; -extern volatile struct SYNC_SOC_REGS SyncSocRegs; -extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; -extern volatile struct DEV_CFG_REGS DevCfgRegs; -extern volatile struct CLK_CFG_REGS ClkCfgRegs; -extern volatile struct CPU_SYS_REGS CpuSysRegs; -extern volatile struct PERIPH_AC_REGS SysPeriphAcRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h deleted file mode 100644 index e3cdff0..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h +++ /dev/null @@ -1,372 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_xbar.h -// -// TITLE: XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_XBAR_H__ -#define __F28004X_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XBAR Individual Register Bit Definitions: - -struct XBARFLG1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal -}; - -union XBARFLG1_REG { - Uint32 all; - struct XBARFLG1_BITS bit; -}; - -struct XBARFLG2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal - Uint16 ADCSOCA:1; // 6 Input Flag for ADCSOCA Signal - Uint16 ADCSOCB:1; // 7 Input Flag for ADCSOCB Signal - Uint16 INPUT7:1; // 8 Input Flag for INPUT7 Signal - Uint16 INPUT8:1; // 9 Input Flag for INPUT8 Signal - Uint16 INPUT9:1; // 10 Input Flag for INPUT9 Signal - Uint16 INPUT10:1; // 11 Input Flag for INPUT10\ Signal - Uint16 INPUT11:1; // 12 Input Flag for INPUT11 Signal - Uint16 INPUT12:1; // 13 Input Flag for INPUT12 Signal - Uint16 INPUT13:1; // 14 Input Flag for INPUT13 Signal - Uint16 INPUT14:1; // 15 Input Flag for INPUT14 Signal - Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal -}; - -union XBARFLG2_REG { - Uint32 all; - struct XBARFLG2_BITS bit; -}; - -struct XBARFLG3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 rsvd4:1; // 6 Reserved - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:1; // 17 Reserved - Uint16 rsvd8:1; // 18 Reserved - Uint16 rsvd9:1; // 19 Reserved - Uint16 rsvd10:1; // 20 Reserved - Uint16 rsvd11:1; // 21 Reserved - Uint16 rsvd12:1; // 22 Reserved - Uint16 ECAP7_OUT:1; // 23 Input Flag for ECAP7.OUT Signal - Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag for SD1FLT1.COMPZ Signal - Uint16 SD1FLT1_DRINT:1; // 25 Input Flag for SD1FLT1.DRINT Signal - Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag for SD1FLT2.COMPZ Signal - Uint16 SD1FLT2_DRINT:1; // 27 Input Flag for SD1FLT2.DRINT Signal - Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag for SD1FLT3.COMPZ Signal - Uint16 SD1FLT3_DRINT:1; // 29 Input Flag for SD1FLT3.DRINT Signal - Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag for SD1FLT4.COMPZ Signal - Uint16 SD1FLT4_DRINT:1; // 31 Input Flag for SD1FLT4.DRINT Signal -}; - -union XBARFLG3_REG { - Uint32 all; - struct XBARFLG3_BITS bit; -}; - -struct XBARFLG4_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:8; // 15:8 Reserved - Uint16 rsvd10:1; // 16 Reserved - Uint16 rsvd11:1; // 17 Reserved - Uint16 rsvd12:1; // 18 Reserved - Uint16 rsvd13:1; // 19 Reserved - Uint16 rsvd14:1; // 20 Reserved - Uint16 rsvd15:1; // 21 Reserved - Uint16 rsvd16:1; // 22 Reserved - Uint16 rsvd17:1; // 23 Reserved - Uint16 rsvd18:7; // 30:24 Reserved - Uint16 CLAHALT:1; // 31 Input Flag for CLAHALT Signal -}; - -union XBARFLG4_REG { - Uint32 all; - struct XBARFLG4_BITS bit; -}; - -struct XBARCLR1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal -}; - -union XBARCLR1_REG { - Uint32 all; - struct XBARCLR1_BITS bit; -}; - -struct XBARCLR2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag Clear for INPUT6 Signal - Uint16 ADCSOCA:1; // 6 Input Flag Clear for ADCSOCA Signal - Uint16 ADCSOCB:1; // 7 Input Flag Clear for ADCSOCB Signal - Uint16 INPUT7:1; // 8 Input Flag Clear for INPUT7 Signal - Uint16 INPUT8:1; // 9 Input Flag Clear for INPUT8 Signal - Uint16 INPUT9:1; // 10 Input Flag Clear for INPUT9 Signal - Uint16 INPUT10:1; // 11 Input Flag Clear for INPUT10 Signal - Uint16 INPUT11:1; // 12 Input Flag Clear for INPUT11 Signal - Uint16 INPUT12:1; // 13 Input Flag Clear for INPUT12 Signal - Uint16 INPUT13:1; // 14 Input Flag Clear for INPUT13 Signal - Uint16 INPUT14:1; // 15 Input Flag Clear for INPUT14 Signal - Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal -}; - -union XBARCLR2_REG { - Uint32 all; - struct XBARCLR2_BITS bit; -}; - -struct XBARCLR3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 rsvd4:1; // 6 Reserved - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:1; // 17 Reserved - Uint16 rsvd8:1; // 18 Reserved - Uint16 rsvd9:1; // 19 Reserved - Uint16 rsvd10:1; // 20 Reserved - Uint16 rsvd11:1; // 21 Reserved - Uint16 rsvd12:1; // 22 Reserved - Uint16 ECAP7_OUT:1; // 23 Input Flag clear for ECAP7.OUT Signal - Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag clear for SD1FLT1.COMPZ Signal - Uint16 SD1FLT1_DRINT:1; // 25 Input Flag clear for SD1FLT1.DRINT Signal - Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag clear for SD1FLT2.COMPZ Signal - Uint16 SD1FLT2_DRINT:1; // 27 Input Flag clear for SD1FLT2.DRINT Signal - Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag clear for SD1FLT3.COMPZ Signal - Uint16 SD1FLT3_DRINT:1; // 29 Input Flag clear for SD1FLT3.DRINT Signal - Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag clear for SD1FLT4.COMPZ Signal - Uint16 SD1FLT4_DRINT:1; // 31 Input Flag clear for SD1FLT4.DRINT Signal -}; - -union XBARCLR3_REG { - Uint32 all; - struct XBARCLR3_BITS bit; -}; - -struct XBARCLR4_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:8; // 15:8 Reserved - Uint16 rsvd10:1; // 16 Reserved - Uint16 rsvd11:1; // 17 Reserved - Uint16 rsvd12:1; // 18 Reserved - Uint16 rsvd13:1; // 19 Reserved - Uint16 rsvd14:1; // 20 Reserved - Uint16 rsvd15:1; // 21 Reserved - Uint16 rsvd16:1; // 22 Reserved - Uint16 rsvd17:1; // 23 Reserved - Uint16 rsvd18:7; // 30:24 Reserved - Uint16 CLAHALT:1; // 31 Input Flag clear for CLAHALT Signal -}; - -union XBARCLR4_REG { - Uint32 all; - struct XBARCLR4_BITS bit; -}; - -struct XBAR_REGS { - union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 - union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 - union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 - union XBARFLG4_REG XBARFLG4; // X-Bar Input Flag Register 4 - union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 - union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 - union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 - union XBARCLR4_REG XBARCLR4; // X-Bar Input Flag Clear Register 4 - Uint16 rsvd1[16]; // Reserved -}; - -//--------------------------------------------------------------------------- -// XBAR External References & Function Declarations: -// -extern volatile struct XBAR_REGS XbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h deleted file mode 100644 index 15fd43b..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h +++ /dev/null @@ -1,138 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_xint.h -// -// TITLE: XINT Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_XINT_H__ -#define __F28004X_XINT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XINT Individual Register Bit Definitions: - -struct XINT1CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT1 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT1 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT1CR_REG { - Uint16 all; - struct XINT1CR_BITS bit; -}; - -struct XINT2CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT2 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT2 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT2CR_REG { - Uint16 all; - struct XINT2CR_BITS bit; -}; - -struct XINT3CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT3 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT3 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT3CR_REG { - Uint16 all; - struct XINT3CR_BITS bit; -}; - -struct XINT4CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT4 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT4 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT4CR_REG { - Uint16 all; - struct XINT4CR_BITS bit; -}; - -struct XINT5CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT5 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT5 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT5CR_REG { - Uint16 all; - struct XINT5CR_BITS bit; -}; - -struct XINT_REGS { - union XINT1CR_REG XINT1CR; // XINT1 configuration register - union XINT2CR_REG XINT2CR; // XINT2 configuration register - union XINT3CR_REG XINT3CR; // XINT3 configuration register - union XINT4CR_REG XINT4CR; // XINT4 configuration register - union XINT5CR_REG XINT5CR; // XINT5 configuration register - Uint16 rsvd1[3]; // Reserved - Uint16 XINT1CTR; // XINT1 counter register - Uint16 XINT2CTR; // XINT2 counter register - Uint16 XINT3CTR; // XINT3 counter register -}; - -//--------------------------------------------------------------------------- -// XINT External References & Function Declarations: -// -extern volatile struct XINT_REGS XintRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c b/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c deleted file mode 100644 index 7c862ee..0000000 --- a/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c +++ /dev/null @@ -1,861 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_globalvariabledefs.c -// -// TITLE: F28004x Global Variables and Data Section Pragmas. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#include "f28004x_device.h" // F28004x Headerfile Include File - -//--------------------------------------------------------------------------- -// Define Global Peripheral Variables: -// -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaResultFile") -#else -#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcaResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbResultFile") -#else -#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcbResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccResultFile") -#else -#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdccResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaRegsFile") -#else -#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); -#endif -volatile struct ADC_REGS AdcaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbRegsFile") -#else -#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); -#endif -volatile struct ADC_REGS AdcbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccRegsFile") -#else -#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); -#endif -volatile struct ADC_REGS AdccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AnalogSubsysRegsFile") -#else -#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); -#endif -volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanaRegsFile") -#else -#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); -#endif -volatile struct CAN_REGS CanaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanbRegsFile") -#else -#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); -#endif -volatile struct CAN_REGS CanbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1RegsFile") -#else -#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); -#endif -volatile struct CLA_REGS Cla1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1SoftIntRegsFile") -#else -#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); -#endif -volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClaPromCrc0RegsFile") -#else -#pragma DATA_SECTION(ClaPromCrc0Regs,"ClaPromCrc0RegsFile"); -#endif -volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss1RegsFile") -#else -#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss2RegsFile") -#else -#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss3RegsFile") -#else -#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss4RegsFile") -#else -#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss5RegsFile") -#else -#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss6RegsFile") -#else -#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss7RegsFile") -#else -#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer0RegsFile") -#else -#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer1RegsFile") -#else -#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer2RegsFile") -#else -#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacaRegsFile") -#else -#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); -#endif -volatile struct DAC_REGS DacaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacbRegsFile") -#else -#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); -#endif -volatile struct DAC_REGS DacbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Dcc0RegsFile") -#else -#pragma DATA_SECTION(Dcc0Regs,"Dcc0RegsFile"); -#endif -volatile struct DCC_REGS Dcc0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank0Z1RegsFile") -#else -#pragma DATA_SECTION(DcsmBank0Z1Regs,"DcsmBank0Z1RegsFile"); -#endif -volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank0Z2RegsFile") -#else -#pragma DATA_SECTION(DcsmBank0Z2Regs,"DcsmBank0Z2RegsFile"); -#endif -volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank1Z1RegsFile") -#else -#pragma DATA_SECTION(DcsmBank1Z1Regs,"DcsmBank1Z1RegsFile"); -#endif -volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank1Z2RegsFile") -#else -#pragma DATA_SECTION(DcsmBank1Z2Regs,"DcsmBank1Z2RegsFile"); -#endif -volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmCommonRegsFile") -#else -#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); -#endif -volatile struct DCSM_COMMON_REGS DcsmCommonRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaRegsFile") -#else -#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); -#endif -volatile struct DMA_REGS DmaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap1RegsFile") -#else -#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); -#endif -volatile struct ECAP_REGS ECap1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap2RegsFile") -#else -#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); -#endif -volatile struct ECAP_REGS ECap2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap3RegsFile") -#else -#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); -#endif -volatile struct ECAP_REGS ECap3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap4RegsFile") -#else -#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); -#endif -volatile struct ECAP_REGS ECap4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap5RegsFile") -#else -#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); -#endif -volatile struct ECAP_REGS ECap5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap6RegsFile") -#else -#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); -#endif -volatile struct ECAP_REGS ECap6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap7RegsFile") -#else -#pragma DATA_SECTION(ECap7Regs,"ECap7RegsFile"); -#endif -volatile struct ECAP_REGS ECap7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga1RegsFile") -#else -#pragma DATA_SECTION(Pga1Regs,"Pga1RegsFile"); -#endif -volatile struct PGA_REGS Pga1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga2RegsFile") -#else -#pragma DATA_SECTION(Pga2Regs,"Pga2RegsFile"); -#endif -volatile struct PGA_REGS Pga2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga3RegsFile") -#else -#pragma DATA_SECTION(Pga3Regs,"Pga3RegsFile"); -#endif -volatile struct PGA_REGS Pga3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga4RegsFile") -#else -#pragma DATA_SECTION(Pga4Regs,"Pga4RegsFile"); -#endif -volatile struct PGA_REGS Pga4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga5RegsFile") -#else -#pragma DATA_SECTION(Pga5Regs,"Pga5RegsFile"); -#endif -volatile struct PGA_REGS Pga5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga6RegsFile") -#else -#pragma DATA_SECTION(Pga6Regs,"Pga6RegsFile"); -#endif -volatile struct PGA_REGS Pga6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga7RegsFile") -#else -#pragma DATA_SECTION(Pga7Regs,"Pga7RegsFile"); -#endif -volatile struct PGA_REGS Pga7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm1RegsFile") -#else -#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); -#endif -volatile struct EPWM_REGS EPwm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm2RegsFile") -#else -#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); -#endif -volatile struct EPWM_REGS EPwm2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm3RegsFile") -#else -#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); -#endif -volatile struct EPWM_REGS EPwm3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm4RegsFile") -#else -#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); -#endif -volatile struct EPWM_REGS EPwm4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm5RegsFile") -#else -#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); -#endif -volatile struct EPWM_REGS EPwm5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm6RegsFile") -#else -#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); -#endif -volatile struct EPWM_REGS EPwm6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm7RegsFile") -#else -#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); -#endif -volatile struct EPWM_REGS EPwm7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm8RegsFile") -#else -#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); -#endif -volatile struct EPWM_REGS EPwm8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwmXbarRegsFile") -#else -#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); -#endif -volatile struct EPWM_XBAR_REGS EPwmXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep1RegsFile") -#else -#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); -#endif -volatile struct EQEP_REGS EQep1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep2RegsFile") -#else -#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); -#endif -volatile struct EQEP_REGS EQep2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0CtrlRegsFile") -#else -#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); -#endif -volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0EccRegsFile") -#else -#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); -#endif -volatile struct FLASH_ECC_REGS Flash0EccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("FsiTxaRegsFile") -#else -#pragma DATA_SECTION(FsiTxaRegs,"FsiTxaRegsFile"); -#endif -volatile struct FSI_TX_REGS FsiTxaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("FsiRxaRegsFile") -#else -#pragma DATA_SECTION(FsiRxaRegs,"FsiRxaRegsFile"); -#endif -volatile struct FSI_RX_REGS FsiRxaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioCtrlRegsFile") -#else -#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); -#endif -volatile struct GPIO_CTRL_REGS GpioCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioDataRegsFile") -#else -#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); -#endif -volatile struct GPIO_DATA_REGS GpioDataRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XbarRegsFile") -#else -#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); -#endif -volatile struct XBAR_REGS XbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("I2caRegsFile") -#else -#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); -#endif -volatile struct I2C_REGS I2caRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("InputXbarRegsFile") -#else -#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); -#endif -volatile struct INPUT_XBAR_REGS InputXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("LinaRegsFile") -#else -#pragma DATA_SECTION(LinaRegs,"LinaRegsFile"); -#endif -volatile struct LIN_REGS LinaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("LinbRegsFile") -#else -#pragma DATA_SECTION(LinbRegs,"LinbRegsFile"); -#endif -volatile struct LIN_REGS LinbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemCfgRegsFile") -#else -#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); -#endif -volatile struct MEM_CFG_REGS MemCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AccessProtectionRegsFile") -#else -#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); -#endif -volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemoryErrorRegsFile") -#else -#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); -#endif -volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("NmiIntruptRegsFile") -#else -#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); -#endif -volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("OutputXbarRegsFile") -#else -#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); -#endif -volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieCtrlRegsFile") -#else -#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); -#endif -volatile struct PIE_CTRL_REGS PieCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieVectTableFile") -#else -#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); -#endif -volatile struct PIE_VECT_TABLE PieVectTable; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PmbusaRegsFile") -#else -#pragma DATA_SECTION(PmbusaRegs,"PmbusaRegsFile"); -#endif -volatile struct PMBUS_REGS PmbusaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SciaRegsFile") -#else -#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); -#endif -volatile struct SCI_REGS SciaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ScibRegsFile") -#else -#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); -#endif -volatile struct SCI_REGS ScibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Sdfm1RegsFile") -#else -#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); -#endif -volatile struct SDFM_REGS Sdfm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpiaRegsFile") -#else -#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); -#endif -volatile struct SPI_REGS SpiaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpibRegsFile") -#else -#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); -#endif -volatile struct SPI_REGS SpibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("WdRegsFile") -#else -#pragma DATA_SECTION(WdRegs,"WdRegsFile"); -#endif -volatile struct WD_REGS WdRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaClaSrcSelRegsFile") -#else -#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); -#endif -volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DevCfgRegsFile") -#else -#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); -#endif -volatile struct DEV_CFG_REGS DevCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClkCfgRegsFile") -#else -#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); -#endif -volatile struct CLK_CFG_REGS ClkCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuSysRegsFile") -#else -#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); -#endif -volatile struct CPU_SYS_REGS CpuSysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SysPeriphAcRegsFile") -#else -#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); -#endif -volatile struct PERIPH_AC_REGS SysPeriphAcRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugGlobalRegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugGlobalRegs,"EnhancedDebugGlobalRegsFile"); -#endif -volatile struct ERAD_GLOBAL_REGS EnhancedDebugGlobalRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP1RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP1Regs,"EnhancedDebugHWBP1RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP2RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP2Regs,"EnhancedDebugHWBP2RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP3RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP3Regs,"EnhancedDebugHWBP3RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP4RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP4Regs,"EnhancedDebugHWBP4RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP5RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP5Regs,"EnhancedDebugHWBP5RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP6RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP6Regs,"EnhancedDebugHWBP6RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP7RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP7Regs,"EnhancedDebugHWBP7RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP8RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP8Regs,"EnhancedDebugHWBP8RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter1RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter1Regs,"EnhancedDebugCounter1RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter2RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter2Regs,"EnhancedDebugCounter2RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter3RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter3Regs,"EnhancedDebugCounter3RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter4RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter4Regs,"EnhancedDebugCounter4RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SyncSocRegsFile") -#else -#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); -#endif -volatile struct SYNC_SOC_REGS SyncSocRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XintRegsFile") -#else -#pragma DATA_SECTION(XintRegs,"XintRegsFile"); -#endif -volatile struct XINT_REGS XintRegs; - - - -//=========================================================================== -// End of file. -//=========================================================================== - diff --git a/els-f280049c/launchxl_ex1_sci_io.c b/els-f280049c/launchxl_ex1_sci_io.c new file mode 100644 index 0000000..4f67a39 --- /dev/null +++ b/els-f280049c/launchxl_ex1_sci_io.c @@ -0,0 +1,284 @@ +//############################################################################# +// +// FILE: launchxl_ex1_sci_io.c +// +// TITLE: Contains the various functions related to the serial +// communications interface (SCI) object +// +//############################################################################# +// $TI Release: F28004x Support Library v1.10.00.00 $ +// $Release Date: Tue May 26 17:06:03 IST 2020 $ +// $Copyright: +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include +#include +#include +#include + +#include "F28x_Project.h" +#include "launchxl_ex1_sci_io.h" + +// +// Defines +// + +// +// Globals +// +uint16_t deviceOpen = 0; +uint16_t deviceOpenB = 0; + +// +// Functions +// + +// +// SCI_open - +// +int SCI_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpen) + { + return (-1); + } + else + { + deviceOpen = 1; + return (1); + } +} + +// +// SCI_close - +// +int SCI_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpen)) + { + return (-1); + } + else + { + deviceOpen = 0; + return (0); + } +} + +// +// SCI_read - +// +int SCI_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = SciaRegs.SCIRXBUF.all; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - +// +int SCI_write(int dev_fd, const char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(!SciaRegs.SCICTL2.bit.TXRDY); + SciaRegs.SCITXBUF.all = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - +// +off_t SCI_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - +// +int SCI_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - +// +int SCI_rename(const char * old_name, const char * new_name) +{ + return (0); +} + + + + + + +// KVV +// +// SCI_open - +// +int SCIB_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpenB) + { + return (-1); + } + else + { + deviceOpenB = 1; + return (1); + } +} + +// +// SCI_close - +// +int SCIB_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpenB)) + { + return (-1); + } + else + { + deviceOpenB = 0; + return (0); + } +} + +// +// SCI_read - +// +int SCIB_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && ScibRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = ScibRegs.SCIRXBUF.all; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - +// +int SCIB_write(int dev_fd, const char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(!ScibRegs.SCICTL2.bit.TXRDY); + ScibRegs.SCITXBUF.all = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - +// +off_t SCIB_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - +// +int SCIB_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - +// +int SCIB_rename(const char * old_name, const char * new_name) +{ + return (0); +} + +// +// End of File +// + diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h b/els-f280049c/launchxl_ex1_sci_io.h similarity index 59% rename from els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h rename to els-f280049c/launchxl_ex1_sci_io.h index 4565488..bd3bab0 100644 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h +++ b/els-f280049c/launchxl_ex1_sci_io.h @@ -1,14 +1,18 @@ -//########################################################################### +#ifndef _SCI_IO_H_ +#define _SCI_IO_H_ + +//############################################################################# // -// FILE: f28004x_adc_defines.h +// FILE: launchxl_ex1_sci_io.h // -// TITLE: #defines used in ADC examples +// TITLE: Contains public interface to various functions related +// to the serial communications interface (SCI) object // -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ +//############################################################################# +// $TI Release: F28004x Support Library v1.10.00.00 $ +// $Release Date: Tue May 26 17:06:03 IST 2020 $ // $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -38,46 +42,44 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ -//########################################################################### - -#ifndef F28004X_ADC_DEFINES_H -#define F28004X_ADC_DEFINES_H +//############################################################################# #ifdef __cplusplus extern "C" { #endif // -// Defines -// - -// -// Definitions for specifying an ADC +// Globals // -#define ADC_ADCA 0 -#define ADC_ADCB 1 -#define ADC_ADCC 2 -#define ADC_ADCD 3 +// +// Function prototypes // -// Definitions for specifying reference mode -// -#define ADC_INTERNAL 0 -#define ADC_EXTERNAL 1 +int SCI_open(const char * path, unsigned flags, int llv_fd); +int SCI_close(int dev_fd); +int SCI_read(int dev_fd, char * buf, unsigned count); +int SCI_write(int dev_fd, const char * buf, unsigned count); +off_t SCI_lseek(int dev_fd, off_t offset, int origin); +int SCI_unlink(const char * path); +int SCI_rename(const char * old_name, const char * new_name); -// -// Definitions for specifying reference voltage -// -#define ADC_VREF3P3 0 -#define ADC_VREF2P5 1 +// KVV +int SCIB_open(const char * path, unsigned flags, int llv_fd); +int SCIB_close(int dev_fd); +int SCIB_read(int dev_fd, char * buf, unsigned count); +int SCIB_write(int dev_fd, const char * buf, unsigned count); +off_t SCIB_lseek(int dev_fd, off_t offset, int origin); +int SCIB_unlink(const char * path); +int SCIB_rename(const char * old_name, const char * new_name); #ifdef __cplusplus } -#endif /* extern "C" */ +#endif // extern "C" -#endif +#endif // end of _SCI_H_ definition // -// End of file +// End of File // + diff --git a/els-f280049c/main.cpp b/els-f280049c/main.cpp index 24c4872..7b96b11 100644 --- a/els-f280049c/main.cpp +++ b/els-f280049c/main.cpp @@ -36,6 +36,9 @@ #include "UserInterface.h" #include "Debug.h" +// KVV +#include "nextion.h" + __interrupt void cpu_timer0_isr(void); @@ -96,6 +99,9 @@ void main(void) // Initialize the PIE control registers to their default state. InitPieCtrl(); + // KVV + InitGpio(); + // Disable CPU interrupts and clear all CPU interrupt flags IER = 0x0000; IFR = 0x0000; @@ -124,6 +130,9 @@ void main(void) stepperDrive.initHardware(); encoder.initHardware(); + // KVV + nextion_init(); + // Enable CPU INT1 which is connected to CPU-Timer 0 IER |= M_INT1; @@ -134,6 +143,9 @@ void main(void) EINT; ERTM; + // KVV + nextion_wait(); + // User interface loop for(;;) { // mark beginning of loop for debugging diff --git a/els-f280049c/nextion-els.HMI b/els-f280049c/nextion-els.HMI new file mode 100644 index 0000000..a7726b8 Binary files /dev/null and b/els-f280049c/nextion-els.HMI differ diff --git a/els-f280049c/nextion-els.tft b/els-f280049c/nextion-els.tft new file mode 100644 index 0000000..c5b568f Binary files /dev/null and b/els-f280049c/nextion-els.tft differ diff --git a/els-f280049c/nextion-notes.txt b/els-f280049c/nextion-notes.txt new file mode 100644 index 0000000..f070dfd --- /dev/null +++ b/els-f280049c/nextion-notes.txt @@ -0,0 +1,22 @@ +To compile the Nextion HMI file, you'll need the Nextion Editor. A precompiled +Nextion TFT file is included. To load the TFT file to the display, copy the file +to a uSD card, insert into the Nextion display, power it on, and watch +the messages. Once firmware is loaded, remove card and power cycle everything. +https://nextion.tech/nextion-editor/ + +The ELS code was built using Code Composer Studio 10.1.0 and C2000Ware 3.02.00. + +The ELS code can be compiled in legacy COFF or to the new eabi (ELF) formats. +However, until C2000Ware is fixed, references to F28x_usDelay may need to be +changed to _F28x_usDelay. Places in C2000Ware that must be updated are +f28004x_sysctrl.c and f28004x_examples.h. Here is the message about the problem. +First try without making any changes and if undefined references to F28x_usDelay +are seen, switch to COFF or make the changes. + +https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/893565/3303362?tisearch=e2e-sitesearch&keymatch=F28x_usDelay#3303362 + +BUT I only managed to get ELF files to work with RAM, not with FLASH. I only +managed to get COFF files to work with FLASH. + +August 2020 +Kent A. Vander Velden (kent.vandervelden@gmail.com) diff --git a/els-f280049c/nextion.cpp b/els-f280049c/nextion.cpp new file mode 100644 index 0000000..3ff8886 --- /dev/null +++ b/els-f280049c/nextion.cpp @@ -0,0 +1,678 @@ +/* + * nextion.cpp + * + * Created on: Aug 25, 2020 + * Author: Kent A. Vander Velden (kent.vandervelden@gmail.com) + * + * Summary: The routines here translate between the existing seven + * segment display and the Nextion, leaving as much code untouched + * as possible. Two UARTS are used, SCIA for virtual COM debugging + * and SCIB which connects to the Nextion. An additional GPIO pin + * is used as a limit switch input, which may be useful as a hard + * limit to profile or thread up to a shoulder. + * + * Other than the TI routines at the end of this file, which have + * their own terms, the code is released to the public domain + * "as is" and is unsupported. + * + */ + +#include "F28x_Project.h" + +#include +#include +#include +#include +#include "driverlib.h" +#include "device.h" +#include "nextion.h" + +typedef unsigned char uchar_t; + +// Set to 1 to enable debugging of the Nextion messages over the +// virtual COM port (57600, 8N1) +#define NEXTION_DEBUG 0 + +#if NEXTION_DEBUG +#include +#include "launchxl_ex1_sci_io.h" + +static void scia_init(); +//static void transmitSCIAChar(uint16_t a); +//static void transmitSCIAMessage(const unsigned char *msg); +//static void initSCIAFIFO(void); +#endif + +static void scib_init(); +static void transmitSCIBChar(uint16_t a); +static void transmitSCIBMessage(const unsigned char *msg); +static void initSCIBFIFO(void); + +static int nextion_read(uchar_t buf[], const int nmax) +{ + int n = 0; + + while (n < nmax && ScibRegs.SCIFFRX.bit.RXFFST) + { + uint16_t ReceivedChar = ScibRegs.SCIRXBUF.all; + buf[n++] = ReceivedChar; + + // This delay is done to increase chances that a complete message from + // the Nextion will be received in one function call. To eliminate the + // delay, add memory to the Nextion routines, continuing to + // read and tokenize per call until a valid message is gathered. + // ~208us to transmit 8-bits at 38.4kBaud + DELAY_US(500); + } + +#if NEXTION_DEBUG + if (n > 0) + { + printf("%d:", n); + for (int i = 0; i < n; i++) + { + printf(" %02x", buf[i]); + } + putchar('\r'); + putchar('\n'); + } +#endif + + return n; +} + +static void nextion_send(const uchar_t *msg) +{ + transmitSCIBMessage((const unsigned char*) msg); + +#if NEXTION_DEBUG + { + const uchar_t *p; + printf("Send: "); + p = msg; + while(*p != '\0') { + if(isprint(*p)) { + putchar(*p); + } else { + putchar(0xff); + } + p++; + } + printf(" : "); + p = msg; + while(*p != '\0') { + printf(" %02x", *p); + p++; + } + putchar('\r'); + putchar('\n'); + } +#endif +} + +void nextion_init() +{ + // Configure the GPIO pin for the limit switch input + // GPIO_setPinConfig(GPIO_25_GPIO25); + GPIO_SetupPinMux(25, GPIO_MUX_CPU1, 0); + GPIO_SetupPinOptions(25, GPIO_INPUT, GPIO_OPENDRAIN | GPIO_PULLUP); + +#if NEXTION_DEBUG + GPIO_setPinConfig(GPIO_28_SCIRXDA); + GPIO_setPinConfig(GPIO_29_SCITXDA); + + GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC); + + scia_init(); +#endif + + GPIO_setPinConfig(GPIO_13_SCIRXDB); + GPIO_setPinConfig(GPIO_40_SCITXDB); + + GPIO_setPadConfig(13, GPIO_PIN_TYPE_PULLUP); + // GPIO_setPadConfig(40, GPIO_PIN_TYPE_PULLUP); + + GPIO_setQualificationMode(13, GPIO_QUAL_ASYNC); + + scib_init(); + + initSCIBFIFO(); + +#if NEXTION_DEBUG + // To help with debugging, configure the UART that is connected to + // USB port, the virtual terminal, to be stdout. + volatile int status = 0; + status = add_device("scia", _SSA, SCI_open, SCI_close, SCI_read, SCI_write, + SCI_lseek, SCI_unlink, SCI_rename); + volatile FILE *fid = fopen("scia", "w"); + freopen("scia:", "w", stdout); + setvbuf(stdout, NULL, _IONBF, 0); +#endif +} + +// Wait for the Nextion to become ready. +void nextion_wait() +{ + // The easiest way to while for the Nextion to be ready with a fixed delay + // to have a fixed delay. + // DELAY_US(250000); + // But the required time, while short, is unspecified. Instead, wait for + // the Nextion to send a ready message, eventually timing out if necessary. + // + // Nextion will send + // 0x00 0x00 0x00 0xff 0xff 0xff + // on start up, and + // 0x88 0xff 0xff 0xff + // when ready. Often both messages will be read in a single + // nextion_read(...) call + // + // The Nextion is ready fast and I rarely saw the ready message unless + // power cycling only the Nextion. It may be better to test if the Nextion + // is ready by checking its response to a query like which page is current. + + // Timeout after 40 * 25us = 1s + for (int i = 0; i < 40; i++) + { + const int nmax = 6; + uchar_t msg[nmax]; + int n = nextion_read(msg, nmax); + if (n > 3) + { + bool has_end = msg[n - 3] == 0xff && msg[n - 2] == 0xff + && msg[n - 1] == 0xff; + if (n >= 4 && msg[n - 4] == 0x88 && has_end) + { + break; + } + } + DELAY_US(25000); + } +} + +// Update the Nextion feed display using the same information used +// to update the seven-segment display. +void nextion_feed(const FEED_THREAD *f, LED_REG leds) +{ + { + uchar_t msg2[8 + 4 + 5] = { "t1.txt=\"" }; + uchar_t *p = msg2 + 8; + for (int i = 0; i < 4; i++) + { + Uint16 a = f->display[i]; + Uint16 pnt = a & POINT; + a &= ~POINT; + switch (a) + { + case BLANK: + *p++ = ' '; + break; + case ZERO: + *p++ = '0'; + break; + case ONE: + *p++ = '1'; + break; + case TWO: + *p++ = '2'; + break; + case THREE: + *p++ = '3'; + break; + case FOUR: + *p++ = '4'; + break; + case FIVE: + *p++ = '5'; + break; + case SIX: + *p++ = '6'; + break; + case SEVEN: + *p++ = '7'; + break; + case EIGHT: + *p++ = '8'; + break; + case NINE: + *p++ = '9'; + break; + default: + *p++ = '?'; + break; + } + if (pnt) + { + *p++ = '.'; + } + } + *p++ = '"'; + *p++ = '\xff'; + *p++ = '\xff'; + *p++ = '\xff'; + *p++ = '\0'; + nextion_send(msg2); + } + + { + const uchar_t *msgs[5] = { "b8.txt=\"mm Pitch\"\xff\xff\xff", + "b8.txt=\"mm / rev\"\xff\xff\xff", + "b8.txt=\"TPI\"\xff\xff\xff", + "b8.txt=\"inch / rev\"\xff\xff\xff", + "b8.txt=\"???\"\xff\xff\xff" }; + + int i = 4; + if (leds.bit.THREAD && leds.bit.TPI) + { + i = 2; + } + else if (leds.bit.FEED && leds.bit.INCH) + { + i = 3; + } + else if (leds.bit.THREAD && leds.bit.MM) + { + i = 0; + } + else if (leds.bit.FEED && leds.bit.MM) + { + i = 1; + } + + nextion_send(msgs[i]); + } + + { + const uchar_t *msgs[5] = { "b9.txt=\"Right Hand\"\xff\xff\xff", + "b9.txt=\"Left Hand\"\xff\xff\xff", + "b9.txt=\"Forward\"\xff\xff\xff", + "b9.txt=\"Reverse\"\xff\xff\xff", + "b9.txt=\"???\"\xff\xff\xff" }; + + int i = 4; + if (leds.bit.THREAD && leds.bit.FORWARD) + { + i = 0; + } + else if (leds.bit.THREAD && leds.bit.REVERSE) + { + i = 1; + } + else if (leds.bit.FEED && leds.bit.FORWARD) + { + i = 2; + } + else if (leds.bit.FEED && leds.bit.REVERSE) + { + i = 3; + } + + nextion_send(msgs[i]); + } +} + +void nextion_rpm(Uint16 rpm) +{ + static bool do_once = true; + static Uint16 p_rpm = 0; + + if (p_rpm != rpm || do_once) + { + uchar_t msg2[32]; + sprintf((char*) msg2, "t0.txt=\"%u\"\xff\xff\xff", rpm); + nextion_send(msg2); + + p_rpm = rpm; + do_once = false; + } +} + +KEY_REG nextion_loop(bool alarm, bool &enabled, bool &at_stop, bool &init) +{ + static bool do_once = true; + bool p_enabled = enabled; + + // Check the limit switch and update the enabled state + at_stop = GPIO_ReadPin(25); + enabled = enabled && !at_stop; + + // Receive message from Nextion display + const int nmax = 12; + uchar_t msg[nmax]; + int n = nextion_read(msg, nmax); + + // Feed_mode must be initialized with the same that's initially shown on the seven-segment display. + // This is a kludge but correcting this might have involved more changes in the original code. + // Worse case is the two are initially out of sync, but will sync up once the mode is changed. + static int feed_mode = 3; + + // Decode message from Nextion display and emulate a seven-segment key presses + KEY_REG key; + key.all = 0; + if (n > 3) + { + bool has_end = msg[n - 3] == 0xff && msg[n - 2] == 0xff + && msg[n - 1] == 0xff; + + if (has_end && (n == 10 || n == 4) && msg[n - 4] == 0x88) + { + // Reinitialize the screen if the Nextion resets, through a flag + // passed back to UserInterface the feed information is reinitialized. + do_once = true; +#if NEXTION_DEBUG + printf("Reinitialize\r\n"); +#endif + } + else if (has_end && n == 7 && msg[0] == 0x65) + { + // Touch Event + uchar_t page_num = msg[1]; + uchar_t comp_id = msg[2]; + uchar_t event = msg[3]; + + if (page_num == 0 && event == 1) + { + switch (comp_id) + { + case 9: + key.bit.DOWN = 1; + break; + case 10: + key.bit.UP = 1; + break; + case 14: + // Consider the desired state of the LEDs and what keys must be pressed to move to desired state. + // Desired state for each feed_mode: + // 0: + // leds.bit.THREAD = 1; + // leds.bit.MM = 1; + // 1: + // leds.bit.FEED = 1; + // leds.bit.MM = 1; + // 2: + // leds.bit.THREAD = 1; + // leds.bit.TPI = 1; + // 3: + // leds.bit.FEED = 1; + // leds.bit.INCH = 1; + feed_mode = (feed_mode + 1) % 4; + switch (feed_mode) + { + case 0: + key.bit.FEED_THREAD = 1; + key.bit.IN_MM = 1; + break; + case 1: + key.bit.FEED_THREAD = 1; + break; + case 2: + key.bit.FEED_THREAD = 1; + key.bit.IN_MM = 1; + break; + case 3: + key.bit.FEED_THREAD = 1; + break; + } + break; + case 15: + key.bit.FWD_REV = 1; + break; + case 18: + // Remain disabled if limit switch is tripped, else toggle enable. + enabled = !at_stop && !enabled; + break; + default: + break; + } + } + } + } + + // Set credits message once + if (do_once) + { + const uchar_t *msg = { "t2.txt=\"ELS 1.3.01\r\n" + "James Clough - Clough42\r\n" + "\r\n" + "Nextion display\r\n" + "Kent A. Vander Velden" + "\"\xff\xff\xff" }; + nextion_send(msg); + } + + // Update alarm indicator + { + static bool p_alarm = true; + const uchar_t *msgs[2] = { "r1.val=0\xff\xff\xff", + "r1.val=1\xff\xff\xff" }; + + if (p_alarm != alarm || do_once) + { + // In this fast loop, update the display only if needed to avoid flicker. + nextion_send(msgs[alarm ? 1 : 0]); + p_alarm = alarm; + } + } + + // Update the enable/disable button + if (p_enabled != enabled || do_once) + { + const uchar_t *msgs[2] = { "b11.txt=\"Enable\"\xff\xff\xff", + "b11.txt=\"Disable\"\xff\xff\xff" }; + nextion_send(msgs[enabled ? 1 : 0]); + } + + init = do_once; + do_once = false; + + return key; +} + +// =========================================================================== +// The support function below are from or based on TI's C2000Ware examples. +// Most are from sci_ex1_echoback.c, and below is the associated TI license. +// =========================================================================== +// +//############################################################################# +// $TI Release: F28002x Support Library v3.02.00.00 $ +// $Release Date: Tue May 26 17:23:28 IST 2020 $ +// $Copyright: +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#if NEXTION_DEBUG +// +// scia_init - SCIA 8-bit word, baud rate 0x001A, default, 1 STOP bit, +// no parity +// +static void scia_init() +{ + // + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + // + + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + SciaRegs.SCICCR.all = 0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + SciaRegs.SCICTL1.all = 0x0003; + + SciaRegs.SCICTL2.bit.TXINTENA = 1; + SciaRegs.SCICTL2.bit.RXBKINTENA = 1; + + // + // 57600 baud @LSPCLK = 12.5MHz (100 MHz SYSCLK) + // (1152kBaud didn't work with LPSCLK = 12.5MHz) + // + SciaRegs.SCIHBAUD.all = 0x00; + SciaRegs.SCILBAUD.all = 0x1B; + + // + // Relinquish SCI from Reset + // + SciaRegs.SCICTL1.all = 0x0023; + + return; +} +#endif + +// +// scib_init - SCIB 8-bit word, baud rate 0x001A, default, 1 STOP bit, +// no parity +// +static void scib_init() +{ + // + // Note: Clocks were turned on to the SCIB peripheral + // in the InitSysCtrl() function + // + + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + ScibRegs.SCICCR.all = 0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + ScibRegs.SCICTL1.all = 0x0003; + + ScibRegs.SCICTL2.bit.TXINTENA = 1; + ScibRegs.SCICTL2.bit.RXBKINTENA = 1; + + // Calculate baud rate bits using BRR = LPSCLK / ((Baud rate + 1) * 8) + // Round to +#if 0 + // + // 9600 baud @LSPCLK = 12.5MHz (100 MHz SYSCLK) + // + ScibRegs.SCIHBAUD.all = 0x00; + ScibRegs.SCILBAUD.all = 0xA3; +#else + // + // 38400 baud @LSPCLK = 12.5MHz (100 MHz SYSCLK) + // + ScibRegs.SCIHBAUD.all = 0x00; + ScibRegs.SCILBAUD.all = 0x29; +#endif + + // + // Relinquish SCI from Reset + // + ScibRegs.SCICTL1.all = 0x0023; + + return; +} + +#if NEXTION_DEBUG +#if 0 +// +// transmitSCIAChar - Transmit a character from the SCI +// +static void transmitSCIAChar(uint16_t a) +{ + while (SciaRegs.SCIFFTX.bit.TXFFST != 0) + { + + } + SciaRegs.SCITXBUF.all = a; +} + +// +// transmitSCIAMessage - Transmit message via SCIA +// +static void transmitSCIAMessage(const unsigned char *msg) +{ + int i; + i = 0; + while (msg[i] != '\0') + { + transmitSCIAChar(msg[i]); + i++; + } +} + +// +// initSCIAFIFO - Initialize the SCI FIFO +// +static void initSCIAFIFO(void) +{ + SciaRegs.SCIFFTX.all = 0xE040; + SciaRegs.SCIFFRX.all = 0x2044; + SciaRegs.SCIFFCT.all = 0x0; +} +#endif +#endif + +// +// transmitSCIAChar - Transmit a character from the SCI +// +static void transmitSCIBChar(uint16_t a) +{ + while (ScibRegs.SCIFFTX.bit.TXFFST != 0) + { + + } + ScibRegs.SCITXBUF.all = a; +} + +// +// transmitSCIAMessage - Transmit message via SCIB +// +static void transmitSCIBMessage(const unsigned char *msg) +{ + int i; + i = 0; + while (msg[i] != '\0') + { + transmitSCIBChar(msg[i]); + i++; + } +} + +// +// initSCIBFIFO - Initialize the SCI FIFO +// +static void initSCIBFIFO(void) +{ + ScibRegs.SCIFFTX.all = 0xE040; + ScibRegs.SCIFFRX.all = 0x2044; + ScibRegs.SCIFFCT.all = 0x0; +} + +// =========================================================================== diff --git a/els-f280049c/nextion.h b/els-f280049c/nextion.h new file mode 100644 index 0000000..80f4afc --- /dev/null +++ b/els-f280049c/nextion.h @@ -0,0 +1,20 @@ +/* + * nextion.h + * + * Created on: Aug 25, 2020 + * Author: Kent A. Vander Velden (kent.vandervelden@gmail.com) + */ + +#ifndef NEXTION_H_ +#define NEXTION_H_ + +#include "Tables.h" +#include "ControlPanel.h" + +void nextion_init(); +void nextion_wait(); +void nextion_feed(const FEED_THREAD*, LED_REG leds); +void nextion_rpm(Uint16 rpm); +KEY_REG nextion_loop(bool alarm, bool &enabled, bool &at_stop, bool &init); + +#endif /* NEXTION_H_ */ diff --git a/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs b/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs index 8e309e6..70ecb0b 100644 --- a/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs +++ b/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs @@ -1,15 +1,4 @@ eclipse.preferences.version=1 -encoding//Debug/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 -encoding//Debug/makefile=UTF-8 -encoding//Debug/objects.mk=UTF-8 -encoding//Debug/sources.mk=UTF-8 -encoding//Debug/subdir_rules.mk=UTF-8 -encoding//Debug/subdir_vars.mk=UTF-8 encoding//Release/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 encoding//Release/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 encoding//Release/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8