From 5c655a9b85a6f0cef36e54d148ce971115f22f67 Mon Sep 17 00:00:00 2001 From: Kent VanderVelden Date: Wed, 26 Aug 2020 20:23:23 -0500 Subject: [PATCH 1/9] Nextion touchscreen and limit switch support, ported to CCS 10 and C2kW 3.02 --- .gitignore | 2 +- els-f280049c/.cproject | 256 +- els-f280049c/.project | 88 + .../org.eclipse.cdt.codan.core.prefs | 100 + .../org.eclipse.core.resources.prefs | 19 +- els-f280049c/28004x_generic_flash_lnk.cmd | 57 +- els-f280049c/28004x_generic_ram_lnk.cmd | 41 +- els-f280049c/Core.cpp | 4 + els-f280049c/Core.h | 28 +- els-f280049c/UserInterface.cpp | 22 + .../common/include/F28x_Project.h | 51 - .../common/include/device.h | 307 -- .../common/include/driverlib.h | 82 - .../common/include/f28004x_cla_defines.h | 199 -- .../common/include/f28004x_cla_typedefs.h | 128 - .../common/include/f28004x_cputimervars.h | 143 - .../common/include/f28004x_defaultisr.h | 202 -- .../common/include/f28004x_dma_defines.h | 193 -- .../common/include/f28004x_epwm_defines.h | 342 -- .../common/include/f28004x_examples.h | 429 --- .../common/include/f28004x_globalprototypes.h | 256 -- .../common/include/f28004x_gpio_defines.h | 105 - .../common/include/f28004x_pie_defines.h | 72 - .../common/include/f28004x_sysctrl_defines.h | 59 - .../common/source/f28004x_adc.c | 102 - .../common/source/f28004x_codestartbranch.asm | 111 - .../common/source/f28004x_cputimers.c | 194 -- .../common/source/f28004x_dcsm_z1otp.asm | 186 -- .../common/source/f28004x_dcsm_z2otp.asm | 159 - .../common/source/f28004x_defaultisr.c | 2780 ----------------- .../common/source/f28004x_dma.c | 1104 ------- .../common/source/f28004x_gpio.c | 441 --- .../common/source/f28004x_piectrl.c | 124 - .../common/source/f28004x_pievect.c | 315 -- .../common/source/f28004x_spi.c | 177 -- .../common/source/f28004x_sysctrl.c | 876 ------ .../common/source/f28004x_usdelay.asm | 92 - .../headers/cmd/f28004x_headers_nonbios.cmd | 303 -- .../headers/include/f28004x_adc.h | 1048 ------- .../headers/include/f28004x_analogsubsys.h | 232 -- .../headers/include/f28004x_can.h | 607 ---- .../headers/include/f28004x_cla.h | 366 --- .../headers/include/f28004x_cla_prom_crc32.h | 157 - .../headers/include/f28004x_cmpss.h | 299 -- .../headers/include/f28004x_cputimer.h | 134 - .../headers/include/f28004x_dac.h | 156 - .../headers/include/f28004x_dcc.h | 203 -- .../headers/include/f28004x_dcsm.h | 658 ---- .../headers/include/f28004x_device.h | 276 -- .../headers/include/f28004x_dma.h | 214 -- .../headers/include/f28004x_ecap.h | 309 -- .../headers/include/f28004x_epwm.h | 1237 -------- .../headers/include/f28004x_epwm_xbar.h | 830 ----- .../headers/include/f28004x_eqep.h | 301 -- .../headers/include/f28004x_erad.h | 306 -- .../headers/include/f28004x_flash.h | 366 --- .../headers/include/f28004x_fsi.h | 660 ---- .../headers/include/f28004x_gpio.h | 1678 ---------- .../headers/include/f28004x_i2c.h | 251 -- .../headers/include/f28004x_input_xbar.h | 112 - .../headers/include/f28004x_lin.h | 576 ---- .../headers/include/f28004x_memconfig.h | 867 ----- .../headers/include/f28004x_nmiintrupt.h | 178 -- .../headers/include/f28004x_output_xbar.h | 905 ------ .../headers/include/f28004x_pga.h | 164 - .../headers/include/f28004x_piectrl.h | 702 ----- .../headers/include/f28004x_pievect.h | 297 -- .../headers/include/f28004x_pmbus.h | 291 -- .../headers/include/f28004x_sci.h | 256 -- .../headers/include/f28004x_sdfm.h | 797 ----- .../headers/include/f28004x_spi.h | 193 -- .../headers/include/f28004x_sysctrl.h | 2062 ------------ .../headers/include/f28004x_xbar.h | 372 --- .../headers/include/f28004x_xint.h | 138 - .../source/f28004x_globalvariabledefs.c | 861 ----- els-f280049c/launchxl_ex1_sci_io.c | 284 ++ ...4x_adc_defines.h => launchxl_ex1_sci_io.h} | 66 +- els-f280049c/main.cpp | 12 + els-f280049c/nextion-els.HMI | Bin 0 -> 1424053 bytes els-f280049c/nextion-els.tft | Bin 0 -> 423476 bytes els-f280049c/nextion-notes.txt | 22 + els-f280049c/nextion.cpp | 650 ++++ els-f280049c/nextion.h | 20 + .../org.eclipse.core.resources.prefs | 11 - 84 files changed, 1498 insertions(+), 28775 deletions(-) delete mode 100644 els-f280049c/device_support_f28004x/common/include/F28x_Project.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/device.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/driverlib.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_examples.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_adc.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_dma.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_spi.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm delete mode 100644 els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_can.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_device.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h delete mode 100644 els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c create mode 100644 els-f280049c/launchxl_ex1_sci_io.c rename els-f280049c/{device_support_f28004x/common/include/f28004x_adc_defines.h => launchxl_ex1_sci_io.h} (59%) create mode 100644 els-f280049c/nextion-els.HMI create mode 100644 els-f280049c/nextion-els.tft create mode 100644 els-f280049c/nextion-notes.txt create mode 100644 els-f280049c/nextion.cpp create mode 100644 els-f280049c/nextion.h diff --git a/.gitignore b/.gitignore index e3a6114..e4cce4e 100644 --- a/.gitignore +++ b/.gitignore @@ -30,7 +30,7 @@ *.exe *.out *.app -/.metadata/ +/.metadata/ .jxbrowser-data RemoteSystemsTempFiles diff --git a/els-f280049c/.cproject b/els-f280049c/.cproject index bbf0e3c..bd43e63 100644 --- a/els-f280049c/.cproject +++ b/els-f280049c/.cproject @@ -15,69 +15,92 @@ - - + + + + + + + + @@ -99,73 +122,103 @@ - - + + + + + + + + + @@ -178,6 +231,15 @@ - + + + + + + + + + + diff --git a/els-f280049c/.project b/els-f280049c/.project index e8c34c3..f123d98 100644 --- a/els-f280049c/.project +++ b/els-f280049c/.project @@ -24,4 +24,92 @@ org.eclipse.cdt.core.ccnature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + device_support_f28004x/device.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/device.c + + + device_support_f28004x/f28004x_adc.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_adc.c + + + device_support_f28004x/f28004x_codestartbranch.asm + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_codestartbranch.asm + + + device_support_f28004x/f28004x_cputimers.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_cputimers.c + + + device_support_f28004x/f28004x_dcsm_z1otp.asm + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_dcsm_z1otp.asm + + + device_support_f28004x/f28004x_dcsm_z2otp.asm + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_dcsm_z2otp.asm + + + device_support_f28004x/f28004x_defaultisr.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_defaultisr.c + + + device_support_f28004x/f28004x_dma.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_dma.c + + + device_support_f28004x/f28004x_globalvariabledefs.c + 1 + PARENT-5-PROJECT_LOC/ti/c2000/C2000Ware_3_02_00_00/device_support/f28004x/headers/source/f28004x_globalvariabledefs.c + + + device_support_f28004x/f28004x_gpio.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_gpio.c + + + device_support_f28004x/f28004x_headers_nonbios.cmd + 1 + PARENT-5-PROJECT_LOC/ti/c2000/C2000Ware_3_02_00_00/device_support/f28004x/headers/cmd/f28004x_headers_nonbios.cmd + + + device_support_f28004x/f28004x_piectrl.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_piectrl.c + + + device_support_f28004x/f28004x_pievect.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_pievect.c + + + device_support_f28004x/f28004x_spi.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_spi.c + + + device_support_f28004x/f28004x_sysctrl.c + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_sysctrl.c + + + device_support_f28004x/f28004x_usdelay.asm + 1 + TI_PRODUCTS_DIR/c2000/C2000Ware_3_02_00_00/device_support/f28004x/common/source/f28004x_usdelay.asm + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/driverlib/f28004x/driverlib + + diff --git a/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs b/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs index 98b6350..b4a10b6 100644 --- a/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs +++ b/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs @@ -1,3 +1,103 @@ eclipse.preferences.version=1 inEditor=false onBuild=false +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=-Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")"} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/els-f280049c/.settings/org.eclipse.core.resources.prefs b/els-f280049c/.settings/org.eclipse.core.resources.prefs index 8e309e6..f3eb3ba 100644 --- a/els-f280049c/.settings/org.eclipse.core.resources.prefs +++ b/els-f280049c/.settings/org.eclipse.core.resources.prefs @@ -1,21 +1,6 @@ eclipse.preferences.version=1 -encoding//Debug/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 -encoding//Debug/makefile=UTF-8 -encoding//Debug/objects.mk=UTF-8 -encoding//Debug/sources.mk=UTF-8 -encoding//Debug/subdir_rules.mk=UTF-8 -encoding//Debug/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 +encoding//Release/device_support_f28004x/subdir_rules.mk=UTF-8 +encoding//Release/device_support_f28004x/subdir_vars.mk=UTF-8 encoding//Release/makefile=UTF-8 encoding//Release/objects.mk=UTF-8 encoding//Release/sources.mk=UTF-8 diff --git a/els-f280049c/28004x_generic_flash_lnk.cmd b/els-f280049c/28004x_generic_flash_lnk.cmd index aa33b0e..ae52fda 100644 --- a/els-f280049c/28004x_generic_flash_lnk.cmd +++ b/els-f280049c/28004x_generic_flash_lnk.cmd @@ -23,14 +23,13 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. - MEMORY { PAGE 0 : /* BEGIN is used for the "boot to Flash" bootloader mode */ BEGIN : origin = 0x080000, length = 0x000002 - RAMM0 : origin = 0x0000F5, length = 0x00030B + RAMM0 : origin = 0x0000F3, length = 0x00030D RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 @@ -74,12 +73,15 @@ PAGE 0 : FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */ - FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */ + FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */ + +// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ PAGE 1 : - BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 @@ -88,28 +90,53 @@ PAGE 1 : RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 - RAMGS3 : origin = 0x012000, length = 0x002000 + RAMGS3 : origin = 0x012000, length = 0x001FF8 +// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } SECTIONS { codestart : > BEGIN, PAGE = 0, ALIGN(4) - .text : >>FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3, PAGE = 0, ALIGN(4) + .text : >>FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5, PAGE = 0, ALIGN(4) .cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) - .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ - .cio : > RAMLS0, PAGE = 0 .stack : > RAMM1, PAGE = 1 - .ebss : > RAMLS5, PAGE = 1 - .esysmem : > RAMLS5, PAGE = 1 - .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4) + +#if defined(__TI_EABI__) + .init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS0, PAGE = 0 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : >>FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7, PAGE = 0, ALIGN(4) +#else + .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) + .ebss : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS0, PAGE = 0 + .econst : >>FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7, PAGE = 0, ALIGN(4) +#endif ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 + +#if defined(__TI_EABI__) + .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(4) +#else .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, LOAD_START(_RamfuncsLoadStart), @@ -119,6 +146,12 @@ SECTIONS RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0, ALIGN(4) +#endif } +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/els-f280049c/28004x_generic_ram_lnk.cmd b/els-f280049c/28004x_generic_ram_lnk.cmd index 5fd166d..bbe5d30 100644 --- a/els-f280049c/28004x_generic_ram_lnk.cmd +++ b/els-f280049c/28004x_generic_ram_lnk.cmd @@ -23,14 +23,13 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. - MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 - RAMM0 : origin = 0x0000F5, length = 0x00030B + RAMM0 : origin = 0x0000F3, length = 0x00030D RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 @@ -78,8 +77,9 @@ PAGE 0 : PAGE 1 : - BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 @@ -88,27 +88,44 @@ PAGE 1 : RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 - RAMGS3 : origin = 0x012000, length = 0x002000 + RAMGS3 : origin = 0x012000, length = 0x001FF8 +// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } /*You can arrange the .text, .cinit, .const, .pinit, .switch and .econst to FLASH when RAM is filled up.*/ SECTIONS { codestart : > BEGIN, PAGE = 0 - .TI.ramfunc : > RAMM0 PAGE = 0 - .text : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .TI.ramfunc : > RAMM0, PAGE = 0 + .text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 .cinit : > RAMM0, PAGE = 0 - .pinit : > RAMM0, PAGE = 0 .switch : > RAMM0, PAGE = 0 - .cio : > RAMLS0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .stack : > RAMM1, PAGE = 1 - .ebss : > RAMLS5|RAMLS6, PAGE = 1 - .econst : > RAMLS5|RAMLS6, PAGE = 1 - .esysmem : > RAMLS5|RAMLS6, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS5, PAGE = 1 + .init_array : > RAMM0, PAGE = 0 + .const : >> RAMLS6|RAMLS7, PAGE = 1, ALIGN(4) + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + .bss:cio : > RAMLS0, PAGE = 0 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : >> RAMLS6|RAMLS7, PAGE = 1, ALIGN(4) + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS0, PAGE = 0 +#endif ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 } +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/els-f280049c/Core.cpp b/els-f280049c/Core.cpp index 266ee46..fccb14c 100644 --- a/els-f280049c/Core.cpp +++ b/els-f280049c/Core.cpp @@ -40,6 +40,10 @@ Core :: Core( Encoder *encoder, StepperDrive *stepperDrive ) this->previousSpindlePosition = 0; this->previousFeedDirection = 0; this->previousFeed = NULL; + + // KVV + this->enabled = true; + this->reenabled = true; } void Core :: setReverse(bool reverse) diff --git a/els-f280049c/Core.h b/els-f280049c/Core.h index b843601..19141bc 100644 --- a/els-f280049c/Core.h +++ b/els-f280049c/Core.h @@ -54,6 +54,10 @@ class Core int32 feedRatio(Uint32 count); + // KVV + bool enabled; + bool reenabled; + public: Core( Encoder *encoder, StepperDrive *stepperDrive ); @@ -63,8 +67,26 @@ class Core bool isAlarm(); void ISR( void ); + + // KVV + void setEnabled(bool v); + bool isEnabled() const; }; +// KVV +inline void Core :: setEnabled(bool v) +{ + if(enabled != v) { + enabled = v; + reenabled = enabled; + } +} + +inline bool Core :: isEnabled() const +{ + return enabled; +} + inline void Core :: setFeed(const FEED_THREAD *feed) { #ifdef USE_FLOATING_POINT @@ -95,7 +117,7 @@ inline int32 Core :: feedRatio(Uint32 count) inline void Core :: ISR( void ) { - if( this->feed != NULL ) { + if( this->enabled && this->feed != NULL ) { // read the encoder Uint32 spindlePosition = encoder->getPosition(); @@ -112,8 +134,10 @@ inline void Core :: ISR( void ) } // if the feed or direction changed, reset sync to avoid a big step - if( feed != previousFeed || feedDirection != previousFeedDirection) { + if( feed != previousFeed || feedDirection != previousFeedDirection || reenabled) { stepperDrive->setCurrentPosition(desiredSteps); + // KVV + reenabled = false; } // remember values for next time diff --git a/els-f280049c/UserInterface.cpp b/els-f280049c/UserInterface.cpp index b30337b..d21ad14 100644 --- a/els-f280049c/UserInterface.cpp +++ b/els-f280049c/UserInterface.cpp @@ -25,6 +25,8 @@ #include "UserInterface.h" +// KVV +#include "nextion.h" const MESSAGE STARTUP_MESSAGE_2 = { @@ -127,6 +129,21 @@ void UserInterface :: loop( void ) // read keypresses from the control panel keys = controlPanel->getKeys(); + // KVV + { + bool at_stop; + bool enabled = core->isEnabled(); + bool nextion_init = false; + KEY_REG nkeys = nextion_loop(core->isAlarm(), enabled, at_stop, nextion_init); + core->setEnabled(enabled); + if (nkeys.all) { + keys = nkeys; + } + if( nextion_init ) { + newFeed = loadFeedTable(); + } + } + // respond to keypresses if( keys.bit.IN_MM ) { @@ -163,6 +180,9 @@ void UserInterface :: loop( void ) LED_REG leds = this->calculateLEDs(newFeed); controlPanel->setLEDs(leds); controlPanel->setValue(newFeed->display); + // KVV + // Must pass leds as newFeed->leds is out of date, and may not have foward/reverse set. + nextion_feed(newFeed, leds); // update the core core->setFeed(newFeed); @@ -171,6 +191,8 @@ void UserInterface :: loop( void ) // update the RPM display controlPanel->setRPM(core->getRPM()); + // KVV + nextion_rpm(core->getRPM()); // write data out to the display controlPanel->refresh(); diff --git a/els-f280049c/device_support_f28004x/common/include/F28x_Project.h b/els-f280049c/device_support_f28004x/common/include/F28x_Project.h deleted file mode 100644 index daebcc0..0000000 --- a/els-f280049c/device_support_f28004x/common/include/F28x_Project.h +++ /dev/null @@ -1,51 +0,0 @@ -//############################################################################# -// -// FILE: F28x_Project.h -// -// TITLE: F28x Project Headerfile and Examples Include File -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F28X_PROJECT_H -#define F28X_PROJECT_H - -#include "f28004x_cla_typedefs.h" // f28004x CLA Type definitions -#include "f28004x_device.h" // f28004x Headerfile Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -#endif // end of F28X_PROJECT_H definition - diff --git a/els-f280049c/device_support_f28004x/common/include/device.h b/els-f280049c/device_support_f28004x/common/include/device.h deleted file mode 100644 index 26690ad..0000000 --- a/els-f280049c/device_support_f28004x/common/include/device.h +++ /dev/null @@ -1,307 +0,0 @@ -//############################################################################# -// -// FILE: device.h -// -// TITLE: Device setup for examples. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef __DEVICE_H__ -#define __DEVICE_H__ - -// -// Included Files -// -#include "driverlib.h" - -//***************************************************************************** -// -// Defines for pin numbers and other GPIO configuration -// -//***************************************************************************** -#ifdef _LAUNCHXL_F280049C -// -// LaunchPad -// - -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 34U // GPIO number for LD4 -#define DEVICE_GPIO_PIN_LED2 23U // GPIO number for LD5 -#define DEVICE_GPIO_CFG_LED1 GPIO_34_GPIO34 // "pinConfig" for LD4 -#define DEVICE_GPIO_CFG_LED2 GPIO_23_GPIO23 // "pinConfig" for LD5 - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 32U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 33U // GPIO number for CANRXA -#define DEVICE_GPIO_CFG_CANRXA GPIO_33_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_32_CANTXA // "pinConfig" for CANA TX - -// -// LINA -// -#define DEVICE_GPIO_CFG_LINTXA GPIO_37_LINTXA // "pinConfig" for LINA TX -#define DEVICE_GPIO_CFG_LINRXA GPIO_35_LINRXA // "pinConfig" for LINA RX - -// -// FSI -// -#define DEVICE_GPIO_PIN_FSI_RXCLK 33U // GPIO number for FSI RXCLK -#define DEVICE_GPIO_CFG_FSI_RXCLK GPIO_33_FSI_RXCLK // "pinConfig" for FSI RXCLK - -// -// SPI -// -#define DEVICE_GPIO_PIN_SPICLKA 56U // GPIO number for SPI CLKA -#define DEVICE_GPIO_PIN_SPISIMOA 16U // GPIO number for SPI SIMOA -#define DEVICE_GPIO_PIN_SPISOMIA 17U // GPIO number for SPI SOMIA -#define DEVICE_GPIO_PIN_SPISTEA 57U // GPIO number for SPI STEA -#define DEVICE_GPIO_CFG_SPICLKA GPIO_56_SPICLKA // "pinConfig" for SPI CLKA -#define DEVICE_GPIO_CFG_SPISIMOA GPIO_16_SPISIMOA // "pinConfig" for SPI SIMOA -#define DEVICE_GPIO_CFG_SPISOMIA GPIO_17_SPISOMIA // "pinConfig" for SPI SOMIA -#define DEVICE_GPIO_CFG_SPISTEA GPIO_57_SPISTEA // "pinConfig" for SPI STEA -#define DEVICE_GPIO_PIN_SPICLKB 26U // GPIO number for SPI CLKB -#define DEVICE_GPIO_PIN_SPISIMOB 24U // GPIO number for SPI SIMOB -#define DEVICE_GPIO_PIN_SPISOMIB 31U // GPIO number for SPI SOMIB -#define DEVICE_GPIO_PIN_SPISTEB 27U // GPIO number for SPI STEB -#define DEVICE_GPIO_CFG_SPICLKB GPIO_26_SPICLKB // "pinConfig" for SPI CLKB -#define DEVICE_GPIO_CFG_SPISIMOB GPIO_24_SPISIMOB // "pinConfig" for SPI SIMOB -#define DEVICE_GPIO_CFG_SPISOMIB GPIO_31_SPISOMIB // "pinConfig" for SPI SOMIB -#define DEVICE_GPIO_CFG_SPISTEB GPIO_27_SPISTEB // "pinConfig" for SPI STEB - -// -// I2C -// -#define DEVICE_GPIO_PIN_SDAA 35U // GPIO number for I2C SDAA -#define DEVICE_GPIO_PIN_SCLA 37U // GPIO number for I2C SCLA -#define DEVICE_GPIO_CFG_SDAA GPIO_35_SDAA // "pinConfig" for I2C SDAA -#define DEVICE_GPIO_CFG_SCLA GPIO_37_SCLA // "pinConfig" for I2C SCLA - -// -// eQEP -// -#define DEVICE_GPIO_PIN_EQEP1A 35U // GPIO number for EQEP 1A -#define DEVICE_GPIO_PIN_EQEP1B 37U // GPIO number for EQEP 1B -#define DEVICE_GPIO_PIN_EQEP1I 59U // GPIO number for EQEP 1I -#define DEVICE_GPIO_CFG_EQEP1A GPIO_35_EQEP1A // "pinConfig" for EQEP 1A -#define DEVICE_GPIO_CFG_EQEP1B GPIO_37_EQEP1B // "pinConfig" for EQEP 1B -#define DEVICE_GPIO_CFG_EQEP1I GPIO_59_EQEP1I // "pinConfig" for EQEP 1I - -// -// EPWM -// -#define DEVICE_PERIPHERAL_BASE_EPWM EPWM6_BASE // Base peripheral EPWM 6 -#define DEVICE_PERIPHERAL_INT_EPWM INT_EPWM6 // Base peripheral EPWM 6 interrupt -#define DEVICE_GPIO_PIN_EPWMxA 10U // GPIO number for EPWM6A -#define DEVICE_GPIO_PIN_EPWMxB 11U // GPIO number for EPWM6B -#define DEVICE_GPIO_PIN_IOINDEX 8U // GPIO number for IO Index -#define DEVICE_GPIO_CFG_EPWMxA GPIO_10_EPWM6A // "pinConfig" for EPWM6A -#define DEVICE_GPIO_CFG_EPWMxB GPIO_11_EPWM6B // "pinConfig" for EPWM6B -#define DEVICE_GPIO_CFG_IOINDEX GPIO_8_GPIO8 // "pinConfig" for IO Index - -#else -// -// ControlCARD -// - -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 -#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 -#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 -#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA - -// -// CAN External Loopback -// -#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX -#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX -#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX - -// -// LINA -// -#define DEVICE_GPIO_CFG_LINTXA GPIO_46_LINTXA // "pinConfig" for LINA TX -#define DEVICE_GPIO_CFG_LINRXA GPIO_47_LINRXA // "pinConfig" for LINA RX - -// -// FSI -// -#define DEVICE_GPIO_PIN_FSI_RXCLK 13U // GPIO number for FSI RXCLK -#define DEVICE_GPIO_CFG_FSI_RXCLK GPIO_13_FSI_RXCLK // "pinConfig" for FSI RXCLK - -// -// SPI -// -#define DEVICE_GPIO_PIN_SPICLKA 9U // GPIO number for SPI CLKA -#define DEVICE_GPIO_PIN_SPISIMOA 8U // GPIO number for SPI SIMOA -#define DEVICE_GPIO_PIN_SPISOMIA 10U // GPIO number for SPI SOMIA -#define DEVICE_GPIO_PIN_SPISTEA 11U // GPIO number for SPI STEA -#define DEVICE_GPIO_CFG_SPICLKA GPIO_9_SPICLKA // "pinConfig" for SPI CLKA -#define DEVICE_GPIO_CFG_SPISIMOA GPIO_8_SPISIMOA // "pinConfig" for SPI SIMOA -#define DEVICE_GPIO_CFG_SPISOMIA GPIO_10_SPISOMIA // "pinConfig" for SPI SOMIA -#define DEVICE_GPIO_CFG_SPISTEA GPIO_11_SPISTEA // "pinConfig" for SPI STEA -#define DEVICE_GPIO_PIN_SPICLKB 26U // GPIO number for SPI CLKB -#define DEVICE_GPIO_PIN_SPISIMOB 24U // GPIO number for SPI SIMOB -#define DEVICE_GPIO_PIN_SPISOMIB 25U // GPIO number for SPI SOMIB -#define DEVICE_GPIO_PIN_SPISTEB 27U // GPIO number for SPI STEB -#define DEVICE_GPIO_CFG_SPICLKB GPIO_26_SPICLKB // "pinConfig" for SPI CLKB -#define DEVICE_GPIO_CFG_SPISIMOB GPIO_24_SPISIMOB // "pinConfig" for SPI SIMOB -#define DEVICE_GPIO_CFG_SPISOMIB GPIO_25_SPISOMIB // "pinConfig" for SPI SOMIB -#define DEVICE_GPIO_CFG_SPISTEB GPIO_27_SPISTEB // "pinConfig" for SPI STEB - -// -// I2C -// -#define DEVICE_GPIO_PIN_SDAA 32U // GPIO number for I2C SDAA -#define DEVICE_GPIO_PIN_SCLA 33U // GPIO number for I2C SCLA -#define DEVICE_GPIO_CFG_SDAA GPIO_32_SDAA // "pinConfig" for I2C SDAA -#define DEVICE_GPIO_CFG_SCLA GPIO_33_SCLA // "pinConfig" for I2C SCLA - -// -// eQEP -// -#define DEVICE_GPIO_PIN_EQEP1A 6U // GPIO number for EQEP 1A -#define DEVICE_GPIO_PIN_EQEP1B 7U // GPIO number for EQEP 1B -#define DEVICE_GPIO_PIN_EQEP1I 9U // GPIO number for EQEP 1I -#define DEVICE_GPIO_CFG_EQEP1A GPIO_6_EQEP1A // "pinConfig" for EQEP 1A -#define DEVICE_GPIO_CFG_EQEP1B GPIO_7_EQEP1B // "pinConfig" for EQEP 1B -#define DEVICE_GPIO_CFG_EQEP1I GPIO_9_EQEP1I // "pinConfig" for EQEP 1I - -// -// EPWM -// -#define DEVICE_PERIPHERAL_BASE_EPWM EPWM1_BASE // Base peripheral EPWM 1 -#define DEVICE_PERIPHERAL_INT_EPWM INT_EPWM1 // Base peripheral EPWM 1 interrupt -#define DEVICE_GPIO_PIN_EPWMxA 0U // GPIO number for EPWM1A -#define DEVICE_GPIO_PIN_EPWMxB 1U // GPIO number for EPWM1B -#define DEVICE_GPIO_PIN_IOINDEX 2U // GPIO number for IO Index -#define DEVICE_GPIO_CFG_EPWMxA GPIO_0_EPWM1A // "pinConfig" for EPWM1A -#define DEVICE_GPIO_CFG_EPWMxB GPIO_1_EPWM1B // "pinConfig" for EPWM1B -#define DEVICE_GPIO_CFG_IOINDEX GPIO_2_GPIO2 // "pinConfig" for IO Index - -#endif - -// -// SCI for USB-to-UART adapter on FTDI chip -// -#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX -#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX -#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX -#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX - -//***************************************************************************** -// -// Defines related to clock configuration -// -//***************************************************************************** -// -// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). -// -#define DEVICE_OSCSRC_FREQ 20000000U - -// -// Define to pass to SysCtl_setClock(). Will configure the clock as follows: -// PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) -// -#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) | \ - SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ - SYSCTL_PLL_ENABLE) - -// -// 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the -// code below if a different clock configuration is used! -// -#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 10 * 1) / 2) - -// -// 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default -// low speed peripheral clock divider of 4. Update the code below if a -// different LSPCLK divider is used! -// -#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) - -//***************************************************************************** -// -// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro -// will convert the desired delay in microseconds to the count value expected -// by the function. \b x is the number of microseconds to delay. -// -//***************************************************************************** -#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ - (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) - -//***************************************************************************** -// -// Defines, Globals, and Header Includes related to Flash Support -// -//***************************************************************************** -#ifdef _FLASH -#include - -extern uint16_t RamfuncsLoadStart; -extern uint16_t RamfuncsLoadEnd; -extern uint16_t RamfuncsLoadSize; -extern uint16_t RamfuncsRunStart; -extern uint16_t RamfuncsRunEnd; -extern uint16_t RamfuncsRunSize; -#endif - -#define DEVICE_FLASH_WAITSTATES 4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void Device_init(void); -extern void Device_enableAllPeripherals(void); -extern void Device_initGPIO(void); -extern void __error__(char *filename, uint32_t line); - -#endif // __DEVICE_H__ diff --git a/els-f280049c/device_support_f28004x/common/include/driverlib.h b/els-f280049c/device_support_f28004x/common/include/driverlib.h deleted file mode 100644 index 54b5ba6..0000000 --- a/els-f280049c/device_support_f28004x/common/include/driverlib.h +++ /dev/null @@ -1,82 +0,0 @@ -//############################################################################# -// -// FILE: driverlib.h -// -// TITLE: C28x Driverlib Header File -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef DRIVERLIB_H -#define DRIVERLIB_H - -#include "inc/hw_memmap.h" - -#include "adc.h" -#include "asysctl.h" -#include "can.h" -#include "cla.h" -#include "clapromcrc.h" -#include "cmpss.h" -#include "cpu.h" -#include "cputimer.h" -#include "dac.h" -#include "dcc.h" -#include "dcsm.h" -#include "debug.h" -#include "dma.h" -#include "ecap.h" -#include "epwm.h" -#include "eqep.h" -#include "flash.h" -#include "fsi.h" -#include "gpio.h" -#include "hrcap.h" -#include "hrpwm.h" -#include "i2c.h" -#include "interrupt.h" -#include "lin.h" -#include "memcfg.h" -#include "pga.h" -#include "pin_map.h" -#include "pmbus.h" -#include "sci.h" -#include "sdfm.h" -#include "spi.h" -#include "sysctl.h" -#include "version.h" -#include "xbar.h" - -#endif // end of DRIVERLIB_H definition diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h deleted file mode 100644 index 9b89799..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h +++ /dev/null @@ -1,199 +0,0 @@ -//############################################################################# -// -// FILE: f28004x_cla_defines.h -// -// TITLE: #defines used in CLA examples -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef F28004X_CLA_DEFINES_H_ -#define F28004X_CLA_DEFINES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// MCTL Register -// -#define CLA_FORCE_RESET 0x1 -#define CLA_IACK_ENABLE 0x1 -#define CLA_IACK_DISABLE 0x0 - -// -// MMEMCFG Register -// -#define CLA_CLA_SPACE 0x1 -#define CLA_CPU_SPACE 0x0 - -// -// MIER Interrupt Enable Register -// -#define CLA_INT_ENABLE 0x1 -#define CLA_INT_DISABLE 0x0 - -// -// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register -// -#define CLA_TRIG_NOPERPH 0 -#define CLA_TRIG_ADCAINT1 1 -#define CLA_TRIG_ADCAINT2 2 -#define CLA_TRIG_ADCAINT3 3 -#define CLA_TRIG_ADCAINT4 4 -#define CLA_TRIG_ADCAEVT 5 -#define CLA_TRIG_ADCBINT1 6 -#define CLA_TRIG_ADCBINT2 7 -#define CLA_TRIG_ADCBINT3 8 -#define CLA_TRIG_ADCBINT4 9 -#define CLA_TRIG_ADCBEVT 10 -#define CLA_TRIG_ADCCINT1 11 -#define CLA_TRIG_ADCCINT2 12 -#define CLA_TRIG_ADCCINT3 13 -#define CLA_TRIG_ADCCINT4 14 -#define CLA_TRIG_ADCCEVT 15 - -#define CLA_TRIG_XINT1 29 -#define CLA_TRIG_XINT2 30 -#define CLA_TRIG_XINT3 31 -#define CLA_TRIG_XINT4 32 -#define CLA_TRIG_XINT5 33 - -#define CLA_TRIG_EPWM1INT 36 -#define CLA_TRIG_EPWM2INT 37 -#define CLA_TRIG_EPWM3INT 38 -#define CLA_TRIG_EPWM4INT 39 -#define CLA_TRIG_EPWM5INT 40 -#define CLA_TRIG_EPWM6INT 41 -#define CLA_TRIG_EPWM7INT 42 -#define CLA_TRIG_EPWM8INT 43 - -#define CLA_TRIG_TINT0 68 -#define CLA_TRIG_TINT1 69 -#define CLA_TRIG_TINT2 70 - -#define CLA_TRIG_ECAP1INT 75 -#define CLA_TRIG_ECAP2INT 76 -#define CLA_TRIG_ECAP3INT 77 -#define CLA_TRIG_ECAP4INT 78 -#define CLA_TRIG_ECAP5INT 79 -#define CLA_TRIG_ECAP6INT 80 -#define CLA_TRIG_ECAP7INT 81 - -#define CLA_TRIG_EQEP1INT 83 -#define CLA_TRIG_EQEP2INT 84 - -#define CLA_TRIG_ECAP6INT2 92 -#define CLA_TRIG_ECAP7INT2 93 - -#define CLA_TRIG_SD1INT 95 -#define CLA_TRIG_SD1DRINT1 96 -#define CLA_TRIG_SD1DRINT2 97 -#define CLA_TRIG_SD1DRINT3 98 -#define CLA_TRIG_SD1DRINT4 99 - -#define CLA_TRIG_PMBUSAINT 105 - -#define CLA_TRIG_SPITXINTA 109 -#define CLA_TRIG_SPIRXINTA 110 -#define CLA_TRIG_SPITXINTB 111 -#define CLA_TRIG_SPIRXINTB 112 - -#define CLA_TRIG_LINA_INT1 117 -#define CLA_TRIG_LINA_INT0 118 - -#define CLA_TRIG_CLA1PROMCRC 121 - -#define CLA_TRIG_FSITXINT1 123 -#define CLA_TRIG_FSITXINT2 124 -#define CLA_TRIG_FSIRXINT1 125 -#define CLA_TRIG_FSIRXINT2 126 -#define CLA_TRIG_CLB1INT 127 -#define CLA_TRIG_CLB2INT 128 -#define CLA_TRIG_CLB3INT 129 -#define CLA_TRIG_CLB4INT 130 - -#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT1 == 1); - -#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT2 == 1); - -#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT3 == 1); - -#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT4 == 1); - -#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT5 == 1); - -#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT6 == 1); - -#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT7 == 1); - -#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT8 == 1); - -#define Cla1ForceTask1() asm(" IACK #0x0001") -#define Cla1ForceTask2() asm(" IACK #0x0002") -#define Cla1ForceTask3() asm(" IACK #0x0004") -#define Cla1ForceTask4() asm(" IACK #0x0008") -#define Cla1ForceTask5() asm(" IACK #0x0010") -#define Cla1ForceTask6() asm(" IACK #0x0020") -#define Cla1ForceTask7() asm(" IACK #0x0040") -#define Cla1ForceTask8() asm(" IACK #0x0080") - -#ifdef __cplusplus -} -#endif - - - -#endif /* F2004X_CLA_DEFINES_H_ */ diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h deleted file mode 100644 index ce918c1..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h +++ /dev/null @@ -1,128 +0,0 @@ - //########################################################################### -// -// FILE: f28004x_cla_typedefs.h -// -// TITLE: Variable type definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - - -#ifndef F28004x_CLA_TYPEDEFS_H_ -#define F28004x_CLA_TYPEDEFS_H_ - -// -// Macros to manipulate pre-processor to generate a header file name -// at compile time that is based on the test name and can be used as -// an argument to #include -// -#define XSTRINGIZE(s) STRINGIZE(s) -#define STRINGIZE(s) #s -#define XCONCAT(x,y) CONCAT(x,y) -#define CONCAT(x,y) x##y - -// -// Suppress warnings casting CLA pointers -// -#pragma diag_suppress 70,770,232 - -#ifdef __TMS320C28XX_CLA__ -// -// For Portability, User Is Recommended To Use Following Data Type Size -// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: -// -// CLA does not support 64-bit types -// This definition is only to allow inclusion of the standard header files -// which do use 64-bit types -// - -#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) -#define F28_DATA_TYPES -#define DSP28_DATA_TYPES -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else -#error f28004x_Cla_Typedefs.h must be included before f28004x_Device.h or any other header \ -file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES -#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) - -#ifndef _TI_STD_TYPES -#define _TI_STD_TYPES -// -// These types are also defined in DSP/BIOS 5.x's and the -// SYS/BIOS 6.x's files. We need to protect their -// definition with the #ifndef/#define guard to avoid the duplicate -// definition warning. -// -// SYS/BIOS requires that the file be included before -// any other .h files. -// -#endif - -// -// MSTF bit description -// -struct MSTF_SHADOW_BITS { - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Rounding Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint16 RPCL:4; // 15:12 Return PC: Low Portion - Uint16 RPCH:8; // 23:16 Return PC: High Portion - Uint16 rsvd4:8; // 31:24 Reserved -}; -extern __cregister volatile unsigned int MSTF; - -#endif - -#ifndef __TMS320C28XX__ -#define __cregister -#endif - -#endif /*f28004x_CLA_TYPEDEFS_H_*/ diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h deleted file mode 100644 index 2b92a3f..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h +++ /dev/null @@ -1,143 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimervars.h -// -// TITLE: f28004x Device CPUTIMERS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_CPUTIMERVARS_H -#define F28004x_CPUTIMERVARS_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Cputimers External References & Function Declarations -// - -// -// CPU Timer Support Variables: -// -struct CPUTIMER_VARS { - volatile struct CPUTIMER_REGS *RegsAddr; - Uint32 InterruptCount; - float CPUFreqInMHz; - float PeriodInUSec; -}; - -// -// Function prototypes and external definitions: -// -void InitCpuTimers(void); -void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); - -extern struct CPUTIMER_VARS CpuTimer0; -extern struct CPUTIMER_VARS CpuTimer1; -extern struct CPUTIMER_VARS CpuTimer2; - -// -// Useful Timer Operations -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of f28004x_CPUTIMERVARS_H definition - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h b/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h deleted file mode 100644 index ddfb733..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h +++ /dev/null @@ -1,202 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_defaultisr.h -// -// TITLE: f28004x Device Default Interrupt Service Routines Definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_DEFAULT_ISR_H -#define F28004x_DEFAULT_ISR_H -#ifdef __cplusplus -extern "C" { -#endif - -// -// Default Interrupt Service Routine Declarations: -// The following function prototypes are for the -// default ISR routines used with the default PIE vector table. -// This default vector table is found in the f28004x_pievect.h -// file. -// -interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt -interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt -interrupt void DATALOG_ISR(void); // Datalogging Interrupt -interrupt void RTOS_ISR(void); // RTOS Interrupt -interrupt void EMU_ISR(void); // Emulation Interrupt -interrupt void NMI_ISR(void); // Non-Maskable Interrupt -interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap -interrupt void USER1_ISR(void); // User Defined Trap 1 -interrupt void USER2_ISR(void); // User Defined Trap 2 -interrupt void USER3_ISR(void); // User Defined Trap 3 -interrupt void USER4_ISR(void); // User Defined Trap 4 -interrupt void USER5_ISR(void); // User Defined Trap 5 -interrupt void USER6_ISR(void); // User Defined Trap 6 -interrupt void USER7_ISR(void); // User Defined Trap 7 -interrupt void USER8_ISR(void); // User Defined Trap 8 -interrupt void USER9_ISR(void); // User Defined Trap 9 -interrupt void USER10_ISR(void); // User Defined Trap 10 -interrupt void USER11_ISR(void); // User Defined Trap 11 -interrupt void USER12_ISR(void); // User Defined Trap 12 -interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 -interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 -interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 -interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt -interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt -interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt -interrupt void WAKE_ISR(void); // 1.8 - Halt Wakeup Interrupt -interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt -interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt -interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt -interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt -interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt -interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt -interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt -interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt -interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt -interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt -interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt -interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt -interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt -interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt -interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt -interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt -interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt -interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt -interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt -interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt -interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt -interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt -interrupt void ECAP7_ISR(void); // 4.7 - eCAP7 Interrupt -interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt -interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt -interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt -interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt -interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt -interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt -interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt -interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt -interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt -interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt -interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt -interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt -interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 -interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 -interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt -interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt -interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt -interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt -interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 -interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 -interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 -interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 -interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt -interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 -interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 -interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 -interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt -interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 -interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 -interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 -interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 -interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 -interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 -interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 -interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 -interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 -interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 -interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 -interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt -interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt -interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt -interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt -interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt -interrupt void ECAP6_2_ISR(void); // 4.14 - eCAP6 HR Calibration Interrupt -interrupt void ECAP7_2_ISR(void); // 4.15 - eCAP6 HR Calibration Interrupt -interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt -interrupt void SD1DR1_ISR(void); // 5.13 - SDFM1 DR Interrupt 1 -interrupt void SD1DR2_ISR(void); // 5.14 - SDFM1 DR Interrupt 2 -interrupt void SD1DR3_ISR(void); // 5.15 - SDFM1 DR Interrupt 3 -interrupt void SD1DR4_ISR(void); // 5.16 - SDFM1 DR Interrupt 4 -interrupt void FSITXA1_ISR(void); // 7.11 - FSITXA1 Interrupt -interrupt void FSITXA2_ISR(void); // 7.12 - FSITXA2 Interrupt -interrupt void FSIRXA1_ISR(void); // 7.13 - FSIRXA1 Interrupt -interrupt void FSIRXA2_ISR(void); // 7.14 - FSIRXA2 Interrupt -interrupt void CLA1PROMCRC_ISR(void); // 7.15 - CLAP1ROMCRC Interrupt -interrupt void LINA_0_ISR(void); // 8.9 - LINA Interrupt 0 -interrupt void LINA_1_ISR(void); // 8.10 - LINA Interrupt 1 -interrupt void PMBUSA_ISR(void); // 8.13 - PMBUSA Interrupt -interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt -interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 -interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 -interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 -// -// 12.10 - RAM Correctable Error Interrupt -// -interrupt void RAM_CORRECTABLE_ERROR_ISR(void); - -// -// 12.11 - Flash Correctable Error Interrupt -// -interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); - -// -// 12.12 - RAM Access Violation Interrupt -// -interrupt void RAM_ACCESS_VIOLATION_ISR(void); - -interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip Interrupt -interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow Interrupt -interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow Interrupt - -// -// Catch-all for PIE Reserved Locations for testing purposes: -// -interrupt void PIE_RESERVED_ISR(void); // Reserved ISR -interrupt void EMPTY_ISR(void); // Only does a return -interrupt void NOTUSED_ISR(void); // Unused ISR -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F28004x_PIEVECT_H definition -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h deleted file mode 100644 index 75dc6fb..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h +++ /dev/null @@ -1,193 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma_defines.h -// -// TITLE: #defines used in DMA examples -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F28004X_DMA_DEFINES_H_ -#define F28004X_DMA_DEFINES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// PERINTSEL bits -// -#define DMA_ADCAINT1 1 -#define DMA_ADCAINT2 2 -#define DMA_ADCAINT3 3 -#define DMA_ADCAINT4 4 -#define DMA_ADCAEVT 5 -#define DMA_ADCBINT1 6 -#define DMA_ADCBINT2 7 -#define DMA_ADCBINT3 8 -#define DMA_ADCBINT4 9 -#define DMA_ADCBEVT 10 -#define DMA_ADCCINT1 11 -#define DMA_ADCCINT2 12 -#define DMA_ADCCINT3 13 -#define DMA_ADCCINT4 14 -#define DMA_ADCCEVT 15 - -#define DMA_XINT1 29 -#define DMA_XINT2 30 -#define DMA_XINT3 31 -#define DMA_XINT4 32 -#define DMA_XINT5 33 - -#define DMA_EPWM1A 36 -#define DMA_EPWM1B 37 -#define DMA_EPWM2A 38 -#define DMA_EPWM2B 39 -#define DMA_EPWM3A 40 -#define DMA_EPWM3B 41 -#define DMA_EPWM4A 42 -#define DMA_EPWM4B 43 -#define DMA_EPWM5A 44 -#define DMA_EPWM5B 45 -#define DMA_EPWM6A 46 -#define DMA_EPWM6B 47 -#define DMA_EPWM7A 48 -#define DMA_EPWM7B 49 -#define DMA_EPWM8A 50 -#define DMA_EPWM8B 51 - -#define DMA_TINT0 68 -#define DMA_TINT1 69 -#define DMA_TINT2 70 - -#define DMA_ECAP1 75 -#define DMA_ECAP2 76 -#define DMA_ECAP3 77 -#define DMA_ECAP4 78 -#define DMA_ECAP5 79 -#define DMA_ECAP6 80 -#define DMA_ECAP7 81 - -#define DMA_SD1FLT1 96 -#define DMA_SD1FLT2 97 -#define DMA_SD1FLT3 98 -#define DMA_SD1FLT4 99 - -#define DMA_SPIATX 109 -#define DMA_SPIARX 110 -#define DMA_SPIBTX 111 -#define DMA_SPIBRX 112 - -#define DMA_LINATX 117 -#define DMA_LINARX 118 - -#define DMA_FSITXA 123 - -#define DMA_FSIRXA 125 - -#define DMA_CANAIF1 167 -#define DMA_CANAIF2 168 -#define DMA_CANAIF3 169 -#define DMA_CANBIF1 170 -#define DMA_CANBIF2 171 -#define DMA_CANBIF3 172 - -// -// OVERINTE bit -// -#define OVRFLOW_DISABLE 0x0 -#define OVEFLOW_ENABLE 0x1 - -// -// PERINTE bit -// -#define PERINT_DISABLE 0x0 -#define PERINT_ENABLE 0x1 - -// -// CHINTMODE bits -// -#define CHINT_BEGIN 0x0 -#define CHINT_END 0x1 - -// -// ONESHOT bits -// -#define ONESHOT_DISABLE 0x0 -#define ONESHOT_ENABLE 0x1 - -// -// CONTINOUS bit -// -#define CONT_DISABLE 0x0 -#define CONT_ENABLE 0x1 - -// -// SYNCE bit -// -#define SYNC_DISABLE 0x0 -#define SYNC_ENABLE 0x1 - -// -// SYNCSEL bit -// -#define SYNC_SRC 0x0 -#define SYNC_DST 0x1 - -// -// DATASIZE bit -// -#define SIXTEEN_BIT 0x0 -#define THIRTYTWO_BIT 0x1 - -// -// CHINTE bit -// -#define CHINT_DISABLE 0x0 -#define CHINT_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif - -#endif /*end of F28004X_DMA_DEFINES_H_ */ -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h deleted file mode 100644 index 2d4595f..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h +++ /dev/null @@ -1,342 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm_defines.h -// -// TITLE: f28004x Device EPWM Register Bit Defines -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_EPWM_DEFINES_H -#define F28004x_EPWM_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// TBCTL (Time-Base Control) -// - -// -// CTRMODE bits -// -#define TB_COUNT_UP 0x0 -#define TB_COUNT_DOWN 0x1 -#define TB_COUNT_UPDOWN 0x2 -#define TB_FREEZE 0x3 - -// -// PHSEN bit -// -#define TB_DISABLE 0x0 -#define TB_ENABLE 0x1 - -// -// PRDLD bit -// -#define TB_SHADOW 0x0 -#define TB_IMMEDIATE 0x1 - -// -// SYNCOSEL bits -// -#define TB_SYNC_IN 0x0 -#define TB_CTR_ZERO 0x1 -#define TB_CTR_CMPB 0x2 -#define TB_SYNC_DISABLE 0x3 - -// -// HSPCLKDIV and CLKDIV bits -// -#define TB_DIV1 0x0 -#define TB_DIV2 0x1 -#define TB_DIV4 0x2 - -// -// PHSDIR bit -// -#define TB_DOWN 0x0 -#define TB_UP 0x1 - -// -// CMPCTL (Compare Control) -// - -// -// LOADAMODE and LOADBMODE bits -// -#define CC_CTR_ZERO 0x0 -#define CC_CTR_PRD 0x1 -#define CC_CTR_ZERO_PRD 0x2 -#define CC_LD_DISABLE 0x3 - -// -// SHDWAMODE and SHDWBMODE bits -// -#define CC_SHADOW 0x0 -#define CC_IMMEDIATE 0x1 - -// -// AQCTLA and AQCTLB (Action Qualifier Control) -// - -// -// ZRO, PRD, CAU, CAD, CBU, CBD bits -// -#define AQ_NO_ACTION 0x0 -#define AQ_CLEAR 0x1 -#define AQ_SET 0x2 -#define AQ_TOGGLE 0x3 - -// -// DBCTL (Dead-Band Control) -// - -// -// OUT MODE bits -// -#define DB_DISABLE 0x0 -#define DBB_ENABLE 0x1 -#define DBA_ENABLE 0x2 -#define DB_FULL_ENABLE 0x3 - -// -// POLSEL bits -// -#define DB_ACTV_HI 0x0 -#define DB_ACTV_LOC 0x1 -#define DB_ACTV_HIC 0x2 -#define DB_ACTV_LO 0x3 - -// -// IN MODE -// -#define DBA_ALL 0x0 -#define DBB_RED_DBA_FED 0x1 -#define DBA_RED_DBB_FED 0x2 -#define DBB_ALL 0x3 - -// -// CHPCTL (chopper control) -// - -// -// CHPEN bit -// -#define CHP_DISABLE 0x0 -#define CHP_ENABLE 0x1 - -// -// CHPFREQ bits -// -#define CHP_DIV1 0x0 -#define CHP_DIV2 0x1 -#define CHP_DIV3 0x2 -#define CHP_DIV4 0x3 -#define CHP_DIV5 0x4 -#define CHP_DIV6 0x5 -#define CHP_DIV7 0x6 -#define CHP_DIV8 0x7 - -// -// CHPDUTY bits -// -#define CHP1_8TH 0x0 -#define CHP2_8TH 0x1 -#define CHP3_8TH 0x2 -#define CHP4_8TH 0x3 -#define CHP5_8TH 0x4 -#define CHP6_8TH 0x5 -#define CHP7_8TH 0x6 - -// -// TZSEL (Trip Zone Select) -// - -// -// CBCn and OSHTn bits -// -#define TZ_DISABLE 0x0 -#define TZ_ENABLE 0x1 - -// -// TZCTL (Trip Zone Control) -// - -// -// TZA and TZB bits -// -#define TZ_HIZ 0x0 -#define TZ_FORCE_HI 0x1 -#define TZ_FORCE_LO 0x2 -#define TZ_NO_CHANGE 0x3 - -// -// TZDCSEL (Trip Zone Digital Compare) -// - -// -// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits -// -#define TZ_EVT_DISABLE 0x0 -#define TZ_DCAH_LOW 0x1 -#define TZ_DCAH_HI 0x2 -#define TZ_DCAL_LOW 0x3 -#define TZ_DCAL_HI 0x4 -#define TZ_DCAL_HI_DCAH_LOW 0x5 - -#define TZ_DCBH_LOW 0x1 -#define TZ_DCBH_HI 0x2 -#define TZ_DCBL_LOW 0x3 -#define TZ_DCBL_HI 0x4 -#define TZ_DCBL_HI_DCBH_LOW 0x5 - -// -// ETSEL (Event Trigger Select) -// -#define ET_DCAEVT1SOC 0x0 -#define ET_CTR_ZERO 0x1 -#define ET_CTR_PRD 0x2 -#define ET_CTR_PRDZERO 0x3 -#define ET_CTRU_CMPA 0x4 -#define ET_CTRD_CMPA 0x5 -#define ET_CTRU_CMPB 0x6 -#define ET_CTRD_CMPB 0x7 - -// -// ETPS (Event Trigger Pre-scale) -// - -// -// INTPRD, SOCAPRD, SOCBPRD bits -// -#define ET_DISABLE 0x0 -#define ET_1ST 0x1 -#define ET_2ND 0x2 -#define ET_3RD 0x3 - -// -// HRPWM (High Resolution PWM) -// - -// -// HRCNFG -// -#define HR_DISABLE 0x0 -#define HR_REP 0x1 -#define HR_FEP 0x2 -#define HR_BEP 0x3 - -#define HR_CMP 0x0 -#define HR_PHS 0x1 - -#define HR_CTR_ZERO 0x0 -#define HR_CTR_PRD 0x1 -#define HR_CTR_ZERO_PRD 0x2 - -#define HR_NORM_B 0x0 -#define HR_INVERT_B 0x1 - -// -// DC (Digital Compare) -// - -// -// DCTRIPSEL -// -#define DC_TZ1 0x0 -#define DC_TZ2 0x1 -#define DC_TZ3 0x2 -#define DC_TRIPIN1 0x0 -#define DC_TRIPIN2 0x1 -#define DC_TRIPIN3 0x2 -#define DC_TRIPIN4 0x3 -#define DC_TRIPIN5 0x4 -#define DC_TRIPIN6 0x5 -#define DC_TRIPIN7 0x6 -#define DC_TRIPIN8 0x7 -#define DC_TRIPIN9 0x8 -#define DC_TRIPIN10 0x9 -#define DC_TRIPIN11 0xA -#define DC_TRIPIN12 0xB -// Reserved 0xC -#define DC_TRIPIN14 0xD -#define DC_TRIPIN15 0xE -#define DC_COMBINATION 0xF - -// -// DCFCTL -// -#define DC_SRC_DCAEVT1 0x0 -#define DC_SRC_DCAEVT2 0x1 -#define DC_SRC_DCBEVT1 0x2 -#define DC_SRC_DCBEVT2 0x3 - -#define DC_PULSESEL_PRD 0x0 -#define DC_PULSESEL_ZERO 0x1 -#define DC_PULSESEL_ZERO_PRD 0x2 - -#define DC_BLANK_DISABLE 0x0 -#define DC_BLANK_ENABLE 0x1 - -#define DC_BLANK_NOTINV 0x0 -#define DC_BLANK_INV 0x1 - -// -//DCACTL/DCBCTL -// -#define DC_EVT1 0x0 -#define DC_EVT2 0x0 -#define DC_EVT_FLT 0x1 -#define DC_EVT_SYNC 0x0 -#define DC_EVT_ASYNC 0x1 -#define DC_SOC_DISABLE 0x0 -#define DC_SOC_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_EPWM_DEFINES_H - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h b/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h deleted file mode 100644 index c1a6266..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h +++ /dev/null @@ -1,429 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_examples.h -// -// TITLE: f28004x Device Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_EXAMPLES_H -#define F28004x_EXAMPLES_H - -#ifdef __cplusplus -extern "C" { -#endif - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select SYSPLL integer multiplier -//***************************************************************************** - -#define IMULT_0 0 -#define IMULT_1 1 -#define IMULT_2 2 -#define IMULT_3 3 -#define IMULT_4 4 -#define IMULT_5 5 -#define IMULT_6 6 -#define IMULT_7 7 -#define IMULT_8 8 -#define IMULT_9 9 -#define IMULT_10 10 -#define IMULT_11 11 -#define IMULT_12 12 -#define IMULT_13 13 -#define IMULT_14 14 -#define IMULT_15 15 -#define IMULT_16 16 -#define IMULT_17 17 -#define IMULT_18 18 -#define IMULT_19 19 -#define IMULT_20 20 -#define IMULT_21 21 -#define IMULT_22 22 -#define IMULT_23 23 -#define IMULT_24 24 -#define IMULT_25 25 -#define IMULT_26 26 -#define IMULT_27 27 -#define IMULT_28 28 -#define IMULT_29 29 -#define IMULT_30 30 -#define IMULT_31 31 -#define IMULT_32 32 -#define IMULT_33 33 -#define IMULT_34 34 -#define IMULT_35 35 -#define IMULT_36 36 -#define IMULT_37 37 -#define IMULT_38 38 -#define IMULT_39 39 -#define IMULT_40 40 -#define IMULT_41 41 -#define IMULT_42 42 -#define IMULT_43 43 -#define IMULT_44 44 -#define IMULT_45 45 -#define IMULT_46 46 -#define IMULT_47 47 -#define IMULT_48 48 -#define IMULT_49 49 -#define IMULT_50 50 -#define IMULT_51 51 -#define IMULT_52 52 -#define IMULT_53 53 -#define IMULT_54 54 -#define IMULT_55 55 -#define IMULT_56 56 -#define IMULT_57 57 -#define IMULT_58 58 -#define IMULT_59 59 -#define IMULT_60 60 -#define IMULT_61 61 -#define IMULT_62 62 -#define IMULT_63 63 -#define IMULT_64 64 -#define IMULT_65 65 -#define IMULT_66 66 -#define IMULT_67 67 -#define IMULT_68 68 -#define IMULT_69 69 -#define IMULT_70 70 -#define IMULT_71 71 -#define IMULT_72 72 -#define IMULT_73 73 -#define IMULT_74 74 -#define IMULT_75 75 -#define IMULT_76 76 -#define IMULT_77 77 -#define IMULT_78 78 -#define IMULT_79 79 -#define IMULT_80 80 -#define IMULT_81 81 -#define IMULT_82 82 -#define IMULT_83 83 -#define IMULT_84 84 -#define IMULT_85 85 -#define IMULT_86 86 -#define IMULT_87 87 -#define IMULT_88 88 -#define IMULT_89 89 -#define IMULT_90 90 -#define IMULT_91 91 -#define IMULT_92 92 -#define IMULT_93 93 -#define IMULT_94 94 -#define IMULT_95 95 -#define IMULT_96 96 -#define IMULT_97 97 -#define IMULT_98 98 -#define IMULT_99 99 -#define IMULT_100 100 -#define IMULT_101 101 -#define IMULT_102 102 -#define IMULT_103 103 -#define IMULT_104 104 -#define IMULT_105 105 -#define IMULT_106 106 -#define IMULT_107 107 -#define IMULT_108 108 -#define IMULT_109 109 -#define IMULT_110 110 -#define IMULT_111 111 -#define IMULT_112 112 -#define IMULT_113 113 -#define IMULT_114 114 -#define IMULT_115 115 -#define IMULT_116 116 -#define IMULT_117 117 -#define IMULT_118 118 -#define IMULT_119 119 -#define IMULT_120 120 -#define IMULT_121 121 -#define IMULT_122 122 -#define IMULT_123 123 -#define IMULT_124 124 -#define IMULT_125 125 -#define IMULT_126 126 -#define IMULT_127 127 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select SYSPLL fractional multiplier -//***************************************************************************** - -#define FMULT_0 0 -#define FMULT_0pt25 1 -#define FMULT_0pt5 2 -#define FMULT_0pt75 3 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select divsel for SYSPLL -//***************************************************************************** - -#define PLLCLK_BY_1 0 -#define PLLCLK_BY_2 1 -#define PLLCLK_BY_4 2 -#define PLLCLK_BY_6 3 -#define PLLCLK_BY_8 4 -#define PLLCLK_BY_10 5 -#define PLLCLK_BY_12 6 -#define PLLCLK_BY_14 7 -#define PLLCLK_BY_16 8 -#define PLLCLK_BY_18 9 -#define PLLCLK_BY_20 10 -#define PLLCLK_BY_22 11 -#define PLLCLK_BY_24 12 -#define PLLCLK_BY_26 13 -#define PLLCLK_BY_28 14 -#define PLLCLK_BY_30 15 -#define PLLCLK_BY_32 16 -#define PLLCLK_BY_34 17 -#define PLLCLK_BY_36 18 -#define PLLCLK_BY_38 19 -#define PLLCLK_BY_40 20 -#define PLLCLK_BY_42 21 -#define PLLCLK_BY_44 22 -#define PLLCLK_BY_46 23 -#define PLLCLK_BY_48 24 -#define PLLCLK_BY_50 25 -#define PLLCLK_BY_52 26 -#define PLLCLK_BY_54 27 -#define PLLCLK_BY_56 28 -#define PLLCLK_BY_58 29 -#define PLLCLK_BY_60 30 -#define PLLCLK_BY_62 31 -#define PLLCLK_BY_64 32 -#define PLLCLK_BY_66 33 -#define PLLCLK_BY_68 34 -#define PLLCLK_BY_70 35 -#define PLLCLK_BY_72 36 -#define PLLCLK_BY_74 37 -#define PLLCLK_BY_76 38 -#define PLLCLK_BY_78 39 -#define PLLCLK_BY_80 40 -#define PLLCLK_BY_82 41 -#define PLLCLK_BY_84 42 -#define PLLCLK_BY_86 43 -#define PLLCLK_BY_88 44 -#define PLLCLK_BY_90 45 -#define PLLCLK_BY_92 46 -#define PLLCLK_BY_94 47 -#define PLLCLK_BY_96 48 -#define PLLCLK_BY_98 49 -#define PLLCLK_BY_100 50 -#define PLLCLK_BY_102 51 -#define PLLCLK_BY_104 52 -#define PLLCLK_BY_106 53 -#define PLLCLK_BY_108 54 -#define PLLCLK_BY_110 55 -#define PLLCLK_BY_112 56 -#define PLLCLK_BY_114 57 -#define PLLCLK_BY_116 58 -#define PLLCLK_BY_118 59 -#define PLLCLK_BY_120 60 -#define PLLCLK_BY_122 61 -#define PLLCLK_BY_124 62 -#define PLLCLK_BY_126 63 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select clock source -//***************************************************************************** - -#define INT_OSC2 0 // Internal oscillator 2 -#define XTAL_OSC 1 // External oscillator, crystal mode -#define INT_OSC1 2 // Internal oscillator 1 -#define XTAL_OSC_SE 5 // External oscillator, single-ended mode - -/*----------------------------------------------------------------------------- - Specify the clock rate of the CPU (SYSCLKOUT) in nS. - - Take into account the input clock frequency and the PLL multiplier - selected in step 1. - - Use one of the values provided, or define your own. - The trailing L is required tells the compiler to treat - the number as a 64-bit value. - - Only one statement should be uncommented. - - Example: 100 MHz devices: - CLKIN is a 10 MHz crystal or internal 10 MHz oscillator - - In step 1 the user specified the PLL multiplier = 0x20 for a - 100 MHz CPU clock (SYSCLKOUT = 100 MHz). - - In this case, the CPU_RATE will be 10.000L - Uncomment the line: #define CPU_RATE 10.000L - ------------------------------------------------------------------------------*/ - -#define CPU_RATE 10.00L // for a 100MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 11.111L // for a 90MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 12.500L // for a 80MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 25.000L // for a 40MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) - -// -// The following pointer to a function call calibrates the ADC reference, -// DAC offset, and internal oscillators -// -#define Device_cal (void (*)(void))0x070282 - -// -// The following pointers to functions calibrate the ADC linearity. Use this -// in the AdcSetMode(...) function only -// -#define CalAdcaINL (void (*)(void))0x0703B4 -#define CalAdcbINL (void (*)(void))0x0703B2 -#define CalAdccINL (void (*)(void))0x0703B0 -#define CalAdcdINL (void (*)(void))0x0703AE - -// -// The following pointer to a function call looks up the ADC offset trim for a -// given condition. Use this in the AdcSetMode(...) function only. -// -#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC - -// -// Include Example Header Files: -// - -#include "f28004x_globalprototypes.h" //Prototypes for global functions - //within the .c files. -#include "f28004x_adc_defines.h" -#include "f28004x_cputimervars.h" -#include "f28004x_epwm_defines.h" -#include "f28004x_gpio_defines.h" // Macros used for GPIO support code -#include "f28004x_pie_defines.h" // Macros used for PIE examples -#include "f28004x_sysctrl_defines.h" // Macros used for LPM support code -#include "f28004x_dma_defines.h" // Macros used for DMA support code -#include "f28004x_cla_defines.h" //Macros used for CLA support code - -#define PARTNO_28004xPACKAGEHERE 0x00 - -#define CPU_FRQ_100MHZ 1 - -// -// Include files not used with F/BIOS -// -#ifndef F28_BIOS -#include "f28004x_defaultisr.h" -#endif - -extern void F28x_usDelay(long LoopCount); -// DO NOT MODIFY THIS LINE. -#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) - -// -// Useful Timer Operations -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F28004x_EXAMPLES_H definition - -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h b/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h deleted file mode 100644 index 0d6a25a..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_globalprototypes.h -// -// TITLE: Global prototypes for f28004x Examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_GLOBALPROTOTYPES_H -#define F28004x_GLOBALPROTOTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// shared global function prototypes -// -extern void EnableInterrupts(void); -extern void InitPeripheralClocks(void); -extern void DisablePeripheralClocks(void); -extern void InitPieCtrl(void); -extern void InitPieVectTable(void); -extern void InitSpi(void); -extern void InitSpiGpio(void); -extern void InitSpiaGpio(void); -extern void InitSysCtrl(void); -extern void InitSysPll(Uint16 clock_source, - Uint16 imult, Uint16 fmult, Uint16 divsel); -extern bool IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult); - -// -// For compatibility with previous versions -// -#define KickDog ServiceDog -extern void ServiceDog(void); -extern void DisableDog(void); - -extern Uint16 CsmUnlock(void); -extern void SysIntOsc1Sel (void); -extern void SysIntOsc2Sel (void); -extern void SysXtalOscSel (void); -extern void SysXtalOscSESel (void); - -// -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -extern void InitFlash(void); -extern void FlashOff(void); - -// -// LPM functions in f28004x_sysctrl.c -// -void IDLE(void); -void HALT(void); - -// -// ADC functions -// -extern void SetVREF(int module, int mode, int ref); - -// -// DMA Functions -// -extern void DMAInitialize(void); - -// -// DMA Channel 1 -// -extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, - int16 desbstep); -extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH1(void); - -// -// DMA Channel 2 -// -extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, - Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, Uint16 chinte); -extern void StartDMACH2(void); - -// -// DMA Channel 3 -// -extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH3(void); - -// -// DMA Channel 4 -// -extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH4(void); - -// -// DMA Channel 5 -// -extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH5(void); - -// -// DMA Channel 6 -// -extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); -extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH6(void); - -// -// GPIO Functions -// -extern void InitGpio(void); -extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, - Uint16 muxPosition); -extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, - Uint16 flags); -extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); -extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); -Uint16 GPIO_ReadPin(Uint16 gpioNumber); -void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); - -// External symbols created by the linker cmd file -// DSP28 examples will use these to relocate code from one LOAD location -// in Flash to a different RUN location in internal -// RAM -// -extern Uint16 RamfuncsLoadStart; -extern Uint16 RamfuncsLoadEnd; -extern Uint16 RamfuncsLoadSize; -extern Uint16 RamfuncsRunStart; -extern Uint16 RamfuncsRunEnd; -extern Uint16 RamfuncsRunSize; - - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_GLOBALPROTOTYPES_H - -// -// End of file. -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h deleted file mode 100644 index 5503c44..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h +++ /dev/null @@ -1,105 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio_defines.h -// -// TITLE: f28004x GPIO support definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_GPIO_DEFINES_H -#define F28004x_GPIO_DEFINES_H - -// -// Defines -// - -// -// CPU pin masters for GPIO_SelectPinMux() -// -#define GPIO_MUX_CPU1 0x0 -#define GPIO_MUX_CPU1CLA 0x1 - -// -// Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, -// QUAL6, and ASYNC) take up two bits and must be in the order specified. -// -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 -#define GPIO_PUSHPULL 0 -#define GPIO_PULLUP (1 << 0) -#define GPIO_INVERT (1 << 1) -#define GPIO_OPENDRAIN (1 << 2) -#define GPIO_SYNC (0x0 << 4) -#define GPIO_QUAL3 (0x1 << 4) -#define GPIO_QUAL6 (0x2 << 4) -#define GPIO_ASYNC (0x3 << 4) - -// -// Flags for GPIO_SetupLock(). -// -#define GPIO_UNLOCK 0 -#define GPIO_LOCK 1 - -// -// Helpful constants for array-based access to GPIO registers -// -#define GPY_CTRL_OFFSET (0x40/2) -#define GPY_DATA_OFFSET (0x8/2) - -#define GPYQSEL (0x2/2) -#define GPYMUX (0x6/2) -#define GPYDIR (0xA/2) -#define GPYPUD (0xC/2) -#define GPYINV (0x10/2) -#define GPYODR (0x12/2) -#define GPYGMUX (0x20/2) -#define GPYCSEL (0x28/2) -#define GPYLOCK (0x3C/2) -#define GPYCR (0x3E/2) - -#define GPYDAT (0x0/2) -#define GPYSET (0x2/2) -#define GPYCLEAR (0x4/2) -#define GPYTOGGLE (0x6/2) - -#endif // end of F28004x_GPIO_DEFINES_H definition - -// -// End of file -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h deleted file mode 100644 index 2cd6101..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h +++ /dev/null @@ -1,72 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pie_defines.h -// -// TITLE: #defines used in PIE examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_PIE_DEFINES_H -#define F28004x_PIE_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIEACK_GROUP1 0x0001 -#define PIEACK_GROUP2 0x0002 -#define PIEACK_GROUP3 0x0004 -#define PIEACK_GROUP4 0x0008 -#define PIEACK_GROUP5 0x0010 -#define PIEACK_GROUP6 0x0020 -#define PIEACK_GROUP7 0x0040 -#define PIEACK_GROUP8 0x0080 -#define PIEACK_GROUP9 0x0100 -#define PIEACK_GROUP10 0x0200 -#define PIEACK_GROUP11 0x0400 -#define PIEACK_GROUP12 0x0800 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_PIE_DEFINES_H - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h deleted file mode 100644 index e54a9b9..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h +++ /dev/null @@ -1,59 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl_defines.h -// -// TITLE: f28004x LPM support definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_SYSCTRL_DEFINES_H -#define F28004x_SYSCTRL_DEFINES_H - -// -// Defines -// -#define LPM_IDLE 0x0 -#define LPM_HALT 0x2 -#define LPM_HIB 0x3 - -#endif // end of F28004x_SYSCTRL_DEFINES_H definition - -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c b/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c deleted file mode 100644 index 1c99c84..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c +++ /dev/null @@ -1,102 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc.c -// -// TITLE: F28004x ADC Support Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Header File Include File -#include "f28004x_examples.h" // Examples Include File - -// -// SetVREF - Set Vref mode. Function to select reference mode and offset trim. -// Offset trim for Internal VREF 3.3 is unique. All other modes use the same -// offset trim. Also note that when the mode parameter is ADC_EXTERNAL, the -// ref parameter has no effect. -// -void SetVREF(int module, int mode, int ref) -{ - Uint16 *offset, offval; - - // - // Define offset locations from OTP - // - offset = (Uint16 *)(0x70594 + (module * 6)); - - if((mode == ADC_INTERNAL) && (ref == ADC_VREF3P3)) - { - offval = (*offset) >> 8; // Internal / 1.65v mode offset - } - else - { - offval = (*offset) & 0xFF; // All other modes - } - - // - // Write offset trim values and configure reference modes - // - EALLOW; - switch(module) - { - case 0: - AdcaRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFASEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFA2P5SEL = ref; - break; - case 1: - AdcbRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFBSEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFB2P5SEL = ref; - break; - case 2: - AdccRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFCSEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFC2P5SEL = ref; - break; - default: - break; - } - EDIS; -} - -// -// End of File -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm deleted file mode 100644 index e34559f..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm +++ /dev/null @@ -1,111 +0,0 @@ -;//########################################################################### -;// -;// FILE: f28004x_codestartbranch.asm -;// -;// TITLE: Branch for redirecting code execution after boot. -;// -;// For these examples, code_start is the first code that is executed after -;// exiting the boot ROM code. -;// -;// The codestart section in the linker cmd file is used to physically place -;// this code at the correct memory location. This section should be placed -;// at the location the BOOT ROM will re-direct the code to. For example, -;// for boot to FLASH this code will be located at 0x80000. -;// -;// In addition, the example f28004x projects are setup such that the codegen -;// entry point is also set to the codestart label. This is done by linker -;// option -e in the project build options. When the debugger loads the code, -;// it will automatically set the PC to the "entry point" address indicated by -;// the -e linker option. In this case the debugger is simply assigning the PC, -;// it is not the same as a full reset of the device. -;// -;// The compiler may warn that the entry point for the project is other then -;// _c_init00. _c_init00 is the C environment setup and is run before -;// main() is entered. The codestart code will re-direct the execution -;// to _c_init00 and thus there is no worry and this warning can be ignored. -;// -;//########################################################################### -;// $TI Release: F28004x Support Library v1.05.00.00 $ -;// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;// $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;//########################################################################### - -*********************************************************************** - -WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 - - .ref _c_int00 - .global code_start - -*********************************************************************** -* Function: codestart section -* -* Description: Branch to code starting point -*********************************************************************** - - .sect "codestart" - -code_start: - .if WD_DISABLE == 1 - LB wd_disable ;Branch to watchdog disable code - .else - LB _c_int00 ;Branch to start of boot._asm in RTS library - .endif - -;end codestart section - -*********************************************************************** -* Function: wd_disable -* -* Description: Disables the watchdog timer -*********************************************************************** - .if WD_DISABLE == 1 - - .text -wd_disable: - SETC OBJMODE ;Set OBJMODE for 28x object code - EALLOW ;Enable EALLOW protected register access - MOVZ DP, #7029h>>6 ;Set data page for WDCR register - MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD - EDIS ;Disable EALLOW protected register access - LB _c_int00 ;Branch to start of boot._asm in RTS library - - .endif - -;end wd_disable - - .end - -;// -;// End of file. -;// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c b/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c deleted file mode 100644 index a4583a3..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c +++ /dev/null @@ -1,194 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimers.c -// -// TITLE: f28004x CPU 32-bit Timers Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File - -// -// Globals -// -struct CPUTIMER_VARS CpuTimer0; -struct CPUTIMER_VARS CpuTimer1; -struct CPUTIMER_VARS CpuTimer2; - -// -// InitCpuTimers - This function initializes all three CPU timers -// to a known state. -// -void -InitCpuTimers(void) -{ - // - // CPU Timer 0 - // Initialize address pointers to respective timer registers - // - CpuTimer0.RegsAddr = &CpuTimer0Regs; - - // - // Initialize timer period to maximum - // - CpuTimer0Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) - // - CpuTimer0Regs.TPR.all = 0; - CpuTimer0Regs.TPRH.all = 0; - - // - // Make sure timer is stopped - // - CpuTimer0Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value - // - CpuTimer0Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters - // - CpuTimer0.InterruptCount = 0; - - // - // CPU Timer 1 and 2 - // Initialize address pointers to respective timer registers - // - CpuTimer1.RegsAddr = &CpuTimer1Regs; - CpuTimer2.RegsAddr = &CpuTimer2Regs; - - // - // Initialize timer period to maximum - // - CpuTimer1Regs.PRD.all = 0xFFFFFFFF; - CpuTimer2Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) - // - CpuTimer1Regs.TPR.all = 0; - CpuTimer1Regs.TPRH.all = 0; - CpuTimer2Regs.TPR.all = 0; - CpuTimer2Regs.TPRH.all = 0; - - // - // Make sure timers are stopped - // - CpuTimer1Regs.TCR.bit.TSS = 1; - CpuTimer2Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value - // - CpuTimer1Regs.TCR.bit.TRB = 1; - CpuTimer2Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters - // - CpuTimer1.InterruptCount = 0; - CpuTimer2.InterruptCount = 0; -} - -// -// ConfigCpuTimer - This function initializes the selected timer to the period -// specified by the "Freq" and "Period" parameters. The "Freq" is entered -// as "MHz" and the "Period" in "uSeconds". The timer is held in the stopped -// state after configuration. -// -void -ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) -{ - Uint32 temp; - - // - // Initialize timer period - // - Timer->CPUFreqInMHz = Freq; - Timer->PeriodInUSec = Period; - temp = (long) (Freq * Period); - Timer->RegsAddr->PRD.all = temp; - - // - // Set pre-scale counter to divide by 1 (SYSCLKOUT) - // - Timer->RegsAddr->TPR.all = 0; - Timer->RegsAddr->TPRH.all = 0; - - // - // Initialize timer control register - // - - // - // 1 = Stop timer, 0 = Start/Restart Timer - // - Timer->RegsAddr->TCR.bit.TSS = 1; - - // - // 1 = reload timer - // - Timer->RegsAddr->TCR.bit.TRB = 1; - Timer->RegsAddr->TCR.bit.SOFT = 0; - - // - // Timer Free Run Disabled - // - Timer->RegsAddr->TCR.bit.FREE = 0; - - // - // 0 = Disable 1 = Enable Timer Interrupt - // - Timer->RegsAddr->TCR.bit.TIE = 1; - - // - // Reset interrupt counter - // - Timer->InterruptCount = 0; -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm deleted file mode 100644 index 151c1d0..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm +++ /dev/null @@ -1,186 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_dcsm_z1otp.asm -;; -;; TITLE: Dual Code Security Module Zone 1 OTP -;; -;; DESCRIPTION: -;; -;; This file is used to specify Z1 DCSM OTP and zone select block -;; values to program. -;; -;; In addition, the 60 reserved values after the zone select block -;; are all programmed to 0x0000 as well. -;; -;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time -;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order -;; to program the below memory sections, user should uncomment the .long words -;; of each section and change the value to what is desired. Additionally, the -;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a -;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section -;; that is being programmed. -;; -;; -;; !!IMPORTANT!! The "bx_dcsm_otp_z1_linkpointer" section contains the -;; Z1 LINKPOINTER which determines the location of the Z1 Zone Select block. -;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z1_linkpointer" -;; section in the *_dcsm_lnk.cmd command linker file must also change to an -;; address decoded from the value specified in the Z1-LINKPOINTER location. -;; -;; -;; The "bx_dcsm_zsel_z1" section contains the actual Z1 Zone Select Block -;; values that will be linked and programmed into to the DCSM Z1 OTP Zone -;; Select block in OTP. -;; These values must be known in order to unlock the CSM module. -;; -;; It is recommended that all values be left as 0xFFFFFFFF during code -;; development. Values of 0xFFFFFFFF do not activate code security and dummy -;; reads of the Z1 DCSM PWL registers is all that is required to unlock the -;; CSM. When code development is complete, modify values to activate the -;; code security module. -;; -;; ******************************WARNING*************************************** -;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users -;; intend to comeback and re-program any of the bits to '0' in future. If user -;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would -;; get programmed to a non erased state and users won't be able to comeback -;; and re-program the OTP location to another value. Please refer to DCSM -;; chapter of device TRM for more details on ECC for the locations in DCSM. -;; -;; Hence TI ships this example commenting out the initialization of all the -;; below locations. -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .sect "b0_dcsm_otp_z1_linkpointer" -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_gpreg" -;; -;; See the ROM Code and Peripheral Booting chapter of TRM for more details. -;; -;; Below is a description of the bit fields of Z1OTP_BOOTPIN_CONFIG -;; used by Boot ROM. -;; -;; | Key (31-24) | BMSP2 (23-16) | BMSP1 (15-8) | BMSP0 (7-0) | -;; -;; Below is a description of the bit fields of Z1OTP_GPREG2 used by -;; Boot ROM. -;; -;; | Key (31-24) | RSVD (23-8) | RSVD (7-6) | ESP (5-4) | RSVD (3-0) | -;; -;; .long 0xFFFFFFFF ;Z1OTP_BOOTPIN_CONFIG -;; .long 0xFFFFFFFF ;Z1OTP_GPREG2 - - .sect "b0_dcsm_otp_z1_pswdlock" -;; .long 0xFFFFFFFF ;Z1OTP_PSWDLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_crclock" -;; .long 0xFFFFFFFF ;Z1OTP_CRCLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_bootctrl" -;; -;; See the ROM Code and Peripheral Booting chapter of TRM for more details. -;; -;; Below is a description of the bit fields of Z1OTP_BOOTDEF_LOW used by -;; Boot ROM. -;; -;; | BOOT_DEF3(31-24) | BOOT_DEF2(23-16) | BOOT_DEF1(15-8) | BOOT_DEF0(7-0) | -;; -;; Below is a description of the bit fields of Z1OTP_BOOTDEF_HIGH -;; used by Boot ROM. -;; -;; | BOOT_DEF7(31-24) | BOOT_DEF6(23-16) | BOOT_DEF5(15-8) | BOOT_DEF4(7-0) | -;; -;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_LOW -;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_HIGH - - .sect "b0_dcsm_zsel_z1" - -;; .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYRAM -;; .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;B0_Z1OTP_GRABRAM -;; .long 0xFFFFFFFF ;B0_Z1OTP_GRABSECT - -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD0 (LSW of 128-bit password) -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD1 -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD2 -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD3 (MSW of 128-bit password) - - .sect "b1_dcsm_otp_z1_linkpointer" -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b1_dcsm_zsel_z1" -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z1OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z1OTP_GRABSECT - -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved - -;;---------------------------------------------------------------------- - -;; For code security operation,after development has completed, prior to -;; production, all other zone select block locations should be programmed -;; to 0x0000 for maximum security. -;; If the first zone select block at offset 0x10 is used, the section -;; "dcsm_rsvd_z1" can be used to program these locations to 0x0000. -;; This code is commented out for development. - -;; .sect "dcsm_rsvd_z1" -;; .loop (1e0h) -;; .int 0x0000 -;; .endloop - - -;;############################################################################# -;; End of file -;;############################################################################# diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm deleted file mode 100644 index 99d093a..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm +++ /dev/null @@ -1,159 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_dcsm_z2otp.asm -;; -;; TITLE: Dual Code Security Module Zone 2 OTP -;; -;; DESCRIPTION: -;; -;; This file is used to specify Z2 DCSM OTP and zone select block -;; values to program. -;; -;; In addition, the 60 reserved values after the zone select block -;; are all programmed to 0x0000 as well. -;; -;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time -;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order -;; to program the below memory sections, user should uncomment the .long words -;; of each section and change the value to what is desired. Additionally, the -;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a -;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section -;; that is being programmed. -;; -;; -;; !!IMPORTANT!! The "bx_dcsm_otp_z2_linkpointer" section contains the -;; Z2 LINKPOINTER which determines the location of the Z2 Zone Select block. -;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z2_linkpointer" -;; section in the *_dcsm_lnk.cmd command linker file must also change to an -;; address decoded from the value specified in the Z2-LINKPOINTER location. -;; -;; -;; The "bx_dcsm_zsel_z2" section contains the actual Z2 Zone Select Block -;; values that will be linked and programmed into to the DCSM Z2 OTP Zone -;; Select block in OTP. -;; These values must be known in order to unlock the CSM module. -;; -;; It is recommended that all values be left as 0xFFFFFFFF during code -;; development. Values of 0xFFFFFFFF do not activate code security and dummy -;; reads of the Z2 DCSM PWL registers is all that is required to unlock the -;; CSM. When code development is complete, modify values to activate the -;; code security module. -;; -;; ******************************WARNING*************************************** -;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users -;; intend to comeback and re-program any of the bits to '0' in future. If user -;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would -;; get programmed to a non erased state and users won't be able to comeback -;; and re-program the OTP location to another value. Please refer to DCSM -;; chapter of device TRM for more details on ECC for the locations in DCSM. -;; -;; Hence TI ships this example commenting out the initialization of all the -;; below locations. -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .sect "b0_dcsm_otp_z2_linkpointer" -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_gpreg" -;; .long 0xFFFFFFFF ;Z2OTP_BOOTPIN_CONFIG -;; .long 0xFFFFFFFF ;Z2OTP_GPREG2 - - .sect "b0_dcsm_otp_z2_pswdlock" -;; .long 0xFFFFFFFF ;Z2OTP_PSWDLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_crclock" -;; .long 0xFFFFFFFF ;Z2OTP_CRCLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_bootctrl" -;; .long 0xFFFFFFFF ;Z2OTP_GPREG3 -;; .long 0xFFFFFFFF ;Z2OTP_BOOTCTRL - - .sect "b0_dcsm_zsel_z2" -;; .long 0xFFFFFFFF ;B0_Z2OTP_EXEONLYRAM -;; .long 0xFFFFFFFF ;B0_Z2OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;B0_Z2OTP_GRABRAM -;; .long 0xFFFFFFFF ;B0_Z2OTP_GRABSECT - -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD0 (LSW of 128-bit password) -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD1 -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD2 -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD3 (MSW of 128-bit password) - - .sect "b1_dcsm_otp_z2_linkpointer" -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b1_dcsm_zsel_z2" -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z2OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z2OTP_GRABSECT - -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved - -;;---------------------------------------------------------------------- - -;; For code security operation,after development has completed, prior to -;; production, all other zone select block locations should be programmed -;; to 0x0000 for maximum security. -;; If the first zone select block at offset 0x10 is used, the section -;; "dcsm_rsvd_z2" can be used to program these locations to 0x0000. -;; This code is commented out for development. - -;; .sect "dcsm_rsvd_z2" -;; .loop (1e0h) -;; .int 0x0000 -;; .endloop - - -;;############################################################################# -;; End of file -;;############################################################################# diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c b/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c deleted file mode 100644 index 06b2643..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c +++ /dev/null @@ -1,2780 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_defaultisr.c -// -// TITLE: f28004x Device Default Interrupt Service Routines -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // F28004x Header File Include File -#include "f28004x_examples.h" // F28004x Examples Include File - -// -// TIMER1_ISR - CPU Timer 1 Interrupt -// -interrupt void -TIMER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// TIMER2_ISR - CPU Timer 2 Interrupt -// -interrupt void -TIMER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DATALOG_ISR - Datalogging Interrupt -// -interrupt void -DATALOG_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RTOS_ISR - RTOS Interrupt -// -interrupt void -RTOS_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EMU_ISR - Emulation Interrupt -// -interrupt void -EMU_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// NMI_ISR - Non-Maskable Interrupt -// -interrupt void -NMI_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ILLEGAL_ISR - Illegal Operation Trap -// -interrupt void -ILLEGAL_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER1_ISR - User Defined Trap 1 -// -interrupt void -USER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER2_ISR - User Defined Trap 2 -// -interrupt void -USER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER3_ISR - User Defined Trap 3 -// -interrupt void -USER3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER4_ISR - User Defined Trap 4 -// -interrupt void -USER4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER5_ISR - User Defined Trap 5 -// -interrupt void -USER5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER6_ISR - User Defined Trap 6 -// -interrupt void -USER6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER7_ISR - User Defined Trap 7 -// -interrupt void -USER7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER8_ISR - User Defined Trap 8 -// -interrupt void -USER8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER9_ISR - User Defined Trap 9 -// -interrupt void -USER9_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER10_ISR - User Defined Trap 10 -// -interrupt void -USER10_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER11_ISR - User Defined Trap 11 -// -interrupt void -USER11_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER12_ISR - User Defined Trap 12 -// -interrupt void -USER12_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA1_ISR - ADCA Interrupt 1 -// -interrupt void -ADCA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB1_ISR - ADCB Interrupt 1 -// -interrupt void -ADCB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC1_ISR - ADCC Interrupt 1 -// -interrupt void -ADCC1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT1_ISR - XINT1 Interrupt -// -interrupt void -XINT1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT2_ISR - XINT2 Interrupt -// -interrupt void -XINT2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// TIMER0_ISR - Timer 0 Interrupt -// -interrupt void -TIMER0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// WAKE_ISR - Halt Wakeup Interrupt -// -interrupt void -WAKE_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM1_TZ_ISR - ePWM1 Trip Zone Interrupt -// -interrupt void -EPWM1_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM2_TZ_ISR - ePWM2 Trip Zone Interrupt -// -interrupt void -EPWM2_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM3_TZ_ISR - ePWM3 Trip Zone Interrupt -// -interrupt void -EPWM3_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM4_TZ_ISR - ePWM4 Trip Zone Interrupt -// -interrupt void -EPWM4_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM5_TZ_ISR - ePWM5 Trip Zone Interrupt -// -interrupt void -EPWM5_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM6_TZ_ISR - ePWM6 Trip Zone Interrupt -// -interrupt void -EPWM6_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM7_TZ_ISR - ePWM7 Trip Zone Interrupt -// -interrupt void -EPWM7_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM8_TZ_ISR - ePWM8 Trip Zone Interrupt -// -interrupt void -EPWM8_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM1_ISR - ePWM1 Interrupt -// -interrupt void -EPWM1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM2_ISR - ePWM2 Interrupt -// -interrupt void -EPWM2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM3_ISR - ePWM3 Interrupt -// -interrupt void -EPWM3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM4_ISR - ePWM4 Interrupt -// -interrupt void -EPWM4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM5_ISR - ePWM5 Interrupt -// -interrupt void -EPWM5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM6_ISR - ePWM6 Interrupt -// -interrupt void -EPWM6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM7_ISR - ePWM7 Interrupt -// -interrupt void -EPWM7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM8_ISR - ePWM8 Interrupt -// -interrupt void -EPWM8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP1_ISR - eCAP1 Interrupt -// -interrupt void -ECAP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP2_ISR - eCAP2 Interrupt -// -interrupt void -ECAP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP3_ISR - eCAP3 Interrupt -// -interrupt void -ECAP3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP4_ISR - eCAP4 Interrupt -// -interrupt void -ECAP4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP5_ISR - eCAP5 Interrupt -// -interrupt void -ECAP5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP6_ISR - eCAP6 Interrupt -// -interrupt void -ECAP6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP7_ISR - eCAP7 Interrupt -// -interrupt void -ECAP7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP6_2_ISR - eCAP6_2 Interrupt -// -interrupt void -ECAP6_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP7_2_ISR - eCAP7_2 Interrupt -// -interrupt void -ECAP7_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EQEP1_ISR - eQEP1 Interrupt -// -interrupt void -EQEP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EQEP2_ISR - eQEP2 Interrupt -// -interrupt void -EQEP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIA_RX_ISR - SPIA Receive Interrupt -// -interrupt void -SPIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIA_TX_ISR - SPIA Transmit Interrupt -// -interrupt void -SPIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIB_RX_ISR - SPIB Receive Interrupt -// -interrupt void -SPIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIB_TX_ISR - SPIB Transmit Interrupt -// -interrupt void -SPIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH1_ISR - DMA Channel 1 Interrupt -// -interrupt void -DMA_CH1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH2_ISR - DMA Channel 2 Interrupt -// -interrupt void -DMA_CH2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH3_ISR - DMA Channel 3 Interrupt -// -interrupt void -DMA_CH3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH4_ISR - DMA Channel 4 Interrupt -// -interrupt void -DMA_CH4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH5_ISR - DMA Channel 5 Interrupt -// -interrupt void -DMA_CH5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH6_ISR - DMA Channel 6 Interrupt -// -interrupt void -DMA_CH6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// I2CA_ISR - I2CA Interrupt 1 -// -interrupt void -I2CA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// I2CA_FIFO_ISR - I2CA Interrupt 2 -// -interrupt void -I2CA_FIFO_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIA_RX_ISR - SCIA Receive Interrupt -// -interrupt void -SCIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIA_TX_ISR - SCIA Transmit Interrupt -// -interrupt void -SCIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIB_RX_ISR - SCIB Receive Interrupt -// -interrupt void -SCIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIB_TX_ISR - SCIB Transmit Interrupt -// -interrupt void -SCIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANA0_ISR - CANA Interrupt 0 -// -interrupt void -CANA0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANA1_ISR - CANA Interrupt 1 -// -interrupt void -CANA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANB0_ISR - CANB Interrupt 0 -// -interrupt void -CANB0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANB1_ISR - CANB Interrupt 1 -// -interrupt void -CANB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA_EVT_ISR - ADCA Event Interrupt -// -interrupt void -ADCA_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA2_ISR - ADCA Interrupt 2 -// -interrupt void -ADCA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA3_ISR - ADCA Interrupt 3 -// -interrupt void -ADCA3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA4_ISR - ADCA Interrupt 4 -// -interrupt void -ADCA4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB_EVT_ISR - ADCB Event Interrupt -// -interrupt void -ADCB_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB2_ISR - ADCB Interrupt 2 -// -interrupt void -ADCB2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB3_ISR - ADCB Interrupt 3 -// -interrupt void -ADCB3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB4_ISR - ADCB Interrupt 4 -// -interrupt void -ADCB4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_1_ISR - CLA1 Interrupt 1 -// -interrupt void -CLA1_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_2_ISR - CLA1 Interrupt 2 -// -interrupt void -CLA1_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_3_ISR - CLA1 Interrupt 3 -// -interrupt void -CLA1_3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_4_ISR - CLA1 Interrupt 4 -// -interrupt void -CLA1_4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_5_ISR - CLA1 Interrupt 5 -// -interrupt void -CLA1_5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_6_ISR - CLA1 Interrupt 6 -// -interrupt void -CLA1_6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_7_ISR - CLA1 Interrupt 7 -// -interrupt void -CLA1_7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_8_ISR - CLA1 Interrupt 8 -// -interrupt void -CLA1_8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT3_ISR - XINT3 Interrupt -// -interrupt void -XINT3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT4_ISR - XINT4 Interrupt -// -interrupt void -XINT4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT5_ISR - XINT5 Interrupt -// -interrupt void -XINT5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FPU_OVERFLOW_ISR - FPU Overflow Interrupt -// -interrupt void -FPU_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FPU_UNDERFLOW_ISR - FPU Underflow Interrupt -// -interrupt void -FPU_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1_ISR - SDFM1 Interrupt -// -interrupt void -SD1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR1_ISR - SDFM1 DR Interrupt 1 -// -interrupt void -SD1DR1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR2_ISR - SDFM1 DR Interrupt 2 -// -interrupt void -SD1DR2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR3_ISR - SDFM1 DR Interrupt 3 -// -interrupt void -SD1DR3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR4_ISR - SDFM1 DR Interrupt 4 -// -interrupt void -SD1DR4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - - -// -// FSITXA1_ISR - FSITXA1_ISR Interrupt -// -interrupt void -FSITXA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSITXA2_ISR - FSITXA2_ISR Interrupt -// -interrupt void -FSITXA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSIRXA1_ISR - FSIRXA1_ISR Interrupt -// -interrupt void -FSIRXA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSIRXA2_ISR - FSIRXA2_ISR Interrupt -// -interrupt void -FSIRXA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1PROMCRC - CLA1PROMCRC Interrupt -// -interrupt void -CLA1PROMCRC_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// LINA_0 - LINA Interrupt 0 -// -interrupt void -LINA_0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// LINA_1 - LINA Interrupt 1 -// -interrupt void -LINA_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// PMBUSA - PMBUSA Interrupt -// -interrupt void -PMBUSA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC_EVT_ISR - ADCC Event Interrupt -// -interrupt void -ADCC_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC2_ISR - ADCC Interrupt 2 -// -interrupt void -ADCC2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC3_ISR - ADCC Interrupt 3 -// -interrupt void -ADCC3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC4_ISR - ADCC Interrupt 4 -// -interrupt void -ADCC4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RAM_CORRECTABLE_ERROR_ISR - RAM Correctable Error Interrupt -// -interrupt void -RAM_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FLASH_CORRECTABLE_ERROR_ISR - Flash Correctable Error Interrupt -// -interrupt void -FLASH_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RAM_ACCESS_VIOLATION_ISR - RAM Access Violation Interrupt -// -interrupt void -RAM_ACCESS_VIOLATION_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SYS_PLL_SLIP_ISR - System PLL Slip Interrupt -// -interrupt void -SYS_PLL_SLIP_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA_OVERFLOW_ISR - CLA Overflow Interrupt -// -interrupt void -CLA_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA_UNDERFLOW_ISR - CLA Underflow Interrupt -// -interrupt void -CLA_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Catch-all Default ISRs -// - -// -// PIE_RESERVED_ISR - Reserved ISR -// -interrupt void -PIE_RESERVED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// EMPTY_ISR - Only does a return -// -interrupt void -EMPTY_ISR(void) -{ - -} - -// -// NOTUSED_ISR - Unused ISR -// -interrupt void -NOTUSED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c b/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c deleted file mode 100644 index 3a245db..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c +++ /dev/null @@ -1,1104 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma.c -// -// TITLE: f28004x DMA Initialization & Support Functions. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "f28004x_device.h" -#include "f28004x_examples.h" - -// -// DMAInitialize - This function initializes the DMA to a known state. -// -void DMAInitialize(void) -{ - EALLOW; - - // - // Perform a hard reset on DMA - // - DmaRegs.DMACTRL.bit.HARDRESET = 1; - __asm (" nop"); // one NOP required after HARDRESET - - // - // Allow DMA to run free on emulation suspend - // - DmaRegs.DEBUGCTRL.bit.FREE = 1; - - EDIS; -} - -// -// DMACH1AddrConfig - DMA Channel 1 Address Configuration -// -void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to - // beginning of - // destination buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH1BurstConfig - DMA Channel 1 Burst size configuration -// -void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) - // x-ferred in a burst. - DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between - // each word x-ferred. - - EDIS; -} - -// -// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration -// -void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored - // when WRAP occurs. - DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored - // when WRAP occurs. - - EDIS; -} - -// -// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration -// -void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap - DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH1ModeConfig - DMA Channel 1 Mode configuration -// -void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; - DmaRegs.CH1.MODE.bit.PERINTSEL = 1; - DmaRegs.CH1.MODE.bit.PERINTE = perinte; - DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH1.MODE.bit.DATASIZE = datasize; - DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH1.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt and sync error flags - // - DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH1 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx1 = 1; - - EDIS; -} - -// -// StartDMACH1 - This function starts DMA Channel 1. -// -void StartDMACH1(void) -{ - EALLOW; - DmaRegs.CH1.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH2AddrConfig - DMA Channel 2 Address Configuration -// -void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer. - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2BurstConfig - DMA Channel 2 Burst size configuration -// -void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration -// -void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration -// -void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH2ModeConfig - DMA Channel 2 Mode configuration -// -void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; - DmaRegs.CH2.MODE.bit.PERINTSEL = 2; - DmaRegs.CH2.MODE.bit.PERINTE = perinte; - DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH2.MODE.bit.DATASIZE = datasize; - DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH2.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH2 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx2 = 1; - - EDIS; -} - -// -// StartDMACH2 - This function starts DMA Channel 2. -// -void StartDMACH2(void) -{ - EALLOW; - DmaRegs.CH2.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH3AddrConfig - DMA Channel 3 Address configuration -// -void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3BurstConfig - DMA Channel 3 burst size configuration -// -void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH3TransferConfig - DMA channel 3 transfer size configuration -// -void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH3WrapConfig - DMA Channel 3 wrap size configuration -// -void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH3ModeConfig - DMA Channel 3 mode configuration -// -void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; - DmaRegs.CH3.MODE.bit.PERINTSEL = 3; - DmaRegs.CH3.MODE.bit.PERINTE = perinte; - DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH3.MODE.bit.DATASIZE = datasize; - DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH3.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt flags and sync error flags - // - DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH3 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx3 = 1; - - EDIS; -} - -// -// StartDMACH3 - This function starts DMA Channel 3. -// -void StartDMACH3(void) -{ - EALLOW; - DmaRegs.CH3.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH4AddrConfig - DMA Channel 4 address configuration -// -void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4BurstConfig - DMA Channel 4 burst size configuration -// -void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH4TransferConfig - DMA channel 4 transfer size configuration -// -void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH4WrapConfig - DMA channel 4 wrap size configuration -// -void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH4ModeConfig - DMA Channel 4 mode configuration -// -void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; - DmaRegs.CH4.MODE.bit.PERINTSEL = 4; - DmaRegs.CH4.MODE.bit.PERINTE = perinte; - DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH4.MODE.bit.DATASIZE = datasize; - DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH4.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH4 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx4 = 1; - - EDIS; -} - -// -// StartDMACH4 - This function starts DMA Channel 4. -// -void StartDMACH4(void) -{ - EALLOW; - DmaRegs.CH4.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH5AddrConfig - DMA channel 5 address configuration -// -void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5BurstConfig - DMA Channel 5 burst size configuration -// -void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH5TransferConfig - DMA channel 5 transfer size configuration -// -void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH5WrapConfig - DMA Channel 5 wrap size configuration -// -void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH5ModeConfig - DMA Channel 5 mode configuration -// -void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; - DmaRegs.CH5.MODE.bit.PERINTSEL = 5; - DmaRegs.CH5.MODE.bit.PERINTE = perinte; - DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH5.MODE.bit.DATASIZE = datasize; - DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH5.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH5 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx5 = 1; - - EDIS; -} - -// -// StartDMACH5 - This function starts DMA Channel 5. -// -void StartDMACH5(void) -{ - EALLOW; - DmaRegs.CH5.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH6AddrConfig - DMA Channel 6 address configuration -// -void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6BurstConfig - DMA Channel 6 burst size configuration -// -void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH6TransferConfig - DMA channel 6 transfer size configuration -// -void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH6WrapConfig - DMA Channel 6 wrap size configuration -// -void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH6ModeConfig - DMA Channel 6 mode configuration -// -void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; - DmaRegs.CH6.MODE.bit.PERINTSEL = 6; - DmaRegs.CH6.MODE.bit.PERINTE = perinte; - DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH6.MODE.bit.DATASIZE = datasize; - DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH6.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH6 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx6 = 1; - - EDIS; -} - -// -// StartDMACH6 - This function starts DMA Channel 6. -// -void StartDMACH6(void) -{ - EALLOW; - DmaRegs.CH6.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit -// -void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit -// -void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit -// -void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit -// -void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; - // Point to beginning - // of destination - // buffer - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit -// -void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; - // Point to beginning - // of destination - // buffer - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit -// -void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c b/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c deleted file mode 100644 index 9f3573e..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c +++ /dev/null @@ -1,441 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio.c -// -// TITLE: f28004x GPIO module support functions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" -#include "f28004x_examples.h" - -// -// Low-level functions for GPIO configuration -// - -// -// InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups -// enabled.Also resets CPU control to CPU1 and disables open drain -// and polarity inversion and sets the qualification to synchronous. -// Also unlocks all GPIOs. Only one CPU should call this function. -// -void -InitGpio() -{ - volatile Uint32 *gpioBaseAddr; - Uint16 regOffset; - - // - // Disable pin locks - // - EALLOW; - GpioCtrlRegs.GPALOCK.all = 0x00000000; - GpioCtrlRegs.GPBLOCK.all = 0x00000000; - GpioCtrlRegs.GPHLOCK.all = 0x00000000; - - // - // Fill all registers with zeros. Writing to each register separately - // for three GPIO modules would make this function *very* long. - // Fortunately, we'd be writing them all with zeros anyway, - // so this saves a lot of space. - // - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; - for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) - { - // - // Must avoid enabling pull-ups on all pins. GPyPUD is offset - // 0x0C in each register group of 0x40 words. Since this is a - // 32-bit pointer, the addresses must be divided by 2. - // - // Also, to avoid changing pin muxing of the emulator pins to regular - // GPIOs, skip GPBMUX1 (0x46) and GPBGMUX1 (0x60). - // - if ((regOffset % (0x40/2) != (0x0C/2)) && (regOffset != (0x46/2)) && - (regOffset != (0x60/2))) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - } - - gpioBaseAddr = (Uint32 *)&GpioDataRegs; - for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - - EDIS; -} - -// -// GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. -// The appropriate parameters can be found in the pinout spreadsheet. -// -void -GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *mux, *gmux, *csel; - Uint16 pin32, pin16, pin8; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pin8 = gpioNumber % 8; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Sanity check for valid cpu and peripheral values - // - if (cpu > GPIO_MUX_CPU1CLA || muxPosition > 0xF) - { - return; - } - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyCSEL1-4. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - mux = gpioBaseAddr + GPYMUX + pin32/16; - gmux = gpioBaseAddr + GPYGMUX + pin32/16; - csel = gpioBaseAddr + GPYCSEL + pin32/8; - - // - // Now for the actual function - // - EALLOW; - - // - // To change the muxing, set the peripheral mux to 0/GPIO first to avoid - // glitches, then change the group mux, then set the peripheral mux to - // its target value. Finally, set the CPU select. This procedure is - // described in the TRM. Unfortunately, since we don't know the pin in - // advance we can't hardcode a bitfield reference, so there's some tricky - // bit twiddling here. - // - *mux &= ~(0x3UL << (2*pin16)); - *gmux &= ~(0x3UL << (2*pin16)); - *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); - *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); - - *csel &= ~(0x3L << (4*pin8)); - *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); - - // - // WARNING: This code does not touch the analog mode select registers. - // - - EDIS; -} - -// -// GPIO_SetupPinOptions - Setup up the GPIO input/output options for the -// specified pin. The flags are a 16-bit mask produced by ORing together -// options. For input pins, the valid flags are: -// GPIO_PULLUP Enable pull-up -// GPIO_INVERT Enable input polarity inversion -// GPIO_SYNC Synchronize the input latch to PLLSYSCLK -// (default -- you don't need to specify this) -// GPIO_QUAL3 Use 3-sample qualification -// GPIO_QUAL6 Use 6-sample qualification -// GPIO_ASYNC Do not use synchronization or qualification -// (Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) -// -// For output pins, the valid flags are: -// GPIO_OPENDRAIN Output in open drain mode -// GPIO_PULLUP If open drain enabled, also enable the pull-up -// and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. -// -// With no flags, the default input state is synchronous with no -// pull-up or polarity inversion. The default output state is -// the standard digital output. -// -void -GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *dir, *pud, *inv, *odr, *qsel; - Uint32 pin32, pin16, pinMask, qual; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyQSEL1-2. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - dir = gpioBaseAddr + GPYDIR; - pud = gpioBaseAddr + GPYPUD; - inv = gpioBaseAddr + GPYINV; - odr = gpioBaseAddr + GPYODR; - qsel = gpioBaseAddr + GPYQSEL + pin32/16; - - EALLOW; - - // - // Set the data direction - // - *dir &= ~pinMask; - if (output == 1) - { - // - // Output, with optional open drain mode and pull-up - // - *dir |= pinMask; - - // - // Enable open drain if necessary - // - if (flags & GPIO_OPENDRAIN) - { - *odr |= pinMask; - } - else - { - *odr &= ~pinMask; - } - - // - // Enable pull-up if necessary. Open drain mode must be active. - // - if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - } - - else - { - // - // Input, with optional pull-up, qualification, and polarity inversion - // - *dir &= ~pinMask; - - // - // Enable pull-up if necessary - // - if (flags & GPIO_PULLUP) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - - // - // Invert polarity if necessary - // - if (flags & GPIO_INVERT) - { - *inv |= pinMask; - } - else - { - *inv &= ~pinMask; - } - } - - // - // Extract the qualification parameter and load it into the register. - // This is also needed for open drain outputs, so we might as well do it - // all the time. - // - qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; - *qsel &= ~(0x3L << (2 * pin16)); - if (qual != 0x0) - { - *qsel |= qual << (2 * pin16); - } - - EDIS; -} - -// -// GPIO_SetupLock - Enable or disable the GPIO register bit lock for the -// specified pin. The valid flags are: -// GPIO_UNLOCK Unlock the pin setup register bits for the specified pin -// GPIO_LOCK Lock the pin setup register bits for the specified pin -// -void -GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *lock; - Uint32 pin32, pinMask; - - pin32 = gpioNumber % 32; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyQSEL1-2. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - lock = gpioBaseAddr + GPYLOCK; - - EALLOW; - - if(flags) - { - // - // Lock the pin - // - *lock |= pinMask; - } - - else - { - // - // Unlock the pin - // - *lock &= ~pinMask; - } - EDIS; -} - -// -// External interrupt setup -// -void -GPIO_SetupXINT1Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT4SELECT = gpioNumber; // Set XINT1 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT2Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT5SELECT = gpioNumber; // Set XINT2 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT3Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT6SELECT = gpioNumber; // Set XINT3 source to GPIO-pin - EDIS; -} -void -GPIO_SetupXINT4Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT13SELECT = gpioNumber; // Set XINT4 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT5Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT14SELECT = gpioNumber; // Set XINT5 source to GPIO-pin - EDIS; -} - -// -// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. -// Note that this returns the actual state of the pin, not the state of the -// output latch. -// -Uint16 -GPIO_ReadPin(Uint16 gpioNumber) -{ - volatile Uint32 *gpioDataReg; - Uint16 pinVal; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; - - return pinVal; -} - -// -// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. -// -void -GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) -{ - volatile Uint32 *gpioDataReg; - Uint32 pinMask; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinMask = 1UL << (gpioNumber % 32); - - if (outVal == 0) - { - gpioDataReg[GPYCLEAR] = pinMask; - } - - else - { - gpioDataReg[GPYSET] = pinMask; - } -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c b/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c deleted file mode 100644 index 624955d..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c +++ /dev/null @@ -1,124 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_piectrl.c -// -// TITLE: f28004x Device PIE Control Register Initialization Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // f28004x Headerfile Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -// -// InitPieCtrl - This function initializes the PIE control registers -// to a known state. -// -void -InitPieCtrl(void) -{ - // - // Disable Interrupts at the CPU level: - // - DINT; - - // - // Disable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 0; - - // - // Clear all PIEIER registers: - // - PieCtrlRegs.PIEIER1.all = 0; - PieCtrlRegs.PIEIER2.all = 0; - PieCtrlRegs.PIEIER3.all = 0; - PieCtrlRegs.PIEIER4.all = 0; - PieCtrlRegs.PIEIER5.all = 0; - PieCtrlRegs.PIEIER6.all = 0; - PieCtrlRegs.PIEIER7.all = 0; - PieCtrlRegs.PIEIER8.all = 0; - PieCtrlRegs.PIEIER9.all = 0; - PieCtrlRegs.PIEIER10.all = 0; - PieCtrlRegs.PIEIER11.all = 0; - PieCtrlRegs.PIEIER12.all = 0; - - // - // Clear all PIEIFR registers: - // - PieCtrlRegs.PIEIFR1.all = 0; - PieCtrlRegs.PIEIFR2.all = 0; - PieCtrlRegs.PIEIFR3.all = 0; - PieCtrlRegs.PIEIFR4.all = 0; - PieCtrlRegs.PIEIFR5.all = 0; - PieCtrlRegs.PIEIFR6.all = 0; - PieCtrlRegs.PIEIFR7.all = 0; - PieCtrlRegs.PIEIFR8.all = 0; - PieCtrlRegs.PIEIFR9.all = 0; - PieCtrlRegs.PIEIFR10.all = 0; - PieCtrlRegs.PIEIFR11.all = 0; - PieCtrlRegs.PIEIFR12.all = 0; -} - -// -// EnableInterrupts - This function enables the PIE module and CPU __interrupts -// -void -EnableInterrupts() -{ - // - // Enable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; - - // - // Enables PIE to drive a pulse into the CPU - // - PieCtrlRegs.PIEACK.all = 0xFFFF; - - // - // Enable Interrupts at the CPU level - // - EINT; -} - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c b/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c deleted file mode 100644 index 467f60f..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c +++ /dev/null @@ -1,315 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pievect.c -// -// TITLE: f28004x Device PIE Vector Initialization Functions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // f28004x Header File Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -// -// Define PIE Vector Table: -// -const struct PIE_VECT_TABLE PieVectTableInit = { - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - TIMER1_ISR, // CPU Timer 1 Interrupt - TIMER2_ISR, // CPU Timer 2 Interrupt - DATALOG_ISR, // Datalogging Interrupt - RTOS_ISR, // RTOS Interrupt - EMU_ISR, // Emulation Interrupt - NMI_ISR, // Non-Maskable Interrupt - ILLEGAL_ISR, // Illegal Operation Trap - USER1_ISR, // User Defined Trap 1 - USER2_ISR, // User Defined Trap 2 - USER3_ISR, // User Defined Trap 3 - USER4_ISR, // User Defined Trap 4 - USER5_ISR, // User Defined Trap 5 - USER6_ISR, // User Defined Trap 6 - USER7_ISR, // User Defined Trap 7 - USER8_ISR, // User Defined Trap 8 - USER9_ISR, // User Defined Trap 9 - USER10_ISR, // User Defined Trap 10 - USER11_ISR, // User Defined Trap 11 - USER12_ISR, // User Defined Trap 12 - ADCA1_ISR, // 1.1 - ADCA Interrupt 1 - ADCB1_ISR, // 1.2 - ADCB Interrupt 1 - ADCC1_ISR, // 1.3 - ADCC Interrupt 1 - XINT1_ISR, // 1.4 - XINT1 Interrupt - XINT2_ISR, // 1.5 - XINT2 Interrupt - PIE_RESERVED_ISR, // 1.6 - Reserved - TIMER0_ISR, // 1.7 - Timer 0 Interrupt - WAKE_ISR, // 1.8 - Halt Wakeup Interrupt - EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt - EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt - EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt - EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt - EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt - EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt - EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt - EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt - EPWM1_ISR, // 3.1 - ePWM1 Interrupt - EPWM2_ISR, // 3.2 - ePWM2 Interrupt - EPWM3_ISR, // 3.3 - ePWM3 Interrupt - EPWM4_ISR, // 3.4 - ePWM4 Interrupt - EPWM5_ISR, // 3.5 - ePWM5 Interrupt - EPWM6_ISR, // 3.6 - ePWM6 Interrupt - EPWM7_ISR, // 3.7 - ePWM7 Interrupt - EPWM8_ISR, // 3.8 - ePWM8 Interrupt - ECAP1_ISR, // 4.1 - eCAP1 Interrupt - ECAP2_ISR, // 4.2 - eCAP2 Interrupt - ECAP3_ISR, // 4.3 - eCAP3 Interrupt - ECAP4_ISR, // 4.4 - eCAP4 Interrupt - ECAP5_ISR, // 4.5 - eCAP5 Interrupt - ECAP6_ISR, // 4.6 - eCAP6 Interrupt - ECAP7_ISR, // 4.7 - eCAP7 Interrupt - PIE_RESERVED_ISR, // 4.8 - Reserved - EQEP1_ISR, // 5.1 - eQEP1 Interrupt - EQEP2_ISR, // 5.2 - eQEP2 Interrupt - PIE_RESERVED_ISR, // 5.3 - Reserved - PIE_RESERVED_ISR, // 5.4 - Reserved - PIE_RESERVED_ISR, // 5.5 - Reserved - PIE_RESERVED_ISR, // 5.6 - Reserved - PIE_RESERVED_ISR, // 5.7 - Reserved - PIE_RESERVED_ISR, // 5.8 - Reserved - SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt - SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt - SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt - SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt - PIE_RESERVED_ISR, // 6.5 - Reserved - PIE_RESERVED_ISR, // 6.6 - Reserved - PIE_RESERVED_ISR, // 6.7 - Reserved - PIE_RESERVED_ISR, // 6.8 - Reserved - DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt - DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt - DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt - DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt - DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt - DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt - PIE_RESERVED_ISR, // 7.7 - Reserved - PIE_RESERVED_ISR, // 7.8 - Reserved - I2CA_ISR, // 8.1 - I2CA Interrupt 1 - I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 - PIE_RESERVED_ISR, // 8.3 - Reserved - PIE_RESERVED_ISR, // 8.4 - Reserved - PIE_RESERVED_ISR, // 8.5 - Reserved - PIE_RESERVED_ISR, // 8.6 - Reserved - PIE_RESERVED_ISR, // 8.7 - Reserved - PIE_RESERVED_ISR, // 8.8 - Reserved - SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt - SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt - SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt - SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt - CANA0_ISR, // 9.5 - CANA Interrupt 0 - CANA1_ISR, // 9.6 - CANA Interrupt 1 - CANB0_ISR, // 9.7 - CANB Interrupt 0 - CANB1_ISR, // 9.8 - CANB Interrupt 1 - ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt - ADCA2_ISR, // 10.2 - ADCA Interrupt 2 - ADCA3_ISR, // 10.3 - ADCA Interrupt 3 - ADCA4_ISR, // 10.4 - ADCA Interrupt 4 - ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt - ADCB2_ISR, // 10.6 - ADCB Interrupt 2 - ADCB3_ISR, // 10.7 - ADCB Interrupt 3 - ADCB4_ISR, // 10.8 - ADCB Interrupt 4 - CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 - CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 - CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 - CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 - CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 - CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 - CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 - CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 - XINT3_ISR, // 12.1 - XINT3 Interrupt - XINT4_ISR, // 12.2 - XINT4 Interrupt - XINT5_ISR, // 12.3 - XINT5 Interrupt - PIE_RESERVED_ISR, // 12.4 - Reserved - PIE_RESERVED_ISR, // 12.5 - Reserved - PIE_RESERVED_ISR, // 12.6 - Reserved - FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt - FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt - PIE_RESERVED_ISR, // 1.9 - Reserved - PIE_RESERVED_ISR, // 1.10 - Reserved - PIE_RESERVED_ISR, // 1.11 - Reserved - PIE_RESERVED_ISR, // 1.12 - Reserved - PIE_RESERVED_ISR, // 1.13 - Reserved - PIE_RESERVED_ISR, // 1.14 - Reserved - PIE_RESERVED_ISR, // 1.15 - Reserved - PIE_RESERVED_ISR, // 1.16 - Reserved - PIE_RESERVED_ISR, // 2.9 - Reserved - PIE_RESERVED_ISR, // 2.10 - Reserved - PIE_RESERVED_ISR, // 2.11 - Reserved - PIE_RESERVED_ISR, // 2.12 - Reserved - PIE_RESERVED_ISR, // 2.13 - Reserved - PIE_RESERVED_ISR, // 2.14 - Reserved - PIE_RESERVED_ISR, // 2.15 - Reserved - PIE_RESERVED_ISR, // 2.16 - Reserved - PIE_RESERVED_ISR, // 3.9 - Reserved - PIE_RESERVED_ISR, // 3.10 - Reserved - PIE_RESERVED_ISR, // 3.11 - Reserved - PIE_RESERVED_ISR, // 3.12 - Reserved - PIE_RESERVED_ISR, // 3.13 - Reserved - PIE_RESERVED_ISR, // 3.14 - Reserved - PIE_RESERVED_ISR, // 3.15 - Reserved - PIE_RESERVED_ISR, // 3.16 - Reserved - PIE_RESERVED_ISR, // 4.9 - Reserved - PIE_RESERVED_ISR, // 4.10 - Reserved - PIE_RESERVED_ISR, // 4.11 - Reserved - PIE_RESERVED_ISR, // 4.12 - Reserved - PIE_RESERVED_ISR, // 4.13 - Reserved - ECAP6_2_ISR, // 4.14 - eCAP6_2 Interrupt - ECAP7_2_ISR, // 4.15 - eCAP7_2 Interrupt - PIE_RESERVED_ISR, // 4.16 - Reserved - SD1_ISR, // 5.9 - SD1 Interrupt - PIE_RESERVED_ISR, // 5.10 - Reserved - PIE_RESERVED_ISR, // 5.11 - Reserved - PIE_RESERVED_ISR, // 5.12 - Reserved - SD1DR1_ISR, // 5.13 - SD1DR1 Interrupt - SD1DR2_ISR, // 5.14 - SD1DR2 Interrupt - SD1DR3_ISR, // 5.15 - SD1DR3 Interrupt - SD1DR4_ISR, // 5.16 - SD1DR4 Interrupt - PIE_RESERVED_ISR, // 6.9 - Reserved - PIE_RESERVED_ISR, // 6.10 - Reserved - PIE_RESERVED_ISR, // 6.11 - Reserved - PIE_RESERVED_ISR, // 6.12 - Reserved - PIE_RESERVED_ISR, // 6.13 - Reserved - PIE_RESERVED_ISR, // 6.14 - Reserved - PIE_RESERVED_ISR, // 6.15 - Reserved - PIE_RESERVED_ISR, // 6.16 - Reserved - PIE_RESERVED_ISR, // 7.9 - Reserved - PIE_RESERVED_ISR, // 7.10 - Reserved - FSITXA1_ISR, // 7.11 - FSITXA1 Interrupt - FSITXA2_ISR, // 7.12 - FSITXA2 Interrupt - FSIRXA1_ISR, // 7.13 - FSIRXA1 Interrupt - FSIRXA2_ISR, // 7.14 - FSIRXA2 Interrupt - CLA1PROMCRC_ISR, // 7.15 - CLA1PROMCRC Interrupt - PIE_RESERVED_ISR, // 7.16 - Reserved - LINA_0_ISR, // 8.9 - LINA Interrupt0 - LINA_1_ISR, // 8.10 - LINA Interrupt1 - PIE_RESERVED_ISR, // 8.11 - Reserved - PIE_RESERVED_ISR, // 8.12 - Reserved - PMBUSA_ISR, // 8.13 - PMBUSA Interrupt - PIE_RESERVED_ISR, // 8.14 - Reserved - PIE_RESERVED_ISR, // 8.15 - Reserved - PIE_RESERVED_ISR, // 8.16 - Reserved - PIE_RESERVED_ISR, // 9.9 - Reserved - PIE_RESERVED_ISR, // 9.10 - Reserved - PIE_RESERVED_ISR, // 9.11 - Reserved - PIE_RESERVED_ISR, // 9.12 - Reserved - PIE_RESERVED_ISR, // 9.13 - Reserved - PIE_RESERVED_ISR, // 9.14 - Reserved - PIE_RESERVED_ISR, // 9.15 - Reserved - PIE_RESERVED_ISR, // 9.16 - Reserved - ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt - ADCC2_ISR, // 10.10 - ADCC Interrupt 2 - ADCC3_ISR, // 10.11 - ADCC Interrupt 3 - ADCC4_ISR, // 10.12 - ADCC Interrupt 4 - PIE_RESERVED_ISR, // 10.13 - Reserved - PIE_RESERVED_ISR, // 10.14 - Reserved - PIE_RESERVED_ISR, // 10.15 - Reserved - PIE_RESERVED_ISR, // 10.16 - Reserved - PIE_RESERVED_ISR, // 11.9 - Reserved - PIE_RESERVED_ISR, // 11.10 - Reserved - PIE_RESERVED_ISR, // 11.11 - Reserved - PIE_RESERVED_ISR, // 11.12 - Reserved - PIE_RESERVED_ISR, // 11.13 - Reserved - PIE_RESERVED_ISR, // 11.14 - Reserved - PIE_RESERVED_ISR, // 11.15 - Reserved - PIE_RESERVED_ISR, // 11.16 - Reserved - PIE_RESERVED_ISR, // 12.9 - Reserved - RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt - FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt - RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt - SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt - PIE_RESERVED_ISR, // 12.14 - Reserved - CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt - CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt -}; - -// -// InitPieVectTable - This function initializes the PIE vector table to a known -// state. This function must be executed after boot time. -// -void -InitPieVectTable(void) -{ - Uint16 i; - Uint32 *Source = (void *) &PieVectTableInit; - Uint32 *Dest = (void *) &PieVectTable; - - // - // Do not write over first 3 32-bit locations (these locations are - // initialized by Boot ROM with boot variables) - // - Source = Source + 3; - Dest = Dest + 3; - - EALLOW; - - for(i = 0; i < 221; i++) - { - *Dest++ = *Source++; - } - - EDIS; - - // - // Enable the PIE Vector Table - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c b/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c deleted file mode 100644 index 75b951c..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c +++ /dev/null @@ -1,177 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_Spi.c -// -// TITLE: f28004x SPI Initialization & Support Functions. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File - -// -// Calculate BRR: 7-bit baud rate register value -// SPI CLK freq = 500 kHz -// LSPCLK freq = CPU freq / 4 (by default) -// BRR = (LSPCLK freq / SPI CLK freq) - 1 -// -#if CPU_FRQ_100MHZ -#define SPI_BRR ((100E6 / 4) / 500E3) - 1 -#endif - -// -// InitSPI - This function initializes the SPI to a known state -// -void InitSpi(void) -{ - // - // Initialize SPI-A - // - // Set reset low before configuration changes - // Clock polarity (0 == rising, 1 == falling) - // 16-bit character - // Enable loop-back - // - SpiaRegs.SPICCR.bit.SPISWRESET = 0; - SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; - SpiaRegs.SPICCR.bit.SPICHAR = (16-1); - SpiaRegs.SPICCR.bit.SPILBK = 1; - - // - // Enable master (0 == slave, 1 == master) - // Enable transmission (Talk) - // Clock phase (0 == normal, 1 == delayed) - // SPI interrupts are disabled - // - SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; - SpiaRegs.SPICTL.bit.TALK = 1; - SpiaRegs.SPICTL.bit.CLK_PHASE = 0; - SpiaRegs.SPICTL.bit.SPIINTENA = 0; - - // - // Set the baud rate - // - SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; - - // - // Set FREE bit - // Halting on a breakpoint will not halt the SPI - // - SpiaRegs.SPIPRI.bit.FREE = 1; - - // - // Release the SPI from reset - // - SpiaRegs.SPICCR.bit.SPISWRESET = 1; -} - -// -// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. -// Each GPIO pin can be configured as a GPIO pin or up to 3 -// different peripheral functional pins. By default all pins come -// up as GPIO inputs after reset. -// -// Caution: -// For each SPI peripheral -// Only one GPIO pin should be enabled for SPISOMO operation. -// Only one GPIO pin should be enabled for SPISOMI operation. -// Only one GPIO pin should be enabled for SPICLK operation. -// Only one GPIO pin should be enabled for SPISTE operation. -// Comment out other unwanted lines. -// -void InitSpiGpio() -{ - InitSpiaGpio(); -} - -// -// InitSpiaGpio - Initialize SPIA GPIOs -// -void InitSpiaGpio() -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) - // GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) - // GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) - GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) - // GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) - // GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) - - // - //Configure SPI-A pins using GPIO regs - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA - // GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA - GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA - // GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA - GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA - GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA - - EDIS; -} - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c b/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c deleted file mode 100644 index 542c0cd..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c +++ /dev/null @@ -1,876 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl.c -// -// TITLE: f28004x Device System Control Initialization & Support Functions. -// -// DESCRIPTION: Example initialization of system resources. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File -#ifdef __cplusplus -using std::memcpy; -#endif - -// -// Functions that will be run from RAM need to be assigned to -// a different section. This section will then be mapped to a load and -// run address using the linker cmd file. -// -// *IMPORTANT* -// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM FLASH -// TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM THROWING -// AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. -// -#ifndef __cplusplus -#pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); -#pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); -#endif - -// -// The following values are used to validate PLL Frequency using DCC -// -#define PLL_RETRIES 100 -#define PLL_LOCK_TIMEOUT 2000 -#define DCC_COUNTER0_WINDOW 100 - -// -// InitSysCtrl - -// -void -InitSysCtrl(void) -{ - // - // Disable the watchdog - // - DisableDog(); - -#ifdef _FLASH - // - // Copy time critical code and Flash setup code to RAM - // This includes the following functions: InitFlash(); - // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart - // symbols are created by the linker. Refer to the device .cmd file. - // - memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); -#endif - - // - // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) - // - InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2); - - // - // Call Flash Initialization to setup flash waitstates - // This function must reside in RAM - // - InitFlash(); - - // - // Turn on all peripherals - // - InitPeripheralClocks(); -} - -// -// InitPeripheralClocks - This function initializes the clocks for the -// peripherals. Note: In order to reduce power consumption, turn off the -// clocks to any peripheral that is not specified for your part-number or is -// not used in the application -// -void -InitPeripheralClocks() -{ - EALLOW; - - CpuSysRegs.PCLKCR0.bit.CLA1 = 1; - CpuSysRegs.PCLKCR0.bit.DMA = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; - CpuSysRegs.PCLKCR0.bit.HRPWM = 1; - CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; - - CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; - - CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP7 = 1; - - CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; - CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; - - CpuSysRegs.PCLKCR6.bit.SD1 = 1; - - CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - CpuSysRegs.PCLKCR7.bit.SCI_B = 1; - - CpuSysRegs.PCLKCR8.bit.SPI_A = 1; - CpuSysRegs.PCLKCR8.bit.SPI_B = 1; - - CpuSysRegs.PCLKCR9.bit.I2C_A = 1; - - CpuSysRegs.PCLKCR10.bit.CAN_A = 1; - CpuSysRegs.PCLKCR10.bit.CAN_B = 1; - - CpuSysRegs.PCLKCR13.bit.ADC_A = 1; - CpuSysRegs.PCLKCR13.bit.ADC_B = 1; - CpuSysRegs.PCLKCR13.bit.ADC_C = 1; - - CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; - - CpuSysRegs.PCLKCR15.bit.PGA1 = 1; - CpuSysRegs.PCLKCR15.bit.PGA2 = 1; - CpuSysRegs.PCLKCR15.bit.PGA3 = 1; - CpuSysRegs.PCLKCR15.bit.PGA4 = 1; - CpuSysRegs.PCLKCR15.bit.PGA5 = 1; - CpuSysRegs.PCLKCR15.bit.PGA6 = 1; - CpuSysRegs.PCLKCR15.bit.PGA7 = 1; - - CpuSysRegs.PCLKCR16.bit.DAC_A = 1; - CpuSysRegs.PCLKCR16.bit.DAC_B = 1; - - CpuSysRegs.PCLKCR19.bit.LIN_A = 1; - - CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1; - - CpuSysRegs.PCLKCR21.bit.DCC_0 = 1; - - EDIS; -} - -// -// DisablePeripheralClocks - -// -void -DisablePeripheralClocks() -{ - EALLOW; - - CpuSysRegs.PCLKCR0.all = 0; - CpuSysRegs.PCLKCR2.all = 0; - CpuSysRegs.PCLKCR3.all = 0; - CpuSysRegs.PCLKCR4.all = 0; - CpuSysRegs.PCLKCR6.all = 0; - CpuSysRegs.PCLKCR7.all = 0; - CpuSysRegs.PCLKCR8.all = 0; - CpuSysRegs.PCLKCR9.all = 0; - CpuSysRegs.PCLKCR10.all = 0; - CpuSysRegs.PCLKCR13.all = 0; - CpuSysRegs.PCLKCR14.all = 0; - CpuSysRegs.PCLKCR15.all = 0; - CpuSysRegs.PCLKCR16.all = 0; - CpuSysRegs.PCLKCR19.all = 0; - CpuSysRegs.PCLKCR20.all = 0; - CpuSysRegs.PCLKCR21.all = 0; - - EDIS; -} - -// -// InitFlash - This function initializes the Flash Control registers -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -#ifdef __cplusplus -#pragma CODE_SECTION(".TI.ramfunc"); -#endif -void -InitFlash(void) -{ - EALLOW; - - // - // At reset bank and pump are in sleep - // A Flash access will power up the bank and pump automatically - // After a Flash access, bank and pump go to low power mode (configurable - // in FBFALLBACK/FPAC1 registers)- if there is no further access to flash - // Power up Flash bank and pump and this also sets the fall back mode of - // flash and pump as active - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0x3; - - // - // Disable Cache and prefetch mechanism before changing wait states - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; - - // - // Set waitstates according to frequency - // CAUTION - // Minimum waitstates required for the flash operating - // at a given CPU rate must be characterized by TI. - // Refer to the datasheet for the latest information. - // -#if CPU_FRQ_100MHZ - if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x0) || - (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x2) || - (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x3)) - { - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x5; - } - else - { - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x4; - } -#endif - - // - // Enable Cache and prefetch mechanism to improve performance - // of code executed from Flash. - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; - - // - // At reset, ECC is enabled. If it is disabled by application software - // and if application again wants to enable ECC - // - Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; - - EDIS; - - // - // Force a pipeline flush to ensure that the write to - // the last register configured occurs before returning. - // - __asm(" RPT #7 || NOP"); -} - -// -// FlashOff - This function powers down the flash -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results. -// Note: a flash access after the flash pump and banks are powered down will -// wake the pump and bank -// -#ifdef __cplusplus -#pragma CODE_SECTION(".TI.ramfunc"); -#endif -void -FlashOff(void) -{ - EALLOW; - - // - // Configure the fallback power mode as sleep - // - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0; - - // - // Configure the fallback power mode as sleep - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; - - EDIS; -} - -// -// ServiceDog - This function resets the watchdog timer. -// Enable this function for using ServiceDog in the application -// -void -ServiceDog(void) -{ - EALLOW; - WdRegs.WDKEY.bit.WDKEY = 0x0055; - WdRegs.WDKEY.bit.WDKEY = 0x00AA; - EDIS; -} - -// -// DisableDog - This function disables the watchdog timer. -// -void -DisableDog(void) -{ - volatile Uint16 temp; - EALLOW; - - // - // Grab the clock config so we don't clobber it - // - temp = WdRegs.WDCR.all & 0x0007; - WdRegs.WDCR.all = 0x0068 | temp; - EDIS; -} - -// -// InitPll - This function initializes the PLL registers. -// -// Note: This function uses the DCC to check that the PLLRAWCLK is running at -// the expected rate. If you are using the DCC, you must back up its -// configuration before calling this function and restore it afterward. -// -void -InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) -{ - Uint32 timeout, retries, temp_syspllmult, pllLockStatus; - bool status; - - if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && - (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && - (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && - (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && - (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) - { - // - // Everything is set as required, so just return - // - return; - } - - if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) || - (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE)) - { - switch (clock_source) - { - case INT_OSC1: - SysIntOsc1Sel(); - break; - - case INT_OSC2: - SysIntOsc2Sel(); - break; - - case XTAL_OSC: - SysXtalOscSel(); - break; - - case XTAL_OSC_SE: - SysXtalOscSESel(); - break; - } - } - - EALLOW; - - // - // First modify the PLL multipliers - // - if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || - fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) - { - // - // Bypass PLL and set dividers to /1 - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; - - // - // Evaluate PLL multipliers - // - temp_syspllmult = ((fmult << 8U) | imult); - - // - // Loop to retry locking the PLL should the DCC module indicate - // that it was not successful. - // - for(retries = 0; (retries < PLL_RETRIES); retries++) - { - // - // Bypass PLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - - // - // Program PLL multipliers - // - ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult; - - // - // Enable SYSPLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; - - timeout = PLL_LOCK_TIMEOUT; - pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; - - // - // Wait for the SYSPLL lock - // - while((pllLockStatus != 1) && (timeout != 0U)) - { - pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; - timeout--; - } - - EDIS; - - status = IsPLLValid(clock_source, imult, fmult); - - // - // Check DCC Status, if no error break the loop - // - if(status) - { - break; - } - } - } - else - { - status = true; - } - - if(status) - { - EALLOW; - // - // Set divider to produce slower output frequency to limit current increase - // - if(divsel != PLLCLK_BY_126) - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; - } - else - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - } - - // - // Enable PLLSYSCLK is fed from system PLL clock - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; - - // - // Small 100 cycle delay - // - asm(" RPT #100 || NOP"); - - // - // Set the divider to user value - // - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - EDIS; - } -} - -// -// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with -// current password for the DSP. -// -Uint16 -CsmUnlock() -{ - // - // Write to the key registers to unlock the device. The 0x0FFFFFFFF's - // are dummmy passwords. User should replace them with the correct password - // for the DSP. - // Note: F28004x has default password keys which are not all 0xFFFFFFFF. - // See DCSM chapter of Technical Reference Manual for default passwords. - EALLOW; - - DcsmBank0Z1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; - - DcsmBank0Z2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; - EDIS; - - return 0; -} - -// -// SysIntOsc1Sel - This function switches to Internal Oscillator 1 and turns -// off all other clock sources to minimize power consumption -// -void -SysIntOsc1Sel (void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 - ClkCfgRegs.XTALCR.bit.OSCOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// SysIntOsc2Sel - This function switches to Internal oscillator 2 from -// External Oscillator and turns off all other clock sources to minimize -// power consumption -// NOTE: If there is no external clock connection, when switching from -// INTOSC1 to INTOSC2, EXTOSC and XLCKIN must be turned OFF prior -// to switching to internal oscillator 1 -// -void -SysIntOsc2Sel (void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 - ClkCfgRegs.XTALCR.bit.OSCOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate -// four times. -// -static void -PollX1Counter(void) -{ - Uint16 loopCount = 0; - - // - // Delay for 1 ms while the XTAL powers up - // - // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles - // - F28x_usDelay(2000); - - // - // Clear and saturate X1CNT 4 times to guarantee operation - // - do - { - // - // Keep clearing the counter until it is no longer saturated - // - while(ClkCfgRegs.X1CNT.all > 0x1FF) - { - ClkCfgRegs.X1CNT.bit.CLR = 1; - } - - // - // Wait for the X1 clock to saturate - // - while(ClkCfgRegs.X1CNT.all != 0x3FFU) - { - ; - } - - // - // Increment the counter - // - loopCount++; - }while(loopCount < 4); -} - -// -// SysXtalOscSel - This function switches to External CRYSTAL oscillator and -// turns off all other clock sources to minimize power consumption. This option -// may not be available on all device packages -// -void -SysXtalOscSel (void) -{ - EALLOW; - ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC - ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTAL as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - - // - // If a missing clock failure was detected, try waiting for the X1 counter - // to saturate again. Consider modifying this code to add a 10ms timeout. - // - while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) - { - EALLOW; - ClkCfgRegs.MCDCR.bit.MCLKCLR = 1; - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTAL as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - } -} - -// -// SysXtalOscSESel - This function switches to external oscillator in -// single-ended mode and turns off all other clock sources to minimize power -// consumption. This option may not be available on all device packages -// -void -SysXtalOscSESel (void) -{ - EALLOW; - ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC - ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTALOSC as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - - // - // If missing clock detected, there is something wrong with the oscillator - // module. - // - if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) - { - ESTOP0; - } -} - -// -// IDLE - Enter IDLE mode -// -void -IDLE() -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; - EDIS; - asm(" IDLE"); -} - -// -// HALT - Enter HALT mode -// -void -HALT() -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - EDIS; - asm(" IDLE"); -} - -//***************************************************************************** -// -// SysCtl_isPLLValid() -// -//***************************************************************************** -bool -IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult) -{ - Uint32 dccCounterSeed0, dccCounterSeed1, dccValidSeed0; - - // - // Setting Counter0 & Valid Seed Value with +/-2% tolerance - // - dccCounterSeed0 = DCC_COUNTER0_WINDOW - 2U; - dccValidSeed0 = 4U; - - // - // Multiplying Counter-0 window with PLL Integer Multiplier - // - dccCounterSeed1 = DCC_COUNTER0_WINDOW * imult; - - // - // Multiplying Counter-0 window with PLL Fractional Multiplier - // - switch(fmult) - { - case FMULT_0pt25: - // - // FMULT * CNTR0 Window = 0.25 * 100 = 25, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 25U; - break; - case FMULT_0pt5: - // - // FMULT * CNTR0 Window = 0.5 * 100 = 50, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 50U; - break; - case FMULT_0pt75: - // - // FMULT * CNTR0 Window = 0.75 * 100 = 75, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 75U; - break; - default: - // - // No fractional multiplier - // - dccCounterSeed1 = dccCounterSeed1; - break; - } - - // - // Enable Peripheral Clock Domain PCLKCR21 for DCC - // - EALLOW; - CpuSysRegs.PCLKCR21.bit.DCC_0 = 1; - - // - // Clear Error & Done Flag - // - Dcc0Regs.DCCSTATUS.bit.ERR = 1; - Dcc0Regs.DCCSTATUS.bit.DONE = 1; - - // - // Disable DCC - // - Dcc0Regs.DCCGCTRL.bit.DCCENA = 0x5; - - // - // Disable Error Signal - // - Dcc0Regs.DCCGCTRL.bit.ERRENA = 0x5; - - // - // Disable Done Signal - // - Dcc0Regs.DCCGCTRL.bit.DONEENA = 0x5; - - // - // Configure Clock Source0 to whatever is set as a clock source for PLL - // - switch(oscSource) - { - case INT_OSC1: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 1; // Clk Src0 = INTOSC1 - break; - - case INT_OSC2: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 2; // Clk Src0 = INTOSC2 - break; - - case XTAL_OSC: - case XTAL_OSC_SE: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 0; // Clk Src0 = XTAL - break; - } - - // - // Configure Clock Source1 to PLL - // - Dcc0Regs.DCCCLKSRC1.bit.KEY = 0xA; // Clk Src1 Key to enable clock source selection for count1 - Dcc0Regs.DCCCLKSRC1.bit.CLKSRC1 = 0; // Clk Src1 = PLL - - // - // Configure COUNTER-0, COUNTER-1 & Valid Window - // - Dcc0Regs.DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value - Dcc0Regs.DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0; // Loaded Valid Value - Dcc0Regs.DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value - - // - // Enable Single Shot Mode - // - Dcc0Regs.DCCGCTRL.bit.SINGLESHOT = 0xA; - - // - // Enable Error Signal - // - Dcc0Regs.DCCGCTRL.bit.ERRENA = 0xA; - - // - // Enable Done Signal - // - Dcc0Regs.DCCGCTRL.bit.DONEENA = 0xA; - - // - // Enable DCC to start counting - // - Dcc0Regs.DCCGCTRL.bit.DCCENA = 0xA; - EDIS; - - // - // Wait until Error or Done Flag is generated - // - while((Dcc0Regs.DCCSTATUS.all & 3) == 0) - { - } - - // - // Returns true if DCC completes without error - // - return((Dcc0Regs.DCCSTATUS.all & 3) == 2); - -} -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm deleted file mode 100644 index b46339d..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm +++ /dev/null @@ -1,92 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_usdelay.asm -;; -;; TITLE: Simple Delay Function -;; -;; DESCRIPTION: -;; -;; This is a simple delay function that can be used to insert a specified -;; delay into code. -;; This function is only accurate if executed from internal zero-waitstate -;; SARAM. If it is executed from waitstate memory then the delay will be -;; longer then specified. -;; To use this function: -;; 1 - update the CPU clock speed in the f28004x_examples.h -;; file. -;; 2 - Call this function by using the DELAY_US(A) macro -;; that is defined in the f28004x_device.h file. This macro -;; will convert the number of microseconds specified -;; into a loop count for use with this function. -;; This count will be based on the CPU frequency you specify. -;; 3 - For the most accurate delay -;; - Execute this function in 0 waitstate RAM. -;; - Disable interrupts before calling the function -;; If you do not disable interrupts, then think of -;; this as an "at least" delay function as the actual -;; delay may be longer. -;; The C assembly call from the DELAY_US(time) macro will -;; look as follows: -;; extern void Delay(long LoopCount); -;; MOV AL,#LowLoopCount -;; MOV AH,#HighLoopCount -;; LCR _Delay -;; Or as follows (if count is less then 16-bits): -;; MOV ACC,#LoopCount -;; LCR _Delay -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .def _F28x_usDelay - .sect ".TI.ramfunc" - - .global __F28x_usDelay -_F28x_usDelay: - SUB ACC,#1 - BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 - LRETR - -;There is a 9/10 cycle overhead and each loop -;takes five cycles. The LoopCount is given by -;the following formula: -; DELAY_CPU_CYCLES = 9 + 5*LoopCount -; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 -; The macro DELAY_US(A) performs this calculation for you - -;;############################################################################# -;; End of file -;;############################################################################# - diff --git a/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd b/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd deleted file mode 100644 index 31cd63d..0000000 --- a/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd +++ /dev/null @@ -1,303 +0,0 @@ -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - - ANALOG_SUBSYS : origin = 0x05D700, length = 0x000100 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000080 /* CLA registers */ - - CLAPROMCRC : origin = 0x0061C0, length = 0x000020 - - CLB_XBAR : origin = 0x007A40, length = 0x000040 - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - - DCC0 : origin = 0x05E700, length = 0x000040 - - DCSM_BANK0_Z1 : origin = 0x05F000, length = 0x000030 - DCSM_BANK0_Z2 : origin = 0x05F040, length = 0x000030 - DCSM_BANK1_Z1 : origin = 0x05F100, length = 0x000030 - DCSM_BANK1_Z2 : origin = 0x05F140, length = 0x000030 - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - - DMA : origin = 0x001000, length = 0x000200 - - ECAP1 : origin = 0x005200, length = 0x000040 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005240, length = 0x000040 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005280, length = 0x000040 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x0052C0, length = 0x000040 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005300, length = 0x000040 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x005340, length = 0x000040 /* Enhanced Capture 6 registers */ - ECAP7 : origin = 0x005380, length = 0x000040 /* Enhanced Capture 7 registers */ - - PGA1 : origin = 0x005B00, length = 0x000010 - PGA2 : origin = 0x005B10, length = 0x000010 - PGA3 : origin = 0x005B20, length = 0x000010 - PGA4 : origin = 0x005B30, length = 0x000010 - PGA5 : origin = 0x005B40, length = 0x000010 - PGA6 : origin = 0x005B50, length = 0x000010 - PGA7 : origin = 0x005B60, length = 0x000010 - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - - EPWM_XBAR : origin = 0x007A00, length = 0x000040 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - FSITXA : origin = 0x006600, length = 0x000080 - FSIRXA : origin = 0x006680, length = 0x000080 - - GPIOCTRL : origin = 0x007C00, length = 0x000200 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000040 /* GPIO data registers */ - - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - - INPUT_XBAR : origin = 0x007900, length = 0x000020 - - LINA : origin = 0x006A00, length = 0x000100 - LINB : origin = 0x006B00, length = 0x000100 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - - PMBUSA : origin = 0x006400, length = 0x000020 - - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - - WD : origin = 0x007000, length = 0x000040 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - DEV_CFG : origin = 0x05D000, length = 0x000180 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - PERIPH_AC : origin = 0x05D500, length = 0x000200 - - ERAD_GLOBAL : origin = 0x05E800, length = 0x000013 - ERAD_HWBP1 : origin = 0x05E900, length = 0x000008 - ERAD_HWBP2 : origin = 0x05E908, length = 0x000008 - ERAD_HWBP3 : origin = 0x05E910, length = 0x000008 - ERAD_HWBP4 : origin = 0x05E918, length = 0x000008 - ERAD_HWBP5 : origin = 0x05E920, length = 0x000008 - ERAD_HWBP6 : origin = 0x05E928, length = 0x000008 - ERAD_HWBP7 : origin = 0x05E930, length = 0x000008 - ERAD_HWBP8 : origin = 0x05E938, length = 0x000008 - ERAD_CTR1 : origin = 0x05E980, length = 0x000010 - ERAD_CTR2 : origin = 0x05E990, length = 0x000010 - ERAD_CTR3 : origin = 0x05E9A0, length = 0x000010 - ERAD_CTR4 : origin = 0x05E9B0, length = 0x000010 - - XBAR : origin = 0x007920, length = 0x000020 - SYNC_SOC : origin = 0x007940, length = 0x000010 - - XINT : origin = 0x007070, length = 0x000010 -} - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile - GROUP - { - EmuKeyVar - EmuBModeVar - FlashCallbackVar - FlashScalingVar - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - - AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - ClaPromCrc0RegsFile : > CLAPROMCRC, PAGE = 1 - - ClbXbarRegsFile : > CLB_XBAR, PAGE = 1 - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - - Dcc0RegsFile : > DCC0 PAGE = 1 - - DcsmBank0Z1RegsFile : > DCSM_BANK0_Z1, PAGE = 1 - DcsmBank0Z2RegsFile : > DCSM_BANK0_Z2, PAGE = 1 - DcsmBank1Z1RegsFile : > DCSM_BANK1_Z1, PAGE = 1 - DcsmBank1Z2RegsFile : > DCSM_BANK1_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA, PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - ECap7RegsFile : > ECAP7, PAGE = 1 - - Pga1RegsFile : > PGA1, PAGE = 1 - Pga2RegsFile : > PGA2, PAGE = 1 - Pga3RegsFile : > PGA3, PAGE = 1 - Pga4RegsFile : > PGA4, PAGE = 1 - Pga5RegsFile : > PGA5, PAGE = 1 - Pga6RegsFile : > PGA6, PAGE = 1 - Pga7RegsFile : > PGA7, PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - - EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - - EnhancedDebugGlobalRegsFile : > ERAD_GLOBAL, PAGE = 1 - EnhancedDebugHWBP1RegsFile : > ERAD_HWBP1, PAGE = 1 - EnhancedDebugHWBP2RegsFile : > ERAD_HWBP2, PAGE = 1 - EnhancedDebugHWBP3RegsFile : > ERAD_HWBP3, PAGE = 1 - EnhancedDebugHWBP4RegsFile : > ERAD_HWBP4, PAGE = 1 - EnhancedDebugHWBP5RegsFile : > ERAD_HWBP5, PAGE = 1 - EnhancedDebugHWBP6RegsFile : > ERAD_HWBP6, PAGE = 1 - EnhancedDebugHWBP7RegsFile : > ERAD_HWBP7, PAGE = 1 - EnhancedDebugHWBP8RegsFile : > ERAD_HWBP8, PAGE = 1 - EnhancedDebugCounter1RegsFile : > ERAD_CTR1, PAGE = 1 - EnhancedDebugCounter2RegsFile : > ERAD_CTR2, PAGE = 1 - EnhancedDebugCounter3RegsFile : > ERAD_CTR3, PAGE = 1 - EnhancedDebugCounter4RegsFile : > ERAD_CTR4, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - FsiTxaRegsFile : > FSITXA PAGE = 1 - FsiRxaRegsFile : > FSIRXA PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - I2caRegsFile : > I2CA, PAGE = 1 - - InputXbarRegsFile : > INPUT_XBAR PAGE = 1 - XbarRegsFile : > XBAR PAGE = 1 - - LinaRegsFile : > LINA, PAGE = 1 - LinbRegsFile : > LINB, PAGE = 1 - - MemCfgRegsFile : > MEMCFG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - - OutputXbarRegsFile : > OUTPUT_XBAR, PAGE = 1 - - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - PmbusaRegsFile : > PMBUSA, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - DevCfgRegsFile : > DEV_CFG, PAGE = 1 - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - SysPeriphAcRegsFile : > PERIPH_AC, PAGE = 1 - - SyncSocRegsFile : > SYNC_SOC, PAGE = 1 - - XintRegsFile : > XINT, PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h deleted file mode 100644 index d064fc1..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h +++ /dev/null @@ -1,1048 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc.h -// -// TITLE: ADC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ADC_H__ -#define __F28004X_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ADC Individual Register Bit Definitions: - -struct ADCCTL1_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position - Uint16 rsvd2:4; // 6:3 Reserved - Uint16 ADCPWDNZ:1; // 7 ADC Power Down - Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel - Uint16 rsvd3:1; // 12 Reserved - Uint16 ADCBSY:1; // 13 ADC Busy - Uint16 rsvd4:2; // 15:14 Reserved -}; - -union ADCCTL1_REG { - Uint16 all; - struct ADCCTL1_BITS bit; -}; - -struct ADCCTL2_BITS { // bits description - Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:5; // 12:8 Reserved - Uint16 rsvd5:3; // 15:13 Reserved -}; - -union ADCCTL2_REG { - Uint16 all; - struct ADCCTL2_BITS bit; -}; - -struct ADCBURSTCTL_BITS { // bits description - Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable -}; - -union ADCBURSTCTL_REG { - Uint16 all; - struct ADCBURSTCTL_BITS bit; -}; - -struct ADCINTFLG_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLG_REG { - Uint16 all; - struct ADCINTFLG_BITS bit; -}; - -struct ADCINTFLGCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLGCLR_REG { - Uint16 all; - struct ADCINTFLGCLR_BITS bit; -}; - -struct ADCINTOVF_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVF_REG { - Uint16 all; - struct ADCINTOVF_BITS bit; -}; - -struct ADCINTOVFCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVFCLR_REG { - Uint16 all; - struct ADCINTOVFCLR_BITS bit; -}; - -struct ADCINTSEL1N2_BITS { // bits description - Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable - Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable - Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL1N2_REG { - Uint16 all; - struct ADCINTSEL1N2_BITS bit; -}; - -struct ADCINTSEL3N4_BITS { // bits description - Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable - Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable - Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL3N4_REG { - Uint16 all; - struct ADCINTSEL3N4_BITS bit; -}; - -struct ADCSOCPRICTL_BITS { // bits description - Uint16 SOCPRIORITY:5; // 4:0 SOC Priority - Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCSOCPRICTL_REG { - Uint16 all; - struct ADCSOCPRICTL_BITS bit; -}; - -struct ADCINTSOCSEL1_BITS { // bits description - Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select - Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select - Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select - Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select - Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select - Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select - Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select - Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL1_REG { - Uint16 all; - struct ADCINTSOCSEL1_BITS bit; -}; - -struct ADCINTSOCSEL2_BITS { // bits description - Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select - Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select - Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select - Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select - Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select - Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select - Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select - Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL2_REG { - Uint16 all; - struct ADCINTSOCSEL2_BITS bit; -}; - -struct ADCSOCFLG1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag -}; - -union ADCSOCFLG1_REG { - Uint16 all; - struct ADCSOCFLG1_BITS bit; -}; - -struct ADCSOCFRC1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit - Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit - Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit - Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit - Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit - Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit - Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit - Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit - Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit - Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit - Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit - Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit - Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit - Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit - Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit - Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit -}; - -union ADCSOCFRC1_REG { - Uint16 all; - struct ADCSOCFRC1_BITS bit; -}; - -struct ADCSOCOVF1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag -}; - -union ADCSOCOVF1_REG { - Uint16 all; - struct ADCSOCOVF1_BITS bit; -}; - -struct ADCSOCOVFCLR1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit - Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit - Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit - Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit - Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit - Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit - Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit - Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit - Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit - Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit - Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit - Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit - Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit - Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit - Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit - Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit -}; - -union ADCSOCOVFCLR1_REG { - Uint16 all; - struct ADCSOCOVFCLR1_BITS bit; -}; - -struct ADCSOC0CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC0 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC0CTL_REG { - Uint32 all; - struct ADCSOC0CTL_BITS bit; -}; - -struct ADCSOC1CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC1 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC1CTL_REG { - Uint32 all; - struct ADCSOC1CTL_BITS bit; -}; - -struct ADCSOC2CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC2 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC2CTL_REG { - Uint32 all; - struct ADCSOC2CTL_BITS bit; -}; - -struct ADCSOC3CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC3 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC3CTL_REG { - Uint32 all; - struct ADCSOC3CTL_BITS bit; -}; - -struct ADCSOC4CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC4 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC4CTL_REG { - Uint32 all; - struct ADCSOC4CTL_BITS bit; -}; - -struct ADCSOC5CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC5 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC5CTL_REG { - Uint32 all; - struct ADCSOC5CTL_BITS bit; -}; - -struct ADCSOC6CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC6 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC6CTL_REG { - Uint32 all; - struct ADCSOC6CTL_BITS bit; -}; - -struct ADCSOC7CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC7 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC7CTL_REG { - Uint32 all; - struct ADCSOC7CTL_BITS bit; -}; - -struct ADCSOC8CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC8 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC8CTL_REG { - Uint32 all; - struct ADCSOC8CTL_BITS bit; -}; - -struct ADCSOC9CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC9 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC9CTL_REG { - Uint32 all; - struct ADCSOC9CTL_BITS bit; -}; - -struct ADCSOC10CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC10 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC10CTL_REG { - Uint32 all; - struct ADCSOC10CTL_BITS bit; -}; - -struct ADCSOC11CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC11 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC11CTL_REG { - Uint32 all; - struct ADCSOC11CTL_BITS bit; -}; - -struct ADCSOC12CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC12 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC12CTL_REG { - Uint32 all; - struct ADCSOC12CTL_BITS bit; -}; - -struct ADCSOC13CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC13 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC13CTL_REG { - Uint32 all; - struct ADCSOC13CTL_BITS bit; -}; - -struct ADCSOC14CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC14 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC14CTL_REG { - Uint32 all; - struct ADCSOC14CTL_BITS bit; -}; - -struct ADCSOC15CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC15 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC15CTL_REG { - Uint32 all; - struct ADCSOC15CTL_BITS bit; -}; - -struct ADCEVTSTAT_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSTAT_REG { - Uint16 all; - struct ADCEVTSTAT_BITS bit; -}; - -struct ADCEVTCLR_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTCLR_REG { - Uint16 all; - struct ADCEVTCLR_BITS bit; -}; - -struct ADCEVTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSEL_REG { - Uint16 all; - struct ADCEVTSEL_BITS bit; -}; - -struct ADCEVTINTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTINTSEL_REG { - Uint16 all; - struct ADCEVTINTSEL_BITS bit; -}; - -struct ADCCOUNTER_BITS { // bits description - Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCCOUNTER_REG { - Uint16 all; - struct ADCCOUNTER_BITS bit; -}; - -struct ADCREV_BITS { // bits description - Uint16 TYPE:8; // 7:0 ADC Type - Uint16 REV:8; // 15:8 ADC Revision -}; - -union ADCREV_REG { - Uint16 all; - struct ADCREV_BITS bit; -}; - -struct ADCOFFTRIM_BITS { // bits description - Uint16 OFFTRIM:12; // 11:0 ADC Offset Trim - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCOFFTRIM_REG { - Uint16 all; - struct ADCOFFTRIM_BITS bit; -}; - -struct ADCPPB1CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB1CONFIG_REG { - Uint16 all; - struct ADCPPB1CONFIG_BITS bit; -}; - -struct ADCPPB1STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB1STAMP_REG { - Uint16 all; - struct ADCPPB1STAMP_BITS bit; -}; - -struct ADCPPB1OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB1OFFCAL_REG { - Uint16 all; - struct ADCPPB1OFFCAL_BITS bit; -}; - -struct ADCPPB1TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB1TRIPHI_REG { - Uint32 all; - struct ADCPPB1TRIPHI_BITS bit; -}; - -struct ADCPPB1TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp -}; - -union ADCPPB1TRIPLO_REG { - Uint32 all; - struct ADCPPB1TRIPLO_BITS bit; -}; - -struct ADCPPB2CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB2CONFIG_REG { - Uint16 all; - struct ADCPPB2CONFIG_BITS bit; -}; - -struct ADCPPB2STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB2STAMP_REG { - Uint16 all; - struct ADCPPB2STAMP_BITS bit; -}; - -struct ADCPPB2OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB2OFFCAL_REG { - Uint16 all; - struct ADCPPB2OFFCAL_BITS bit; -}; - -struct ADCPPB2TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB2TRIPHI_REG { - Uint32 all; - struct ADCPPB2TRIPHI_BITS bit; -}; - -struct ADCPPB2TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp -}; - -union ADCPPB2TRIPLO_REG { - Uint32 all; - struct ADCPPB2TRIPLO_BITS bit; -}; - -struct ADCPPB3CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB3CONFIG_REG { - Uint16 all; - struct ADCPPB3CONFIG_BITS bit; -}; - -struct ADCPPB3STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB3STAMP_REG { - Uint16 all; - struct ADCPPB3STAMP_BITS bit; -}; - -struct ADCPPB3OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB3OFFCAL_REG { - Uint16 all; - struct ADCPPB3OFFCAL_BITS bit; -}; - -struct ADCPPB3TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB3TRIPHI_REG { - Uint32 all; - struct ADCPPB3TRIPHI_BITS bit; -}; - -struct ADCPPB3TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp -}; - -union ADCPPB3TRIPLO_REG { - Uint32 all; - struct ADCPPB3TRIPLO_BITS bit; -}; - -struct ADCPPB4CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB4CONFIG_REG { - Uint16 all; - struct ADCPPB4CONFIG_BITS bit; -}; - -struct ADCPPB4STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB4STAMP_REG { - Uint16 all; - struct ADCPPB4STAMP_BITS bit; -}; - -struct ADCPPB4OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB4OFFCAL_REG { - Uint16 all; - struct ADCPPB4OFFCAL_BITS bit; -}; - -struct ADCPPB4TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB4TRIPHI_REG { - Uint32 all; - struct ADCPPB4TRIPHI_BITS bit; -}; - -struct ADCPPB4TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp -}; - -union ADCPPB4TRIPLO_REG { - Uint32 all; - struct ADCPPB4TRIPLO_BITS bit; -}; - -struct ADC_REGS { - union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register - union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register - union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register - union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register - union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register - union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register - union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register - union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register - union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register - union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register - union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register - union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register - union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register - union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register - union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register - union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register - union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register - union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register - union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register - union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register - union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register - union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register - union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register - union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register - union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register - union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register - union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register - union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register - union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register - union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register - union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register - union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register - union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register - Uint16 rsvd1; // Reserved - union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register - Uint16 rsvd2; // Reserved - union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register - Uint16 rsvd3; // Reserved - union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register - Uint16 rsvd4[2]; // Reserved - union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register - union ADCREV_REG ADCREV; // ADC Revision Register - union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register - Uint16 rsvd5[4]; // Reserved - union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register - union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register - union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register - Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register - union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register - union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register - union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register - union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register - union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register - Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register - union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register - union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register - union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register - union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register - union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register - Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register - union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register - union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register - union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register - union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register - union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register - Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register - union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register - union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register - Uint16 rsvd6[15]; // Reserved - Uint16 ADCINTCYCLE; // ADC Early Interrupt Generation Cycle - Uint16 rsvd7[16]; // Reserved -}; - -struct ADCPPB1RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB1RESULT_REG { - Uint32 all; - struct ADCPPB1RESULT_BITS bit; -}; - -struct ADCPPB2RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB2RESULT_REG { - Uint32 all; - struct ADCPPB2RESULT_BITS bit; -}; - -struct ADCPPB3RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB3RESULT_REG { - Uint32 all; - struct ADCPPB3RESULT_BITS bit; -}; - -struct ADCPPB4RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB4RESULT_REG { - Uint32 all; - struct ADCPPB4RESULT_BITS bit; -}; - -struct ADC_RESULT_REGS { - Uint16 ADCRESULT0; // ADC Result 0 Register - Uint16 ADCRESULT1; // ADC Result 1 Register - Uint16 ADCRESULT2; // ADC Result 2 Register - Uint16 ADCRESULT3; // ADC Result 3 Register - Uint16 ADCRESULT4; // ADC Result 4 Register - Uint16 ADCRESULT5; // ADC Result 5 Register - Uint16 ADCRESULT6; // ADC Result 6 Register - Uint16 ADCRESULT7; // ADC Result 7 Register - Uint16 ADCRESULT8; // ADC Result 8 Register - Uint16 ADCRESULT9; // ADC Result 9 Register - Uint16 ADCRESULT10; // ADC Result 10 Register - Uint16 ADCRESULT11; // ADC Result 11 Register - Uint16 ADCRESULT12; // ADC Result 12 Register - Uint16 ADCRESULT13; // ADC Result 13 Register - Uint16 ADCRESULT14; // ADC Result 14 Register - Uint16 ADCRESULT15; // ADC Result 15 Register - union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register - union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register - union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register - union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register -}; - -//--------------------------------------------------------------------------- -// ADC External References & Function Declarations: -// -extern volatile struct ADC_RESULT_REGS AdcaResultRegs; -extern volatile struct ADC_RESULT_REGS AdcbResultRegs; -extern volatile struct ADC_RESULT_REGS AdccResultRegs; -extern volatile struct ADC_REGS AdcaRegs; -extern volatile struct ADC_REGS AdcbRegs; -extern volatile struct ADC_REGS AdccRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h deleted file mode 100644 index ce95230..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h +++ /dev/null @@ -1,232 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_analogsubsys.h -// -// TITLE: ANALOGSUBSYS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ANALOGSUBSYS_H__ -#define __F28004X_ANALOGSUBSYS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS Individual Register Bit Definitions: - -struct ANAREFPP_BITS { // bits description - Uint16 ANAREFBDIS:1; // 0 Disable ANAREFB - Uint16 ANAREFCDIS:1; // 1 Disable ANAREFC - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union ANAREFPP_REG { - Uint16 all; - struct ANAREFPP_BITS bit; -}; - -struct TSNSCTL_BITS { // bits description - Uint16 ENABLE:1; // 0 Temperature Sensor Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TSNSCTL_REG { - Uint16 all; - struct TSNSCTL_BITS bit; -}; - -struct ANAREFCTL_BITS { // bits description - Uint16 ANAREFASEL:1; // 0 Analog Reference A Select - Uint16 ANAREFBSEL:1; // 1 Analog Reference B Select - Uint16 ANAREFCSEL:1; // 2 Analog Reference C Select - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 ANAREFA2P5SEL:1; // 8 Analog Reference A Select - Uint16 ANAREFB2P5SEL:1; // 9 Analog Reference B Select - Uint16 ANAREFC2P5SEL:1; // 10 Analog Reference B Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union ANAREFCTL_REG { - Uint16 all; - struct ANAREFCTL_BITS bit; -}; - -struct DCDCCTL_BITS { // bits description - Uint16 DCDCEN:1; // 0 DCDC Enable - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:15; // 30:16 Reserved - Uint16 rsvd3:1; // 31 Reserved -}; - -union DCDCCTL_REG { - Uint32 all; - struct DCDCCTL_BITS bit; -}; - -struct DCDCSTS_BITS { // bits description - Uint16 INDDETECT:1; // 0 Inductor Detected - Uint16 SWSEQDONE:1; // 1 Switch sequence to DC-DC done. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:13; // 15:3 Reserved -}; - -union DCDCSTS_REG { - Uint16 all; - struct DCDCSTS_BITS bit; -}; - -struct CMPHPMXSEL_BITS { // bits description - Uint16 CMP1HPMXSEL:3; // 2:0 CMP1HPMXSEL bits - Uint16 CMP2HPMXSEL:3; // 5:3 CMP2HPMXSEL bits - Uint16 CMP3HPMXSEL:3; // 8:6 CMP3HPMXSEL bits - Uint16 CMP4HPMXSEL:3; // 11:9 CMP4HPMXSEL bits - Uint16 CMP5HPMXSEL:3; // 14:12 CMP5HPMXSEL bits - Uint16 rsvd1:1; // 15 Reserved - Uint16 CMP6HPMXSEL:3; // 18:16 CMP6HPMXSEL bits - Uint16 CMP7HPMXSEL:3; // 21:19 CMP7HPMXSEL bits - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union CMPHPMXSEL_REG { - Uint32 all; - struct CMPHPMXSEL_BITS bit; -}; - -struct CMPLPMXSEL_BITS { // bits description - Uint16 CMP1LPMXSEL:3; // 2:0 CMP1LPMXSEL bits - Uint16 CMP2LPMXSEL:3; // 5:3 CMP2LPMXSEL bits - Uint16 CMP3LPMXSEL:3; // 8:6 CMP3LPMXSEL bits - Uint16 CMP4LPMXSEL:3; // 11:9 CMP4LPMXSEL bits - Uint16 CMP5LPMXSEL:3; // 14:12 CMP5LPMXSEL bits - Uint16 rsvd1:1; // 15 Reserved - Uint16 CMP6LPMXSEL:3; // 18:16 CMP6LPMXSEL bits - Uint16 CMP7LPMXSEL:3; // 21:19 CMP7LPMXSEL bits - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union CMPLPMXSEL_REG { - Uint32 all; - struct CMPLPMXSEL_BITS bit; -}; - -struct CMPHNMXSEL_BITS { // bits description - Uint16 CMP1HNMXSEL:1; // 0 CMP1HNMXSEL bits - Uint16 CMP2HNMXSEL:1; // 1 CMP2HNMXSEL bits - Uint16 CMP3HNMXSEL:1; // 2 CMP3HNMXSEL bits - Uint16 CMP4HNMXSEL:1; // 3 CMP4HNMXSEL bits - Uint16 CMP5HNMXSEL:1; // 4 CMP5HNMXSEL bits - Uint16 CMP6HNMXSEL:1; // 5 CMP6HNMXSEL bits - Uint16 CMP7HNMXSEL:1; // 6 CMP7HNMXSEL bits - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union CMPHNMXSEL_REG { - Uint16 all; - struct CMPHNMXSEL_BITS bit; -}; - -struct CMPLNMXSEL_BITS { // bits description - Uint16 CMP1LNMXSEL:1; // 0 CMP1LNMXSEL bits - Uint16 CMP2LNMXSEL:1; // 1 CMP2LNMXSEL bits - Uint16 CMP3LNMXSEL:1; // 2 CMP3LNMXSEL bits - Uint16 CMP4LNMXSEL:1; // 3 CMP4LNMXSEL bits - Uint16 CMP5LNMXSEL:1; // 4 CMP5LNMXSEL bits - Uint16 CMP6LNMXSEL:1; // 5 CMP6LNMXSEL bits - Uint16 CMP7LNMXSEL:1; // 6 CMP7LNMXSEL bits - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union CMPLNMXSEL_REG { - Uint16 all; - struct CMPLNMXSEL_BITS bit; -}; - -struct LOCK_BITS { // bits description - Uint16 TSNSCTL:1; // 0 TSNSCTL Register lock bit - Uint16 ANAREFCTL:1; // 1 ANAREFCTL Register lock bit - Uint16 VMONCTL:1; // 2 VMONCTL Register lock bit - Uint16 DCDCCTL:1; // 3 DCDCCTL Register lock bit - Uint16 ADCINMXSEL:1; // 4 ADCINMXSEL Register lock bit - Uint16 CMPHPMXSEL:1; // 5 CMPHPMXSEL Register lock bit - Uint16 CMPLPMXSEL:1; // 6 CMPLPMXSEL Register lock bit - Uint16 CMPHNMXSEL:1; // 7 CMPHNMXSEL Register lock bit - Uint16 CMPLNMXSEL:1; // 8 CMPLNMXSEL Register lock bit - Uint16 VREGCTL:1; // 9 VREGCTL Register lock bit - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOCK_REG { - Uint32 all; - struct LOCK_BITS bit; -}; - -struct ANALOG_SUBSYS_REGS { - Uint16 rsvd1[30]; // Reserved - union ANAREFPP_REG ANAREFPP; // ADC Analog Reference Peripheral Properties register - Uint16 rsvd2[65]; // Reserved - union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register - Uint16 rsvd3[7]; // Reserved - union ANAREFCTL_REG ANAREFCTL; // Analog Reference Control Register - Uint16 rsvd4[15]; // Reserved - union DCDCCTL_REG DCDCCTL; // DC-DC control register. - union DCDCSTS_REG DCDCSTS; // DC-DC status register. - Uint16 rsvd5[7]; // Reserved - union CMPHPMXSEL_REG CMPHPMXSEL; // Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details. - union CMPLPMXSEL_REG CMPLPMXSEL; // Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details. - union CMPHNMXSEL_REG CMPHNMXSEL; // Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details. - union CMPLNMXSEL_REG CMPLNMXSEL; // Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details. - Uint16 rsvd6[6]; // Reserved - union LOCK_REG LOCK; // Lock Register -}; - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS External References & Function Declarations: -// -extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h deleted file mode 100644 index 6417951..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h +++ /dev/null @@ -1,607 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_can.h -// -// TITLE: CAN Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CAN_H__ -#define __F28004X_CAN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CAN Individual Register Bit Definitions: - -struct CAN_CTL_BITS { // bits description - bp_16 Init:1; // 0 Initialization - bp_16 IE0:1; // 1 Interrupt line 0 Enable - bp_16 SIE:1; // 2 Status Change Interrupt Enable - bp_16 EIE:1; // 3 Error Interrupt Enable - bp_16 rsvd1:1; // 4 Reserved - bp_16 DAR:1; // 5 Disable Automatic Retransmission - bp_16 CCE:1; // 6 Configuration Change Enable - bp_16 Test:1; // 7 Test Mode Enable - bp_16 IDS:1; // 8 Interruption Debug Support Enable - bp_16 ABO:1; // 9 Auto-Bus-On Enable - bp_16 PMD:4; // 13:10 Parity on/off - bp_16 rsvd2:1; // 14 Reserved - bp_16 SWR:1; // 15 SW Reset Enable - bp_32 INITDBG:1; // 16 Debug Mode Status - bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled - bp_32 DE1:1; // 18 Enable DMA request line - bp_32 DE2:1; // 19 Enable DMA request line - bp_32 DE3:1; // 20 Enable DMA request line - bp_32 rsvd3:3; // 23:21 Reserved - bp_32 rsvd4:1; // 24 Reserved - bp_32 rsvd5:1; // 25 Reserved - bp_32 rsvd6:6; // 31:26 Reserved -}; - -union CAN_CTL_REG { - bp_32 all; - struct CAN_CTL_BITS bit; -}; - -struct CAN_ES_BITS { // bits description - bp_16 LEC:3; // 2:0 Last Error Code - bp_16 TxOk:1; // 3 Transmission status - bp_16 RxOk:1; // 4 Reception status - bp_16 EPass:1; // 5 Error Passive State - bp_16 EWarn:1; // 6 Warning State - bp_16 BOff:1; // 7 Bus-Off State - bp_16 PER:1; // 8 Parity Error Detected - bp_16 rsvd1:1; // 9 Reserved - bp_16 rsvd2:1; // 10 Reserved - bp_16 rsvd3:5; // 15:11 Reserved - bp_32 rsvd4:16; // 31:16 Reserved -}; - -union CAN_ES_REG { - bp_32 all; - struct CAN_ES_BITS bit; -}; - -struct CAN_ERRC_BITS { // bits description - bp_16 TEC:8; // 7:0 Transmit Error Counter - bp_16 REC:7; // 14:8 Receive Error Counter - bp_16 RP:1; // 15 Receive Error Passive - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union CAN_ERRC_REG { - bp_32 all; - struct CAN_ERRC_BITS bit; -}; - -struct CAN_BTR_BITS { // bits description - bp_16 BRP:6; // 5:0 Baud Rate Prescaler - bp_16 SJW:2; // 7:6 Synchronization Jump Width - bp_16 TSEG1:4; // 11:8 Time segment - bp_16 TSEG2:3; // 14:12 Time segment - bp_16 rsvd1:1; // 15 Reserved - bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension - bp_32 rsvd2:12; // 31:20 Reserved -}; - -union CAN_BTR_REG { - bp_32 all; - struct CAN_BTR_BITS bit; -}; - -struct CAN_INT_BITS { // bits description - bp_16 INT0ID:16; // 15:0 Interrupt Identifier - bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union CAN_INT_REG { - bp_32 all; - struct CAN_INT_BITS bit; -}; - -struct CAN_TEST_BITS { // bits description - bp_16 rsvd1:3; // 2:0 Reserved - bp_16 SILENT:1; // 3 Silent Mode - bp_16 LBACK:1; // 4 Loopback Mode - bp_16 TX:2; // 6:5 CANTX Pin Control - bp_16 RX:1; // 7 CANRX Pin Status - bp_16 EXL:1; // 8 External Loopback Mode - bp_16 RDA:1; // 9 RAM Direct Access Enable: - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_TEST_REG { - bp_32 all; - struct CAN_TEST_BITS bit; -}; - -struct CAN_PERR_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 WORD_NUM:3; // 10:8 Word Number - bp_16 rsvd1:5; // 15:11 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_PERR_REG { - bp_32 all; - struct CAN_PERR_BITS bit; -}; - -struct CAN_RAM_INIT_BITS { // bits description - bp_16 KEY0:1; // 0 KEY0 - bp_16 KEY1:1; // 1 KEY1 - bp_16 KEY2:1; // 2 KEY2 - bp_16 KEY3:1; // 3 KEY3 - bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM - bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete - bp_16 rsvd1:10; // 15:6 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_RAM_INIT_REG { - bp_32 all; - struct CAN_RAM_INIT_BITS bit; -}; - -struct CAN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_EN_REG { - bp_32 all; - struct CAN_GLB_INT_EN_BITS bit; -}; - -struct CAN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_FLG_REG { - bp_32 all; - struct CAN_GLB_INT_FLG_BITS bit; -}; - -struct CAN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_CLR_REG { - bp_32 all; - struct CAN_GLB_INT_CLR_BITS bit; -}; - -struct CAN_TXRQ_X_BITS { // bits description - bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 - bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_TXRQ_X_REG { - bp_32 all; - struct CAN_TXRQ_X_BITS bit; -}; - -struct CAN_NDAT_X_BITS { // bits description - bp_16 NewDatReg1:2; // 1:0 New Data Register 1 - bp_16 NewDatReg2:2; // 3:2 New Data Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_NDAT_X_REG { - bp_32 all; - struct CAN_NDAT_X_BITS bit; -}; - -struct CAN_IPEN_X_BITS { // bits description - bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 - bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IPEN_X_REG { - bp_32 all; - struct CAN_IPEN_X_BITS bit; -}; - -struct CAN_MVAL_X_BITS { // bits description - bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 - bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_MVAL_X_REG { - bp_32 all; - struct CAN_MVAL_X_BITS bit; -}; - -struct CAN_IF1CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 DMAactive:1; // 14 DMA Status - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TXRQST:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union CAN_IF1CMD_REG { - bp_32 all; - struct CAN_IF1CMD_BITS bit; -}; - -struct CAN_IF1MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF1MSK_REG { - bp_32 all; - struct CAN_IF1MSK_BITS bit; -}; - -struct CAN_IF1ARB_BITS { // bits description - bp_32 ID:29; // 28:0 ` - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF1ARB_REG { - bp_32 all; - struct CAN_IF1ARB_BITS bit; -}; - -struct CAN_IF1MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF1MCTL_REG { - bp_32 all; - struct CAN_IF1MCTL_BITS bit; -}; - -struct CAN_IF1DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF1DATA_REG { - bp_32 all; - struct CAN_IF1DATA_BITS bit; -}; - -struct CAN_IF1DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF1DATB_REG { - bp_32 all; - struct CAN_IF1DATB_BITS bit; -}; - -struct CAN_IF2CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 DMAactive:1; // 14 DMA Status - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TxRqst:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union CAN_IF2CMD_REG { - bp_32 all; - struct CAN_IF2CMD_BITS bit; -}; - -struct CAN_IF2MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF2MSK_REG { - bp_32 all; - struct CAN_IF2MSK_BITS bit; -}; - -struct CAN_IF2ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF2ARB_REG { - bp_32 all; - struct CAN_IF2ARB_BITS bit; -}; - -struct CAN_IF2MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF2MCTL_REG { - bp_32 all; - struct CAN_IF2MCTL_BITS bit; -}; - -struct CAN_IF2DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF2DATA_REG { - bp_32 all; - struct CAN_IF2DATA_BITS bit; -}; - -struct CAN_IF2DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF2DATB_REG { - bp_32 all; - struct CAN_IF2DATB_BITS bit; -}; - -struct CAN_IF3OBS_BITS { // bits description - bp_16 Mask:1; // 0 Mask data read observation - bp_16 Arb:1; // 1 Arbitration data read observation - bp_16 Ctrl:1; // 2 Ctrl read observation - bp_16 Data_A:1; // 3 Data A read observation - bp_16 Data_B:1; // 4 Data B read observation - bp_16 rsvd1:3; // 7:5 Reserved - bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access - bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access - bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access - bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access - bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access - bp_16 rsvd2:2; // 14:13 Reserved - bp_16 IF3Upd:1; // 15 IF3 Update Data - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_IF3OBS_REG { - bp_32 all; - struct CAN_IF3OBS_BITS bit; -}; - -struct CAN_IF3MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF3MSK_REG { - bp_32 all; - struct CAN_IF3MSK_BITS bit; -}; - -struct CAN_IF3ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF3ARB_REG { - bp_32 all; - struct CAN_IF3ARB_BITS bit; -}; - -struct CAN_IF3MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF3MCTL_REG { - bp_32 all; - struct CAN_IF3MCTL_BITS bit; -}; - -struct CAN_IF3DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF3DATA_REG { - bp_32 all; - struct CAN_IF3DATA_BITS bit; -}; - -struct CAN_IF3DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF3DATB_REG { - bp_32 all; - struct CAN_IF3DATB_BITS bit; -}; - -struct CAN_REGS { - union CAN_CTL_REG CAN_CTL; // CAN Control Register - union CAN_ES_REG CAN_ES; // Error and Status Register - union CAN_ERRC_REG CAN_ERRC; // Error Counter Register - union CAN_BTR_REG CAN_BTR; // Bit Timing Register - union CAN_INT_REG CAN_INT; // Interrupt Register - union CAN_TEST_REG CAN_TEST; // Test Register - uint32_t rsvd6[2]; // Reserved - union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register - uint32_t rsvd7[16]; // Reserved - union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register - uint32_t rsvd8[6]; // Reserved - union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register - union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register - union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register - uint32_t rsvd11[18]; // Reserved - bp_32 CAN_ABOTR; // Auto-Bus-On Time Register - union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register - bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register - uint32_t rsvd14[6]; // Reserved - union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register - bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register - uint32_t rsvd16[6]; // Reserved - union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register - bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register - uint32_t rsvd18[6]; // Reserved - union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register - bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register - uint32_t rsvd20[8]; // Reserved - bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register - uint32_t rsvd21[18]; // Reserved - union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register - union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register - union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register - union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register - union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register - union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register - uint32_t rsvd27[4]; // Reserved - union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register - union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register - union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register - union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register - union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register - union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register - uint32_t rsvd33[4]; // Reserved - union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register - union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register - union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register - union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register - union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register - union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register - uint32_t rsvd39[4]; // Reserved - bp_32 CAN_IF3UPD; // IF3 Update Enable Register - uint32_t rsvd40[78]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CAN External References & Function Declarations: -// -extern volatile struct CAN_REGS CanaRegs; -extern volatile struct CAN_REGS CanbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h deleted file mode 100644 index 9a64068..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h +++ /dev/null @@ -1,366 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cla.h -// -// TITLE: CLA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CLA_H__ -#define __F28004X_CLA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA Individual Register Bit Definitions: - -struct MCTL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset - Uint16 SOFTRESET:1; // 1 Soft Reset - Uint16 IACKE:1; // 2 IACK enable - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union MCTL_REG { - Uint16 all; - struct MCTL_BITS bit; -}; - -struct SOFTINTEN_BITS { // bits description - Uint16 TASK1:1; // 0 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK2:1; // 1 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK3:1; // 2 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK4:1; // 3 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK5:1; // 4 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK6:1; // 5 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK7:1; // 6 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK8:1; // 7 Configure Software Interrupt or End of Task interrupt. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SOFTINTEN_REG { - Uint16 all; - struct SOFTINTEN_BITS bit; -}; - -struct _MSTSBGRND_BITS { // bits description - Uint16 RUN:1; // 0 Background task run status bit. - Uint16 _BGINTM:1; // 1 Indicates whether background task can be interrupted. - Uint16 BGOVF:1; // 2 background task harware trigger overflow. - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union _MSTSBGRND_REG { - Uint16 all; - struct _MSTSBGRND_BITS bit; -}; - -struct _MCTLBGRND_BITS { // bits description - Uint16 BGSTART:1; // 0 Background task start bit - Uint16 TRIGEN:1; // 1 Background task hardware trigger enable - Uint16 rsvd1:13; // 14:2 Reserved - Uint16 BGEN:1; // 15 Enable background task -}; - -union _MCTLBGRND_REG { - Uint16 all; - struct _MCTLBGRND_BITS bit; -}; - -struct MIFR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFR_REG { - Uint16 all; - struct MIFR_BITS bit; -}; - -struct MIOVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIOVF_REG { - Uint16 all; - struct MIOVF_BITS bit; -}; - -struct MIFRC_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Force - Uint16 INT2:1; // 1 Task 2 Interrupt Force - Uint16 INT3:1; // 2 Task 3 Interrupt Force - Uint16 INT4:1; // 3 Task 4 Interrupt Force - Uint16 INT5:1; // 4 Task 5 Interrupt Force - Uint16 INT6:1; // 5 Task 6 Interrupt Force - Uint16 INT7:1; // 6 Task 7 Interrupt Force - Uint16 INT8:1; // 7 Task 8 Interrupt Force - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFRC_REG { - Uint16 all; - struct MIFRC_BITS bit; -}; - -struct MICLR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLR_REG { - Uint16 all; - struct MICLR_BITS bit; -}; - -struct MICLROVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLROVF_REG { - Uint16 all; - struct MICLROVF_BITS bit; -}; - -struct MIER_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Enable - Uint16 INT2:1; // 1 Task 2 Interrupt Enable - Uint16 INT3:1; // 2 Task 3 Interrupt Enable - Uint16 INT4:1; // 3 Task 4 Interrupt Enable - Uint16 INT5:1; // 4 Task 5 Interrupt Enable - Uint16 INT6:1; // 5 Task 6 Interrupt Enable - Uint16 INT7:1; // 6 Task 7 Interrupt Enable - Uint16 INT8:1; // 7 Task 8 Interrupt Enable - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIER_REG { - Uint16 all; - struct MIER_BITS bit; -}; - -struct MIRUN_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Run Status - Uint16 INT2:1; // 1 Task 2 Run Status - Uint16 INT3:1; // 2 Task 3 Run Status - Uint16 INT4:1; // 3 Task 4 Run Status - Uint16 INT5:1; // 4 Task 5 Run Status - Uint16 INT6:1; // 5 Task 6 Run Status - Uint16 INT7:1; // 6 Task 7 Run Status - Uint16 INT8:1; // 7 Task 8 Run Status - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIRUN_REG { - Uint16 all; - struct MIRUN_BITS bit; -}; - -struct _MSTF_BITS { // bits description - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint32 _RPC:16; // 27:12 Return PC - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union _MSTF_REG { - Uint32 all; - struct _MSTF_BITS bit; -}; - -struct _MPSACTL_BITS { // bits description - Uint16 MPABSTART:1; // 0 Start logging PAB onto PSA1 - Uint16 MPABCYC:1; // 1 PAB logging into PSA1 is on every cycle or when PAB changes. - Uint16 MDWDBSTART:1; // 2 Start logging DWDB onto PSA2 - Uint16 MDWDBCYC:1; // 3 DWDB logging into PSA2 is on every cycle. - Uint16 MPSA1CLEAR:1; // 4 PSA1 clear - Uint16 MPSA2CLEAR:1; // 5 PSA2 Clear - Uint16 MPSA2CFG:2; // 7:6 PSA2 Polynomial Configuration - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union _MPSACTL_REG { - Uint16 all; - struct _MPSACTL_BITS bit; -}; - -union MR_REG { - Uint32 i32; - float f32; -}; - -struct CLA_REGS { - Uint16 MVECT1; // Task Interrupt Vector - Uint16 MVECT2; // Task Interrupt Vector - Uint16 MVECT3; // Task Interrupt Vector - Uint16 MVECT4; // Task Interrupt Vector - Uint16 MVECT5; // Task Interrupt Vector - Uint16 MVECT6; // Task Interrupt Vector - Uint16 MVECT7; // Task Interrupt Vector - Uint16 MVECT8; // Task Interrupt Vector - Uint16 rsvd1[8]; // Reserved - union MCTL_REG MCTL; // Control Register - Uint16 rsvd2[10]; // Reserved - Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - union _MSTSBGRND_REG _MSTSBGRND; // Status register for the back ground task. - union _MCTLBGRND_REG _MCTLBGRND; // Control register for the back ground task. - Uint16 _MVECTBGRND; // Vector for the back ground task. - union MIFR_REG MIFR; // Interrupt Flag Register - union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register - union MIFRC_REG MIFRC; // Interrupt Force Register - union MICLR_REG MICLR; // Interrupt Flag Clear Register - union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register - union MIER_REG MIER; // Interrupt Enable Register - union MIRUN_REG MIRUN; // Interrupt Run Status Register - Uint16 rsvd3; // Reserved - Uint16 _MPC; // CLA Program Counter - Uint16 rsvd4; // Reserved - Uint16 _MAR0; // CLA Auxiliary Register 0 - Uint16 _MAR1; // CLA Auxiliary Register 1 - Uint16 rsvd5[2]; // Reserved - union _MSTF_REG _MSTF; // CLA Floating-Point Status Register - union MR_REG _MR0; // CLA Floating-Point Result Register 0 - Uint16 rsvd6[2]; // Reserved - union MR_REG _MR1; // CLA Floating-Point Result Register 1 - Uint16 rsvd7[2]; // Reserved - union MR_REG _MR2; // CLA Floating-Point Result Register 2 - Uint16 rsvd8[2]; // Reserved - union MR_REG _MR3; // CLA Floating-Point Result Register 3 - Uint16 rsvd9[4]; // Reserved - union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register - Uint16 rsvd10; // Reserved - Uint32 _MPSA1; // CLA PSA1 Register - Uint32 _MPSA2; // CLA PSA2 Register - Uint16 rsvd11[56]; // Reserved -}; - -struct SOFTINTFRC_BITS { // bits description - Uint16 TASK1:1; // 0 Force CLA software interrupt for the corresponding task. - Uint16 TASK2:1; // 1 Force CLA software interrupt for the corresponding task. - Uint16 TASK3:1; // 2 Force CLA software interrupt for the corresponding task. - Uint16 TASK4:1; // 3 Force CLA software interrupt for the corresponding task. - Uint16 TASK5:1; // 4 Force CLA software interrupt for the corresponding task. - Uint16 TASK6:1; // 5 Force CLA software interrupt for the corresponding task. - Uint16 TASK7:1; // 6 Force CLA software interrupt for the corresponding task. - Uint16 TASK8:1; // 7 Force CLA software interrupt for the corresponding task. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SOFTINTFRC_REG { - Uint16 all; - struct SOFTINTFRC_BITS bit; -}; - -struct CLA_ONLY_REGS { - Uint16 rsvd1[128]; // Reserved - Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. - Uint16 rsvd2[63]; // Reserved - union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register - Uint16 rsvd3; // Reserved - Uint32 _MPSA1; // CLA PSA1 Register - Uint32 _MPSA2; // CLA PSA2 Register - Uint16 rsvd4[26]; // Reserved - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - Uint16 rsvd5; // Reserved - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register - Uint16 rsvd6[12]; // Reserved -}; - -struct CLA_SOFTINT_REGS { - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - Uint16 rsvd1; // Reserved - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register - Uint16 rsvd2[12]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CLA External References & Function Declarations: -// -extern volatile struct CLA_ONLY_REGS Cla1OnlyRegs; -extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; -extern volatile struct CLA_REGS Cla1Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h deleted file mode 100644 index 0409187..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h +++ /dev/null @@ -1,157 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cla_prom_crc32.h -// -// TITLE: CLA_PROM_CRC32 Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CLA_PROM_CRC32_H__ -#define __F28004X_CLA_PROM_CRC32_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA_PROM_CRC32 Individual Register Bit Definitions: - -struct CRC32_CONTROLREG_BITS { // bits description - Uint16 START:1; // 0 Start Bit - Uint16 rsvd1:3; // 3:1 Reserved - Uint16 FREE_SOFT:1; // 4 emulation control bit - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 HALT:1; // 8 Halt Bit - Uint16 rsvd3:7; // 15:9 Reserved - Uint16 BLOCKSIZE:7; // 22:16 Block size of ROM for which CRC is to be calculated - Uint16 rsvd4:9; // 31:23 Reserved -}; - -union CRC32_CONTROLREG_REG { - Uint32 all; - struct CRC32_CONTROLREG_BITS bit; -}; - -struct CRC32_STATUSREG_BITS { // bits description - Uint16 CURRENTADDR:16; // 15:0 Point to the data fetch unit current address - Uint16 rsvd1:7; // 22:16 Reserved - Uint16 CRCCHECKSTATUS:1; // 23 CRC active status - Uint16 rsvd2:7; // 30:24 Reserved - Uint16 RUNSTATUS:1; // 31 CRC active status -}; - -union CRC32_STATUSREG_REG { - Uint32 all; - struct CRC32_STATUSREG_BITS bit; -}; - -struct CRC32_INTEN_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CRCDONE:1; // 1 CRCDONE interrupt enable register - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CRC32_INTEN_REG { - Uint32 all; - struct CRC32_INTEN_BITS bit; -}; - -struct CRC32_FLG_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt status flag - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt status flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CRC32_FLG_REG { - Uint32 all; - struct CRC32_FLG_BITS bit; -}; - -struct CRC32_CLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt clear - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CRC32_CLR_REG { - Uint32 all; - struct CRC32_CLR_BITS bit; -}; - -struct CRC32_FRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt force - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CRC32_FRC_REG { - Uint32 all; - struct CRC32_FRC_BITS bit; -}; - -struct CLA_PROM_CRC32_REGS { - union CRC32_CONTROLREG_REG CRC32_CONTROLREG; // CRC32-Control Register - Uint32 CRC32_STARTADDRESS; // CRC32-Start address register - Uint32 CRC32_SEED; // CRC32-Seed Register - union CRC32_STATUSREG_REG CRC32_STATUSREG; // CRC32-Status Register - Uint32 CRC32_CRCRESULT; // CRC32-CRC result Register - Uint32 CRC32_GOLDENCRC; // CRC32-Golden CRC register - Uint16 rsvd1[12]; // Reserved - union CRC32_INTEN_REG CRC32_INTEN; // CRC32-Interrupt enable register - union CRC32_FLG_REG CRC32_FLG; // CRC32-Interrupt Flag Register - union CRC32_CLR_REG CRC32_CLR; // CRC32-Interrupt Clear Register - union CRC32_FRC_REG CRC32_FRC; // CRC32-Interrupt Force Register -}; - -//--------------------------------------------------------------------------- -// CLA_PROM_CRC32 External References & Function Declarations: -// -extern volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h deleted file mode 100644 index 29c5717..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h +++ /dev/null @@ -1,299 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cmpss.h -// -// TITLE: CMPSS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CMPSS_H__ -#define __F28004X_CMPSS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CMPSS Individual Register Bit Definitions: - -struct COMPCTL_BITS { // bits description - Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select - Uint16 COMPHINV:1; // 1 High Comparator Invert Select - Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select - Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select - Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable - Uint16 rsvd1:1; // 7 Reserved - Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select - Uint16 COMPLINV:1; // 9 Low Comparator Invert Select - Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select - Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select - Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable - Uint16 COMPDACE:1; // 15 Comparator/DAC Enable -}; - -union COMPCTL_REG { - Uint16 all; - struct COMPCTL_BITS bit; -}; - -struct COMPHYSCTL_BITS { // bits description - Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union COMPHYSCTL_REG { - Uint16 all; - struct COMPHYSCTL_BITS bit; -}; - -struct COMPSTS_BITS { // bits description - Uint16 COMPHSTS:1; // 0 High Comparator Status - Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 COMPLSTS:1; // 8 Low Comparator Status - Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status - Uint16 rsvd2:6; // 15:10 Reserved -}; - -union COMPSTS_REG { - Uint16 all; - struct COMPSTS_BITS bit; -}; - -struct COMPSTSCLR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear - Uint16 HSYNCCLREN:1; // 2 High Comparator EPWMSYNCO Clear Enable - Uint16 rsvd2:6; // 8:3 Reserved - Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear - Uint16 LSYNCCLREN:1; // 10 Low Comparator EPWMSYNCO Clear Enable - Uint16 rsvd3:5; // 15:11 Reserved -}; - -union COMPSTSCLR_REG { - Uint16 all; - struct COMPSTSCLR_BITS bit; -}; - -struct COMPDACCTL_BITS { // bits description - Uint16 DACSOURCE:1; // 0 DAC Source Control - Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control - Uint16 SELREF:1; // 5 DAC Reference Select - Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select - Uint16 SWLOADSEL:1; // 7 Software Load Select - Uint16 BLANKSOURCE:4; // 11:8 EPWMBLANK Source Select - Uint16 BLANKEN:1; // 12 EPWMBLANK Enable - Uint16 rsvd1:1; // 13 Reserved - Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits -}; - -union COMPDACCTL_REG { - Uint16 all; - struct COMPDACCTL_BITS bit; -}; - -struct DACHVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALS_REG { - Uint16 all; - struct DACHVALS_BITS bit; -}; - -struct DACHVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALA_REG { - Uint16 all; - struct DACHVALA_BITS bit; -}; - -struct DACLVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALS_REG { - Uint16 all; - struct DACLVALS_BITS bit; -}; - -struct DACLVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALA_REG { - Uint16 all; - struct DACLVALA_BITS bit; -}; - -struct RAMPDLYA_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYA_REG { - Uint16 all; - struct RAMPDLYA_BITS bit; -}; - -struct RAMPDLYS_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYS_REG { - Uint16 all; - struct RAMPDLYS_BITS bit; -}; - -struct CTRIPLFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPLFILCTL_REG { - Uint16 all; - struct CTRIPLFILCTL_BITS bit; -}; - -struct CTRIPLFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPLFILCLKCTL_REG { - Uint16 all; - struct CTRIPLFILCLKCTL_BITS bit; -}; - -struct CTRIPHFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPHFILCTL_REG { - Uint16 all; - struct CTRIPHFILCTL_BITS bit; -}; - -struct CTRIPHFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPHFILCLKCTL_REG { - Uint16 all; - struct CTRIPHFILCLKCTL_BITS bit; -}; - -struct COMPLOCK_BITS { // bits description - Uint16 COMPCTL:1; // 0 COMPCTL Lock - Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock - Uint16 DACCTL:1; // 2 DACCTL Lock - Uint16 CTRIP:1; // 3 CTRIP Lock - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union COMPLOCK_REG { - Uint16 all; - struct COMPLOCK_BITS bit; -}; - -struct CMPSS_REGS { - union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register - union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register - union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register - union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register - union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register - Uint16 rsvd1; // Reserved - union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register - union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register - Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register - Uint16 rsvd2; // Reserved - Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register - Uint16 rsvd3; // Reserved - Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register - Uint16 rsvd4; // Reserved - Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register - Uint16 rsvd5; // Reserved - Uint16 RAMPSTS; // CMPSS Ramp Status Register - Uint16 rsvd6; // Reserved - union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register - union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register - union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register - union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register - union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register - union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register - union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register - union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register - union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register - Uint16 rsvd7[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CMPSS External References & Function Declarations: -// -extern volatile struct CMPSS_REGS Cmpss1Regs; -extern volatile struct CMPSS_REGS Cmpss2Regs; -extern volatile struct CMPSS_REGS Cmpss3Regs; -extern volatile struct CMPSS_REGS Cmpss4Regs; -extern volatile struct CMPSS_REGS Cmpss5Regs; -extern volatile struct CMPSS_REGS Cmpss6Regs; -extern volatile struct CMPSS_REGS Cmpss7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h deleted file mode 100644 index 378c166..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h +++ /dev/null @@ -1,134 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimer.h -// -// TITLE: CPUTIMER Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CPUTIMER_H__ -#define __F28004X_CPUTIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CPUTIMER Individual Register Bit Definitions: - -struct TIM_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers - Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High -}; - -union TIM_REG { - Uint32 all; - struct TIM_BITS bit; -}; - -struct PRD_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Period Registers - Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High -}; - -union PRD_REG { - Uint32 all; - struct PRD_BITS bit; -}; - -struct TCR_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 TSS:1; // 4 CPU-Timer stop status bit. - Uint16 TRB:1; // 5 Timer reload - Uint16 rsvd2:4; // 9:6 Reserved - Uint16 SOFT:1; // 10 Emulation modes - Uint16 FREE:1; // 11 Emulation modes - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. - Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. -}; - -union TCR_REG { - Uint16 all; - struct TCR_BITS bit; -}; - -struct TPR_BITS { // bits description - Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPR_REG { - Uint16 all; - struct TPR_BITS bit; -}; - -struct TPRH_BITS { // bits description - Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPRH_REG { - Uint16 all; - struct TPRH_BITS bit; -}; - -struct CPUTIMER_REGS { - union TIM_REG TIM; // CPU-Timer, Counter Register - union PRD_REG PRD; // CPU-Timer, Period Register - union TCR_REG TCR; // CPU-Timer, Control Register - Uint16 rsvd1; // Reserved - union TPR_REG TPR; // CPU-Timer, Prescale Register - union TPRH_REG TPRH; // CPU-Timer, Prescale Register High -}; - -//--------------------------------------------------------------------------- -// CPUTIMER External References & Function Declarations: -// -extern volatile struct CPUTIMER_REGS CpuTimer0Regs; -extern volatile struct CPUTIMER_REGS CpuTimer1Regs; -extern volatile struct CPUTIMER_REGS CpuTimer2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h deleted file mode 100644 index d76444d..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h +++ /dev/null @@ -1,156 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dac.h -// -// TITLE: DAC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DAC_H__ -#define __F28004X_DAC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DAC Individual Register Bit Definitions: - -struct DACREV_BITS { // bits description - Uint16 REV:8; // 7:0 DAC Revision Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union DACREV_REG { - Uint16 all; - struct DACREV_BITS bit; -}; - -struct DACCTL_BITS { // bits description - Uint16 DACREFSEL:1; // 0 DAC Reference Select - Uint16 MODE:1; // 1 DAC Mode Select - Uint16 LOADMODE:1; // 2 DACVALA Load Mode - Uint16 rsvd1:1; // 3 Reserved - Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union DACCTL_REG { - Uint16 all; - struct DACCTL_BITS bit; -}; - -struct DACVALA_BITS { // bits description - Uint16 DACVALA:12; // 11:0 DAC Active Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALA_REG { - Uint16 all; - struct DACVALA_BITS bit; -}; - -struct DACVALS_BITS { // bits description - Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALS_REG { - Uint16 all; - struct DACVALS_BITS bit; -}; - -struct DACOUTEN_BITS { // bits description - Uint16 DACOUTEN:1; // 0 DAC Output Code - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union DACOUTEN_REG { - Uint16 all; - struct DACOUTEN_BITS bit; -}; - -struct DACLOCK_BITS { // bits description - Uint16 DACCTL:1; // 0 DAC Control Register Lock - Uint16 DACVAL:1; // 1 DAC Value Register Lock - Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock - Uint16 rsvd1:9; // 11:3 Reserved - Uint16 KEY:4; // 15:12 DAC Register Lock Key -}; - -union DACLOCK_REG { - Uint16 all; - struct DACLOCK_BITS bit; -}; - -struct DACTRIM_BITS { // bits description - Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim - Uint16 rsvd1:4; // 11:8 Reserved - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union DACTRIM_REG { - Uint16 all; - struct DACTRIM_BITS bit; -}; - -struct DAC_REGS { - union DACREV_REG DACREV; // DAC Revision Register - union DACCTL_REG DACCTL; // DAC Control Register - union DACVALA_REG DACVALA; // DAC Value Register - Active - union DACVALS_REG DACVALS; // DAC Value Register - Shadow - union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register - union DACLOCK_REG DACLOCK; // DAC Lock Register - union DACTRIM_REG DACTRIM; // DAC Trim Register - Uint16 rsvd1; // Reserved -}; - -//--------------------------------------------------------------------------- -// DAC External References & Function Declarations: -// -extern volatile struct DAC_REGS DacaRegs; -extern volatile struct DAC_REGS DacbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h deleted file mode 100644 index e422cf2..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h +++ /dev/null @@ -1,203 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dcc.h -// -// TITLE: DCC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DCC_H__ -#define __F28004X_DCC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCC Individual Register Bit Definitions: - -struct DCCGCTRL_BITS { // bits description - bp_16 DCCENA:4; // 3:0 DCC Enable - bp_16 ERRENA:4; // 7:4 Error Enable - bp_16 SINGLESHOT:4; // 11:8 Single-Shot Enable - bp_16 DONEENA:4; // 15:12 DONE Enable - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCGCTRL_REG { - bp_32 all; - struct DCCGCTRL_BITS bit; -}; - -struct DCCREV_BITS { // bits description - bp_16 MINOR:6; // 5:0 Minor Revision Number - bp_16 CUSTOM:2; // 7:6 Custom Module Number - bp_16 MAJOR:3; // 10:8 Major Revision Number - bp_16 RTL:5; // 15:11 Design Release Number - bp_32 FUNC:12; // 27:16 Functional Release Number - bp_32 rsvd1:2; // 29:28 Reserved - bp_32 SCHEME:2; // 31:30 Defines Scheme for Module -}; - -union DCCREV_REG { - bp_32 all; - struct DCCREV_BITS bit; -}; - -struct DCCCNTSEED0_BITS { // bits description - bp_32 COUNTSEED0:20; // 19:0 Seed Value for Counter 0 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNTSEED0_REG { - bp_32 all; - struct DCCCNTSEED0_BITS bit; -}; - -struct DCCVALIDSEED0_BITS { // bits description - bp_16 VALIDSEED:16; // 15:0 Seed Value for Valid Duration Counter 0 - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCVALIDSEED0_REG { - bp_32 all; - struct DCCVALIDSEED0_BITS bit; -}; - -struct DCCCNTSEED1_BITS { // bits description - bp_32 COUNTSEED1:20; // 19:0 Seed Value for Counter 1 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNTSEED1_REG { - bp_32 all; - struct DCCCNTSEED1_BITS bit; -}; - -struct DCCSTATUS_BITS { // bits description - bp_16 ERR:1; // 0 Error Flag - bp_16 DONE:1; // 1 Single-Shot Done Flag - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCSTATUS_REG { - bp_32 all; - struct DCCSTATUS_BITS bit; -}; - -struct DCCCNT0_BITS { // bits description - bp_32 COUNT0:20; // 19:0 Current Value of Counter 0 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNT0_REG { - bp_32 all; - struct DCCCNT0_BITS bit; -}; - -struct DCCVALID0_BITS { // bits description - bp_16 VALID0:16; // 15:0 Current Value of Valid 0 - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCVALID0_REG { - bp_32 all; - struct DCCVALID0_BITS bit; -}; - -struct DCCCNT1_BITS { // bits description - bp_32 COUNT1:20; // 19:0 Current Value of Counter 1 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNT1_REG { - bp_32 all; - struct DCCCNT1_BITS bit; -}; - -struct DCCCLKSRC1_BITS { // bits description - bp_16 CLKSRC1:4; // 3:0 Clock Source Select for Counter 1 - bp_16 rsvd1:8; // 11:4 Reserved - bp_16 KEY:4; // 15:12 Enables or Disables Clock Source Selection for COUNT1 - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCCLKSRC1_REG { - bp_32 all; - struct DCCCLKSRC1_BITS bit; -}; - -struct DCCCLKSRC0_BITS { // bits description - bp_16 CLKSRC0:4; // 3:0 Clock Source Select for Counter 0 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCCLKSRC0_REG { - bp_32 all; - struct DCCCLKSRC0_BITS bit; -}; - -struct DCC_REGS { - union DCCGCTRL_REG DCCGCTRL; // Global Control Register - union DCCREV_REG DCCREV; // DCC Revision Register - union DCCCNTSEED0_REG DCCCNTSEED0; // Counter 0 seed value - union DCCVALIDSEED0_REG DCCVALIDSEED0; // Valid 0 seed value - union DCCCNTSEED1_REG DCCCNTSEED1; // Counter 1 Seed Value - union DCCSTATUS_REG DCCSTATUS; // DCC Status - union DCCCNT0_REG DCCCNT0; // Counter 0 Value - union DCCVALID0_REG DCCVALID0; // Valid Value 0 - union DCCCNT1_REG DCCCNT1; // Counter 1 Value - union DCCCLKSRC1_REG DCCCLKSRC1; // Clock Source 1 - union DCCCLKSRC0_REG DCCCLKSRC0; // Clock Source 0 -}; - -//--------------------------------------------------------------------------- -// DCC External References & Function Declarations: -// -extern volatile struct DCC_REGS Dcc0Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h deleted file mode 100644 index 87c1033..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h +++ /dev/null @@ -1,658 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dcsm.h -// -// TITLE: DCSM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DCSM_H__ -#define __F28004X_DCSM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCSM Individual Register Bit Definitions: - -struct B0_Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer for zone Flash BANK0 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z1_LINKPOINTER_REG { - Uint32 all; - struct B0_Z1_LINKPOINTER_BITS bit; -}; - -struct Z1_OTPSECLOCK_BITS { // bits description - Uint16 JTAGLOCK:4; // 3:0 Zone1 JTAG Lock. - Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_OTPSECLOCK_REG { - Uint32 all; - struct Z1_OTPSECLOCK_BITS bit; -}; - -struct B0_Z1_LINKPOINTERERR_BITS { // bits description - Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z1_LINKPOINTERERR_REG { - Uint32 all; - struct B0_Z1_LINKPOINTERERR_BITS bit; -}; - -struct Z1_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Passwords Read Status - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z1_CR_REG { - Uint16 all; - struct Z1_CR_BITS bit; -}; - -struct B0_Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK0 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK0 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK0 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK0 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK0 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK0 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK0 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK0 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK0 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK0 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK0 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK0 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK0 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK0 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK0 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK0 -}; - -union B0_Z1_GRABSECTR_REG { - Uint32 all; - struct B0_Z1_GRABSECTR_BITS bit; -}; - -struct Z1_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union Z1_GRABRAMR_REG { - Uint32 all; - struct Z1_GRABRAMR_BITS bit; -}; - -struct B0_Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B0_Z1_EXEONLYSECTR_REG { - Uint32 all; - struct B0_Z1_EXEONLYSECTR_BITS bit; -}; - -struct Z1_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_EXEONLYRAMR_REG { - Uint32 all; - struct Z1_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_BANK0_Z1_REGS { - union B0_Z1_LINKPOINTER_REG B0_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK0 - union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock - Uint32 Z1_BOOTDEF_HIGH; // Boot definition (high 32bit) - union B0_Z1_LINKPOINTERERR_REG B0_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK0 - Uint32 Z1_BOOTPIN_CONFIG; // Boot Pin Configuration - Uint32 Z1_GPREG2; // Zone1 General Purpose Register-2 - Uint32 Z1_BOOTDEF_LOW; // Boot definition (low 32bit) - Uint16 rsvd1[2]; // Reserved - Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 - Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 - Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 - Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 - Uint16 rsvd2; // Reserved - union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register - union B0_Z1_GRABSECTR_REG B0_Z1_GRABSECTR; // Zone 1 Grab Flash BANK0 Sectors Register - union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register - union B0_Z1_EXEONLYSECTR_REG B0_Z1_EXEONLYSECTR; // Zone 1 Flash BANK0 Execute_Only Sector Register - union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register - Uint16 rsvd3; // Reserved -}; - -struct B0_Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK0 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z2_LINKPOINTER_REG { - Uint32 all; - struct B0_Z2_LINKPOINTER_BITS bit; -}; - -struct Z2_OTPSECLOCK_BITS { // bits description - Uint16 JTAGLOCK:4; // 3:0 Zone2 JTAG Lock. - Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_OTPSECLOCK_REG { - Uint32 all; - struct Z2_OTPSECLOCK_BITS bit; -}; - -struct B0_Z2_LINKPOINTERERR_BITS { // bits description - Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z2_LINKPOINTERERR_REG { - Uint32 all; - struct B0_Z2_LINKPOINTERERR_BITS bit; -}; - -struct Z2_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Passwords Read Status - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z2_CR_REG { - Uint16 all; - struct Z2_CR_BITS bit; -}; - -struct B0_Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK0 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK0 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK0 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK0 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK0 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK0 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK0 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK0 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK0 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK0 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK0 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK0 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK0 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK0 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK0 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK0 -}; - -union B0_Z2_GRABSECTR_REG { - Uint32 all; - struct B0_Z2_GRABSECTR_BITS bit; -}; - -struct Z2_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union Z2_GRABRAMR_REG { - Uint32 all; - struct Z2_GRABRAMR_BITS bit; -}; - -struct B0_Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B0_Z2_EXEONLYSECTR_REG { - Uint32 all; - struct B0_Z2_EXEONLYSECTR_BITS bit; -}; - -struct Z2_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_EXEONLYRAMR_REG { - Uint32 all; - struct Z2_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_BANK0_Z2_REGS { - union B0_Z2_LINKPOINTER_REG B0_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK0 - union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock - Uint16 rsvd1[2]; // Reserved - union B0_Z2_LINKPOINTERERR_REG B0_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK0 - Uint16 rsvd2[8]; // Reserved - Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 - Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 - Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 - Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 - Uint16 rsvd3; // Reserved - union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register - union B0_Z2_GRABSECTR_REG B0_Z2_GRABSECTR; // Zone 2 Grab Flash BANK0 Sectors Register - union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register - union B0_Z2_EXEONLYSECTR_REG B0_Z2_EXEONLYSECTR; // Zone 2 Flash BANK0 Execute_Only Sector Register - union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register - Uint16 rsvd4; // Reserved -}; - -struct FLSEM_BITS { // bits description - Uint16 SEM:2; // 1:0 Flash Semaphore Bit - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Semaphore Key - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FLSEM_REG { - Uint32 all; - struct FLSEM_BITS bit; -}; - -struct B0_SECTSTAT_BITS { // bits description - Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK0 Sector 0 - Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK0 sector 1 - Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK0 Sector 2 - Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK0 Sector 3 - Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK0 Sector 4 - Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK0 Sector 5 - Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK0 Sector 6 - Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK0 Sector 7 - Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK0 sector 8 - Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK0 Sector 9 - Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK0 Sector 10 - Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK0 Sector 11 - Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK0 Sector 12 - Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK0 Sector 13 - Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK0 Sector 14 - Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK0 Sector 15 -}; - -union B0_SECTSTAT_REG { - Uint32 all; - struct B0_SECTSTAT_BITS bit; -}; - -struct RAMSTAT_BITS { // bits description - Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 - Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 - Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 - Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 - Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 - Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 - Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM LS6 - Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union RAMSTAT_REG { - Uint32 all; - struct RAMSTAT_BITS bit; -}; - -struct B1_SECTSTAT_BITS { // bits description - Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK1 Sector 0 - Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK1 sector 1 - Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK1 Sector 2 - Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK1 Sector 3 - Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK1 Sector 4 - Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK1 Sector 5 - Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK1 Sector 6 - Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK1 Sector 7 - Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK1 sector 8 - Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK1 Sector 9 - Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK1 Sector 10 - Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK1 Sector 11 - Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK1 Sector 12 - Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK1 Sector 13 - Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK1 Sector 14 - Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK1 Sector 15 -}; - -union B1_SECTSTAT_REG { - Uint32 all; - struct B1_SECTSTAT_BITS bit; -}; - -struct SECERRSTAT_BITS { // bits description - Uint16 ERR:1; // 0 Security Configuration load Error Status - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRSTAT_REG { - Uint32 all; - struct SECERRSTAT_BITS bit; -}; - -struct SECERRCLR_BITS { // bits description - Uint16 ERR:1; // 0 Clear Security Configuration Load Error Status Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRCLR_REG { - Uint32 all; - struct SECERRCLR_BITS bit; -}; - -struct SECERRFRC_BITS { // bits description - Uint16 ERR:1; // 0 Set Security Configuration Load Error Status Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRFRC_REG { - Uint32 all; - struct SECERRFRC_BITS bit; -}; - -struct DCSM_COMMON_REGS { - union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register - union B0_SECTSTAT_REG B0_SECTSTAT; // Flash BANK0 Sectors Status Register - union RAMSTAT_REG RAMSTAT; // RAM Status Register - Uint16 rsvd1[2]; // Reserved - union B1_SECTSTAT_REG B1_SECTSTAT; // Flash BANK1 Sectors Status Register - union SECERRSTAT_REG SECERRSTAT; // Security Error Status Register - union SECERRCLR_REG SECERRCLR; // Security Error Clear Register - union SECERRFRC_REG SECERRFRC; // Security Error Force Register -}; - -struct B1_Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer in Flash BANK1 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z1_LINKPOINTER_REG { - Uint32 all; - struct B1_Z1_LINKPOINTER_BITS bit; -}; - -struct B1_Z1_LINKPOINTERERR_BITS { // bits description - Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z1_LINKPOINTERERR_REG { - Uint32 all; - struct B1_Z1_LINKPOINTERERR_BITS bit; -}; - -struct B1_Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK1 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK1 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK1 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK1 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK1 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK1 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK1 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK1 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK1 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK1 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK1 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK1 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK1 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK1 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK1 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK1 -}; - -union B1_Z1_GRABSECTR_REG { - Uint32 all; - struct B1_Z1_GRABSECTR_BITS bit; -}; - -struct B1_Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B1_Z1_EXEONLYSECTR_REG { - Uint32 all; - struct B1_Z1_EXEONLYSECTR_BITS bit; -}; - -struct DCSM_BANK1_Z1_REGS { - union B1_Z1_LINKPOINTER_REG B1_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK1 - Uint16 rsvd1[4]; // Reserved - union B1_Z1_LINKPOINTERERR_REG B1_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK1 - Uint16 rsvd2[18]; // Reserved - union B1_Z1_GRABSECTR_REG B1_Z1_GRABSECTR; // Zone 1 Grab Flash BANK1 Sectors Register - Uint16 rsvd3[2]; // Reserved - union B1_Z1_EXEONLYSECTR_REG B1_Z1_EXEONLYSECTR; // Zone 1 Flash BANK1 Execute_Only Sector Register - Uint16 rsvd4[3]; // Reserved -}; - -struct B1_Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK1 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z2_LINKPOINTER_REG { - Uint32 all; - struct B1_Z2_LINKPOINTER_BITS bit; -}; - -struct B1_Z2_LINKPOINTERERR_BITS { // bits description - Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z2_LINKPOINTERERR_REG { - Uint32 all; - struct B1_Z2_LINKPOINTERERR_BITS bit; -}; - -struct B1_Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK1 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK1 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK1 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK1 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK1 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK1 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK1 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK1 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK1 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK1 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK1 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK1 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK1 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK1 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK1 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK1 -}; - -union B1_Z2_GRABSECTR_REG { - Uint32 all; - struct B1_Z2_GRABSECTR_BITS bit; -}; - -struct B1_Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B1_Z2_EXEONLYSECTR_REG { - Uint32 all; - struct B1_Z2_EXEONLYSECTR_BITS bit; -}; - -struct DCSM_BANK1_Z2_REGS { - union B1_Z2_LINKPOINTER_REG B1_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK1 - Uint16 rsvd1[4]; // Reserved - union B1_Z2_LINKPOINTERERR_REG B1_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK1 - Uint16 rsvd2[18]; // Reserved - union B1_Z2_GRABSECTR_REG B1_Z2_GRABSECTR; // Zone 2 Grab Flash BANK1 Sectors Register - Uint16 rsvd3[2]; // Reserved - union B1_Z2_EXEONLYSECTR_REG B1_Z2_EXEONLYSECTR; // Zone 2 Flash BANK1 Execute_Only Sector Register - Uint16 rsvd4[3]; // Reserved -}; - -//--------------------------------------------------------------------------- -// DCSM External References & Function Declarations: -// -extern volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; -extern volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; -extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; -extern volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; -extern volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h deleted file mode 100644 index 9548456..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h +++ /dev/null @@ -1,276 +0,0 @@ -//########################################################################### -// -// FILE: F28004x_device.h -// -// TITLE: F28004x Device Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_DEVICE_H -#define F28004X_DEVICE_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Common CPU Definitions: -// -#ifdef __TMS320C28XX_CLA__ -// -// There are only two assembly instructions that can access the MSTF register -// - MMOV32 mem32, MSTF -// - MMOV32 mem32, MSTF -// The CLA C compiler allows 'C' access to this control register through the __cregister -// keyword. In order to access the register's contents, the user must copy it to the -// shadow object defined below -// Note that _MSTF is the only __cregister recognized by the CLA C compiler; IER and IFR -// are not accessible (therefore not recognized), therefore __cregister must be redefined to -// null to prevent a cla C compiler error -// -struct MSTF_SHADOW_BITS { // bits description - unsigned short LVF:1; // 0 Latched Overflow Flag - unsigned short LUF:1; // 1 Latched Underflow Flag - unsigned short NF:1; // 2 Negative Float Flag - unsigned short ZF:1; // 3 Zero Float Flag - unsigned short rsvd1:2; // 5:4 Reserved - unsigned short TF:1; // 6 Test Flag - unsigned short rsvd2:2; // 8:7 Reserved - unsigned short RNDF32:1; // 9 Rounding Mode - unsigned short rsvd3:1; // 10 Reserved - unsigned short MEALLOW:1; // 11 MEALLOW Status - unsigned short RPCL:4; // 15:12 Return PC: Low Portion - unsigned short RPCH:12; // 27:16 Return PC: High Portion - unsigned short rsvd4:4; // 31:28 Reserved -}; -extern __cregister volatile unsigned int MSTF; -#endif //__TMS320C28XX_CLA__ - -#ifndef __TMS320C28XX__ -#define __cregister -#endif //__TMS320C28xx__ - -extern __cregister volatile unsigned int IFR; -extern __cregister volatile unsigned int IER; - -#define EINT __asm(" clrc INTM") -#define DINT __asm(" setc INTM") -#define ERTM __asm(" clrc DBGM") -#define DRTM __asm(" setc DBGM") -#define EALLOW __eallow() -#define EDIS __edis() -#define ESTOP0 __asm(" ESTOP0") - -#define M_INT1 0x0001 -#define M_INT2 0x0002 -#define M_INT3 0x0004 -#define M_INT4 0x0008 -#define M_INT5 0x0010 -#define M_INT6 0x0020 -#define M_INT7 0x0040 -#define M_INT8 0x0080 -#define M_INT9 0x0100 -#define M_INT10 0x0200 -#define M_INT11 0x0400 -#define M_INT12 0x0800 -#define M_INT13 0x1000 -#define M_INT14 0x2000 -#define M_DLOG 0x4000 -#define M_RTOS 0x8000 - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -// -// For Portability, User Is Recommended To Use the C99 Standard integer types -// -#if !defined(__TMS320C28XX_CLA__) -#include -#include -#endif //__TMS320C28XX_CLA__ -#include -#include -#include - -#if defined(__cplusplus) -typedef bool _Bool; -#endif - -// -// C99 defines boolean type to be _Bool, but this doesn't match the format of -// the other standard integer types. bool_t has been defined to fill this gap. -// -typedef _Bool bool_t; - -// -// Used for a bool function return status -// -typedef _Bool status_t; - -#ifndef SUCCESS -#define SUCCESS true -#endif - -#ifndef FAIL -#define FAIL false -#endif - -// -// The following data types are included for compatibility with legacy code, -// they are not recommended for use in new software. Please use the C99 -// types included above -// -#if (!defined(DSP28_DATA_TYPES) && !defined(F28_DATA_TYPES)) -#define DSP28_DATA_TYPES -#define F28_DATA_TYPES - -#ifdef __TMS320C28XX_CLA__ -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else // __TMS320C28XX__ -typedef int int16; -typedef long int32; -typedef long long int64; -typedef unsigned int Uint16; -typedef unsigned long Uint32; -typedef unsigned long long Uint64; -typedef float float32; -typedef long double float64; -#endif //__TMS320C28XX_CLA__ - -#endif //(!defined(DSP28_DATA_TYPES) && !defined(F28_DATA_TYPES)) - -// -// The following data types are for use with byte addressable peripherals. -// See compiler documentation on the byte_peripheral type attribute. -// -#ifndef __TMS320C28XX_CLA__ -typedef unsigned int bp_16 __attribute__((byte_peripheral)); -typedef unsigned long bp_32 __attribute__((byte_peripheral)); -#endif - -// -// Include All Peripheral Header Files: -// -#include "f28004x_adc.h" -#include "f28004x_analogsubsys.h" -#include "f28004x_cla.h" -#include "f28004x_cla_prom_crc32.h" -#include "f28004x_cmpss.h" -#include "f28004x_cputimer.h" -#include "f28004x_dac.h" -#include "f28004x_dcsm.h" -#include "f28004x_dma.h" -#include "f28004x_ecap.h" -#include "f28004x_epwm.h" -#include "f28004x_epwm_xbar.h" -#include "f28004x_eqep.h" -#include "f28004x_erad.h" -#include "f28004x_flash.h" -#include "f28004x_fsi.h" -#include "f28004x_gpio.h" -#include "f28004x_i2c.h" -#include "f28004x_input_xbar.h" -#include "f28004x_memconfig.h" -#include "f28004x_nmiintrupt.h" -#include "f28004x_output_xbar.h" -#include "f28004x_pga.h" -#include "f28004x_piectrl.h" -#include "f28004x_pievect.h" -#include "f28004x_pmbus.h" -#include "f28004x_sci.h" -#include "f28004x_sdfm.h" -#include "f28004x_spi.h" -#include "f28004x_sysctrl.h" -#include "f28004x_xbar.h" -#include "f28004x_xint.h" - -// -// byte_peripheral attribute is only supported on the C28 -// -#ifndef __TMS320C28XX_CLA__ -#include "f28004x_can.h" -#include "f28004x_dcc.h" -#include "f28004x_lin.h" -#endif - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F28004X_DEVICE_H definition - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h deleted file mode 100644 index ffc9ec8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h +++ /dev/null @@ -1,214 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma.h -// -// TITLE: F28004x Device DMA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DMA_H__ -#define __F28004X_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DMA Individual Register Bit Definitions: - -struct MODE_BITS { // bits description - Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable - Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable - Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode - Uint16 ONESHOT:1; // 10 One Shot Mode Bit - Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 DATASIZE:1; // 14 Data Size Mode Bit - Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit -}; - -union MODE_REG { - Uint16 all; - struct MODE_BITS bit; -}; - -struct CONTROL_BITS { // bits description - Uint16 RUN:1; // 0 Run Bit - Uint16 HALT:1; // 1 Halt Bit - Uint16 SOFTRESET:1; // 2 Soft Reset Bit - Uint16 PERINTFRC:1; // 3 Interrupt Force Bit - Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 ERRCLR:1; // 7 Error Clear Bit - Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit - Uint16 SYNCFLG:1; // 9 Sync Flag Bit - Uint16 SYNCERR:1; // 10 Sync Error Flag Bit - Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit - Uint16 BURSTSTS:1; // 12 Burst Status Bit - Uint16 RUNSTS:1; // 13 Run Status Bit - Uint16 OVRFLG:1; // 14 Overflow Flag Bit - Uint16 rsvd1:1; // 15 Reserved -}; - -union CONTROL_REG { - Uint16 all; - struct CONTROL_BITS bit; -}; - -struct DMACTRL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset Bit - Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union DMACTRL_REG { - Uint16 all; - struct DMACTRL_BITS bit; -}; - -struct DEBUGCTRL_BITS { // bits description - Uint16 rsvd1:15; // 14:0 Reserved - Uint16 FREE:1; // 15 Debug Mode Bit -}; - -union DEBUGCTRL_REG { - Uint16 all; - struct DEBUGCTRL_BITS bit; -}; - -struct PRIORITYCTRL1_BITS { // bits description - Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union PRIORITYCTRL1_REG { - Uint16 all; - struct PRIORITYCTRL1_BITS bit; -}; - -struct PRIORITYSTAT_BITS { // bits description - Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits - Uint16 rsvd1:1; // 3 Reserved - Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union PRIORITYSTAT_REG { - Uint16 all; - struct PRIORITYSTAT_BITS bit; -}; - -struct BURST_SIZE_BITS { // bits description - Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_SIZE_REG { - Uint16 all; - struct BURST_SIZE_BITS bit; -}; - -struct BURST_COUNT_BITS { // bits description - Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_COUNT_REG { - Uint16 all; - struct BURST_COUNT_BITS bit; -}; - -struct CH_REGS { - union MODE_REG MODE; // Mode Register - union CONTROL_REG CONTROL; // Control Register - union BURST_SIZE_REG BURST_SIZE; // Burst Size Register - union BURST_COUNT_REG BURST_COUNT; // Burst Count Register - int16 SRC_BURST_STEP; // Source Burst Step Register - int16 DST_BURST_STEP; // Destination Burst Step Register - Uint16 TRANSFER_SIZE; // Transfer Size Register - Uint16 TRANSFER_COUNT; // Transfer Count Register - int16 SRC_TRANSFER_STEP; // Source Transfer Step Register - int16 DST_TRANSFER_STEP; // Destination Transfer Step Register - Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register - Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register - int16 SRC_WRAP_STEP; // Source Wrap Step Register - Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register - Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register - int16 DST_WRAP_STEP; // Destination Wrap Step Register - Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register - Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register - Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register - Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register - Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register - Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register - Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register - Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register -}; - -struct DMA_REGS { - union DMACTRL_REG DMACTRL; // DMA Control Register - union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register - Uint16 rsvd0; // Reserved - Uint16 rsvd1; // Reserved - union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register - Uint16 rsvd2; // Reserved - union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register - Uint16 rsvd3[25]; // Reserved - struct CH_REGS CH1; // DMA Channel 1 Registers - struct CH_REGS CH2; // DMA Channel 2 Registers - struct CH_REGS CH3; // DMA Channel 3 Registers - struct CH_REGS CH4; // DMA Channel 4 Registers - struct CH_REGS CH5; // DMA Channel 5 Registers - struct CH_REGS CH6; // DMA Channel 6 Registers -}; - -//--------------------------------------------------------------------------- -// DMA External References & Function Declarations: -// -extern volatile struct DMA_REGS DmaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h deleted file mode 100644 index a6e3605..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h +++ /dev/null @@ -1,309 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_ecap.h -// -// TITLE: ECAP Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ECAP_H__ -#define __F28004X_ECAP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ECAP Individual Register Bit Definitions: - -struct ECCTL0_BITS { // bits description - Uint16 INPUTSEL:7; // 6:0 INPUT source select - Uint16 rsvd1:9; // 15:7 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECCTL0_REG { - Uint32 all; - struct ECCTL0_BITS bit; -}; - -struct ECCTL1_BITS { // bits description - Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select - Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 - Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select - Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 - Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select - Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 - Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select - Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 - Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event - Uint16 PRESCALE:5; // 13:9 Event Filter prescale select - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union ECCTL1_REG { - Uint16 all; - struct ECCTL1_BITS bit; -}; - -struct ECCTL2_BITS { // bits description - Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot - Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous - Uint16 REARM:1; // 3 One-shot re-arm - Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop - Uint16 SYNCI_EN:1; // 5 Counter sync-in select - Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode - Uint16 SWSYNC:1; // 8 SW forced counter sync - Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select - Uint16 APWMPOL:1; // 10 APWM output polarity select - Uint16 CTRFILTRESET:1; // 11 Reset event filter, modulus counter, and interrupt flags. - Uint16 DMAEVTSEL:2; // 13:12 DMA event select - Uint16 MODCNTRSTS:2; // 15:14 modulo counter status -}; - -union ECCTL2_REG { - Uint16 all; - struct ECCTL2_BITS bit; -}; - -struct ECEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable - Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable - Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:7; // 15:9 Reserved -}; - -union ECEINT_REG { - Uint16 all; - struct ECEINT_BITS bit; -}; - -struct ECFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Flag - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag - Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag - Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union ECFLG_REG { - Uint16 all; - struct ECFLG_BITS bit; -}; - -struct ECCLR_BITS { // bits description - Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear - Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear - Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear - Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear - Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear - Uint16 CTROVF:1; // 5 Counter Overflow Status Clear - Uint16 CTR_PRD:1; // 6 Period Equal Status Clear - Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union ECCLR_REG { - Uint16 all; - struct ECCLR_BITS bit; -}; - -struct ECFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt - Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt - Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt - Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt - Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt - Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt - Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:7; // 15:9 Reserved -}; - -union ECFRC_REG { - Uint16 all; - struct ECFRC_BITS bit; -}; - -struct ECAPSYNCINSEL_BITS { // bits description - Uint16 SEL:5; // 4:0 SYNCIN source select - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAPSYNCINSEL_REG { - Uint32 all; - struct ECAPSYNCINSEL_BITS bit; -}; - -struct ECAP_REGS { - Uint32 TSCTR; // Time-Stamp Counter - Uint32 CTRPHS; // Counter Phase Offset Value Register - Uint32 CAP1; // Capture 1 Register - Uint32 CAP2; // Capture 2 Register - Uint32 CAP3; // Capture 3 Register - Uint32 CAP4; // Capture 4 Register - Uint16 rsvd1[6]; // Reserved - union ECCTL0_REG ECCTL0; // Capture Control Register 0 - union ECCTL1_REG ECCTL1; // Capture Control Register 1 - union ECCTL2_REG ECCTL2; // Capture Control Register 2 - union ECEINT_REG ECEINT; // Capture Interrupt Enable Register - union ECFLG_REG ECFLG; // Capture Interrupt Flag Register - union ECCLR_REG ECCLR; // Capture Interrupt Clear Register - union ECFRC_REG ECFRC; // Capture Interrupt Force Register - Uint16 rsvd2[4]; // Reserved - union ECAPSYNCINSEL_REG ECAPSYNCINSEL; // SYNC source select register -}; - -struct HRCTL_BITS { // bits description - Uint16 HRE:1; // 0 High Resolution Enable - Uint16 HRCLKE:1; // 1 High Resolution Clock Enable - Uint16 PRDSEL:1; // 2 Calibration Period Match - Uint16 CALIBSTART:1; // 3 Calibration start - Uint16 CALIBSTS:1; // 4 Calibration status - Uint16 CALIBCONT:1; // 5 Continuous mode Calibration Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRCTL_REG { - Uint32 all; - struct HRCTL_BITS bit; -}; - -struct HRINTEN_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CALIBDONE:1; // 1 Calibration doe interrupt enable - Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status enable - Uint16 rsvd2:13; // 15:3 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union HRINTEN_REG { - Uint32 all; - struct HRINTEN_BITS bit; -}; - -struct HRFLG_BITS { // bits description - Uint16 CALIBINT:1; // 0 Global calibration Interrupt Status Flag - Uint16 CALIBDONE:1; // 1 Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status Flag Bi - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRFLG_REG { - Uint32 all; - struct HRFLG_BITS bit; -}; - -struct HRCLR_BITS { // bits description - Uint16 CALIBINT:1; // 0 Clear Global calibration Interrupt Flag - Uint16 CALIBDONE:1; // 1 Clear Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Clear Calibration period check status Flag Bit: - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRCLR_REG { - Uint32 all; - struct HRCLR_BITS bit; -}; - -struct HRFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CALIBDONE:1; // 1 Force Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Force Calibration period check status Flag Bit: - Uint16 rsvd2:13; // 15:3 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union HRFRC_REG { - Uint32 all; - struct HRFRC_BITS bit; -}; - -struct HRCAP_REGS { - union HRCTL_REG HRCTL; // High-Res Control Register - Uint16 rsvd1[2]; // Reserved - union HRINTEN_REG HRINTEN; // High-Res Calibration Interrupt Enable Register - union HRFLG_REG HRFLG; // High-Res Calibration Interrupt Flag Register - union HRCLR_REG HRCLR; // High-Res Calibration Interrupt Clear Register - union HRFRC_REG HRFRC; // High-Res Calibration Interrupt Force Register - Uint32 HRCALPRD; // High-Res Calibration Period Register - Uint32 HRSYSCLKCTR; // High-Res Calibration SYSCLK Counter Register - Uint32 HRSYSCLKCAP; // High-Res Calibration SYSCLK Capture Register - Uint32 HRCLKCTR; // High-Res Calibration HRCLK Counter Register - Uint32 HRCLKCAP; // High-Res Calibration HRCLK Capture Register - Uint16 rsvd2[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ECAP External References & Function Declarations: -// -extern volatile struct ECAP_REGS ECap1Regs; -extern volatile struct ECAP_REGS ECap2Regs; -extern volatile struct ECAP_REGS ECap3Regs; -extern volatile struct ECAP_REGS ECap4Regs; -extern volatile struct ECAP_REGS ECap5Regs; -extern volatile struct ECAP_REGS ECap6Regs; -extern volatile struct ECAP_REGS ECap7Regs; -extern volatile struct HRCAP_REGS HRCap6Regs; -extern volatile struct HRCAP_REGS HRCap7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h deleted file mode 100644 index e7219dc..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h +++ /dev/null @@ -1,1237 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm.h -// -// TITLE: EPWM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EPWM_H__ -#define __F28004X_EPWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM Individual Register Bit Definitions: - -struct TBCTL_BITS { // bits description - Uint16 CTRMODE:2; // 1:0 Counter Mode - Uint16 PHSEN:1; // 2 Phase Load Enable - Uint16 PRDLD:1; // 3 Active Period Load - Uint16 SYNCOSEL:2; // 5:4 Sync Output Select - Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse - Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler - Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler - Uint16 PHSDIR:1; // 13 Phase Direction Bit - Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits -}; - -union TBCTL_REG { - Uint16 all; - struct TBCTL_BITS bit; -}; - -struct TBCTL2_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode - Uint16 OSHTSYNC:1; // 7 One shot sync - Uint16 rsvd3:4; // 11:8 Reserved - Uint16 SYNCOSELX:2; // 13:12 Syncout selection - Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event -}; - -union TBCTL2_REG { - Uint16 all; - struct TBCTL2_BITS bit; -}; - -struct TBSTS_BITS { // bits description - Uint16 CTRDIR:1; // 0 Counter Direction Status - Uint16 SYNCI:1; // 1 External Input Sync Status - Uint16 CTRMAX:1; // 2 Counter Max Latched Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union TBSTS_REG { - Uint16 all; - struct TBSTS_BITS bit; -}; - -struct CMPCTL_BITS { // bits description - Uint16 LOADAMODE:2; // 1:0 Active Compare A Load - Uint16 LOADBMODE:2; // 3:2 Active Compare B Load - Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status - Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status - Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC - Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL_REG { - Uint16 all; - struct CMPCTL_BITS bit; -}; - -struct CMPCTL2_BITS { // bits description - Uint16 LOADCMODE:2; // 1:0 Active Compare C Load - Uint16 LOADDMODE:2; // 3:2 Active Compare D load - Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode - Uint16 rsvd2:3; // 9:7 Reserved - Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC - Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL2_REG { - Uint16 all; - struct CMPCTL2_BITS bit; -}; - -struct DBCTL_BITS { // bits description - Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control - Uint16 POLSEL:2; // 3:2 Polarity Select Control - Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control - Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode - Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode - Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode - Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode - Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control - Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control - Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable -}; - -union DBCTL_REG { - Uint16 all; - struct DBCTL_BITS bit; -}; - -struct DBCTL2_BITS { // bits description - Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select - Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union DBCTL2_REG { - Uint16 all; - struct DBCTL2_BITS bit; -}; - -struct AQCTL_BITS { // bits description - Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select - Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select - Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC - Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC - Uint16 rsvd3:4; // 15:12 Reserved -}; - -union AQCTL_REG { - Uint16 all; - struct AQCTL_BITS bit; -}; - -struct AQTSRCSEL_BITS { // bits description - Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits - Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQTSRCSEL_REG { - Uint16 all; - struct AQTSRCSEL_BITS bit; -}; - -struct PCCTL_BITS { // bits description - Uint16 CHPEN:1; // 0 PWM chopping enable - Uint16 OSHTWTH:4; // 4:1 One-shot pulse width - Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency - Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union PCCTL_REG { - Uint16 all; - struct PCCTL_BITS bit; -}; - -struct VCAPCTL_BITS { // bits description - Uint16 VCAPE:1; // 0 Valley Capture mode - Uint16 VCAPSTART:1; // 1 Valley Capture Start - Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable - Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union VCAPCTL_REG { - Uint16 all; - struct VCAPCTL_BITS bit; -}; - -struct VCNTCFG_BITS { // bits description - Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection - Uint16 rsvd1:3; // 6:4 Reserved - Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit - Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit -}; - -union VCNTCFG_REG { - Uint16 all; - struct VCNTCFG_BITS bit; -}; - -struct HRCNFG_BITS { // bits description - Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits - Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits - Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits - Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit - Uint16 AUTOCONV:1; // 6 Autoconversion Bit - Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit - Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits - Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits - Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits - Uint16 rsvd1:1; // 13 Reserved - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union HRCNFG_REG { - Uint16 all; - struct HRCNFG_BITS bit; -}; - -struct HRPWR_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:4; // 9:6 Reserved - Uint16 rsvd7:5; // 14:10 Reserved - Uint16 CALPWRON:1; // 15 Calibration Power On -}; - -union HRPWR_REG { - Uint16 all; - struct HRPWR_BITS bit; -}; - -struct HRMSTEP_BITS { // bits description - Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union HRMSTEP_REG { - Uint16 all; - struct HRMSTEP_BITS bit; -}; - -struct HRCNFG2_BITS { // bits description - Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits - Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits - Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits - Uint16 rsvd1:8; // 13:6 Reserved - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union HRCNFG2_REG { - Uint16 all; - struct HRCNFG2_BITS bit; -}; - -struct HRPCTL_BITS { // bits description - Uint16 HRPE:1; // 0 High Resolution Period Enable - Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select - Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union HRPCTL_REG { - Uint16 all; - struct HRPCTL_BITS bit; -}; - -struct TRREM_BITS { // bits description - Uint16 TRREM:11; // 10:0 Translator Remainder Bits - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union TRREM_REG { - Uint16 all; - struct TRREM_BITS bit; -}; - -struct GLDCTL_BITS { // bits description - Uint16 GLD:1; // 0 Global Shadow to Active load event control - Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection - Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register - Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union GLDCTL_REG { - Uint16 all; - struct GLDCTL_BITS bit; -}; - -struct GLDCFG_BITS { // bits description - Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR - Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR - Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR - Uint16 CMPC:1; // 3 Global load event configuration for CMPC - Uint16 CMPD:1; // 4 Global load event configuration for CMPD - Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR - Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR - Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL - Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 - Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 - Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union GLDCFG_REG { - Uint16 all; - struct GLDCFG_BITS bit; -}; - -struct EPWMXLINK_BITS { // bits description - Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link - Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link - Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link - Uint16 CMPCLINK:4; // 15:12 CMPC Link - Uint16 CMPDLINK:4; // 19:16 CMPD Link - Uint16 rsvd1:8; // 27:20 Reserved - Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link -}; - -union EPWMXLINK_REG { - Uint32 all; - struct EPWMXLINK_BITS bit; -}; - -struct EPWMREV_BITS { // bits description - Uint16 REV:8; // 7:0 EPWM Silicon Revision bits - Uint16 TYPE:8; // 15:8 EPWM Type Bits -}; - -union EPWMREV_REG { - Uint16 all; - struct EPWMREV_BITS bit; -}; - -struct AQCTLA_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLA_REG { - Uint16 all; - struct AQCTLA_BITS bit; -}; - -struct AQCTLA2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLA2_REG { - Uint16 all; - struct AQCTLA2_BITS bit; -}; - -struct AQCTLB_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLB_REG { - Uint16 all; - struct AQCTLB_BITS bit; -}; - -struct AQCTLB2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLB2_REG { - Uint16 all; - struct AQCTLB2_BITS bit; -}; - -struct AQSFRC_BITS { // bits description - Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked - Uint16 OTSFA:1; // 2 One-time SW Force A Output - Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked - Uint16 OTSFB:1; // 5 One-time SW Force A Output - Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQSFRC_REG { - Uint16 all; - struct AQSFRC_BITS bit; -}; - -struct AQCSFRC_BITS { // bits description - Uint16 CSFA:2; // 1:0 Continuous Software Force on output A - Uint16 CSFB:2; // 3:2 Continuous Software Force on output B - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union AQCSFRC_REG { - Uint16 all; - struct AQCSFRC_BITS bit; -}; - -struct DBREDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits -}; - -union DBREDHR_REG { - Uint16 all; - struct DBREDHR_BITS bit; -}; - -struct DBRED_BITS { // bits description - Uint16 DBRED:14; // 13:0 Rising edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBRED_REG { - Uint16 all; - struct DBRED_BITS bit; -}; - -struct DBFEDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits -}; - -union DBFEDHR_REG { - Uint16 all; - struct DBFEDHR_BITS bit; -}; - -struct DBFED_BITS { // bits description - Uint16 DBFED:14; // 13:0 Falling edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBFED_REG { - Uint16 all; - struct DBFED_BITS bit; -}; - -struct TBPHS_BITS { // bits description - Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) - Uint16 TBPHS:16; // 31:16 Phase Offset Register -}; - -union TBPHS_REG { - Uint32 all; - struct TBPHS_BITS bit; -}; - -struct CMPA_BITS { // bits description - Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register - Uint16 CMPA:16; // 31:16 Compare A Register -}; - -union CMPA_REG { - Uint32 all; - struct CMPA_BITS bit; -}; - -struct CMPB_BITS { // bits description - Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits - Uint16 CMPB:16; // 31:16 Compare B Register -}; - -union CMPB_REG { - Uint32 all; - struct CMPB_BITS bit; -}; - -struct GLDCTL2_BITS { // bits description - Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode - Uint16 GFRCLD:1; // 1 Force reload event in one shot mode - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLDCTL2_REG { - Uint16 all; - struct GLDCTL2_BITS bit; -}; - -struct TZSEL_BITS { // bits description - Uint16 CBC1:1; // 0 TZ1 CBC select - Uint16 CBC2:1; // 1 TZ2 CBC select - Uint16 CBC3:1; // 2 TZ3 CBC select - Uint16 CBC4:1; // 3 TZ4 CBC select - Uint16 CBC5:1; // 4 TZ5 CBC select - Uint16 CBC6:1; // 5 TZ6 CBC select - Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select - Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select - Uint16 OSHT1:1; // 8 One-shot TZ1 select - Uint16 OSHT2:1; // 9 One-shot TZ2 select - Uint16 OSHT3:1; // 10 One-shot TZ3 select - Uint16 OSHT4:1; // 11 One-shot TZ4 select - Uint16 OSHT5:1; // 12 One-shot TZ5 select - Uint16 OSHT6:1; // 13 One-shot TZ6 select - Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select - Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select -}; - -union TZSEL_REG { - Uint16 all; - struct TZSEL_BITS bit; -}; - -struct TZDCSEL_BITS { // bits description - Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 - Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 - Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 - Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZDCSEL_REG { - Uint16 all; - struct TZDCSEL_BITS bit; -}; - -struct TZCTL_BITS { // bits description - Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA - Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB - Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 - Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 - Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 - Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTL_REG { - Uint16 all; - struct TZCTL_BITS bit; -}; - -struct TZCTL2_BITS { // bits description - Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP - Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN - Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP - Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN - Uint16 rsvd1:3; // 14:12 Reserved - Uint16 ETZE:1; // 15 TZCTL2 Enable -}; - -union TZCTL2_REG { - Uint16 all; - struct TZCTL2_BITS bit; -}; - -struct TZCTLDCA_BITS { // bits description - Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCA_REG { - Uint16 all; - struct TZCTLDCA_BITS bit; -}; - -struct TZCTLDCB_BITS { // bits description - Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCB_REG { - Uint16 all; - struct TZCTLDCB_BITS bit; -}; - -struct TZEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable - Uint16 OST:1; // 2 Trip Zones One Shot Int Enable - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZEINT_REG { - Uint16 all; - struct TZEINT_BITS bit; -}; - -struct TZFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Int Status Flag - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag - Uint16 OST:1; // 2 Trip Zones One Shot Flag - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TZFLG_REG { - Uint16 all; - struct TZFLG_BITS bit; -}; - -struct TZCBCFLG_BITS { // bits description - Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch - Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch - Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch - Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch - Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch - Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch - Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 - Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCFLG_REG { - Uint16 all; - struct TZCBCFLG_BITS bit; -}; - -struct TZOSTFLG_BITS { // bits description - Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch - Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch - Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch - Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch - Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch - Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch - Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 - Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTFLG_REG { - Uint16 all; - struct TZOSTFLG_BITS bit; -}; - -struct TZCLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt Clear Flag - Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear - Uint16 OST:1; // 2 One-Shot Flag Clear - Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear - Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear - Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear - Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear - Uint16 rsvd1:7; // 13:7 Reserved - Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch -}; - -union TZCLR_REG { - Uint16 all; - struct TZCLR_BITS bit; -}; - -struct TZCBCCLR_BITS { // bits description - Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch - Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch - Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch - Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch - Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch - Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch - Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC - Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCCLR_REG { - Uint16 all; - struct TZCBCCLR_BITS bit; -}; - -struct TZOSTCLR_BITS { // bits description - Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch - Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch - Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch - Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch - Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch - Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch - Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST - Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTCLR_REG { - Uint16 all; - struct TZOSTCLR_BITS bit; -}; - -struct TZFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event - Uint16 OST:1; // 2 Force Trip Zones One Shot Event - Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 - Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 - Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 - Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZFRC_REG { - Uint16 all; - struct TZFRC_BITS bit; -}; - -struct ETSEL_BITS { // bits description - Uint16 INTSEL:3; // 2:0 EPWMxINTn Select - Uint16 INTEN:1; // 3 EPWMxINTn Enable - Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select - Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select - Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select - Uint16 SOCAEN:1; // 11 Start of Conversion A Enable - Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select - Uint16 SOCBEN:1; // 15 Start of Conversion B Enable -}; - -union ETSEL_REG { - Uint16 all; - struct ETSEL_BITS bit; -}; - -struct ETPS_BITS { // bits description - Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select - Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register - Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits - Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select - Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register - Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select - Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter -}; - -union ETPS_REG { - Uint16 all; - struct ETPS_BITS bit; -}; - -struct ETFLG_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Flag - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Flag - Uint16 SOCB:1; // 3 EPWMxSOCB Flag - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFLG_REG { - Uint16 all; - struct ETFLG_BITS bit; -}; - -struct ETCLR_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Clear - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Clear - Uint16 SOCB:1; // 3 EPWMxSOCB Clear - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETCLR_REG { - Uint16 all; - struct ETCLR_BITS bit; -}; - -struct ETFRC_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Force - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Force - Uint16 SOCB:1; // 3 EPWMxSOCB Force - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFRC_REG { - Uint16 all; - struct ETFRC_BITS bit; -}; - -struct ETINTPS_BITS { // bits description - Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select - Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ETINTPS_REG { - Uint16 all; - struct ETINTPS_BITS bit; -}; - -struct ETSOCPS_BITS { // bits description - Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select - Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register - Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select - Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register -}; - -union ETSOCPS_REG { - Uint16 all; - struct ETSOCPS_BITS bit; -}; - -struct ETCNTINITCTL_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force - Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force - Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force - Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable - Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable - Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable -}; - -union ETCNTINITCTL_REG { - Uint16 all; - struct ETCNTINITCTL_BITS bit; -}; - -struct ETCNTINIT_BITS { // bits description - Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits - Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits - Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ETCNTINIT_REG { - Uint16 all; - struct ETCNTINIT_BITS bit; -}; - -struct DCTRIPSEL_BITS { // bits description - Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select - Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select - Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select - Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select -}; - -union DCTRIPSEL_REG { - Uint16 all; - struct DCTRIPSEL_BITS bit; -}; - -struct DCACTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCACTL_REG { - Uint16 all; - struct DCACTL_BITS bit; -}; - -struct DCBCTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCBCTL_REG { - Uint16 all; - struct DCBCTL_BITS bit; -}; - -struct DCFCTL_BITS { // bits description - Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select - Uint16 BLANKE:1; // 2 Blanking Enable/Disable - Uint16 BLANKINV:1; // 3 Blanking Window Inversion - Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment - Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 EDGEMODE:2; // 9:8 Edge Mode - Uint16 EDGECOUNT:3; // 12:10 Edge Count - Uint16 EDGESTATUS:3; // 15:13 Edge Status -}; - -union DCFCTL_REG { - Uint16 all; - struct DCFCTL_BITS bit; -}; - -struct DCCAPCTL_BITS { // bits description - Uint16 CAPE:1; // 0 Counter Capture Enable - Uint16 SHDWMODE:1; // 1 Counter Capture Mode - Uint16 rsvd1:11; // 12:2 Reserved - Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event - Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag - Uint16 CAPMODE:1; // 15 Counter Capture Mode -}; - -union DCCAPCTL_REG { - Uint16 all; - struct DCCAPCTL_BITS bit; -}; - -struct DCAHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCAHTRIPSEL_REG { - Uint16 all; - struct DCAHTRIPSEL_BITS bit; -}; - -struct DCALTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCALTRIPSEL_REG { - Uint16 all; - struct DCALTRIPSEL_BITS bit; -}; - -struct DCBHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBHTRIPSEL_REG { - Uint16 all; - struct DCBHTRIPSEL_BITS bit; -}; - -struct DCBLTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBLTRIPSEL_REG { - Uint16 all; - struct DCBLTRIPSEL_BITS bit; -}; - -struct EPWMLOCK_BITS { // bits description - Uint16 HRLOCK:1; // 0 HRPWM Register Set Lock - Uint16 GLLOCK:1; // 1 Global Load Register Set Lock - Uint16 TZCFGLOCK:1; // 2 TripZone Register Set Lock - Uint16 TZCLRLOCK:1; // 3 TripZone Clear Register Set Lock - Uint16 DCLOCK:1; // 4 Digital Compare Register Set Lock - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 KEY:16; // 31:16 Key to write to this register -}; - -union EPWMLOCK_REG { - Uint32 all; - struct EPWMLOCK_BITS bit; -}; - -struct EPWM_REGS { - union TBCTL_REG TBCTL; // Time Base Control Register - union TBCTL2_REG TBCTL2; // Time Base Control Register 2 - Uint16 rsvd1[2]; // Reserved - Uint16 TBCTR; // Time Base Counter Register - union TBSTS_REG TBSTS; // Time Base Status Register - Uint16 rsvd2[2]; // Reserved - union CMPCTL_REG CMPCTL; // Counter Compare Control Register - union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 - Uint16 rsvd3[2]; // Reserved - union DBCTL_REG DBCTL; // Dead-Band Generator Control Register - union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 - Uint16 rsvd4[2]; // Reserved - union AQCTL_REG AQCTL; // Action Qualifier Control Register - union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register - Uint16 rsvd5[2]; // Reserved - union PCCTL_REG PCCTL; // PWM Chopper Control Register - Uint16 rsvd6[3]; // Reserved - union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register - union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register - Uint16 rsvd7[6]; // Reserved - union HRCNFG_REG HRCNFG; // HRPWM Configuration Register - union HRPWR_REG HRPWR; // HRPWM Power Register - Uint16 rsvd8[4]; // Reserved - union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register - union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register - Uint16 rsvd9[5]; // Reserved - union HRPCTL_REG HRPCTL; // High Resolution Period Control Register - union TRREM_REG TRREM; // Translator High Resolution Remainder Register - Uint16 rsvd10[5]; // Reserved - union GLDCTL_REG GLDCTL; // Global PWM Load Control Register - union GLDCFG_REG GLDCFG; // Global PWM Load Config Register - Uint16 rsvd11[2]; // Reserved - union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register - Uint16 rsvd12[4]; // Reserved - union EPWMREV_REG EPWMREV; // EPWM Revision Register - Uint16 rsvd13; // Reserved - union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A - union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A - union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B - union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B - Uint16 rsvd14[3]; // Reserved - union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register - Uint16 rsvd15; // Reserved - union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register - Uint16 rsvd16[6]; // Reserved - union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register - union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register - Uint16 rsvd17[12]; // Reserved - union TBPHS_REG TBPHS; // Time Base Phase High - Uint16 TBPRDHR; // Time Base Period High Resolution Register - Uint16 TBPRD; // Time Base Period Register - Uint16 rsvd18[6]; // Reserved - union CMPA_REG CMPA; // Counter Compare A Register - union CMPB_REG CMPB; // Compare B Register - Uint16 rsvd19; // Reserved - Uint16 CMPC; // Counter Compare C Register - Uint16 rsvd20; // Reserved - Uint16 CMPD; // Counter Compare D Register - Uint16 rsvd21[2]; // Reserved - union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 - Uint16 rsvd22[2]; // Reserved - Uint16 SWVDELVAL; // Software Valley Mode Delay Register - Uint16 rsvd23[8]; // Reserved - union TZSEL_REG TZSEL; // Trip Zone Select Register - Uint16 rsvd24; // Reserved - union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register - Uint16 rsvd25; // Reserved - union TZCTL_REG TZCTL; // Trip Zone Control Register - union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register - union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A - union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B - Uint16 rsvd26[5]; // Reserved - union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register - Uint16 rsvd27[5]; // Reserved - union TZFLG_REG TZFLG; // Trip Zone Flag Register - union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register - union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register - Uint16 rsvd28; // Reserved - union TZCLR_REG TZCLR; // Trip Zone Clear Register - union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register - union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register - Uint16 rsvd29; // Reserved - union TZFRC_REG TZFRC; // Trip Zone Force Register - Uint16 rsvd30[8]; // Reserved - union ETSEL_REG ETSEL; // Event Trigger Selection Register - Uint16 rsvd31; // Reserved - union ETPS_REG ETPS; // Event Trigger Pre-Scale Register - Uint16 rsvd32; // Reserved - union ETFLG_REG ETFLG; // Event Trigger Flag Register - Uint16 rsvd33; // Reserved - union ETCLR_REG ETCLR; // Event Trigger Clear Register - Uint16 rsvd34; // Reserved - union ETFRC_REG ETFRC; // Event Trigger Force Register - Uint16 rsvd35; // Reserved - union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register - Uint16 rsvd36; // Reserved - union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register - Uint16 rsvd37; // Reserved - union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register - Uint16 rsvd38; // Reserved - union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register - Uint16 rsvd39[11]; // Reserved - union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register - Uint16 rsvd40[2]; // Reserved - union DCACTL_REG DCACTL; // Digital Compare A Control Register - union DCBCTL_REG DCBCTL; // Digital Compare B Control Register - Uint16 rsvd41[2]; // Reserved - union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register - union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register - Uint16 DCFOFFSET; // Digital Compare Filter Offset Register - Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register - Uint16 DCFWINDOW; // Digital Compare Filter Window Register - Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register - Uint16 rsvd42[2]; // Reserved - Uint16 DCCAP; // Digital Compare Counter Capture Register - Uint16 rsvd43[2]; // Reserved - union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select - union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select - union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select - union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select - Uint16 rsvd44[36]; // Reserved - union EPWMLOCK_REG EPWMLOCK; // EPWM Lock Register - Uint16 rsvd45; // Reserved - Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register - Uint16 VCNTVAL; // Hardware Valley Counter Register - Uint16 rsvd46; // Reserved -}; - -//--------------------------------------------------------------------------- -// EPWM External References & Function Declarations: -// -extern volatile struct EPWM_REGS EPwm1Regs; -extern volatile struct EPWM_REGS EPwm2Regs; -extern volatile struct EPWM_REGS EPwm3Regs; -extern volatile struct EPWM_REGS EPwm4Regs; -extern volatile struct EPWM_REGS EPwm5Regs; -extern volatile struct EPWM_REGS EPwm6Regs; -extern volatile struct EPWM_REGS EPwm7Regs; -extern volatile struct EPWM_REGS EPwm8Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h deleted file mode 100644 index d0ebfd7..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h +++ /dev/null @@ -1,830 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm_xbar.h -// -// TITLE: EPWM_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EPWM_XBAR_H__ -#define __F28004X_EPWM_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM_XBAR Individual Register Bit Definitions: - -struct TRIP4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX0TO15CFG_REG { - Uint32 all; - struct TRIP4MUX0TO15CFG_BITS bit; -}; - -struct TRIP4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX16TO31CFG_REG { - Uint32 all; - struct TRIP4MUX16TO31CFG_BITS bit; -}; - -struct TRIP5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX0TO15CFG_REG { - Uint32 all; - struct TRIP5MUX0TO15CFG_BITS bit; -}; - -struct TRIP5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX16TO31CFG_REG { - Uint32 all; - struct TRIP5MUX16TO31CFG_BITS bit; -}; - -struct TRIP7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX0TO15CFG_REG { - Uint32 all; - struct TRIP7MUX0TO15CFG_BITS bit; -}; - -struct TRIP7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX16TO31CFG_REG { - Uint32 all; - struct TRIP7MUX16TO31CFG_BITS bit; -}; - -struct TRIP8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX0TO15CFG_REG { - Uint32 all; - struct TRIP8MUX0TO15CFG_BITS bit; -}; - -struct TRIP8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX16TO31CFG_REG { - Uint32 all; - struct TRIP8MUX16TO31CFG_BITS bit; -}; - -struct TRIP9MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX0TO15CFG_REG { - Uint32 all; - struct TRIP9MUX0TO15CFG_BITS bit; -}; - -struct TRIP9MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX16TO31CFG_REG { - Uint32 all; - struct TRIP9MUX16TO31CFG_BITS bit; -}; - -struct TRIP10MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX0TO15CFG_REG { - Uint32 all; - struct TRIP10MUX0TO15CFG_BITS bit; -}; - -struct TRIP10MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX16TO31CFG_REG { - Uint32 all; - struct TRIP10MUX16TO31CFG_BITS bit; -}; - -struct TRIP11MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX0TO15CFG_REG { - Uint32 all; - struct TRIP11MUX0TO15CFG_BITS bit; -}; - -struct TRIP11MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX16TO31CFG_REG { - Uint32 all; - struct TRIP11MUX16TO31CFG_BITS bit; -}; - -struct TRIP12MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX0TO15CFG_REG { - Uint32 all; - struct TRIP12MUX0TO15CFG_BITS bit; -}; - -struct TRIP12MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX16TO31CFG_REG { - Uint32 all; - struct TRIP12MUX16TO31CFG_BITS bit; -}; - -struct TRIP4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR -}; - -union TRIP4MUXENABLE_REG { - Uint32 all; - struct TRIP4MUXENABLE_BITS bit; -}; - -struct TRIP5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR -}; - -union TRIP5MUXENABLE_REG { - Uint32 all; - struct TRIP5MUXENABLE_BITS bit; -}; - -struct TRIP7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR -}; - -union TRIP7MUXENABLE_REG { - Uint32 all; - struct TRIP7MUXENABLE_BITS bit; -}; - -struct TRIP8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR -}; - -union TRIP8MUXENABLE_REG { - Uint32 all; - struct TRIP8MUXENABLE_BITS bit; -}; - -struct TRIP9MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR -}; - -union TRIP9MUXENABLE_REG { - Uint32 all; - struct TRIP9MUXENABLE_BITS bit; -}; - -struct TRIP10MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR -}; - -union TRIP10MUXENABLE_REG { - Uint32 all; - struct TRIP10MUXENABLE_BITS bit; -}; - -struct TRIP11MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR -}; - -union TRIP11MUXENABLE_REG { - Uint32 all; - struct TRIP11MUXENABLE_BITS bit; -}; - -struct TRIP12MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR -}; - -union TRIP12MUXENABLE_REG { - Uint32 all; - struct TRIP12MUXENABLE_BITS bit; -}; - -struct TRIPOUTINV_BITS { // bits description - Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR - Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR - Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR - Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR - Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR - Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR - Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR - Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TRIPOUTINV_REG { - Uint32 all; - struct TRIPOUTINV_BITS bit; -}; - -struct TRIPLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write protection KEY -}; - -union TRIPLOCK_REG { - Uint32 all; - struct TRIPLOCK_BITS bit; -}; - -struct EPWM_XBAR_REGS { - union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 - union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 - union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 - union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 - union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 - union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 - union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 - union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 - Uint16 rsvd1[8]; // Reserved - union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register - Uint16 rsvd2[4]; // Reserved - union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// EPWM_XBAR External References & Function Declarations: -// -extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h deleted file mode 100644 index e14b9c8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h +++ /dev/null @@ -1,301 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_eqep.h -// -// TITLE: EQEP Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EQEP_H__ -#define __F28004X_EQEP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EQEP Individual Register Bit Definitions: - -struct QDECCTL_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 QSP:1; // 5 QEPS input polarity - Uint16 QIP:1; // 6 QEPI input polarity - Uint16 QBP:1; // 7 QEPB input polarity - Uint16 QAP:1; // 8 QEPA input polarity - Uint16 IGATE:1; // 9 Index pulse gating option - Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter - Uint16 XCR:1; // 11 External Clock Rate - Uint16 SPSEL:1; // 12 Sync output pin selection - Uint16 SOEN:1; // 13 Sync output-enable - Uint16 QSRC:2; // 15:14 Position-counter source selection -}; - -union QDECCTL_REG { - Uint16 all; - struct QDECCTL_BITS bit; -}; - -struct QEPCTL_BITS { // bits description - Uint16 WDE:1; // 0 QEP watchdog enable - Uint16 UTE:1; // 1 QEP unit timer enable - Uint16 QCLM:1; // 2 QEP capture latch mode - Uint16 QPEN:1; // 3 Quadrature postotion counter enable - Uint16 IEL:2; // 5:4 Index event latch - Uint16 SEL:1; // 6 Strobe event latch - Uint16 SWI:1; // 7 Software init position counter - Uint16 IEI:2; // 9:8 Index event init of position count - Uint16 SEI:2; // 11:10 Strobe event init - Uint16 PCRM:2; // 13:12 Postion counter reset - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union QEPCTL_REG { - Uint16 all; - struct QEPCTL_BITS bit; -}; - -struct QCAPCTL_BITS { // bits description - Uint16 UPPS:4; // 3:0 Unit position event prescaler - Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler - Uint16 rsvd1:8; // 14:7 Reserved - Uint16 CEN:1; // 15 Enable eQEP capture -}; - -union QCAPCTL_REG { - Uint16 all; - struct QCAPCTL_BITS bit; -}; - -struct QPOSCTL_BITS { // bits description - Uint16 PCSPW:12; // 11:0 Position compare sync pulse width - Uint16 PCE:1; // 12 Position compare enable/disable - Uint16 PCPOL:1; // 13 Polarity of sync output - Uint16 PCLOAD:1; // 14 Position compare of shadow load - Uint16 PCSHDW:1; // 15 Position compare of shadow enable -}; - -union QPOSCTL_REG { - Uint16 all; - struct QPOSCTL_BITS bit; -}; - -struct QEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Position counter error interrupt enable - Uint16 QPE:1; // 2 Quadrature phase error interrupt enable - Uint16 QDC:1; // 3 Quadrature direction change interrupt enable - Uint16 WTO:1; // 4 Watchdog time out interrupt enable - Uint16 PCU:1; // 5 Position counter underflow interrupt enable - Uint16 PCO:1; // 6 Position counter overflow interrupt enable - Uint16 PCR:1; // 7 Position-compare ready interrupt enable - Uint16 PCM:1; // 8 Position-compare match interrupt enable - Uint16 SEL:1; // 9 Strobe event latch interrupt enable - Uint16 IEL:1; // 10 Index event latch interrupt enable - Uint16 UTO:1; // 11 Unit time out interrupt enable - Uint16 QMAE:1; // 12 QMA error interrupt enable - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union QEINT_REG { - Uint16 all; - struct QEINT_BITS bit; -}; - -struct QFLG_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt status flag - Uint16 PCE:1; // 1 Position counter error interrupt flag - Uint16 PHE:1; // 2 Quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Position counter underflow interrupt flag - Uint16 PCO:1; // 6 Position counter overflow interrupt flag - Uint16 PCR:1; // 7 Position-compare ready interrupt flag - Uint16 PCM:1; // 8 eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Strobe event latch interrupt flag - Uint16 IEL:1; // 10 Index event latch interrupt flag - Uint16 UTO:1; // 11 Unit time out interrupt flag - Uint16 QMAE:1; // 12 QMA error interrupt flag - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union QFLG_REG { - Uint16 all; - struct QFLG_BITS bit; -}; - -struct QCLR_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt clear flag - Uint16 PCE:1; // 1 Clear position counter error interrupt flag - Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag - Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag - Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag - Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag - Uint16 IEL:1; // 10 Clear index event latch interrupt flag - Uint16 UTO:1; // 11 Clear unit time out interrupt flag - Uint16 QMAE:1; // 12 Clear QMA error interrupt flag - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union QCLR_REG { - Uint16 all; - struct QCLR_BITS bit; -}; - -struct QFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Force position counter error interrupt - Uint16 PHE:1; // 2 Force quadrature phase error interrupt - Uint16 QDC:1; // 3 Force quadrature direction change interrupt - Uint16 WTO:1; // 4 Force watchdog time out interrupt - Uint16 PCU:1; // 5 Force position counter underflow interrupt - Uint16 PCO:1; // 6 Force position counter overflow interrupt - Uint16 PCR:1; // 7 Force position-compare ready interrupt - Uint16 PCM:1; // 8 Force position-compare match interrupt - Uint16 SEL:1; // 9 Force strobe event latch interrupt - Uint16 IEL:1; // 10 Force index event latch interrupt - Uint16 UTO:1; // 11 Force unit time out interrupt - Uint16 QMAE:1; // 12 Force QMA error interrupt - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union QFRC_REG { - Uint16 all; - struct QFRC_BITS bit; -}; - -struct QEPSTS_BITS { // bits description - Uint16 PCEF:1; // 0 Position counter error flag. - Uint16 FIMF:1; // 1 First index marker flag - Uint16 CDEF:1; // 2 Capture direction error flag - Uint16 COEF:1; // 3 Capture overflow error flag - Uint16 QDLF:1; // 4 eQEP direction latch flag - Uint16 QDF:1; // 5 Quadrature direction flag - Uint16 FIDF:1; // 6 The first index marker - Uint16 UPEVNT:1; // 7 Unit position event flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union QEPSTS_REG { - Uint16 all; - struct QEPSTS_BITS bit; -}; - -struct REV_BITS { // bits description - Uint16 MAJOR:3; // 2:0 Major Revision Number - Uint16 MINOR:3; // 5:3 Minor Revision Number - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union REV_REG { - Uint32 all; - struct REV_BITS bit; -}; - -struct QEPSTROBESEL_BITS { // bits description - Uint16 STROBESEL:2; // 1:0 QMA Mode Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union QEPSTROBESEL_REG { - Uint32 all; - struct QEPSTROBESEL_BITS bit; -}; - -struct QMACTRL_BITS { // bits description - Uint16 MODE:3; // 2:0 QMA Mode Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union QMACTRL_REG { - Uint32 all; - struct QMACTRL_BITS bit; -}; - -struct EQEP_REGS { - Uint32 QPOSCNT; // Position Counter - Uint32 QPOSINIT; // Position Counter Init - Uint32 QPOSMAX; // Maximum Position Count - Uint32 QPOSCMP; // Position Compare - Uint32 QPOSILAT; // Index Position Latch - Uint32 QPOSSLAT; // Strobe Position Latch - Uint32 QPOSLAT; // Position Latch - Uint32 QUTMR; // QEP Unit Timer - Uint32 QUPRD; // QEP Unit Period - Uint16 QWDTMR; // QEP Watchdog Timer - Uint16 QWDPRD; // QEP Watchdog Period - union QDECCTL_REG QDECCTL; // Quadrature Decoder Control - union QEPCTL_REG QEPCTL; // QEP Control - union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control - union QPOSCTL_REG QPOSCTL; // Position Compare Control - union QEINT_REG QEINT; // QEP Interrupt Control - union QFLG_REG QFLG; // QEP Interrupt Flag - union QCLR_REG QCLR; // QEP Interrupt Clear - union QFRC_REG QFRC; // QEP Interrupt Force - union QEPSTS_REG QEPSTS; // QEP Status - Uint16 QCTMR; // QEP Capture Timer - Uint16 QCPRD; // QEP Capture Period - Uint16 QCTMRLAT; // QEP Capture Latch - Uint16 QCPRDLAT; // QEP Capture Period Latch - Uint16 rsvd1[15]; // Reserved - union REV_REG REV; // QEP Revision Number - union QEPSTROBESEL_REG QEPSTROBESEL; // QEP Strobe select register - union QMACTRL_REG QMACTRL; // QMA Control register - Uint16 rsvd2[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// EQEP External References & Function Declarations: -// -extern volatile struct EQEP_REGS EQep1Regs; -extern volatile struct EQEP_REGS EQep2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h deleted file mode 100644 index e113533..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h +++ /dev/null @@ -1,306 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_erad.h -// -// TITLE: ERAD Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ERAD_H__ -#define __F28004X_ERAD_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ERAD Individual Register Bit Definitions: - -struct GLBL_EVENT_STAT_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Event Status - Uint16 HWBP2:1; // 1 Bus Comparator Module Event Status - Uint16 HWBP3:1; // 2 Bus Comparator Module Event Status - Uint16 HWBP4:1; // 3 Bus Comparator Module Event Status - Uint16 HWBP5:1; // 4 Bus Comparator Module Event Status - Uint16 HWBP6:1; // 5 Bus Comparator Module Event Status - Uint16 HWBP7:1; // 6 Bus Comparator Module Event Status - Uint16 HWBP8:1; // 7 Bus Comparator Module Event Status - Uint16 CTM1:1; // 8 Counter Module Event Status - Uint16 CTM2:1; // 9 Counter Module Event Status - Uint16 CTM3:1; // 10 Counter Module Event Status - Uint16 CTM4:1; // 11 Counter Module Event Status - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_EVENT_STAT_REG { - Uint16 all; - struct GLBL_EVENT_STAT_BITS bit; -}; - -struct GLBL_HALT_STAT_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Halt Status - Uint16 HWBP2:1; // 1 Bus Comparator Module Halt Status - Uint16 HWBP3:1; // 2 Bus Comparator Module Halt Status - Uint16 HWBP4:1; // 3 Bus Comparator Module Halt Status - Uint16 HWBP5:1; // 4 Bus Comparator Module Halt Status - Uint16 HWBP6:1; // 5 Bus Comparator Module Halt Status - Uint16 HWBP7:1; // 6 Bus Comparator Module Halt Status - Uint16 HWBP8:1; // 7 Bus Comparator Module Halt Status - Uint16 CTM1:1; // 8 Counter Module Halt Status - Uint16 CTM2:1; // 9 Counter Module Halt Status - Uint16 CTM3:1; // 10 Counter Module Halt Status - Uint16 CTM4:1; // 11 Counter Module Halt Status - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_HALT_STAT_REG { - Uint16 all; - struct GLBL_HALT_STAT_BITS bit; -}; - -struct GLBL_ENABLE_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Global Enable - Uint16 HWBP2:1; // 1 Bus Comparator Module Global Enable - Uint16 HWBP3:1; // 2 Bus Comparator Module Global Enable - Uint16 HWBP4:1; // 3 Bus Comparator Module Global Enable - Uint16 HWBP5:1; // 4 Bus Comparator Module Global Enable - Uint16 HWBP6:1; // 5 Bus Comparator Module Global Enable - Uint16 HWBP7:1; // 6 Bus Comparator Module Global Enable - Uint16 HWBP8:1; // 7 Bus Comparator Module Global Enable - Uint16 CTM1:1; // 8 Counter Module Global Enable - Uint16 CTM2:1; // 9 Counter Module Global Enable - Uint16 CTM3:1; // 10 Counter Module Global Enable - Uint16 CTM4:1; // 11 Counter Module Global Enable - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_ENABLE_REG { - Uint16 all; - struct GLBL_ENABLE_BITS bit; -}; - -struct GLBL_CTM_RESET_BITS { // bits description - Uint16 CTM1:1; // 0 Global Reset for the counters - Uint16 CTM2:1; // 1 Global Reset for the counters - Uint16 CTM3:1; // 2 Global Reset for the counters - Uint16 CTM4:1; // 3 Global Reset for the counters - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union GLBL_CTM_RESET_REG { - Uint16 all; - struct GLBL_CTM_RESET_BITS bit; -}; - -struct GLBL_OWNER_BITS { // bits description - Uint16 OWNER:2; // 1:0 Global Ownership Bits - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLBL_OWNER_REG { - Uint16 all; - struct GLBL_OWNER_BITS bit; -}; - -struct ERAD_GLOBAL_REGS { - union GLBL_EVENT_STAT_REG GLBL_EVENT_STAT; // Global Event Status Register - Uint16 rsvd1; // Reserved - union GLBL_HALT_STAT_REG GLBL_HALT_STAT; // Global Halt Status Register - Uint16 rsvd2; // Reserved - union GLBL_ENABLE_REG GLBL_ENABLE; // Global Enable Register - Uint16 rsvd3; // Reserved - union GLBL_CTM_RESET_REG GLBL_CTM_RESET; // Global Counter Reset - Uint16 rsvd4[3]; // Reserved - union GLBL_OWNER_REG GLBL_OWNER; // Global Ownership - Uint16 rsvd5[8]; // Reserved -}; - -struct HWBP_CLEAR_BITS { // bits description - Uint16 EVENT_CLR:1; // 0 Event Clear register - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union HWBP_CLEAR_REG { - Uint16 all; - struct HWBP_CLEAR_BITS bit; -}; - -struct HWBP_CNTL_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 BUS_SEL:3; // 4:2 Bus select bits - Uint16 STOP:1; // 5 Stop bit (Halt/No Halt of CPU) - Uint16 RTOSINT:1; // 6 RTOSINT bit - Uint16 COMP_MODE:3; // 9:7 Compare mode - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union HWBP_CNTL_REG { - Uint16 all; - struct HWBP_CNTL_BITS bit; -}; - -struct HWBP_STATUS_BITS { // bits description - Uint16 EVENT_FIRED:1; // 0 HWBP Event Fired bits - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 MODULE_ID:6; // 13:8 Identification bits - Uint16 STATUS:2; // 15:14 Status bits -}; - -union HWBP_STATUS_REG { - Uint16 all; - struct HWBP_STATUS_BITS bit; -}; - -struct ERAD_HWBP_REGS { - Uint32 HWBP_MASK; // HWBP Mask Register - Uint32 HWBP_REF; // HWBP Reference Register - union HWBP_CLEAR_REG HWBP_CLEAR; // HWBP Clear Register - Uint16 rsvd1; // Reserved - union HWBP_CNTL_REG HWBP_CNTL; // HWBP Control Register - union HWBP_STATUS_REG HWBP_STATUS; // HWBP Status Register -}; - -struct CTM_CNTL_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 START_STOP_MODE:1; // 2 Start_stop mode bit - Uint16 EVENT_MODE:1; // 3 Event mode bit - Uint16 RST_ON_MATCH:1; // 4 Reset_on_match bit - Uint16 rsvd2:1; // 5 Reserved - Uint16 STOP:1; // 6 Stop bit (Halt/No Halt of CPU) - Uint16 RTOSINT:1; // 7 RTOSINT bit - Uint16 START_STOP_CUMULATIVE:1; // 8 Start stop cumulative bit - Uint16 rsvd3:1; // 9 Reserved - Uint16 RST_EN:1; // 10 Enable Reset - Uint16 RST_INP_SEL:5; // 15:11 Reset Input select -}; - -union CTM_CNTL_REG { - Uint16 all; - struct CTM_CNTL_BITS bit; -}; - -struct CTM_STATUS_BITS { // bits description - Uint16 EVENT_FIRED:1; // 0 Counter Event Fired bits - Uint16 OVERFLOW:1; // 1 Counter Overflowed - Uint16 MODULE_ID:10; // 11:2 Identification bits - Uint16 STATUS:4; // 15:12 Status bits -}; - -union CTM_STATUS_REG { - Uint16 all; - struct CTM_STATUS_BITS bit; -}; - -struct CTM_INPUT_SEL_BITS { // bits description - Uint16 CTM_INP_SEL_EN:1; // 0 Count input select enable - Uint16 CNT_INP_SEL:5; // 5:1 Count input select - Uint16 STA_INP_SEL:5; // 10:6 Start input select - Uint16 STO_INP_SEL:5; // 15:11 Stop input select -}; - -union CTM_INPUT_SEL_REG { - Uint16 all; - struct CTM_INPUT_SEL_BITS bit; -}; - -struct CTM_CLEAR_BITS { // bits description - Uint16 EVENT_CLEAR:1; // 0 Clear EVENT_FIRED - Uint16 OVERFLOW_CLEAR:1; // 1 Clear OVERFLOW - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union CTM_CLEAR_REG { - Uint16 all; - struct CTM_CLEAR_BITS bit; -}; - -struct CTM_INPUT_SEL_MSB_BITS { // bits description - Uint16 CTM_INP_SEL_MSB:1; // 0 Count input select - Uint16 rsvd1:3; // 3:1 Reserved - Uint16 STA_INP_SEL_MSB:1; // 4 Start input select - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 STO_INP_SEL_MSB:1; // 8 Stop input select - Uint16 rsvd3:3; // 11:9 Reserved - Uint16 RST_INP_SEL_MSB:1; // 12 Reset Input Select - Uint16 rsvd4:3; // 15:13 Reserved -}; - -union CTM_INPUT_SEL_MSB_REG { - Uint16 all; - struct CTM_INPUT_SEL_MSB_BITS bit; -}; - -struct ERAD_COUNTER_REGS { - union CTM_CNTL_REG CTM_CNTL; // Counter Control Register - union CTM_STATUS_REG CTM_STATUS; // Counter Status Register - Uint32 CTM_REF; // Counter Reference Register - Uint32 CTM_COUNT; // Counter Current Value Register - Uint32 CTM_MAX_COUNT; // Counter Max Count Value Register - union CTM_INPUT_SEL_REG CTM_INPUT_SEL; // Counter Input Select Register - union CTM_CLEAR_REG CTM_CLEAR; // Counter Clear Register - union CTM_INPUT_SEL_MSB_REG CTM_INPUT_SEL_MSB; // Counter Input Select Extension Register - Uint16 rsvd1[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ERAD External References & Function Declarations: -// -extern volatile struct ERAD_GLOBAL_REGS EnhancedDebugGlobalRegs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP1Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP2Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP3Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP4Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP5Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP6Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP7Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP8Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter1Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter2Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter3Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter4Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h deleted file mode 100644 index c91a491..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h +++ /dev/null @@ -1,366 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_flash.h -// -// TITLE: FLASH Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_FLASH_H__ -#define __F28004X_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FLASH Individual Register Bit Definitions: - -struct FRDCNTL_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 RWAIT:4; // 11:8 Random Read Waitstate - Uint16 rsvd2:4; // 15:12 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union FRDCNTL_REG { - Uint32 all; - struct FRDCNTL_BITS bit; -}; - -struct FBAC_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 BAGP:8; // 15:8 Bank Active Grace Period - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBAC_REG { - Uint32 all; - struct FBAC_BITS bit; -}; - -struct FBFALLBACK_BITS { // bits description - Uint16 BNKPWR0:2; // 1:0 Bank Power Mode of BANK0 - Uint16 BNKPWR1:2; // 3:2 Bank Power Mode of BANK1 - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBFALLBACK_REG { - Uint32 all; - struct FBFALLBACK_BITS bit; -}; - -struct FBPRDY_BITS { // bits description - Uint16 BANK0RDY:1; // 0 Flash Bank Active Power State - Uint16 BANK1RDY:1; // 1 Flash Bank Active Power State - Uint16 rsvd1:13; // 14:2 Reserved - Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBPRDY_REG { - Uint32 all; - struct FBPRDY_BITS bit; -}; - -struct FPAC1_BITS { // bits description - Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count - Uint16 rsvd2:4; // 31:28 Reserved -}; - -union FPAC1_REG { - Uint32 all; - struct FPAC1_BITS bit; -}; - -struct FPAC2_BITS { // bits description - Uint16 PAGP:16; // 15:0 Pump Active Grace Period - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union FPAC2_REG { - Uint32 all; - struct FPAC2_BITS bit; -}; - -struct FMSTAT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status - Uint16 CSTAT:1; // 4 Command Fail Status - Uint16 INVDAT:1; // 5 Invalid Data - Uint16 PGM:1; // 6 Program Operation Status - Uint16 ERS:1; // 7 Erase Operation Status - Uint16 BUSY:1; // 8 Busy Bit - Uint16 rsvd4:1; // 9 Reserved - Uint16 EV:1; // 10 Erase Verify Status - Uint16 rsvd5:1; // 11 Reserved - Uint16 PGV:1; // 12 Programming Verify Status - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:1; // 16 Reserved - Uint16 rsvd10:1; // 17 Reserved - Uint16 rsvd11:14; // 31:18 Reserved -}; - -union FMSTAT_REG { - Uint32 all; - struct FMSTAT_BITS bit; -}; - -struct FRD_INTF_CTRL_BITS { // bits description - Uint16 PREFETCH_EN:1; // 0 Prefetch Enable - Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FRD_INTF_CTRL_REG { - Uint32 all; - struct FRD_INTF_CTRL_BITS bit; -}; - -struct FLASH_CTRL_REGS { - union FRDCNTL_REG FRDCNTL; // Flash Read Control Register - Uint16 rsvd1[28]; // Reserved - union FBAC_REG FBAC; // Flash Bank Access Control Register - union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register - union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register - union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 - union FPAC2_REG FPAC2; // Flash Pump Access Control Register 2 - Uint16 rsvd2[2]; // Reserved - union FMSTAT_REG FMSTAT; // Flash Module Status Register - Uint16 rsvd3[340]; // Reserved - union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register -}; - -struct ECC_ENABLE_BITS { // bits description - Uint16 ENABLE:4; // 3:0 Enable ECC - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECC_ENABLE_REG { - Uint32 all; - struct ECC_ENABLE_BITS bit; -}; - -struct ERR_STATUS_BITS { // bits description - Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_REG { - Uint32 all; - struct ERR_STATUS_BITS bit; -}; - -struct ERR_POS_BITS { // bits description - Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits - Uint16 rsvd2:7; // 15:9 Reserved - Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits - Uint16 rsvd4:7; // 31:25 Reserved -}; - -union ERR_POS_REG { - Uint32 all; - struct ERR_POS_BITS bit; -}; - -struct ERR_STATUS_CLR_BITS { // bits description - Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_CLR_REG { - Uint32 all; - struct ERR_STATUS_CLR_BITS bit; -}; - -struct ERR_CNT_BITS { // bits description - Uint16 ERR_CNT:16; // 15:0 Error counter - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_CNT_REG { - Uint32 all; - struct ERR_CNT_BITS bit; -}; - -struct ERR_THRESHOLD_BITS { // bits description - Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_THRESHOLD_REG { - Uint32 all; - struct ERR_THRESHOLD_BITS bit; -}; - -struct ERR_INTFLG_BITS { // bits description - Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag - Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTFLG_REG { - Uint32 all; - struct ERR_INTFLG_BITS bit; -}; - -struct ERR_INTCLR_BITS { // bits description - Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear - Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTCLR_REG { - Uint32 all; - struct ERR_INTCLR_BITS bit; -}; - -struct FADDR_TEST_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ADDRL:13; // 15:3 ECC Address Low - Uint16 ADDRH:6; // 21:16 ECC Address High - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union FADDR_TEST_REG { - Uint32 all; - struct FADDR_TEST_BITS bit; -}; - -struct FECC_TEST_BITS { // bits description - Uint16 ECC:8; // 7:0 ECC Control Bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_TEST_REG { - Uint32 all; - struct FECC_TEST_BITS bit; -}; - -struct FECC_CTRL_BITS { // bits description - Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic - Uint16 ECC_SELECT:1; // 1 ECC Bit Select - Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_CTRL_REG { - Uint32 all; - struct FECC_CTRL_BITS bit; -}; - -struct FECC_STATUS_BITS { // bits description - Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error - Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error - Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error - Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error - Uint16 rsvd1:7; // 15:9 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_STATUS_REG { - Uint32 all; - struct FECC_STATUS_BITS bit; -}; - -struct FLASH_ECC_REGS { - union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable - Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low - Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High - Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low - Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High - union ERR_STATUS_REG ERR_STATUS; // Error Status - union ERR_POS_REG ERR_POS; // Error Position - union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear - union ERR_CNT_REG ERR_CNT; // Error Control - union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold - union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag - union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear - Uint32 FDATAH_TEST; // Data High Test - Uint32 FDATAL_TEST; // Data Low Test - union FADDR_TEST_REG FADDR_TEST; // ECC Test Address - union FECC_TEST_REG FECC_TEST; // ECC Test Address - union FECC_CTRL_REG FECC_CTRL; // ECC Control - Uint32 FOUTH_TEST; // Test Data Out High - Uint32 FOUTL_TEST; // Test Data Out Low - union FECC_STATUS_REG FECC_STATUS; // ECC Status -}; - -//--------------------------------------------------------------------------- -// FLASH External References & Function Declarations: -// -extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; -extern volatile struct FLASH_ECC_REGS Flash0EccRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h deleted file mode 100644 index 3b7a7e9..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h +++ /dev/null @@ -1,660 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_fsi.h -// -// TITLE: FSI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_FSI_H__ -#define __F28004X_FSI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FSI Individual Register Bit Definitions: - -struct TX_MASTER_CTRL_BITS { // bits description - Uint16 CORE_RST:1; // 0 Transmitter Master Core Reset - Uint16 FLUSH:1; // 1 Flush Operation Start - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union TX_MASTER_CTRL_REG { - Uint16 all; - struct TX_MASTER_CTRL_BITS bit; -}; - -struct TX_CLK_CTRL_BITS { // bits description - Uint16 CLK_RST:1; // 0 Soft Reset for the Clock Divider - Uint16 CLK_EN:1; // 1 Clock Divider Enable - Uint16 PRESCALE_VAL:8; // 9:2 Prescale value - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union TX_CLK_CTRL_REG { - Uint16 all; - struct TX_CLK_CTRL_BITS bit; -}; - -struct TX_OPER_CTRL_LO_BITS { // bits description - Uint16 DATA_WIDTH:2; // 1:0 Transmit Data width - Uint16 rsvd1:1; // 2 Reserved - Uint16 START_MODE:3; // 5:3 Transmission Start Mode Select - Uint16 SW_CRC:1; // 6 CRC Source Select - Uint16 PING_TO_MODE:1; // 7 Ping Counter Reset Mode Select - Uint16 SEL_PLLCLK:1; // 8 Input Clock Select - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union TX_OPER_CTRL_LO_REG { - Uint16 all; - struct TX_OPER_CTRL_LO_BITS bit; -}; - -struct TX_OPER_CTRL_HI_BITS { // bits description - Uint16 EXT_TRIG_SEL:5; // 4:0 External Trigger Select - Uint16 FORCE_ERR:1; // 5 Error Frame Force - Uint16 ECC_SEL:1; // 6 ECC Data Width Select - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TX_OPER_CTRL_HI_REG { - Uint16 all; - struct TX_OPER_CTRL_HI_BITS bit; -}; - -struct TX_FRAME_CTRL_BITS { // bits description - Uint16 FRAME_TYPE:4; // 3:0 Transmit Frame Type - Uint16 N_WORDS:4; // 7:4 Number of Words to be Transmitted - Uint16 rsvd1:7; // 14:8 Reserved - Uint16 START:1; // 15 Start Transmission -}; - -union TX_FRAME_CTRL_REG { - Uint16 all; - struct TX_FRAME_CTRL_BITS bit; -}; - -struct TX_FRAME_TAG_UDATA_BITS { // bits description - Uint16 FRAME_TAG:4; // 3:0 Frame Tag - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 USER_DATA:8; // 15:8 User Data -}; - -union TX_FRAME_TAG_UDATA_REG { - Uint16 all; - struct TX_FRAME_TAG_UDATA_BITS bit; -}; - -struct TX_BUF_PTR_LOAD_BITS { // bits description - Uint16 BUF_PTR_LOAD:4; // 3:0 Buffer Pointer Force Load - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_BUF_PTR_LOAD_REG { - Uint16 all; - struct TX_BUF_PTR_LOAD_BITS bit; -}; - -struct TX_BUF_PTR_STS_BITS { // bits description - Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 CURR_WORD_CNT:5; // 12:8 Remaining Words in Buffer - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union TX_BUF_PTR_STS_REG { - Uint16 all; - struct TX_BUF_PTR_STS_BITS bit; -}; - -struct TX_PING_CTRL_BITS { // bits description - Uint16 CNT_RST:1; // 0 Ping Counter Reset - Uint16 TIMER_EN:1; // 1 Ping Counter Enable - Uint16 EXT_TRIG_EN:1; // 2 External Trigger Enable - Uint16 EXT_TRIG_SEL:5; // 7:3 External Trigger Select - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_PING_CTRL_REG { - Uint16 all; - struct TX_PING_CTRL_BITS bit; -}; - -struct TX_PING_TAG_BITS { // bits description - Uint16 TAG:4; // 3:0 Ping Frame Tag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_PING_TAG_REG { - Uint16 all; - struct TX_PING_TAG_BITS bit; -}; - -struct TX_INT_CTRL_BITS { // bits description - Uint16 INT1_EN_FRAME_DONE:1; // 0 Enable Frame Done Interrupt to INT1 - Uint16 INT1_EN_BUF_UNDERRUN:1; // 1 Enable Buffer Underrun Interrupt to INT1 - Uint16 INT1_EN_BUF_OVERRUN:1; // 2 Enable Buffer Overrun Interrupt to INT1 - Uint16 INT1_EN_PING_TO:1; // 3 Enable Ping Timer Interrupt to INT1 - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 INT2_EN_FRAME_DONE:1; // 8 Enable Frame Done Interrupt to INT2 - Uint16 INT2_EN_BUF_UNDERRUN:1; // 9 Enable Buffer Underrun Interrupt to INT2 - Uint16 INT2_EN_BUF_OVERRUN:1; // 10 Enable Buffer Overrun Interrupt to INT2 - Uint16 INT2_EN_PING_TO:1; // 11 Enable Ping Timer Interrupt to INT2 - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union TX_INT_CTRL_REG { - Uint16 all; - struct TX_INT_CTRL_BITS bit; -}; - -struct TX_DMA_CTRL_BITS { // bits description - Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TX_DMA_CTRL_REG { - Uint16 all; - struct TX_DMA_CTRL_BITS bit; -}; - -struct TX_LOCK_CTRL_BITS { // bits description - Uint16 LOCK:1; // 0 Control Register Lock Enable - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union TX_LOCK_CTRL_REG { - Uint16 all; - struct TX_LOCK_CTRL_BITS bit; -}; - -struct TX_EVT_STS_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_STS_REG { - Uint16 all; - struct TX_EVT_STS_BITS bit; -}; - -struct TX_EVT_CLR_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag Clear - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Clear - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Clear - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_CLR_REG { - Uint16 all; - struct TX_EVT_CLR_BITS bit; -}; - -struct TX_EVT_FRC_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag Force - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Force - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Force - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Force - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_FRC_REG { - Uint16 all; - struct TX_EVT_FRC_BITS bit; -}; - -struct TX_USER_CRC_BITS { // bits description - Uint16 USER_CRC:8; // 7:0 User-defined CRC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_USER_CRC_REG { - Uint16 all; - struct TX_USER_CRC_BITS bit; -}; - -struct TX_ECC_DATA_BITS { // bits description - Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits - Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits -}; - -union TX_ECC_DATA_REG { - Uint32 all; - struct TX_ECC_DATA_BITS bit; -}; - -struct TX_ECC_VAL_BITS { // bits description - Uint16 ECC_VAL:8; // 7:0 Computed ECC Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_ECC_VAL_REG { - Uint16 all; - struct TX_ECC_VAL_BITS bit; -}; - -struct FSI_TX_REGS { - union TX_MASTER_CTRL_REG TX_MASTER_CTRL; // Transmit master control register - Uint16 rsvd1; // Reserved - union TX_CLK_CTRL_REG TX_CLK_CTRL; // Transmit clock control register - Uint16 rsvd2; // Reserved - union TX_OPER_CTRL_LO_REG TX_OPER_CTRL_LO; // Transmit operation control register low - union TX_OPER_CTRL_HI_REG TX_OPER_CTRL_HI; // Transmit operation control register high - union TX_FRAME_CTRL_REG TX_FRAME_CTRL; // Transmit frame control register - union TX_FRAME_TAG_UDATA_REG TX_FRAME_TAG_UDATA; // Transmit frame tag and user data register - union TX_BUF_PTR_LOAD_REG TX_BUF_PTR_LOAD; // Transmit buffer pointer control load register - union TX_BUF_PTR_STS_REG TX_BUF_PTR_STS; // Transmit buffer pointer control status register - union TX_PING_CTRL_REG TX_PING_CTRL; // Transmit ping control register - union TX_PING_TAG_REG TX_PING_TAG; // Transmit ping tag register - Uint32 TX_PING_TO_REF; // Transmit ping timeout counter reference - Uint32 TX_PING_TO_CNT; // Transmit ping timeout current count - union TX_INT_CTRL_REG TX_INT_CTRL; // Transmit interrupt event control register - union TX_DMA_CTRL_REG TX_DMA_CTRL; // Transmit DMA event control register - union TX_LOCK_CTRL_REG TX_LOCK_CTRL; // Transmit lock control register - Uint16 rsvd3; // Reserved - union TX_EVT_STS_REG TX_EVT_STS; // Transmit event and error status flag register - Uint16 rsvd4; // Reserved - union TX_EVT_CLR_REG TX_EVT_CLR; // Transmit event and error clear register - union TX_EVT_FRC_REG TX_EVT_FRC; // Transmit event and error flag force register - union TX_USER_CRC_REG TX_USER_CRC; // Transmit user-defined CRC register - Uint16 rsvd5[7]; // Reserved - union TX_ECC_DATA_REG TX_ECC_DATA; // Transmit ECC data register - union TX_ECC_VAL_REG TX_ECC_VAL; // Transmit ECC value register - Uint16 rsvd6[29]; // Reserved - Uint16 TX_BUF_BASE; // Base address for transmit buffer -}; - -struct RX_MASTER_CTRL_BITS { // bits description - Uint16 CORE_RST:1; // 0 Receiver Master Core Reset - Uint16 INT_LOOPBACK:1; // 1 Internal Loopback Enable - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:5; // 7:3 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union RX_MASTER_CTRL_REG { - Uint16 all; - struct RX_MASTER_CTRL_BITS bit; -}; - -struct RX_OPER_CTRL_BITS { // bits description - Uint16 DATA_WIDTH:2; // 1:0 Receive Data Width Select - Uint16 rsvd1:1; // 2 Reserved - Uint16 N_WORDS:4; // 6:3 Number of Words to be Received - Uint16 ECC_SEL:1; // 7 ECC Data Width Select - Uint16 PING_WD_RST_MODE:1; // 8 Ping Watchdog Timeout Mode Select - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union RX_OPER_CTRL_REG { - Uint16 all; - struct RX_OPER_CTRL_BITS bit; -}; - -struct RX_FRAME_INFO_BITS { // bits description - Uint16 FRAME_TYPE:4; // 3:0 Received Frame Type - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RX_FRAME_INFO_REG { - Uint16 all; - struct RX_FRAME_INFO_BITS bit; -}; - -struct RX_FRAME_TAG_UDATA_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 FRAME_TAG:4; // 4:1 Received Frame Tag - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 USER_DATA:8; // 15:8 Received User Data -}; - -union RX_FRAME_TAG_UDATA_REG { - Uint16 all; - struct RX_FRAME_TAG_UDATA_BITS bit; -}; - -struct RX_DMA_CTRL_BITS { // bits description - Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union RX_DMA_CTRL_REG { - Uint16 all; - struct RX_DMA_CTRL_BITS bit; -}; - -struct RX_EVT_STS_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag. - Uint16 CRC_ERR:1; // 2 CRC Error Flag - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag - Uint16 FRAME_DONE:1; // 6 Frame Done Flag - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag - Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_STS_REG { - Uint16 all; - struct RX_EVT_STS_BITS bit; -}; - -struct RX_CRC_INFO_BITS { // bits description - Uint16 RX_CRC:8; // 7:0 Received CRC Value - Uint16 CALC_CRC:8; // 15:8 Hardware Calculated CRC -}; - -union RX_CRC_INFO_REG { - Uint16 all; - struct RX_CRC_INFO_BITS bit; -}; - -struct RX_EVT_CLR_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Clear - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Clear - Uint16 CRC_ERR:1; // 2 CRC Error Flag Clear - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Clear - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Clear - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Clear - Uint16 FRAME_DONE:1; // 6 Frame Done Flag Clear - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Clear - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Clear - Uint16 PING_FRAME:1; // 9 PING Frame Received Flag Clear - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Clear - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Clear - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_CLR_REG { - Uint16 all; - struct RX_EVT_CLR_BITS bit; -}; - -struct RX_EVT_FRC_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Force - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Force - Uint16 CRC_ERR:1; // 2 CRC Error Flag Force - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Force - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Force - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Force - Uint16 FRAME_DONE:1; // 6 Frame Done Flag Force - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Force - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Force - Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Force - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Force - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Force - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_FRC_REG { - Uint16 all; - struct RX_EVT_FRC_BITS bit; -}; - -struct RX_BUF_PTR_LOAD_BITS { // bits description - Uint16 BUF_PTR_LOAD:4; // 3:0 Load value for receive buffer pointer - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RX_BUF_PTR_LOAD_REG { - Uint16 all; - struct RX_BUF_PTR_LOAD_BITS bit; -}; - -struct RX_BUF_PTR_STS_BITS { // bits description - Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 CURR_WORD_CNT:5; // 12:8 Available Words in Buffer - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union RX_BUF_PTR_STS_REG { - Uint16 all; - struct RX_BUF_PTR_STS_BITS bit; -}; - -struct RX_FRAME_WD_CTRL_BITS { // bits description - Uint16 FRAME_WD_CNT_RST:1; // 0 Frame Watchdog Counter Reset - Uint16 FRAME_WD_EN:1; // 1 Frame Watchdog Counter Enable - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_FRAME_WD_CTRL_REG { - Uint16 all; - struct RX_FRAME_WD_CTRL_BITS bit; -}; - -struct RX_PING_WD_CTRL_BITS { // bits description - Uint16 PING_WD_RST:1; // 0 Ping Watchdog Counter Reset - Uint16 PING_WD_EN:1; // 1 Ping Watchdog Counter Enable - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_PING_WD_CTRL_REG { - Uint16 all; - struct RX_PING_WD_CTRL_BITS bit; -}; - -struct RX_PING_TAG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PING_TAG:4; // 4:1 Ping Frame Tag - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union RX_PING_TAG_REG { - Uint16 all; - struct RX_PING_TAG_BITS bit; -}; - -struct RX_INT1_CTRL_BITS { // bits description - Uint16 INT1_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT1 - Uint16 INT1_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT1 - Uint16 INT1_EN_CRC_ERR:1; // 2 Enable CRC Error Interrupt to INT1 - Uint16 INT1_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT1 - Uint16 INT1_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT1 - Uint16 INT1_EN_OVERRUN:1; // 5 Enable Receive Buffer Overrun Interrupt to INT1 - Uint16 INT1_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT1 - Uint16 INT1_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT1 - Uint16 INT1_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT1 - Uint16 INT1_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT1 - Uint16 INT1_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT1 - Uint16 INT1_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT1 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_INT1_CTRL_REG { - Uint16 all; - struct RX_INT1_CTRL_BITS bit; -}; - -struct RX_INT2_CTRL_BITS { // bits description - Uint16 INT2_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT2 - Uint16 INT2_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT2 - Uint16 INT2_EN_CRC_ERR:1; // 2 Enable CRC Errror Interrupt to INT2 - Uint16 INT2_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT2 - Uint16 INT2_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT2 - Uint16 INT2_EN_OVERRUN:1; // 5 Enable Buffer Overrun Interrupt to INT2 - Uint16 INT2_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT2 - Uint16 INT2_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT2 - Uint16 INT2_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT2 - Uint16 INT2_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT2 - Uint16 INT2_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT2 - Uint16 INT2_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_INT2_CTRL_REG { - Uint16 all; - struct RX_INT2_CTRL_BITS bit; -}; - -struct RX_LOCK_CTRL_BITS { // bits description - Uint16 LOCK:1; // 0 Control Register Lock Enable - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union RX_LOCK_CTRL_REG { - Uint16 all; - struct RX_LOCK_CTRL_BITS bit; -}; - -struct RX_ECC_DATA_BITS { // bits description - Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits - Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits -}; - -union RX_ECC_DATA_REG { - Uint32 all; - struct RX_ECC_DATA_BITS bit; -}; - -struct RX_ECC_VAL_BITS { // bits description - Uint16 ECC_VAL:8; // 7:0 Computed ECC Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union RX_ECC_VAL_REG { - Uint16 all; - struct RX_ECC_VAL_BITS bit; -}; - -struct RX_ECC_LOG_BITS { // bits description - Uint16 SBE:1; // 0 Single Bit Error Detected - Uint16 MBE:1; // 1 Multiple Bit Errors Detected - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_ECC_LOG_REG { - Uint16 all; - struct RX_ECC_LOG_BITS bit; -}; - -struct RX_DLYLINE_CTRL_BITS { // bits description - Uint16 RXCLK_DLY:5; // 4:0 Delay Line Tap Select for RXCLK - Uint16 RXD0_DLY:5; // 9:5 Delay Line Tap Select for RXD0 - Uint16 RXD1_DLY:5; // 14:10 Delay Line Tap Select for RXD1 - Uint16 rsvd1:1; // 15 Reserved -}; - -union RX_DLYLINE_CTRL_REG { - Uint16 all; - struct RX_DLYLINE_CTRL_BITS bit; -}; - -struct RX_VIS_1_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 RX_CORE_STS:1; // 3 Receiver Core Status - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union RX_VIS_1_REG { - Uint32 all; - struct RX_VIS_1_BITS bit; -}; - -struct FSI_RX_REGS { - union RX_MASTER_CTRL_REG RX_MASTER_CTRL; // Receive master control register - Uint16 rsvd1[3]; // Reserved - union RX_OPER_CTRL_REG RX_OPER_CTRL; // Receive operation control register - Uint16 rsvd2; // Reserved - union RX_FRAME_INFO_REG RX_FRAME_INFO; // Receive frame control register - union RX_FRAME_TAG_UDATA_REG RX_FRAME_TAG_UDATA; // Receive frame tag and user data register - union RX_DMA_CTRL_REG RX_DMA_CTRL; // Receive DMA event control register - Uint16 rsvd3; // Reserved - union RX_EVT_STS_REG RX_EVT_STS; // Receive event and error status flag register - union RX_CRC_INFO_REG RX_CRC_INFO; // Receive CRC info of received and computed CRC - union RX_EVT_CLR_REG RX_EVT_CLR; // Receive event and error clear register - union RX_EVT_FRC_REG RX_EVT_FRC; // Receive event and error flag force register - union RX_BUF_PTR_LOAD_REG RX_BUF_PTR_LOAD; // Receive buffer pointer load register - union RX_BUF_PTR_STS_REG RX_BUF_PTR_STS; // Receive buffer pointer status register - union RX_FRAME_WD_CTRL_REG RX_FRAME_WD_CTRL; // Receive frame watchdog control register - Uint16 rsvd4; // Reserved - Uint32 RX_FRAME_WD_REF; // Receive frame watchdog counter reference - Uint32 RX_FRAME_WD_CNT; // Receive frame watchdog current count - union RX_PING_WD_CTRL_REG RX_PING_WD_CTRL; // Receive ping watchdog control register - union RX_PING_TAG_REG RX_PING_TAG; // Receive ping tag register - Uint32 RX_PING_WD_REF; // Receive ping watchdog counter reference - Uint32 RX_PING_WD_CNT; // Receive pingwatchdog current count - union RX_INT1_CTRL_REG RX_INT1_CTRL; // Receive interrupt control register for RX_INT1 - union RX_INT2_CTRL_REG RX_INT2_CTRL; // Receive interrupt control register for RX_INT2 - union RX_LOCK_CTRL_REG RX_LOCK_CTRL; // Receive lock control register - Uint16 rsvd5; // Reserved - union RX_ECC_DATA_REG RX_ECC_DATA; // Receive ECC data register - union RX_ECC_VAL_REG RX_ECC_VAL; // Receive ECC value register - Uint16 rsvd6; // Reserved - Uint32 RX_ECC_SEC_DATA; // Receive ECC corrected data register - union RX_ECC_LOG_REG RX_ECC_LOG; // Receive ECC log and status register - Uint16 rsvd7[9]; // Reserved - union RX_DLYLINE_CTRL_REG RX_DLYLINE_CTRL; // Receive delay line control register - Uint16 rsvd8[7]; // Reserved - union RX_VIS_1_REG RX_VIS_1; // Receive debug visibility register 1 - Uint16 rsvd9[6]; // Reserved - Uint16 RX_BUF_BASE; // Base address for receive data buffer -}; - -//--------------------------------------------------------------------------- -// FSI External References & Function Declarations: -// -extern volatile struct FSI_TX_REGS FsiTxaRegs; -extern volatile struct FSI_RX_REGS FsiRxaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h deleted file mode 100644 index 0c05ef1..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h +++ /dev/null @@ -1,1678 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio.h -// -// TITLE: GPIO Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_GPIO_H__ -#define __F28004X_GPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// GPIO Individual Register Bit Definitions: - -struct GPACTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 -}; - -union GPACTRL_REG { - Uint32 all; - struct GPACTRL_BITS bit; -}; - -struct GPAQSEL1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 - Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 - Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 - Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 - Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 - Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 - Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 - Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 - Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 - Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 - Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 - Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 - Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 - Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 - Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 - Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 -}; - -union GPAQSEL1_REG { - Uint32 all; - struct GPAQSEL1_BITS bit; -}; - -struct GPAQSEL2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 - Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 - Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 - Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 - Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 - Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 - Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 - Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 - Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 - Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 - Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 - Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 - Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 - Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 - Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 - Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 -}; - -union GPAQSEL2_REG { - Uint32 all; - struct GPAQSEL2_BITS bit; -}; - -struct GPAMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAMUX1_REG { - Uint32 all; - struct GPAMUX1_BITS bit; -}; - -struct GPAMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAMUX2_REG { - Uint32 all; - struct GPAMUX2_BITS bit; -}; - -struct GPADIR_BITS { // bits description - Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPADIR_REG { - Uint32 all; - struct GPADIR_BITS bit; -}; - -struct GPAPUD_BITS { // bits description - Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin -}; - -union GPAPUD_REG { - Uint32 all; - struct GPAPUD_BITS bit; -}; - -struct GPAINV_BITS { // bits description - Uint16 GPIO0:1; // 0 Input inversion control for this pin - Uint16 GPIO1:1; // 1 Input inversion control for this pin - Uint16 GPIO2:1; // 2 Input inversion control for this pin - Uint16 GPIO3:1; // 3 Input inversion control for this pin - Uint16 GPIO4:1; // 4 Input inversion control for this pin - Uint16 GPIO5:1; // 5 Input inversion control for this pin - Uint16 GPIO6:1; // 6 Input inversion control for this pin - Uint16 GPIO7:1; // 7 Input inversion control for this pin - Uint16 GPIO8:1; // 8 Input inversion control for this pin - Uint16 GPIO9:1; // 9 Input inversion control for this pin - Uint16 GPIO10:1; // 10 Input inversion control for this pin - Uint16 GPIO11:1; // 11 Input inversion control for this pin - Uint16 GPIO12:1; // 12 Input inversion control for this pin - Uint16 GPIO13:1; // 13 Input inversion control for this pin - Uint16 GPIO14:1; // 14 Input inversion control for this pin - Uint16 GPIO15:1; // 15 Input inversion control for this pin - Uint16 GPIO16:1; // 16 Input inversion control for this pin - Uint16 GPIO17:1; // 17 Input inversion control for this pin - Uint16 GPIO18:1; // 18 Input inversion control for this pin - Uint16 GPIO19:1; // 19 Input inversion control for this pin - Uint16 GPIO20:1; // 20 Input inversion control for this pin - Uint16 GPIO21:1; // 21 Input inversion control for this pin - Uint16 GPIO22:1; // 22 Input inversion control for this pin - Uint16 GPIO23:1; // 23 Input inversion control for this pin - Uint16 GPIO24:1; // 24 Input inversion control for this pin - Uint16 GPIO25:1; // 25 Input inversion control for this pin - Uint16 GPIO26:1; // 26 Input inversion control for this pin - Uint16 GPIO27:1; // 27 Input inversion control for this pin - Uint16 GPIO28:1; // 28 Input inversion control for this pin - Uint16 GPIO29:1; // 29 Input inversion control for this pin - Uint16 GPIO30:1; // 30 Input inversion control for this pin - Uint16 GPIO31:1; // 31 Input inversion control for this pin -}; - -union GPAINV_REG { - Uint32 all; - struct GPAINV_BITS bit; -}; - -struct GPAODR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Open-Drain control for this pin - Uint16 GPIO1:1; // 1 Output Open-Drain control for this pin - Uint16 GPIO2:1; // 2 Output Open-Drain control for this pin - Uint16 GPIO3:1; // 3 Output Open-Drain control for this pin - Uint16 GPIO4:1; // 4 Output Open-Drain control for this pin - Uint16 GPIO5:1; // 5 Output Open-Drain control for this pin - Uint16 GPIO6:1; // 6 Output Open-Drain control for this pin - Uint16 GPIO7:1; // 7 Output Open-Drain control for this pin - Uint16 GPIO8:1; // 8 Output Open-Drain control for this pin - Uint16 GPIO9:1; // 9 Output Open-Drain control for this pin - Uint16 GPIO10:1; // 10 Output Open-Drain control for this pin - Uint16 GPIO11:1; // 11 Output Open-Drain control for this pin - Uint16 GPIO12:1; // 12 Output Open-Drain control for this pin - Uint16 GPIO13:1; // 13 Output Open-Drain control for this pin - Uint16 GPIO14:1; // 14 Output Open-Drain control for this pin - Uint16 GPIO15:1; // 15 Output Open-Drain control for this pin - Uint16 GPIO16:1; // 16 Output Open-Drain control for this pin - Uint16 GPIO17:1; // 17 Output Open-Drain control for this pin - Uint16 GPIO18:1; // 18 Output Open-Drain control for this pin - Uint16 GPIO19:1; // 19 Output Open-Drain control for this pin - Uint16 GPIO20:1; // 20 Output Open-Drain control for this pin - Uint16 GPIO21:1; // 21 Output Open-Drain control for this pin - Uint16 GPIO22:1; // 22 Output Open-Drain control for this pin - Uint16 GPIO23:1; // 23 Output Open-Drain control for this pin - Uint16 GPIO24:1; // 24 Output Open-Drain control for this pin - Uint16 GPIO25:1; // 25 Output Open-Drain control for this pin - Uint16 GPIO26:1; // 26 Output Open-Drain control for this pin - Uint16 GPIO27:1; // 27 Output Open-Drain control for this pin - Uint16 GPIO28:1; // 28 Output Open-Drain control for this pin - Uint16 GPIO29:1; // 29 Output Open-Drain control for this pin - Uint16 GPIO30:1; // 30 Output Open-Drain control for this pin - Uint16 GPIO31:1; // 31 Output Open-Drain control for this pin -}; - -union GPAODR_REG { - Uint32 all; - struct GPAODR_BITS bit; -}; - -struct GPAAMSEL_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:1; // 8 Reserved - Uint16 rsvd10:1; // 9 Reserved - Uint16 rsvd11:1; // 10 Reserved - Uint16 rsvd12:1; // 11 Reserved - Uint16 rsvd13:1; // 12 Reserved - Uint16 rsvd14:1; // 13 Reserved - Uint16 rsvd15:1; // 14 Reserved - Uint16 rsvd16:1; // 15 Reserved - Uint16 rsvd17:1; // 16 Reserved - Uint16 rsvd18:1; // 17 Reserved - Uint16 rsvd19:1; // 18 Reserved - Uint16 rsvd20:1; // 19 Reserved - Uint16 rsvd21:1; // 20 Reserved - Uint16 rsvd22:1; // 21 Reserved - Uint16 GPIO22:1; // 22 Analog Mode select for this pin - Uint16 GPIO23:1; // 23 Analog Mode select for this pin - Uint16 rsvd23:1; // 24 Reserved - Uint16 rsvd24:1; // 25 Reserved - Uint16 rsvd25:1; // 26 Reserved - Uint16 rsvd26:1; // 27 Reserved - Uint16 rsvd27:1; // 28 Reserved - Uint16 rsvd28:1; // 29 Reserved - Uint16 rsvd29:1; // 30 Reserved - Uint16 rsvd30:1; // 31 Reserved -}; - -union GPAAMSEL_REG { - Uint32 all; - struct GPAAMSEL_BITS bit; -}; - -struct GPAGMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAGMUX1_REG { - Uint32 all; - struct GPAGMUX1_BITS bit; -}; - -struct GPAGMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAGMUX2_REG { - Uint32 all; - struct GPAGMUX2_BITS bit; -}; - -struct GPACSEL1_BITS { // bits description - Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select - Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select - Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select - Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select - Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select - Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select - Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select - Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select -}; - -union GPACSEL1_REG { - Uint32 all; - struct GPACSEL1_BITS bit; -}; - -struct GPACSEL2_BITS { // bits description - Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select - Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select - Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select - Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select - Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select - Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select - Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select - Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select -}; - -union GPACSEL2_REG { - Uint32 all; - struct GPACSEL2_BITS bit; -}; - -struct GPACSEL3_BITS { // bits description - Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select - Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select - Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select - Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select - Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select - Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select - Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select - Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select -}; - -union GPACSEL3_REG { - Uint32 all; - struct GPACSEL3_BITS bit; -}; - -struct GPACSEL4_BITS { // bits description - Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select - Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select - Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select - Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select - Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select - Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select - Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select - Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select -}; - -union GPACSEL4_REG { - Uint32 all; - struct GPACSEL4_BITS bit; -}; - -struct GPALOCK_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin -}; - -union GPALOCK_REG { - Uint32 all; - struct GPALOCK_BITS bit; -}; - -struct GPACR_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin -}; - -union GPACR_REG { - Uint32 all; - struct GPACR_BITS bit; -}; - -struct GPBCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 -}; - -union GPBCTRL_REG { - Uint32 all; - struct GPBCTRL_BITS bit; -}; - -struct GPBQSEL1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 - Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 - Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 - Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 - Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 - Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 - Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 - Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 - Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 - Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 - Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 - Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 -}; - -union GPBQSEL1_REG { - Uint32 all; - struct GPBQSEL1_BITS bit; -}; - -struct GPBQSEL2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 - Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 - Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 - Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 - Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 - Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 - Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 - Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 - Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 - Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 - Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 - Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBQSEL2_REG { - Uint32 all; - struct GPBQSEL2_BITS bit; -}; - -struct GPBMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBMUX1_REG { - Uint32 all; - struct GPBMUX1_BITS bit; -}; - -struct GPBMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBMUX2_REG { - Uint32 all; - struct GPBMUX2_BITS bit; -}; - -struct GPBDIR_BITS { // bits description - Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBDIR_REG { - Uint32 all; - struct GPBDIR_BITS bit; -}; - -struct GPBPUD_BITS { // bits description - Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBPUD_REG { - Uint32 all; - struct GPBPUD_BITS bit; -}; - -struct GPBINV_BITS { // bits description - Uint16 GPIO32:1; // 0 Input inversion control for this pin - Uint16 GPIO33:1; // 1 Input inversion control for this pin - Uint16 GPIO34:1; // 2 Input inversion control for this pin - Uint16 GPIO35:1; // 3 Input inversion control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Input inversion control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Input inversion control for this pin - Uint16 GPIO40:1; // 8 Input inversion control for this pin - Uint16 GPIO41:1; // 9 Input inversion control for this pin - Uint16 GPIO42:1; // 10 Input inversion control for this pin - Uint16 GPIO43:1; // 11 Input inversion control for this pin - Uint16 GPIO44:1; // 12 Input inversion control for this pin - Uint16 GPIO45:1; // 13 Input inversion control for this pin - Uint16 GPIO46:1; // 14 Input inversion control for this pin - Uint16 GPIO47:1; // 15 Input inversion control for this pin - Uint16 GPIO48:1; // 16 Input inversion control for this pin - Uint16 GPIO49:1; // 17 Input inversion control for this pin - Uint16 GPIO50:1; // 18 Input inversion control for this pin - Uint16 GPIO51:1; // 19 Input inversion control for this pin - Uint16 GPIO52:1; // 20 Input inversion control for this pin - Uint16 GPIO53:1; // 21 Input inversion control for this pin - Uint16 GPIO54:1; // 22 Input inversion control for this pin - Uint16 GPIO55:1; // 23 Input inversion control for this pin - Uint16 GPIO56:1; // 24 Input inversion control for this pin - Uint16 GPIO57:1; // 25 Input inversion control for this pin - Uint16 GPIO58:1; // 26 Input inversion control for this pin - Uint16 GPIO59:1; // 27 Input inversion control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBINV_REG { - Uint32 all; - struct GPBINV_BITS bit; -}; - -struct GPBODR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Open-Drain control for this pin - Uint16 GPIO33:1; // 1 Output Open-Drain control for this pin - Uint16 GPIO34:1; // 2 Output Open-Drain control for this pin - Uint16 GPIO35:1; // 3 Output Open-Drain control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Open-Drain control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Open-Drain control for this pin - Uint16 GPIO40:1; // 8 Output Open-Drain control for this pin - Uint16 GPIO41:1; // 9 Output Open-Drain control for this pin - Uint16 GPIO42:1; // 10 Output Open-Drain control for this pin - Uint16 GPIO43:1; // 11 Output Open-Drain control for this pin - Uint16 GPIO44:1; // 12 Output Open-Drain control for this pin - Uint16 GPIO45:1; // 13 Output Open-Drain control for this pin - Uint16 GPIO46:1; // 14 Output Open-Drain control for this pin - Uint16 GPIO47:1; // 15 Output Open-Drain control for this pin - Uint16 GPIO48:1; // 16 Output Open-Drain control for this pin - Uint16 GPIO49:1; // 17 Output Open-Drain control for this pin - Uint16 GPIO50:1; // 18 Output Open-Drain control for this pin - Uint16 GPIO51:1; // 19 Output Open-Drain control for this pin - Uint16 GPIO52:1; // 20 Output Open-Drain control for this pin - Uint16 GPIO53:1; // 21 Output Open-Drain control for this pin - Uint16 GPIO54:1; // 22 Output Open-Drain control for this pin - Uint16 GPIO55:1; // 23 Output Open-Drain control for this pin - Uint16 GPIO56:1; // 24 Output Open-Drain control for this pin - Uint16 GPIO57:1; // 25 Output Open-Drain control for this pin - Uint16 GPIO58:1; // 26 Output Open-Drain control for this pin - Uint16 GPIO59:1; // 27 Output Open-Drain control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBODR_REG { - Uint32 all; - struct GPBODR_BITS bit; -}; - -struct GPBGMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBGMUX1_REG { - Uint32 all; - struct GPBGMUX1_BITS bit; -}; - -struct GPBGMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBGMUX2_REG { - Uint32 all; - struct GPBGMUX2_BITS bit; -}; - -struct GPBCSEL1_BITS { // bits description - Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select - Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select - Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select - Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select - Uint16 rsvd1:4; // 19:16 Reserved - Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select - Uint16 rsvd2:4; // 27:24 Reserved - Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select -}; - -union GPBCSEL1_REG { - Uint32 all; - struct GPBCSEL1_BITS bit; -}; - -struct GPBCSEL2_BITS { // bits description - Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select - Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select - Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select - Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select - Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select - Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select - Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select - Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select -}; - -union GPBCSEL2_REG { - Uint32 all; - struct GPBCSEL2_BITS bit; -}; - -struct GPBCSEL3_BITS { // bits description - Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select - Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select - Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select - Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select - Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select - Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select - Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select - Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select -}; - -union GPBCSEL3_REG { - Uint32 all; - struct GPBCSEL3_BITS bit; -}; - -struct GPBCSEL4_BITS { // bits description - Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select - Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select - Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select - Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select - Uint16 rsvd1:4; // 19:16 Reserved - Uint16 rsvd2:4; // 23:20 Reserved - Uint16 rsvd3:4; // 27:24 Reserved - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union GPBCSEL4_REG { - Uint32 all; - struct GPBCSEL4_BITS bit; -}; - -struct GPBLOCK_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBLOCK_REG { - Uint32 all; - struct GPBLOCK_BITS bit; -}; - -struct GPBCR_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBCR_REG { - Uint32 all; - struct GPBCR_BITS bit; -}; - -struct GPHCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO224 to GPIO231 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO232 to GPIO239 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO240 to GPIO247 - Uint16 rsvd1:8; // 31:24 Reserved -}; - -union GPHCTRL_REG { - Uint32 all; - struct GPHCTRL_BITS bit; -}; - -struct GPHQSEL1_BITS { // bits description - Uint16 GPIO224:2; // 1:0 Select input qualification type for this GPIO Pin - Uint16 GPIO225:2; // 3:2 Select input qualification type for this GPIO Pin - Uint16 GPIO226:2; // 5:4 Select input qualification type for this GPIO Pin - Uint16 GPIO227:2; // 7:6 Select input qualification type for this GPIO Pin - Uint16 GPIO228:2; // 9:8 Select input qualification type for this GPIO Pin - Uint16 GPIO229:2; // 11:10 Select input qualification type for this GPIO Pin - Uint16 GPIO230:2; // 13:12 Select input qualification type for this GPIO Pin - Uint16 GPIO231:2; // 15:14 Select input qualification type for this GPIO Pin - Uint16 GPIO232:2; // 17:16 Select input qualification type for this GPIO Pin - Uint16 GPIO233:2; // 19:18 Select input qualification type for this GPIO Pin - Uint16 GPIO234:2; // 21:20 Select input qualification type for this GPIO Pin - Uint16 GPIO235:2; // 23:22 Select input qualification type for this GPIO Pin - Uint16 GPIO236:2; // 25:24 Select input qualification type for this GPIO Pin - Uint16 GPIO237:2; // 27:26 Select input qualification type for this GPIO Pin - Uint16 GPIO238:2; // 29:28 Select input qualification type for this GPIO Pin - Uint16 GPIO239:2; // 31:30 Select input qualification type for this GPIO Pin -}; - -union GPHQSEL1_REG { - Uint32 all; - struct GPHQSEL1_BITS bit; -}; - -struct GPHQSEL2_BITS { // bits description - Uint16 GPIO240:2; // 1:0 Select input qualification type for this GPIO Pin - Uint16 GPIO241:2; // 3:2 Select input qualification type for this GPIO Pin - Uint16 GPIO242:2; // 5:4 Select input qualification type for this GPIO Pin - Uint16 GPIO243:2; // 7:6 Select input qualification type for this GPIO Pin - Uint16 GPIO244:2; // 9:8 Select input qualification type for this GPIO Pin - Uint16 GPIO245:2; // 11:10 Select input qualification type for this GPIO Pin - Uint16 GPIO246:2; // 13:12 Select input qualification type for this GPIO Pin - Uint16 GPIO247:2; // 15:14 Select input qualification type for this GPIO Pin - Uint16 rsvd1:2; // 17:16 Reserved - Uint16 rsvd2:2; // 19:18 Reserved - Uint16 rsvd3:2; // 21:20 Reserved - Uint16 rsvd4:2; // 23:22 Reserved - Uint16 rsvd5:2; // 25:24 Reserved - Uint16 rsvd6:2; // 27:26 Reserved - Uint16 rsvd7:2; // 29:28 Reserved - Uint16 rsvd8:2; // 31:30 Reserved -}; - -union GPHQSEL2_REG { - Uint32 all; - struct GPHQSEL2_BITS bit; -}; - -struct GPHINV_BITS { // bits description - Uint16 GPIO224:1; // 0 Input inversion control for this pin - Uint16 GPIO225:1; // 1 Input inversion control for this pin - Uint16 GPIO226:1; // 2 Input inversion control for this pin - Uint16 GPIO227:1; // 3 Input inversion control for this pin - Uint16 GPIO228:1; // 4 Input inversion control for this pin - Uint16 GPIO229:1; // 5 Input inversion control for this pin - Uint16 GPIO230:1; // 6 Input inversion control for this pin - Uint16 GPIO231:1; // 7 Input inversion control for this pin - Uint16 GPIO232:1; // 8 Input inversion control for this pin - Uint16 GPIO233:1; // 9 Input inversion control for this pin - Uint16 GPIO234:1; // 10 Input inversion control for this pin - Uint16 GPIO235:1; // 11 Input inversion control for this pin - Uint16 GPIO236:1; // 12 Input inversion control for this pin - Uint16 GPIO237:1; // 13 Input inversion control for this pin - Uint16 GPIO238:1; // 14 Input inversion control for this pin - Uint16 GPIO239:1; // 15 Input inversion control for this pin - Uint16 GPIO240:1; // 16 Input inversion control for this pin - Uint16 GPIO241:1; // 17 Input inversion control for this pin - Uint16 GPIO242:1; // 18 Input inversion control for this pin - Uint16 GPIO243:1; // 19 Input inversion control for this pin - Uint16 GPIO244:1; // 20 Input inversion control for this pin - Uint16 GPIO245:1; // 21 Input inversion control for this pin - Uint16 GPIO246:1; // 22 Input inversion control for this pin - Uint16 GPIO247:1; // 23 Input inversion control for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHINV_REG { - Uint32 all; - struct GPHINV_BITS bit; -}; - -struct GPHAMSEL_BITS { // bits description - Uint16 GPIO224:1; // 0 Analog Mode select for this pin - Uint16 GPIO225:1; // 1 Analog Mode select for this pin - Uint16 GPIO226:1; // 2 Analog Mode select for this pin - Uint16 GPIO227:1; // 3 Analog Mode select for this pin - Uint16 GPIO228:1; // 4 Analog Mode select for this pin - Uint16 GPIO229:1; // 5 Analog Mode select for this pin - Uint16 GPIO230:1; // 6 Analog Mode select for this pin - Uint16 GPIO231:1; // 7 Analog Mode select for this pin - Uint16 GPIO232:1; // 8 Analog Mode select for this pin - Uint16 GPIO233:1; // 9 Analog Mode select for this pin - Uint16 GPIO234:1; // 10 Analog Mode select for this pin - Uint16 GPIO235:1; // 11 Analog Mode select for this pin - Uint16 GPIO236:1; // 12 Analog Mode select for this pin - Uint16 GPIO237:1; // 13 Analog Mode select for this pin - Uint16 GPIO238:1; // 14 Analog Mode select for this pin - Uint16 GPIO239:1; // 15 Analog Mode select for this pin - Uint16 GPIO240:1; // 16 Analog Mode select for this pin - Uint16 GPIO241:1; // 17 Analog Mode select for this pin - Uint16 GPIO242:1; // 18 Analog Mode select for this pin - Uint16 GPIO243:1; // 19 Analog Mode select for this pin - Uint16 GPIO244:1; // 20 Analog Mode select for this pin - Uint16 GPIO245:1; // 21 Analog Mode select for this pin - Uint16 GPIO246:1; // 22 Analog Mode select for this pin - Uint16 GPIO247:1; // 23 Analog Mode select for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHAMSEL_REG { - Uint32 all; - struct GPHAMSEL_BITS bit; -}; - -struct GPHLOCK_BITS { // bits description - Uint16 GPIO224:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO225:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO226:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO227:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO228:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO229:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO230:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO231:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO232:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO233:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO234:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO235:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO236:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO237:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO238:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO239:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO240:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO241:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO242:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO243:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO244:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO245:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO246:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO247:1; // 23 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHLOCK_REG { - Uint32 all; - struct GPHLOCK_BITS bit; -}; - -struct GPHCR_BITS { // bits description - Uint16 GPIO224:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO225:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO226:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO227:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO228:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO229:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO230:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO231:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO232:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO233:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO234:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO235:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO236:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO237:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO238:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO239:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO240:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO241:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO242:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO243:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO244:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO245:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO246:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO247:1; // 23 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHCR_REG { - Uint32 all; - struct GPHCR_BITS bit; -}; - -struct GPIO_CTRL_REGS { - union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period (GPIO0 to GPIO31) - union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualification Type (GPIO0 to GPIO15) - union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualification Type (GPIO16 to GPIO31) - union GPAMUX1_REG GPAMUX1; // GPIO A Peripheral Mux (GPIO0 to GPIO15) - union GPAMUX2_REG GPAMUX2; // GPIO A Peripheral Mux (GPIO16 to GPIO31) - union GPADIR_REG GPADIR; // GPIO A Direction (GPIO0 to GPIO31) - union GPAPUD_REG GPAPUD; // GPIO A Pull-Up Disable (GPIO0 to GPIO31) - Uint16 rsvd1[2]; // Reserved - union GPAINV_REG GPAINV; // GPIO A Input Inversion (GPIO0 to GPIO31) - union GPAODR_REG GPAODR; // GPIO A Open Drain Output Mode (GPIO0 to GPIO31) - union GPAAMSEL_REG GPAAMSEL; // GPIO A Analog Mode Select (GPIO0 to GPIO31) - Uint16 rsvd2[10]; // Reserved - union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to GPIO15) - union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to GPIO31) - Uint16 rsvd3[4]; // Reserved - union GPACSEL1_REG GPACSEL1; // GPIO A Master Core Select (GPIO0 to GPIO7) - union GPACSEL2_REG GPACSEL2; // GPIO A Master Core Select (GPIO8 to GPIO15) - union GPACSEL3_REG GPACSEL3; // GPIO A Master Core Select (GPIO16 to GPIO23) - union GPACSEL4_REG GPACSEL4; // GPIO A Master Core Select (GPIO24 to GPIO31) - Uint16 rsvd4[12]; // Reserved - union GPALOCK_REG GPALOCK; // GPIO A Lock Register (GPIO0 to GPIO31) - union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to GPIO31) - union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period (GPIO32 to GPIO63) - union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualification Type (GPIO32 to GPIO47) - union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualification Type (GPIO48 to GPIO63) - union GPBMUX1_REG GPBMUX1; // GPIO B Peripheral Mux (GPIO32 to GPIO47) - union GPBMUX2_REG GPBMUX2; // GPIO B Peripheral Mux (GPIO48 to GPIO63) - union GPBDIR_REG GPBDIR; // GPIO B Direction (GPIO32 to GPIO63) - union GPBPUD_REG GPBPUD; // GPIO B Pull-Up Disable (GPIO32 to GPIO63) - Uint16 rsvd5[2]; // Reserved - union GPBINV_REG GPBINV; // GPIO B Input Inversion (GPIO32 to GPIO63) - union GPBODR_REG GPBODR; // GPIO B Open Drain Output Mode (GPIO32 to GPIO63) - Uint16 rsvd6[12]; // Reserved - union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to GPIO47) - union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to GPIO63) - Uint16 rsvd7[4]; // Reserved - union GPBCSEL1_REG GPBCSEL1; // GPIO B Master Core Select (GPIO32 to GPIO39) - union GPBCSEL2_REG GPBCSEL2; // GPIO B Master Core Select (GPIO40 to GPIO47) - union GPBCSEL3_REG GPBCSEL3; // GPIO B Master Core Select (GPIO48 to GPIO55) - union GPBCSEL4_REG GPBCSEL4; // GPIO B Master Core Select (GPIO56 to GPIO63) - Uint16 rsvd8[12]; // Reserved - union GPBLOCK_REG GPBLOCK; // GPIO B Lock Register (GPIO32 to GPIO63) - union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to GPIO63) - Uint16 rsvd9[320]; // Reserved - union GPHCTRL_REG GPHCTRL; // GPIO H Qualification Sampling Period (GPIO224 to GPIO255) - union GPHQSEL1_REG GPHQSEL1; // GPIO H Qualification Type (GPIO224 to GPIO239) - union GPHQSEL2_REG GPHQSEL2; // GPIO H Qualification Type (GPIO240 to GPIO255) - Uint16 rsvd10[10]; // Reserved - union GPHINV_REG GPHINV; // GPIO H Input Inversion (GPIO224 to GPIO255) - Uint16 rsvd11[2]; // Reserved - union GPHAMSEL_REG GPHAMSEL; // GPIO H Analog Mode Select (GPIO224 to GPIO255) - Uint16 rsvd12[38]; // Reserved - union GPHLOCK_REG GPHLOCK; // GPIO H Lock Register (GPIO224 to GPIO255) - union GPHCR_REG GPHCR; // GPIO H Lock Commit Register (GPIO224 to GPIO255) -}; - -struct GPADAT_BITS { // bits description - Uint16 GPIO0:1; // 0 Data Register for this pin - Uint16 GPIO1:1; // 1 Data Register for this pin - Uint16 GPIO2:1; // 2 Data Register for this pin - Uint16 GPIO3:1; // 3 Data Register for this pin - Uint16 GPIO4:1; // 4 Data Register for this pin - Uint16 GPIO5:1; // 5 Data Register for this pin - Uint16 GPIO6:1; // 6 Data Register for this pin - Uint16 GPIO7:1; // 7 Data Register for this pin - Uint16 GPIO8:1; // 8 Data Register for this pin - Uint16 GPIO9:1; // 9 Data Register for this pin - Uint16 GPIO10:1; // 10 Data Register for this pin - Uint16 GPIO11:1; // 11 Data Register for this pin - Uint16 GPIO12:1; // 12 Data Register for this pin - Uint16 GPIO13:1; // 13 Data Register for this pin - Uint16 GPIO14:1; // 14 Data Register for this pin - Uint16 GPIO15:1; // 15 Data Register for this pin - Uint16 GPIO16:1; // 16 Data Register for this pin - Uint16 GPIO17:1; // 17 Data Register for this pin - Uint16 GPIO18:1; // 18 Data Register for this pin - Uint16 GPIO19:1; // 19 Data Register for this pin - Uint16 GPIO20:1; // 20 Data Register for this pin - Uint16 GPIO21:1; // 21 Data Register for this pin - Uint16 GPIO22:1; // 22 Data Register for this pin - Uint16 GPIO23:1; // 23 Data Register for this pin - Uint16 GPIO24:1; // 24 Data Register for this pin - Uint16 GPIO25:1; // 25 Data Register for this pin - Uint16 GPIO26:1; // 26 Data Register for this pin - Uint16 GPIO27:1; // 27 Data Register for this pin - Uint16 GPIO28:1; // 28 Data Register for this pin - Uint16 GPIO29:1; // 29 Data Register for this pin - Uint16 GPIO30:1; // 30 Data Register for this pin - Uint16 GPIO31:1; // 31 Data Register for this pin -}; - -union GPADAT_REG { - Uint32 all; - struct GPADAT_BITS bit; -}; - -struct GPASET_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Set bit for this pin - Uint16 GPIO1:1; // 1 Output Set bit for this pin - Uint16 GPIO2:1; // 2 Output Set bit for this pin - Uint16 GPIO3:1; // 3 Output Set bit for this pin - Uint16 GPIO4:1; // 4 Output Set bit for this pin - Uint16 GPIO5:1; // 5 Output Set bit for this pin - Uint16 GPIO6:1; // 6 Output Set bit for this pin - Uint16 GPIO7:1; // 7 Output Set bit for this pin - Uint16 GPIO8:1; // 8 Output Set bit for this pin - Uint16 GPIO9:1; // 9 Output Set bit for this pin - Uint16 GPIO10:1; // 10 Output Set bit for this pin - Uint16 GPIO11:1; // 11 Output Set bit for this pin - Uint16 GPIO12:1; // 12 Output Set bit for this pin - Uint16 GPIO13:1; // 13 Output Set bit for this pin - Uint16 GPIO14:1; // 14 Output Set bit for this pin - Uint16 GPIO15:1; // 15 Output Set bit for this pin - Uint16 GPIO16:1; // 16 Output Set bit for this pin - Uint16 GPIO17:1; // 17 Output Set bit for this pin - Uint16 GPIO18:1; // 18 Output Set bit for this pin - Uint16 GPIO19:1; // 19 Output Set bit for this pin - Uint16 GPIO20:1; // 20 Output Set bit for this pin - Uint16 GPIO21:1; // 21 Output Set bit for this pin - Uint16 GPIO22:1; // 22 Output Set bit for this pin - Uint16 GPIO23:1; // 23 Output Set bit for this pin - Uint16 GPIO24:1; // 24 Output Set bit for this pin - Uint16 GPIO25:1; // 25 Output Set bit for this pin - Uint16 GPIO26:1; // 26 Output Set bit for this pin - Uint16 GPIO27:1; // 27 Output Set bit for this pin - Uint16 GPIO28:1; // 28 Output Set bit for this pin - Uint16 GPIO29:1; // 29 Output Set bit for this pin - Uint16 GPIO30:1; // 30 Output Set bit for this pin - Uint16 GPIO31:1; // 31 Output Set bit for this pin -}; - -union GPASET_REG { - Uint32 all; - struct GPASET_BITS bit; -}; - -struct GPACLEAR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Clear bit for this pin - Uint16 GPIO1:1; // 1 Output Clear bit for this pin - Uint16 GPIO2:1; // 2 Output Clear bit for this pin - Uint16 GPIO3:1; // 3 Output Clear bit for this pin - Uint16 GPIO4:1; // 4 Output Clear bit for this pin - Uint16 GPIO5:1; // 5 Output Clear bit for this pin - Uint16 GPIO6:1; // 6 Output Clear bit for this pin - Uint16 GPIO7:1; // 7 Output Clear bit for this pin - Uint16 GPIO8:1; // 8 Output Clear bit for this pin - Uint16 GPIO9:1; // 9 Output Clear bit for this pin - Uint16 GPIO10:1; // 10 Output Clear bit for this pin - Uint16 GPIO11:1; // 11 Output Clear bit for this pin - Uint16 GPIO12:1; // 12 Output Clear bit for this pin - Uint16 GPIO13:1; // 13 Output Clear bit for this pin - Uint16 GPIO14:1; // 14 Output Clear bit for this pin - Uint16 GPIO15:1; // 15 Output Clear bit for this pin - Uint16 GPIO16:1; // 16 Output Clear bit for this pin - Uint16 GPIO17:1; // 17 Output Clear bit for this pin - Uint16 GPIO18:1; // 18 Output Clear bit for this pin - Uint16 GPIO19:1; // 19 Output Clear bit for this pin - Uint16 GPIO20:1; // 20 Output Clear bit for this pin - Uint16 GPIO21:1; // 21 Output Clear bit for this pin - Uint16 GPIO22:1; // 22 Output Clear bit for this pin - Uint16 GPIO23:1; // 23 Output Clear bit for this pin - Uint16 GPIO24:1; // 24 Output Clear bit for this pin - Uint16 GPIO25:1; // 25 Output Clear bit for this pin - Uint16 GPIO26:1; // 26 Output Clear bit for this pin - Uint16 GPIO27:1; // 27 Output Clear bit for this pin - Uint16 GPIO28:1; // 28 Output Clear bit for this pin - Uint16 GPIO29:1; // 29 Output Clear bit for this pin - Uint16 GPIO30:1; // 30 Output Clear bit for this pin - Uint16 GPIO31:1; // 31 Output Clear bit for this pin -}; - -union GPACLEAR_REG { - Uint32 all; - struct GPACLEAR_BITS bit; -}; - -struct GPATOGGLE_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Toggle bit for this pin - Uint16 GPIO1:1; // 1 Output Toggle bit for this pin - Uint16 GPIO2:1; // 2 Output Toggle bit for this pin - Uint16 GPIO3:1; // 3 Output Toggle bit for this pin - Uint16 GPIO4:1; // 4 Output Toggle bit for this pin - Uint16 GPIO5:1; // 5 Output Toggle bit for this pin - Uint16 GPIO6:1; // 6 Output Toggle bit for this pin - Uint16 GPIO7:1; // 7 Output Toggle bit for this pin - Uint16 GPIO8:1; // 8 Output Toggle bit for this pin - Uint16 GPIO9:1; // 9 Output Toggle bit for this pin - Uint16 GPIO10:1; // 10 Output Toggle bit for this pin - Uint16 GPIO11:1; // 11 Output Toggle bit for this pin - Uint16 GPIO12:1; // 12 Output Toggle bit for this pin - Uint16 GPIO13:1; // 13 Output Toggle bit for this pin - Uint16 GPIO14:1; // 14 Output Toggle bit for this pin - Uint16 GPIO15:1; // 15 Output Toggle bit for this pin - Uint16 GPIO16:1; // 16 Output Toggle bit for this pin - Uint16 GPIO17:1; // 17 Output Toggle bit for this pin - Uint16 GPIO18:1; // 18 Output Toggle bit for this pin - Uint16 GPIO19:1; // 19 Output Toggle bit for this pin - Uint16 GPIO20:1; // 20 Output Toggle bit for this pin - Uint16 GPIO21:1; // 21 Output Toggle bit for this pin - Uint16 GPIO22:1; // 22 Output Toggle bit for this pin - Uint16 GPIO23:1; // 23 Output Toggle bit for this pin - Uint16 GPIO24:1; // 24 Output Toggle bit for this pin - Uint16 GPIO25:1; // 25 Output Toggle bit for this pin - Uint16 GPIO26:1; // 26 Output Toggle bit for this pin - Uint16 GPIO27:1; // 27 Output Toggle bit for this pin - Uint16 GPIO28:1; // 28 Output Toggle bit for this pin - Uint16 GPIO29:1; // 29 Output Toggle bit for this pin - Uint16 GPIO30:1; // 30 Output Toggle bit for this pin - Uint16 GPIO31:1; // 31 Output Toggle bit for this pin -}; - -union GPATOGGLE_REG { - Uint32 all; - struct GPATOGGLE_BITS bit; -}; - -struct GPBDAT_BITS { // bits description - Uint16 GPIO32:1; // 0 Data Register for this pin - Uint16 GPIO33:1; // 1 Data Register for this pin - Uint16 GPIO34:1; // 2 Data Register for this pin - Uint16 GPIO35:1; // 3 Data Register for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Data Register for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Data Register for this pin - Uint16 GPIO40:1; // 8 Data Register for this pin - Uint16 GPIO41:1; // 9 Data Register for this pin - Uint16 GPIO42:1; // 10 Data Register for this pin - Uint16 GPIO43:1; // 11 Data Register for this pin - Uint16 GPIO44:1; // 12 Data Register for this pin - Uint16 GPIO45:1; // 13 Data Register for this pin - Uint16 GPIO46:1; // 14 Data Register for this pin - Uint16 GPIO47:1; // 15 Data Register for this pin - Uint16 GPIO48:1; // 16 Data Register for this pin - Uint16 GPIO49:1; // 17 Data Register for this pin - Uint16 GPIO50:1; // 18 Data Register for this pin - Uint16 GPIO51:1; // 19 Data Register for this pin - Uint16 GPIO52:1; // 20 Data Register for this pin - Uint16 GPIO53:1; // 21 Data Register for this pin - Uint16 GPIO54:1; // 22 Data Register for this pin - Uint16 GPIO55:1; // 23 Data Register for this pin - Uint16 GPIO56:1; // 24 Data Register for this pin - Uint16 GPIO57:1; // 25 Data Register for this pin - Uint16 GPIO58:1; // 26 Data Register for this pin - Uint16 GPIO59:1; // 27 Data Register for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBDAT_REG { - Uint32 all; - struct GPBDAT_BITS bit; -}; - -struct GPBSET_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Set bit for this pin - Uint16 GPIO33:1; // 1 Output Set bit for this pin - Uint16 GPIO34:1; // 2 Output Set bit for this pin - Uint16 GPIO35:1; // 3 Output Set bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Set bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Set bit for this pin - Uint16 GPIO40:1; // 8 Output Set bit for this pin - Uint16 GPIO41:1; // 9 Output Set bit for this pin - Uint16 GPIO42:1; // 10 Output Set bit for this pin - Uint16 GPIO43:1; // 11 Output Set bit for this pin - Uint16 GPIO44:1; // 12 Output Set bit for this pin - Uint16 GPIO45:1; // 13 Output Set bit for this pin - Uint16 GPIO46:1; // 14 Output Set bit for this pin - Uint16 GPIO47:1; // 15 Output Set bit for this pin - Uint16 GPIO48:1; // 16 Output Set bit for this pin - Uint16 GPIO49:1; // 17 Output Set bit for this pin - Uint16 GPIO50:1; // 18 Output Set bit for this pin - Uint16 GPIO51:1; // 19 Output Set bit for this pin - Uint16 GPIO52:1; // 20 Output Set bit for this pin - Uint16 GPIO53:1; // 21 Output Set bit for this pin - Uint16 GPIO54:1; // 22 Output Set bit for this pin - Uint16 GPIO55:1; // 23 Output Set bit for this pin - Uint16 GPIO56:1; // 24 Output Set bit for this pin - Uint16 GPIO57:1; // 25 Output Set bit for this pin - Uint16 GPIO58:1; // 26 Output Set bit for this pin - Uint16 GPIO59:1; // 27 Output Set bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBSET_REG { - Uint32 all; - struct GPBSET_BITS bit; -}; - -struct GPBCLEAR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Clear bit for this pin - Uint16 GPIO33:1; // 1 Output Clear bit for this pin - Uint16 GPIO34:1; // 2 Output Clear bit for this pin - Uint16 GPIO35:1; // 3 Output Clear bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Clear bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Clear bit for this pin - Uint16 GPIO40:1; // 8 Output Clear bit for this pin - Uint16 GPIO41:1; // 9 Output Clear bit for this pin - Uint16 GPIO42:1; // 10 Output Clear bit for this pin - Uint16 GPIO43:1; // 11 Output Clear bit for this pin - Uint16 GPIO44:1; // 12 Output Clear bit for this pin - Uint16 GPIO45:1; // 13 Output Clear bit for this pin - Uint16 GPIO46:1; // 14 Output Clear bit for this pin - Uint16 GPIO47:1; // 15 Output Clear bit for this pin - Uint16 GPIO48:1; // 16 Output Clear bit for this pin - Uint16 GPIO49:1; // 17 Output Clear bit for this pin - Uint16 GPIO50:1; // 18 Output Clear bit for this pin - Uint16 GPIO51:1; // 19 Output Clear bit for this pin - Uint16 GPIO52:1; // 20 Output Clear bit for this pin - Uint16 GPIO53:1; // 21 Output Clear bit for this pin - Uint16 GPIO54:1; // 22 Output Clear bit for this pin - Uint16 GPIO55:1; // 23 Output Clear bit for this pin - Uint16 GPIO56:1; // 24 Output Clear bit for this pin - Uint16 GPIO57:1; // 25 Output Clear bit for this pin - Uint16 GPIO58:1; // 26 Output Clear bit for this pin - Uint16 GPIO59:1; // 27 Output Clear bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBCLEAR_REG { - Uint32 all; - struct GPBCLEAR_BITS bit; -}; - -struct GPBTOGGLE_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Toggle bit for this pin - Uint16 GPIO33:1; // 1 Output Toggle bit for this pin - Uint16 GPIO34:1; // 2 Output Toggle bit for this pin - Uint16 GPIO35:1; // 3 Output Toggle bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Toggle bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Toggle bit for this pin - Uint16 GPIO40:1; // 8 Output Toggle bit for this pin - Uint16 GPIO41:1; // 9 Output Toggle bit for this pin - Uint16 GPIO42:1; // 10 Output Toggle bit for this pin - Uint16 GPIO43:1; // 11 Output Toggle bit for this pin - Uint16 GPIO44:1; // 12 Output Toggle bit for this pin - Uint16 GPIO45:1; // 13 Output Toggle bit for this pin - Uint16 GPIO46:1; // 14 Output Toggle bit for this pin - Uint16 GPIO47:1; // 15 Output Toggle bit for this pin - Uint16 GPIO48:1; // 16 Output Toggle bit for this pin - Uint16 GPIO49:1; // 17 Output Toggle bit for this pin - Uint16 GPIO50:1; // 18 Output Toggle bit for this pin - Uint16 GPIO51:1; // 19 Output Toggle bit for this pin - Uint16 GPIO52:1; // 20 Output Toggle bit for this pin - Uint16 GPIO53:1; // 21 Output Toggle bit for this pin - Uint16 GPIO54:1; // 22 Output Toggle bit for this pin - Uint16 GPIO55:1; // 23 Output Toggle bit for this pin - Uint16 GPIO56:1; // 24 Output Toggle bit for this pin - Uint16 GPIO57:1; // 25 Output Toggle bit for this pin - Uint16 GPIO58:1; // 26 Output Toggle bit for this pin - Uint16 GPIO59:1; // 27 Output Toggle bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBTOGGLE_REG { - Uint32 all; - struct GPBTOGGLE_BITS bit; -}; - -struct GPHDAT_BITS { // bits description - Uint16 GPIO224:1; // 0 Data Register for this pin - Uint16 GPIO225:1; // 1 Data Register for this pin - Uint16 GPIO226:1; // 2 Data Register for this pin - Uint16 GPIO227:1; // 3 Data Register for this pin - Uint16 GPIO228:1; // 4 Data Register for this pin - Uint16 GPIO229:1; // 5 Data Register for this pin - Uint16 GPIO230:1; // 6 Data Register for this pin - Uint16 GPIO231:1; // 7 Data Register for this pin - Uint16 GPIO232:1; // 8 Data Register for this pin - Uint16 GPIO233:1; // 9 Data Register for this pin - Uint16 GPIO234:1; // 10 Data Register for this pin - Uint16 GPIO235:1; // 11 Data Register for this pin - Uint16 GPIO236:1; // 12 Data Register for this pin - Uint16 GPIO237:1; // 13 Data Register for this pin - Uint16 GPIO238:1; // 14 Data Register for this pin - Uint16 GPIO239:1; // 15 Data Register for this pin - Uint16 GPIO240:1; // 16 Data Register for this pin - Uint16 GPIO241:1; // 17 Data Register for this pin - Uint16 GPIO242:1; // 18 Data Register for this pin - Uint16 GPIO243:1; // 19 Data Register for this pin - Uint16 GPIO244:1; // 20 Data Register for this pin - Uint16 GPIO245:1; // 21 Data Register for this pin - Uint16 GPIO246:1; // 22 Data Register for this pin - Uint16 GPIO247:1; // 23 Data Register for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHDAT_REG { - Uint32 all; - struct GPHDAT_BITS bit; -}; - -struct GPIO_DATA_REGS { - union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to GPIO31) - union GPASET_REG GPASET; // GPIO A Output Set (GPIO0 to GPIO31) - union GPACLEAR_REG GPACLEAR; // GPIO A Output Clear (GPIO0 to GPIO31) - union GPATOGGLE_REG GPATOGGLE; // GPIO A Output Toggle (GPIO0 to GPIO31) - union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to GPIO64) - union GPBSET_REG GPBSET; // GPIO B Output Set (GPIO32 to GPIO64) - union GPBCLEAR_REG GPBCLEAR; // GPIO B Output Clear (GPIO32 to GPIO64) - union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Output Toggle (GPIO32 to GPIO64) - Uint16 rsvd1[40]; // Reserved - union GPHDAT_REG GPHDAT; // GPIO H Data Register (GPIO0 to GPIO255) - Uint16 rsvd2[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// GPIO External References & Function Declarations: -// -extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; -extern volatile struct GPIO_DATA_REGS GpioDataRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h deleted file mode 100644 index ee13416..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h +++ /dev/null @@ -1,251 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_i2c.h -// -// TITLE: I2C Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_I2C_H__ -#define __F28004X_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// I2C Individual Register Bit Definitions: - -struct I2COAR_BITS { // bits description - Uint16 OAR:10; // 9:0 I2C Own address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2COAR_REG { - Uint16 all; - struct I2COAR_BITS bit; -}; - -struct I2CIER_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable - Uint16 NACK:1; // 1 No-acknowledgment interrupt enable - Uint16 ARDY:1; // 2 Register-access-ready interrupt enable - Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable - Uint16 SCD:1; // 5 Stop condition detected interrupt enable - Uint16 AAS:1; // 6 Addressed as slave interrupt enable - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union I2CIER_REG { - Uint16 all; - struct I2CIER_BITS bit; -}; - -struct I2CSTR_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit - Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. - Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit - Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. - Uint16 SCD:1; // 5 Stop condition detected bit. - Uint16 BYTESENT:1; // 6 Byte transmit over indication - Uint16 rsvd1:1; // 7 Reserved - Uint16 AD0:1; // 8 Address 0 bits - Uint16 AAS:1; // 9 Addressed-as-slave bit - Uint16 XSMT:1; // 10 Transmit shift register empty bit. - Uint16 RSFULL:1; // 11 Receive shift register full bit. - Uint16 BB:1; // 12 Bus busy bit. - Uint16 NACKSNT:1; // 13 NACK sent bit. - Uint16 SDIR:1; // 14 Slave direction bit - Uint16 rsvd2:1; // 15 Reserved -}; - -union I2CSTR_REG { - Uint16 all; - struct I2CSTR_BITS bit; -}; - -struct I2CDRR_BITS { // bits description - Uint16 DATA:8; // 7:0 Receive data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDRR_REG { - Uint16 all; - struct I2CDRR_BITS bit; -}; - -struct I2CSAR_BITS { // bits description - Uint16 SAR:10; // 9:0 Slave Address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2CSAR_REG { - Uint16 all; - struct I2CSAR_BITS bit; -}; - -struct I2CDXR_BITS { // bits description - Uint16 DATA:8; // 7:0 Transmit data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDXR_REG { - Uint16 all; - struct I2CDXR_BITS bit; -}; - -struct I2CMDR_BITS { // bits description - Uint16 BC:3; // 2:0 Bit count bits. - Uint16 FDF:1; // 3 Free Data Format - Uint16 STB:1; // 4 START Byte Mode - Uint16 IRS:1; // 5 I2C Module Reset - Uint16 DLB:1; // 6 Digital Loopback Mode - Uint16 RM:1; // 7 Repeat Mode - Uint16 XA:1; // 8 Expanded Address Mode - Uint16 TRX:1; // 9 Transmitter Mode - Uint16 MST:1; // 10 Master Mode - Uint16 STP:1; // 11 STOP Condition - Uint16 rsvd1:1; // 12 Reserved - Uint16 STT:1; // 13 START condition bit - Uint16 FREE:1; // 14 Debug Action - Uint16 NACKMOD:1; // 15 NACK mode bit -}; - -union I2CMDR_REG { - Uint16 all; - struct I2CMDR_BITS bit; -}; - -struct I2CISRC_BITS { // bits description - Uint16 INTCODE:3; // 2:0 Interrupt code bits. - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 WRITE_ZEROS:4; // 11:8 Always write all 0s to this field - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union I2CISRC_REG { - Uint16 all; - struct I2CISRC_BITS bit; -}; - -struct I2CEMDR_BITS { // bits description - Uint16 BC:1; // 0 Backwards compatibility mode - Uint16 FCM:1; // 1 Forward Compatibility for Tx behav in Type1 - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union I2CEMDR_REG { - Uint16 all; - struct I2CEMDR_BITS bit; -}; - -struct I2CPSC_BITS { // bits description - Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CPSC_REG { - Uint16 all; - struct I2CPSC_BITS bit; -}; - -struct I2CFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear - Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFFRST:1; // 13 Transmit FIFO Reset - Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable - Uint16 rsvd1:1; // 15 Reserved -}; - -union I2CFFTX_REG { - Uint16 all; - struct I2CFFTX_BITS bit; -}; - -struct I2CFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear - Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFFRST:1; // 13 Receive FIFO Reset - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union I2CFFRX_REG { - Uint16 all; - struct I2CFFRX_BITS bit; -}; - -struct I2C_REGS { - union I2COAR_REG I2COAR; // I2C Own address - union I2CIER_REG I2CIER; // I2C Interrupt Enable - union I2CSTR_REG I2CSTR; // I2C Status - Uint16 I2CCLKL; // I2C Clock low-time divider - Uint16 I2CCLKH; // I2C Clock high-time divider - Uint16 I2CCNT; // I2C Data count - union I2CDRR_REG I2CDRR; // I2C Data receive - union I2CSAR_REG I2CSAR; // I2C Slave address - union I2CDXR_REG I2CDXR; // I2C Data Transmit - union I2CMDR_REG I2CMDR; // I2C Mode - union I2CISRC_REG I2CISRC; // I2C Interrupt Source - union I2CEMDR_REG I2CEMDR; // I2C Extended Mode - union I2CPSC_REG I2CPSC; // I2C Prescaler - Uint16 rsvd1[19]; // Reserved - union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit - union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive -}; - -//--------------------------------------------------------------------------- -// I2C External References & Function Declarations: -// -extern volatile struct I2C_REGS I2caRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h deleted file mode 100644 index 856c66a..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h +++ /dev/null @@ -1,112 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_input_xbar.h -// -// TITLE: INPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_INPUT_XBAR_H__ -#define __F28004X_INPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// INPUT_XBAR Individual Register Bit Definitions: - -struct INPUTSELECTLOCK_BITS { // bits description - Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register - Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register - Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register - Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register - Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register - Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register - Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register - Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register - Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register - Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register - Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register - Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register - Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register - Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register - Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register - Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union INPUTSELECTLOCK_REG { - Uint32 all; - struct INPUTSELECTLOCK_BITS bit; -}; - -struct INPUT_XBAR_REGS { - Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) - Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) - Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) - Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) - Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) - Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) - Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) - Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) - Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) - Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) - Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) - Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) - Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) - Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) - Uint16 INPUT15SELECT; // INPUT15 Input Select Register (GPIO0 to x) - Uint16 INPUT16SELECT; // INPUT16 Input Select Register (GPIO0 to x) - Uint16 rsvd1[14]; // Reserved - union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register -}; - -//--------------------------------------------------------------------------- -// INPUT_XBAR External References & Function Declarations: -// -extern volatile struct INPUT_XBAR_REGS InputXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h deleted file mode 100644 index 88e1971..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h +++ /dev/null @@ -1,576 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_lin.h -// -// TITLE: LIN Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_LIN_H__ -#define __F28004X_LIN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// LIN Individual Register Bit Definitions: - -struct SCIGCR0_BITS { // bits description - bp_16 RESET:1; // 0 LIN Module reset bit - bp_16 rsvd1:15; // 15:1 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIGCR0_REG { - bp_32 all; - struct SCIGCR0_BITS bit; -}; - -struct SCIGCR1_BITS { // bits description - bp_16 COMMMODE:1; // 0 SCI/LIN communications mode bit - bp_16 TIMINGMODE:1; // 1 SCI timing mode bit. Should be set to 1 for SCI mode. - bp_16 PARITYENA:1; // 2 Parity enable - bp_16 PARITY:1; // 3 SCI parity odd/even selection - bp_16 STOP:1; // 4 SCI number of stop bits - bp_16 CLK_MASTER:1; // 5 LIN Master/Slave selection and SCI clock enable - bp_16 LINMODE:1; // 6 LIN Mode enable/disable - bp_16 SWnRST:1; // 7 Software reset - bp_16 SLEEP:1; // 8 SCI sleep (SCI compatibility mode) - bp_16 ADAPT:1; // 9 Automatic baudrate adjustment control(LIN mode) - bp_16 MBUFMODE:1; // 10 Multi-buffer mode - bp_16 CTYPE:1; // 11 Checksum type (LIN mode) - bp_16 HGENCTRL:1; // 12 Mask filtering comparison control (LIN mode) - bp_16 STOPEXTFRAME:1; // 13 Stop extended frame communication (LIN mode) - bp_16 rsvd1:2; // 15:14 Reserved - bp_32 LOOPBACK:1; // 16 Digital loopback mode - bp_32 CONT:1; // 17 Continue on suspend - bp_32 rsvd2:6; // 23:18 Reserved - bp_32 RXENA:1; // 24 SCI mode receiver enable - bp_32 TXENA:1; // 25 SCI mode transmitter enable - bp_32 rsvd3:6; // 31:26 Reserved -}; - -union SCIGCR1_REG { - bp_32 all; - struct SCIGCR1_BITS bit; -}; - -struct SCIGCR2_BITS { // bits description - bp_16 POWERDOWN:1; // 0 Low-power mode PowerDown bit - bp_16 rsvd1:7; // 7:1 Reserved - bp_16 GENWU:1; // 8 Generate Wakeup - bp_16 rsvd2:7; // 15:9 Reserved - bp_32 SC:1; // 16 Send Checksum (LIN mode) - bp_32 CC:1; // 17 Compare Checksum (LIN mode) - bp_32 rsvd3:14; // 31:18 Reserved -}; - -union SCIGCR2_REG { - bp_32 all; - struct SCIGCR2_BITS bit; -}; - -struct SCISETINT_BITS { // bits description - bp_16 SETBRKDTINT:1; // 0 Set Break-detect Interrupt (SCI compatible mode) - bp_16 SETWAKEUPINT:1; // 1 Set Wake-up Interrupt - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 SETTIMEOUTINT:1; // 4 Set Timeout Interrupt (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 SETTOAWUSINT:1; // 6 Set Timeout After Wakeup Signal Interrupt (LIN only) - bp_16 SETTOA3WUSINT:1; // 7 Set Timeout After 3 Wakeup Signals Interrupt (LIN only) - bp_16 SETTXINT:1; // 8 Set Transmitter Interrupt - bp_16 SETRXINT:1; // 9 Receiver Interrupt Enable - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 SETIDINT:1; // 13 Set Identifier Interrupt (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 SETPEINT:1; // 24 Set Parity Interrupt - bp_32 SETOEINT:1; // 25 Set Overrun-Error Interrupt - bp_32 SETFEINT:1; // 26 Set Framing-Error Interrupt - bp_32 SETNREINT:1; // 27 Set No-Response-Error Interrupt (LIN only) - bp_32 SETISFEINT:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt (LIN only) - bp_32 SETCEINT:1; // 29 Set Checksum-error Interrupt (LIN only) - bp_32 SETPBEINT:1; // 30 Set Physical Bus Error Interrupt (LIN only) - bp_32 SETBEINT:1; // 31 Set Bit Error Interrupt (LIN only) -}; - -union SCISETINT_REG { - bp_32 all; - struct SCISETINT_BITS bit; -}; - -struct SCICLEARINT_BITS { // bits description - bp_16 CLRBRKDTINT:1; // 0 Clear Break-detect Interrupt (SCI compatible mode - bp_16 CLRWAKEUPINT:1; // 1 Clear Wake-up Interrupt - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 CLRTIMEOUTINT:1; // 4 Clear Timeout Interrupt (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 CLRTOAWUSINT:1; // 6 Clear Timeout After Wakeup Signal Interrupt (LIN only) - bp_16 CLRTOA3WUSINT:1; // 7 Clear Timeout After 3 Wakeup Signals Interrupt (LIN only) - bp_16 CLRTXINT:1; // 8 Clear Transmitter Interrupt - bp_16 CLRRXINT:1; // 9 Clear Receiver Interrupt - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 CLRIDINT:1; // 13 Clear Identifier Interrupt (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 CLRPEINT:1; // 24 Clear Parity Interrupt - bp_32 CLROEINT:1; // 25 Clear Overrun-Error Interrupt - bp_32 CLRFEINT:1; // 26 Clear Framing-Error Interrupt - bp_32 CLRNREINT:1; // 27 Clear No-Response-Error Interrupt (LIN only) - bp_32 CLRISFEINT:1; // 28 Clear Inconsistent-Synch-Field-Error Interrupt (LIN only) - bp_32 CLRCEINT:1; // 29 Clear Checksum-error Interrupt (LIN only) - bp_32 CLRPBEINT:1; // 30 Clear Physical Bus Error Interrupt (LIN only) - bp_32 CLRBEINT:1; // 31 Clear Bit Error Interrupt (LIN only) -}; - -union SCICLEARINT_REG { - bp_32 all; - struct SCICLEARINT_BITS bit; -}; - -struct SCISETINTLVL_BITS { // bits description - bp_16 SETBRKDTINTLVL:1; // 0 Set Break-detect Interrupt Level (SCI compatible mode) - bp_16 SETWAKEUPINTLVL:1; // 1 Set Wake-up Interrupt Level - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 SETTIMEOUTINTLVL:1; // 4 Set Timeout Interrupt Level (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 SETTOAWUSINTLVL:1; // 6 Set Timeout After Wakeup Signal Interrupt Level (LIN only) - bp_16 SETTOA3WUSINTLVL:1; // 7 Set Timeout After 3 Wakeup Signals - bp_16 SETTXINTLVL:1; // 8 Set Transmitter Interrupt Level - bp_16 SETRXINTOVO:1; // 9 Receiver Interrupt Enable Level - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 SETIDINTLVL:1; // 13 Set Identifier Interrupt Level (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 SETPEINTLVL:1; // 24 Set Parity Interrupt Level - bp_32 SETOEINTLVL:1; // 25 Set Overrun-Error Interrupt Level - bp_32 SETFEINTLVL:1; // 26 Set Framing-Error Interrupt Level - bp_32 SETNREINTLVL:1; // 27 Set No-Response-Error Interrupt Level (LIN only) - bp_32 SETISFEINTLVL:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt Level - bp_32 SETCEINTLVL:1; // 29 Set Checksum-error Interrupt Level (LIN only) - bp_32 SETPBEINTLVL:1; // 30 Set Physical Bus Error Interrupt Level (LIN only) - bp_32 SETBEINTLVL:1; // 31 Set Bit Error Interrupt Level(LIN only) -}; - -union SCISETINTLVL_REG { - bp_32 all; - struct SCISETINTLVL_BITS bit; -}; - -struct SCICLEARINTLVL_BITS { // bits description - bp_16 CLRBRKDTINTLVL:1; // 0 Clear Break-detect Interrupt Level (SCI compatible mode) - bp_16 CLRWAKEUPINTLVL:1; // 1 Clear Wake-up Interrupt Level - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 CLRTIMEOUTINTLVL:1; // 4 Clear Timeout Interrupt Level (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 CLRTOAWUSINTLVL:1; // 6 Clear Timeout After Wakeup Signal Interrupt Level (LIN only) - bp_16 CLRTOA3WUSINTLVL:1; // 7 Clear Timeout After 3 Wakeup Signals - bp_16 CLRTXINTLVL:1; // 8 Clear Transmitter Interrupt Level - bp_16 CLRRXINTLVL:1; // 9 Clear Receiver interrupt Level. - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 CLRIDINTLVL:1; // 13 Clear Identifier Interrupt Level (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 CLRPEINTLVL:1; // 24 Clear Parity Interrupt Level - bp_32 CLROEINTLVL:1; // 25 Clear Overrun-Error Interrupt Level - bp_32 CLRFEINTLVL:1; // 26 Clear Framing-Error Interrupt Level - bp_32 CLRNREINTLVL:1; // 27 Clear No-Response-Error Interrupt Level (LIN only) - bp_32 CLRISFEINTLVL:1; // 28 Clear Inconsistent-Synch-Field-Error - bp_32 CLRCEINTLVL:1; // 29 Clear Checksum-error Interrupt Level (LIN only) - bp_32 CLRPBEINTLVL:1; // 30 Clear Physical Bus Error Interrupt Level (LIN only) - bp_32 CLRBEINTLVL:1; // 31 Clear Bit Error Interrupt Level (LIN only) -}; - -union SCICLEARINTLVL_REG { - bp_32 all; - struct SCICLEARINTLVL_BITS bit; -}; - -struct SCIFLR_BITS { // bits description - bp_16 BRKDT:1; // 0 Break-detect Flag (SCI compatible mode) - bp_16 WAKEUP:1; // 1 Wake-up Flag - bp_16 IDLE:1; // 2 SCI receiver in idle state (SCI compatible mode) - bp_16 BUSY:1; // 3 Busy Flag - bp_16 TIMEOUT:1; // 4 LIN Bus IDLE timeout Flag (LIN only) - bp_16 rsvd1:1; // 5 Reserved - bp_16 TOAWUS:1; // 6 Timeout After Wakeup Signal Flag (LIN only) - bp_16 TOA3WUS:1; // 7 Timeout After 3 Wakeup Signals Flag (LIN only) - bp_16 TXRDY:1; // 8 Transmitter Buffer Ready Flag - bp_16 RXRDY:1; // 9 Receiver Buffer Ready Flag - bp_16 TXWAKE:1; // 10 SCI Transmitter Wakeup Method Select - bp_16 TXEMPTY:1; // 11 Transmitter Empty Clag - bp_16 RXWAKE:1; // 12 Receiver Wakeup Detect Flag - bp_16 IDTXFLAG:1; // 13 Identifier On Transmit Flag (LIN only) - bp_16 IDRXFLAG:1; // 14 Identifier on Receive Flag - bp_16 rsvd2:1; // 15 Reserved - bp_32 rsvd3:8; // 23:16 Reserved - bp_32 PE:1; // 24 Parity Error Flag - bp_32 OE:1; // 25 Overrun Error Flag - bp_32 FE:1; // 26 Framing Error Flag - bp_32 NRE:1; // 27 No-Response Error Flag (LIN only) - bp_32 ISFE:1; // 28 Inconsistent Synch Field Error Flag (LIN only) - bp_32 CE:1; // 29 Checksum Error Flag (LIN only) - bp_32 PBE:1; // 30 Physical Bus Error Flag (LIN only) - bp_32 BE:1; // 31 Bit Error Flag (LIN only) -}; - -union SCIFLR_REG { - bp_32 all; - struct SCIFLR_BITS bit; -}; - -struct SCIINTVECT0_BITS { // bits description - bp_16 INTVECT0:5; // 4:0 LIN Module reset bit - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIINTVECT0_REG { - bp_32 all; - struct SCIINTVECT0_BITS bit; -}; - -struct SCIINTVECT1_BITS { // bits description - bp_16 INTVECT1:5; // 4:0 LIN Module reset bit - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIINTVECT1_REG { - bp_32 all; - struct SCIINTVECT1_BITS bit; -}; - -struct SCIFORMAT_BITS { // bits description - bp_16 CHAR:5; // 4:0 Character Length Control Bits - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 LENGTH:3; // 18:16 Frame Length Control Bits - bp_32 rsvd2:13; // 31:19 Reserved -}; - -union SCIFORMAT_REG { - bp_32 all; - struct SCIFORMAT_BITS bit; -}; - -struct BRSR_BITS { // bits description - bp_16 SCI_LIN_PSL:16; // 15:0 Character Length Control Bits - bp_32 SCI_LIN_PSH:8; // 23:16 24-Bit Integer Prescaler Select - bp_32 M:4; // 27:24 Frame Length Control Bits - bp_32 rsvd1:4; // 31:28 Reserved -}; - -union BRSR_REG { - bp_32 all; - struct BRSR_BITS bit; -}; - -struct SCIED_BITS { // bits description - bp_16 ED:8; // 7:0 Receiver Emulation Data. - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIED_REG { - bp_32 all; - struct SCIED_BITS bit; -}; - -struct SCIRD_BITS { // bits description - bp_16 RD:8; // 7:0 Received Data. - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIRD_REG { - bp_32 all; - struct SCIRD_BITS bit; -}; - -struct SCITD_BITS { // bits description - bp_16 TD:8; // 7:0 Transmit data - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCITD_REG { - bp_32 all; - struct SCITD_BITS bit; -}; - -struct SCIPIO0_BITS { // bits description - bp_16 rsvd1:1; // 0 Reserved - bp_16 RXFUNC:1; // 1 LINRX pin function - bp_16 TXFUNC:1; // 2 LINTX pin function - bp_16 rsvd2:13; // 15:3 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union SCIPIO0_REG { - bp_32 all; - struct SCIPIO0_BITS bit; -}; - -struct SCIPIO2_BITS { // bits description - bp_16 rsvd1:1; // 0 Reserved - bp_16 RXIN:1; // 1 SCIRX pin value - bp_16 TXIN:1; // 2 SCITX pin value - bp_16 rsvd2:13; // 15:3 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union SCIPIO2_REG { - bp_32 all; - struct SCIPIO2_BITS bit; -}; - -struct LINCOMP_BITS { // bits description - bp_16 SBREAK:3; // 2:0 Synch Break Extend - bp_16 rsvd1:5; // 7:3 Reserved - bp_16 SDEL:2; // 9:8 Sync Delimiter Compare - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union LINCOMP_REG { - bp_32 all; - struct LINCOMP_BITS bit; -}; - -struct LINRD0_BITS { // bits description - bp_16 RD3:8; // 7:0 Receive Buffer 3 - bp_16 RD2:8; // 15:8 Receive Buffer 2 - bp_32 RD1:8; // 23:16 Receive Buffer 1 - bp_32 RD0:8; // 31:24 Receive Buffer 0 -}; - -union LINRD0_REG { - bp_32 all; - struct LINRD0_BITS bit; -}; - -struct LINRD1_BITS { // bits description - bp_16 RD7:8; // 7:0 Receive Buffer 3 - bp_16 RD6:8; // 15:8 Receive Buffer 2 - bp_32 RD5:8; // 23:16 Receive Buffer 1 - bp_32 RD4:8; // 31:24 Receive Buffer 0 -}; - -union LINRD1_REG { - bp_32 all; - struct LINRD1_BITS bit; -}; - -struct LINMASK_BITS { // bits description - bp_16 TXIDMASK:8; // 7:0 TX ID Mask bits (LIN only) - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 RXIDMASK:8; // 23:16 RX ID Mask bits (LIN only) - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union LINMASK_REG { - bp_32 all; - struct LINMASK_BITS bit; -}; - -struct LINID_BITS { // bits description - bp_16 IDBYTE:8; // 7:0 LIN message ID (LIN only) - bp_16 IDSLAVETASKBYTE:8; // 15:8 Received ID comparison ID (LIN only) - bp_32 RECEIVEDID:8; // 23:16 Current Message ID (LIN only) - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union LINID_REG { - bp_32 all; - struct LINID_BITS bit; -}; - -struct LINTD0_BITS { // bits description - bp_16 TD3:8; // 7:0 TRANSMIT Buffer 3 - bp_16 TD2:8; // 15:8 TRANSMIT Buffer 2 - bp_32 TD1:8; // 23:16 TRANSMIT Buffer 1 - bp_32 TD0:8; // 31:24 TRANSMIT Buffer 0 -}; - -union LINTD0_REG { - bp_32 all; - struct LINTD0_BITS bit; -}; - -struct LINTD1_BITS { // bits description - bp_16 TD7:8; // 7:0 TRANSMIT Buffer 7 - bp_16 TD6:8; // 15:8 TRANSMIT Buffer 6 - bp_32 TD5:8; // 23:16 TRANSMIT Buffer 5 - bp_32 TD4:8; // 31:24 TRANSMIT Buffer 4 -}; - -union LINTD1_REG { - bp_32 all; - struct LINTD1_BITS bit; -}; - -struct MBRSR_BITS { // bits description - bp_16 MBR:13; // 12:0 Received Data. - bp_16 rsvd1:3; // 15:13 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union MBRSR_REG { - bp_32 all; - struct MBRSR_BITS bit; -}; - -struct IODFTCTRL_BITS { // bits description - bp_16 RXPENA:1; // 0 Analog Loopback Via Receive Pin Enable - bp_16 LPBENA:1; // 1 Module Loopback Enable - bp_16 rsvd1:6; // 7:2 Reserved - bp_16 IODFTENA:4; // 11:8 IO DFT Enable Key - bp_16 rsvd2:4; // 15:12 Reserved - bp_32 TXSHIFT:3; // 18:16 Transmit Delay Shift - bp_32 PINSAMPLEMASK:2; // 20:19 TX Pin Sample Mask - bp_32 rsvd3:3; // 23:21 Reserved - bp_32 BRKDTERRENA:1; // 24 Break Detect Error Enable (SCI compatibility mode) - bp_32 PERRENA:1; // 25 Parity Error Enable (SCI compatibility mode) - bp_32 FERRENA:1; // 26 Frame Error Enable (SCI compatibility mode) - bp_32 rsvd4:1; // 27 Reserved - bp_32 ISFERRENA:1; // 28 Inconsistent Synch Field Error Enable (LIN mode) - bp_32 CERRENA:1; // 29 Checksum Error Enable(LIN mode) - bp_32 PBERRENA:1; // 30 Physical Bus Error Enable (LIN mode) - bp_32 BERRENA:1; // 31 Bit Error Enable (LIN mode) -}; - -union IODFTCTRL_REG { - bp_32 all; - struct IODFTCTRL_BITS bit; -}; - -struct LIN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for LIN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_EN_REG { - bp_32 all; - struct LIN_GLB_INT_EN_BITS bit; -}; - -struct LIN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for LIN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_FLG_REG { - bp_32 all; - struct LIN_GLB_INT_FLG_BITS bit; -}; - -struct LIN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for LIN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_CLR_REG { - bp_32 all; - struct LIN_GLB_INT_CLR_BITS bit; -}; - -struct LIN_REGS { - union SCIGCR0_REG SCIGCR0; // Global Control Register 0 - union SCIGCR1_REG SCIGCR1; // Global Control Register 1 - union SCIGCR2_REG SCIGCR2; // Global Control Register 2 - union SCISETINT_REG SCISETINT; // Interrupt Enable Register - union SCICLEARINT_REG SCICLEARINT; // Interrupt Disable Register - union SCISETINTLVL_REG SCISETINTLVL; // Set Interrupt Level Register - union SCICLEARINTLVL_REG SCICLEARINTLVL; // Clear Interrupt Level Register - union SCIFLR_REG SCIFLR; // Flag Register - union SCIINTVECT0_REG SCIINTVECT0; // Interrupt Vector Offset Register 0 - union SCIINTVECT1_REG SCIINTVECT1; // Interrupt Vector Offset Register 1 - union SCIFORMAT_REG SCIFORMAT; // Length Control Register - union BRSR_REG BRSR; // Baud Rate Selection Register - union SCIED_REG SCIED; // Emulation buffer Register - union SCIRD_REG SCIRD; // Receiver data buffer Register - union SCITD_REG SCITD; // Transmit data buffer Register - union SCIPIO0_REG SCIPIO0; // Pin control Register 0 - uint32_t rsvd1[2]; // Reserved - union SCIPIO2_REG SCIPIO2; // Pin control Register 2 - uint32_t rsvd2[12]; // Reserved - union LINCOMP_REG LINCOMP; // Compare register - union LINRD0_REG LINRD0; // Receive data register 0 - union LINRD1_REG LINRD1; // Receive data register 1 - union LINMASK_REG LINMASK; // Acceptance mask register - union LINID_REG LINID; // LIN ID Register - union LINTD0_REG LINTD0; // Transmit Data Register 0 - union LINTD1_REG LINTD1; // Transmit Data Register 1 - union MBRSR_REG MBRSR; // Baud Rate Selection Register - uint32_t rsvd3[8]; // Reserved - union IODFTCTRL_REG IODFTCTRL; // IODFT for LIN - uint32_t rsvd4[38]; // Reserved - union LIN_GLB_INT_EN_REG LIN_GLB_INT_EN; // LIN Global Interrupt Enable Register - union LIN_GLB_INT_FLG_REG LIN_GLB_INT_FLG; // LIN Global Interrupt Flag Register - union LIN_GLB_INT_CLR_REG LIN_GLB_INT_CLR; // LIN Global Interrupt Clear Register -}; - -//--------------------------------------------------------------------------- -// LIN External References & Function Declarations: -// -extern volatile struct LIN_REGS LinaRegs; -extern volatile struct LIN_REGS LinbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h deleted file mode 100644 index 7debf52..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h +++ /dev/null @@ -1,867 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_memconfig.h -// -// TITLE: MEMCONFIG Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_MEMCONFIG_H__ -#define __F28004X_MEMCONFIG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// MEMCONFIG Individual Register Bit Definitions: - -struct DxLOCK_BITS { // bits description - Uint16 LOCK_M0:1; // 0 M0 RAM Lock bits - Uint16 LOCK_M1:1; // 1 M1 RAM Lock bits - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxLOCK_REG { - Uint32 all; - struct DxLOCK_BITS bit; -}; - -struct DxCOMMIT_BITS { // bits description - Uint16 COMMIT_M0:1; // 0 M0 RAM Permanent Lock bits - Uint16 COMMIT_M1:1; // 1 M1 RAM Permanent Lock bits - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxCOMMIT_REG { - Uint32 all; - struct DxCOMMIT_BITS bit; -}; - -struct DxTEST_BITS { // bits description - Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM - Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxTEST_REG { - Uint32 all; - struct DxTEST_BITS bit; -}; - -struct DxINIT_BITS { // bits description - Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. - Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxINIT_REG { - Uint32 all; - struct DxINIT_BITS bit; -}; - -struct DxINITDONE_BITS { // bits description - Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. - Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxINITDONE_REG { - Uint32 all; - struct DxINITDONE_BITS bit; -}; - -struct LSxLOCK_BITS { // bits description - Uint16 LOCK_LS0:1; // 0 LS0 RAM Lock bits - Uint16 LOCK_LS1:1; // 1 LS1 RAM Lock bits - Uint16 LOCK_LS2:1; // 2 LS2 RAM Lock bits - Uint16 LOCK_LS3:1; // 3 LS3 RAM Lock bits - Uint16 LOCK_LS4:1; // 4 LS4 RAM Lock bits - Uint16 LOCK_LS5:1; // 5 LS5 RAM Lock bits - Uint16 LOCK_LS6:1; // 6 LS6 RAM Lock bits - Uint16 LOCK_LS7:1; // 7 LS7 RAM Lock bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxLOCK_REG { - Uint32 all; - struct LSxLOCK_BITS bit; -}; - -struct LSxCOMMIT_BITS { // bits description - Uint16 COMMIT_LS0:1; // 0 LS0 RAM Permanent Lock bits - Uint16 COMMIT_LS1:1; // 1 LS1 RAM Permanent Lock bits - Uint16 COMMIT_LS2:1; // 2 LS2 RAM Permanent Lock bits - Uint16 COMMIT_LS3:1; // 3 LS3 RAM Permanent Lock bits - Uint16 COMMIT_LS4:1; // 4 LS4 RAM Permanent Lock bits - Uint16 COMMIT_LS5:1; // 5 LS5 RAM Permanent Lock bits - Uint16 COMMIT_LS6:1; // 6 LS6 RAM Permanent Lock bits - Uint16 COMMIT_LS7:1; // 7 LS7 RAM Permanent Lock bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCOMMIT_REG { - Uint32 all; - struct LSxCOMMIT_BITS bit; -}; - -struct LSxMSEL_BITS { // bits description - Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM - Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM - Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM - Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM - Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM - Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM - Uint16 MSEL_LS6:2; // 13:12 Master Select for LS6 RAM - Uint16 MSEL_LS7:2; // 15:14 Master Select for LS7 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union LSxMSEL_REG { - Uint32 all; - struct LSxMSEL_BITS bit; -}; - -struct LSxCLAPGM_BITS { // bits description - Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS6:1; // 6 Selects LS6 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS7:1; // 7 Selects LS7 RAM as program vs data memory for CLA - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCLAPGM_REG { - Uint32 all; - struct LSxCLAPGM_BITS bit; -}; - -struct LSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM - Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM - Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM - Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM - Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT0_REG { - Uint32 all; - struct LSxACCPROT0_BITS bit; -}; - -struct LSxACCPROT1_BITS { // bits description - Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM - Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM - Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS6:1; // 16 Fetch Protection For LS6 RAM - Uint16 CPUWRPROT_LS6:1; // 17 CPU WR Protection For LS6 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS7:1; // 24 Fetch Protection For LS7 RAM - Uint16 CPUWRPROT_LS7:1; // 25 CPU WR Protection For LS7 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT1_REG { - Uint32 all; - struct LSxACCPROT1_BITS bit; -}; - -struct LSxTEST_BITS { // bits description - Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM - Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM - Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM - Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM - Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM - Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM - Uint16 TEST_LS6:2; // 13:12 Selects the different modes for LS6 RAM - Uint16 TEST_LS7:2; // 15:14 Selects the different modes for LS7 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union LSxTEST_REG { - Uint32 all; - struct LSxTEST_BITS bit; -}; - -struct LSxINIT_BITS { // bits description - Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. - Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. - Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. - Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. - Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. - Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. - Uint16 INIT_LS6:1; // 6 RAM Initialization control for LS6 RAM. - Uint16 INIT_LS7:1; // 7 RAM Initialization control for LS7 RAM. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINIT_REG { - Uint32 all; - struct LSxINIT_BITS bit; -}; - -struct LSxINITDONE_BITS { // bits description - Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. - Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. - Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. - Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. - Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. - Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. - Uint16 INITDONE_LS6:1; // 6 RAM Initialization status for LS6 RAM. - Uint16 INITDONE_LS7:1; // 7 RAM Initialization status for LS7 RAM. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINITDONE_REG { - Uint32 all; - struct LSxINITDONE_BITS bit; -}; - -struct GSxLOCK_BITS { // bits description - Uint16 LOCK_GS0:1; // 0 GS0 RAM Lock bits - Uint16 LOCK_GS1:1; // 1 GS1 RAM Lock bits - Uint16 LOCK_GS2:1; // 2 GS2 RAM Lock bits - Uint16 LOCK_GS3:1; // 3 GS3 RAM Lock bits - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxLOCK_REG { - Uint32 all; - struct GSxLOCK_BITS bit; -}; - -struct GSxCOMMIT_BITS { // bits description - Uint16 COMMIT_GS0:1; // 0 GS0 RAM Permanent Lock bits - Uint16 COMMIT_GS1:1; // 1 GS1 RAM Permanent Lock bits - Uint16 COMMIT_GS2:1; // 2 GS2 RAM Permanent Lock bits - Uint16 COMMIT_GS3:1; // 3 GS3 RAM Permanent Lock bits - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxCOMMIT_REG { - Uint32 all; - struct GSxCOMMIT_BITS bit; -}; - -struct GSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM - Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM - Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM - Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM - Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM - Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM - Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM - Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM - Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT0_REG { - Uint32 all; - struct GSxACCPROT0_BITS bit; -}; - -struct GSxTEST_BITS { // bits description - Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM - Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM - Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM - Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 rsvd2:2; // 11:10 Reserved - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 rsvd4:2; // 15:14 Reserved - Uint16 rsvd5:2; // 17:16 Reserved - Uint16 rsvd6:2; // 19:18 Reserved - Uint16 rsvd7:2; // 21:20 Reserved - Uint16 rsvd8:2; // 23:22 Reserved - Uint16 rsvd9:2; // 25:24 Reserved - Uint16 rsvd10:2; // 27:26 Reserved - Uint16 rsvd11:2; // 29:28 Reserved - Uint16 rsvd12:2; // 31:30 Reserved -}; - -union GSxTEST_REG { - Uint32 all; - struct GSxTEST_BITS bit; -}; - -struct GSxINIT_BITS { // bits description - Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. - Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. - Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. - Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxINIT_REG { - Uint32 all; - struct GSxINIT_BITS bit; -}; - -struct GSxINITDONE_BITS { // bits description - Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. - Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. - Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. - Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxINITDONE_REG { - Uint32 all; - struct GSxINITDONE_BITS bit; -}; - -struct MSGxLOCK_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 LOCK_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM Lock bits - Uint16 LOCK_CLA1TOCPU:1; // 2 CLA1TOCPU RAM Lock bits - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxLOCK_REG { - Uint32 all; - struct MSGxLOCK_BITS bit; -}; - -struct MSGxCOMMIT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 COMMIT_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM control fields COMMIT bit - Uint16 COMMIT_CLA1TOCPU:1; // 2 CLA1TOCPU RAM control fields COMMIT bit - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxCOMMIT_REG { - Uint32 all; - struct MSGxCOMMIT_BITS bit; -}; - -struct MSGxTEST_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select - Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxTEST_REG { - Uint32 all; - struct MSGxTEST_BITS bit; -}; - -struct MSGxINIT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM - Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxINIT_REG { - Uint32 all; - struct MSGxINIT_BITS bit; -}; - -struct MSGxINITDONE_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM - Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxINITDONE_REG { - Uint32 all; - struct MSGxINITDONE_BITS bit; -}; - -struct MEM_CFG_REGS { - union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register - union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register - Uint16 rsvd1[12]; // Reserved - union DxTEST_REG DxTEST; // Dedicated RAM TEST Register - union DxINIT_REG DxINIT; // Dedicated RAM Init Register - union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register - Uint16 rsvd2[10]; // Reserved - union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register - union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register - union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register - union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register - union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 - union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 - Uint16 rsvd3[4]; // Reserved - union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register - union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register - union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register - Uint16 rsvd4[10]; // Reserved - union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register - union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register - Uint16 rsvd5[4]; // Reserved - union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 - Uint16 rsvd6[6]; // Reserved - union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register - union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register - union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register - Uint16 rsvd7[10]; // Reserved - union MSGxLOCK_REG MSGxLOCK; // Message RAM Config Lock Register - union MSGxCOMMIT_REG MSGxCOMMIT; // Message RAM Config Lock Commit Register - Uint16 rsvd8[12]; // Reserved - union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register - union MSGxINIT_REG MSGxINIT; // Message RAM Init Register - union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register - Uint16 rsvd9[10]; // Reserved -}; - -struct NMAVFLG_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVFLG_REG { - Uint32 all; - struct NMAVFLG_BITS bit; -}; - -struct NMAVSET_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVSET_REG { - Uint32 all; - struct NMAVSET_BITS bit; -}; - -struct NMAVCLR_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVCLR_REG { - Uint32 all; - struct NMAVCLR_BITS bit; -}; - -struct NMAVINTEN_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:6; // 15:10 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union NMAVINTEN_REG { - Uint32 all; - struct NMAVINTEN_BITS bit; -}; - -struct MAVFLG_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVFLG_REG { - Uint32 all; - struct MAVFLG_BITS bit; -}; - -struct MAVSET_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVSET_REG { - Uint32 all; - struct MAVSET_BITS bit; -}; - -struct MAVCLR_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVCLR_REG { - Uint32 all; - struct MAVCLR_BITS bit; -}; - -struct MAVINTEN_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVINTEN_REG { - Uint32 all; - struct MAVINTEN_BITS bit; -}; - -struct ACCESS_PROTECTION_REGS { - union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register - union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register - union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register - union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register - Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address - Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address - Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address - Uint16 rsvd1[2]; // Reserved - Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address - Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address - Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address - Uint16 rsvd2[10]; // Reserved - union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register - union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register - union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register - union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register - Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address - Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address - Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address - Uint16 rsvd3[18]; // Reserved -}; - -struct UCERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRFLG_REG { - Uint32 all; - struct UCERRFLG_BITS bit; -}; - -struct UCERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRSET_REG { - Uint32 all; - struct UCERRSET_BITS bit; -}; - -struct UCERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRCLR_REG { - Uint32 all; - struct UCERRCLR_BITS bit; -}; - -struct CERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRFLG_REG { - Uint32 all; - struct CERRFLG_BITS bit; -}; - -struct CERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRSET_REG { - Uint32 all; - struct CERRSET_BITS bit; -}; - -struct CERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRCLR_REG { - Uint32 all; - struct CERRCLR_BITS bit; -}; - -struct CEINTFLG_BITS { // bits description - Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTFLG_REG { - Uint32 all; - struct CEINTFLG_BITS bit; -}; - -struct CEINTCLR_BITS { // bits description - Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTCLR_REG { - Uint32 all; - struct CEINTCLR_BITS bit; -}; - -struct CEINTSET_BITS { // bits description - Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTSET_REG { - Uint32 all; - struct CEINTSET_BITS bit; -}; - -struct CEINTEN_BITS { // bits description - Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTEN_REG { - Uint32 all; - struct CEINTEN_BITS bit; -}; - -struct MEMORY_ERROR_REGS { - union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register - union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register - union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register - Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address - Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address - Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address - Uint16 rsvd1[20]; // Reserved - union CERRFLG_REG CERRFLG; // Correctable Error Flag Register - union CERRSET_REG CERRSET; // Correctable Error Flag Set Register - union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register - Uint32 CCPUREADDR; // Correctable CPU Read Error Address - Uint16 rsvd2[6]; // Reserved - Uint32 CERRCNT; // Correctable Error Count Register - Uint32 CERRTHRES; // Correctable Error Threshold Value Register - union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register - union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register - union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register - union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register - Uint16 rsvd3[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// MEMCONFIG External References & Function Declarations: -// -extern volatile struct MEM_CFG_REGS MemCfgRegs; -extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; -extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h deleted file mode 100644 index 73c40c6..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h +++ /dev/null @@ -1,178 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_nmiintrupt.h -// -// TITLE: NMIINTRUPT Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_NMIINTRUPT_H__ -#define __F28004X_NMIINTRUPT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// NMIINTRUPT Individual Register Bit Definitions: - -struct NMICFG_BITS { // bits description - Uint16 NMIE:1; // 0 Global NMI Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union NMICFG_REG { - Uint16 all; - struct NMICFG_BITS bit; -}; - -struct NMIFLG_BITS { // bits description - Uint16 NMIINT:1; // 0 NMI Interrupt Flag - Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag - Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag - Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 rsvd7:1; // 11 Reserved - Uint16 rsvd8:1; // 12 Reserved - Uint16 SWERR:1; // 13 SW Error Force NMI Flag - Uint16 rsvd9:2; // 15:14 Reserved -}; - -union NMIFLG_REG { - Uint16 all; - struct NMIFLG_BITS bit; -}; - -struct NMIFLGCLR_BITS { // bits description - Uint16 NMIINT:1; // 0 NMIINT Flag Clear - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 rsvd7:1; // 11 Reserved - Uint16 rsvd8:1; // 12 Reserved - Uint16 SWERR:1; // 13 SWERR Flag Clear - Uint16 rsvd9:2; // 15:14 Reserved -}; - -union NMIFLGCLR_REG { - Uint16 all; - struct NMIFLGCLR_BITS bit; -}; - -struct NMIFLGFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 SWERR:1; // 13 SWERR Flag Force - Uint16 rsvd10:2; // 15:14 Reserved -}; - -union NMIFLGFRC_REG { - Uint16 all; - struct NMIFLGFRC_BITS bit; -}; - -struct NMISHDFLG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag - Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag - Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 SWERR:1; // 13 SW Error Force NMI Flag - Uint16 rsvd10:2; // 15:14 Reserved -}; - -union NMISHDFLG_REG { - Uint16 all; - struct NMISHDFLG_BITS bit; -}; - -struct NMI_INTRUPT_REGS { - union NMICFG_REG NMICFG; // NMI Configuration Register - union NMIFLG_REG NMIFLG; // NMI Flag Register (SYSRsn Clear) - union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register - union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register - Uint16 NMIWDCNT; // NMI Watchdog Counter Register - Uint16 NMIWDPRD; // NMI Watchdog Period Register - union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register -}; - -//--------------------------------------------------------------------------- -// NMIINTRUPT External References & Function Declarations: -// -extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h deleted file mode 100644 index 461cfdf..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h +++ /dev/null @@ -1,905 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_output_xbar.h -// -// TITLE: OUTPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_OUTPUT_XBAR_H__ -#define __F28004X_OUTPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR Individual Register Bit Definitions: - -struct OUTPUT1MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT1MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT1MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT1MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT2MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT2MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT2MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT2MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT3MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT3MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT3MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT3MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT4MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT4MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT5MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT5MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT6MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT6MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT6MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT6MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT7MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT7MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT8MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT8MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT1MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUXENABLE_REG { - Uint32 all; - struct OUTPUT1MUXENABLE_BITS bit; -}; - -struct OUTPUT2MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUXENABLE_REG { - Uint32 all; - struct OUTPUT2MUXENABLE_BITS bit; -}; - -struct OUTPUT3MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUXENABLE_REG { - Uint32 all; - struct OUTPUT3MUXENABLE_BITS bit; -}; - -struct OUTPUT4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUXENABLE_REG { - Uint32 all; - struct OUTPUT4MUXENABLE_BITS bit; -}; - -struct OUTPUT5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUXENABLE_REG { - Uint32 all; - struct OUTPUT5MUXENABLE_BITS bit; -}; - -struct OUTPUT6MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUXENABLE_REG { - Uint32 all; - struct OUTPUT6MUXENABLE_BITS bit; -}; - -struct OUTPUT7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUXENABLE_REG { - Uint32 all; - struct OUTPUT7MUXENABLE_BITS bit; -}; - -struct OUTPUT8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUXENABLE_REG { - Uint32 all; - struct OUTPUT8MUXENABLE_BITS bit; -}; - -struct OUTPUTLATCH_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCH_REG { - Uint32 all; - struct OUTPUTLATCH_BITS bit; -}; - -struct OUTPUTLATCHCLR_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHCLR_REG { - Uint32 all; - struct OUTPUTLATCHCLR_BITS bit; -}; - -struct OUTPUTLATCHFRC_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHFRC_REG { - Uint32 all; - struct OUTPUTLATCHFRC_BITS bit; -}; - -struct OUTPUTLATCHENABLE_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHENABLE_REG { - Uint32 all; - struct OUTPUTLATCHENABLE_BITS bit; -}; - -struct OUTPUTINV_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTINV_REG { - Uint32 all; - struct OUTPUTINV_BITS bit; -}; - -struct OUTPUTLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write Protection KEY -}; - -union OUTPUTLOCK_REG { - Uint32 all; - struct OUTPUTLOCK_BITS bit; -}; - -struct OUTPUT_XBAR_REGS { - union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 - union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 - union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 - union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 - union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 - union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 - union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 - union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 - union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch - union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear - union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear - union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable - union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion - Uint16 rsvd1[4]; // Reserved - union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR External References & Function Declarations: -// -extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h deleted file mode 100644 index d4adbd8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h +++ /dev/null @@ -1,164 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pga.h -// -// TITLE: PGA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PGA_H__ -#define __F28004X_PGA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PGA Individual Register Bit Definitions: - -struct PGACTL_BITS { // bits description - Uint16 PGAEN:1; // 0 PGA Enable - Uint16 FILTRESSEL:4; // 4:1 Filter Resistor Select - Uint16 GAIN:3; // 7:5 PGA gain setting - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGACTL_REG { - Uint32 all; - struct PGACTL_BITS bit; -}; - -struct PGALOCK_BITS { // bits description - Uint16 PGACTL:1; // 0 Lock bit for PGACTL. - Uint16 rsvd1:1; // 1 Reserved - Uint16 PGAGAIN3TRIM:1; // 2 Lock bit for PGAGAIN3TRIM. - Uint16 PGAGAIN6TRIM:1; // 3 Lock bit for PGAGAIN6TRIM. - Uint16 PGAGAIN12TRIM:1; // 4 Lock bit for PGAGAIN12TRIM. - Uint16 PGAGAIN24TRIM:1; // 5 Lock bit for PGAGAIN24TRIM. - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:8; // 15:8 Reserved -}; - -union PGALOCK_REG { - Uint16 all; - struct PGALOCK_BITS bit; -}; - -struct PGAGAIN3TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 3 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 3 -}; - -union PGAGAIN3TRIM_REG { - Uint16 all; - struct PGAGAIN3TRIM_BITS bit; -}; - -struct PGAGAIN6TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 6 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 6 -}; - -union PGAGAIN6TRIM_REG { - Uint16 all; - struct PGAGAIN6TRIM_BITS bit; -}; - -struct PGAGAIN12TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 12 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 12 -}; - -union PGAGAIN12TRIM_REG { - Uint16 all; - struct PGAGAIN12TRIM_BITS bit; -}; - -struct PGAGAIN24TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 24 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 24 -}; - -union PGAGAIN24TRIM_REG { - Uint16 all; - struct PGAGAIN24TRIM_BITS bit; -}; - -struct PGATYPE_BITS { // bits description - Uint16 REV:8; // 7:0 PGA Revision Field - Uint16 TYPE:8; // 15:8 PGA Type Field -}; - -union PGATYPE_REG { - Uint16 all; - struct PGATYPE_BITS bit; -}; - -struct PGA_REGS { - union PGACTL_REG PGACTL; // PGA Control Register - union PGALOCK_REG PGALOCK; // PGA Lock Register - Uint16 rsvd1; // Reserved - union PGAGAIN3TRIM_REG PGAGAIN3TRIM; // PGA Gain Trim Register for a gain setting of 3 - union PGAGAIN6TRIM_REG PGAGAIN6TRIM; // PGA Gain Trim Register for a gain setting of 6 - union PGAGAIN12TRIM_REG PGAGAIN12TRIM; // PGA Gain Trim Register for a gain setting of 12 - union PGAGAIN24TRIM_REG PGAGAIN24TRIM; // PGA Gain Trim Register for a gain setting of 24 - union PGATYPE_REG PGATYPE; // PGA Type Register - Uint16 rsvd2[7]; // Reserved -}; - -//--------------------------------------------------------------------------- -// PGA External References & Function Declarations: -// -extern volatile struct PGA_REGS Pga1Regs; -extern volatile struct PGA_REGS Pga2Regs; -extern volatile struct PGA_REGS Pga3Regs; -extern volatile struct PGA_REGS Pga4Regs; -extern volatile struct PGA_REGS Pga5Regs; -extern volatile struct PGA_REGS Pga6Regs; -extern volatile struct PGA_REGS Pga7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h deleted file mode 100644 index 2c44154..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h +++ /dev/null @@ -1,702 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_piectrl.h -// -// TITLE: PIECTRL Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PIECTRL_H__ -#define __F28004X_PIECTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PIECTRL Individual Register Bit Definitions: - -struct PIECTRL_BITS { // bits description - Uint16 ENPIE:1; // 0 PIE Enable - Uint16 PIEVECT:15; // 15:1 PIE Vector Address -}; - -union PIECTRL_REG { - Uint16 all; - struct PIECTRL_BITS bit; -}; - -struct PIEACK_BITS { // bits description - Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 - Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 - Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 - Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 - Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 - Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 - Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 - Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 - Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 - Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 - Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 - Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union PIEACK_REG { - Uint16 all; - struct PIEACK_BITS bit; -}; - -struct PIEIER1_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 -}; - -union PIEIER1_REG { - Uint16 all; - struct PIEIER1_BITS bit; -}; - -struct PIEIFR1_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 -}; - -union PIEIFR1_REG { - Uint16 all; - struct PIEIFR1_BITS bit; -}; - -struct PIEIER2_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 -}; - -union PIEIER2_REG { - Uint16 all; - struct PIEIER2_BITS bit; -}; - -struct PIEIFR2_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 -}; - -union PIEIFR2_REG { - Uint16 all; - struct PIEIFR2_BITS bit; -}; - -struct PIEIER3_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 -}; - -union PIEIER3_REG { - Uint16 all; - struct PIEIER3_BITS bit; -}; - -struct PIEIFR3_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 -}; - -union PIEIFR3_REG { - Uint16 all; - struct PIEIFR3_BITS bit; -}; - -struct PIEIER4_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 -}; - -union PIEIER4_REG { - Uint16 all; - struct PIEIER4_BITS bit; -}; - -struct PIEIFR4_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 -}; - -union PIEIFR4_REG { - Uint16 all; - struct PIEIFR4_BITS bit; -}; - -struct PIEIER5_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 -}; - -union PIEIER5_REG { - Uint16 all; - struct PIEIER5_BITS bit; -}; - -struct PIEIFR5_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 -}; - -union PIEIFR5_REG { - Uint16 all; - struct PIEIFR5_BITS bit; -}; - -struct PIEIER6_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 -}; - -union PIEIER6_REG { - Uint16 all; - struct PIEIER6_BITS bit; -}; - -struct PIEIFR6_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 -}; - -union PIEIFR6_REG { - Uint16 all; - struct PIEIFR6_BITS bit; -}; - -struct PIEIER7_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 -}; - -union PIEIER7_REG { - Uint16 all; - struct PIEIER7_BITS bit; -}; - -struct PIEIFR7_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 -}; - -union PIEIFR7_REG { - Uint16 all; - struct PIEIFR7_BITS bit; -}; - -struct PIEIER8_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 -}; - -union PIEIER8_REG { - Uint16 all; - struct PIEIER8_BITS bit; -}; - -struct PIEIFR8_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 -}; - -union PIEIFR8_REG { - Uint16 all; - struct PIEIFR8_BITS bit; -}; - -struct PIEIER9_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 -}; - -union PIEIER9_REG { - Uint16 all; - struct PIEIER9_BITS bit; -}; - -struct PIEIFR9_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 -}; - -union PIEIFR9_REG { - Uint16 all; - struct PIEIFR9_BITS bit; -}; - -struct PIEIER10_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 -}; - -union PIEIER10_REG { - Uint16 all; - struct PIEIER10_BITS bit; -}; - -struct PIEIFR10_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 -}; - -union PIEIFR10_REG { - Uint16 all; - struct PIEIFR10_BITS bit; -}; - -struct PIEIER11_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 -}; - -union PIEIER11_REG { - Uint16 all; - struct PIEIER11_BITS bit; -}; - -struct PIEIFR11_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 -}; - -union PIEIFR11_REG { - Uint16 all; - struct PIEIFR11_BITS bit; -}; - -struct PIEIER12_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 -}; - -union PIEIER12_REG { - Uint16 all; - struct PIEIER12_BITS bit; -}; - -struct PIEIFR12_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 -}; - -union PIEIFR12_REG { - Uint16 all; - struct PIEIFR12_BITS bit; -}; - -struct PIE_CTRL_REGS { - union PIECTRL_REG PIECTRL; // ePIE Control Register - union PIEACK_REG PIEACK; // Interrupt Acknowledge Register - union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register - union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register - union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register - union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register - union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register - union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register - union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register - union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register - union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register - union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register - union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register - union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register - union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register - union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register - union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register - union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register - union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register - union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register - union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register - union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register - union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register - union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register - union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register - union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register -}; - -//--------------------------------------------------------------------------- -// PIECTRL External References & Function Declarations: -// -extern volatile struct PIE_CTRL_REGS PieCtrlRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h deleted file mode 100644 index 54899af..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h +++ /dev/null @@ -1,297 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pievect.h -// -// TITLE: F28004x Device PIE Vector Table Definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_PIEVECT_H -#define F28004X_PIEVECT_H -#ifdef __cplusplus -extern "C" { -#endif - -//--------------------------------------------------------------------------- -// PIE Interrupt Vector Table Definition: -// Create a user type called PINT (pointer to interrupt): - -typedef __interrupt void (*PINT)(void); - -// Define Vector Table: -struct PIE_VECT_TABLE { - PINT PIE1_RESERVED_INT; // Reserved - PINT PIE2_RESERVED_INT; // Reserved - PINT PIE3_RESERVED_INT; // Reserved - PINT PIE4_RESERVED_INT; // Reserved - PINT PIE5_RESERVED_INT; // Reserved - PINT PIE6_RESERVED_INT; // Reserved - PINT PIE7_RESERVED_INT; // Reserved - PINT PIE8_RESERVED_INT; // Reserved - PINT PIE9_RESERVED_INT; // Reserved - PINT PIE10_RESERVED_INT; // Reserved - PINT PIE11_RESERVED_INT; // Reserved - PINT PIE12_RESERVED_INT; // Reserved - PINT PIE13_RESERVED_INT; // Reserved - PINT TIMER1_INT; // CPU Timer 1 Interrupt - PINT TIMER2_INT; // CPU Timer 2 Interrupt - PINT DATALOG_INT; // Datalogging Interrupt - PINT RTOS_INT; // RTOS Interrupt - PINT EMU_INT; // Emulation Interrupt - PINT NMI_INT; // Non-Maskable Interrupt - PINT ILLEGAL_INT; // Illegal Operation Trap - PINT USER1_INT; // User Defined Trap 1 - PINT USER2_INT; // User Defined Trap 2 - PINT USER3_INT; // User Defined Trap 3 - PINT USER4_INT; // User Defined Trap 4 - PINT USER5_INT; // User Defined Trap 5 - PINT USER6_INT; // User Defined Trap 6 - PINT USER7_INT; // User Defined Trap 7 - PINT USER8_INT; // User Defined Trap 8 - PINT USER9_INT; // User Defined Trap 9 - PINT USER10_INT; // User Defined Trap 10 - PINT USER11_INT; // User Defined Trap 11 - PINT USER12_INT; // User Defined Trap 12 - PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 - PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 - PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 - PINT XINT1_INT; // 1.4 - XINT1 Interrupt - PINT XINT2_INT; // 1.5 - XINT2 Interrupt - PINT PIE14_RESERVED_INT; // 1.6 - Reserved - PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt - PINT WAKE_INT; // 1.8 - Halt Wakeup Interrupt - PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt - PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt - PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt - PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt - PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt - PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt - PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt - PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt - PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt - PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt - PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt - PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt - PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt - PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt - PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt - PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt - PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt - PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt - PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt - PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt - PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt - PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt - PINT ECAP7_INT; // 4.7 - eCAP7 Interrupt - PINT PIE15_RESERVED_INT; // 4.8 - Reserved - PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt - PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt - PINT PIE16_RESERVED_INT; // 5.3 - Reserved - PINT PIE17_RESERVED_INT; // 5.4 - Reserved - PINT PIE18_RESERVED_INT; // 5.5 - Reserved - PINT PIE19_RESERVED_INT; // 5.6 - Reserved - PINT PIE20_RESERVED_INT; // 5.7 - Reserved - PINT PIE21_RESERVED_INT; // 5.8 - Reserved - PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt - PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt - PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt - PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt - PINT PIE22_RESERVED_INT; // 6.5 - Reserved - PINT PIE23_RESERVED_INT; // 6.6 - Reserved - PINT PIE24_RESERVED_INT; // 6.7 - Reserved - PINT PIE25_RESERVED_INT; // 6.8 - Reserved - PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt - PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt - PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt - PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt - PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt - PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt - PINT PIE26_RESERVED_INT; // 7.7 - Reserved - PINT PIE27_RESERVED_INT; // 7.8 - Reserved - PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 - PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 - PINT PIE28_RESERVED_INT; // 8.3 - Reserved - PINT PIE29_RESERVED_INT; // 8.4 - Reserved - PINT PIE30_RESERVED_INT; // 8.5 - Reserved - PINT PIE31_RESERVED_INT; // 8.6 - Reserved - PINT PIE32_RESERVED_INT; // 8.7 - Reserved - PINT PIE33_RESERVED_INT; // 8.8 - Reserved - PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt - PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt - PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt - PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt - PINT CANA0_INT; // 9.5 - CANA Interrupt 0 - PINT CANA1_INT; // 9.6 - CANA Interrupt 1 - PINT CANB0_INT; // 9.7 - CANB Interrupt 0 - PINT CANB1_INT; // 9.8 - CANB Interrupt 1 - PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt - PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 - PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 - PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 - PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt - PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 - PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 - PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 - PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 - PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 - PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 - PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 - PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 - PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 - PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 - PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 - PINT XINT3_INT; // 12.1 - XINT3 Interrupt - PINT XINT4_INT; // 12.2 - XINT4 Interrupt - PINT XINT5_INT; // 12.3 - XINT5 Interrupt - PINT PIE34_RESERVED_INT; // 12.4 - Reserved - PINT PIE35_RESERVED_INT; // 12.5 - Reserved - PINT PIE36_RESERVED_INT; // 12.6 - Reserved - PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt - PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt - PINT PIE37_RESERVED_INT; // 1.9 - Reserved - PINT PIE38_RESERVED_INT; // 1.10 - Reserved - PINT PIE39_RESERVED_INT; // 1.11 - Reserved - PINT PIE40_RESERVED_INT; // 1.12 - Reserved - PINT PIE41_RESERVED_INT; // 1.13 - Reserved - PINT PIE42_RESERVED_INT; // 1.14 - Reserved - PINT PIE43_RESERVED_INT; // 1.15 - Reserved - PINT PIE44_RESERVED_INT; // 1.16 - Reserved - PINT PIE45_RESERVED_INT; // 2.9 - Reserved - PINT PIE46_RESERVED_INT; // 2.10 - Reserved - PINT PIE47_RESERVED_INT; // 2.11 - Reserved - PINT PIE48_RESERVED_INT; // 2.12 - Reserved - PINT PIE49_RESERVED_INT; // 2.13 - Reserved - PINT PIE50_RESERVED_INT; // 2.14 - Reserved - PINT PIE51_RESERVED_INT; // 2.15 - Reserved - PINT PIE52_RESERVED_INT; // 2.16 - Reserved - PINT PIE53_RESERVED_INT; // 3.9 - Reserved - PINT PIE54_RESERVED_INT; // 3.10 - Reserved - PINT PIE55_RESERVED_INT; // 3.11 - Reserved - PINT PIE56_RESERVED_INT; // 3.12 - Reserved - PINT PIE57_RESERVED_INT; // 3.13 - Reserved - PINT PIE58_RESERVED_INT; // 3.14 - Reserved - PINT PIE59_RESERVED_INT; // 3.15 - Reserved - PINT PIE60_RESERVED_INT; // 3.16 - Reserved - PINT PIE61_RESERVED_INT; // 4.9 - Reserved - PINT PIE62_RESERVED_INT; // 4.10 - Reserved - PINT PIE63_RESERVED_INT; // 4.11 - Reserved - PINT PIE64_RESERVED_INT; // 4.12 - Reserved - PINT PIE65_RESERVED_INT; // 4.13 - Reserved - PINT ECAP6_2_INT; // 4.14 - eCAP6_2 Interrupt - PINT ECAP7_2_INT; // 4.15 - eCAP7_2 Interrupt - PINT PIE66_RESERVED_INT; // 4.16 - Reserved - PINT SD1_INT; // 5.9 - SD1 Interrupt - PINT PIE67_RESERVED_INT; // 5.10 - Reserved - PINT PIE68_RESERVED_INT; // 5.11 - Reserved - PINT PIE69_RESERVED_INT; // 5.12 - Reserved - PINT SD1DR1_INT; // 5.13 - SD1DR1 Interrupt - PINT SD1DR2_INT; // 5.14 - SD1DR2 Interrupt - PINT SD1DR3_INT; // 5.15 - SD1DR3 Interrupt - PINT SD1DR4_INT; // 5.16 - SD1DR4 Interrupt - PINT PIE70_RESERVED_INT; // 6.9 - Reserved - PINT PIE71_RESERVED_INT; // 6.10 - Reserved - PINT PIE72_RESERVED_INT; // 6.11 - Reserved - PINT PIE73_RESERVED_INT; // 6.12 - Reserved - PINT PIE74_RESERVED_INT; // 6.13 - Reserved - PINT PIE75_RESERVED_INT; // 6.14 - Reserved - PINT PIE76_RESERVED_INT; // 6.15 - Reserved - PINT PIE77_RESERVED_INT; // 6.16 - Reserved - PINT PIE78_RESERVED_INT; // 7.9 - Reserved - PINT PIE79_RESERVED_INT; // 7.10 - Reserved - PINT PIE80_RESERVED_INT; // 7.11 - Reserved - PINT PIE81_RESERVED_INT; // 7.12 - Reserved - PINT PIE82_RESERVED_INT; // 7.13 - Reserved - PINT PIE83_RESERVED_INT; // 7.14 - Reserved - PINT CLA1PROMCRC_INT; // 7.15 - CLA1PROMCRC Interrupt - PINT PIE84_RESERVED_INT; // 7.16 - Reserved - PINT LINA_0_INT; // 8.9 - LINA Interrupt0 - PINT LINA_1_INT; // 8.10 - LINA Interrupt1 - PINT PIE85_RESERVED_INT; // 8.11 - Reserved - PINT PIE86_RESERVED_INT; // 8.12 - Reserved - PINT PMBUSA_INT; // 8.13 - PMBUSA Interrupt - PINT PIE87_RESERVED_INT; // 8.14 - Reserved - PINT PIE88_RESERVED_INT; // 8.15 - Reserved - PINT PIE89_RESERVED_INT; // 8.16 - Reserved - PINT PIE90_RESERVED_INT; // 9.9 - Reserved - PINT PIE91_RESERVED_INT; // 9.10 - Reserved - PINT PIE92_RESERVED_INT; // 9.11 - Reserved - PINT PIE93_RESERVED_INT; // 9.12 - Reserved - PINT PIE94_RESERVED_INT; // 9.13 - Reserved - PINT PIE95_RESERVED_INT; // 9.14 - Reserved - PINT PIE96_RESERVED_INT; // 9.15 - Reserved - PINT PIE97_RESERVED_INT; // 9.16 - Reserved - PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt - PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 - PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 - PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 - PINT PIE98_RESERVED_INT; // 10.13 - Reserved - PINT PIE99_RESERVED_INT; // 10.14 - Reserved - PINT PIE100_RESERVED_INT; // 10.15 - Reserved - PINT PIE101_RESERVED_INT; // 10.16 - Reserved - PINT PIE102_RESERVED_INT; // 11.9 - Reserved - PINT PIE103_RESERVED_INT; // 11.10 - Reserved - PINT PIE104_RESERVED_INT; // 11.11 - Reserved - PINT PIE105_RESERVED_INT; // 11.12 - Reserved - PINT PIE106_RESERVED_INT; // 11.13 - Reserved - PINT PIE107_RESERVED_INT; // 11.14 - Reserved - PINT PIE108_RESERVED_INT; // 11.15 - Reserved - PINT PIE109_RESERVED_INT; // 11.16 - Reserved - PINT PIE110_RESERVED_INT; // 12.9 - Reserved - PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt - PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt - PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt - PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt - PINT PIE111_RESERVED_INT; // 12.14 - Reserved - PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt - PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt -}; - -//--------------------------------------------------------------------------- -// PieVect External References & Function Declarations: -// - -extern volatile struct PIE_VECT_TABLE PieVectTable; - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F28004X_PIEVECT_H definition -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h deleted file mode 100644 index 0f55745..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h +++ /dev/null @@ -1,291 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pmbus.h -// -// TITLE: PMBUS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PMBUS_H__ -#define __F28004X_PMBUS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PMBUS Individual Register Bit Definitions: - -struct PMBMC_BITS { // bits description - Uint16 RW:1; // 0 RnW bit of the Message - Uint16 SLAVE_ADDR:7; // 7:1 Slave Address - Uint16 BYTE_COUNT:8; // 15:8 Number of Bytes Transmitted - Uint16 CMD_ENA:1; // 16 Master Command Code Enable - Uint16 EXT_CMD:1; // 17 Master Extended Command Code Enable - Uint16 PEC_ENA:1; // 18 Master PEC Processing Enable - Uint16 GRP_CMD:1; // 19 Master Group Command Message Enable - Uint16 PRC_CALL:1; // 20 Master Process Call Message Enable - Uint16 rsvd1:11; // 31:21 Reserved -}; - -union PMBMC_REG { - Uint32 all; - struct PMBMC_BITS bit; -}; - -struct PMBACK_BITS { // bits description - Uint16 ACK:1; // 0 Allows firmware to ack/nack received data - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBACK_REG { - Uint32 all; - struct PMBACK_BITS bit; -}; - -struct PMBSTS_BITS { // bits description - Uint16 RD_BYTE_COUNT:3; // 2:0 Number of Data Bytes available in Receive Data Register - Uint16 DATA_READY:1; // 3 Data Ready Flag - Uint16 DATA_REQUEST:1; // 4 Data Request Flag - Uint16 EOM:1; // 5 End of Message Indicator - Uint16 NACK:1; // 6 Not Acknowledge Flag Status - Uint16 PEC_VALID:1; // 7 PEC Valid Indicator - Uint16 CLK_LOW_TIMEOUT:1; // 8 Clock Low Timeout Status - Uint16 CLK_HIGH_DETECTED:1; // 9 Clock High Detection Status - Uint16 SLAVE_ADDR_READY:1; // 10 Slave Address Ready - Uint16 RPT_START:1; // 11 Repeated Start Flag - Uint16 UNIT_BUSY:1; // 12 PMBus Busy Indicator - Uint16 BUS_FREE:1; // 13 PMBus Free Indicator - Uint16 LOST_ARB:1; // 14 Lost Arbitration Flag - Uint16 MASTER:1; // 15 Master Indicator - Uint16 ALERT_EDGE:1; // 16 Alert Edge Detection Status - Uint16 CONTROL_EDGE:1; // 17 Control Edge Detection Status - Uint16 ALERT_RAW:1; // 18 Alert Pin Real Time Status - Uint16 CONTROL_RAW:1; // 19 Control Pin Real Time Status - Uint16 SDA_RAW:1; // 20 PMBus Data Pin Real Time Status - Uint16 SCL_RAW:1; // 21 PMBus Clock Pin Real Time Status - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PMBSTS_REG { - Uint32 all; - struct PMBSTS_BITS bit; -}; - -struct PMBINTM_BITS { // bits description - Uint16 BUS_FREE:1; // 0 Bus Free Interrupt Mask - Uint16 BUS_LOW_TIMEOUT:1; // 1 Clock Low Timeout Interrupt Mask - Uint16 DATA_READY:1; // 2 Data Ready Interrupt Mask - Uint16 DATA_REQUEST:1; // 3 Data Request Interrupt Mask - Uint16 SLAVE_ADDR_READY:1; // 4 Slave Address Ready Interrupt Mask - Uint16 EOM:1; // 5 End of Message Interrupt Mask - Uint16 ALERT:1; // 6 Alert Detection Interrupt Mask - Uint16 CONTROL:1; // 7 Control Detection Interrupt Mask - Uint16 LOST_ARB:1; // 8 Lost Arbitration Interrupt Mask - Uint16 CLK_HIGH_DETECT:1; // 9 Clock High Detection Interrupt Mask - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBINTM_REG { - Uint32 all; - struct PMBINTM_BITS bit; -}; - -struct PMBSC_BITS { // bits description - Uint16 SLAVE_ADDR:7; // 6:0 Configures the current device address of the slave. - Uint16 MAN_SLAVE_ACK:1; // 7 Manual Slave Address Acknowledgement Mode - Uint16 SLAVE_MASK:7; // 14:8 Slave address mask - Uint16 PEC_ENA:1; // 15 PEC Processing Enable - Uint16 TX_COUNT:3; // 18:16 Number of valid bytes in Transmit Data Register - Uint16 TX_PEC:1; // 19 send a PEC byte at end of message - Uint16 MAN_CMD:1; // 20 Manual Command Acknowledgement Mode - Uint16 RX_BYTE_ACK_CNT:2; // 22:21 Number of data bytes to automatically acknowledge - Uint16 rsvd1:9; // 31:23 Reserved -}; - -union PMBSC_REG { - Uint32 all; - struct PMBSC_BITS bit; -}; - -struct PMBHSA_BITS { // bits description - Uint16 SLAVE_RW:1; // 0 Stored R/W bit - Uint16 SLAVE_ADDR:7; // 7:1 Stored device address - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBHSA_REG { - Uint32 all; - struct PMBHSA_BITS bit; -}; - -struct PMBCTRL_BITS { // bits description - Uint16 RESET:1; // 0 PMBus Interface Synchronous Reset - Uint16 ALERT_EN:1; // 1 Slave Alert Enable - Uint16 BUS_LO_INT_EDGE:1; // 2 Clock Low Timeout Interrupt Edge Select - Uint16 FAST_MODE:1; // 3 Fast Mode Enable - Uint16 FAST_MODE_PLUS:1; // 4 Fast Mode Plus Enable - Uint16 CNTL_INT_EDGE:1; // 5 Control Interrupt Edge Select - Uint16 ALERT_MODE:1; // 6 Configures mode of Alert pin - Uint16 ALERT_VALUE:1; // 7 Configures output value of Alert pin in GPIO Mode - Uint16 ALERT_DIR:1; // 8 Configures direction of Alert pin in GPIO mode - Uint16 CNTL_MODE:1; // 9 Configures mode of Control pin - Uint16 CNTL_VALUE:1; // 10 Configures output value of Control pin in GPIO Mode - Uint16 CNTL_DIR:1; // 11 Configures direction of Control pin in GPIO mode - Uint16 SDA_MODE:1; // 12 Configures mode of PMBus Data pin - Uint16 SDA_VALUE:1; // 13 Configures output value of PMBus data pin in GPIO Mode - Uint16 SDA_DIR:1; // 14 Configures direction of PMBus data pin in GPIO mode - Uint16 SCL_MODE:1; // 15 Configures mode of PMBus Clock pin - Uint16 SCL_VALUE:1; // 16 Configures output value of PMBus clock pin in GPIO Mode - Uint16 SCL_DIR:1; // 17 Configures direction of PMBus clock pin in GPIO mode - Uint16 IBIAS_A_EN:1; // 18 PMBus Current Source A Control - Uint16 IBIAS_B_EN:1; // 19 PMBus Current Source B Control - Uint16 CLK_LO_DIS:1; // 20 Clock Low Timeout Disable - Uint16 SLAVE_EN:1; // 21 PMBus Slave Enable - Uint16 MASTER_EN:1; // 22 PMBus Master Enable - Uint16 CLKDIV:5; // 27:23 PMBUS IP Clock Divide Value - Uint16 rsvd1:3; // 30:28 Reserved - Uint16 I2CMODE:1; // 31 Bit to enable I2C mode -}; - -union PMBCTRL_REG { - Uint32 all; - struct PMBCTRL_BITS bit; -}; - -struct PMBTIMCTL_BITS { // bits description - Uint16 TIM_OVERRIDE:1; // 0 Overide the default settings of the timing parameters. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMCTL_REG { - Uint32 all; - struct PMBTIMCTL_BITS bit; -}; - -struct PMBTIMCLK_BITS { // bits description - Uint16 CLK_HIGH_LIMIT:8; // 7:0 Determines the PMBUS master clock high pulse width. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 CLK_FREQ:8; // 23:16 Determines the PMBUS master clock frequency. - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union PMBTIMCLK_REG { - Uint32 all; - struct PMBTIMCLK_BITS bit; -}; - -struct PMBTIMSTSETUP_BITS { // bits description - Uint16 TSU_STA:8; // 7:0 Setup time, rise edge of PMBUS master clock to start edge. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMSTSETUP_REG { - Uint32 all; - struct PMBTIMSTSETUP_BITS bit; -}; - -struct PMBTIMBIDLE_BITS { // bits description - Uint16 BUSIDLE:10; // 9:0 Determines the Bus Idle Limit - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMBIDLE_REG { - Uint32 all; - struct PMBTIMBIDLE_BITS bit; -}; - -struct PMBTIMLOWTIMOUT_BITS { // bits description - Uint32 CLKLOWTIMOUT:20; // 19:0 Determines the clock low timeout value - Uint16 rsvd1:12; // 31:20 Reserved -}; - -union PMBTIMLOWTIMOUT_REG { - Uint32 all; - struct PMBTIMLOWTIMOUT_BITS bit; -}; - -struct PMBTIMHIGHTIMOUT_BITS { // bits description - Uint16 CLKHIGHTIMOUT:10; // 9:0 Determines the clock high timeout value - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMHIGHTIMOUT_REG { - Uint32 all; - struct PMBTIMHIGHTIMOUT_BITS bit; -}; - -struct PMBUS_REGS { - union PMBMC_REG PMBMC; // PMBUS Master Mode Control Register - Uint32 PMBTXBUF; // PMBUS Transmit Buffer - Uint32 PMBRXBUF; // PMBUS Receive buffer - union PMBACK_REG PMBACK; // PMBUS Acknowledge Register - union PMBSTS_REG PMBSTS; // PMBUS Status Register - union PMBINTM_REG PMBINTM; // PMBUS Interrupt Mask Register - union PMBSC_REG PMBSC; // PMBUS Slave Mode Configuration Register - union PMBHSA_REG PMBHSA; // PMBUS Hold Slave Address Register - union PMBCTRL_REG PMBCTRL; // PMBUS Control Register - union PMBTIMCTL_REG PMBTIMCTL; // PMBUS Timing Control Register - union PMBTIMCLK_REG PMBTIMCLK; // PMBUS Clock Timing Register - union PMBTIMSTSETUP_REG PMBTIMSTSETUP; // PMBUS Start Setup Time Register - union PMBTIMBIDLE_REG PMBTIMBIDLE; // PMBUS Bus Idle Time Register - union PMBTIMLOWTIMOUT_REG PMBTIMLOWTIMOUT; // PMBUS Clock Low Timeout Value Register - union PMBTIMHIGHTIMOUT_REG PMBTIMHIGHTIMOUT; // PMBUS Clock High Timeout Value Register - Uint16 rsvd1[2]; // Reserved -}; - -//--------------------------------------------------------------------------- -// PMBUS External References & Function Declarations: -// -extern volatile struct PMBUS_REGS PmbusaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h deleted file mode 100644 index cbb8c2c..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sci.h -// -// TITLE: SCI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SCI_H__ -#define __F28004X_SCI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SCI Individual Register Bit Definitions: - -struct SCICCR_BITS { // bits description - Uint16 SCICHAR:3; // 2:0 Character length control - Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control - Uint16 LOOPBKENA:1; // 4 Loop Back enable - Uint16 PARITYENA:1; // 5 Parity enable - Uint16 PARITY:1; // 6 Even or Odd Parity - Uint16 STOPBITS:1; // 7 Number of Stop Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCICCR_REG { - Uint16 all; - struct SCICCR_BITS bit; -}; - -struct SCICTL1_BITS { // bits description - Uint16 RXENA:1; // 0 SCI receiver enable - Uint16 TXENA:1; // 1 SCI transmitter enable - Uint16 SLEEP:1; // 2 SCI sleep - Uint16 TXWAKE:1; // 3 Transmitter wakeup method - Uint16 rsvd1:1; // 4 Reserved - Uint16 SWRESET:1; // 5 Software reset - Uint16 RXERRINTENA:1; // 6 Receive __interrupt enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union SCICTL1_REG { - Uint16 all; - struct SCICTL1_BITS bit; -}; - -struct SCIHBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIHBAUD_REG { - Uint16 all; - struct SCIHBAUD_BITS bit; -}; - -struct SCILBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCILBAUD_REG { - Uint16 all; - struct SCILBAUD_BITS bit; -}; - -struct SCICTL2_BITS { // bits description - Uint16 TXINTENA:1; // 0 Transmit __interrupt enable - Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable - Uint16 rsvd1:4; // 5:2 Reserved - Uint16 TXEMPTY:1; // 6 Transmitter empty flag - Uint16 TXRDY:1; // 7 Transmitter ready flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCICTL2_REG { - Uint16 all; - struct SCICTL2_BITS bit; -}; - -struct SCIRXST_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag - Uint16 PE:1; // 2 Parity error flag - Uint16 OE:1; // 3 Overrun error flag - Uint16 FE:1; // 4 Framing error flag - Uint16 BRKDT:1; // 5 Break-detect flag - Uint16 RXRDY:1; // 6 Receiver ready flag - Uint16 RXERROR:1; // 7 Receiver error flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCIRXST_REG { - Uint16 all; - struct SCIRXST_BITS bit; -}; - -struct SCIRXEMU_BITS { // bits description - Uint16 ERXDT:8; // 7:0 Receive emulation buffer data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIRXEMU_REG { - Uint16 all; - struct SCIRXEMU_BITS bit; -}; - -struct SCIRXBUF_BITS { // bits description - Uint16 SAR:8; // 7:0 Receive Character bits - Uint16 rsvd1:6; // 13:8 Reserved - Uint16 SCIFFPE:1; // 14 Receiver error flag - Uint16 SCIFFFE:1; // 15 Receiver error flag -}; - -union SCIRXBUF_REG { - Uint16 all; - struct SCIRXBUF_BITS bit; -}; - -struct SCITXBUF_BITS { // bits description - Uint16 TXDT:8; // 7:0 Transmit data buffer - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCITXBUF_REG { - Uint16 all; - struct SCITXBUF_BITS bit; -}; - -struct SCIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Interrupt level - Uint16 TXFFIENA:1; // 5 Interrupt enable - Uint16 TXFFINTCLR:1; // 6 Clear INT flag - Uint16 TXFFINT:1; // 7 INT flag - Uint16 TXFFST:5; // 12:8 FIFO status - Uint16 TXFIFORESET:1; // 13 FIFO reset - Uint16 SCIFFENA:1; // 14 Enhancement enable - Uint16 SCIRST:1; // 15 SCI reset rx/tx channels -}; - -union SCIFFTX_REG { - Uint16 all; - struct SCIFFTX_BITS bit; -}; - -struct SCIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Interrupt level - Uint16 RXFFIENA:1; // 5 Interrupt enable - Uint16 RXFFINTCLR:1; // 6 Clear INT flag - Uint16 RXFFINT:1; // 7 INT flag - Uint16 RXFFST:5; // 12:8 FIFO status - Uint16 RXFIFORESET:1; // 13 FIFO reset - Uint16 RXFFOVRCLR:1; // 14 Clear overflow - Uint16 RXFFOVF:1; // 15 FIFO overflow -}; - -union SCIFFRX_REG { - Uint16 all; - struct SCIFFRX_BITS bit; -}; - -struct SCIFFCT_BITS { // bits description - Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay - Uint16 rsvd1:5; // 12:8 Reserved - Uint16 CDC:1; // 13 Auto baud mode enable - Uint16 ABDCLR:1; // 14 Auto baud clear - Uint16 ABD:1; // 15 Auto baud detect -}; - -union SCIFFCT_REG { - Uint16 all; - struct SCIFFCT_BITS bit; -}; - -struct SCIPRI_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 FREESOFT:2; // 4:3 Emulation modes - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 rsvd3:8; // 15:8 Reserved -}; - -union SCIPRI_REG { - Uint16 all; - struct SCIPRI_BITS bit; -}; - -struct SCI_REGS { - union SCICCR_REG SCICCR; // Communications control register - union SCICTL1_REG SCICTL1; // Control register 1 - union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register - union SCILBAUD_REG SCILBAUD; // Baud rate (low) register - union SCICTL2_REG SCICTL2; // Control register 2 - union SCIRXST_REG SCIRXST; // Receive status register - union SCIRXEMU_REG SCIRXEMU; // Receive emulation buffer register - union SCIRXBUF_REG SCIRXBUF; // Receive data buffer - Uint16 rsvd1; // Reserved - union SCITXBUF_REG SCITXBUF; // Transmit data buffer - union SCIFFTX_REG SCIFFTX; // FIFO transmit register - union SCIFFRX_REG SCIFFRX; // FIFO Receive register - union SCIFFCT_REG SCIFFCT; // FIFO control register - Uint16 rsvd2[2]; // Reserved - union SCIPRI_REG SCIPRI; // SCI Priority control -}; - -//--------------------------------------------------------------------------- -// SCI External References & Function Declarations: -// -extern volatile struct SCI_REGS SciaRegs; -extern volatile struct SCI_REGS ScibRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h deleted file mode 100644 index 340903e..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h +++ /dev/null @@ -1,797 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sdfm.h -// -// TITLE: SDFM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SDFM_H__ -#define __F28004X_SDFM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SDFM Individual Register Bit Definitions: - -struct SDIFLG_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 - Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 - Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 - Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 - Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 - Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 - Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 - Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 SDFFOVF1:1; // 16 FIFO Overflow Flag for Ch1. - Uint16 SDFFOVF2:1; // 17 FIFO Overflow Flag for Ch2 - Uint16 SDFFOVF3:1; // 18 FIFO Overflow Flag for Ch3 - Uint16 SDFFOVF4:1; // 19 FIFO Overflow Flag for Ch4 - Uint16 SDFFINT1:1; // 20 SDFIFO interrupt for Ch1 - Uint16 SDFFINT2:1; // 21 SDFIFO interrupt for Ch2 - Uint16 SDFFINT3:1; // 22 SDFIFO interrupt for Ch3 - Uint16 SDFFINT4:1; // 23 SDFIFO interrupt for Ch4 - Uint16 rsvd1:7; // 30:24 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLG_REG { - Uint32 all; - struct SDIFLG_BITS bit; -}; - -struct SDIFLGCLR_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 - Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 - Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 - Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 - Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 - Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 - Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 - Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 SDFFOVF1:1; // 16 SDFIFO overflow clear Ch1 - Uint16 SDFFOVF2:1; // 17 SDFIFO overflow clear Ch2 - Uint16 SDFFOVF3:1; // 18 SDFIFO overflow clear Ch3 - Uint16 SDFFOVF4:1; // 19 SDFIFO overflow clear Ch4 - Uint16 SDFFINT1:1; // 20 SDFIFO Interrupt flag-clear bit for Ch1 - Uint16 SDFFINT2:1; // 21 SDFIFO Interrupt flag-clear bit for Ch2 - Uint16 SDFFINT3:1; // 22 SDFIFO Interrupt flag-clear bit for Ch3 - Uint16 SDFFINT4:1; // 23 SDFIFO Interrupt flag-clear bit for Ch4 - Uint16 rsvd1:7; // 30:24 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLGCLR_REG { - Uint32 all; - struct SDIFLGCLR_BITS bit; -}; - -struct SDCTL_BITS { // bits description - Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 - Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 - Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 - Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 - Uint16 rsvd1:9; // 12:4 Reserved - Uint16 MIE:1; // 13 Master SDy_ERR Interrupt enable - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union SDCTL_REG { - Uint16 all; - struct SDCTL_BITS bit; -}; - -struct SDMFILEN_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:3; // 6:4 Reserved - Uint16 rsvd3:2; // 8:7 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:1; // 10 Reserved - Uint16 MFE:1; // 11 Master Filter Enable. - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:3; // 15:13 Reserved -}; - -union SDMFILEN_REG { - Uint16 all; - struct SDMFILEN_BITS bit; -}; - -struct SDSTATUS_BITS { // bits description - Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 - Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 - Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 - Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:1; // 10 Reserved - Uint16 rsvd5:1; // 11 Reserved - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:1; // 13 Reserved - Uint16 rsvd8:1; // 14 Reserved - Uint16 rsvd9:1; // 15 Reserved -}; - -union SDSTATUS_REG { - Uint16 all; - struct SDSTATUS_BITS bit; -}; - -struct SDCTLPARM1_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM1_REG { - Uint16 all; - struct SDCTLPARM1_BITS bit; -}; - -struct SDDFPARM1_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM1_REG { - Uint16 all; - struct SDDFPARM1_BITS bit; -}; - -struct SDDPARM1_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM1_REG { - Uint16 all; - struct SDDPARM1_BITS bit; -}; - -struct SDCMPH1_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH1_REG { - Uint16 all; - struct SDCMPH1_BITS bit; -}; - -struct SDCMPL1_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL1_REG { - Uint16 all; - struct SDCMPL1_BITS bit; -}; - -struct SDCPARM1_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM1_REG { - Uint16 all; - struct SDCPARM1_BITS bit; -}; - -struct SDDATA1_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA1_REG { - Uint32 all; - struct SDDATA1_BITS bit; -}; - -struct SDDATFIFO1_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO1_REG { - Uint32 all; - struct SDDATFIFO1_BITS bit; -}; - -struct SDCMPHZ1_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ1_REG { - Uint16 all; - struct SDCMPHZ1_BITS bit; -}; - -struct SDFIFOCTL1_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL1_REG { - Uint16 all; - struct SDFIFOCTL1_BITS bit; -}; - -struct SDSYNC1_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC1_REG { - Uint16 all; - struct SDSYNC1_BITS bit; -}; - -struct SDCTLPARM2_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM2_REG { - Uint16 all; - struct SDCTLPARM2_BITS bit; -}; - -struct SDDFPARM2_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM2_REG { - Uint16 all; - struct SDDFPARM2_BITS bit; -}; - -struct SDDPARM2_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM2_REG { - Uint16 all; - struct SDDPARM2_BITS bit; -}; - -struct SDCMPH2_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH2_REG { - Uint16 all; - struct SDCMPH2_BITS bit; -}; - -struct SDCMPL2_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL2_REG { - Uint16 all; - struct SDCMPL2_BITS bit; -}; - -struct SDCPARM2_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM2_REG { - Uint16 all; - struct SDCPARM2_BITS bit; -}; - -struct SDDATA2_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA2_REG { - Uint32 all; - struct SDDATA2_BITS bit; -}; - -struct SDDATFIFO2_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO2_REG { - Uint32 all; - struct SDDATFIFO2_BITS bit; -}; - -struct SDCMPHZ2_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ2_REG { - Uint16 all; - struct SDCMPHZ2_BITS bit; -}; - -struct SDFIFOCTL2_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL2_REG { - Uint16 all; - struct SDFIFOCTL2_BITS bit; -}; - -struct SDSYNC2_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC2_REG { - Uint16 all; - struct SDSYNC2_BITS bit; -}; - -struct SDCTLPARM3_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM3_REG { - Uint16 all; - struct SDCTLPARM3_BITS bit; -}; - -struct SDDFPARM3_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM3_REG { - Uint16 all; - struct SDDFPARM3_BITS bit; -}; - -struct SDDPARM3_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM3_REG { - Uint16 all; - struct SDDPARM3_BITS bit; -}; - -struct SDCMPH3_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH3_REG { - Uint16 all; - struct SDCMPH3_BITS bit; -}; - -struct SDCMPL3_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL3_REG { - Uint16 all; - struct SDCMPL3_BITS bit; -}; - -struct SDCPARM3_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM3_REG { - Uint16 all; - struct SDCPARM3_BITS bit; -}; - -struct SDDATA3_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA3_REG { - Uint32 all; - struct SDDATA3_BITS bit; -}; - -struct SDDATFIFO3_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO3_REG { - Uint32 all; - struct SDDATFIFO3_BITS bit; -}; - -struct SDCMPHZ3_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ3_REG { - Uint16 all; - struct SDCMPHZ3_BITS bit; -}; - -struct SDFIFOCTL3_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL3_REG { - Uint16 all; - struct SDFIFOCTL3_BITS bit; -}; - -struct SDSYNC3_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC3_REG { - Uint16 all; - struct SDSYNC3_BITS bit; -}; - -struct SDCTLPARM4_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM4_REG { - Uint16 all; - struct SDCTLPARM4_BITS bit; -}; - -struct SDDFPARM4_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM4_REG { - Uint16 all; - struct SDDFPARM4_BITS bit; -}; - -struct SDDPARM4_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM4_REG { - Uint16 all; - struct SDDPARM4_BITS bit; -}; - -struct SDCMPH4_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH4_REG { - Uint16 all; - struct SDCMPH4_BITS bit; -}; - -struct SDCMPL4_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL4_REG { - Uint16 all; - struct SDCMPL4_BITS bit; -}; - -struct SDCPARM4_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM4_REG { - Uint16 all; - struct SDCPARM4_BITS bit; -}; - -struct SDDATA4_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA4_REG { - Uint32 all; - struct SDDATA4_BITS bit; -}; - -struct SDDATFIFO4_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO4_REG { - Uint32 all; - struct SDDATFIFO4_BITS bit; -}; - -struct SDCMPHZ4_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ4_REG { - Uint16 all; - struct SDCMPHZ4_BITS bit; -}; - -struct SDFIFOCTL4_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL4_REG { - Uint16 all; - struct SDFIFOCTL4_BITS bit; -}; - -struct SDSYNC4_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC4_REG { - Uint16 all; - struct SDSYNC4_BITS bit; -}; - -struct SDFM_REGS { - union SDIFLG_REG SDIFLG; // SD Interrupt Flag Register - union SDIFLGCLR_REG SDIFLGCLR; // SD Interrupt Flag Clear Register - union SDCTL_REG SDCTL; // SD Control Register - Uint16 rsvd1; // Reserved - union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable - union SDSTATUS_REG SDSTATUS; // SD Status Register - Uint16 rsvd2[8]; // Reserved - union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 - union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 - union SDDPARM1_REG SDDPARM1; // Data Parameter Register for Ch1 - union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 - union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 - union SDCPARM1_REG SDCPARM1; // Comparator Filter Parameter Register for Ch1 - union SDDATA1_REG SDDATA1; // Data Filter Data Register (16 or 32bit) for Ch1 - union SDDATFIFO1_REG SDDATFIFO1; // Filter Data FIFO Output(32b) for Ch1 - Uint16 SDCDATA1; // Comparator Filter Data Register (16b) for Ch1 - Uint16 rsvd3; // Reserved - union SDCMPHZ1_REG SDCMPHZ1; // High-level (Z) Threshold Register for Ch1 - union SDFIFOCTL1_REG SDFIFOCTL1; // FIFO Control Register for Ch1 - union SDSYNC1_REG SDSYNC1; // SD Filter Sync control for Ch1 - Uint16 rsvd4; // Reserved - union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 - union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 - union SDDPARM2_REG SDDPARM2; // Data Parameter Register for Ch2 - union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 - union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 - union SDCPARM2_REG SDCPARM2; // Comparator Filter Parameter Register for Ch2 - union SDDATA2_REG SDDATA2; // Data Filter Data Register (16 or 32bit) for Ch2 - union SDDATFIFO2_REG SDDATFIFO2; // Filter Data FIFO Output(32b) for Ch2 - Uint16 SDCDATA2; // Comparator Filter Data Register (16b) for Ch2 - Uint16 rsvd5; // Reserved - union SDCMPHZ2_REG SDCMPHZ2; // High-level (Z) Threshold Register for Ch2 - union SDFIFOCTL2_REG SDFIFOCTL2; // FIFO Control Register for Ch2 - union SDSYNC2_REG SDSYNC2; // SD Filter Sync control for Ch2 - Uint16 rsvd6; // Reserved - union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 - union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 - union SDDPARM3_REG SDDPARM3; // Data Parameter Register for Ch3 - union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 - union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 - union SDCPARM3_REG SDCPARM3; // Comparator Filter Parameter Register for Ch3 - union SDDATA3_REG SDDATA3; // Data Filter Data Register (16 or 32bit) for Ch3 - union SDDATFIFO3_REG SDDATFIFO3; // Filter Data FIFO Output(32b) for Ch3 - Uint16 SDCDATA3; // Comparator Filter Data Register (16b) for Ch3 - Uint16 rsvd7; // Reserved - union SDCMPHZ3_REG SDCMPHZ3; // High-level (Z) Threshold Register for Ch3 - union SDFIFOCTL3_REG SDFIFOCTL3; // FIFO Control Register for Ch3 - union SDSYNC3_REG SDSYNC3; // SD Filter Sync control for Ch3 - Uint16 rsvd8; // Reserved - union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 - union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 - union SDDPARM4_REG SDDPARM4; // Data Parameter Register for Ch4 - union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 - union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 - union SDCPARM4_REG SDCPARM4; // Comparator Filter Parameter Register for Ch4 - union SDDATA4_REG SDDATA4; // Data Filter Data Register (16 or 32bit) for Ch4 - union SDDATFIFO4_REG SDDATFIFO4; // Filter Data FIFO Output(32b) for Ch4 - Uint16 SDCDATA4; // Comparator Filter Data Register (16b) for Ch4 - Uint16 rsvd9; // Reserved - union SDCMPHZ4_REG SDCMPHZ4; // High-level (Z) Threshold Register for Ch4 - union SDFIFOCTL4_REG SDFIFOCTL4; // FIFO Control Register for Ch4 - union SDSYNC4_REG SDSYNC4; // SD Filter Sync control for Ch4 - Uint16 rsvd10[33]; // Reserved -}; - -//--------------------------------------------------------------------------- -// SDFM External References & Function Declarations: -// -extern volatile struct SDFM_REGS Sdfm1Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h deleted file mode 100644 index 27721ed..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h +++ /dev/null @@ -1,193 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_spi.h -// -// TITLE: SPI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SPI_H__ -#define __F28004X_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SPI Individual Register Bit Definitions: - -struct SPICCR_BITS { // bits description - Uint16 SPICHAR:4; // 3:0 Character Length Control - Uint16 SPILBK:1; // 4 SPI Loopback - Uint16 HS_MODE:1; // 5 High Speed mode control - Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity - Uint16 SPISWRESET:1; // 7 SPI Software Reset - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPICCR_REG { - Uint16 all; - struct SPICCR_BITS bit; -}; - -struct SPICTL_BITS { // bits description - Uint16 SPIINTENA:1; // 0 SPI Interupt Enable - Uint16 TALK:1; // 1 Master/Slave Transmit Enable - Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control - Uint16 CLK_PHASE:1; // 3 SPI Clock Phase - Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union SPICTL_REG { - Uint16 all; - struct SPICTL_BITS bit; -}; - -struct SPISTS_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag - Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag - Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SPISTS_REG { - Uint16 all; - struct SPISTS_BITS bit; -}; - -struct SPIBRR_BITS { // bits description - Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union SPIBRR_REG { - Uint16 all; - struct SPIBRR_BITS bit; -}; - -struct SPIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear - Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFIFO:1; // 13 TXFIFO Reset - Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable - Uint16 SPIRST:1; // 15 SPI Reset -}; - -union SPIFFTX_REG { - Uint16 all; - struct SPIFFTX_BITS bit; -}; - -struct SPIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear - Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFIFORESET:1; // 13 RXFIFO Reset - Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear - Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag -}; - -union SPIFFRX_REG { - Uint16 all; - struct SPIFFRX_BITS bit; -}; - -struct SPIFFCT_BITS { // bits description - Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPIFFCT_REG { - Uint16 all; - struct SPIFFCT_BITS bit; -}; - -struct SPIPRI_BITS { // bits description - Uint16 TRIWIRE:1; // 0 3-wire mode select bit - Uint16 STEINV:1; // 1 SPISTE inversion bit - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 FREE:1; // 4 Free emulation mode - Uint16 SOFT:1; // 5 Soft emulation mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:9; // 15:7 Reserved -}; - -union SPIPRI_REG { - Uint16 all; - struct SPIPRI_BITS bit; -}; - -struct SPI_REGS { - union SPICCR_REG SPICCR; // SPI Configuration Control Register - union SPICTL_REG SPICTL; // SPI Operation Control Register - union SPISTS_REG SPISTS; // SPI Status Register - Uint16 rsvd1; // Reserved - union SPIBRR_REG SPIBRR; // SPI Baud Rate Register - Uint16 rsvd2; // Reserved - Uint16 SPIRXEMU; // SPI Emulation Buffer Register - Uint16 SPIRXBUF; // SPI Serial Input Buffer Register - Uint16 SPITXBUF; // SPI Serial Output Buffer Register - Uint16 SPIDAT; // SPI Serial Data Register - union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register - union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register - union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register - Uint16 rsvd3[2]; // Reserved - union SPIPRI_REG SPIPRI; // SPI Priority Control Register -}; - -//--------------------------------------------------------------------------- -// SPI External References & Function Declarations: -// -extern volatile struct SPI_REGS SpiaRegs; -extern volatile struct SPI_REGS SpibRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h deleted file mode 100644 index adbdf64..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h +++ /dev/null @@ -1,2062 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl.h -// -// TITLE: SYSCTRL Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SYSCTRL_H__ -#define __F28004X_SYSCTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SYSCTRL Individual Register Bit Definitions: - -struct PARTIDL_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 rsvd2:2; // 4:3 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 QUAL:2; // 7:6 Qualification Status - Uint16 PIN_COUNT:3; // 10:8 Device Pin Count - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 INSTASPIN:2; // 14:13 Instaspin feature set - Uint16 rsvd6:1; // 15 Reserved - Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB - Uint16 rsvd7:4; // 27:24 Reserved - Uint16 rsvd8:4; // 31:28 Reserved -}; - -union PARTIDL_REG { - Uint32 all; - struct PARTIDL_BITS bit; -}; - -struct PARTIDH_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:4; // 7:4 Reserved - Uint16 FAMILY:8; // 15:8 Device family - Uint16 PARTNO:8; // 23:16 Device part number - Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID -}; - -union PARTIDH_REG { - Uint32 all; - struct PARTIDH_BITS bit; -}; - -struct REVID_BITS { // bits description - Uint16 REVID:16; // 15:0 Device Revision ID. This is specific to the Device - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union REVID_REG { - Uint32 all; - struct REVID_BITS bit; -}; - -struct FUSEERR_BITS { // bits description - Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status - Uint16 ERR:1; // 5 Efuse Self Test Error Status - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FUSEERR_REG { - Uint32 all; - struct FUSEERR_BITS bit; -}; - -struct SOFTPRES0_BITS { // bits description - Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES0_REG { - Uint32 all; - struct SOFTPRES0_BITS bit; -}; - -struct SOFTPRES2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 software reset bit - Uint16 EPWM2:1; // 1 EPWM2 software reset bit - Uint16 EPWM3:1; // 2 EPWM3 software reset bit - Uint16 EPWM4:1; // 3 EPWM4 software reset bit - Uint16 EPWM5:1; // 4 EPWM5 software reset bit - Uint16 EPWM6:1; // 5 EPWM6 software reset bit - Uint16 EPWM7:1; // 6 EPWM7 software reset bit - Uint16 EPWM8:1; // 7 EPWM8 software reset bit - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union SOFTPRES2_REG { - Uint32 all; - struct SOFTPRES2_BITS bit; -}; - -struct SOFTPRES3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 software reset bit - Uint16 ECAP2:1; // 1 ECAP2 software reset bit - Uint16 ECAP3:1; // 2 ECAP3 software reset bit - Uint16 ECAP4:1; // 3 ECAP4 software reset bit - Uint16 ECAP5:1; // 4 ECAP5 software reset bit - Uint16 ECAP6:1; // 5 ECAP6 software reset bit - Uint16 ECAP7:1; // 6 ECAP7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES3_REG { - Uint32 all; - struct SOFTPRES3_BITS bit; -}; - -struct SOFTPRES4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 software reset bit - Uint16 EQEP2:1; // 1 EQEP2 software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES4_REG { - Uint32 all; - struct SOFTPRES4_BITS bit; -}; - -struct SOFTPRES6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint16 rsvd7:1; // 7 Reserved - Uint16 rsvd8:8; // 15:8 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union SOFTPRES6_REG { - Uint32 all; - struct SOFTPRES6_BITS bit; -}; - -struct SOFTPRES7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A software reset bit - Uint16 SCI_B:1; // 1 SCI_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES7_REG { - Uint32 all; - struct SOFTPRES7_BITS bit; -}; - -struct SOFTPRES8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A software reset bit - Uint16 SPI_B:1; // 1 SPI_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:1; // 16 Reserved - Uint16 rsvd5:1; // 17 Reserved - Uint16 rsvd6:14; // 31:18 Reserved -}; - -union SOFTPRES8_REG { - Uint32 all; - struct SOFTPRES8_BITS bit; -}; - -struct SOFTPRES9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES9_REG { - Uint32 all; - struct SOFTPRES9_BITS bit; -}; - -struct SOFTPRES10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A software reset bit - Uint16 CAN_B:1; // 1 CAN_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES10_REG { - Uint32 all; - struct SOFTPRES10_BITS bit; -}; - -struct SOFTPRES13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A software reset bit - Uint16 ADC_B:1; // 1 ADC_B software reset bit - Uint16 ADC_C:1; // 2 ADC_C software reset bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES13_REG { - Uint32 all; - struct SOFTPRES13_BITS bit; -}; - -struct SOFTPRES14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit - Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit - Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit - Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit - Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit - Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit - Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES14_REG { - Uint32 all; - struct SOFTPRES14_BITS bit; -}; - -struct SOFTPRES15_BITS { // bits description - Uint16 PGA1:1; // 0 PGA1 software reset bit - Uint16 PGA2:1; // 1 PGA2 software reset bit - Uint16 PGA3:1; // 2 PGA3 software reset bit - Uint16 PGA4:1; // 3 PGA4 software reset bit - Uint16 PGA5:1; // 4 PGA5 software reset bit - Uint16 PGA6:1; // 5 PGA6 software reset bit - Uint16 PGA7:1; // 6 PGA7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES15_REG { - Uint32 all; - struct SOFTPRES15_BITS bit; -}; - -struct SOFTPRES16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit - Uint16 rsvd6:1; // 18 Reserved - Uint16 rsvd7:1; // 19 Reserved - Uint16 rsvd8:12; // 31:20 Reserved -}; - -union SOFTPRES16_REG { - Uint32 all; - struct SOFTPRES16_BITS bit; -}; - -struct SOFTPRES19_BITS { // bits description - Uint16 LIN_A:1; // 0 LIN_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES19_REG { - Uint32 all; - struct SOFTPRES19_BITS bit; -}; - -struct SOFTPRES20_BITS { // bits description - Uint16 PMBUS_A:1; // 0 PMBUS_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES20_REG { - Uint32 all; - struct SOFTPRES20_BITS bit; -}; - -struct TAP_STATUS_BITS { // bits description - Uint16 TAP_STATE:16; // 15:0 Present TAP State - Uint16 rsvd1:15; // 30:16 Reserved - Uint16 DCON:1; // 31 Debugger Connect Indication -}; - -union TAP_STATUS_REG { - Uint32 all; - struct TAP_STATUS_BITS bit; -}; - -struct DEV_CFG_REGS { - Uint16 rsvd1[8]; // Reserved - union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number - union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number - union REVID_REG REVID; // Device Revision Number - Uint16 rsvd2[102]; // Reserved - union FUSEERR_REG FUSEERR; // e-Fuse error Status register - Uint16 rsvd3[12]; // Reserved - union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register - Uint16 rsvd4[2]; // Reserved - union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register - union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register - union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register - Uint16 rsvd5[2]; // Reserved - union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register - union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register - union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register - union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register - union SOFTPRES10_REG SOFTPRES10; // Peripheral Software Reset register - Uint16 rsvd6[4]; // Reserved - union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register - union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register - union SOFTPRES15_REG SOFTPRES15; // Peripheral Software Reset register - union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register - Uint16 rsvd7[4]; // Reserved - union SOFTPRES19_REG SOFTPRES19; // Peripheral Software Reset register - union SOFTPRES20_REG SOFTPRES20; // Peripheral Software Reset register - Uint16 rsvd8[132]; // Reserved - union TAP_STATUS_REG TAP_STATUS; // Status of JTAG State machine & Debugger Connect - Uint16 rsvd9[78]; // Reserved -}; - -struct CLKCFGLOCK1_BITS { // bits description - Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register - Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register - Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register - Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register - Uint16 rsvd7:1; // 12 Reserved - Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register - Uint16 rsvd8:1; // 14 Reserved - Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register - Uint16 XTALCR:1; // 16 Lock bit for XTALCR register - Uint16 rsvd9:15; // 31:17 Reserved -}; - -union CLKCFGLOCK1_REG { - Uint32 all; - struct CLKCFGLOCK1_BITS bit; -}; - -struct CLKSRCCTL1_BITS { // bits description - Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit - Uint16 rsvd2:1; // 4 Reserved - Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit - Uint16 rsvd3:10; // 15:6 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CLKSRCCTL1_REG { - Uint32 all; - struct CLKSRCCTL1_BITS bit; -}; - -struct CLKSRCCTL2_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit - Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union CLKSRCCTL2_REG { - Uint32 all; - struct CLKSRCCTL2_BITS bit; -}; - -struct CLKSRCCTL3_BITS { // bits description - Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLKSRCCTL3_REG { - Uint32 all; - struct CLKSRCCTL3_BITS bit; -}; - -struct SYSPLLCTL1_BITS { // bits description - Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit - Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLCTL1_REG { - Uint32 all; - struct SYSPLLCTL1_BITS bit; -}; - -struct SYSPLLMULT_BITS { // bits description - Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier - Uint16 rsvd1:1; // 7 Reserved - Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 ODIV:3; // 18:16 Output Clock Divider - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 rsvd4:6; // 29:24 Reserved - Uint16 rsvd5:2; // 31:30 Reserved -}; - -union SYSPLLMULT_REG { - Uint32 all; - struct SYSPLLMULT_BITS bit; -}; - -struct SYSPLLSTS_BITS { // bits description - Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit - Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLSTS_REG { - Uint32 all; - struct SYSPLLSTS_BITS bit; -}; - -struct SYSCLKDIVSEL_BITS { // bits description - Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSCLKDIVSEL_REG { - Uint32 all; - struct SYSCLKDIVSEL_BITS bit; -}; - -struct XCLKOUTDIVSEL_BITS { // bits description - Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XCLKOUTDIVSEL_REG { - Uint32 all; - struct XCLKOUTDIVSEL_BITS bit; -}; - -struct LOSPCP_BITS { // bits description - Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOSPCP_REG { - Uint32 all; - struct LOSPCP_BITS bit; -}; - -struct MCDCR_BITS { // bits description - Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit - Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit - Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit - Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MCDCR_REG { - Uint32 all; - struct MCDCR_BITS bit; -}; - -struct X1CNT_BITS { // bits description - Uint16 X1CNT:10; // 9:0 X1 Counter - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 CLR:1; // 16 X1 Counter Clear - Uint16 rsvd2:15; // 31:17 Reserved -}; - -union X1CNT_REG { - Uint32 all; - struct X1CNT_BITS bit; -}; - -struct XTALCR_BITS { // bits description - Uint16 OSCOFF:1; // 0 XTAL Oscillator powered-down - Uint16 SE:1; // 1 XTAL Oscilator in Single-Ended mode - Uint16 SWH:1; // 2 XTAL Oscilator Operation range - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XTALCR_REG { - Uint32 all; - struct XTALCR_BITS bit; -}; - -struct CLK_CFG_REGS { - Uint16 rsvd1[2]; // Reserved - union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers - Uint16 rsvd2[4]; // Reserved - union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 - union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 - union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 - union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 - Uint16 rsvd3[4]; // Reserved - union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register - union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register - Uint16 rsvd4[10]; // Reserved - union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register - Uint16 rsvd5[4]; // Reserved - union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register - Uint16 rsvd6[2]; // Reserved - union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar - union MCDCR_REG MCDCR; // Missing Clock Detect Control Register - union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock - union XTALCR_REG XTALCR; // XTAL Control Register - Uint16 rsvd7[2]; // Reserved -}; - -struct CPUSYSLOCK1_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register - Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register - Uint16 rsvd3:1; // 4 Reserved - Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register - Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register - Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register - Uint16 rsvd4:1; // 8 Reserved - Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register - Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register - Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register - Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register - Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register - Uint16 rsvd5:1; // 14 Reserved - Uint16 rsvd6:1; // 15 Reserved - Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register - Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register - Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register - Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register - Uint16 rsvd7:1; // 20 Reserved - Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register - Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register - Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register - Uint16 PCLKCR17:1; // 24 Lock bit for PCLKCR17 Register - Uint16 PCLKCR18:1; // 25 Lock bit for PCLKCR18 Register - Uint16 PCLKCR19:1; // 26 Lock bit for PCLKCR19 Register - Uint16 PCLKCR20:1; // 27 Lock bit for PCLKCR20 Register - Uint16 PCLKCR21:1; // 28 Lock bit for PCLKCR21 Register - Uint16 rsvd8:1; // 29 Reserved - Uint16 rsvd9:1; // 30 Reserved - Uint16 rsvd10:1; // 31 Reserved -}; - -union CPUSYSLOCK1_REG { - Uint32 all; - struct CPUSYSLOCK1_BITS bit; -}; - -struct PIEVERRADDR_BITS { // bits description - Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PIEVERRADDR_REG { - Uint32 all; - struct PIEVERRADDR_BITS bit; -}; - -struct PCLKCR0_BITS { // bits description - Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 DMA:1; // 2 DMA Clock Enable bit - Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit - Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit - Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit - Uint16 rsvd3:1; // 17 Reserved - Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync - Uint16 rsvd4:1; // 19 Reserved - Uint16 rsvd5:12; // 31:20 Reserved -}; - -union PCLKCR0_REG { - Uint32 all; - struct PCLKCR0_BITS bit; -}; - -struct PCLKCR2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit - Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit - Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit - Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit - Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit - Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit - Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit - Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union PCLKCR2_REG { - Uint32 all; - struct PCLKCR2_BITS bit; -}; - -struct PCLKCR3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit - Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit - Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit - Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit - Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit - Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit - Uint16 ECAP7:1; // 6 ECAP7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR3_REG { - Uint32 all; - struct PCLKCR3_BITS bit; -}; - -struct PCLKCR4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit - Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR4_REG { - Uint32 all; - struct PCLKCR4_BITS bit; -}; - -struct PCLKCR6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint16 rsvd7:1; // 7 Reserved - Uint16 rsvd8:8; // 15:8 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union PCLKCR6_REG { - Uint32 all; - struct PCLKCR6_BITS bit; -}; - -struct PCLKCR7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit - Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR7_REG { - Uint32 all; - struct PCLKCR7_BITS bit; -}; - -struct PCLKCR8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit - Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:1; // 16 Reserved - Uint16 rsvd5:1; // 17 Reserved - Uint16 rsvd6:14; // 31:18 Reserved -}; - -union PCLKCR8_REG { - Uint32 all; - struct PCLKCR8_BITS bit; -}; - -struct PCLKCR9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR9_REG { - Uint32 all; - struct PCLKCR9_BITS bit; -}; - -struct PCLKCR10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit - Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR10_REG { - Uint32 all; - struct PCLKCR10_BITS bit; -}; - -struct PCLKCR13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit - Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit - Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR13_REG { - Uint32 all; - struct PCLKCR13_BITS bit; -}; - -struct PCLKCR14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit - Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit - Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit - Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit - Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit - Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit - Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR14_REG { - Uint32 all; - struct PCLKCR14_BITS bit; -}; - -struct PCLKCR15_BITS { // bits description - Uint16 PGA1:1; // 0 PGA1 Clock Enable bit - Uint16 PGA2:1; // 1 PGA2 Clock Enable bit - Uint16 PGA3:1; // 2 PGA3 Clock Enable bit - Uint16 PGA4:1; // 3 PGA4 Clock Enable bit - Uint16 PGA5:1; // 4 PGA5 Clock Enable bit - Uint16 PGA6:1; // 5 PGA6 Clock Enable bit - Uint16 PGA7:1; // 6 PGA7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR15_REG { - Uint32 all; - struct PCLKCR15_BITS bit; -}; - -struct PCLKCR16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit - Uint16 rsvd6:1; // 18 Reserved - Uint16 rsvd7:1; // 19 Reserved - Uint16 rsvd8:12; // 31:20 Reserved -}; - -union PCLKCR16_REG { - Uint32 all; - struct PCLKCR16_BITS bit; -}; - -struct PCLKCR19_BITS { // bits description - Uint16 LIN_A:1; // 0 LIN_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union PCLKCR19_REG { - Uint32 all; - struct PCLKCR19_BITS bit; -}; - -struct PCLKCR20_BITS { // bits description - Uint16 PMBUS_A:1; // 0 PMBUS_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR20_REG { - Uint32 all; - struct PCLKCR20_BITS bit; -}; - -struct PCLKCR21_BITS { // bits description - Uint16 DCC_0:1; // 0 DCC_0 Clock Enable Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR21_REG { - Uint32 all; - struct PCLKCR21_BITS bit; -}; - -struct LPMCR_BITS { // bits description - Uint16 LPM:2; // 1:0 Low Power Mode setting - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 rsvd2:7; // 14:8 Reserved - Uint16 rsvd3:1; // 15 Reserved - Uint16 rsvd4:2; // 17:16 Reserved - Uint16 rsvd5:13; // 30:18 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union LPMCR_REG { - Uint32 all; - struct LPMCR_BITS bit; -}; - -struct GPIOLPMSEL0_BITS { // bits description - Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup - Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup - Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup - Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup - Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup - Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup - Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup - Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup - Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup - Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup - Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup - Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup - Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup - Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup - Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup - Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup - Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup - Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup - Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup - Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup - Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup - Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup - Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup - Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup - Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup - Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup - Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup - Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup - Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup - Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup - Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup - Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup -}; - -union GPIOLPMSEL0_REG { - Uint32 all; - struct GPIOLPMSEL0_BITS bit; -}; - -struct GPIOLPMSEL1_BITS { // bits description - Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup - Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup - Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup - Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup - Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup - Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup - Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup - Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup - Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup - Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup - Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup - Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup - Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup - Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup - Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup - Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup - Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup - Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup - Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup - Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup - Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup - Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup - Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup - Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup - Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup - Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup - Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup - Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup - Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup - Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup - Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup - Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup -}; - -union GPIOLPMSEL1_REG { - Uint32 all; - struct GPIOLPMSEL1_BITS bit; -}; - -struct TMR2CLKCTL_BITS { // bits description - Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit - Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TMR2CLKCTL_REG { - Uint32 all; - struct TMR2CLKCTL_BITS bit; -}; - -struct RESCCLR_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd5:7; // 15:9 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union RESCCLR_REG { - Uint32 all; - struct RESCCLR_BITS bit; -}; - -struct RESC_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd5:7; // 15:9 Reserved - Uint16 rsvd6:14; // 29:16 Reserved - Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status - Uint16 DCON:1; // 31 Debugger conntion status to C28x -}; - -union RESC_REG { - Uint32 all; - struct RESC_BITS bit; -}; - -struct CPU_SYS_REGS { - union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers - Uint16 rsvd1[8]; // Reserved - union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register - Uint16 rsvd2[22]; // Reserved - union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers - Uint16 rsvd3[2]; // Reserved - union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers - union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers - union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers - Uint16 rsvd4[2]; // Reserved - union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers - union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers - union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers - union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers - union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers - Uint16 rsvd5[4]; // Reserved - union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers - union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers - union PCLKCR15_REG PCLKCR15; // Peripheral Clock Gating Registers - union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers - Uint16 rsvd6[4]; // Reserved - union PCLKCR19_REG PCLKCR19; // Peripheral Clock Gating Registers - union PCLKCR20_REG PCLKCR20; // Peripheral Clock Gating Registers - union PCLKCR21_REG PCLKCR21; // Peripheral Clock Gating Registers - Uint16 rsvd7[40]; // Reserved - union LPMCR_REG LPMCR; // LPM Control Register - union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers - union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers - union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register - union RESCCLR_REG RESCCLR; // Reset Cause Clear Register - union RESC_REG RESC; // Reset Cause register -}; - -struct SCSR_BITS { // bits description - Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit - Uint16 WDENINT:1; // 1 WD Interrupt Enable - Uint16 WDINTS:1; // 2 WD Interrupt Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union SCSR_REG { - Uint16 all; - struct SCSR_BITS bit; -}; - -struct WDCNTR_BITS { // bits description - Uint16 WDCNTR:8; // 7:0 WD Counter - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDCNTR_REG { - Uint16 all; - struct WDCNTR_BITS bit; -}; - -struct WDKEY_BITS { // bits description - Uint16 WDKEY:8; // 7:0 Key to pet the watchdog timer. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDKEY_REG { - Uint16 all; - struct WDKEY_BITS bit; -}; - -struct WDCR_BITS { // bits description - Uint16 WDPS:3; // 2:0 WD Clock Prescalar - Uint16 WDCHK:3; // 5:3 WD Check Bits - Uint16 WDDIS:1; // 6 WD Disable - Uint16 rsvd1:1; // 7 Reserved - Uint16 WDPRECLKDIV:4; // 11:8 WD Pre Clock Divider - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union WDCR_REG { - Uint16 all; - struct WDCR_BITS bit; -}; - -struct WDWCR_BITS { // bits description - Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union WDWCR_REG { - Uint16 all; - struct WDWCR_BITS bit; -}; - -struct WD_REGS { - Uint16 rsvd1[34]; // Reserved - union SCSR_REG SCSR; // System Control & Status Register - union WDCNTR_REG WDCNTR; // Watchdog Counter Register - Uint16 rsvd2; // Reserved - union WDKEY_REG WDKEY; // Watchdog Reset Key Register - Uint16 rsvd3[3]; // Reserved - union WDCR_REG WDCR; // Watchdog Control Register - union WDWCR_REG WDWCR; // Watchdog Windowed Control Register -}; - -struct CLA1TASKSRCSELLOCK_BITS { // bits description - Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit - Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLA1TASKSRCSELLOCK_REG { - Uint32 all; - struct CLA1TASKSRCSELLOCK_BITS bit; -}; - -struct DMACHSRCSELLOCK_BITS { // bits description - Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit - Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DMACHSRCSELLOCK_REG { - Uint32 all; - struct DMACHSRCSELLOCK_BITS bit; -}; - -struct CLA1TASKSRCSEL1_BITS { // bits description - Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 - Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 - Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 - Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 -}; - -union CLA1TASKSRCSEL1_REG { - Uint32 all; - struct CLA1TASKSRCSEL1_BITS bit; -}; - -struct CLA1TASKSRCSEL2_BITS { // bits description - Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 - Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 - Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 - Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 -}; - -union CLA1TASKSRCSEL2_REG { - Uint32 all; - struct CLA1TASKSRCSEL2_BITS bit; -}; - -struct DMACHSRCSEL1_BITS { // bits description - Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA - Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA - Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA - Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA -}; - -union DMACHSRCSEL1_REG { - Uint32 all; - struct DMACHSRCSEL1_BITS bit; -}; - -struct DMACHSRCSEL2_BITS { // bits description - Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA - Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union DMACHSRCSEL2_REG { - Uint32 all; - struct DMACHSRCSEL2_BITS bit; -}; - -struct DMA_CLA_SRC_SEL_REGS { - union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register - Uint16 rsvd1[2]; // Reserved - union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register - union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 - union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 - Uint16 rsvd2[12]; // Reserved - union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 - union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 -}; - -struct ADCA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCA_AC_REG { - Uint32 all; - struct ADCA_AC_BITS bit; -}; - -struct ADCB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCB_AC_REG { - Uint32 all; - struct ADCB_AC_BITS bit; -}; - -struct ADCC_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCC_AC_REG { - Uint32 all; - struct ADCC_AC_BITS bit; -}; - -struct CMPSS1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS1_AC_REG { - Uint32 all; - struct CMPSS1_AC_BITS bit; -}; - -struct CMPSS2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS2_AC_REG { - Uint32 all; - struct CMPSS2_AC_BITS bit; -}; - -struct CMPSS3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS3_AC_REG { - Uint32 all; - struct CMPSS3_AC_BITS bit; -}; - -struct CMPSS4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS4_AC_REG { - Uint32 all; - struct CMPSS4_AC_BITS bit; -}; - -struct CMPSS5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS5_AC_REG { - Uint32 all; - struct CMPSS5_AC_BITS bit; -}; - -struct CMPSS6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS6_AC_REG { - Uint32 all; - struct CMPSS6_AC_BITS bit; -}; - -struct CMPSS7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS7_AC_REG { - Uint32 all; - struct CMPSS7_AC_BITS bit; -}; - -struct DACA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DACA_AC_REG { - Uint32 all; - struct DACA_AC_BITS bit; -}; - -struct DACB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DACB_AC_REG { - Uint32 all; - struct DACB_AC_BITS bit; -}; - -struct PGA1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA1_AC_REG { - Uint32 all; - struct PGA1_AC_BITS bit; -}; - -struct PGA2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA2_AC_REG { - Uint32 all; - struct PGA2_AC_BITS bit; -}; - -struct PGA3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA3_AC_REG { - Uint32 all; - struct PGA3_AC_BITS bit; -}; - -struct PGA4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA4_AC_REG { - Uint32 all; - struct PGA4_AC_BITS bit; -}; - -struct PGA5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA5_AC_REG { - Uint32 all; - struct PGA5_AC_BITS bit; -}; - -struct PGA6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA6_AC_REG { - Uint32 all; - struct PGA6_AC_BITS bit; -}; - -struct PGA7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA7_AC_REG { - Uint32 all; - struct PGA7_AC_BITS bit; -}; - -struct EPWM1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM1_AC_REG { - Uint32 all; - struct EPWM1_AC_BITS bit; -}; - -struct EPWM2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM2_AC_REG { - Uint32 all; - struct EPWM2_AC_BITS bit; -}; - -struct EPWM3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM3_AC_REG { - Uint32 all; - struct EPWM3_AC_BITS bit; -}; - -struct EPWM4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM4_AC_REG { - Uint32 all; - struct EPWM4_AC_BITS bit; -}; - -struct EPWM5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM5_AC_REG { - Uint32 all; - struct EPWM5_AC_BITS bit; -}; - -struct EPWM6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM6_AC_REG { - Uint32 all; - struct EPWM6_AC_BITS bit; -}; - -struct EPWM7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM7_AC_REG { - Uint32 all; - struct EPWM7_AC_BITS bit; -}; - -struct EPWM8_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM8_AC_REG { - Uint32 all; - struct EPWM8_AC_BITS bit; -}; - -struct EQEP1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EQEP1_AC_REG { - Uint32 all; - struct EQEP1_AC_BITS bit; -}; - -struct EQEP2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EQEP2_AC_REG { - Uint32 all; - struct EQEP2_AC_BITS bit; -}; - -struct ECAP1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP1_AC_REG { - Uint32 all; - struct ECAP1_AC_BITS bit; -}; - -struct ECAP2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP2_AC_REG { - Uint32 all; - struct ECAP2_AC_BITS bit; -}; - -struct ECAP3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP3_AC_REG { - Uint32 all; - struct ECAP3_AC_BITS bit; -}; - -struct ECAP4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP4_AC_REG { - Uint32 all; - struct ECAP4_AC_BITS bit; -}; - -struct ECAP5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP5_AC_REG { - Uint32 all; - struct ECAP5_AC_BITS bit; -}; - -struct ECAP6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP6_AC_REG { - Uint32 all; - struct ECAP6_AC_BITS bit; -}; - -struct ECAP7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP7_AC_REG { - Uint32 all; - struct ECAP7_AC_BITS bit; -}; - -struct SDFM1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SDFM1_AC_REG { - Uint32 all; - struct SDFM1_AC_BITS bit; -}; - -struct CLB1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB1_AC_REG { - Uint32 all; - struct CLB1_AC_BITS bit; -}; - -struct CLB2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB2_AC_REG { - Uint32 all; - struct CLB2_AC_BITS bit; -}; - -struct CLB3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB3_AC_REG { - Uint32 all; - struct CLB3_AC_BITS bit; -}; - -struct CLB4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB4_AC_REG { - Uint32 all; - struct CLB4_AC_BITS bit; -}; - -struct CLA1PROMCRC_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLA1PROMCRC_AC_REG { - Uint32 all; - struct CLA1PROMCRC_AC_BITS bit; -}; - -struct SPIA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SPIA_AC_REG { - Uint32 all; - struct SPIA_AC_BITS bit; -}; - -struct SPIB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SPIB_AC_REG { - Uint32 all; - struct SPIB_AC_BITS bit; -}; - -struct PMBUS_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBUS_A_AC_REG { - Uint32 all; - struct PMBUS_A_AC_BITS bit; -}; - -struct LIN_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LIN_A_AC_REG { - Uint32 all; - struct LIN_A_AC_BITS bit; -}; - -struct DCANA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DCANA_AC_REG { - Uint32 all; - struct DCANA_AC_BITS bit; -}; - -struct DCANB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DCANB_AC_REG { - Uint32 all; - struct DCANB_AC_BITS bit; -}; - -struct FSIATX_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FSIATX_AC_REG { - Uint32 all; - struct FSIATX_AC_BITS bit; -}; - -struct FSIARX_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FSIARX_AC_REG { - Uint32 all; - struct FSIARX_AC_BITS bit; -}; - -struct HRPWM_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRPWM_A_AC_REG { - Uint32 all; - struct HRPWM_A_AC_BITS bit; -}; - -struct PERIPH_AC_LOCK_BITS { // bits description - Uint16 LOCK_AC_WR:1; // 0 Lock control for Access control registers write. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PERIPH_AC_LOCK_REG { - Uint32 all; - struct PERIPH_AC_LOCK_BITS bit; -}; - -struct PERIPH_AC_REGS { - union ADCA_AC_REG ADCA_AC; // ADCA Master Access Control Register - union ADCB_AC_REG ADCB_AC; // ADCB Master Access Control Register - union ADCC_AC_REG ADCC_AC; // ADCC Master Access Control Register - Uint16 rsvd1[10]; // Reserved - union CMPSS1_AC_REG CMPSS1_AC; // CMPSS1 Master Access Control Register - union CMPSS2_AC_REG CMPSS2_AC; // CMPSS2 Master Access Control Register - union CMPSS3_AC_REG CMPSS3_AC; // CMPSS3 Master Access Control Register - union CMPSS4_AC_REG CMPSS4_AC; // CMPSS4 Master Access Control Register - union CMPSS5_AC_REG CMPSS5_AC; // CMPSS5 Master Access Control Register - union CMPSS6_AC_REG CMPSS6_AC; // CMPSS6 Master Access Control Register - union CMPSS7_AC_REG CMPSS7_AC; // CMPSS7 Master Access Control Register - Uint16 rsvd2[10]; // Reserved - union DACA_AC_REG DACA_AC; // DACA Master Access Control Register - union DACB_AC_REG DACB_AC; // DACB Master Access Control Register - Uint16 rsvd3[12]; // Reserved - union PGA1_AC_REG PGA1_AC; // PGAA Master Access Control Register - union PGA2_AC_REG PGA2_AC; // PGAB Master Access Control Register - union PGA3_AC_REG PGA3_AC; // PGAC Master Access Control Register - union PGA4_AC_REG PGA4_AC; // PGAD Master Access Control Register - union PGA5_AC_REG PGA5_AC; // PGAE Master Access Control Register - union PGA6_AC_REG PGA6_AC; // PGAF Master Access Control Register - union PGA7_AC_REG PGA7_AC; // PGAG Master Access Control Register - Uint16 rsvd4[2]; // Reserved - union EPWM1_AC_REG EPWM1_AC; // EPWM1 Master Access Control Register - union EPWM2_AC_REG EPWM2_AC; // EPWM2 Master Access Control Register - union EPWM3_AC_REG EPWM3_AC; // EPWM3 Master Access Control Register - union EPWM4_AC_REG EPWM4_AC; // EPWM4 Master Access Control Register - union EPWM5_AC_REG EPWM5_AC; // EPWM5 Master Access Control Register - union EPWM6_AC_REG EPWM6_AC; // EPWM6 Master Access Control Register - union EPWM7_AC_REG EPWM7_AC; // EPWM7 Master Access Control Register - union EPWM8_AC_REG EPWM8_AC; // EPWM8 Master Access Control Register - Uint16 rsvd5[24]; // Reserved - union EQEP1_AC_REG EQEP1_AC; // EQEP1 Master Access Control Register - union EQEP2_AC_REG EQEP2_AC; // EQEP2 Master Access Control Register - Uint16 rsvd6[12]; // Reserved - union ECAP1_AC_REG ECAP1_AC; // ECAP1 Master Access Control Register - union ECAP2_AC_REG ECAP2_AC; // ECAP2 Master Access Control Register - union ECAP3_AC_REG ECAP3_AC; // ECAP3 Master Access Control Register - union ECAP4_AC_REG ECAP4_AC; // ECAP4 Master Access Control Register - union ECAP5_AC_REG ECAP5_AC; // ECAP5 Master Access Control Register - union ECAP6_AC_REG ECAP6_AC; // ECAP6 Master Access Control Register - union ECAP7_AC_REG ECAP7_AC; // ECAP7 Master Access Control Register - Uint16 rsvd7[26]; // Reserved - union SDFM1_AC_REG SDFM1_AC; // SDFM1 Master Access Control Register - Uint16 rsvd8[6]; // Reserved - union CLB1_AC_REG CLB1_AC; // CLB1 Master Access Control Register - union CLB2_AC_REG CLB2_AC; // CLB2 Master Access Control Register - union CLB3_AC_REG CLB3_AC; // CLB3 Master Access Control Register - union CLB4_AC_REG CLB4_AC; // CLB4 Master Access Control Register - Uint16 rsvd9[8]; // Reserved - union CLA1PROMCRC_AC_REG CLA1PROMCRC_AC; // CLA1PROMCRC Master Access Control Register - Uint16 rsvd10[78]; // Reserved - union SPIA_AC_REG SPIA_AC; // SPIA Master Access Control Register - union SPIB_AC_REG SPIB_AC; // SPIB Master Access Control Register - Uint16 rsvd11[28]; // Reserved - union PMBUS_A_AC_REG PMBUS_A_AC; // PMBUSA Master Access Control Register - Uint16 rsvd12[6]; // Reserved - union LIN_A_AC_REG LIN_A_AC; // LINA Master Access Control Register - Uint16 rsvd13[6]; // Reserved - union DCANA_AC_REG DCANA_AC; // DCANA Master Access Control Register - union DCANB_AC_REG DCANB_AC; // DCANB Master Access Control Register - Uint16 rsvd14[20]; // Reserved - union FSIATX_AC_REG FSIATX_AC; // FSIA Master Access Control Register - union FSIARX_AC_REG FSIARX_AC; // FSIB Master Access Control Register - Uint16 rsvd15[78]; // Reserved - union HRPWM_A_AC_REG HRPWM_A_AC; // HRPWM Master Access Control Register - Uint16 rsvd16[82]; // Reserved - union PERIPH_AC_LOCK_REG PERIPH_AC_LOCK; // Lock Register to stop Write access to peripheral Access register. -}; - -struct SYNCSELECT_BITS { // bits description - Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 - Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 - Uint16 rsvd1:3; // 8:6 Reserved - Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 - Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 - Uint32 ECAP6SYNCIN:3; // 17:15 Selects Sync Input Source for ECAP6 - Uint16 rsvd2:9; // 26:18 Reserved - Uint16 SYNCOUT:2; // 28:27 Select Syncout Source - Uint16 EPWM1SYNCIN:3; // 31:29 Selects Sync Input Source for EPWM1 -}; - -union SYNCSELECT_REG { - Uint32 all; - struct SYNCSELECT_BITS bit; -}; - -struct ADCSOCOUTSELECT_BITS { // bits description - Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAOn - Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAOn - Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAOn - Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAOn - Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAOn - Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAOn - Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAOn - Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAOn - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:4; // 15:12 Reserved - Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBOn - Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBOn - Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBOn - Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBOn - Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBOn - Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBOn - Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBOn - Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBOn - Uint16 rsvd6:1; // 24 Reserved - Uint16 rsvd7:1; // 25 Reserved - Uint16 rsvd8:1; // 26 Reserved - Uint16 rsvd9:1; // 27 Reserved - Uint16 rsvd10:4; // 31:28 Reserved -}; - -union ADCSOCOUTSELECT_REG { - Uint32 all; - struct ADCSOCOUTSELECT_BITS bit; -}; - -struct SYNCSOCLOCK_BITS { // bits description - Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit - Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYNCSOCLOCK_REG { - Uint32 all; - struct SYNCSOCLOCK_BITS bit; -}; - -struct SYNC_SOC_REGS { - union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register - union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADCSOC Select Register - union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register -}; - -//--------------------------------------------------------------------------- -// SYSCTRL External References & Function Declarations: -// -extern volatile struct WD_REGS WdRegs; -extern volatile struct SYNC_SOC_REGS SyncSocRegs; -extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; -extern volatile struct DEV_CFG_REGS DevCfgRegs; -extern volatile struct CLK_CFG_REGS ClkCfgRegs; -extern volatile struct CPU_SYS_REGS CpuSysRegs; -extern volatile struct PERIPH_AC_REGS SysPeriphAcRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h deleted file mode 100644 index e3cdff0..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h +++ /dev/null @@ -1,372 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_xbar.h -// -// TITLE: XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_XBAR_H__ -#define __F28004X_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XBAR Individual Register Bit Definitions: - -struct XBARFLG1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal -}; - -union XBARFLG1_REG { - Uint32 all; - struct XBARFLG1_BITS bit; -}; - -struct XBARFLG2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal - Uint16 ADCSOCA:1; // 6 Input Flag for ADCSOCA Signal - Uint16 ADCSOCB:1; // 7 Input Flag for ADCSOCB Signal - Uint16 INPUT7:1; // 8 Input Flag for INPUT7 Signal - Uint16 INPUT8:1; // 9 Input Flag for INPUT8 Signal - Uint16 INPUT9:1; // 10 Input Flag for INPUT9 Signal - Uint16 INPUT10:1; // 11 Input Flag for INPUT10\ Signal - Uint16 INPUT11:1; // 12 Input Flag for INPUT11 Signal - Uint16 INPUT12:1; // 13 Input Flag for INPUT12 Signal - Uint16 INPUT13:1; // 14 Input Flag for INPUT13 Signal - Uint16 INPUT14:1; // 15 Input Flag for INPUT14 Signal - Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal -}; - -union XBARFLG2_REG { - Uint32 all; - struct XBARFLG2_BITS bit; -}; - -struct XBARFLG3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 rsvd4:1; // 6 Reserved - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:1; // 17 Reserved - Uint16 rsvd8:1; // 18 Reserved - Uint16 rsvd9:1; // 19 Reserved - Uint16 rsvd10:1; // 20 Reserved - Uint16 rsvd11:1; // 21 Reserved - Uint16 rsvd12:1; // 22 Reserved - Uint16 ECAP7_OUT:1; // 23 Input Flag for ECAP7.OUT Signal - Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag for SD1FLT1.COMPZ Signal - Uint16 SD1FLT1_DRINT:1; // 25 Input Flag for SD1FLT1.DRINT Signal - Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag for SD1FLT2.COMPZ Signal - Uint16 SD1FLT2_DRINT:1; // 27 Input Flag for SD1FLT2.DRINT Signal - Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag for SD1FLT3.COMPZ Signal - Uint16 SD1FLT3_DRINT:1; // 29 Input Flag for SD1FLT3.DRINT Signal - Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag for SD1FLT4.COMPZ Signal - Uint16 SD1FLT4_DRINT:1; // 31 Input Flag for SD1FLT4.DRINT Signal -}; - -union XBARFLG3_REG { - Uint32 all; - struct XBARFLG3_BITS bit; -}; - -struct XBARFLG4_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:8; // 15:8 Reserved - Uint16 rsvd10:1; // 16 Reserved - Uint16 rsvd11:1; // 17 Reserved - Uint16 rsvd12:1; // 18 Reserved - Uint16 rsvd13:1; // 19 Reserved - Uint16 rsvd14:1; // 20 Reserved - Uint16 rsvd15:1; // 21 Reserved - Uint16 rsvd16:1; // 22 Reserved - Uint16 rsvd17:1; // 23 Reserved - Uint16 rsvd18:7; // 30:24 Reserved - Uint16 CLAHALT:1; // 31 Input Flag for CLAHALT Signal -}; - -union XBARFLG4_REG { - Uint32 all; - struct XBARFLG4_BITS bit; -}; - -struct XBARCLR1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal -}; - -union XBARCLR1_REG { - Uint32 all; - struct XBARCLR1_BITS bit; -}; - -struct XBARCLR2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag Clear for INPUT6 Signal - Uint16 ADCSOCA:1; // 6 Input Flag Clear for ADCSOCA Signal - Uint16 ADCSOCB:1; // 7 Input Flag Clear for ADCSOCB Signal - Uint16 INPUT7:1; // 8 Input Flag Clear for INPUT7 Signal - Uint16 INPUT8:1; // 9 Input Flag Clear for INPUT8 Signal - Uint16 INPUT9:1; // 10 Input Flag Clear for INPUT9 Signal - Uint16 INPUT10:1; // 11 Input Flag Clear for INPUT10 Signal - Uint16 INPUT11:1; // 12 Input Flag Clear for INPUT11 Signal - Uint16 INPUT12:1; // 13 Input Flag Clear for INPUT12 Signal - Uint16 INPUT13:1; // 14 Input Flag Clear for INPUT13 Signal - Uint16 INPUT14:1; // 15 Input Flag Clear for INPUT14 Signal - Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal -}; - -union XBARCLR2_REG { - Uint32 all; - struct XBARCLR2_BITS bit; -}; - -struct XBARCLR3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 rsvd4:1; // 6 Reserved - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:1; // 17 Reserved - Uint16 rsvd8:1; // 18 Reserved - Uint16 rsvd9:1; // 19 Reserved - Uint16 rsvd10:1; // 20 Reserved - Uint16 rsvd11:1; // 21 Reserved - Uint16 rsvd12:1; // 22 Reserved - Uint16 ECAP7_OUT:1; // 23 Input Flag clear for ECAP7.OUT Signal - Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag clear for SD1FLT1.COMPZ Signal - Uint16 SD1FLT1_DRINT:1; // 25 Input Flag clear for SD1FLT1.DRINT Signal - Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag clear for SD1FLT2.COMPZ Signal - Uint16 SD1FLT2_DRINT:1; // 27 Input Flag clear for SD1FLT2.DRINT Signal - Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag clear for SD1FLT3.COMPZ Signal - Uint16 SD1FLT3_DRINT:1; // 29 Input Flag clear for SD1FLT3.DRINT Signal - Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag clear for SD1FLT4.COMPZ Signal - Uint16 SD1FLT4_DRINT:1; // 31 Input Flag clear for SD1FLT4.DRINT Signal -}; - -union XBARCLR3_REG { - Uint32 all; - struct XBARCLR3_BITS bit; -}; - -struct XBARCLR4_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:8; // 15:8 Reserved - Uint16 rsvd10:1; // 16 Reserved - Uint16 rsvd11:1; // 17 Reserved - Uint16 rsvd12:1; // 18 Reserved - Uint16 rsvd13:1; // 19 Reserved - Uint16 rsvd14:1; // 20 Reserved - Uint16 rsvd15:1; // 21 Reserved - Uint16 rsvd16:1; // 22 Reserved - Uint16 rsvd17:1; // 23 Reserved - Uint16 rsvd18:7; // 30:24 Reserved - Uint16 CLAHALT:1; // 31 Input Flag clear for CLAHALT Signal -}; - -union XBARCLR4_REG { - Uint32 all; - struct XBARCLR4_BITS bit; -}; - -struct XBAR_REGS { - union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 - union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 - union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 - union XBARFLG4_REG XBARFLG4; // X-Bar Input Flag Register 4 - union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 - union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 - union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 - union XBARCLR4_REG XBARCLR4; // X-Bar Input Flag Clear Register 4 - Uint16 rsvd1[16]; // Reserved -}; - -//--------------------------------------------------------------------------- -// XBAR External References & Function Declarations: -// -extern volatile struct XBAR_REGS XbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h deleted file mode 100644 index 15fd43b..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h +++ /dev/null @@ -1,138 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_xint.h -// -// TITLE: XINT Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_XINT_H__ -#define __F28004X_XINT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XINT Individual Register Bit Definitions: - -struct XINT1CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT1 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT1 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT1CR_REG { - Uint16 all; - struct XINT1CR_BITS bit; -}; - -struct XINT2CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT2 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT2 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT2CR_REG { - Uint16 all; - struct XINT2CR_BITS bit; -}; - -struct XINT3CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT3 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT3 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT3CR_REG { - Uint16 all; - struct XINT3CR_BITS bit; -}; - -struct XINT4CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT4 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT4 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT4CR_REG { - Uint16 all; - struct XINT4CR_BITS bit; -}; - -struct XINT5CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT5 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT5 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT5CR_REG { - Uint16 all; - struct XINT5CR_BITS bit; -}; - -struct XINT_REGS { - union XINT1CR_REG XINT1CR; // XINT1 configuration register - union XINT2CR_REG XINT2CR; // XINT2 configuration register - union XINT3CR_REG XINT3CR; // XINT3 configuration register - union XINT4CR_REG XINT4CR; // XINT4 configuration register - union XINT5CR_REG XINT5CR; // XINT5 configuration register - Uint16 rsvd1[3]; // Reserved - Uint16 XINT1CTR; // XINT1 counter register - Uint16 XINT2CTR; // XINT2 counter register - Uint16 XINT3CTR; // XINT3 counter register -}; - -//--------------------------------------------------------------------------- -// XINT External References & Function Declarations: -// -extern volatile struct XINT_REGS XintRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c b/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c deleted file mode 100644 index 7c862ee..0000000 --- a/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c +++ /dev/null @@ -1,861 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_globalvariabledefs.c -// -// TITLE: F28004x Global Variables and Data Section Pragmas. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#include "f28004x_device.h" // F28004x Headerfile Include File - -//--------------------------------------------------------------------------- -// Define Global Peripheral Variables: -// -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaResultFile") -#else -#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcaResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbResultFile") -#else -#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcbResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccResultFile") -#else -#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdccResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaRegsFile") -#else -#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); -#endif -volatile struct ADC_REGS AdcaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbRegsFile") -#else -#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); -#endif -volatile struct ADC_REGS AdcbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccRegsFile") -#else -#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); -#endif -volatile struct ADC_REGS AdccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AnalogSubsysRegsFile") -#else -#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); -#endif -volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanaRegsFile") -#else -#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); -#endif -volatile struct CAN_REGS CanaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanbRegsFile") -#else -#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); -#endif -volatile struct CAN_REGS CanbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1RegsFile") -#else -#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); -#endif -volatile struct CLA_REGS Cla1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1SoftIntRegsFile") -#else -#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); -#endif -volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClaPromCrc0RegsFile") -#else -#pragma DATA_SECTION(ClaPromCrc0Regs,"ClaPromCrc0RegsFile"); -#endif -volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss1RegsFile") -#else -#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss2RegsFile") -#else -#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss3RegsFile") -#else -#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss4RegsFile") -#else -#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss5RegsFile") -#else -#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss6RegsFile") -#else -#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss7RegsFile") -#else -#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer0RegsFile") -#else -#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer1RegsFile") -#else -#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer2RegsFile") -#else -#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacaRegsFile") -#else -#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); -#endif -volatile struct DAC_REGS DacaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacbRegsFile") -#else -#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); -#endif -volatile struct DAC_REGS DacbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Dcc0RegsFile") -#else -#pragma DATA_SECTION(Dcc0Regs,"Dcc0RegsFile"); -#endif -volatile struct DCC_REGS Dcc0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank0Z1RegsFile") -#else -#pragma DATA_SECTION(DcsmBank0Z1Regs,"DcsmBank0Z1RegsFile"); -#endif -volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank0Z2RegsFile") -#else -#pragma DATA_SECTION(DcsmBank0Z2Regs,"DcsmBank0Z2RegsFile"); -#endif -volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank1Z1RegsFile") -#else -#pragma DATA_SECTION(DcsmBank1Z1Regs,"DcsmBank1Z1RegsFile"); -#endif -volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank1Z2RegsFile") -#else -#pragma DATA_SECTION(DcsmBank1Z2Regs,"DcsmBank1Z2RegsFile"); -#endif -volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmCommonRegsFile") -#else -#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); -#endif -volatile struct DCSM_COMMON_REGS DcsmCommonRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaRegsFile") -#else -#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); -#endif -volatile struct DMA_REGS DmaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap1RegsFile") -#else -#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); -#endif -volatile struct ECAP_REGS ECap1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap2RegsFile") -#else -#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); -#endif -volatile struct ECAP_REGS ECap2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap3RegsFile") -#else -#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); -#endif -volatile struct ECAP_REGS ECap3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap4RegsFile") -#else -#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); -#endif -volatile struct ECAP_REGS ECap4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap5RegsFile") -#else -#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); -#endif -volatile struct ECAP_REGS ECap5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap6RegsFile") -#else -#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); -#endif -volatile struct ECAP_REGS ECap6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap7RegsFile") -#else -#pragma DATA_SECTION(ECap7Regs,"ECap7RegsFile"); -#endif -volatile struct ECAP_REGS ECap7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga1RegsFile") -#else -#pragma DATA_SECTION(Pga1Regs,"Pga1RegsFile"); -#endif -volatile struct PGA_REGS Pga1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga2RegsFile") -#else -#pragma DATA_SECTION(Pga2Regs,"Pga2RegsFile"); -#endif -volatile struct PGA_REGS Pga2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga3RegsFile") -#else -#pragma DATA_SECTION(Pga3Regs,"Pga3RegsFile"); -#endif -volatile struct PGA_REGS Pga3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga4RegsFile") -#else -#pragma DATA_SECTION(Pga4Regs,"Pga4RegsFile"); -#endif -volatile struct PGA_REGS Pga4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga5RegsFile") -#else -#pragma DATA_SECTION(Pga5Regs,"Pga5RegsFile"); -#endif -volatile struct PGA_REGS Pga5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga6RegsFile") -#else -#pragma DATA_SECTION(Pga6Regs,"Pga6RegsFile"); -#endif -volatile struct PGA_REGS Pga6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga7RegsFile") -#else -#pragma DATA_SECTION(Pga7Regs,"Pga7RegsFile"); -#endif -volatile struct PGA_REGS Pga7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm1RegsFile") -#else -#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); -#endif -volatile struct EPWM_REGS EPwm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm2RegsFile") -#else -#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); -#endif -volatile struct EPWM_REGS EPwm2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm3RegsFile") -#else -#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); -#endif -volatile struct EPWM_REGS EPwm3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm4RegsFile") -#else -#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); -#endif -volatile struct EPWM_REGS EPwm4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm5RegsFile") -#else -#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); -#endif -volatile struct EPWM_REGS EPwm5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm6RegsFile") -#else -#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); -#endif -volatile struct EPWM_REGS EPwm6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm7RegsFile") -#else -#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); -#endif -volatile struct EPWM_REGS EPwm7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm8RegsFile") -#else -#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); -#endif -volatile struct EPWM_REGS EPwm8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwmXbarRegsFile") -#else -#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); -#endif -volatile struct EPWM_XBAR_REGS EPwmXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep1RegsFile") -#else -#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); -#endif -volatile struct EQEP_REGS EQep1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep2RegsFile") -#else -#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); -#endif -volatile struct EQEP_REGS EQep2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0CtrlRegsFile") -#else -#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); -#endif -volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0EccRegsFile") -#else -#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); -#endif -volatile struct FLASH_ECC_REGS Flash0EccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("FsiTxaRegsFile") -#else -#pragma DATA_SECTION(FsiTxaRegs,"FsiTxaRegsFile"); -#endif -volatile struct FSI_TX_REGS FsiTxaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("FsiRxaRegsFile") -#else -#pragma DATA_SECTION(FsiRxaRegs,"FsiRxaRegsFile"); -#endif -volatile struct FSI_RX_REGS FsiRxaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioCtrlRegsFile") -#else -#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); -#endif -volatile struct GPIO_CTRL_REGS GpioCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioDataRegsFile") -#else -#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); -#endif -volatile struct GPIO_DATA_REGS GpioDataRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XbarRegsFile") -#else -#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); -#endif -volatile struct XBAR_REGS XbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("I2caRegsFile") -#else -#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); -#endif -volatile struct I2C_REGS I2caRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("InputXbarRegsFile") -#else -#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); -#endif -volatile struct INPUT_XBAR_REGS InputXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("LinaRegsFile") -#else -#pragma DATA_SECTION(LinaRegs,"LinaRegsFile"); -#endif -volatile struct LIN_REGS LinaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("LinbRegsFile") -#else -#pragma DATA_SECTION(LinbRegs,"LinbRegsFile"); -#endif -volatile struct LIN_REGS LinbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemCfgRegsFile") -#else -#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); -#endif -volatile struct MEM_CFG_REGS MemCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AccessProtectionRegsFile") -#else -#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); -#endif -volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemoryErrorRegsFile") -#else -#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); -#endif -volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("NmiIntruptRegsFile") -#else -#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); -#endif -volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("OutputXbarRegsFile") -#else -#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); -#endif -volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieCtrlRegsFile") -#else -#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); -#endif -volatile struct PIE_CTRL_REGS PieCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieVectTableFile") -#else -#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); -#endif -volatile struct PIE_VECT_TABLE PieVectTable; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PmbusaRegsFile") -#else -#pragma DATA_SECTION(PmbusaRegs,"PmbusaRegsFile"); -#endif -volatile struct PMBUS_REGS PmbusaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SciaRegsFile") -#else -#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); -#endif -volatile struct SCI_REGS SciaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ScibRegsFile") -#else -#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); -#endif -volatile struct SCI_REGS ScibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Sdfm1RegsFile") -#else -#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); -#endif -volatile struct SDFM_REGS Sdfm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpiaRegsFile") -#else -#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); -#endif -volatile struct SPI_REGS SpiaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpibRegsFile") -#else -#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); -#endif -volatile struct SPI_REGS SpibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("WdRegsFile") -#else -#pragma DATA_SECTION(WdRegs,"WdRegsFile"); -#endif -volatile struct WD_REGS WdRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaClaSrcSelRegsFile") -#else -#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); -#endif -volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DevCfgRegsFile") -#else -#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); -#endif -volatile struct DEV_CFG_REGS DevCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClkCfgRegsFile") -#else -#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); -#endif -volatile struct CLK_CFG_REGS ClkCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuSysRegsFile") -#else -#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); -#endif -volatile struct CPU_SYS_REGS CpuSysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SysPeriphAcRegsFile") -#else -#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); -#endif -volatile struct PERIPH_AC_REGS SysPeriphAcRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugGlobalRegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugGlobalRegs,"EnhancedDebugGlobalRegsFile"); -#endif -volatile struct ERAD_GLOBAL_REGS EnhancedDebugGlobalRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP1RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP1Regs,"EnhancedDebugHWBP1RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP2RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP2Regs,"EnhancedDebugHWBP2RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP3RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP3Regs,"EnhancedDebugHWBP3RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP4RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP4Regs,"EnhancedDebugHWBP4RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP5RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP5Regs,"EnhancedDebugHWBP5RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP6RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP6Regs,"EnhancedDebugHWBP6RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP7RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP7Regs,"EnhancedDebugHWBP7RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP8RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP8Regs,"EnhancedDebugHWBP8RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter1RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter1Regs,"EnhancedDebugCounter1RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter2RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter2Regs,"EnhancedDebugCounter2RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter3RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter3Regs,"EnhancedDebugCounter3RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter4RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter4Regs,"EnhancedDebugCounter4RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SyncSocRegsFile") -#else -#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); -#endif -volatile struct SYNC_SOC_REGS SyncSocRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XintRegsFile") -#else -#pragma DATA_SECTION(XintRegs,"XintRegsFile"); -#endif -volatile struct XINT_REGS XintRegs; - - - -//=========================================================================== -// End of file. -//=========================================================================== - diff --git a/els-f280049c/launchxl_ex1_sci_io.c b/els-f280049c/launchxl_ex1_sci_io.c new file mode 100644 index 0000000..4f67a39 --- /dev/null +++ b/els-f280049c/launchxl_ex1_sci_io.c @@ -0,0 +1,284 @@ +//############################################################################# +// +// FILE: launchxl_ex1_sci_io.c +// +// TITLE: Contains the various functions related to the serial +// communications interface (SCI) object +// +//############################################################################# +// $TI Release: F28004x Support Library v1.10.00.00 $ +// $Release Date: Tue May 26 17:06:03 IST 2020 $ +// $Copyright: +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include +#include +#include +#include + +#include "F28x_Project.h" +#include "launchxl_ex1_sci_io.h" + +// +// Defines +// + +// +// Globals +// +uint16_t deviceOpen = 0; +uint16_t deviceOpenB = 0; + +// +// Functions +// + +// +// SCI_open - +// +int SCI_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpen) + { + return (-1); + } + else + { + deviceOpen = 1; + return (1); + } +} + +// +// SCI_close - +// +int SCI_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpen)) + { + return (-1); + } + else + { + deviceOpen = 0; + return (0); + } +} + +// +// SCI_read - +// +int SCI_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = SciaRegs.SCIRXBUF.all; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - +// +int SCI_write(int dev_fd, const char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(!SciaRegs.SCICTL2.bit.TXRDY); + SciaRegs.SCITXBUF.all = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - +// +off_t SCI_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - +// +int SCI_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - +// +int SCI_rename(const char * old_name, const char * new_name) +{ + return (0); +} + + + + + + +// KVV +// +// SCI_open - +// +int SCIB_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpenB) + { + return (-1); + } + else + { + deviceOpenB = 1; + return (1); + } +} + +// +// SCI_close - +// +int SCIB_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpenB)) + { + return (-1); + } + else + { + deviceOpenB = 0; + return (0); + } +} + +// +// SCI_read - +// +int SCIB_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && ScibRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = ScibRegs.SCIRXBUF.all; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - +// +int SCIB_write(int dev_fd, const char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(!ScibRegs.SCICTL2.bit.TXRDY); + ScibRegs.SCITXBUF.all = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - +// +off_t SCIB_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - +// +int SCIB_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - +// +int SCIB_rename(const char * old_name, const char * new_name) +{ + return (0); +} + +// +// End of File +// + diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h b/els-f280049c/launchxl_ex1_sci_io.h similarity index 59% rename from els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h rename to els-f280049c/launchxl_ex1_sci_io.h index 4565488..bd3bab0 100644 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h +++ b/els-f280049c/launchxl_ex1_sci_io.h @@ -1,14 +1,18 @@ -//########################################################################### +#ifndef _SCI_IO_H_ +#define _SCI_IO_H_ + +//############################################################################# // -// FILE: f28004x_adc_defines.h +// FILE: launchxl_ex1_sci_io.h // -// TITLE: #defines used in ADC examples +// TITLE: Contains public interface to various functions related +// to the serial communications interface (SCI) object // -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ +//############################################################################# +// $TI Release: F28004x Support Library v1.10.00.00 $ +// $Release Date: Tue May 26 17:06:03 IST 2020 $ // $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -38,46 +42,44 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ -//########################################################################### - -#ifndef F28004X_ADC_DEFINES_H -#define F28004X_ADC_DEFINES_H +//############################################################################# #ifdef __cplusplus extern "C" { #endif // -// Defines -// - -// -// Definitions for specifying an ADC +// Globals // -#define ADC_ADCA 0 -#define ADC_ADCB 1 -#define ADC_ADCC 2 -#define ADC_ADCD 3 +// +// Function prototypes // -// Definitions for specifying reference mode -// -#define ADC_INTERNAL 0 -#define ADC_EXTERNAL 1 +int SCI_open(const char * path, unsigned flags, int llv_fd); +int SCI_close(int dev_fd); +int SCI_read(int dev_fd, char * buf, unsigned count); +int SCI_write(int dev_fd, const char * buf, unsigned count); +off_t SCI_lseek(int dev_fd, off_t offset, int origin); +int SCI_unlink(const char * path); +int SCI_rename(const char * old_name, const char * new_name); -// -// Definitions for specifying reference voltage -// -#define ADC_VREF3P3 0 -#define ADC_VREF2P5 1 +// KVV +int SCIB_open(const char * path, unsigned flags, int llv_fd); +int SCIB_close(int dev_fd); +int SCIB_read(int dev_fd, char * buf, unsigned count); +int SCIB_write(int dev_fd, const char * buf, unsigned count); +off_t SCIB_lseek(int dev_fd, off_t offset, int origin); +int SCIB_unlink(const char * path); +int SCIB_rename(const char * old_name, const char * new_name); #ifdef __cplusplus } -#endif /* extern "C" */ +#endif // extern "C" -#endif +#endif // end of _SCI_H_ definition // -// End of file +// End of File // + diff --git a/els-f280049c/main.cpp b/els-f280049c/main.cpp index 24c4872..7b96b11 100644 --- a/els-f280049c/main.cpp +++ b/els-f280049c/main.cpp @@ -36,6 +36,9 @@ #include "UserInterface.h" #include "Debug.h" +// KVV +#include "nextion.h" + __interrupt void cpu_timer0_isr(void); @@ -96,6 +99,9 @@ void main(void) // Initialize the PIE control registers to their default state. InitPieCtrl(); + // KVV + InitGpio(); + // Disable CPU interrupts and clear all CPU interrupt flags IER = 0x0000; IFR = 0x0000; @@ -124,6 +130,9 @@ void main(void) stepperDrive.initHardware(); encoder.initHardware(); + // KVV + nextion_init(); + // Enable CPU INT1 which is connected to CPU-Timer 0 IER |= M_INT1; @@ -134,6 +143,9 @@ void main(void) EINT; ERTM; + // KVV + nextion_wait(); + // User interface loop for(;;) { // mark beginning of loop for debugging diff --git a/els-f280049c/nextion-els.HMI b/els-f280049c/nextion-els.HMI new file mode 100644 index 0000000000000000000000000000000000000000..a7726b868fe881548ca039bb340fa71cc0c6c075 GIT binary patch literal 1424053 zcmeF)31C#!z4-An1TYC%*+J`Mwk*i5ZPnIRR6hy4C-^pa=H|Or3 zd(OGbxifdDkwCdBqrm)30>^#Vn5!38&tF`A{lq0*U4CW?OvoW0mc4t( z^(n)Bdq8qH^WZgh_f=otHbBRt4`)V!`RNB`oDWu?Fuh++@0yml-CJ#@OuV(q?$Gt}o;d}k_9FRk$EE@^aZ!2i zZufqpz$}<8!^yunbd9-O{?{+_W`5z;)dME{R;D+gt6SGR+&m{a^d-M9Fy3L(?NGIu zoHD&H1`Et@f1jM*oZm@=Gq$#7G5g=orf6F%^hX);I0AHBQf zKXc9c;~fYPKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009IL zKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~ z0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY** z5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0 z009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{ z1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R#|0009ILKmY**5I_I{1Q0*~0R;Z(1%|3X zdDX&+bFR9w2cy9JOg=d7yT)9-xO)EL^6Muq>FW41Q(!_4`LOKWL#|I5?%M;B!;@^B>I-q7oV*q#DO!BPLJ2A=i*CBEa$(V;>YFMT%jfY$s zR#!Z)%$Of{#Ye{*Q`Z&$V6rjGy5hWxjJd3<9DVp=V-m^HnAw*Y^Y^Z}>{4T{9FY95 z`2EJL=o)sgB$Y2+I$`Q1g%atC>Ked)yG0YL=JigJc!c~{&;9Dc^6PtgR`VecO8#08bt_L(s|adFlB>w2f!iBj--4{dCjxfRuY5|iSKsw(=V zzWVAA`K;CLk_FY}^CnEr>-|w2CtP@rq}(X=?1keecZU~^pPbp1I%V?s$;U^b%Q0bc zR`)1wSTtdB?(q)`lM|57raRAHWM|maJik;)QuDmMOsRQ(Y5&RagVSdCfp%(YhA*)f zHZ{Y4-tIRw!;kMS27NO8m+Yeaw#e`&WKLbXOP1cUpr`7R1WoKy>&WLJ(i~4cKClK|sVQSf&g{(`(y<3T4hs5^#+Qf?Rr8{oTBs8FSb1qyU6rqQVR7?U03Og;+NAF#k{oJ z9*Ux{zNJOct_)7CDC&;X2}N<@KfEknsAVa2vp821Q#XrtmP;**bI-cjc)<%itfZ+J{@cNEnw!}xJo9cwZd^R?$XQwc`>_XS4#EJYkI~S&ISWl-g-1wC?(93TFke%-w7(SQK{}%+6y~XCVK4dY6y}<=h55|4%ul5)%xsw@xAbgR z<-_sE@$KsI6b<^>mU*~Wuywn$&pZ#L5Zo^~Vsg)=VF;j|m++bGiS=psEb zO_9Fxqq*5vUDaPU(V1z>^Sk>^d0uXp+|(oJ7LMEigH%kqWqqIUX;_fGM&!Ju=GWF3Pt%Hy=hKYlrQKnML9cdQGRc~ zDaz>^sm^>aJAES+d)cztdIz5hOShN3u<|C^Q2%4g^Qm8pH6&emUfO?7Z9kuOFMFz+L3i5lGDg#=K0Esu zSK65)b#Fg?MtUG^M*5(gnwpV@r_D$&zdbUNR;s7;6%2cJ`}Ntdlka1kaQHn+R8kv^ z<@XMjEUjK-Z=2rgFDJg;e>XtCHmzTB)|$h8I4{FFyg8Z`@@Ks=yu}^fUF=`g-qbN8 zy1A{U%nFnS1L3Odmc#Y2t;NAju@1}W%y5njL^E6bbArQ8vHuYvS7x9kdY5ZiV(2Lj z;w-O8Tw8Ohy^o1mGa`*`S*`xnZR<|>b7qWewWdXuyE0q-x3#T4;csll`7P1<_V${N z+PI8jUE7uu{+xp|oEti7+X9i0U&eB>UWPyR+|zfvgM*)b$dw%k?{vr729|_Zb^4dP zD|WZlwC{-5Bz7e9eeUiyP3|06;@|8EJDrXUr}MUsKf1QNmc@ekt@p={Z0Yp*SG$AD z+t|Ji%*&Qba^YN=NteVfT?OCDv-URol5PzEz6drnvkklJD}l(^}rK zuEf7O-qJ25N=jb$fc|qboMS_N_l~ymywjhJfv=jJ42O|6lA>3`QpF9HugiY}tT*vL;&G-sJvrbK_D=)7zhuGGjcP0*t( zmt#I)F45?o9O-tcPA!%rOY=UB2Ia~UzF)hJ&Xr}nOrsCvngSU{qK|6Y2Q^xnD@%5{ z{?g0(T=N4nO*Py)j_DeGF;DuMA*bAN@5 z-7L+QzUF9uzsi?kue9eXUkpB^KM^pxKzu%|!_F>{{yw5}u&h9ay-N3g4i=cNnUCtQ zC57e_=3_d(uNO*xSL+b}T_{WYFPirM3S}H0*ZyVF`QkY)IauKlqZmFp4}kC3s<)#x)LWUeZ7$$v6J z=4zg%9ULL+s#2q4BP1_ft7CSJl>9nh(`Jm6b#R?VKNuu*xiPmK}#n>B627|G$cXk?9% zsokp4z_C)szOG{~9V^rQhK}!(V;l z@m-BNHTs@L6VH|C`x<>oqaSFrLZg4vpAkEBt{Gr{sA>0T+P`ZQ)#yhW6`dzhjYd~% zv`nM#XjH4wFEm=NQCOqfG%9$PL@PA9T%#Xrv`C}dHTs!GbsAY3)oUc{WwKeR(PWKQ zY4jD1R%>*-Mr$;>N28x;6xHab8WlMuYS8FvjT$xjjz&!y{X(O)8ih4lr%^$XMC&!W zT%-TcXpu%g)97bf3vSS8YmwyGjjH>HBB^mUX%s7xJib|@NiIp-qS04eQlhr%5DhM= zCI3^?4!R@{{gy5}ybuabedP@<5$|>m0rp7`!)KUSL(XEb^fmRO5Q!7!>;hk{2kN- z#{FKYdw#7^hEM9FLmGX=C$-CeYky5Xsm1TnTHt?tQa~( zWnO-#(Vw;J?=>1;BDLQiwC?;|iH!Mww0vwTkrMCMu1}SS_!R-`_R*wnk5D^egT9j7HIkvW0q9x5VQoiF1pt=|z(yKS#9d&n8JeeNLl4 zY4p5C19ZFjf<_ljmbCxVIaHdc#-tykiA^z@C@f| zawL@hw@ohn+mih2IyM@kJHqceQX82bY^m$Gt*xf(-#!khYg_5s;mUY%XLNdSYq%y} zR~8ABMppJp$rv|aT;uW2)2*4oWo$-{Co$+3cBffBO}F_d3^fzq_$>+9T~-i)EMm$vHBt>}NZj+ggw84$ck-td*|2 zUF##$t$nU_u9eXP@;cqplqWtU9pl*#c3RIYiyir}Ke5b}{Ys>42GosU@ z0oR(g{he;>peHN#Nc`@^^yog>ZQa*icR8Hjnk$dO49C;6tt*%*-hQ!9iCi&Z# z*pQeN*(w9i3U6}F4sLY4OBa7c%dq`HT!};Cs>*ow-Q*?cBhE?y{9GPL&wKci6gzZn7 z>aTa5Cu3geK6L!=NZc%G6_qojb5=_@tJNLc6HCmu?$+tnbu`EkTzrc!x+B(Z z&rVH8Rv?mTKlj*qwyvWw-q0~4+|V)L*fu$O-_{YZwspR;-;)`LX9j}Kk=>K=ua<-H zj*8u`xGy>#lkBS4JE;bmQGo`W-C(;`$PWKC0k08^X5J>xH!004)tb6n-X>H zvm!O^l{2FA*0tBiTn(igTH2>YGXvqdo8xQSSGqS8TN_$BEqllfomnl`by>|}S@=0o zS@_IYRv@frQ=&SV*6gynGUrg4FU_bMOZ;<#t2*mCb;fqJ&E3%1=(a-fjWPG(Z83MG z(h5b_#+%~n+8PsU+t_=t1($~5~R%_5%+m_Yh-`|-Tkb>wxi21czvSA9j$S%jINB=b#88}b!8lDif@wl8NpR;n_Vki zb@7VIRneNZ8Ih*Mn(%aMnH;3L>*DK!%S-&rqfOBj@mRaRCcZl?D`#7~tjhhz{?ynK z%zh;1eqM@~%&pAUoM_D27hl$X$W^hYeQlXlSGL==p?!ONZQE?AOYUe}mbg2y+?91q z@%67t`^FR@-u4s9t7Hk1Zu9NCm;itn)h z8#}G0#MV+d`Q{5cwc;*()br$_lJMqEtKJ=~*yC`PP}kSQKW)Jy*>yZ-gFB(Ia1X>dz#8_I&) zTV;~Euvvk!V9mH-cBs#DWm!<3y%PtF3(C`;%bZY93Teu-t~4mm-ib9b;x|bHBSGA@xg5;>u`^&p)qD{uh2UI#-fb#rL>3xSy21HkJkt z#5!d$<@|#)zg3pNb&~&a!PW9SNmo5pqxt{je`0^$6Yj7SmkOzO>e`!xPUhr5+84VN zRt0w?>fC-=mz_HjTcyt5;P$UfZ0}s3xU+qQJ9ur(9o*~wd*WbwZQ_phm5H4)%FUg! zf~4EtXFgU?3lWkfR~tK9lJz+=_Q+p@S!V1}FnT^`ks z(<06OP;h!AU`-3^dnn_WCLe2RlTXhj8shTyLfgP&^7c}6Q+r}YEWFVZlyMEx*Mn{; z=t*u_!gcO_@*mlhSl1Dk7uPhY64$wErRrHHo70u@TGy$sYvZ-@I!|9VwufXz?CO+o zn@6I3Zh1MB&~@M(^@L=CJ*B}7?&q7_*1GmR?uJfbUM6{3VDuZNlj#BhuVgO zf^+vtj*+^+zrI9DtQ2_Ns9zcR&`JJwjSIF)iPP`6=u%1K%O#<=6yI#*3% zr&QT9!qXx%qs!to@zqkx&IpH^WYd>%%yFzia?z%?_L(x-hIZM-s&60U*%7ae@9Ny% zE)}0lDk~;quW|3~Z0e}=uaB=yTwC9HcSpJGt6Ei3!*^!KT7w7LSG4VM*SW9tuWa9( z*d4F$+~fA!GnyCjXQw=+Hg9%+H556RSP|db*)vd`dyjif{9wCX18x}?X)TM$v@=_S znJwYWX4xfhebt{S3Gyivu@l;|LZy+~vWV1x0e3{6vRm_-e>EQMYjno>&9nULgKMLW zu36T)aFc68+f3P2)KBY!P0>*q$^HVbH$Ho8y7iUZ&}^-i4P{-tA>lZ-D<0qGmTj0b z$1!$-cGZV{*l=FJlAYEL-7K^|;t8)SiO7lE8n?8pY>|ECM)$hTmps;L-&0%S{)36e zPJ1UxH=52tGDMB+Petlv5ZO_R)O2p>sFy6VQvUV5u5)9@`h=W5ueVR1H+SvJCHLsG zY8(52C)`l7HX(cN*U4VOfi}r+^H=G|nvxB=b6{uv)<@jWZIRQ;Zauv$`C(n#WT z|N1^}o$TthuPfP-h_&zPIq7Wgfh=q73~nlp&Nw1tltwRqsMOzF>JNlv9J1AHNbX+Q z3sT$Gl=4^WeZd>4mCc94JNL-gj7_mlYjbh1&Mh=evSTCXwoiGs#7ZmI)(su&TqpbA z*r9utkvd;YS{jaa@Ae+28XJhzbkv>jm!rueGQ{2?D?WPiyq2#SM>aoWT4X=FqM@U) zy{==c942n)T-LFp!yVb}iEQX>jx==EbTqhSI&ObWhfI8b^2M2#agrJ6o+aJhj}GWQ zd`DeEGyLnkwl{V(%2et-{^pML-e4(?GYdWf)zdPnWvgZkRBr~=yUKeXB4mZX+WrKaL z)ESAD9{;K~sX1lqocyctJ}3Fs{va*8&er?2(PoR3oy0mhb~<@WSA)_I%y51)vpFtp zL9?HB?Ujb1tE=Nf5JY7XvpN2R`&{fKQHt$v-0wTYGO^_^Se+WP_b0ndE@-gst9)v3?z7}@iZ z=U%sen?5ah-W5O8eyDxFR0$=1tqlW58a%sXpQr0^zP-}l5DV7Df^+?K?a71uO^Ge> zI!{BVb$-UmlnNuY0_pxdCPPLdEx&WS&L?ziOl)nFdPJUE+jNVXJkv05m+T5*ok9)u+ySsCYtJb#Ti{`$88um22rf}{F-{|?zU{&Ouc%X{*y z{Z7cytY6k|w}9qnyK*0%(d$wtIk~^tKFz-=+7!vRPvFUMPtF6`5AT(844aC>71pD2 zg!Si+E9UNrl<%|3?~=W`$K<5f%3?XLKYB&>1G4)s8|YZORr41)AM?lhR@r@cR!-H* zQJtLW99SGYR$_;|dt#oToIMC{Pb`;XN4cIWv9?XmJTGhC z*|x%UMMO>|rfx&e4f*>fjmg;TK6;lg+}J7eurkpo2O!z4hclbq!R_(p&RNklZoljr zbXHjFU5$FqVWT@bExOBnO!gcsIXcUh%WOK=yLS1)JLF`)9wIwG9|;9JY7@Gv;~e$C zE3a7Ryy#zhcz1YjTT`Ug6ReF+m-C1(ud$xk-&PxWVU88JEqFyxU#viFbdRJ>OLnhK z_Pt&P9Q2~U>G1w%Uy_3&-OoQaK0Wwief&1h^8;So=c<=WkdE4??s7t_ zqIX56$r9AI-Pz_iwzpl5ZRK4*@0RpUu2s5MqzAgrg05DA?AFrNW%^mRh9}NDGP9XPh;SC z`>5WT7fNi3uCP}7Ya=VeD=axfr%QQ$sI;fuBDD=e&ZvgG(iqd!v0je;H^?FWvRFb7 zFwcL?Ep0v19*=K#``3hLO8l5RsHZoaUkt8yZEAO>?wFScTRJ)h$VuRc>^H8E!@pD5 zg{^J7&9&q7{@qWmY`e|t5BX&uTwc5~3ZMLYpDBB=B<#!+lOKLx4;$n_YkIh$eOJez z7iFHELv+qx9Ay9PIwl9ETY`GVOEW-LsMEhpPEZecafbEEjG(;A3A!ftVLJzWOs-Aa z99cBYhW|BT?A;LPB`=&WOrjcv0J&koL(UE3TP)4KxR z=q&3l$*p@k{hM5OB=*E-2k#2c4o?f$x-w!QhoJ9av`d9uw725?C;3Z`pNIS z&2C0W7OgjSl795FIf3wyR!ff&-{2UUhXf+oF~6Sjcw=K2DQDBNT3f8DpjJF@bR0)k zShKB`h*s@ya1?SCo}jw5a(QE8$c|ZAe_4_JmlZ=|mM)4juPnHuV?bH3QqIb5YL}OJ zL*y_kJ5(H%bD68+gG*%-b53dSwzgck95XC0t@)w9B=SQ~xUxcJa<;ovD!X@O41dV& z&uYnSZoA5#^_b`R-t8fNX$5J2-3F1&jH{9@+ALz=^1)jIHa!`$n)#~p81wwoQc$z=zD$bjOSj{5dh z@j#?DzOAFab6dw+IWg9;(JkAIYwJ4ha@BQgmnQYyu7>sv?Tv{I(lldj^+oQGJ!#!J zJ&pE?VJ~F|g3@+lAKskKa3Q^%Bj&eTv`=HW!jRQ@sJ-pFWW(HP4R~alHS-*Zulixi#jR_8mSqH4BJf$Hk`Hc#_E<-O@X)I~>Mb^kEXScPct;(`5>8}a7 zGA3CA#vdJYY`3&^g;%-5a#nVNwJFvvgJ`pmv?S)q#(bAcwse^RzmDwn+jvf;rKZm+ zJf#78ue(zjpzlgMwIO=Y)3?pZj<2+jcaAw(3(B1EZLazbxpHYwul9hRwgEY0Z}qpd zSZmtl$l@fu1cI&iC2ni84{2Yk4WuGm6AP~@+2D?~-_iD=!%rV@TZ5l|@Q8g}d|HiD z`Jvu<^tC40)9lh`?VaKvz1QEV4bpcFp5idFn_$h9-2}VDo#HUP3!C#g|8@QXJwjhB zfs_EL>CcsGApah%E0Gl^?43<9SAC+sO`0HsavbPyemuTPTBYI@>*TyfxV~iOBl@+Z zWQjlZ2AiRM>a^1suD9!HG!V&GhB+JyIZ$k~wNjdjW3G@9%Z zC$v1D?p!RaNmSOz^*igIx$)3~*+#C|HF{lg^6@d3vG01^{aM}}m&x_+y&g|X{GN5HY*rMZ`Mcj~))?lAqHp76ar;l;h~J3XaWEPWrJiMRY7)cxmo z-E!>0k@`yyOQII??IjRcTerLaKbM==r%OF)-gz9i1?XC=|06~~+Xn=5vfImvGarM-RTi5ohtKEAiuQ@Vd)UwPfz% z-kHhXiZ5AIesj9SzPa?Z4nKA1?sGI3**`U!`U917?Wxb}GZ~Zq2GVC^!)jNNZ~Cu@ z54He;X}FUz@h`&;U%ZOXFb<(`t*ow4=(cuDM?Xx;&3dD0j9OIc2P|LD2>=YH_FrY*~7 zerCJg9&c({rkUz^seMN_Q>EL_ejD5m{xoi-mi7kJi_b<&mAzx~rngk3zZxqe?SA&@ z+)8au_uhA(&He}99{bt4u}Ezb>bfxTg#A%%o=n}JbewXN=c!-Tm;T1dXJaSt>|~@* z+bg`!+Sa{{v>E9EyWiC77t-HK&25h%b;Iz1w?{_O%<)fhfvufuQjfOmwQx$;5=~oB zzWDn7vXhqf*2!}(wyT0A71fI>HD`A{H1UmJ*Y{SQJh{a#b*a}972D-2wJd(9yZY{P z{YUx(uHV>M}Ok7``XXB)r;p z_#Hb#rZ!U8qyC3ovRkNEDW0%}ozj19D&Lm&%;w!`i(`ph@KSf0i_;cIXWCYZP(Le< z_ClP&Ce~&=NohKzYj)4PmBJ*y!+k>8wKx86yv5O8ktggl>%K>7i{l5=mE||N!SND3 zHC1(Osr@bV%chj+PeOcM?ha~-if*i0QZz-rE}m(BN`6g!ki_4tT(G3_#QvuA>Tim6 z{-)e8G5KZp?)!effh+rmrmrT>#tGB2b8Madgy~MZ==bbqij+J~=h%8m+O76099wrc zTT128d*}Xb+?Z*vvr{{^PPgHoS+%5m?t;p0je&sy#c7qoi989pm7N2vQE#>(EUuLs6e9)IA!ux$$%^t}NZn+JnTUL9(n|T(V zcJ|R>U?Ky+V&5o%ft(1!Lv)`Mw})7 zeO@UD+r5%|BMmd!qtmt@H#71Kz*-qQhdP!Qlblkr5A+1cyC1&MFLfpOd*Q zlsj{IqlHf&@P^06JXXQ|FL{oJy!j7K3g)y-$%#!3XT^L^HiSyDLf&X*tIs+|YM2&p z^bTKc%zKV6m?M+e=*#y7H+iFZEy>ay^6r*09`Fv5+CyLcy#un6O#2~4;R*P zScB~G9h6afBFX9a5BOxN-maPOMTf*DM{`>yM)DuL;K;E1Uy}QY_AImg%bh(RM?5Nb z1KjM%Zz(?F54fYbQYGfbCgn-EOzOMbfZN(AzgVgLpZloi6-zQmliVmX;H`;W5X}mB z0~6(TvZY5FLO%cgQfrUgMYu$MlvN6pRJuO@9-n`RzDi{*-Ly)6>tA~owd)t;yAy`X ztyISpkCinuMu5l4EROX?#s)n8u_3pVOy?LIPHOTac1z4_qL)Qok+1{GgaYu$UyRAmuwB|k} zHy=Fyu+66Z?3(8d<$M=)9pV;Hp?-u|B$__AbSn|J*EE4;>R0XM9Y+Y;yS{=0Cp(TI#L365+n@edDqLS8xU zOCIw1Z}SEVC8CDA`jcJ+qG zJYhY4AJOU=8Sq#mTJ%=mPNy7yH+xrk<#^o_Ugpd5Sp$65kY?{DZ+J+HC)nVV(+FF= zmK-+f(UTlQ%CTIwFSEsC-R%wE?TsFi^9nIfrgRE&TENTwty84K1?@OT$A;!oylUPj(;kB}=KSGC3Xc z8qbZ-%6Si|7wTfAhld2b%O=RZT)fR)yYwwS%ig7r>Mp&|?J2g;qsX}m=~XJ#JShh9 zDn~Q&DtplK8j$_plfN`;S2?v|52SNvRY*PvS*taC=TB33+^vH>aTB= zia&6X9BhQfNA-|H?&~d+Zupz`DVfM?ELQUV+erhbQ#Kb3-pCM{@aw$k03+WqIbqO|SHp6~f3RH9{*&JuGhX6Xjl+>6@0zZUc~wgmEhxX`%X;-m)spH77hnAD zOD0SyGWo{blWB^K%M?h@ndXPaZRD2`ugx-FGagAdf66kQ#;Z{v+YER3%v59kKE&Ma zC^p4%{b{b5hKCHtYC^PSOd_?CUHqQLgTqRm&_XQ^C_^1y1 z!wKeJ9Us&2#U`5fIwLv;~MR{_CnJkODyx!aFO|y z`J{IJmv_sspVF>BdXFh^d|Fh^Pv2|)>iCSNExE*uaD3M8da3!V`JBBR?=#!Y=XIWQ z-)}aWFKG1h_nQXuMUCcMCRSfE=StTPnD3b{8>hqZ;}4iC%~y2o2R|T=<+?$?(9bi5-+pLisE#rG;wuzVp+V#OJ%n!`<>h~{m%*Bp{I&96A=5MB2 zqia88o-&Ixn)6{3H~*^9^pBV$X0gumMOT?`nI$^Dy;sTnE!Cx*_ffOb+@Sr%K5G6T zxm>#b`eWu^nFlfb*41XF<7Q3!&A&+6EgF6Q<0fQo)oAWD=11o1I_BrEF%Ot;Xt})W z6C(LdP5aCzCAWV|^PlfiGAG|QPGi=5%1kr%wHVExl6?PNZTH#!X^Fn4(KkOM(f2jF z`m+-KK*#6#ocS;FZ^mKF{hu=fC1*+3z~`jvziYJd^Ai0?qZ_^;QH@4(z9`W$jn4g& zM70{dq|tJX?)|bvw`sKMD-x~HXnwgwKi25dxf0#3QEr7qbsB{=s@G`WJc(9n^utPt zR%!IvYb9E((fIiitn(OQiT zYqUm%>Gl;{w*X5L3B(Lw%^|A66Ss%M~h@aeIHadQ8&T}{}`MQ~5eqp4I?i*j19JEJ= zIQn(TBYSlk3%?<`Z=Xg_enWEF9U6W5n`XMXQ>W4JO_}GrG?(1)Ei=*aOI@~2-Pt;CChe9n?}`eb+2;{92=iX|1bdomx8P+gBT}<4+phvBvz^@n@|GXZ+NB$nmg7 zw>3!gh(^tg=F^TxHJZ5AT;q65qwlUWpK&y+{p0IJFQ{pC{~=>}T*p_m!FFG@}5IC_WFI4?;(nNfYGl-^e9 zI-v7TDGN~@;s`w_llKGB*-^eZPsxGD)=fZZpvFibgjckbQ<@ z8ZA9&203EtcgwHMLaEawt>xD;{x*$XJ|x?ZxJH5hmK>YVXvaOW6zv+VyjPaHLznHQ z-^esNHErQpz?&`4mei3SpH|n@dmmFLle%7qHFwq(X^fU# zZ8_gB|95-jn8Y1E=n3Y^;m{$EKR4!<2CDo%J%qY@uu^*1|Gr>d_cJp&NV7Y7K*kwz z2M>DWMuBd75IOmvqm*tkv51_;(eA%ac0b4K&-G@>8JA1_E8o}kJVz4p0v;J4l5PN< zJ5Nvdu#QmXUPpL*?mgYhs_%MBJ^L}z^Dg^u%)_nT7p$S7@xi=@CLPWROtrF$pLckc z#pJY8i`PHE(^xERbN&p^Ms2qX5A^Kx$?21Up20q8${Fmr%PWmJkwKn)dNxVk_jbJ( z%K9JVk!GX89%)gs26~1T5AqC^gQ)?YVI@Z#o?*=w_=h%+f2#1o2}cSam~eRL{jKBt z!#ph|!#(xIk)fWgK51-{CZ0mi4ry@mZ1)ZIY_tCldLsip+q}_z-snK-7M9av8J^u< zOHStKJW75G%RKw!u5MnL%rZH6$_`BR4+%_?V@zoVdL$-GJGyJxyD0j!b9bdJYjI0k zc;-W;hvgix9FAV#mtx>A2zZ{Xk9l%5Ne)DJd&1c<_t0j~es8v9okD3MIwVc1-eF$r zphs8kP_O@hCwh)|n6#%H@JcoqY6s_dqREsyJl1f#mkplC2z#I{9={xo>u4H1;gLG# z-JUVYNlC)!&R}Md)^*ryCIo(`lohx&>^@8wN z`Lte|_PoK-GLKE(y_*9qaxA?=E)DR?Ssr(AizkvPkte##6U_7m zhqbt^uE-OWVI)Zo(fxPYeHF?iWC3N!LP@(@M>SL?l4Xxwgye8@uXm`7RE}(Q4hp?_ zv2o!-Nyuv{72XG8$(zGoke>;Mm(7Hu$*DE@|xTCjX#nj=N48@wl5=yO_eM< z{&|0$Hb%wDp37?WM&yKPP^vO3v$*GvkJ2#gPp zZYe!-?)@>%n7tq8_T?Jp@elS`+dRP?p2$w`on9%Z1ATJxCiSVK$jYeqSb44P0#77Q z)^naWU-Dj_R6{LN-AGoIN<^w1d6)AwF;8BzM^2MSm8PdVELjmj`4p8;a*j0SkpdzK za-PWUAg5*IJtF`59<;k@ckNHFN0G5d?G8F7{S?m8vCBlHp--lm6LUvo?0(t)L~_0Q z7S5G3M{X-uFKTh;$!X^5L}l zLT6Dw>9o6N&8w#}bp`{n1ope8;-GyZ_H8b#$;+dX2?*%H6dijgcWOol<1=+0$;3QpS=~mUCz4 zz2>v9^^!X;P5w!?eeHhxE==;1*0kA=xnyn13Be(;_921JoaRJMs7;@J_da9?A>9}x z&Au~yuWq9!`3LlR_Uh6T=5>{kbbC2Hef5gECoopM@M zLaFv77e@yt&s^sF_R2LDe%Yi;;kI9;{VAg7I`vHo@=4#idePQ@9ab;Z@NbZpb9BT~ zv&lpvcS@m@Qnycvy3BxF451e!>5N5mW@VnUF#nx!K1kWp%5Xco2z2>YtCnb~e z1DE(4E|urDOTwdzWlQ0Wj%xN?Jrv! z*`mq6e?&lflmAi0(NVI+k_#E+x;(F6-h-oCymDDic#O}IrPnJPq*YBC1Lf4VY;NTI z{~>Xg#=gBiNs()FWaq^bmFB+iei>f(m;7}tKDnx8N;v1CNkQ3NdT!Xmt#Y+XuZ8Ku zJW4NrvxYu6UizJQI5##$TGf1yH#}CX*S<)l<&}IEmZnWhuJ@7}R`QnASYA6zbX^-F zm-&V5s}?0k$(4%{X<6;Qa#1c~w8lugQF zK4wV&3c(D`zevgLdU~-%M?y+l40#f13Z266|{Z5B=Q@gzQcE%=(m3 zDIAE7wgf>v{nQi2u1kg2 z8S8YvY-8r*mTk;eHERVEVza!P-Eg++a$T|)?NYx7uvCCqOfR~3(y&o%GubfFFu{rn z*rl;pM9>6iu&U@TXveFV4^fsw!vjGi8O&EqWxO*JAhV&Mngqv2r)7o0J?@)ERZ>Tn z!<25gZv+2Io95J>$TVTF z8j#7tXPV%IjHK)t78zX1Je(;Oh%hD;Ra7Y^r&WnL;Q=ttj6V1wE{SK)#ME13#e0M$xYEz;AGsu0zT=jH@=cmD zK^|wGHoS2LKvJJ%OMg(r+})p{{iA9GfEi%~u&A-CsPs3P#Yk9?1N>9^Oe#snR&dN< zph=anMpM-nFbd15juDgg><1gz>(##BHQPvSe6rXyd;^~C6@yWd|HbT9Y& z&R~6_v;DNude&-AMjJk)s25aGrO31O2`N5BPDU;^rHt9u6mz+x95-{GHTAN-a!l#r1uIZO^!?fG7UK3dKIq( zb8|ypss6q5Df4$9+1jDx&?RmALl-xs9=^O@zxpeC;)9PPUi+_|y7$t?j8^}?>1g%S zhNCqw-Dn^*Y&PLQ18}2Q-Pwr?;j8uuz5e}ZurKPb)xDZjw;SuR$KfFQVts2N8gb*? zP6K($NK*I55lq1dtd1~K*rPfGWew;Brij%L6jr`#A@DK%?XWYYJ5z=WIvK#&J4{(| zol)%UM+TuTRO@zRQ-{^ym8q74qp&rQ%FMwUVRKv#YBmzS3QiJG=zD|lo6Z^d+=AznuuznP#j=evNIUdll{nEML^AL_7A;*JPO_{ zIH>OcQNd+0dAgO%LRY9eA@Lh%dFc@A$iGGy8;DRHbRMSNLo_qn2%Tt38nZR0EbzqE z)n84VNh1V$|6zB-hYz^gj*kZ}X`%Pdr;Sg~<#+Dfeope9J8q7_$unW5VCD@6%H15- zOU)MM*jB?AWH%{_%J;ECKjWc zoQj92?x2!agaimrCvD_aFpbAqyN2Bw>M$MVE`TOsU-F2EuE?Wc!lefV zO~xS*IOMWVZ{g=s-DAB4mZyc51k2NAtYi*IhCe_`8U8rzuS;9bx`fqXc^i_3O{E68 zH_oQ33r0I9N6x1Q+{)7rAjx|W?ZQL!7;yQNTSniE@Lk7@0Fxv4gi+6y_eL54s9r>B zBnTtJNbOXTJ<2B7Ajof-+gO}P9v=N z_XGKi0d>+=TuEnA`n7ZIXZzfyvqNru^8T6Hw0X%MzF;A}V-+`T!Y}AE)d~0oOgoT- zBBT|b0iF+GBug_{Loh!yb1-Sp*EDdV+N-*!?K3nCVc_?%%gKG6y#36%U556Wp}o%a zpa91ugJUW$mYR|=T~i*zjN-^+Sq9jQA-_BZzmNp)lqq6WJX_|P`28~tsX@2tbnn%5 zaD<-~51EAmtIGF&o9=UKPj7Uq->0=`waT=4^;gnT70d*xa?`qM6444s6Tyl}hY`hw zN(~>87oEwGc@%fW%ki&RWopQtyhN^U|?^Pqa|22}w?gQ<8{X-honPCl0XXk_(u zzh#fObDyu1$MHwqxldu4i@UZAbYzQn%OZmVK{Ac8{fMtTwM0P8SM7HqKnJu_o|C{{gRcfJ? zBMKEurrJ@{lbLqhRNTVbrY$rZTL(#y4k&_-xJVKDloIlko4#6tgj9D&Auv^R{DVAVhK0R75ea;@B;mldEG7x?`KNpE-do_udQp`30}Z z>%F=27f=}xJRxI`{_108>m*@e5_FVYq{ zy5GW(?>a}C?O)I~daU){~@zbu0O zaOR?w^cnd4ZR(<}pm|u9We&EpNJxh>cdVc%aaE>jc=1ZE${etMVi}RS170=(!%tDK zKqzA2-^lK#uzcyTx;Uky*k(a76-AnbP!zO&lx;)O0^{!0$0czZ_#uMoqlojBb}U=a zt}8H7ChL&tvI25Lmdyi5&<>GA+*(PZHg*LhVqV~ey2OOo4Rr$uATi<$4Yl(gaz(Xc zv+@G5z;8Cpd3J9bjB4iG9)!o4y&d2UGJAWG3ug9SM{+KFPImPQE*4$J_uE(t>-H(Ii3ju_3K9#yPON22#)TVn8X z)AUBSK5kyMhv8|M-YzpMdew2mse-GiG94x=ry`|0Jb`71%Zk9K<6*_2+mH|VjS~jE z3rw)EHLxPW){GnNa5dl_P$ayq`z*I@KwTpJ0l+Yy2%KU5D0j)h%nh%pyC+pn*=&&; z%R`Q+2eOl4c2rSBxGqIQgeWD=mb)_h8obVBjGcKsR-f{o^}KWwFW*KbY`{qJ7MLC3 z@xKnYoV%y`z26SGm1iGdLAQy8CrjbD`H><&Sz7gu;V1%@Sp#QRy(rv-#!-oqPyu-f zBCX7C>XJ!AN{Gd}Pyz(AlGicQR#Y&>%2cRGS^6O;9E;+!54zPK{BEeIuN07q+F7kU z{e^~bCD6t#JJV?zz{zauyI2=DQ-halryq7}QwV2N&q*P1mYx%fpckU&bk9J$kdlW# zv*_Q*-fVgSiO7E}+NIS!eC_xC^m^3jwoSdyNXakYYGewhDnzryef+rD9N4R_?lc+)b zfr<_}$k~Sw#yku|L7$LIkTR+Kn6@0r5N^a*g~*g?D#J=2S4-;rZFcpWD>{?7+)QSw ztftDdEMa~mr7BN7LJ1#M4`&>t?>w>AL?o!9 zf*^a4K7JF6Lcfl>Lfl6^(!U!-yH9UN*Ulu-04=5SNCLxw3|&+@nKbg&}N;g@aW_ zGvfDy01J)7x{rw0S0ezNhPZ!$a}1OOnGsN{@Izh=r{J5#70jF? z%15X?(q!2~lS12oOM^)gJcDWnZuJ;+wTuUT0Nw}~gdy)Al0kvghE!JN(@S=$@+%lYP9RD}zPG7;3UZfUumm{EvK_Xno6^U?_?#2-MCc`@cz{kU| z`Cg6guS8p)48N+^#KP`wU`yPzi+KjNc_$ux!Y&**oHDo$s@8@#2P%jKEEVyV4#ofw zOquQ-P*l%>`#+4695fsToc$y#>k1l-m4kd>-npEU@{24s9ab9Z4!_JG4>A&`PNLda zP5!i$aH2eO2akqn1X}LhjVCmoeJGehEb)X z)J=5;+(Vo1Rf_`3!dP?>8B=v>Dv;Jg7F-pjBa9e~V(ALoSsH*`LR;^xFuWS8mW!Yn zvVuh(oR3kNYsBJ3955&3VurKAbdi#IJ50Nth1&rmsEZl)TTn97L7{~qI+!EWOa}9W z2SpP`0>)0L8p0IOb)bhA{SEqjmeckDLjX0wh!M~Q-IXA#Qo2LWX)(FKH5Lup8ByzC zn>Uz#2hZIA7qc!NvD^5mEv=IgiXex3n&NZ;lM?P1$4P(_Ahl$%1~y7Pvo-^WVvd&u zxkK@S3QArU!w#4QD3t@);2ro((>Y|;$Bi-5sYeDdS08F;4!EB?J!NQHzT#)Q;mCXu z@z#O92B_R_TsC}aSM*C%!5)T+9t^9OpmyXXs4GP%QLE8nBI-fVu3kf!GG2o(=fPzt zj-cAKkC}|TU@a>E+T#tX*mOqB#<;P{L>8`lFEXxCb{6~<4dsT^k6zg<|LYTYB8nU9 zsH=ABt(^?P7X_%#*P9M!T+VQTIx~L-RjRI#Gjc`lp3D{W2e`Xn@oeq(Oup+L^;hRU z1to1LtxHAiSGuyFG8*w){mhkwolHSP*@g09n7c4-(^;A5bjpE}RxmfS2bQ(qygzr| z%bZ8#t8P&DX6}%CQ=MRNz`@2ki+)IEe#pxdknCKh@~}+7R+l!WqHlJoe>w{kdTD&K zWzM|B+67{Wg6^T!8>my6$^~L}QnaWZy3@6SZk34`$;oO1iQ#xg)&e15#>9dNbUjiQ z2=gpViY{)YnZe8}Ck;?8 zK~hy4XyBPlbAz|QjH>+%*c}m4?CTc!+SYy+`N;u$A}Tm8Bbcye1gB7WPB=Lf{AJ1!N|T=>^;{tI{>^qGFiZh%$RtCiJpJ&{FZG#qkjTC2ZDtNrUwqDY@~$2mLZ0T|p6QPJxXp)&Z-6ugPzz zHY|uffpgP$q#~DTimknZ1_2z29S}$u<&N*L;ph48V1*#QJH+3H>TR;_rQ>BfBpfaK z%0owy6AyJRa}h7ZMZA*qR~iZyPB3@U`NVlglBJ&Mz@1Ma{lWK34PU&ci){gloEb4+J}qju?Du+-EcjfTsZOt(v`ZnsT! zJ7AsnUbl;@ZnqngiBp0BookN5o&4^lA({{-e-g~qH@jsq$`dEVJb|t7$UrA#;ya-x zzA5m}nTe0z%hEVfqs)m>n? zc47d5v;rFil>c}AgIC!F4^gGskk|e&)B*^^W|8r<3gEOD@gP;icQ3nRhQJdh#kDKs zh+R-r)E)~19J10Vm>aUN!A@A3Mz_(KFfRr#u^Nl%K$9vHJ;=IH!Nd%f4a`mfZO4|D zlqHp6W1mU6c&8hG=DT{<7UwQC`b~RL zwg=3YC$~q9(eYLF-dpJ!@%cr$=2K~1^*zco8B@Yb%)+NE#0|oy*oUI_SOkEnvojT5 zAzN6cK0DFNU7=*x%q!wpuPhPq#+7fqiu2%FLlDE8GqZ&Y;H5f8BoWTB8{Wfy@}x z8&qxtYaQgxENTsSUrGu11_&ri7Ua#0R!- zHZu;@+J^-MqI7}ZU?GO&8?ufX-z$H=XSPQ1oCQVA9^|N?r0Z-O-YxK$=)eR$${Qo>K_Er^|H(rFCPY`waaRSIY6w3a6s7WK?5=_&#$n? zE{j=kYhb5>GB|D|g)I_&L_IcX^X5c2QcOng)zPdj+_)w;NcvG(;M3GKt>` zaW{$MNt6J%pu}8X{85Ul0}$=3aS_xbu76bo_2R)2Ze|TD0`Y7KKt#M;BHY2{B~o@V z-8+GisYra3P@P{KJd=n-epKk_UZnc0BM_0Zq8O3o=XNq@&Rv1f9Q^ene+4g~en-Gi zVPsGhP7SZZdK2{w44Q?GgJK{}jxbmd-B`}a2p$ty!>mQ9WLN6H#>6qkIwl@|PsgW6 zfK>$Vfbs%mK|CxT7tnctI*N(iYS_isz&^cH_bI=qLT|ymqR)(LrB$MjW=o*rHpa zCLLjAX<;x1s2pwrDkly|L#*OiccBU@N7M`bdD%dF&G>c1+!8fKv1X{a8uMX*$bFGf zBUi3SiM*S(LEvqco3OYbQk=I%iX*Vbx8z|s6;e#>7O0>wu?S`)I0CdZ3g!a&Tm-qc zEe=W>sQUV(0AZpa6MikILFOkBnAuyExIc z;JN7fthKcMwC)3<04`M@kJKC9PV{qb6AG>bu3Nk&9JtVy&CEwAd6sk^U-$4z_0J%6 zP^Ab4Sxjxj6H3rPWuqMdtt7TDU;X#S2mR9Ar?`*Eaa-v&ra5p-Gv&bk%79H(oD~U= z=(q$11F^{YG!bK@!Y@Khlwf?tO$c60=$IS}_!61krOIiO%ve`lV7_3#%(#Rc*b~(r zB49)~;c5}pR7nn!Q*rL|$0CnWS~upC^0NqI0C%a!u~e@;{D+FuUEb<QU65-XH}UFr!-uOMvn&3_UVmlg z6Q1hyS1z$luJG!Oa%$t{SGva<@_W)sZN0wy%MiMkzL`?V2x({1Sh+mz@69>xdooD0 z<=J_8cD~ze#`0KN3cTEMD=oLux3c0`?s&@`Z@J^$88&!%EG>_v<*~Fpmaem?S)Lx2 zr-$X~VR?G^zD^G}QPXskVslo$=!b|oSr0&BN0|+(gMJXrynN?^?hu1Veef8s0`sJ> z$H{!L*}>!o`yT@NEO>;{m}ECuWOmzUgbev|ef(e6r#@dFULXI@jUS}K|J>=+2@ox% zfM@|~^I3ZjN-%)ttHT&r0bcdSFbl-;&>rt}SBPf&WT(B&XbgiotBZdDvZgNiIqrZ6 z;-Uw&u`kDry7<4aNqx>HJYm$v|1+D!=YW4}(tp6KP)!(o3c)^rd5#(Ti2Wll(-mQ$ zz`)vLUmg|rI=|_3Uq^e7L+~vac~lJfRk(r^(}f1>n$sw6@kQ<}Hk>cA9ObPGd{TkS z=>#Nn#w+dl>{qMa{dL$ceMCM_TpB$;;Ji|C>f`XWbmxqOhi^;p1r9+36-gcCp*n-@ z0#Q%Pa8iKw>xl6&fbMesD@Y+=_uR#gI5tSst{KoH zZ#@{C+!zpzIsj-Tn0_D?Gr)KRw<2Iqz!ww-YjsKnKm(*yDvT{tUQ(uhnY%7~Uzy4U z?+%$f(?eKA-S3}#P##RARi2DRY_2d9ofr%TAy129Cb?QOppj-y>?;WcmPNg+>~HPg6T5m&Mt5fY#;X+4ThipE)}<_l2>`%o>pIFf#RJm z^Qi;AlydgYRAZ>ci{h*tT$2I%MzA$9_s|(ZvoXMN8bRwzN;Qy*?TFJxyaW79wpueS zG0Sbi@oD4xxCV}g(-E=#cDF}VM3<2$6O%uQCmMzeZqf1DVVA{C?`>wQY16?_3cY$T zPDB~;FpuSv^Om6k!yK}t)A^H@n(0nhvywq5ZgFSDbOb0C%6rS(s{7T`)@OKkBEjH(yq zsR%zEfKmt@#k|9iv>W*naEaJWc)GQZi6IK1%f<=p-gWteija1s*I9!ns4%8vIE)v+ zy7o#;{B<(^&PwbVqqb0X}dzrbWvOgvYIT_Qt;{Wno#I?d_M$T{FDSTfCxRC3wY&%uCY`R2@JRfdhq=$0m%*1wlub zz=ASYi4D|f%h}#5>r@@*w;1~iS_0dMM4!L6Up`=gAfceJFTEZ9Fd7`}4_?9a1b2=) z?uY%|VQ)&dg!YmxGb-ERGdOMQn>pC)z8U%5M= z4D;}C#q5PyeHb_$-RBLcDI-+?;B<71?U`PQJpDMjg+sbI`a+-pzL|)H4T3cHx3!3ew~XjRB&(pL1UgCd+z*gkEGp9 zFNscjry5JdT9bo)*@%N>?61lUDSRs6Kw6C`1{3>qVusYouv{-As*IjK8Men{NYVGX zVvUTbvREhXukE*GRAEIuOBQNmVeDwDp;eaX&FqAdeVLsp{Sp~Xh8bUkjw2&A#)t^W zlgKCiMM#1SbV~k-&X79IQ+Yfdy17~nv`LjmW}qGIxA&_tcA`(-hA|d8pN`5)GRh=4 z+}$2wbB%SQory=^FnH&&kxU#&@6OyN;XemjYj)@e_HxFsZAr?)m7N_`$m z{o$QX`<+gQ2$Jkfs?#whqE4`8nHz{3hsPbusUovn<^|y?v~~HO^MQxoxC`HAgsg@< zL#$kJw8m7wo$BA+FAi{^mSU<1a8=k}eTG!%^$g@p%%4FP3$m>f=PblcCRxd*B*uU3aQuZ(9cS?RZd^nW zWm1JTOLxvzTAdgT$=-n*d$^D8m5(SGV|-+^NVk$L zDF4^PHiTlOPy%<0IP>rHw?HED6Lm6k#U6F_F1eAg5aa<)Uot$>V;_(D74oQTF^XrU zb&93KtELQa7>w|duwSF&`4=ZV!Z+afE{wZ?TJd2j?#t~}@E}37i ziSw*Zf3GmP_#*4{cfw`I!j0^0!Jq;bs)5~?h>l7wayI#;WYiSvyaHp7AB9*a*GM)J zw1g%M@N38dJk0u~f?rx=T*j?!u})@u$XlnoUbo*N2rReAQ9HMkkxJ+L{;=ba6zVoBsQXNEfC6ZO8I1-fT zs+~CN)6c;T;=HdjV0OZdU^!!utX@knvmgsUhVaIvlyu2-MIXh&Qi2dR`QS5?fDR25@B!dvgPq`T6asYrIDGjq3`qc?{rpmbq+GhN)y_GU85^k&JYS#@W!Au1ii zM4WW0-br*G>Gsk|hNWu;dzKTughM{0UmU?%DX(%AA)`)YVb)PL z%&l~}34H^%P3Z(D@?~(5A-vByX#(-?#!XBpzTAUDZr+L}NQBSPyItbjN)Mr{F}A7V z!#eL+tIr@(fGZ?Aad#l^*AS2T+99#XEAG#2r4^@?`-u0uXKQnj50lu#Vxy=$aL{3K z<&UdP0tZ!zk96!tkSbBzndpa^a9ZN5AQOZQi3KrVlK3-C8VE1!=5+Q;Mk>Ce5y*us zauFP^!+RCJZe#RSzEZXgta@>#yWm?~?%Z+C+%R{Hzn1S&;F(6+RwF`I;X~ zseY(PKOWmVy{$-TnST$bzC_etyu$x}bttXHz#T)=^)^JTDB_&HSJlH>f;q^r*QaK7 zf4M&P!?!+P7k3Z*OJ*a7>W2=l=-|qn^;eFlWz*J&5fbB`lf+#0Fn;fKx0J+e#}_Rk z3rKLS5pV!o>5#DQ@Yj*RRFbe*@z#^1^$w-yaW`xVIyN~S5Bl1JwuXuhvVnvF=>ajY zFxDr)zymf`jI|`_iE2m)`Xoo_^EC9K_+BT<7BUem!nrjwIB(`;u@}4V!DRyX9~CS6~=q;2b-OiANj36vRfa^hLkU=0Yu$(XVSVB zk95SM9qI5n4V!Ll6%WTwTRW&<)Lu7jZC9Fj!N?>#K1i9L;Uui@VpC#>*hCwhnrv7x zV#cYMT___|STVa?;);nuw!{^4MI(l_E*cirIR$aWY%0eku$cc90*g@%5{V2``8yF= zjCIOah%9!`M$8hf^hTUZu_ED~eGyh3>OE3nm@uyc*9S0QxY)HfzymL!3HR)4ydrT~ zh=%CwRO|q9Qt`CS2OoP#HsA&}V03*Fs@7jolWV?zHOnqd_5DVD6}x8A(kaUJ3CC)eBf3x!GFS{%rV)O~yL z=UcFuj}wV6v__~j7z0VZ)fkX?-@>W4^vLCCNg{-~L(!7jPUCRnwQy^aFi5d*OT3?u z1^sq&IM|Y~2oKWf>_^E6H&!ff(X{1QN{h!*A|SY@g^NT;|m;@ReJCm0Yyn(CbSL-pZa81(3p$_&4~9}(?%OfGlz|wmS84) z#t0fBfN(6$2xd?Vo}_{pF10Zeh>2Slk3n%c}sAgSVG-6mSyG0`>a_CXz_4Z2tH=^BjTC{TjZkpfe|Nxj1h zqASOZo=XfLVwn-&kl>y*6f>ruK`Sj0og=_mX}y@m>#<(KK|FD9azPF)6{4;(ZK)7- zmFccbh&r$k@22lZ6-l(Hq079JGoJ3bSR4Pm?3DP@Y&>wpfm~751^cm>4hD>vii@ zYZFmg>-9Fw2gQ}S)I)kr=wCsstI4>|g}GfUt^O86-zKjc`t~M;mT7+euTZ_&ghjz8 zc1tSiqxPBVg9ET921M6$Q~+>3JBP&NP4qqJhHxd!4m}9-q*0?jyU83AmxZ%LSF6D_ zzd3`G(!-X7AUbAY!lMX2`l52;)zLZOe zh^)%4Hpl?i#4`U@N!$nc0g1Ixi4_fQIYG1Q{3`Y+L1ik8d5ZWY#ltP&W4TGig2cSW zBS8HnLI~By1_;R5=QO0cE;myPh4{@m$*5G^5(_1Tp@`cKxTrnFLMH6D0}jB%59=t2 zGB@85v;qj_5_?D94~(H`HQISaD1?Ms1~G)b0|j8-OBPUvCH9h{w1g$cT80P+*c0Jz z8bG4M*k~~5`;AzhH7CGfp{2@u;{v_T5_@9}oZ_WJ;Ns%eC9uF%1W6;DR8_ju#=E^& z9ri{)?#!a~GjCh~X<2G7E8)q8b%7M$EXix$r95m~Pj}9?#SQNl?p9E~NpJYe=9K-U z`pSVi-OTTD-TW&T%*EN$J3rPxbt*piz5c0P^?r|gyytR7qTe1)6YeTG=xiCng5uJC zU>N2(u_0X}Ug!--3sgYGjEhHrA*)y<75JrxR`|n4wZ+O3xFd#_Oestwvf%Uy@>_}N zrmU8AnMunCpm6XZckE2s2;SV>6}-JU>b|qtoMi>=S9f3gjree8*{y@LmEgl}iy>Z` z!QVoaFiDB&#LdJ0IFM%^HOh%ofd6_lGBZ=rnKB0QaS1!ueQs3Z1SSWP5-G6HiAk`) zZtu0;t97S-AHL><2-{FdujXs3V6U~b>=a(*>o6;*O-Eb=1G5CbYf0gp9pylHwi&~M zMhpvp1^W#jg0iSicF$H!_j_eS!8%JECz4zaXfRMLK zaPR$>)FcGv*Cso45&-Yce>71Jfte>eSX^So=mR#vMFo-E zbsRO|Ndy5gR1!j1V?c~qkA-=AaEh6rU{Dekp^#3Nl|Ucox0y5QXLT`=jpWt?k`3{V zlsSXsel+u_xS<{#ibzZ_$^j)E!semxa*gqi>CS8Ca0?NjKy%mp6P`CPI417;yFx1C z(aVhq^J3Fk6O)Vx_B#?@1*;x+Cn4HrC+HlR3dn2=-7qZW2yp9fhx5)XpqFrXxUWa3 z=ezyV42t(P>G)EA?K?r{mwFv&m|&`vb}X~f9;{CEi}9tiRV}prQH&+>C%S@#_L3j& zx5oqJ*9-e}Ck$K{e&w>3d`}IUhM?-Ymlov;9nP1T;AwD zM0YG4jEHIg*Bir<9tgXml8%J^F-c4HVJhGq0Nt^$=#E!M zMLmClFi^biS`%By`52v6HfZP&zPu=UEW9P%b-5zmY412MRJl5y<#LK^BR?qo5()l? z1@hOB!!C)qhFE5Q9r5ducsCK=i1W0#PS|ymg+ z4U=W~e5{Rcu+1Najo+=9f7`+mrO8&wxncRc3-b3DcPRg z|G%qCO5V@z|9$=Z{=aE1Dfx%&`StB3B_Cw>QyWT3ob3Mp^TU#o)7kxP#{B+YMCY%u zdP_?F^~y|np6#E1?iWMz`AO_y6>nC;lU~KA%A&yMOiEGk^2!(@*C2;*z}c zgY#FHl*sc6E4-xSk8<+KXMXYX{0r5|pFZ`If`X}&&prKDf1Q6;oqYa<$Mf$lQ8n}9 zC!Q%dsjZUwdiLoj3eNuVj|`uZC!Trospo(C%;Qh?4oY`?{+G`WJT|~sn*V_s?R}6@ zSMs+{KmUXKdj@j58|QZ)nBRSHes@#PKq!0L;9%Z9SI<3JUcYysEcd*>dA4_;YVP3Y zs$8mmb3^6+0jad&q4I*9EFLPVDvF273-`;VOJbZ#gS7(dIiKSk)c${of*A|bH zq1@;x7$^Uy>Z13=I9brArOBRu;g>(1pYb>$CkrMkj{hkA{KwBc_vBO0<@a^DG;?;o z-d4)VpFH#P{1KIznXWr}^0O@Yqk7iDF{MUY(fG?0_V1o}s$it668y60q&PY@Q@=lLL)n$rD;@p_K z!y{2uc=1S7ueD$#Hqw)eN8$i~OJyi39%;c)9F*x{Neo3_5wF4-tEA-ihayWgs-T#8 zTpo&4$~QU`7bS{|4@FrCEf|V@-}+d*PsUO)gZg7RS7O{iy71vs>cCI4x9HkGs^w@gkE_~jQOf$akI%8JnX)a$ z)yLFqW_D#G@}29HH^8J;jjz@BVtpaNMCqhxFah@7$ds{g-!X zNdL|9kp3PHXq}w^jp>v-TDf;Y|-(&amg^bmd7%keO@rl!Q9`RV0!M1?0g5ta{s?uDr31~(XssC zk{QeY)1qVf_9fdp7p2R~YAVL(R~gGoOii^IpZ)WvegUceR>$*@;**Qj&I(sttah$k zY&<`AH#Aj>v$^AH=f!c6rHk^}k1fh)XU-O@o&Qyi`z}y|ZN4}7Y-zJ%1#cGCyMP~6 zGjox8b;VtP^;Ip_kzTkPOy1q;NPnRkyr8v(xmdI#onEvfZO(O>0$gRM%Apv)@S}U9 zBT47@o&apW0<3Q_EYW}Y)5o9t*|$2W-+${1uIk0c;*U2i876IU;mI%6_$tN{nQD9$ zV~PIFqGNIK1=s(py2kehOQfo1sS8h(6#mw*M2l%GfA+H<{MpklJn`2{WklC3I-(Uv zw7pF-_C=}m|DkdyUV8nfMLFhQFR?MLihHLGVN}f&ul#N#U%3vM zUv!mt>u}u#hA=IQ49F**d+N!jUwD48(fGfr4q0rLrfLiew1VZ6y7KFrrQJHuTqls@ zg^=C50l>dI!|@M`N;Z!zIvg!E@QRscbJ5{=&s$R8(gIegTE0yH{_SfizEJ?atQCtj zj++-7%Xiqs^dS*VJ^ho2GChB6Fe-i^{^xQwKlp)IoDX6y9#Tgc+w|4!|NT=xeg3J1 z*A3=fHz+^5i+8`zO}#VzSm)wzM+;| zp5U3_vwlK;@PnI7@SA#WVS;x@(vjJ+m>KU0w)Z+y51i?@CpJfdiLNXAx@Y%U&REoW zGwQx+dSemiFds7*vz#f*ow6n@ZYwWJ?9t5GdoIm$v6S5{2vU;wbK9A8_!ENCnOoD* z*>Y;87jJ_PI8&QKv95DF@O(HC^^TaqM8pYMR79C&k69Hd;^fKJ{kFDwFR(CfRrbf` z4^qT7Xh`&UHSq!58V`Bp@%ud@=3N;{TFyy}20msvxP*4!G6^_tj#+kv<&0QF({cBi zxHvZaS4@KRnX8Du6Jtww;i9dae_dU3P~8yhH3@!bcw}NZt1P!XZXU64;q0%myin4# zk67Lj3m1>(>`2-wkKON-$A+BB>HeA8v)xxE(%~lsUK>~BJFd)o<+cy?&*aftyFJxn zPOinGvm+_fmlmU$B18$q`L^Yi#mxz;GHp1cmK2UHaTD0ac;)MF;_@qXFn5#6fQ~X@ zRglY=CEm1o%FKl2Pjp?{8&QRLfU=m$9*4oQz02e39q08c)iJZ}`X4P9mptzc)vm-; zy5=;#-_3K%68GZ^bEAFyL7T3)BN4Tan!$;PeaNz<7;l+wxn-}mDlL1z8B|#IYeb{4 z?1My#ux#2-ZE0Ti^S5%I_G6p5@_^~HzhAOhZ4tgvGA3xGDUUfBv5#8zTTz>NVOO_( z;z2uoF}c|jmP_4) z=nj&^Bng@bK7|vk^K}`z}?*2i%JH2i=O(#MwC0=hvJ{ciHtHM)37$657J> zcUTo{OJ(c5YKp^EXP;%Cu+~H_?N6ER_{QMGeL-1bz^gdjJ6lUslKkKt^Kt*$$)xN$ z-!=X2io6fSz223#d_ImNSmyqi>1~}^-DAJjZLjXO#|R^OjNmER8obU()g<<)nlitc z%^HRS^UP7xVQd_+PDE+B*}dKNJM`B6gh}|Y9*@qNin`KS&+Av`IsiKbuIT4~C};S@ z&6gQa4EwE&4Tt_sg&d#(6NWo%ikn=9kv(MwhfL?V>8vq>lV&JsgiP<4>2QvnH}R`$ ztl^fJ;f$CBYtg-ZL~n^3t5mGkttR2iyzPcp6*pFzPPO^2Nqp0PG+e@;{^Az8X|FJd1LwX(v{*c4 z;!<+A9;{$SiR)fcKVWPjgf3n*@svMo{Da{UI7fxm_$R}uNa%#_JxI+|#iPNYF0ZP~ z8|!kah=04Lt0o=^C9R+)5*#B^4PL0HB6ba9HDm?!#&Q~wNU;oY0+SZ~tzWzsL&btJ zhUad}IcE8*BB97(%Nw^Gh|Dl_Eo}s^K+H^sN-a;AD=imV^Ba@kJ-v2yqMLv@(SU}N zMvFA1EWbV;b?bVFP}dz0`}iLrpD`nN$+V%9&Q>#^n+V;7jF7v1l3BqFCasX=j>_Zh zS5=GH}#4Xn>|P#H^-B z=87~|q|{X|SISjB-#~qdtJLu5%Itq$HP6LssD^7H*fBn;lM(k=mwU3yov^Zzndq}g z0zSbfUgzs@UfLa+TxC@fu!`%Qa+z;WSjQk2Z z4SSGt$pVJ-I*)Kw5ui6hd6>tlEFMD6UEZgq?v_yicI)E=J%L zh9t9(A><Ce?qlhEsczR}gmi&#AGCLMUJfPt?7g2?Ug+`;+2YK-z`uT8AHD8w z^@{8Mbc;WzhUiH3z1Xk*CHD7=OJ|cQbbsbuGZW_WyW9iqx7;rG<`^n$7bcID%j5qZ z7%r-_6t>NByDYcMou|aheQYVr%gbYbdF(Hb{TnSrmglkMdF*b_5zBpSxsNUPv0JA@ z%j0EvyeyBGRAG@H)cR zw-YIsUAy6fR3wY?0K=hbjv21iYAmF@xJJES`bDfF6N zgCc8{9#o?;8`0fr%igEkY+u!DEqjOV)mZjU-C?_1w`OM#req%OLJe#^Z_Gj2axdwYMXn5^t2+Ub&GOb#rwQ|z1%&Ml z(<`Tz-vkqd;*O-1dgtr4g8OQXo9$qe_+5?~Q$y%x3%_;z%q#MhR4xV0)NXPoCzD3I z$xpi5nhei0_^)+c`=~te!{K!QRcA*s{K{kMKm6G_d-&JA-pYS+s@^*f2rt)$q-_OV zEb~K|TmP%_v{xJd15uT|>O}a2;h#?F*IabsuRRhBryp|O+TZDa}k%R=s!&#g`x$>j1qs`@YWc?8{L=R zFr3#6d$`|uo!Jqn*q}3FI4>KkEhY=&Ej?Ii2ng(m;f@$~Tz5*%vUFH3Oz8U=rV0H` z-A{%6SB$2F{*n%;swu9o090v zgN2rXUH-%lO?O{D+;6WM2=*DXfaX@3RMko&I7C$KnC?%U`F+&ipYHWv9q{)I`diH_ z_71~;kv=I~`;cs%{ieUow6~^Af8~(BbI>2@O6vZhRQQuEhOcRF54yW^pW?!3+Tu`A zb=?Lk^Hl?Ip1+s3HFx^JT;Rc<(1>iu+eLX-mKb1e~uPXesoBmBd3+pU0N)Ue_1rz7rHgNlPS<{BAOV}|>-@wOUL zqjGZ6U{J9~M>%9LuGk%>zQ+uP*67fbN(LDoa@c=46w?`3qkRrcALELPcNqa=YMVj6 zBTQp5wAejh*lX0#;=zouvCPmi+&7FPGO~8a^PJ4UVxLR*$=KRrxJQg(HM)4*VZ(We z@x{rt1~l)EkFe1ny{rE1`NsK*d-Is}GwIGN)zeX@Jl5@%^#S#CwxsnCfLPrb(}P0{ zHr*e~ebyM0x_eZ2hYkBMU|K3L)nk{XyFhd@y=vzl!94{9%OQn@6n#>b=MF)s!Zs$dN!&mFCZ@__V$6Ot$`s?^0 zb-(?_L-yWB?3W+4w?AgbAG6baE_3(DfNb}v?W<~AIw)rrZeLNq?p51iwFMB!m7{7q zu5vrlD`$@P$TswTmn7w<04kG0f0o2nTV32OY8NcISr8X@%i^1gf7i5E47)O=%l9+z z{=jE}ik6>ZIb!;J#%K2dTkkpE?My~zVSqn%aznb+s4=P&Iy4)wtr_Z3|KU$#Mzwjp z|Ai0FTjrIEtx|a+IulCwIB)a=qj$Ejka?8}Qf7T9Pq0mh(aQ#FHJcK@owwx-e8w7c zCsfIVrGxQ#8R9{IAs1M#{r$&#WVhG1KT-SPIo z8d)Q7L%?nKnB=#M6Pe7bVulSdt!Av1!Zb0P?1QOF!_06JzL>VG#*hFmwWz8?#r>cy z9`?2JMA)wyo-#dCKx@nVeal__bywTX-l4PnXX#m>j>n!u%)?Z;+H5 zC1uWZ8%bq~gA4aDLa-$*XMTqx@x@l5MN+ekZHNq8Nsk$>98MTPI|;2Q$++Q8(J9#z z2HZrjpfmTgO4FSamfcK7$0ByK5lltxCi=n2sLh(fJrO={*bO}WxDHR-z~d)$ho9@| z7;AOmbL(QdcT%@y55k)WySoj$mP`-p0ToA+x@+&VD^@thSB;#3 zY&4T#RN=^jvAOW%xTvla;3T-IctUR4+xaRWMb{=I?H$)spJrKB*!5mkm@~Y*pf^du2k=s5v(I& zc_Inxoze4*Jf7u`z!9dSGc6{}TO(PO4%qe73NwI=p?V`=K#iEvRfe$(H0vk>QmtBQ zN0u|Z5NkY#Il-w-nsEGH&9r4#%gC@Ccz*gTtPA;7fu*ly*%LQs5LF-oLBz!i$BY>| zqsP#+Pa4&+L3`3byfMh~gf2d~NG;bDcj_j!;MMkb&(u?~$NHpAy{Unkm_fzN$TEYX zhs@P1OeuN;gGqX8{V5jV{7?(zyn?r873)<}t@SDEVujh5iXxh%TBi+JwzfkMsXw&< zWHbcibwJh-#<HC0NtX08b(JL%Ta7?Y}7^FoD;WH>D7!(yMdc|S6B6JOiVbGt}p2=^y=It&~>-vI$y5oNM!|t zDWjc_5)gVKIc!OoNEzK`n7wA?lTGQoFXvjUpe1RxS&}!8V2$VwBOr5z#Ta!BGM0o9 zh()gDj>91)%n)|i7IOnqKdU^65H&f(%V9H%Sg29f$rut;#4K&Aoma5XT72)b>gO~Tq% zBW8@5&`D5krM;%0g3?wEfs}{N8Vbepl;vF?@%+)5$px$z@ zw5v}sOsz(K-)RPomiID6Nt&frGo%LjXLFi$lEI8@7B?`VtEn3pz7EUnh*LdjL)%IX z@jBWH4!0R{hgb@IAM2(jVQMkU-;j>D>k?gdTg-qWx6z37{GKc>3ES&*C)pXSk4Kyh31+F&;fsjo zzNghCU1h;vS>i|Sn}67r+}s-5{KMAN<{!4idYP7tq^Y4ux@>6`*1Hx<0K;chUT*EM zH007qS2YZ3huK1HIX7jETG~kynyVegqS?}*yQ2@e=rsK?5{%U!a?y3QN!$96w&Gze@sRdNN796FZ-5XX;@JS5;%GfblB5k*6z00PtZK}4 z79w1;9U4^~dt|lc)x;io&8mw%G7R4sd*l_XKK96h*HtHqIl`Ui)B2~sYCqFA+dO@r zQ=i!A*QPhY1>%cf_)HX52POgyA;!oE;nAkVpvXzHEM?YPVw_qBt;MAY5)JISod(O< zZ#7x&Yi6J!eb%sF*08!Q_+r^yaLgJ{UANoxwOy8meyG86c_Z=~x3HVF@%K@e#01`S zYO#=x*wrZ{6j(r`J@LvhmMxo(RHY-AMn8-?Rq0I#t{-sf;`jMY7y2)^o%+4?nbQ%2 zdDpf?0xcHtw4IiAz|>wd|MDEve|?X;zB|~^<#wdGrna;a`VPC*A-oSfK!@-?2}9cr z@3X?xb}HUy*N@!E{Ez8((A2m7eY7l*|M@Dn=3o0GcYO2wr>L=4m5TN81}k9X+Z%Y3 z4KOwxDLv5OOTQ^IwDgd-F|%k=qan)~6y&Y+X((e1!p9;lo)pClJdUc+L=! zKvUX4e}~#M@z_#mAWadtCZTfI-AJn*UlNV9U7Q!-5rP>4#+Ydmd;yE?n1Lj~El=rM z785&-xi<+#fU}i zlU>22@p}|Wc<-=Z74>8AvT1KIy|}n^aI|WS?Z2f@rnK7nQWjG7i{^RrMjKaKC!Vgp zolmx;1uzIXw{76sZxB6foUKc2LNEF-qNGQZQ-jcZ7oyNQC@sEG1Vd0AlXbJ<*GA+B z^@0c91o4NQtAj8zXV$aAlq6yDQ$3T_I0-+IK*=)O6%T+$aId$WyHd!g+?~xNlOuGW z?6VION+^%Ed>)1jN#HNYOO-pJ>I6s}G&igu6#U`6B$~9uBZws*nyE^_b|f}ls!Q}= z`%Uq>R%6?$u9!A*rN7uBa_J)QEZUe1DA15{Z<|`;_9gti5|JDvR7^6-I7$Lx>OQV zNp&JBM>Xk)O7J1WQEf_PQ>PB(t(FdrukcuvT+ zR-+Il9T)m8wIzmTo2DP|>f@VcYU7bB_V5L2J#Jktk4F$AI#qCO6@d2O)G$&F6a*&)B}Y~RHWFdx@GDyl-QrWC1-r>%-;yqSg{GEF#w zH%x6U^@xyEI|>J+)i2lK4ePLhb%(Y;;%cQ`w)Rq2pe6KchPNSR{K|CJr}f}Pb3J?) zqzDm@kK~(G<#LVQutv3x3*jq(Ia*_pOD`JjLqTg|&~0UsZ8Q8ck)R#CY*J0G>z6C? z#uZ7=bGHGxxaEW?qHVcSZ(OOx)2JN3>Q#SMo&KUK{Y52C)5_CfM`Rxe;vHPN9TkU_ zmiM|PkWO!p6;zU>O%$yCL2bM@sE>CCjVJ}0Qw#4JT(E4mbgtw?uYRTLJbR{BBwc>z7! zC{FQ$9jQUTYFeL2_Fk+@{y|Wb*FI`025z^M!fR+F$a!9dUBSVh27FfAYie)8wX8BB zx}q);wiE^yHfZT2@JJ}n>iABHM#^W45D#E9HVdo|5k`p(27)(PLgHYNmIJH~oC)z1 zstw^{%BJCD;vz}=Fao4=6SfK)XX@kkxyYtGW+l35QMaxr#gUvQ(%Ka;f_U)LKt-T- zqk56pl$sjgL~apZvdi^(OZ8a?XRED1_J{ar1LC7~B0hqP5%E!5Mtszw#7CgWg;_)@ zrWRYvef8#jRYU7sYPH^QBOP3Z&vJLYrS5twV%x12I2Y4rU57flGy+t|bavv9lyk4K z8jq}v)TCsc<>PN#9JD$W5&lUryudyOdWGEJBqlZZ0u|E0N*QehQYPg1X+zwBvcAV1 zC}1UXnsr>d*KUsWVB^$Zr~na+KnxkpKmdG6Sk_3AFu5SRg~Vnq@FY>v z8r0Y#gAtO+b+VEsDSt1;!ue6awhu$89|E)bz}2e6(5Jtup=;l$(0Q*ay9I`5Ks&ML zYQ}!8ej2_hHV8gw2t*S$SujYI7Ptiuh9a2a^~BVQMA$FojT_Iv6&8>$5v;_;`=lut z36f)A5@RN)8McR|{3hrJwqrv5&CH9zkFbA8f$P>p#ByLVB95_7MggRg5#G*YW?3>a zGiBk68_`N-(n78xprlbtDrQtLdSe#4t>N5e%-RZjBtLDj*2r~x%vo&0Caj%9__yCT zfTZTNK79Wl!XsttLU?cHDD;VF+c!)W%R6A@QGz4p7uf1Q4>zNg)LKg&WU*S2fs~sgKY&b6?$Je zK|iv|9*SEIGy)7?fO4ZfsXJ{jPujZgz)PY4#BvPe zN3^-y14)Hmpe}A~GwW#46=IWzA7^lN2CktIN;Z54-dNj~{_@gmMs+-L=_Qctu|a0r zLA!DYo?Ca%L_9#D_DHG|Rs46N7YlIhMew_~obcYwOTU>LpcgsH=;*8jbd-3ycuZo--Nf~MDB2?HPzyH0B zq2!>m?LI6$`kj#hzv66%t5qpLP>=_!dXJ|Hk zJ~bB{5Ro;B?m84VwTZ}VeVk@3%X^_)pwR8=O_eKwX#&P%TnQkHAYe?&a^4Xl9SEI9 zK=G!?CX4|12qm|3F=KpL<7Q*VJhn>x+bbWV=`cxF_VzyOj&>w2)XRZPkdc4}JudoP z_oOtTRh|amn#M~&qJO65bkA(#8DgLmthfto7;j3D*Dt+y`fBu75Wrd22ur2Wz7G9q zSwgSb9H4yrR)SkTPJ5$oyh6tORKM*t*K*4O=4lTtQFMP&pFd4Sg*_%&7z6B1;@ z3z=mJ-PS;ri?;PHd@|EwMRs0kWcag$3lW)Ms@pw^kj6e>Zb$WKIxCPAvn(|oxW`ib zEvRryEL!gPCp%H+Jhu?J=tYw$=>{8^R@PR`TX*A=El$Czq3SmRXdg~>0tEO61j@CE zUgBV|f{aDohO-f`;X)V3y{sk;q|{z*veVrQaBlX5S^q(*o8|Fk%`T<3f$fGB6r11G_FkBMDD`3gyCnV za_*3M9fdFgZB~&Y@^;>~yh(HjiZZcwBY2nc<|4tndR&~)+%S08t#jBL#F)fkW&527 z$oAF9?sp+h+gBmU--Y-6+T{AX@bcPrR?Y`y<$Mui8ntpx$;uh|RBq*bD6??RV=li7 zFMgXm%y*#*vZRhg7K5$V`SNqiV$Kv;DBkFv`OI^BIRow7aW>rzT>4A93i5O9qpd6! z6ZbixxKPUbQFm`FWATEIFo||KDbX$`q7v-#WEV~Vj&!qdJEmVXCD`Sd@vbQ=m$!6B zD5Y~i$Egsj+7V+|l2U=6k?z+2fA-D?w+2}?K80*!w1W9 zED&H9SYSCrfQ97@_b%7Mf}Pllj|8mPS$qY2vhoFz53U6|i7hq6_Ox?&+JcF2t6 zgjw$I_j)8*mmLQJ#EYfrt~Wh>R9C&KdiCnP|6`q)^p-F>Q>MS@g*KR*3>PFe^s{#u z4~8+U_trFG|L#nPfzP$uLOAm$Su#i6oeh3z_S-87ewmn!-y2(ERv&`l-KpsLqWDaA z#X~aqmGp?O)!^T76q?HzPC^)LF<&M!>7Qr!^o87e(vc&CTISF6RzdMSeXk~iL<${1 zJc2!4)WwZkw5o|At*VDs6`2p;csCa-IG~5F)Hh{qX&DYKm$4WAW`*&Jtk4ZC=dpCa zYz{Y6v^i!?96Ma5dE(-Xt1Pcp_)TA1v4tz(cM(E!wO)Dbx*yQiV zcYg4F?|$>g-gwh{-*fXjKlt9J`Sa&o+thZADpl$`dFmSVELG0QdFmE5Q&lVVu6*@D z)xc48GGF~tg@uY2s60(qvy@5{s;_8YvNhCsd4ktB1?fN68^i`=@gCcdALw+fuIPt7bWNs$9)cEl^rbh5D*$mFMoO zP-R-1P(Q3xcdB-wZmd#wlM|?>YV}h!Td1-c73XTGWQ{tm<_dLiikhg+6Y6_Y)z^3m z)H`cczILrpADE^Jwd>@$|5m4-uNDaP{W|qeYN6!xn(1n_S|rq->FV#*^+M&X?*7fN2<7*R{qi_{FI{D^YYi{%;LveY8& z?<5CLL{*o131y^q#?(F9OXb>+HmRGmm&yH3Hmf%626^@Foij`sJGmk-URw*EnWoij&WtG!Boea~D~ti77D)IKp!-LJhyj{U>6szUom zq27L-dQiPqu6^zTwMV^9@|;5Jib!ctP}P4&4n9Dhwcq`n z`ZO(s`+f2y>Rak&dEdD&gwmrsF8K&$s@-sdTC9CEIQDY&Kk8#b zz48_C?#G3i`$}s16H*%Aex>Rq*JVmA|9eXE-{jb=f1vh1Dg2lFDq7E{R0zI$m3j_& zpmYzsN^Mb}5$bKPhWe~fC9i?{ccH#1)aPjDIdA$$sLv}+sr=Wf3F<%O*W%Z5>cww`x=pCZg}Pm+bvHtNS*Yi~4eBdGrG#1|)K_kT z>JaKVZ-=@=sIx+?6>8Nxpwf4`EAJo1r=e2)EeUJWv9_jJVsCwvo{Yd&8Zwc4h{HlJvRNX`G4)uduNbeD9 z`K|Qr_X_p4WvWLVmN%NUoO(GTRD3zL)}zX`oR9q{W!B3v&H55`;K-eS@+Hdi$3mr7 zsLyFXk)H78RqFZLeL{7whB_(~9QR7?m{70$vU;(0T&O$0qF$}VrR<+rqYf%pj_vAD zpVdyt{bsLKFW2rD>htT=OSK1ty6;Z)dhJ1>TE5Et9+EtNc0Ik>Nuh4u0F{s)^QMiI zkS8VirA_K*>XcA7Z-zQ8)NAfiY5E4J7ko|qoTE^4zOH_u9u_LLg)#XN8HvMN)hsP3 zJ;N;I|V8}t=Frzgy*{%@$q=qD$9 z`M=?V6u;(LowVb$T=A_=de%On4(w9DCjU_1+)bZ&UZ|~mNFNt!-CjnzCxlwNPyL3x zLVe|%jK3KvzjfcDNBmzoR@tR~MgF0RyXj+pCDa+Ael64w_LKMD2(|NoN~+(=yWMt> zBfpblD-JPs|6Y!Dd|MT1mx&->gE9A*PY5?|thBM$#&A3PvGY^lCuP`(d(IL!eqX@{ zXk}JjgUu(+Zn%-kS~=<#mdfQ5IQ5V791%M&7S3LNs_kv?z+s1Kj1}GIj z+u&3s7TUKgy6~A~Og6xs+lBAtg`4fj-fSXJf1Ugad};7AH*?7{4vK&m$<6o~cdKE4 zLyOYW_3VG`F##v2Of{Y@jSFfwXlrpaQoVD%L&h0RUy89HhIctS0O>mnCr9tV0B?eh z=BdL-=K{CHI*y;KZv>!QQb3G@R4mqWb?hJ~08eHBg8)lizj`RI zG){HEh|u(vChLfvev8;R%*Ml`-7f-Uu;h5t85XDX$DOGIFPtrmX(JgRI9PNnd>U^8 zkRHIYE>Gc08W&WuCKq=R0Qn^7J=hQ&GHftR^H>1GY!Cpl-8vXx;uH!-ZaGGwy1!ko z6gyAAe6dA?*r5y9**0Un?tlspu^BWu&H!i`fB^$e@@@yV59g1aJcS85Cv||M=;Qjx zQ(ds1rnU%RaBXj6dbM6pT=ZO==CA=gyItS<2$*K|sIgaITRA-y?r7|r#Y-%9+b6Y!O7dE@PLDcMgzhx(i+;@LIU%yF3}oVKDp%1P7^M&?(X|2@ z+l7s$xzq&XpOwVbIK!CER>Q}SXf?*nhQA`RIwFSq9p*10Ai_1Jr(|N@)LyHIvL)hy9J>UMhOBZch|sXb&jNO$Olj_zdNO4?E@~ zcgfFPDv>lATrn7g+wr6Z7Le|T-p?=2NDYMvZ~zKQm@bT-NzA%+fd>~<(u^+9m>3TW zVsM(c^d?9y*auUbL9}_^62(K{@;;CThBU$N8P4N$LF5(fL=a4YZ!9SD%>lF$Q{mup zav}D~WD5IZ9tbQZ&!Rg9M9(cE%VaTIAa%J#i3aJnf!>sUS>A=-ub95I$Pie?A}qZU zdU0Uy?2wBKlw^c4E69kvQjoi1fwv1jaIE~wOR~z#k>cQ06PtXu6{23D5&`}y<5WmEe#VN zV4-5@07D zcEE8g!WeLX3Ooz(FqE$;e((o=z*tOt4*7)+5WoN7zfgO_e@JtQE9j5~U~vz-;F8C) z86H`ocRbecgj01S<`GZ>;KIOE4u1`Il{jqJIA$~spu{a9)Q z-4qp~dswd*@XJJL8JOyu5+{YQIX*@#!QPQQcX+adp7z4|V&BhgWH(7}j4J^T!ERGP zyRr6X3F!pyuiV|4hC0l{nXm-ku#LiSPBt9|REPiB1 z$&$s?KiTKrha3D-^CX^~t%D!DA1koYjX0Q3PBqfChEqEnnqlNh;k4cb_6h>UEL=|{ zodxa`&`7Znt-)>yU{35Y0aakD0%oczKCoeDT7`)XSbu%hcu}xzOv7kYc5;w|hKq6-=o*95RVC)E*XJG6oXr5y1n8eue zNRwL$K*G6U#XM-#lx4!~+F&K7tYxVd6zoKL>YeRngCL1@W~VH0Qk4vQAkqZJnPdcm z9&?b7FbV>nG#d^HTOV>ija;V)iiCg2)TDWO3T{K?iAKBPaLlee9Vh$) z*O18twzi;uVEM#g-D?n&f&HCf&~A-Y$W^^Yjv&n%w}uhUjNXPcj#Wgns*q*7UW?^B zaGCL@f)PN=0JoU}#~D$)K!#q574Z=bL~0Hj%_Gzt@<&lmyH_}e;71Y#1{8WT-5G%^ zq~^ApjG6QYu2^3U)LdG60G6hMnuFi@Wb4pp$(@xL#`>_m0|V@&-W7ol@{%lhCnEWo zIqCe&Y&c<-Uw9-2hn5_}?AhT)y|936al~J|DT9r;R#_O^jGjNw&l~u-dGm$~NF&FD zm4vz>o=dd9yri z-9z(OO>Y9#DF1lOp#cVNJUON;RKcHt^)W`(gqjjBD+E*=jl_=GhGk9sgT;?sIJP4~ z@7NA(aw}q7vsZRJK-e8=fIKwS%T_lI#MrLa28{#26&L|2T8_{lXfCw=?17-!$Pr$c zBLE}^N9Z&Lj?^L(kx>A6CDIt4MLI_$WSN~kA`NvK4LCSJ+sy_eTVQuAkT?U`&oB-I z9%$I#O0n|Cn?INv7G>xh`p0aVx~vHHspkD(rc^@gi_(X0Tv_) z3=63ZsTzSSmXouE=WPL}I3f@On}r*QHjr-C?Wy>y~t zi71fBNh}dB*@>=s2%+DpIvzWN&jSG5nAT^As6|h;G9sMC@a^ZZvb#$LMR}Oaf?-=G z#V%bP+)I_FgBBYXAVvo<4ys?i&KTj_L~s1dG8H08JS4I!UW6`7RK{{f}rEy zV*2@!Q}iWRi86m^bBg0FV3o%_F`gfH1W|`MQ*GdTJ_iz9tzvU7d)XuRhjzy82|Szxrt7se#n1J{g^QG&1#Yq~>_E z@^GV%dFm-#3C@%DmmY39ReG|?B>-W6MJjr#Dn(SXl-^&e$iR7nCsZG=Kip7vT(3=-HOHdFeM^@eYdj@D-$N-cD&10L z$~sk@GWw^cjI&cy7NGgDv(+aXPgEVlXM&fk;svXYH=U|H+=SzCY|3$~_Lw<68J=-+ zW@stin4|wjO1L5Hqwo_ScjHQo--bquX>?c8Pto1c>k-BP*(z>I=(%c~MgkEla3(bR z5SOs|0&YrrL3%$Xyn$d6v;o*!TvoF#B_@gkBnqNAf+6o69CQppzQ2^LRB_KkDFaXA z(5__r+0c^Y{Qmky{dI{&ebbD`e{4^<`#xgkOiljoMA=cxo7!KKFw;1>gVw*?K*_Kj<9f%La+3S8Nhm0^okRfX)i6 zHNJE*%2GSTDdWp-anC}J2?>HbK0Knk;tLZ35jlv7MWhj*DT0qCi)^5&p(0RE5e8tp z=@DylqmgIqvrgb>M<@k)azX)$^wn3>gZ>6r-k#xP~)+bG*<`K&1P-sl>*wXtR!zTCm zJh!0dT3qn213zzp+ijhe0cJ7|t|Y`5z$4V%XQFz59o$k9SUH>6l591D1O^`V+az#| z`E55LF-Rsy(0l1F!3u0)<-GU;M$PNo!ejGMGV=5|Pe;xY5lqk}g~eg};Q0*ka%q<- zx9i54pJe}tB>NLGf}AH93355}pX}XujNHDkXTDo}e6Cw|-(zjVW!F)D{K7g}1hhIL zJ=PGFu!87>rM>fU_T`RvSa?Md;&LI119Jo*jE$fOr=t8M9;rcy3jsLp5=|uKf(;np zLK2-|I4p99AR`Y4P6p6;#CJP%iy2x=<$=4r5e#O4n7KzMSPrloP91`SvfHc(B-GLj z(;Ft8#Ti-?0yaoUsL&#(fe?(Oi+kr2mUj-gg6(}Z$D2=23(&JhHjkV!quA7YAI`M6 zWk=_NGD-dPP*2ns=mDq2xsr-9`=zAwX^v9h2y0R`;5`Y495g`^MOyR9Np_jGBxrc$ zAj~5P%#%%QNhqGDw1?S--DKdFG)Xx)@VLn)%L%$mm=VcPUPQhie+G<*V`{)v1)0eC z9}Bk?!th1#2#`K*8T?TRq(I9^1_^~m7twIEW@yH}KWNKaqeJ$s5AhGtirE1)6`$Cr*CWTFEy6T z^^1+;^XjhhC zv{&+|$tI=7ltK8M_jv{+i)Xr%M{j@Tj1A`~=mDNWJvXpK{%0q$85*I33-g3kk@13oI_Qb>frtqP?A}0~gWf=NK*+L;XQcSE zN;eJsQCdbbaZE9ZbhOUkN7sXD*6Nv zNO3dGr8G}qPf^+#X^a?<^3!NCI9(J?Wz6(RN=eW-ad&$!p?OITqU<1%M-x-Yk*o;T zpyUu=5=U~3mLPZ$v~4mx4!rD^NFWETj|8LRu#$ru?uReN7uUM$ue_ zb96B0oh;2lZ(h8C(9-e)s^WZtB?+nN%}$tanqmz#`vsx^ZF2Strxfb<23N2M z+i;&yXIWT{H=GmlQR3(6!I`OWX|jRQr4v8kc$CB`jj=D!SZ-&OnS~^9vm{`OMchs+ zT|pGnVRe`#hazha{Q@i{4k$?MGVz%l0bPs40z*QQbdWH_%C{KcU6KHEMbd~}4M|h* zrAd~g8I0oMc_qZXOosx(&WL@29I|^Q2$&GJ3U+2dVJQKNaERd5SpvI=-NBJHpn%CQ z8wKV|2qwT(7X(w#EI|}->XIXq4Vz+z=*HF}Ao6%DmBOLCUa1lYrlwK_P%IZv=0e29 z?+c=kc=9AgjlrG*=1VbUD+z^4QbK8xlx9RVN#wmCp$C$0fyPCkK{gSAW}}Jz1^Wa7w_&5;i|Pg=g)xa(E(|+}HIRHGNT+CSn1^un z*5FPkfontw!*UmfH(;5dfJMMT)W++jz{Kz(z$f?UkVWI~gED3p0Yr9$F0nTv*qJa= z&$S3;bNZ@}&vK_8Z9YFkO5#c7o2M!pk3PTTo`+|-MJJhRg7}u7VWOK^;2s#5juMGb zdTjL7GCUChSjMMqri^3Tne3BLc#?<);6j3OAp2Wz%D^mm5(|=?vNt_R3Q#i*p(NAk!BfqhDk6Uy(M>4x$!g$j|c4HDT0=`rHo+T35(8_Bfwmt__p zD=r|!q(#9B)1)HAd=;jNiB1`&X$l6}f=rW#u0|FzP*E3(*^ch^V%ZU}&RsK|;(&SF z2|uIS;NF0JSZ1Ib1@Kqc#}C*iV2Y8PlKpmR_A$}!U7UNofP0wI4Pzg|1P1Jre)`xa z#6S&ZndmBHx`}iy^TnZQqx>?NevbrMT@p0tQn#>okR%N`NC^g0UD5hTB_m48uW0Ut zZ;)I9fd!F9-G&uf3Z*HWQ-GcVsBW1G@tMdzW44mTGktB;HdtGdP92s1P~p8YSDcn?K3{{s zb9v8PBw2!@WMDQ*gaJCJL+lV_$(to$1At6fL@EtzQ-JeEgo}$FOJa^t%!s*Oc_93< zN8B#w+<|r?!(70rS4J|t*q}!j9J2sofjafDT|6RDFQ>7jKP?$`Y8yS4R1SDC8SbL%{24V~S?0WRJ5(^i=bP-H&<;7GJ5sY!gAhH^WKTauXLbSkf zY4$owU=+m6Dv*rOeWL(I>y8p0%`xUo7%Q6$9GHM$t7USD$kiV1votwkqJjlh7A*LI zAVc%R%o9yN?XTC^$&`j#T7jA@LFjE_qBL{o*cM{8 z%aEA9jfo&mwX5`e-6KFarjr=fz-V$JtN1!vbb&v=E1V`w2W+&FI~N%Nus&6{x%I*zW6IGAuQUmMK3I1`nga#Em==7PGTpk&D8~P(&;e z+{p@XOkj5~ohnQPK(1IhAZoIxek)wkOIcHu8lA9(44$U*EvDNewzN2hkNz98=&=q- z5jKyY2J@Dh9wOvgc!$cpOV|m?2M$Z`XBsQwLduX{mB9`4e32FCZIMA`3>18NSqb3j zn_;?yfeK7i(|EJPZgil?p@P}h=uFK-F`_1-a3W$)XAGF$Yo@1TH!V$TYP_+w8G|bW zp&4{yhmnwG=;xRW9o!L{7;X=!F?pR7VJgm(VJ$Mo`E*^P?G~8^Ifv30vB&WCGAv{a zXQRnLVcIL0!i-u08KYa2hW}JQaU+C|W;(AF^b#4C53!A^>1_gDS?{9^SkC0bt=-#$ zaWE~B967=&KW~GaS!!bajE!$lsI(0vdtjX@?f~MsC?ztzUjq0uwc>5&VqS{1MAU{r zMDtP}$`S0IhuKR}^`qMH3}Rs3ws_{yr;Z}4jRRjvaZRJ>SYmT($2&$2Ime%7UN~*o zp%hnAS==dmR)$#i;~j&8ILF~m?zHRu3Bx|axpZ1ChX3|$jTb&*(eao249^L4Hmidn z$7ax`>7oK#)CA_D!B^m%!`Mb=e+Xj_EyvwL1nul`F*Pm3{xo^v2kcb2;3@tfeW={Z z;7-z;$|JJbE6lA*#Wpt%{Abl;qNjRhZ$mlGzQov7sNrk^&2YpD>K!7POd|B30myeZ z`t`886T2T{tHB)JA*?x=Dd`mk_UJ5>Vni19H3N5|!;Ba4a7r&@3SZi55$Ya=UoaD> z9B!T$=;Mld7yokTGb$5L`RgDe-bF5CU|}4yVF$)AvH5rC%$Sa`O3y$L8ED@lyYXF^ z*CE>)t73huC@dEo?o^A{d9AZ0b^=HnkZdsbTn{2DvYQxf#gWXh_YL-08u4Mh*bAX0 zK%(z7C*FP3a<|O)I_J4vbI#=Vww>qxF{0`*mifHY|WM~g+AX>S$SSO?fx#`i|ncSjl(U&!%DD*^nS0@#k*qI5vU@sm;rGr{3*7t!UKpKXwxww?u?%3h}goeb1@Q}jRxLGM$f>cOCHkC+1xYBwd3wD zye4puBY1I1)*4r=!g^X+aA;3sN1YZs>O>$EvCtswFF5$nfX>>Nn(mP`I4y&*Gg4K3WZc)Hd6^EO|niL)r z`$>?jdd*YxOVYr0nJmT18j276DfS)*5ssy2p)GX`aM=>(4zQWlBy5&?#<5vEdZrq4 z>2u>r+tkj;mQx19z1Gg?rr3l=db*>}0F~E%;VOZVjZz2Lbe7W$uCM==!FK1L;rNOKepya9T{MR3t1YZSmdSY zQPjvd&&YJ*K)x=d_I{}u*aCBTKFB-%Hp|~?*;`F-CG+T&Da+osm~pS=^jy2U$y+Wh zH}AOBzfoKp3IhLL`r{z3?_e>EmyUF;xk5Xs@m_4SLUiRr;U`X1VFg~+gL?t8Rsq3f z^1&%a*vd=M7n<10i?oF+3Th72Xmpk0Ylnve=Kp~<2ASN)wRb=zgWy8LLBJTjm*YbN zK20|};CG08gJdeceb@n_)50)_y2aHiayl6BL3(7sN7!gZ1vb`4Vfb4z;9t61E`@bePpy9=m>yP{tW++@HPC0jP zh}t=Ac8-OHCdYyob0U=ZZJC+phjZ4*Nm)HsNl)BghK~TAo-CENdxz$*7j?{GxWWQoifPWb0 z!7i(>Gu9dN);DhHUrhtx!xVzakZ5-QsBL4*s)2vZfG&2k!4e%Y^oMpMEaFnQD(WNE z-rB@8*+?|!_s;cY?nE_pT4+)|5Zk+%)&wq3U4Jfs)&Rb)$C&(@sEfETVdIvo?-5X{R37K!BehZ*3&LqQMqaO=(XTcg*c-Au`!{z1D!S%AUbVo1)a9InQb(=*FHmFj=}T5tes^l zne{TorSj3u>*?i4qzU~2SvH8Vj2o)}@&yf?Ulj@1DOw2|;mU-yT@yAo`h(1s69!8O zG#CeQ7yEi3Js73AJIh}9!V(21FS0`(5BiYLgnZn-0qeTTqv3N^JrUe>272@;5s zNr*>9iosA?Odl(IO~TW1M)ph=131f(st&f`3|T!)S7qk;xz}F!jN+8R=9T~mKx~;M z7*k%t%1>CrGsse6{t^Iqpd(?{BIqAuHx!ew3Y&m_(BwIZB`-|L`e|DP@)LiH9=ZX{ ztcWUthVz6lm@KMsYZQM1B7)XbZXvfC?-AK!a=u$gTabwn5H*|Me{TE6BPQi+(P^~eF78v#D(?=_2_p;eY_qD5M(bvsytbFP|`seN~zOe#Z&1R zjX7#}MbHJa00^={KI^-M$1#DGlPGkmhDH=zCYL{X&B`L3z`4KymY)~(@dNg$OurD} z&mZ8Z!DW_l8Eo8xB_i>b+_Oh8(%m&JZddBpYuXX48{8F(u=hN*GTG*?Xz=&9_-kgm z1?V`o{Hg>G@JF3VcMrSYj3s!M9Gi4jhlVp9+#_VcF|Crjj zTB3hU>5X^oh!UkW4lV{><>vE5cDAlW7)YH%>UoFwg<-N;2?`nx&Zb@D4c~?vH za!cxR&%0Wpms?Vod*0O&z1)(z-1DxM=;fBw<(_x7L@&3bF892vC3?9fb-CwVEz!#@ zsmnd@YKdNMNnP%FS4;GAOX_mZ8&RT9qPv`t%ff8_#Xc7>Faq}?w6gerp+g_oT+)HC z6G89^qEN7;N=S;-&<4gR>tOh@fc-YkbB60n1s+gzkPqKqpJ}KAetH`4)6K)E+~ zxOSH%8(4Aj%Q6jX#80rnUx80c12A6vV6$g6&EznFI!hA`tU~(Wmjks}687#AOX#Ix z2cwRO=B?rF0=TifA>9Fny^&}T5VyRTa}*fJ_<(sPOWIF)y==} zv8cDXvL}pXX;^SQ1>`dhx@Sh87U1LoujdCFwFXcxP!}wGjNEYh65CY4@tp>uuYALv zMJ!ci%R)cnO`pc~h!QOnELPT6#IF(~6|YNxG=qqwfl=zfTaU)k9OFwTZ&+|o<%#_G zuga6Z><&9C#kO;Gm>BS;Ev~s z=d_LY-lQPG#S_5v8a=)$LD;P=tT3xO1@#1>D- zElL)MeGnBK>aNU4->#?e_r+5USP|X73-1J7KwV_XYOi=((dNX2+7p`yF$IuyTY=*X zkXI)FjfQ#kS{#VnCAdZ<3>IU{%)u2DDfy80$FE(%=8Xn3?PExCl)_9vO31v z-x^S8Dca4lxQJuF)hC_aR**En*@%Me=yc&Lvd&<=s&6Uw3q4WtB(Ue@si**g;~8(J zrvPd@g|$}D5@@6X@WgUE`+RKsTu`W4vlgd?2zbs^Em(4dNJ)cxn+9^!eGrottnlI6t;1I0 zXBe20A_DzDUChr=)~Z_lafF|ceRMKcZPi|AJ*altAmEQ8n;TU@4^y0In&^EQ0F)^;W`O050(QgoB?JL-Wcv9O@%jN zX)%5Zh?q7vwL-{P1dzJx3#Y`&#o}s zWd>fV{xThmP4@QoV87y+;Vf%Q-`1L5*WACudg8Rr#U5=L#5-?yklS zn1$aQ-k#C`Mg>=77i$x&)-d+qOZs+Lh}Ly0KB=^>C780&h_Md?2a_{c(06V(>|$Vb zf}q9|fC#}PXq8b)2Q4nX@<9C6!-Sb4Q|>xmO_*k!zIvcArw<=jhZQg+{Rz(ePxcuW zTVv$q!@d;^Ta&tQ_>XK(nJ~<12hC|I&c(WoO%W}MW&_O;+SFQozi#7UycUZi;v50z zDy<6sh0eCB?K&q*qv{eAR~u*}+SEbtbA_f!iG$oK-QFzCDnH(22kojW)eMRb4Qp3h zHl5U-O}7~*xXDJHwgnU{4++}WM1x##2U^%fF#Ur&C&H8DXh+b%?$Y}?H)voR+G*F) zyf(FgWJ~kf)@m;an%Ay}8|~%NyoiGQCv936D(I3_ZSSJHub2P8m1AsYIpX5#qYdXv zdm>nWMbr7cjo4a4}!Hn@Nss~7{m5fV!`Wqdf!THyqXILm{1Up z^pzZ=4;{GmNIUG%!J!y0I~In({kSya{?S2U#((3gRNImEWo=%n73*At{~odR#QG|Z z49pOU8(tq$xd5L8u0e6J)FEaO0xCTy)Mgk$@DSFuxOX;r+hcB?bf(!C9v?2dR@~|A z?u_McZ?;zwb<60ZZ-_IF_(^Q;jAa-C(F+&FCAC}tZm>@wC&`H0W%LJ6C*03k-Cag> zFT-Bi;;(Jq9rN>o+h!j;WFosJw|-4`EFt9&4C_W3wWNO9R=*+2PXm z*X1W0PML81xos`>s))U;m3=zN-b&CIn$C7u_WDc&7dCrqgy;_9XNb5!f^*29Z8!AR zBMI#N5Pax|>Ey3~y(u2BModP^31D;BtGuJyLe86JdX$eQLtNiIW%9X$)a z@M}Po<#s=8INjK^?TQf_P2%pXJiph#oQkMYCkn+ZDq;EshZ%DvIGAjs?lAW2pt;1z zUuua)c(MP(shN3=!9O0n0CN}NAFY=T1S%QsuR3_kQSwUBLv&+>$w+@*Poq1j#o0tR zXRJ2}vA9}C5XqHTdyZyw3(i!!Q}=m`VSA2%U%g*hzEeL#yI<4dZEZ@6 z=#4+ikXyhQV_v+x?R65Rg(zFdtC=u2Al{c?sv}Q;5XT{R1%gIG7i@O=4w%}YfAA!D zSWbYavRZ@^3``Mdz?^^<-zsDmqFV^SN)FR2(_RutI$+3&P>kq8pgr8nMHWJ60d$4C zBObZDa4FKJKPWw=M7&K87T%b2q?=&&=NjIHp%K0g1D}DRv7{nxhJEBxhg)UvS1*cDLm2Ac?#C@p*m z9cV+GYw-3X=wjg4g(q=u#6F}mrEw1E4nD?2K4XG|ye=vPUGzT0BqU2Vl}DUH;vS~= zlF)gQ)RLEjXc*#QANigDOa$a|r!d-c9Z>5;)*`Lu5|l<5lhfgnRw3mTk&=^iv7{U) zz5lV9((OAXOr$Zn_DdxNgDZ+IAncT-j1!>20F@Q+KpOF!iUCBd!3F56VQ_#QEcfvk zx}vvDIL6u1&OAKqcDCEZBkgMQF*LLXqIbC>52Aj(m^qBi-XZ?1JhFwn<*K}x{eo=BIj;W)*Pg)Yl-_vp-rWvq{xXn z>B;vgh7@fLB^4Aomjp%4HB!_}uYev4ikSBSG#%icI0Y%G$oG^qSC&%7C6s&_Wz48R z5d-AI?Dz7ESU8&MhFM94Tj6BNPdJ*|2K2IBz<-35DLxY6QKDDDYr@BH^gfBV6maxz z-5KC$x)I@HI64!qf`Fl!s&PLUnijwz7@7tECsRPSFf?JFYT#)2Ugqg=y>K)<4@c*5 zT`=9FQ2`pcHwMyC*jdwz@+Ry}Xmu(C{mxk;l}VvZz!aZ`PMNJY_R;N7o?DFR{IJES zmlmS1TU9*+2w8D7waU(U?{gY$VA0BrOV!sD1KOZ-oPf0~HO0Os%2rmh?w06z`9Lpov=HqjQ z_YOwbY5Yx5eBkVfydg29@T>4~G(xBW-mex-M#h+mY$pM%hHVnn%mp@CVyaDvqd24k z6%`~vGDcSY*sIGBH3N~5`;5Dd%K6~eG3}DJ^j8v-0hVw=IYwwLWtU^PA(T3yI3vb# zLXJ?@A<*kaPi+5s3WwJ0hL-E0)w)NaI3X~cGP(nUfz;&9h}h+Sy+tDsF}Y?99TFl5 zh|8`9R%=4Pl|UdFVu0ASy-^pet#p0Lv}XW@_19Zcp{b9|JTF=j+u($G2m^|Z854KZ(mz&97)g~m*u|7yx7|1j*a)O0~Eb*5)# zdhv$oy))Cdv22-`>8@hIFFw;FsROC7!KT@H^^Epo+T6f!SH2KjXg_BmVX5)MB{99+ zg?1@eKMMt0(XB;|nlkDHVA^n|kuYTQ4VQCUl8o+8&w@HgVtVxpLf5%7t_x|`I-&XL z5K97p9Y}J3EF|U&0EQ%c4Zv9DqhBazFX69AHkcu#09HLipec0FyYdY-kYttNhqw}z zt|YiwhPbO{h6+qOg%&p7yxR;Fnn$>_z)Uh;6*k*70F+KyJky@C_&2qSpEYgq_`2G> z-14LJS~C*Xj7+pX5v!+1Uy`Wj0jQQkc-V(lTXqQV;Ly@XbbH3pjPb;Y+9NIJYf|8t z#^<7!o)5}lHUdvN8-d3gh`=MjKtA|@tR#Y5>PhIC;SqR@-GBK2JnmBp!1GLvE`wS( zq!|p$K8YJjQBNYX0Q|_<>@YBoK|6bax?L-@Uw*(-30{G;pc%#bl z19l+(#KHV-6kw~r$R{)%V~r)oIpb10f6Oc;^cRV%mY1zxG}4D&&gn?aJd174fM`0D5DxNc zRFV-5es$xmt>&OHq&))(LR843lo1;V;+I)8qO*hFzZwKgRS7 zAeGRPXlNtA!FLgc<7)GM@}NW0k2Rd$px0&0)64W}bdggNZSK@e+ce!jYS~j!MAB29 z4~;U_pp{?c&e7Z%BJ{V59rooX<3#$*jzl{!B}3!!yW-?b;9m$5!RiWjup&^~1bYFu z41W~rM7wGBUMh^@!0#rp<&>&nDc(PTQm{XBya>_EmkYzX(s6LX_ zVgbr+z^fqvIf;H}@oLQ)RvI5c?R33IU%mbhZMlGf&P}pcvwt$slnLz1E5U};w`k;hjU0i^?1R;?C z=VFGu-o)&Nb#o9axs#}^wi%~cdnZUlV;T$P1JN|Ahy~Fg=mBO8lBNrJNr~%(HB^5A zalt?u&&CBS=)E48u!VhSy6hyey2$$4mh)vj4Nm8SDI$bbWxP<~2<6fk`Q>W(8=4?` zI}ol$B`~g-4}>NdAq=ZX+z=y4XeE*i(cVI<7>5CsEgC&yTrJQsB{@*M6ex@44%*Am zW+cN^MraN4%x0<1q2#3IHT`kRVIPqfaiAabhYf7NWVx3tuS%kG0O;(*~vg*)e z)uYKmMI2f|%$loZ`xMGHR4$sdDVN-Z2Ed#z3~^U{Xq;tFRm(d%XyoYcf3YBv{n$!f zB#7kbJdXZ;p+2Do0l)?hE|pLsQ@}-I9cX{E2aoJ&#qiDE+D^EMn@))t1-{TQB6!}*8S_n>?qM;AXW(n)#xK10YsA1`(NtStXA2ow$PDae6X54V$W3!=9R9r31@M zEW5;lDP`EixEuD0p^@>8ub_9Vg1Z5}MW}ahx4~s_6`_9(*I+di99q9J8Lf$80m4gT z7jxlnq%H6j^uD3m!wqNGW4}wh(OY!8DA^Xc3MSi_2sWgTT3BLw9hh`ncvW$A9RBS} zdRc6CSUg~%{&JIHFM6eRO|{2no|jN@IC0isFM&NpRdS}26Ru9pw1d6SiJ9qJ8`9O8 z2&S8OET5eDc;KHCy#81%3_|!lk6;>Ec%Q_fDIs*vfyVwK!pL^C;#<+~E^YTF&-w9e zcZb_$`cNUiD9lQcpn-@2FI~GU#4=#?J#&g#%YJB3{kHzhc`7_p(5=Bu$ za$~I^fr{`hFNmOHkZ4E%pPOmi)I7k9_e8~HbCLuCik;e!GSc0P$ys*#uOJJ>v9Y3W3((kZnbQ40mHyyi_nG@jPs=F#%zeGk(=g6pZicY^r}%`hvIh$vXA*q13A|3HjF#62 z<9$*j==BFfDKMEp!v9lzLO4>mc?KQ`0>s}b0SM^lx4IMvO32M*fW*@@mvDZwafz5XDL%u`IhnQadDLw?oWBglUUV4|! z&QJjbUsn=;H3;XuS4#;)16#JcaunBq6O$CTO?HU3TpR}9BcPV;6UkQABDI)d&n z`9t;0;OR5Q$QUZg*q}Ru;dc0005Px~!GlwG?+~ws4wT)@^(G2li{Wm^|0B|ENwghj z@;pZF*&f@J{d+2>vY6qJ$XV@u$s03y(F_(cbCMt3!)C^ z&1HR^oJuIz_$;FOgq>iSytrqkTmQtkZ$46qbp?db!bAHHQ@UOO?}k13AEs=*0^SY3 zn~h?Q0EiJXU2;&z>IOR2bR|)8t3d2P6Xjn@%X$U8Xb3DXBzhdVpL9R0Mb7xY7D1~} z_wb4*nq4@J^Q2R4)}Yv{!nlQqSbo(I)Qc1W<~^5&d%3d0ZQ_ye2Zyi!zZOOf%a>&a zAP4$oCKp;n?S$W}f?Q3#NvUgo?0Zhq$n-`g~Q{+w%@+OAPkl=@DddZBujnx<5KzIs5-RM#l=vwZaf)u7sx+ESqQ zYhj^oEK;X6UA;u9=a;ChIflAUsdSloSTj|HQpYOP`&C5E;MYoJYL-y{QUw*|K5BKf z`k9KUSxSAhMx7*wJndCe)E8BgoOg1Hdar7hV=tMiZc;5m?VhU6t5$jLUA1bj)+W^J z>eM2wU8t{2S2t+0g!1dv+qBt2y(FYQpv@8L+t;Y~X>)~YnW=Vb^MpFxpr&c_h5Aic z{kL|lP}>dl4edI4+Up|fqiTUr_eE5PS|~aF7fVgm776wFsQRJ0UZ@wx)D&&8T>F+r z^#bkL>eWhZZBie|eU6mI^fvWP?f(gNU%Prld#+lnRM%{EP{w1 zIe#ZPXnL+{(q5uopww%hr}W&H%C(>3UO6w5`+fg~>i60Wa>e&v%v-)(j=ldSsv+kU za^C8fsb6WYlwX&>Ty53kmFgYZKgh3N{d;v-dsUFrSE=u5uU0Qts`)i4C-*gS zto3#3``SMWb^i70J=$yK+Bd&Jy;OUhcKau$JIXx<-A$_TD?IhteWaqXR|TB+B+j~x87s?Jq6yk9kI?~?m{ z@&js}_HOyL?q*e_{fm^J`5|><&U@tATRsAByjQ3NAES=mC)C$IuD+|iU#NHdt6Hvo zfIMrz_&4>0`k>tJ+$Yr>?Pht)Yd)=ht3D*>)qh5PPW!O@y8g53Z?%s|nfm{(LOCCm zW0U_wy-@p@P&a%*eMI}XP(S*j>Q|qT(&$=3PXAR+RVuku{YL$p9Q)}ll-MVQ|EiX$ zbLvyH5cT_IYL)u5s#R*`a`o@pXN0Q$64Ymf`pOEZe;2B571ZZw=Q($-hWfnHlzP_f zYNGlN`PI0cV_y(z%a@_PC{*Jbs3k&uqXTNGQ0;4>ZV_tlI;dNPn*U!=%Y@qhRjB1c zUB3b9KZW}4MyM|d^}NkcD}?&dT~I59dePURRta@v3)E_%ZrBEOn^5;{hq_&;SM7xQ zvQQ_!0reH3Uf&6|MySLts1BjtvIpu8p&s4~wN|Kid=qM&Q0Kk{b*E78>4y3*q5Aei zeO3Cun-9|et(O`+co1&dAT{`vLu!|{QK%PvhrVQ!P~G2EAJjGr)%1P!R_!jSqc8oB zN~o{NvG@Lf_WO0It(X2t-Kw^zXDfC8kJN{9w$it%m))b{YMY#A+^b%$ZI`6(O!ARr;n;`Z692sU3Xkf&H1Lh+bdl4HuWtz@0+grvg#7*r6<(?sBXz$ z#r?F<{c>&b1M1b<0cjOCKB!)hb5N-5C)M+F4hhxosh8$_Th4p-PvPwENH6e(pQ(qm z?+SI}BkBR|dqOSt)fw&kLPgH<>;DKf@lo}l_5-0#{apR8_Cxh5YBi-!YCn?p@y$N2 zu;tgUo>wchyM=0dLVZcQN2u@qf>wL4P;dBO)uA1hH~QaSs`=Uxp;~{f=4w6k@7hhj zAy>U}Y{zeDGmhN(J6D^LbDvOen5fm~92M#llePAoV?yo7 z*P3#U3w3{?HY+DCWnWyPy;yVQ*lS9)Pv@MF`?=*>O1odEA606PY7YptyINB@4+hi} zEv-EydEQv7tCe#qO*5P^m`kJ=$5J z{;65}ly*+22V1m{Xpbs#`N}r!x9aEggxU@5+V9k3^pg`_I!mk4QmQ&9_bszImX<5t zG)LQ{^$9g$o_4?1FVxBT+A{6DQ17~qoIWnpFBWKPwI_sHxky{B{X!^XF;qs%ulw2B zW9on9*w>$dnv9Hfz5UYSQ0m8?|2xwdMKRUhOwRz2OBM`>nj2_9E@epcELCfvr4cmM1|$$bLZ0PJk895`P(z|G)-*n&Fn?hB)wX$}y$J4lQ_-vWw?# z^qWo^VU{AlRwk@9QF~kTsq8F2H)?OO+&is2%UO%{oMqn;@ef9}03I2c6p`r1tZ|@& z+5y@$miH2r+1_gSm>_fo0kerRJvwJk<@=bI7`j-j$O?!ZOhn;)%$!reYg3R_5gP;s za8^uA{3Vd^Wu8+#>^9WNnA`XTk?O#70$9$)QLHUu<8DQfLTpQ99>@8Kz|c=$XPLr236 z9-F-7uj3!1qeoaTgSTN4E z>!FPC^ZP?b+fGkAKBsR=a=u&Hvj7j8MPAwBUzMh;e$6EM#V>sY3~P)u>M+ z=^(MVLv7UKezo9W^CZBGuzka!D0&vWiD|vFfHrD(rzhJVCvL=?{@VDwQ&W!2Kf~ru zJvrB#c67E^H^-SqrW@-F_qLc@Yq)D;(+qc0)R}6y6Qf`fy4x(D{T2&=1b0%DGbTk3 zS~icK6g^-8Z%(?OVCtlnzsvF=wpiZe=wuvXEa#Brkk##$eZZ2}oQQu;uO+x}8!Vz# zSR9%VEsR@zWPSw@pM(K8Ma~aLfpG*Or8vIWDUC0}f^UIS*>kN^b9@e&Zu3I-K4Lua zQ}9>DsUxYkv47)3>5e&X3NV6?(g`d{#XNy;dvtU6MWq%ifexkEvABEQA&7dRc;wvt^9> zIA&8OI$n8>Srh>*7)*_%Q2R{>Kq`pIravPfb^}ip5R*(l6r8=?46TY3MQ~U0LQ80I z+<3EzbErV~Z^579PMp3{hR?BW5fJq|@K~7`aSudxV(z&o;sB{DhbCL6RshUDfxG6# z=h%1Pp-W5%%!~a{Ax_X6%}`0a1mgu=ow{UQWU`U&lrO-;}BLd)m7Gm_WZ(|aup_pJ2vRK(jAwWs0KN54Ykm1j!dHd2?O zID;e|B*8IaMdVXYoapCUUR~7QZ&BHibZ4}_*K*fK-TIVeuZ*Tcv7e-(p;hzj(Cu^V z(3)9&q208{yi~IT|1?4MG_y;z+Mz9(_R!Wj>Cno?jOB%Z^Nu;YEer{w{)(7Qk5GVl z-GCILlomd{{=0*!aEsZ%j7F9(UbxaNsR`Ss+7saEu&~HRblh!XR={ZX? z?P=@~ab#?V?IV~Rv6OaLcXa{)q^nyS5yW=f)$|mJJ2+C^@&PC36^eSEbBq zdSG6Gw=!9ckoPoeQb+~8D6hc)1gtYo!fRt=S{*0BhNi{@T zVxrWj=4@?e#YqvoC^>vsmgj30I`1`jVWODcjQ1~Lt?(f(@0ppG{B`vM z`Dcch{SP6=z=>Y^Cb?Fq@F{$16N@c(|KjLHx2aFzX7c2x_&3rD?I~THcky{$Wv`Bf zqF+H=fQlse*@jIRrwXD4mC7tqu=K!s21~LcF$m6^f1xA1+)Nbr&a>CdALnx!HyGmp zeHqsboN|fR9(|Kh(^>G*?6L?9>@kJLr{1VAv7nRqYaE9h{)5c03AZ)&2e7h(ALLpl z-9vX8dmMW_o-q8lJPT=O)bZ@2g5xx=VHadCO&Ar(P|WOy9z6W`=vN*Cls0ri{=FdN z{5W(+bN>vC@@sqM_*3HZfnK|g9&bUqB4hR2E0R%)hS?4xMrl;$NWd9H+#*K&Vhfz- zNSX*M5$Oo?t#pOuA-z=ao6M#vQW1m#xGlo;LwZE# zAj4P0J!CPEFhybS59}?55Wmy%tD;>`zRTkjD?Q?RxtEu{JCh?GyPH8Uh1P*2 z6DhF#3WS=BWS0p+#4h6vkYA|rNRgE;vj91W$T5T%`nX65QU_FVAO%@=31UeGp(k$n zU9pN(^h8H8>Q*cS9Q;~VXXmA-^e{c5kR@PMXw8F!al5oWW286GP>n&rF36XRZJ|6Q z_5*B_EjP56ZF|%WZHl>}6-)s_N1NSgcR$$XPD#xjwZ+a_9I;LbzVhspdDT|{qXF9E_ zwJ+4-hP2lHPg$%)`gxWFX(!x zNgj_5h1zwfzw)?MfX7jkU_rF?j8zn4&S6OiCBh0ZWl6^FUw^!jU#_PsUx++?ZC`bK z9cc^PXk*L|t$`EnWLwqb zhn6(^q2+9eW`9O+i$5cyGvOlkVcPPU4%_Sz(=^LR3e2_qX^3siEEu)yGX$LrJKt3X}Kp1z6R6rm!`w=zUn zNiv3CWcdgiB^JtVAYVw3aQRl8z~|cXi+WAJlq9t{wqtSQs85Ku=Aln{8&k@|4_rdf zDo-u`bxDS8af4etu!-6WB$uIG0zJ%rYGnUFH++!vAl!6_4gEG-DBlX@^+wn@l?q%b z;X6-ELE=v~6D-6`wxhaQ#0Yb}Tbf#o5&z=flr;6*Yfd)0MX|nuc+4)062y?9$0CRw zvunz-T!MB1>Kf+>`)CQf23a}V6WxY)Hn)#v-pgvw+#rwQhA{ZeK0v zHq%cw_lH*Cbp9kxd?PI(hu1{GJr7Gaa!01=Y<;4=zqV(tR|7^el1REDzL2Gi*r_$g z zpqx4xh?&r&A{#P|rz)7GEy=W=DYN{qU7_bU5 zR$0s?=n!fUdf%1wzU7Gp>B{7FsK4g*O^G9iB-{FDBt;Gpe!R3Ca`8Dp@#1LS=nu-} z#gy}|NSc=5P|%?~CfGr1kYk5}?iYOyZj(kJuqa*5q_YTA3TCuT*i`aj_l(;TcRP_f*jdD zaAa$AID?L*>n>U{#5xvcUX@`?#7=k$(qFZR)Nx?a4^rlw|t_}%q>p6XmQ92gnHf-RGJ9~!t#p30k`|2cg1qR$dX<(BAJWKW<%oX4rk|!mM)NA& zgNuYyWnt^i{KfB#R$Fw`$WdncV9+sejcDOmp<%_v%1=dD^NmtUUP&@mkU~c7X)5TA zqIYaAM26jvY+<^xxB-8NdGJwja*o4r%i4hkKOAZ8TS32nxbZv-JyirWe&T-V9D^2< zrlBD!(IWP7Xi`+VPNs3_GKu&Drxn1L7K&P@L_%3{=Y+*X2>z442WhA*+D8ZNlqRC5 zH^4WH6zR&$bu}3#K*>2??eX@$`s2-~LmfePKeka_I5Gy1?!r%@&?>2gaX-V)8b)ut z>}HaXM6bWTqP`I!^EzV5Qwq7oAFIE6s^Pmiff3t#191cDL?$ zdq2yN|DV100FWb1>$|H*X+lrVu|U#vh3=l9oK|fxe1J(G!5EAU#^%6h6OLfu_y8L) z21&bXOWIwKRx7Nqf>8p6m90oNwF=XvlQdo0pe||ewoB6ObU2nhEf2SkYf2%z_)_+yLTu0^@ zflgkBnZBhSPux)ldT*#3`$yDGK_3imj%)vEM@5u#h^-SV`49WK)xQ4jSv>XtsNj*D)obgp`Su|s)X zrGwQC0e!JPhfQb$N5}S)O+RtrPEi~jg85Sq%hxX1lmlHu{dW8L{*jKM{_B)?ImSpb-=j8BgJmFA#%9NBFXnM zVwbo@N!~}2_u;1zEaNwpnl|>rwPk1D{G9gA zTNhPz)3v3yEw%OXnmZOwO(|fuYqP1?O%>xmFH$y`!nAm}@AgG&&a0Pl2;jSucdXj8 znDkIoTyM?A{jPM}?aZ2f2TX|iyy>@*(usy}TLXD>695w3SIg2yGhLw~_hZnYf?5%K zh+ie@$*W>R64t!(T95m@?tpO08q1Qi$i`|ihhC(p$S=w0SoW*nD9d3I=Aoj4MNWMQ z7L$EIm89m|rC1}7ILnwO*2YUg(n5&_>jYW~TvFLk0y+t-DJSF&Y?0^!GYGI){#oU# z@~r9zw;8S6v}-VniVu!k%3hu&3RAAzaQ^sXfzyRS8_^iH2PZA~b2hmT%YU8dKG@<{ z(0IbwW6l=aw+Pd9yd$^afh^YEI(X(NegVLYHNe+PO=N3vT+nz5*kU*efW{C$Fyk;- zbDBr019Va`?+6xE2_ugYXdiCzF5H;)&k*-3jA-F5fP}W`)!7w~n?~&DGHcnkKpUU|i9$~KNgpn9AcJY8dlcgdZ z=e_hA{Wx$zxYLEfu>yAHUAz2T08^vRf{jt( zljR$}nr~(xgNymc2sVc08!Zahm+|ZBCRm^3NXNMau6m~Dw$*Sc=*HWk@7>p4Ej{~2 zz$K-OcC{h{K8{*(Eyc92ypoFDQ0sK~ruLAW=d4?a#Lyyb)c?69Ss-DqYp+UNx(@^vi{-ZqqRK5#8%D%8afIhy`>uIaC;zdWW>0K~@!k z8NkDUk1Th)ED)Ziv{L*IQvKEBGy@Jq{0ct7)Nv$GM^C8exbK z+-@RC`yG&o!-j(wg>}$Sk#lfZ>dF}V=w#F0Zjf@x-$Xa9H?61HRbsjkz{Ab;?Al@u zv1gCrPw0Y&Z9ag-IpL%oEAPH#x24yg=_I zC^ZGzOtu?@L#AwmU#4i{t)o&R34|r}N0f#0Xt(gZoF3i=<(b?Req2iQI;hrkukJ!9 zH}VW|tD0vU=GnTjNv9UvY~Xos@VuCgc+_Ez(kEO}efEu{C3kKZ68|oFGE_j6%~?Y> zTWD{X46h{vS=Bx1CMn?G!jk?9%Pbx$vVUSZdORefayg{t-pyJNX5`+@LPjW?(x&`m zW5x^QRPm9jp*S=e0+ux$5I2S! zaE(DRunTv!`5TwfcwTa#Q6o*;Lmf@rBm!s%!8 z7>JuBibE%F^N1{qy59j0g}YH3BRFR;QQfMz)r^_}l|Un-y9OSM7}I)@`tnra9np%r z4TH%$ukN@6OVAw9PpvuBr|p@w!)k7|qi$P)43O);p;n%Kv(VfVX4^wIODEO5jGo?< zUM}p*y3}o}omqOPO~!w-jCx_=@vDXD7Y;A_>LmdoqgHn=$>e3w4aHHIFcwkq$y8#z z(|a%;SCW>rByAh?z~(?;pga&3nx7e(>UQXe`L`gU zH#+I2*IALL^>1=Xpm6z)l=zdSl2d&#(B(-#fUi^>f;7qJ1Np&8Z<^{6Zg+~WX|(n| zSf+=a8+K`_^y?H~Jf4iQ59%uwqq!&fd~m<|xOaY7>y6zv4WX=A)*(0!wdP#Vk7G{x z&`N~!V2zlDQ(siGsfF-GDa~pPk~gdYgc>BO_^oP8k&StCxIPnaWH};j1QG^rEuyrH5&W{)fdaDBe|wBg{GsjfFX)O+d{j8L4X3csednra*S zBpILDDoa$WEHcGI$crp3d>XPVNS842o9ks47mO+7Mh6UdPprB)j~XZ=S$S0PJLNYi zcjQ>Qm~|f)jX{?varKnH)m7Udc8Hj8V~5U^DAy1(>gCNx?`Qx z)ODBM!L@z51WSFi|5OuGq{A#MAs?pi6j(ZweLkE|{P3q5JJ}|$PjEa#vI)6pS=+u= zJ`)>fQk`lYdJXj%vsWdLJFX~$?o@_uJC%k9mn~8kdJ}_eyg2rNtBzs^V~&A9 zg1McOQ5)K)n4;$OEl|?R?CKiaTWW&kC~21BDYwXN8S1&-f%%%)qe=fgO5E6i`vrM% zu>G`9pet&oC}sRLp*#`Jt|>6#Yv8dcg{f0UQ&wv*Usv+1{{ zlkUp|F>%FQ1PSznC*mz)!9w#UGE+rhz%C*zAxFuhLgD>zYNCsgSEwSMN?r*ocle4m zc@%JL*TxZTDZ~mzS(giC;d+)pX&|yGg?xMiFDwn%7~tX{C0b%>*d{KMhHj<-LlHHO zzEH#fQ#`)BR)ie7r!6pL3uPwiH>3bGIFJ4}g=QgSO1Trd;E&iRrNfM(w0!V0b%Q-> z#uTqcqewtcf;o}w>XC1|J(HA@_%11XI(p^XZq3Ni9>h;6d)xZt+ioU$iqdJ$NvY#f z+pGnmW!1AWrbP@BEp_ZGxICr9`gw^e=)R8GH?5!5IOSqkweZr<#?}?;z;)K+QdPLX z%ETHpyI3c~Rc$7=v2fb6F|4EAe(|CWTAk(;>+3XJH)2+Ct3-2&XWLS^=sEIKxWyZ6 z(rigKQQRUnt1=hcQ8;Z|%&*kk;x$`AdgZ+0)@*d7x!6GAygewmd4}Ruy9jv$sgw7}9N0PDJEwBv>PQLR*<+rs_8sBvC#W1i;j z*Gh|Ra)zWCXvf2|xDR-z#f{^dyG_G4H#{QIce8LDE?!j1laa~(-X>1ePZO+HJX)st z5uHgKUP%=1tCC@@xRr@r;>C(v<=Wrz%7r84K~j`Z;Wg!%q!58ZJuMPtp?&dK?cxb$99u>iX0|G+U|e zVd(8!7J9y<)sjOQnoW=yA#T@Z<1k64i!zj0CX*zF;wof_`H$!TMr9m#Ml||(u^1{Y z9W111*0P4W$*iPaA|6MEx(jv;t_(dsDpS(Fp*=kWKf%AIcBThEd=#cA6qA zzknl-Jn6d7Cx)O{e4PUndN7mXmDL$A<^!V>VHFoX0y@QJh-w%XhF0-~`Jk1CVNQr= zgO3@E`^_1AK`$iyR%BIc$K@d5qtWbky8`s6>W0*?x_=GPow;Q=0$lDVy+rNVP;ouB z|E8)}JVKYcWA)wJufZCo7TiFA7rTz~2W*PaoP!3)M@)g4y#pHPH4esQn~o0E zj4g55i54|fY@#73+6lr4Q51@hR58&nrfY7@blp65y6!Gc*RA8G>&u1ddSt5UN`S;P z=4tU1nXY&{%XGz8ZOn9?i(eem6;uS7uDI37bOpL0oUVI}aJphUM8VWFh;P5dA0S|T z5w8yvT~-6hQg>p-X4=BjSuYf3ZY?f+m_(SowP_QPP^NEnumsmyMp9-;1GAS5T;c4k zCcs%{Z&fB4&fZEm(dKaWUJCl~22I7?mLO#gw`5asRC23sCt*vM-6Uvd82p4g*8YTr zJSpZ7c^tKMkl=dYt+6g==A(OBN96ic{~nfCX8ie0>9qv?v@)IVAX%l1n~Z(zR_Rp2 z!zh@uGF^;*(mP4QZAB9^ihLM5{s!d0+;LrhbQng?pV(7^>_C0B-(U)k?jB6*?2_*+{FTA7MZpRz9wREj zajseo^a3|#y~3j&T!MZcY5!85X!D9Yc2{QAjjr74>m3)?-0Z|c*m-%?uzEHJqQTZ{ zOYked)~{9!;UN(vjR8OlIB%c^z!?rwz%Muiv32ky_|SLaK8q6A@Xi=rhDRI^qsln} z!;#VLQj-xUIsCjfoOHQXAYAaF6^{h84Fsbzy0hjmqoo>UI)+_bR+4YMI&fKXDWtlw zZK5b{%%+B0EbEwrI-8@}9aX-FS- zBOC{qUak;CmLyz5aQF8cnI^cROM-GJ!!Qar+}Hu>xDqGaApseIS+$z5tk^h9EC7%v zHQbe7gF`9KUFyKK#fTD27%-crF=6Q2Dd!9+F5$uFm^Q>&-E8<93?E+HDS`5&jhEpN znCx5GXW9r4oO(30dN~6omUm7M4$&7)FaaFL&CaQzU5I?nl2gwi-=lD^CK0t8T2ThIQtOX~7=N3MKz!nKX!-1>Aun~Ye zkz&v2P8S$!>NC2%50Z=6ivX=g3~P&_Zqpt9)Q!473&sMVl=ZMlJ9YPI&X{B1O?FEE z6pPIv{nO|n&h+^N==1^@)TdVDK#vivh+2`vPYuS#&q7JCUM1Je(yNg}#1WEmcuQS>uU_WS>-6Phd9hyWak6Y38W_$ zdU6Q?GXy*nOb{A7iQSL6hv1gLgyK1Lpl$FlJ&hVs9!aNd#qU;LagG51%})G4aU#VZ zkzi1N7m=MhUWxbx9+XtKytpo-+YZ1X zkH0~0No!Vwr{%lO`Tu!MCV(XX~8SPmOe3VPLF6x<>Uzdq}T65ci zSO7qt7HBv&_OM#_bYyxOvq`_B2T!e}(~(a&jXgk5VI&U{UFk$~HjY4T!vDqbl{B5^ zgt{J+L>__>iHqlt`YaxbX$Cq7N7%l%7-(JyKzrOv# zqQPBo@v`#4Tw)&Jz}^(MQIL4`?8n-Tzbr(Dv*kl*4#Y(KhlPv~NF-`WQ{3s`+@RVJ z48y@~hfpiOEnXT&lJgFTgO_1%HE99ET8CR}+VG!+Zmu_9M{Ig&iL1_8q8?vlsVDnz zNJUGEizd-3v<>^!n}6G6s@x3LJQl((zT$pppU40!(DMCUr? z^a)Rma@j-_!I2tj#*5Iu5U#L)Q4dM?x&%FeS;6bFo7b(RifbvMSccO?z1;L$h!3WT zP`NlKOs9?NToV?@+i&75Yi}_b;l>_1E@FBcOm(YykzU?r2CNka7t_x+{fuXSfCnQaz;){IN{&pa}l*5<0O3c>{i#Xf-NK$ z7j6Ykuka(RVD}E7ed0I51G(@3KtP3Gn|wb8yuwq+jmDh+!2a;3CUV~6bEreu`@C2B zC;nB#27NXEJ@`iKQ76-^9%h|?R=2v~JG+1yL4nkf1h6&P-V3-#EYRRop4FheKCsUH~g1JaMf@f zFuB#4lvS0Q&x%bn`M^*dji)h;Hch-L(Ibj$qsWekoZ^R0a&BZsLeR2=k+E)^2F)O^ zkA7Mu%&4#Na4ZKsj9)$d?NA|L^G*{6`AC_S22NABt{TLBxb*wB5q-R#Y`oZ zS?(#O+Oj+nX;@g}3pfrmq zUYASlyk4DMgekN(+vC1$)E7ePCv7DTOc7`;OAxLw@AkQnrA)9#1Rva6UB%QJI}b`MIaGS8j3)# z=NtMegd!Z!AwJ(&3W3U{Ot8%!@rBas{#D$4%pLhjw#tbT(nEY6P_;5*T?wD5Dk0cI z(I6f*8N5lPpyASN55mWdE!jS%?1HMyvb#ogX6Z8+VisF@y)M@~{Jc?rJ_&kz)1}Wn z3d-iu+TaIUwTj1gt90{v3E@Ooy8_R)^NyG+( zH~JSeGjMwZ*d!#orhu+Xh`K@Xh{saP=^4j!0N#`w$NY+R7(~IPh1OVPzVAt_64kY0YG>1;E;go!KX0% ztimmS`Aq=Ji0B8{VH$vC<4Hix*|!N)h+armf8O$w>Q<;E7<*6sPMCkdfGnTlZBA$IiB%aBW<_2*Rm5xy9%&^*5Fg z(OUq6TY!%otHd?&Ax;jn*hbR{6u9zc@DaQv&^$ogLDkS#F(EgfZLQ+jc8dND35OYqBC!l9*DRF@IB5x*#FyUAscAxXku zaZ9|EM5y6+LZUPvaSqOrFw6mOM`Rp%E_smBJb(+7@FDWB&|nx`JRV>aM0S8Eg(OG> zQF%EM4ExzDR>HndFR-n% z-p58`m|~>roM5)e0NRKts|>VI>H4Sp?Y%*-2y{-c$bNCLjDRV@76O^e>LtlNqH)$^S)wpGz%?>SrO}w3 zGPJ`gg8xi4bYOqt?eI7Q<#6UaVL%6C}>dxSM(N$ zXGAX{jOGwVa|ok3gi#RBM5M!oO|&S!2%@1dioHsNQ8X$w62)c!P%EymC{e}RR-{n` zNdQK0g%xR3JSzx+C`hA*Ak@skhD;{3DZdXIO=t~@m+j{!NPB|&8Qcf_%;@5XCk`1R zs+xkNB}k7^s6%ij8#U6e8Y)uD-W9Bac5! zKUUBnJ+88G-1(~dsF)EI%fy0r2puH5qI^FSm+wHnUr+Lt=WB(vqxb57J&+`rBrdiF zVtAnq=&xkp{9}LajiURNN5RkBKT~Q|AyS0ZdcOZgx8IaF2~)n{93;vcnYGt3as-LZY{6W$g8!9OZilB z?++ooBC86EI-O4$FzlO`PW(dvna;&e;+$%krcKTwrI9lXOdY#Y(^wfMWc=PFqwf)NRSXJcR|4x!$uWq0=Dtp zwadeZKxC+Bh^I&J5px|EPaHA*%8W)>wIshl(yqb8PaeT)_5qV$gPe`irDOuFO^XjN zHg9b%5a1bNr17rQ-R*i)P9sNWBYW24Jt=OyI1ZQSxD9Kc5~pE&A&I}}wcGkS@ZTjc z-tOq>0+Ov05f5iSAG{nqgRzI<^Seo(sv#%Or!!UKk2|*Bq|s0r;Jk~6vwZw#L+yfS z7@Q4)r;bxP4v0W_j3Y4jgldWP{Ap$$l@!c)YBp5~qv9Tn=EKQ)2 zmi6F1s2?X$WxA(4FU{yOngC#@U45Wcao-`F{De`a4QuWR1GnkJnghsc=txcGR2xqm z&@#(#ojs;)(#V+`HRfqviRSN>(WzNGHRlEG2>ptW#%|5ptl2N?s8lp}w!TxoaN3Uf zTc~ON7M$vH+Ahw}cIpfc&3;}xqJh;}qdVMiKyzOR1idpB!6_gedzXm!Tr5M9z&;#ygBT9yNw2(@0h~m) zlWYPGEt?=2Vj`MJ;9ZCypKKv#Mc%}F9f%~{T;a7PCcIg!Rq-}7)R2DQoG>QiEh$!- zaXmQs#^iZD9(qkR_FeoK{n>HMPo_l zhP@Y*ldJ&{G6b1{;lnd9Vnl?I!Gx^wDS~L1v}F42mVB?rxR)`{h!01*`0*yJ&U~B* z#v}=td#zSHRa>(C4lL^H2EM?02~L$Ph3gB(dQ8Wd*KwTp(aw`H?{4{emf&c{;}eaOfa zv*I6$Ty2J2y`ZbiGW9v#QcHAF*%o$fWfzeQFA=R`A2r(YH#X5pt@+;ee2?9hPde?m zH+1CVk}`KhEiNEadYL}hTQ#`8ypoEI|LX>e*2MD{OdMQn;kl5$yU-rvZR>Y2*f}bP ziiaHzyBzikhfTF`6x1BKSjMXy^@~TX&ijX*!eKBXqa9dJbku0~7IN{j zmWL7{3>bZc?IYnKHA?KYN0MF-x(W(Z+^fnY&`=vUtZJl58FJWKqzGKUl-v z;h>!QvE(lI-o2tvP}Q=n#_FX)Y4m(xdqO#6(ePtZfD<`8`ioZjl_J3!biJB9;emzzV4f4 zpl=*mfa}x}=j43ywf3PUBZo_3q~c=hC9DEdr!5qUEAd4hKt>*8L!%!!Qs zi`{;me*|-ZjX(4KURq$Z0mruLvWbqiV?B#!y5LCnw+dD^2zYY zh96?*wA#X7UL&xFKVp1}9{_6!rX?CM{2LRo?NKj$2oDkfUc&w!`ZN#Ssg47mdf?p( zJB~Tz4x3LBqHMPXE`PUL5hGwMpE`-LSpTflT~ z3|12Rw8pDVIV1?Xx``+dQh@L74g|o^v<`M(B6CIFum)l!f)hrZX*U^RCC%XJZbDrx zfVk$xh%&Uv8{?lKx3g19kkzSf$+l~q>9(5y0qC~KCUhd!Ogo(JCKIFXafx7Q9FDc{ zeUx0)6vw(9DF$N1l<4l>7}53Kfo`uAWZRhCYWO>21Uc&aV`Mh6ws(_fL$^1^zz@*f zO+=W2;1uXDb^Bnx2rwfQfC21^vdLc+U1u%6XT}qbG=Uc&=R*Lzuay}uOhN%4a03M9Y93TRuWgz1!Q<6qLrj4 zgo_E3tYDWBEi7@HAo>!^DUre?4go8fkgpors*DD&HOudPOF~KDRh{s2NU$qS@|h4} zc$EF1wT9b-A*oL}br1ZJNsAN>92Crk@gGvxf!!*{i8fY=?ePP4WG zd~o-*okS?pxFCNMKzuZ1+Q(9aUgtiIC$oQPm)S z65Rz-nOg}AkWQd9vAtv(%4=j9BKHs>zU01=TtwdZ@4|tga2kQ~gwGQ{tbr>_l4dd? zfwe)PJ-tB;BYoX$KB`;K zB^_c)OEcZpUO~e?9OE|90t>h;?eY2Qi=9(8@x(TrB6AGQ(QY~>83n)|Fv&DzJ#V;8 zdEMOt=8_~UBedBerLjaQo*)Q~#+Fe@STYb4f-x*G3Xn;M)MUVn3Kl`QC(tVije|gd zNnioCByfKuA1e)G9!t~U2oPv@46N2PnXyRNta*Egn>DP>MjNTbO2{=vUl2amPBge- zb>vB@Nzx7hh$lDDR+7SP>#@6r z`n-<(Vy7j&Y#0o%PxT6fkF_r7VU5tNUA;j3l2t574p#*r7O;>2K3Or?<1i^JGf5%E z)wu)*z#T|HpRMY_xL|J9=FBpaWKRwV@C|eBEFl_iD^8cbf;7k{+y|0PP;hhMKh0 z%~Up$`c!?9jV%dJJ-`d^2Y2Tvi-5^u!VH2kk-vi$qvd4A38JPCZbFq=%_7PAFAYl8 za%o>d_Q}xNfc88?$2a-Ze`_K!u{aZ;a_o?mfY-I8B@Q_ZEEcG6H-WP!hP@zCWUPL4NYqy}hY zXxPn$ApvdBN5~iJL+9Ogh`$UAG8ek!JF&@E$haWk@g^`Q8J>cz4_POVU7oCV=X-9I z=VA_t@XB)iHzj}FL9Hya)IP3xJ2m^n3j3sHZIAgUR$22jcOz--fWRMO4!L87AB4$D&MWlE@Bm10;0<@d)~^Eyzh{1AJl-mkGXSz(V;tc zfU1+$TJ=_)U;SLN;>wb;+_K{<53icLdcSe!;#_?We6GGjx61j7@&VIjj&7ec59(l| z#`mqByZTUnPCMS~ks~Ee&c_OH%sw09;p^uWq-e-AwUq&pfOHJ2v6l8nh@Vk8l$ zUaGf%0CSW~LrjLlIuJkhTtI(H}g>z^jUFCjohm3g!85!NZRCD1IHS>JOG>@mX26Vd_Jewn$ z4=@n}9JwXt&(m9hxnZjDa$woCY2>w>MzZVah<6Wf(~V?TI6lQk1(u04h9AV&!yjlm zd&?&V(LMB{e-MJK3abw(-qLsX24Yr7i+3!&BZ)x|YKK;Uyc82sJg}1WJSMdG&?>7m zq{W9;dF+A^AJ?oymyPm}4pV2w!j^XnA!Z98Bi2kPaakI68?8c_&|>Z?M{J~Y2y(au z^+imFD$5rARgvvxmuwt@;+JO%TPsI<*m!J-9onI-Jq;N zw-9blBQGm2B$ONa4Y{%lq+4EE<76S+1JtuIC>q3j2X)?`RIzh)_E!YmKAB>n;ak`M z$!a^z2I<=<&mmY+LdL=$i->w0ryDm!x<3ZDH0m}Q<`+x7pSYlcYwc;`U zTC;!)orGjg_Gx*Ho5?R1{zV^k+efs?L=4i_v!8)etR70E*i90Fq2bvp|m_XPltK03?LC0;2F4G~q2WCRu7x ztBLHU1Mn;$JT|a}v@ZxeaFun?da^aU4SFMVa^mgY!}fcE*hB|1ibR>$B@x0$a0>w+ zSS`t82YRMR`%V-Usbq#L&yg_z0Lao@&(+d&g5-CLy@A!)gg3Ct4dULwN_Rc=74A0b z%hCCg>EUhDExR0aOU{SO!TfjaFu%rl{pLh{=hWNu^c0BBhu_FQWtCkqZw&a_ znKG?yskpT%m9W;OlGd}!gtK<;XkRHYT4duITi>p`OU+p>I9;&IcKha}LMR6VTQbI4P}`nFTA(Dw`59CEmD!|p8P^-Rp0rAO1i-A?!l4{ZZV+HlVULAFQX#ADdcS42G4thu_?Oq+tz@e*ZNzCa)JJJGzUMKj+`EI9!Cum{bw4-?-Q8S>g z8XUjwv@yIIWDd15!0MPsG-iVou!R&fIw=`@LtRT_K6V?e3)&SX)QH?m#Jlc>8Wv5HXC@FeO!jX4nW)FT=uNez2o%&C&gPHGP7K5WhG zh|*dpAgIt@VMWAjQrO2(jB*Is&tZIrWf?=IG97DT7nizKm>01^1l*Zxv40hAY^aB^ zh5=5>aEhkm>VD+dAdV#O!9%LE^{U*$tfnGQMltH?@(u{dCAzwft73LUSD!`3#GcD8 zo+OGfcb4A8YebQIsG-EiG^uy;EQr|t9K8dbl?YCA^mg7Qn(IbW)y@M|WL62ObfVc+ zRy{{5r3_-#6f_!w_9}};gK$#nK)Nz~EHxsmB8aZ!)8^%8=?&5y6= zgF>!Z3U0>BFpPM8x4Afu>ZLbn?0Py=#*GY+G2^C&p&AYx86YxnWPpqxI9AxdGCIP6 zBlimj4mXstf*u(iH(p`9Fz6U)Sp7K?r6Qvy+=F^p==5hVqN8)>k;*uq7*WwSo+2~) zR?R!JM0%n$zrz`XM_L1u zIcB%#H1@ge=};@!0aX#YfQlL7M*HF-A$q}90H9mg-+V!AqBu9OsM6RNwG6in<)<;+ z&b=B*Y}1ay2>s-62Uk%#om>SzEYIgO=9gm@ig}Hh6<(#@9IWu7+^R9X(nI&}Hf1TH zO8J$KCA>}Ur!ZzXkv0+_&h}hlq>J%WmFe?&-|F0Ad@-1?nI%5&4~pYd>(&wSnKO=!AO}h{VYe-t3@2QrqK8!Y>?)DfK8VjfzWl5F&6&P8#ihe<2MtQ}RtyzteATR)c zyZ9)e>~q=!c|@|wX#s!*;< z9Ul-TJ5;F*QUi&i=ScC%*u^ox#1DcLKk6|dF>x8^QD_oMM#v0AX*Tw?kSJ}#xE~Uw zO}P3t7)KeA8Z;2;R@ zcpv#FSkRsU|DQIzinvoTNRq+~39K^Ye#%KgD^foNq<#uW{gfm16S>35QGAme#rIP` z&6x!hu&;`ThgxlVSWS2m63ehJ^wBI4!&S|vdCVpa$?gBgxC&W}$ zx1)3N7!B@hLwymu3CEv>LsQr5_*>XrJjfB<>oUrWE-apDL8 znWPT0+D&m0>p;sx8tM*u^Pr*9pK}D}+}KAim^P``pELYTl61zjo@Q5x>5^+=mnlix zx0plh*+ZW_`d`hgj<}+GqdU{S%+w^itfqgG3o<5Go}0o@L{Qem=uHC#ArWPaA( zvn9=)>Dmux*CK=9h6%cTal!=&VRiAtD9!Y-UW_n@j>;6XRi;x3vw9=WNxBdAzq^Mk z#rOzjK1!gXUb%gyqd%M-E%O|6`uy8?S6C2YyL9;qCtGZS@@||C4Be7 zMgp~>`{r}vBA;2{@5aTuEWf~>)2){07g%G8EKbX~e3xYw9u%kVV4*eG4S|Q5g5&3I zgD^<7R~Fo%@5z=k!*qQZnXXZyJFOCSvIoJAuM??0^$edQseW~CYLU8+&m1Gi^1RJ} z{bT)h_V!Pr`Gx&G6YEf0a$qf{L>&CCVF|{wXCeqFhQepi;u#x)oBIm3+$}k4kA) znJSrUok~+BA#OF_T+cq(=!I%sz*j8{wOX6f)S7H6rq-l%wK~TZAqG~R35TkC^`>yE zjeNrrH<-*Dqls_RVHZ&e&3u~qJAtgyU-2xz7Y7c7!Xtf)C&E+;Zf<{A#BwyLPx8 zKR!i8=!&qnCVh$bePFV_kp1ub=8tuQsk$QUsE4%w#9a-u&~MNI%#TW3e$|RJaSi1` z4?<|Kr=HN?qG#qBB6z+mZZy8SRrj|;c-9&A7Ip^M+YDANYc3rc{yUx`?cyVP=&|1N zu}=P|bxxs82MlXAR1E#rdn$^3zGJ3m!m;#ZrcFs4Lx$lIW_>?olIP zkU+eQMh@ecTdUWlF;S_gY3@h$evQd{Zt>3DKMJM zjJrpPNorGi`8#i2RM(|$TkV7r-)TcGBK>v>FA)qZcsbxVO$(CMwUU6j?)dhC&DhghTv0J2HkG?38dr z3X!FxM4|~x33|uI6uN>UR1ql5hBYfS-@?jc7fWZlWq5gj!MJdnF-2$LhdMLi@7?=( zgs$*03Qt#j)_adG;?%wOD!wJc6}DsA08^m6ZmZ;nrfCpiq%E2<1b~2|?n;tO zpkdnvJ>nb9nkQT{qjA1wVF22U0~S6T2F!S z9u|IB#GO{zN?0vn;fF=i!5~tZ?g=+~JR-m=)4c?4QS^lyeJ&DhWx5|XB?>(w>1!#^ z5t$cOEUbvNg&NkuV(sbB#hKGA7}@H=(M=K%FPB;`;Z9hn%_bH<+_g)`H7KkRI2$e0 z21Gq6=N}0LVyVqDY;+h>JAtrVsNrVklohIF1Sl43JWH`!j<|VR1~Xi;ZoLxL2-@`u zwJ4^%1K~c#L17nJ)KMtQ1;q8gRH$V1!k+59<~|?psxho*3KgQ&3pLDwPT}VnEf>Or zWP-gLR_cR(xnq4MEE;lsveg)FG-i5bqbX1FV~TWGG-s2t)e> zwI0K0KD>Viimd7UYn#=a7X1}#RBK?Um{rwQQFEZtvQ=X5Jr$@9wL@&1IL@dzx7eyU zRk15%4)~3YZ+tE$nwr`nG&NDO!>Y%F)vmfb^#yf(Y9Z7h)jiyvOTJ~Hgh)zM?nqTO zL8yP+uFb~rc_1z~ZIWKsbj7&_2Y#0)!Go1S8?QBejJqyOo(lX5R&l5io*SFYO6ny{ zY?LOu3{l;9m~>I-;FARi2NKn8gVh;mD$q^#?$mro-H;kq_piZ{nOinOkaYjM^wHT+tu~#JA?M)v zxCt+dX4pkl>?48>p^ChU@{)lf!-LTxBg0bL5K3{o^3--2FQbFw(9GcY=njrfCb__(R1a5kq_t7XLRpMcR3r_%M%G>m-2 zp2C-6vFLVAyt&}E+(!N#pCK0V#m#?rVy?yJWVmb$0MQeWspecx|&28*rs zz(5KYwijLxE|{C~Tn4u$J^}E)xP|sfe%FFOl;^OpWb$05ASe|+F&>*wdLggDCq3V8 z$jrAI((;PaYmISdl|MrB5WR~%eZH@*g8<)si%^dR!yQA5?u76I%~w{89426AaLve8 z@d{6QX$f{tC7t?gD(Ti2Wr0Q1L>B1vDUk&dgcge|5J!r>FAKC_)f8C($p>MeC7%>w zpf%TvFwmUq6KMd~RJ@WfXk$La^o~d%*d*%6e2dVSHM5uzDk7^aFz;GDa^dA(1h9{FXpu zjD+733Kcy&mws=;85Kl z@{%-y3SJCaFN6(2mQg{BvsD41VIM*W@eHm?@Ko`}I}9{dNW~xZZ|IYOyhqd>?2R;2o}f@_>|N2>><|Aq9XnXbafM;B*nWNn(6DWmcC|G z(${G;B6R`kg_;~JeszZ6hN^xXe)1X`Cqa=Br4w4-?R2)pCty}lkLdnx2Ekr|lX6u2 zJ&&+6{MY)?pXCKg_EDJYVUIQCHE)-pp4K1lyExs&m^(w;zdC4p(c_5ujT3Ld;Rr5f z)ZvI#9OXIQVXWje;u8k{ATd%9hR|#;9WJ&D6@no=0Se+5Os6wz?uc6*ach_9qw{u- z5lWpg{NwR9kVUcvW-Y@h4~R5pXGPis0@8w4bnDR~RIwW%PfR%i7h?ggL&z_|VR`VH z+1+5m$^lPDY$sY;r-^zwoTur7?QCHsb559qi5k{ilL6@MH;E;%x8SvxGxo5AMNDsl zsctndLfy8R0fg@0V)ghULacF)E5olRbnvMFp8@YoLcQS2h!|6ApWI(@f=pFBio1tz zdhgzJtM1-@4YNgR!3_*yvFq5ya3~0)y|9o8;Bh>(DAu06max$TdX0neCZjtdwkd?M6CwV! zdN}C0p>9|*+!-vhThlAumNlTBt`X}BFqI}_S^%#R4YAw8@4?}TaN=Q?0@ji;qr)Cj z=5(f^hv7;vQJq>mKMbpu(8w$l;uHOyeORV!4P_v z#|W`^@pZ*7gZ)*Rq*$Y!YL3&zz#t@KusHR36Ilx2Eh4!A_l3drDUg$7Ct{Kfo=`I$ zL{hM4OhMzY1r{}CCOMhVuk!HX=M45Z++~yDpEBjgX2q{=WgN>{TUW`5b9S#3gSB&T zxtJTBqf5hQJQ4KazRNoe;VFAu!rmWc8=frc8^&Bc1*w?}WfhcU%uniRL#4UZ6BI&I zfnq?FD$)_*)zF}O(ovPD+7aG6FE6^)N>YJ_!BxX`nWqo~QdSkPOieoiWD1%2j0vXh1q|ng}6<>b6G%rEc;ivWN>+b}8jhBNJb(f#28A??R zrsh{7F@VUv5SZk5uVRm@NQ@vbm(wqZ$mMZ-wsdS}VnybjVpcB86Gj>q*7!o;nCZEi zbZCOBPRGTSy)v7C@H^#0J>{AB)g71nEApvseCwm>6<3U^V5yyFkT1e)TMJzL%SOE* z{9c`M7ET5g)gdy=oVa>~4hW-=d41vlk3-UrvXIS#Q$48@{>)k@;QFQag_W9_rhk7; zPrL+{S3H^bpiO%Y&DwhW&QYd`@X%S19guGk9WYXg0;Wz&F|N{S95U{JNlnbbt>*zZOs|qeCG|iYkf_6H$j7X6LBeg+T#2o00x$`(+BUX4^HIg<77d840RtEB2cB0?%~bdj*4MH z!Vz;}sNypVtpf|KE;bG>RM#(b30o}bwzd(=_)NF`G^v0}l8(9s`CtIj1%`PTrAU0v z%wqk%7VFV5{+MMAYRvAtw=Y%-4*U%j8%OC-@0~W%H*8%B?$2r~w;Z;5&EKtZfVNnT z8+z&~K$=PLvSVm*AuW(_PZgOywDyuD1p%l>(gQi=7!W}BsLY8(gIEDzUl20Lc1=PM zN?@mI@+e{9EnYS;kHApuHerOp^n%eg)qMsmEvo->Z@z;w9{gDC<+`+ z17xj19Xn20-td4`8L_rpGtb4zfpa-wl?Q9wXV=1FuJ*UDA=}4F@8BxjpO!nPmJinh zvr;~^#A!U=cfIOz?@0UQyu<_w$0o65kMVC>ppN(MR~P<3$58K$=Ir8;dH`Q)vMYzH za%!2e9q;97hOuWmu)f~~$>&||YYzQ{phPr}; zLg+UzXT^tUTAqz&9g4f<*|n8CZ)J|g%&dTWUg9;L@4w!5DX+f^s(}Zv5kY>DxThwq zP6*XmhLXCOL9mgJV9C4y%3u11wJ87}E8R!fU>{O$uiKjL0g5c)c3cSUIg{bwzaO!r zhStYavfG;i6flMW9#23ChF=8e1AVC%~bAuf1S;VBUcy#Dk|(cJ<&> z028kQ^>F!3(1b=n6S|?UyZlH|WD-rldzVCHtk1Oey{SLGGD&McLE+;t>YJJ7AK&Wt zwkB!*@HlSX*bT`0@mSxZw{D*q^`lMkV0pjUJ2Ql$qxUi;5}nKt1;=~Qi|eQhZ2&@j z(EPvxi%9|_?u7MOl(=72pK%Q^Hh)_w>{nSq?O(=RzCqV6o(%=ut&O_|^0o*B-JlF;hY)VNVsjCdUd!X*9!Cy#80yXX5Km zrgz3s`#gZD`f%yc0&FbyF3@TTKsvAcZP_JuTV~NnN4ocx8bQCk0nncFy;jGSe!p$d z{5z~Sfj07jAhUK~-vN?Ee!g?UXdfX42Q@V!FSI%KIW%_HmidjOcSX3W%RNPw)f6x% zUm!*v9x4gT3r{sD;sbtg!e7B>;hV<{eSH%#sO>)$L zL9ht%Om}jms!8i_NCqQ3z%Y_6AW#h1gEV_sIES&70=MKyL{52H=m$0v-Ws$>!8Acw z6jM!2G5ZBVXqjw&4VL$s`Jt7`X5af2uaKTM2R*ksfWdFhAYLIQ*5weda)?*q1WOPG z849<)h*qI^#e5R+3PHEV1gzI!f`#sq^f0cDB3~gI0h4orS%G|IGc|~$E67)2ezz&6 z*1d@rPQ}rAS(v5aG-J*V7+!Ijd8fi@W{dD;mKTzWGTyM`3#TF`d_azbLSW-GuzLzr zP9gEHPZHp<)68iZ0?75s7$Db&c0*z3WYg^Z$zC&EQJ{EFq${4VU^de?Pq1&8M5C*b z_$y0Hb3*}sGhB@v`38QoA%x#-EWmFzjfdat3iWa`q)Rx2Co*3`!uI|p>6v-*War5w zix8?!V&$g!RlG+Rj#pFX8y!7yn)eNVf075BV)t0NdWzFV57k`8o$AXVl+7P*mP!AX zwL50lUF*BCL9fj%A()~nvlh(pwFHB#6%=t`@{tR!jAvWm00i3)_9ZTC3s~x?>h;f0v^9Bf-6^a6Tc4wBbhZ(*Tch*_0!&Lz?PJA(pJNngS$x#eq@d* zX*F?{qY`vG;hs|xQo@eI#FL0PF+f&M!#iLcB*Ou!`vb=An2%c8K}K9p7Ebi|I5Xqt zh~xr`yXjGVJ+lytOB2d z$Ig~(1;F|$Kjb>ZOME|tv)~6?hlrA zlL!~@hXuunUyNHiu4o^%0wchvRAYjdPq>yOwim;n9nHt-RKEfU2RzZTJ%p59-Eyt3 zYGt5TWtUwcP2LhW4+7I7_ZeK1`t0WoQdVJ(ZX`1zHk+ybO(rM2ch;1c?vGsG6yNB> z)kU;3mRB5^W+&B`lcaU;wY$=NLOeSGo$v2wy@Bl#wl|@2BzK>>aTMB=fHDbH)qTQ8>#3HQ4JJ{e*mha>fz{RR*=C)IEm+L( z0J{-52T*d27=j6}!~l$rFQ?-bT!ra?ZL9@$d5HQF&FWDMCuvk&OkI4Z@r;(FXr#vt z2sJjW;|Ab+&PiNB*aw_k4Ju3Ef=FzK+D#JP0|KMX)d`Z-?5&bo*WFGMAQBP+21B?j z!JoSOv`&H+UW@?PPYGC1?9&?1FuitLUq>$Kw&NMy(bJWSyPX8tb_H0n;UtJyP`A+* zn`x65bae~l=sA1=N@%K0g=@S7@#(sIyo!O)|lBR{p@@*SaA2XM((mXNLt52!n&^U(UMabh%Rzvzkesw=B*9W98!h@Sm@4W(5(~qIpH1k!U5lpx+XUr` zW)iPs`o}@ZC9dNX;`EI(y(mv4u6MVMYTqU^Fv`7=whP**peU! zkh22ux+cUJMo_e>*yivmPuxWL1wY$^_BCr_kON1(Mf*o@lNll7^Rp*fXvLuCov;ue?^JTiYWg^ zQNHdguA(S&n-t|^-x5(0)W4!cB2h}&FaLi0E2xD&>z#V#+E-xm2Tg5lyL6l#_MJClp=jQj~bTqD2g;eQyIbllv&2Y~)Ge%3?+N zp(f=TPspz=Z&rR!Ny>SD)~x)j(j)tNT9ltqdZqSUi*iTlli&T_R^?=*Uuxgjt~?c4 zB(?wCp?qg#vDD6YDnA)nBDKY;@`=b&sqOkY<>w;Hq}DKBITTqgwZB=QbVXK3?X88% z(a1`v{eFz2tK`?dRabshSuM4{)Rk?@8hO$mF_gB*Q&RgCQ~6tEt<+L+r6H1%Yrij{ zq$2-B`4@_^DXIMOtZ$IkDC<{_N4`;Nf4N9`JMvGJl%o9c66JK{o22%!Wy;@0zFCg` z@CxOpBma-GR8g#zJpH#Q-=rwLs}(o$t#V%VQ_3GlzD=Ixf2~#OBL7VK^VO8{-H~sX zYg@iSnN#u|@&uj#R7pm@Q~6d!`DfpxESU9Oa_vuZuafVU`yKi=+e+5lJAxCe(k%JFGRjij{eg3CmvZel|A_Maksp?4-twc$s>r{R+NFP^ zysP|csr~JbDPL56L@{ZXf2;V)k1G8UBe=D`6 zKcSq6{5yH`{7)*0$dAju_Kz#iL_Q|9KmHHOw?}@0J4f#PN9DTmld|vfPbmi@|6Xdp z^)t#)q<;P2Y zMy~yxUsnDk^0QJ~@=4|6kxxkNrC+57e@<%u^4FCA5&3zZIdbdQmA_MdLGI`NhO#K~ zi}IFr|3&$Gd@r>>klKNL)V4@%ct5qRQd@eE+KW>Ax5kX-T3tIDu)SbpQ$ zS>=>+L~2{lDd&`=Fuzi8*iV74jp5ZME-D4sV(_m@@{`>D<4z-x185_QTcu4 zxYYJvRQ_5yA3T_93YE$2)zL2%)`qUp&U&>n8m`YM#$vgYasdrNMW$oX$rv9H) zK`3T#I+a=#N=^24r2d!G16g~oGxa~Gre&?GJM~uTYgzlKC$%^AkFqw}m->&XZ)ENN z?N1#}{Z?k;|L(s?wXZ4)1^FLdOZ_*gNRIxe4XJ;hdMIm~22%fh>XEFyZ>0XG)VH$M zVWs}Z)bIWwo%)A8cIsdL;X5c{>VJ1qfBc8OZ7@khS6Q)c=|KQP%#`=G6YwKgrsEyEU~h zl}P#5_Zf0nf`-bkHK{byPGkN<{!|03Tu z_HR@F2XDx}&;HBQKc@aa*>~o@;;mA1JmsHRu3w-NB^zqPB7gc>O=N&=CMm6NkjwSS zAKvr^%77;eszU?!6&84Y`3svYaM+{9yg9evN@5`n;41OtPkfDC0x0Jek9AD-EQ`F+ zbNlC2#w+US=Uq!aC8LVm&V>PYoe_fB=bb>;jbi+ySz|`0O!uO7ftW9gJo1D^uCby| zt>BQ2%MY@3l^q|k-4o7-c5uRRS2=&;?{n{?7SmqOo!5d6nndhmJf#)LhaJ}FY~QH< zV~JKn%^$W|BoWr9;3qThl&Eq_P(DR6ic9k0C+CO-;kk2&$H<(@WuN=QcM@6Dlq}t( z%`QI?xE-_h>D}ZEpO<2fWY*@1B?B~Ao=CJc*YMuFC8tF5P9X%(h-$3*QqGA!#KZkX zOD!si@>AuOJfw0?x6Nt1xgl<8~DWjydFdA2{u>1IXdd!oVlsP!tBv+X27l z=6;F3;ZxWYGn1@{1|d4mN0C$Nl(9~dN_j^Nywz$jEgdn4?x}UW1IBTO5F~G}am4ZJ zGrZ-Vgs6W%*IazvZ7%KrZFpPQKDl|e`_AaJy8WGrt@pC=!j_oVj=e8x!+B@S+c^7` zHgW7voQEA?efA|oL0g_&?fFsEa05|Kep5^~3b$uV*d&`p^U)Ff{R#%jio+8GrJDep z8}UVqECr(v-3fqTb$AkzN8C5bx!zZjQ6S?n=*2mim~|c^3E>&`5jH%Jb-a36$C0;B zubTwRyK}2Nv%kFe61hXmYwL;V)@uf&jXcX9V?SKW&QiO`2+hB0Jvxj!@G$!>Zizo)Pqjbp9!4!$=lJnd* zJhDKaMA7$&5u-G`Y^e!RBvKiQXMAWzjPO_;;e92fpUmfGbd)j8C#pA1_n1}3i77KY zrB_PEWlAc=2+rx1l7U|^d-{9>;$CNkebl7hMP5|{=tAn(@_MNeYF%#H1Kq7btyM7l zOp>9SQhPm2hqZY#xMX=fW>jA?J=&I?%y|#?(Y?D#3D#KHEN$IV+!Xiltd`J#-t?t4<*An^HLB7c=o5Pk#!#%zoHLw}) zOLhQ|VTb*;zkZv+yCT*4TODJ zfp)SK)3S?(5PLU$+&Y}W6Ry_z0DB`8sfJiIC!EmuDr+;|@eHn+R(K-gzJn@}J4|GD zXG3t<60A}0ZpI?DX-1tTty@)ba0b{2(hOAjq#~~Z4v^T?F;^Yh9IJg~=1XNB0YmY& zho(?G&YWM^}lZW00-PqXeNPgKNMX6laA!q2+<9whH-flca z&x7g)`36+O?FH7PzpxcB%`NoP@kpJd!&emumaRkS{Nqa@96FY6=Wc(1`Gt9IK&V4l zO;@#~qh7YWD^>tX)p|Q#?_6|XQWpJt(#-%)KWMn^W=DZ6g?JADR@VU$q41dH1*I@; z;TmZ~AlbDs?%Eg?Oxz^vqqHK>?qDO#u+2^uymTh}$J=i$R~Mq;i|9t);lwx$_n& zYi?G5kuLn_e>c-Sx$(+I0w@Qfqs))=?f1=y2{YO!IJbuPHW;P6g>Sgcc*Ril5Q20D zh#WrPcFFnSR^7GVj(_W2*ySGEb#^CA5RN6p|6-zsUooou4YThVhl(5GfA{DN#PPMD z>fTkuop75?uNxb-8FbMrWLfZF#VxR>mzmYsD=AnUB0#pvnJ?rTK zOD>rA?Tf`+S5Dgh%>eSy;bbuA^TzE;TFs2m&zpZ+FRx!emsH z-v;GE44uay--;;}8V;D57f7DB%L+5M(cr{6IKcti~K6qMX1L-)_p= z5y9QGmGj^bcxo-lPB701-_CFII!fa+1U!*Y7X;INfO##>iU4!_(to^;M4JDimP5C{ zOJ0-w)$R>Pio02Uw>-CueEnHZVGxA6?2I}Bw8?Rj$(#b-;2hEQa5unYfmMe1AsHVQ ztD(jvD(@8ZoyB8uE6e4a9fEk_u>jH)s-qbNPNez>w~&uA>SM5He+{p@FYBrOmE|Di zJ3vb97GT=l;L`4gCElM6)Bz40Bq#EF8Iauhg7V_=HJ&=ma){+4usY<+P%J3&W>bcM zYN*TLK9Fh%oDD@@aK;Jta}YeL7$5Xr88`Gj6krUWpvs}6A}a#tAzVE;^YlL^0|35} z(t*oP$NvV@=@AY%~p_D0xL+68R+ju2VhYrnZU?7lJbSc3^5tS|C!iJrLoOSA%w@JVa!cQFl`Qlemz=6>wG6%|` zqjd0JfFSU(pK40*?1;w+h1$@N3RDl@t^gE~v`y>+MvYorM@yWf#!qJ-1Dd}X6-wXK zn3@_<2Zq(;NWVWylrpcn+W~5mnwD-wO{1mJcLI-%O0ROnv7<(Q0rM1s<}^Dp)EVa? zS|QPwdN|Zl&#Xmw*aAgjBd$12C5M2+jMwxA+4FYBt@-UR^jiYr^Bz8p&s$XXSPFNf zzNAs|=Fsw%UFNdUnnjj6d`L^gWP@_&n*#pb2)~R(yrywE^dM*nOP z$1Or8s!-%os}^n-s$PPfFIigYNP)Bh!De(qtSf1nGvBz;N;`Sgjm)`HHx1gE@TT%KZnBb_Xd ztJ_5@g3`(&6gS{By#N=4$I!f=2DU28A1VK3K}FB)Xnr|S-oqPdW+Y_HhTX-@Ui;)W zRC_zZ)?_Dr4sL|81@8PzRRKtPuyw?N4j+BcdbOXEsBFVV^dXXYK|{gD5Jm>9c9EjC zwaXM3_2l<+i0Rct)h9k33d=lC(Pk5v$ZvF3$d2YYgv=l`LuJWGVWBS-5!!{`5G@QI zWlXXS_ab_gNuY$m0I1Ulq7rXBMC;H+?vJ3C$!)Apw!tVAw|r$c7RCdH-ObUNcX1)R zF*u9g6C%^bAMUNw%`WXM3FZ`3UOP`g; z9XyTT%M6`Px`so*a1oSD0ybL&K_-Fd7dOvzO>GK#?+!gyhs&LOu7#c}my)$41K>&C zlB9S-MrH0o>0H^R=P)Sw9Dzl*Omgy=uhU0_=IW1>iJd(hnV{6WLR|&x=>2*ZLwP;- zk@=sCCZu-sE~zPY$yk9H!Wl?6K36$Z-WN!>Mw`l{!OclDf(F&2R%KuL{0S>6@5=#? zl(VXG&U1gy)ydP%=Y##99?@%is9Kp8r$!!NZFq>afozz7rY5h`egvTa@WZs2ttaG^ zSuv_bCpQV~6*G4uwgv|v1lzmhh_+8c(|v4TbVOpug#$i8fI8Fu33?9Q;7K8wKQKGM z`JzzsI2nIMINJDP`EK-2octVl63&bu4iUdXj>MufQ-$AS14_u_S-9M6FqMs3{2f8M zxMimECU`^OIrUDCc|_}z-gGO8Vs?0~+1WiMGO?hLJeml`s~rovR3jhb!F@CY^=9e7okPedbjp4VY_TvIVz^u02E7hRJ3EhnZ>4Azjd` zd6zWr)Zvc@J*ZrjknKO2mC?fi2Cq0c+c!Bj3k@RAlqm3z6k;R~}t565}+Bu=WoL&t;3 zCCNMx`Dk}C{1EnG_Rp(31S9PVBM;P`(#WhjfYw~^-!1$1%YN2o zWzFSWc(CIl`%IMR&u4KkR>!m`#DV^)QMcy?Hp;uBv%Q7Uhdp=4!k+u1kJ zWJd&61@O4h2R%1NANNj;g6S|S4fLq8Zh+eT-l_tu8wc)aC4~Iwi;l zqtEn-Jtcb0o8s^chduqFK5+Vj6QGDO^(n@PBKNPi$&h2291}h zo8lcC?(()xy!LYcEmYslzmjY~yzGnr=FU9xl#`v~Xqo-X46two1-RdeFnHQg6UhG` zWJttTk^K{7^nJ+qvaCkN7lpuk96ZGG5np%=e(1Djg0x5}Y`jo-0;|ioHE$~;1l-U&xTjBA*waEyEq&l8wn6RqRzrtd~i(6!5x#E1AkLo zg+;;NGP5PVjB#aKX-l{seFv&Z_pOn8s3+YEqJ*`>lS2U_)`<;2gwb;U2KS*YJt# zMN0!%rHSD00bh#k8Fm8$Jf2QLb#@jJS3DPB^2p?tAAEcZAr0|VgS}Pz2#Z+lgL*5t z!fFk1t7a9{I9J0y^8 z7Hn~KeB|p}?%L08mxhrIq{kzv(TVGB=Fl26-OX(XRNM7r=QN3iOXH8}-MeppQ!)Vf zeQs#IY;y_aS@}{LB38%jS-#~x+k@(?b`Fvl#twJ$I&az@$-q_0jt@KF!UiNQ?@z4r zcHD2r*q3`@#W0`uqVD!>F!e&XziwDFB-XH-w#nPw3_*yCM@H^Ccv8X;k(UMC9u_@B zFVjHQ68LK7K74uLS#$J;V$N*I=M0DpY1`;;0=Sg6rJdm5$RkPDY~xudiekdx8fhba z!@Si+4`FcgEa{t_G$)P&JzQ3!gHtWZZrCIKMml0u#<|yLqj;c4Ojuz*ec?P3n(eNo zM)neW1oc>DpSIM8mbaQ+hpkW|&DPlOS%`XG3hl%?i|k(_6TXSs;*y0TOI3|B(cpei zL&MgT262j^wF&K)=@BIn;<19lzO31p+h4A&s9b#F_IEqo^c^~PD^fmQP&vaT?TaW2 zsZX+3K)59bo(KYU*@x0?#mht3Z;)T9e2@}t%mS2&q?i$vqbCKb9ZA3^1F%aQ75 zrpvrA;I`i6yIP8@HBGXQL`aWsHF8m-^H8Wu12j{<3JMjd3CJe=>)URqnO0i?)wDO0@Hu z&+ZR`k%hLqkcr7r8X+{sEg8HWoDhE=FOB4lklc}X8jB1}G*~2vDoFlKyANuH-(A>? zR)^8bCR#+rfMp01c3ToCw)NFrguz)*R-f>cohT6%rx4LFRK4l|_9n~Hc&hR9g7aGePhgoXTB zOrwt5Itl)F0XXmiXXaIMiVLeYu%huP&u*}eSj2* z#r;xH`KYvo-4NBb4AOEzN)kpkRsL*Yq4+M-fmbSNKz;tayV0NY^YnwBJe~&C&o94S zOjAV`Xq$Zn-0w*tZ+ftya zNrq*+h)$;4A!McNK26edz4V5w;7*qsu*)RO+#Ut&OMjG5vA@_)eGV}1MV6oMC2I0H zIN_K6EHY#&yO%*9H7iDELb&^D|J2i`7F&Mix2qB&^75aT)O6Fbm<_o>jpUdhv4Jv! zi}%N-`^@-6Y3qY->&&jG)ADxb{<#Bo2%?&{^U&AU&5v)b6>8fuHrq%Jz2=db)&d5~ z;ebqfZsQO}IHxH)(<6%2EK&Zrb-VpgbJ$J+Lqc775MwQz^lH?&6z|!Q6oXQv8GpLK~`oY|<};Y%XCQ^G!EQn8HmFx?_x$KAe& z+rXw`#3|WvJ5y9!)@zx}L}_f*jd!yM69_VA?+nFV`J4%Bo!iI+mHQ*vqh6m?m$%QV z+B?Z87Upuok0s|RrIzD6EUnw^l!@&xHRUs2*(v9xw9?o#|vZB<62@nOBQXHkPn~m(LTXS-8kg zP-9T6&xn77dnuzOKx}oI*{V();XlFnh_v_!H4~l->C)9QU1G<&1lUf?X9XB9jyFK@ zq-@OSm;te6HM7}NaL^;+%xgy?sy2(5LfPUY4^p-karC1kzq{DEko^Tnj*LP+-f)Q| z5yMvwb5uvhyOMR0ZmtZvodrAkV94#_l7qu8sdkI}0xgYUptuvY%nrQtN4Q6yKXlV3 z$5qzl#tMziTWoRvcWh#69G5INy}Zqb&~FM5_PQw;m0c9L2z643YL#cAoYawoD{DtOY~FI-uQsaliczKblPP5xK8ys)O&*|2QZNbZ2L z2~`BDUdmcoCt&2sy3YeKwNxgB^#M7#>zTON^3&x~AKqwdJ?q|zq zoj0pYd|vbc&c9+-uHcMIgjAIeoJKcI>|A-{V;!d(SGMrr;)njfwpqAWVH8Z&{l+yhG)!_soW5AgpYxHYGhs<)ZyGqz?*Z`MiT>lNnalSDD~x z8I@~xo45rT?(Xtwd(9RzsI0$jV6`8JD_bcOySP!ggKxB%UZqM1BO!D!tZWgb;Tz>k zuAw3@Z|VEqkWh?)2YMYB@N~f_pN>I`K#YQ}+r;RUI0wFQIP544O9^PYF1ttA8bVV< zMz{Qs*X8T7SB`N0HSV zS+aGp0oB$;tcxMZZtT_#LsX@RbTNVsi>*<;F)C@7-MTTaRTr@??C*7~5EhV!+8)75 zgq|4VgRH%cF1ft6+pg?7C}HdRAh|(gjB?sxT+Q{$hoqe@udT(=tGsp+myq(>1#(H3 z*UrLRl-Di`;+4J@mu@}YxL;M?s_eudAzShgY)>*=WX-oK`-m^Z3qtl`O*v6sK`UKe zgPchB=3s+e-h&1_q8qYDl;HF&S<74HT}^1hck5lG$(GK>K>=thueB7-d-`Cj?dwCW z{-~VMhN+e!tvAwiA2!-cLsE3;jgG>gY;@8;q#ziOq6;k>MK=?u6f!~EM8E0>5Mejh z2No+Aa=we5S$q3CLmZo$ZzLnrs(uPxXqCSchw0>vK<&+Ki2FsW)01R>xOD=_vn$Cw zB+atdkvKDG0=+aIG_44qXhc0Ug)tMdhvpDtlug(lz-0)Yy-tj=C+>qxi((N)R*cby z7+URXBN_2TQ;NeiUc{crrlK^%@>=b)^Oz%HT@fr4*<6@ z!U4p?60`4;h1{77%2)Gy#m3O0Z>yg|wmmVpsH1pd+u{L-`H=*DST}hUUQqTPaYU|8 z;jM@5VXxEZ1pV+Lv=C8?%^C1l2{o|AfQ8eR9e2RUwbGbv@Oy1}@|pXYu$?p+^;6lf zQw(hCv)N+o7;fAo+Ihwt{FVrwmuRyHD=xAX;GIeoeD?#^J%IUy>llDj~y;{ zxZLksr|4KD2A9|~*duMSs!!0n)RnT+uJEn3XdZ=2tEH|e#1~SSGrVzyITHaym-L-3 z*`|N!($P#C%5M3_Wfaxr3-Hp@m(Sgf?kcyh$;e(YjLNfXGc)okwPLdn#u6{CjH};T zzkg#P2NQaOZ)&}Rp`~4Npzl~>v@XRz_D^wxJ@kowpG>j6d1FSDDqc-_;P#R}^u+zq z>F&ww%s%YtUB&EIJJE*ZGC{{=E)#badBF~UgdWE5?O=K;58pvdfs#z)rT`Fw;)*BMgVP+ z4qGuph{jAd=bHoAt1TIG<^WHI3TC}Xm)L^Xl-3nV6;+&;SaF1xqYZQg84);v=wa7L zt*|LQM3+85#f*WnZIVo!TCQp?i&^v^Ep|Z>XG9ExB5D}SHgTU7IW8^MzxJD0|JrZ! z(0`3Sm~ye@_<`TknJ^2JOh`peNl zF016@=hYMt1U#h3>?S3%oqTP5$qDtl?`)*_T83(qOhj zA&N6+^JGRQF1HOuLaq1@*b#;-f?EXh-r^etjWp~5?jA&jqUBu{g{u{QYU8HBkB-Lc z$LXF!xGcEmaA|;8Fr#3VZz$pOQ125uRaY8ByE=-q#aZ#VIJ9lr?VsE+jd_qXvb!Gk z-q;oP-P!5ky#$uP{@-pUXzHsmzy_`-L$D%P`Rk`LN(`+spYQ~XmwAYMIfoP#4^Je& zV!{)gb(#Quany;D8*YTpsVmtX%qMvqtP?9jSwbK*?#<#}ixah2@=x4G1Z?p!__m>E zkJ~46Ag=73?JI1>FY>oy9VW<4Yv>napxD0*Zi|dz;-$IrLmgnv8+G@hX@1f2l4=H8 zVLAV5V3dp>zxGh;Z$hhoYWqWV;Pt3)GWUlbkbym>#sLr33x4)?lEvNJd4#h(UelzL z!o=OmDjlwwv4Q73Atyw^3+S^gMhXBpWQbsPaJvXvk%56U1743s&=~j@tV1o!C2G(f zM`&8*mw=JP`h{2m{%mdkQth;i5yLGoaKl66-BW@gXvpI5Ok7x9lEnjP5LY08tyRqk zSUJP^2qnW3<@As66z8qqKr7bS09WIK^d>^XM;0jAu{vab#Nh*0c!cACfgiHLxsE^P z1mwVzFbH6gDMVX>qX6M2e6i0b#2NC3VuuAkC#WG*5H#;DT%Zsw<4(vCBni_uh~Dh$ zK%rW&I(()lyh9S)7g-Rh=|IeO1q&ZSVj-IeN`|gB%TmG>Fd{aY&=3i1Vm}EFt#%Z& zkXxKLB>DoC1Y$D`Xktk>Bh=Ota~X6FAvhKcDjbSXLf~!c^a{yF1z}0-0Ci(8BQW)C+e4gDO!%vjZ1VOI7_WEj;BBbXemjPP;LMk{;VYs%>3dzk>500+ z$|pW-82MnQXqLTB(3w&1qWESuRoPBLX!=pZwwD}aPe3Sin({RG-M#t2_Chx5Eezs# zGT29)d)u(rGt4YUW^&(53;;F~q7RFJpL;Ed;hQ}PI=YZ(d*+6`>7unj8HZbBr*FP% z5_#wOW>?XOP|p#czmH}l$sww!yb%NC)b5+!Dj@fa@EzRZ3g$;dQF6%vtAmFe0lD2e zW_ci>91@+RMpgnF#an~b!w5bS2on>h(7KZ09mm)193HCHghhl4syA^+HSjqN1?3%= zR4(`g=T6f-4=z<=xaU!5+vp9!s{%fWiOP(KyhJk>Uc{jfjRsDns1d7d(L>5nD5Rf?*utaGr5e%yE0Gb#-i~H2C z?I4XWkmKQm1@ZR~FazI4K4)0PFYWWs9_(7qTqK!tR%cv-NL9%W-qnLIK9uRtOgONS zKpeq6V!E!%kViE}=@E4#sJ-B4)41Z`&d1xvlGL!3@FesoL{{UQI zf&skSiQk5%@FlGEGnF3Z(LRZg9Iq!+mFY<&5H7}?1X1OM`8-@F)1sdz7*2l;4NB}8 z=V8s^V_8_|;|XfBqgKwT^PP5ps}NtwQjL3B2m8Tjh`TbuS#a}^)7EByfP<#J^xtxt zQ0AcKpYD%lgg?&2c-AwO)uJHAtCgBW3|E(=CN~lEZ1YJ}<~1r4ILx;k^^P5{7NTgo zhv`F3c!v4eCQKDqL+>*BHu?i0#F*yj0#Q3V#SJR(RxO+(O!K#Tw@%;i(5cjx@dzF4lZJtBbjB?;;MhtnY$@;*)gE-)_ zk1AK}d}(zrJ!LfK#)4IgEVzYJbwnj19`Md|P`WKSx}V+882JJBbYXPCpN+cpm;CplkDB-CON4jNJ9mkVYFi9J z=LnY|(g7|DzDD>YFndYeC#;dMS`y2{8dDYAT4FYqFxbK}5+!qi_?VJ;mcSS`J`|85 z6SU1%%X`PfRwSIK3p5~HX*-}C!jdNNtA(K+%maS54~1DTTm@4(V59(N03G_mf6wHF zOXtQAxS#wjin8;<`}~|cS1oG-Ug8Z7m{eCg)un+H;h}-wL)!xiU;$~0^wcmvEy6It zZwWv4?7tc;h@Qm4sHq>?8x67*V~V_yR|u^E@wnFqtoso6zSDNq_KyI z8-xe8-70jI2`*3sO2c|$S;90bK2R<53%|S*r2@yA;mauCd1|mZ63$=E{5_S0pI-mj zm&u@4gW94tx6!M^9kd}g+w}T$%l03trrm|IBjL=1Dwd#a>q=%K&IKdW7GX*4dZ<3`D`sN zw!Q>v6Ud#v^VA1}4-deJkfVsVY@FQmSe!e-Q}A=Ymt;=3CE<5Ag(Ze+RDjA{z$zpxUx3PVpE!}G#ulD!QUKy4zsMl^spx{5OKj%_6-gAUfPC=Itk=mmke&*F5qPbc>JqL3 zU?CjCtEyJ=SJg?dUA@1B_iymWuS@2*kr@)m0WtCzxb!x`J^h?aqL@qm^kuP@dkL|m zHxN0~dt-RI11yO);J%uZ?bwWV5`OkNc2PRhzNxHR4P*(*G`J~YDTDPArAdBx@La-E zTAOykmPlDrsxdy`axuq{n++an53KKQdh#lmcXqFS?vEpKl(;zwq(gc^)}yP(AKHxb z@Ho}vxW{00OIEzj0mcFp*%%NXFcfBLO4ytV0-rpANz zJHxZRFAchVQGG2DqJC0m+p?o0gAX7iAVCm$8s#^EI~Q#s_uKbdy?X3~b))wV6IoO@ z99*QfYKQ3Fc3l>)2%v|usE*yNP!%Yh6!dv1$~1=YbV1 zw;`%WpWcxBV^c0{vLB7jw%F0$p;?q&Wmt~(XUNsFq-#0rFKP$9Zwc2K>ASc(+yUBb zYCHsm9pu>^X#aQ3Gzrbo&}PLxVbqGn&sF;H zRU40Z&}S+bW&(dBs846h-*+aLxiJ6lT+WHG2DH&kC(ubiBEWcodI9YY#tU-+?HFsQ z7<^|1HwOAZtw&G`9Y@YAqn+GPT~tkGG#;DuXwo9nH+FF~z(A8*XFBQ8J@jZGR9=S2 zv1nB;?AI8DAZCBbzv^vnYQZ0~+Prs2;HPB5L_1%yyot|_mF%jqX#JSGel)BaiK~ah zn!$&4Uw%LE!~8&B3DTG#4)D9r!M+%t?U~vfbQHItS=@o{a97Y&dIJl&BvrnXZ3LjD zL|;G-tb?-13<@q41400~(S6Y!0JaX9e@NzlI$3D)dGH4SNz=o>WX6k(|L^|Z#(x>3 zY7wS&(axyUQXw@U-RS8bw&(A$giOn41IQ{?SePRiNc?4R$QM2Xf>K)`d$b*Lw{gENlw{B`)=QBaH6-vr4|ii-d_Qox1E7VNk9CP_#x zJU4@dNnA=yY2cP>PZ8O~kpN{fJ{^uYJs{0#vjr>wRJ~CwX`1<=Kwsj0M3J{YK){0s z*o%)xVqGJdLw*a!zRko}j1#dij#tYjw|$&QY76cOtMY9acpl0_T6rgWk1($X7<0&~ zj5&n07*>|aCFU_Q=~D<43vVEvC%hJ87!(h_fl?0_#3Olm^rQM4uQ-u>`FVo>DB!IB zyye+8d9vO;Uwr2ozodctQ@rbws!$B-SNJE-MwK8Pc4hTvs|Rcw)Gy={ejd~t#y!-u z=!n*Ud9qee_XrDtxyO2*#r%dO&O~{U1VopaBs1RO(kO`OqI%d`KpU|&DCH2#$HP^d zzZJSL798FbOGEm@vlF8-ikpCHttn(5GK5=@&%br+m&{J`3Y}(2FQXL}=;vgCUZth< zxl1S)HO}_uYF}~aQ7@X5uELg?^dzDOD45`Ed*D>Sq}>H&0BKrODYzOkQ=uF{Z-*`g z*;J56WKP4TSR>fsIILhf6(2nT3w?qticmu4FHlC%ylANt1q|3fgx;kcqR(FZ1K3&G zo)c3~is@X7si*~jgymVFO@i`|j{?e7<}QJ#l*mt8W-t*{(YzqGis~iCj;(bs;2DD) zj@c7Qm3Id5%m?vo5)^&LRL|Wd!9EvlfU=~@r1TDT&z-Y`o^3_WUaSG0+y6p2Ti9&TYyVXjQMV!666uRk1$8I_ z?Me4&VaPqY%{@BAEPizG3)?-Kl{xunCSpE5N|Hl?@%(u=LD8O!Pq*c_PPdk}1a@FUUWnWz?9Ms;bZrZf~)m4@9lk5v4!q?)8K8Cfqu+5dwc$n~54Er3NiYx(Z%X^gD2} zQozOj>nomC-g4Joiot@%Bsp8kmZkl;Q6<1D!s`PZ8TJkJ;XF);ZrC%@;|~)|fVU`q zyykDT7w;-7>=38n4(_lA_s*h8#>})8zh|Y{a~P9yVy+X5vWep`Qa{nx7A75co!yMx z88~`8ElGn(V`CB|4F_3}@r1-w48Aw9Rp0n6$bWe=1r}<-xC5YR!H7x*=%ah^d?8T@-lyw{ zwl!NwbZLa-A4%~pzPTFsSMMzyK^`A8-H**97WuRHo55N$+K=={yR9~(V`i`#lX1ax ze{B*0|7-29eVRkoX;J;?6ZV-Q2$dk1a%p_P^p2u8rTIQK-#6FWbv6O{yxRrZigrC~ zhP*UhAmSRn-ok}=!p2$riaBXk+Y*L+$;5vH*AEh6Rp)`T#ZC6A6;%(5ZJO?af94?G z+ulj>D$hnpq^IpVto(_E{tur^QBQebh5}b06oJMT=-@hM4e=~M2|IXK;ua4eQm|Jm zyF}3w4k6jF7u-G)Q@}efg5}eLk zOzrK3(V!DI|E@g9BlM!)Bop=JGvYt42RMVfSBCaTPiZ*nM2p=qj>G(Ki2W(o4Dt$< z=3+~uHpz@&3-&zkbduidL|2hi=*xIj>iJUiYMHtWK7rJ`9ZonAJ={A=tY_Z&n4|#( zrteqzC-WsRQyaj>pORFmnW(pzjmV4@b^Ak6_ejKun%!TF09>8uk_;C_FC4*?w2I+O zCsyxT>Jaqo0Lr}buHY|6--3U&^i865_vY*uF8!Gh2sL0AnLCP(B2JEMQ-WdRu>>3{ zA1;;;%c08Q{!IC3iHqfE0oYG{p}v?4%ZG~`hF|Q*C#iC{KLZqSZez3-zoHi{uhQQX z-Zv@ZyU*JQ^~*+0gHhv9&@kMH`@s|`bBIGgpvOgkU=${fHiA&ff5K$LZY;SliNVNL za-vEi)|iPWt)p15Vhf{A1UIo7vZI!pmM$Cfa5niY+|8^j=2|8&ucagjTIG!h znP5%sDmQ0Y`bFer<)xo|0bj%8AR>H2&~yW8IULsyd-X$6!w}ebO_{KnYI(jYaYakP zjsD&IJ^TIWPnvIkkFP7)(K1a*wy`kSkRNI&4$(-ok0^L(Bdg7!Vs)31>YZz$rAqB8 zRq0MT%`g)pmwVi_mAl~d)^rV8OYUp0p_K6?$e>yJ1LpST5>j3%>o#3W$U1CATKY^l zHkW?4-0w(VJlA98zRP^I@`uQ8x%<;u=(G=7lA#8Fs4*FA%nyPb+fsD!v@)KpE!G#f z4nKGNr`_zmjw;#fyjDAvolg7c0!PUs`_EN{ah#Vn1n0Lss=hf8oZK~i=&nf;#B6yn zXWiX*b_J&h4Vu~(pW7JL-Q65s-rzOf7{hM#`?mYp$F&8wP>4j9#ifxr8oN?pv=&6cN?zfyhNb{#a8;^%EaCm9e}smRH8| zBFw^arPaTY^H#?4%2-|*%PV7fMG;%311t1!g&wZZ!xehCLJwEy;ZH>eR_2tIIpwG7 zOMi~oxY7?-`r%4HT;Xk2c$*d8=BJ_qD|5=vI;Z?pK7H#~t3F)lm;VRmMFUR1Ebfy9 z-_1%87%^e;=Uaq0fsGk8R+c6!(tkk{4!!&l2?AKSEFKFm94rEnDp;)rfozpO-)PB~ z{We<`f4`>=aSPT`&l~Pef9tCHfrq4|98k4|jj^gp$i`G-c&gfGPf_+5LI1UH27WNy z-ut7yg-t={S;wui0$&bZlsJ#NZQAHokAxaE_>0r(;pMhMyn)*Cpz68u%=58NUX zcX-)2Ky(QH*;fZ5f**)f^VS>QK~kmq1MYqj&+x26cGzu%Yk<7Y4*){KkqdTrX=6lG zccu2L8tzwQ1&6)n(S+!%p&*lrMJ)R7+`Zm`4ONQ%j*y|gg| z8&TjzR>?t+fE90#0f-^-D#6|Xt|H@a^!9)U+6n<3s|@!9DS`9W=L7KxveuO>o_0J# z6v~jdyO4<+3vaZPcHySIJr+#Kj+^5TdnQL7^k;u}Pwg=t0)9OJ)ObQA8lhAsHCmJn z5SjA>fMnm<0A%+41ue8-$GYd6Y~C5^Yu{}A;a2zE%Sm>+?Z$?ao2DDCCmT;~d3@{W z?UIG#?9;yi0`qQ{w$Gm0@UZrJX*@jlM|_aK0)lh>Z~AW1;Dj5gt7fRKSRh4HUL`1F zf;f#U0s{y1+j_z~&%PiWeS-ZQ?=I|WUGN8_Au-Tk$l+`aeq6{6V!cgE5!W8*WrB0S zm8%xW!?|CMGh~P+0{@bQeiMU%NWMBoRa^^N89_FLG||KI4k?q!!sXC1ndzfbx@8zT zyKu%PC7ZuB>MU-W?JW#XtKD}>1HW6~BtKW5OQ7t{omMHEuJv7O%#(ZN5A}JnudpzL zypvxg8-C}Vz(1MrtOJALK8qNe>Ct;m@Cor4S92zCJ-}1dCIU~DfJ&NuaA*qua6SZd z?nuB8fdU1F19T)wjsf5+@udwm&f^5^m;ek&hEg(wQVB)E%E0C=nWR{l_ggujPoo0^ zB*!YL4jLt{ipQG7DewwVD28m+q#ZU9th?`Srnv|fD4-EY$>0gn;g6q#?pvK~B<0Ki_j*lgfLoKT^Y=|&@3rSDYq8BGB2HCXo^B$2 z?iH6b$*I;XvMhGbmtE65s){D{)|ujRiH;eQ0<;}Zee!>% zOJ;oDBJ+}DfRJz$XpVUK69vf}paG2t5+U&kO&bajRz1LG z;K|d6DJ6&*3_!BItNo?H$9e|lPG-U?LPv@Y;G_f`1%&g_8RE+hnKG)0`Jq=`$;{ACysAOQHz=MY z0nGy4P>Wau{_r%Y}o75b*Aw*<7N zPXeO%$V7CQONDkRam(X$j5}pMQbC7G`gHu1*hC51=zOM9}~W5!FR)O6aey zT>7#tz`;;1YMyAb=HkwvHQ64eldWW)+#GfJn}Xgc@VT&A5+n+&VZ%=#Wciuc? zy62c(5|V9udyV+2*aeP;PGmpwW<6g~%idmqWU}llIT03}k*)O_UEazq9o|G|6;7G9*u$yGBU!DHG^_!#%3W zGxS(CP78_t)Rc49X$lPi17AbB10=dy5}z6FdQGDt`f|mmno6@qVj}~D2FP?R2otPV zL8o~S@~kll4?wG-5q6aKlHg4yv}@la!|q{IlXP{=`b81*r+xOPTRWZ`{NkCvC*nfSGHCEpZ_#!ae8^7H zAgBF7B9DjTCVw<+G-vlQyVjQm;*<2of%uXEyE`B~vM$+3ml$x-F`;upG2*dCAv-Et zb8Dr6n!-SxKM-6r0N)$%P9W3z#-k%hv&FGyCNrR&XWDL(AN;z^bPL{e$<%gWM%w|T zY0;%}%UWB#%3s$~x9xnj`z`pe#da+D!OvgVP}&~9wIh6MhxgWw_qPY{Yy%HSz<|Ir zKsW-A5qZP`oYj<1eGgGQp-n}f4Wuvv&~^Zvc^ySEEN{CQJh@IkFVinOySoY)eq-G+>O z>oAk@YMVTgz#LUs-d>B0k-=U8K4KyU7~g!*njeblCjpa~0@k5`8U`Gb24EhLW@gbO z@iinXY6FEIE=lI;V2vGcSNDT0(Yh_}#5nmNM@ddM7&gM(eEVG2TS~_<@4FYxt-s*$nRibhkIt6q%T?bVqu7k+Zh3m0}ul1r}?%d7(X$InSX8=M+? z&?v=-pkoE6#u%U!n*xNm;MBMPmj$ObqXnYaqBpigmqBdW>YkHdAh3c{+hoT!kLo|Q z4Vi)8Sbn$5u^0W64-840p+;H9}DXyN8k*yVe4%s z^ZD}+b+8=qp5(g&@ux7B)h`dp?RV@2qp$VQD@9iOtt?y%zE##CtLy zAiYONZG?5pJ8pYgHGm~iE);dagx#ryd~%|@==yo1=%f|T=@+c{6W$pu6!LvX!MtpN z!zgcy8sZ{436TFLP+ss&7f@c9@p^I{{;B_7EzMw^rA`7-WT~TIT3L#u-~1jCu0riI zqqGJ5T1$Qh1Q`GauQc6niw)_qc*);C9E*UzHcDHpFj+_g7tWOM- z%|_H~fzVTD^;<_NN`}{GeKf$dZ-o8Udjr5lqSLeX8HlJ6}S>Cr8$cEuWG$Yn1Yo35!B` z)MC&F)Fp|tDBmL`yOjH>GbzbV#RQrGf zjVz;h=7g3+* z_N{>!ozRJCC3nQ*-kakg)>Bgc?O-0-MTWvRu$qFdNTvl$KaN*ja%d-ermo=Bl`xw^ zGz5qhGkT2Ah-5S*X{m=nCb%fMOQTB~Ju$`sh$IpvNui4&SN`w}!U-j$9X)l*Q4?5p zk7h7;V${X#c{r<%VF5kBvcIzIWA{f`LXUIiS|?Jc@n~5m_mKp7B*)X9GvX1$T*P)B zZ<=S8xzFZNmlye)J7xLhvg88lB38%jSq!+K?&2k|+BxVbpm=xl~5_1Rj}H@<;vr#1%5YXuuh=8VX4U6 z3zjeT6b1>_kCN4p$BU#PLHXa{=V+gtjbBgBY{}0zh|j)mY2f+X`L1NCYEpO zO{R@Y7ITWK8ik1%id4<8r)o-r4908-51VlneKJ-JXkqZLsWjpmdIht&rvQR>75UC% z1+aFgaNzNj=sOgU*a}rzpuijU6o8QmT~4Hc9S&ZYyx{rXvC_PM#pb_dgSzCumDc?$wQj@x4Ud?D%^B5*a3H*xt7->kb`KD~P}mT! z5%2qCgLix*QqsWLjnR|e30W_02tV4$8UDs_cWI-lD`f*{H~hW0GA@g3FX$QF`JCP7 zMCkW>i}s0})04NuqZB3kY|iP%cb$FRB`apD%ZC+M?{o=&UgdNOhd_~7yqMEbz&Px5 zz^&If?X1_~f`k@JGOIJaIBEG-2ax+n)jO@oJgPn?Tt*Id1B-%c%$ce=2iw_{qb8bR zvsJT0PVq>!;Ogq~%fu9_Rx(<2mU08+XbC!`bh`M3bN6I#ZQhDy8?Sp;N*uz_7Et0Q zr8*p3^F!6?kp4n-J9s(=s>`W@neBEi^IhG}de(a!e5Ck20Y}^GoUv8EgBq4Fn~z|S zN%Io0AXgFQs(e25PtFXhd=3CP$ zon%!@KC4VW* zn$PYJVR}ZECEphi^-*&%(?b4*R^N%6U=7o(lf(nPF4Z`2}I z_4+y|w#Rl@L%Ib5S!}8cxreGmy{$yKjSs!8P;4vGBd|v#41ndM%8zfWG{;}K=!+|- zhKf$cl}LE1jhnT~g>)Uf(<8-BqG(j!u5}czC1PNogGP)uq?;n8^P*lIFWF7rUf#Jg zK?-DPN49C?16#=h*<5f)j6vixe8EW(Fxv+K8S)tQzwc?GZxTXb<8`kUjGdS%Ms5QBa`R_MN`vFgGjh z@oMdH#lA>R92J8u zCf!oYvU{&I&8szyQpfERv`4{uwO>8Z7D@u-8-5b_%M9`Nu&xyL1h?5jsY&ielaOW8 z6?K;=Z^^4l5@(_dvB<*1h^h-3v(R4scUf&j&3H`~8er^xCN)P?8RimfD`=RAX+=|r zeZxji7?B#=dx4EsdKali|E?B#8?)C5J50<7a=P304%zMjA*R7cRqF<6nqL zVi*pTw4?b!%=x6{POvCA3ms7YK06<22ytG0h=FH0KL}yVjCJG0+h3Koy1jRDZr5Ez zosI%rd)m*LZd)lwA~VcC*mj2=-;zLjmmE}&TBXc}#Lu``_F(hH%fgO3DM?0%Y>YdB zjlgMPJtewa%A(yXg%k8ph#({d14j1NI#^I~ANB2iDUe&_Xbn<}E=g}EnI1mp`HML6y%V zX`}x5f*r`m(|?h|Df3Qd0Z{K91aP}u z_i2ls>!mkbb?wXVwk;(nDV?``3BFtocRPJ~X^E&uiVO}K6j{BI4ZCDx(CySktcxLB zSJ*l15+Y3z>0(4etlYX$y)hbM>vQYIJo2YeVECu7zc1&@tE0ElePmCBd{J3@TSrLC zzTI|Z*Fg(>4Sm{b$ZC1*uwB_jgf<@Caz2h*m=R?S->u5p1)^5V`_3X(m)9;64p&~o z9FKunUs9DPhD5L7a~H8C_aOjAvZKnHk7JzPCt& zBkd2%M!N(a+fj$!=qNxX?Wi-ssevM|i!S7Fwz?Ct3{oJWQ{b*6MK8jCiD-T&Q?FG z_V#zikJH#qZzLnrs(xx~h>>L{hWg}J*u`-!)QLdnULHcB3MF$ZOn(TEWl8S8FD;Zv`xX%|}#de_wIC7xaLR3P5;i|WE zR%4QulD`_C5F8MoA*Tg*0`C5pgJUfED2I?1nE8(}JyT6*YTU$;;tff!qQQMe$eP`s8HMTWZ3jGKpJF&`l&1dtb>nl zo%nJn?4Hcw+fmAGAQCngstee6h;MPc{SI#Nj>oaCyaNZ6L?tcn#Ww!GTGuzgYY)UNSk_zo4RKrYhqV94cKO6ttC?kERh;;PIxH5y z&k=`T3wuQzs2iB+n%Wu&UQ62F8GLM|C*PQPPeLzpuLa<3v=(z4dEeHua4^n_2nQn} zj4r~#Aj!71aDel(=pf3%0d-26ZrkfX9unaI@kmPtoym}v4mye?Uxzj6C=&LIbkJTf z|FJ9|5DpZkL`0B~q<6JXayx5y*@~c$wohnDftX{rA}oO2=7OgLV=uweS43oJ#cG3m zfY^XTLnvAaM299;kt{`g06Wu#s@?j z5TYU0-aX)#NEZ=DIKo-%dIya#P78I#5u#e`#*wg7#EwDaOuKndB0MBmP|7EAM+-s1 zB6rYETJC5~fRaS+Xf2MFa$;XCjSo&_)a_W~{Ji%zdWx-owI+QYoR>9MO$ZGWf^ydL#U=0E{N z9_sYPx}O&z^mdXZ^2K@7P(}MIG8i`t+$nHG2vDy?0uQH47^EIYw7`|$#KM**N~SvJU;l5VT~;G55CG#T zMwhGF#n>rBPf2GG#{`%_*gw2v@L8ai@m|1RL1c(FQSO!I{_A(AN^^trq9p8$ zHZ-Nl1H5lo0m(^xT<~q7v9)hXD?U;Lxdf^;BW)g*u@7D}nCI`wnEH10{)4u2bG^0uR;<8;LQ^~QmqXRhN{btsK&yOhjR(>7ftyL4k^BPC^3aC zQ^UB@`hP2}k3XIre28jv-Je+KQN27P2KJifpY9JmD&948zIu=lRIRvi)WCyR7eThX zH0G*xn_?8g02Qml&Nb9ntDN91N4;ams~rN8Z1*q*DknU{3~pa^hwP! zS7O8OMKD&xG1{nRu|6esIw9W(M%t@{?(bFk9`MG$Ffg`57=lt7H?rTKi~`iw@^#vjCxMB2(=VI!YBI7#ix3AbuQDUAQtM|P-vZ+mYiBM~erx^y zjfEUWzZ-m0>m3lJ+pm4`9iRK^)%462^QOS(H&!pjBux+;eM?;|W@km7t}l+vB7C^D zd4R>mezqk(Wn*F879OWS5d-Kdh`Y0g3JyEK&;`#JaUAOisK~5bwXv4PtPn?wAi>#8 z0EB+K+-zQ=qCwy^UrnR z2cQ#6A^70BL>8bF6DE=r2246?3+zwTqyu>n2u`u&>;i~%XBWs!UH+E1cXB*XcR=}_ z&?w%|H~Z7=CG;C-b+B%$9epqyG}+O?O}ty=Z;tEjN88=noKcqp_HT6BJ%j}wFcYJpg-!%es$H{103bj$W1ytdIFzx~|pgzaDd%yQM{NkKIgOD#$RiKi;! zIljm?L8}N;fZ*b24N5_+Pss6!`x)qM?pKX@@Y?;?z2?asGlKZvd3S8Oe@@OU*IPX_ zP=I6!`9&;2C!x6(G?5U)%eLaBvEsqdKu|w%)FmPeK(lyS< zMpFNmBktw?p&@jXH`dyWx9R67^>$k zk&Ktj4&R@bRS_cT*CCaW5_JEDe_-9&jZ( z+4vJ}Qx_wd+Jfp}h2zDF(0^Pa6r&Eg8HzUgeHAL~kQh~2XH`l{h?RoAZj*`64F~|E zL9dyX$0mM+8cRDC0VRR>nK&rPfzsqQOEUEn!C-O?<#hyiG&nS*xrlyBocYB-ppa6m zn!o;?Q_B5Rs^8{!YB06j{}?KyW-J7DCpU;=#-54TM~j*K?!^;Ug`jo1`lO8!F)dXO z^M)w15yUz$s~{%vF9Ct<&;UBK0!%XTOUQ*{Yv9Y-N5|8=hVBd_GOw=d5pSTE zR>Ldt$o$tzGrg@@18FgW~O%1jEXYZ~M+I#jp{&yl5=W$#SR9sTcW##uf@BfJZeoR7M4`U zy5)pokm^Wt@p&TwM|I?(@Jg1x{Wb3oIEU}UOOnTvT-n=nQ!mj$K8W7ImvuDG{IeYpM4rolFNLXKDg{FAHJ6ppQylMQ&=wSEX%l?{sb`RFcXp12eN!(_NCs3=wr|r-_PZUBK$eMwEV=J@q{+%yP(N1e8w$M} z4`8ie`=+dOh0i4zk|8}b1fL44fxI~W?SY!VOhAzbmtlFEZZaeiA{?pL%A_3Iw)6xxiTM0wX7JV&S4%V$NP>fzXhGFOK&TK^6%duw zct}HYJW3alN;^jj2PyRk0b&#e&n{6Ae* zg{frU#1#zCcayxlqN6qGt5CXOFeG)pX3e;Z?g#J^Pd{2ety*v>L7RkkMKCG&eZU8) z0MpdJ8&f|u<)-as31G(UHt+q-j*RmCh3~%p1H$v-)UQyw5N}~w_7tQLM?wB2q}hQqCj(652-|4b zqP$0_j6rPv{eQ6P^TRgp(P&;Y(8CeRBE_+mhu@JY*q(<4(IC6)XZx17vV9zH<96#L z$-ap;?y1_MTn6p*f^oy+0R2yMeY4wQt?TC>4{vnl_ANe-jD)}X;8#+PqC_Q!F`m7i z)MDitNRPOzKAa)dpw_|(kl2*PXWuU`K5C%lRkKuDL)$A#mKT=Ll~Vn_^Gq^R`SqwA<^r+5Nai{PD z(>(qMKK98)UFje}5I}SU0|^7(O91yCBp=t!4E-G3 zaxeoj^!WcTr)9af!% zi$XoRJdB2pgT-)zx;|>vtKL{c66~2Hgi6rGqShk@1G)@hX9cPB(cSxoW zJqwimkTbCOKJUdcF`6-xdap@$!j(Y>Cz;3+X2B|=?Dk1@ zDJtyZDe`+IvPjujYWt;!Ed0W;9nuh%G2q*~z4Sr$;BnJ4)B|6+8|j?xWVe|RN34Hh zai59(4GXM%>=ezXihbEPz?;KmE032SK1%L2g$^m>1N?2g7>;;2#kzkIQZX%(_{6Gu zjS6AkeSkh6+C(e#9jf|WRdoB1TQEdg0dfowhipCEJqj0fBy9Z7))1FSxxrzFgA8XI zdNTNec37!}V_xzp!~$yLKC?ivpaf`3&~{06VKxJ8!#=IGBJ}J^p64nF9uhC*frWL3 zlLDE`>-6;ePQiV}f?t3}rVYJ7kH{Yi;{>+JZ;-DswLSAu{-wkKSmDn}lOOlihK2CA zSpLzbIq(fk^yXaBlEhnj_yt)wp$eF(m!O~bDDG%a7PA7LpoTvdxm-bfWb{CRG;Is; zf?-3BnUC+MKVi@CPGp;;+m<|&ObJ_YCSv?);efqP@{0`yMWqdfk_x09#G#M0`3vsL zJ1@UidYAHBm;R6N6#V~68oHU>8ss2x33wZm= literal 0 HcmV?d00001 diff --git a/els-f280049c/nextion-els.tft b/els-f280049c/nextion-els.tft new file mode 100644 index 0000000000000000000000000000000000000000..c5b568f9558088259de0ddc302a9a3b111c25ebd GIT binary patch literal 423476 zcmeF&X}H_uoiO~Hz@#A!A%qY@2oO>TAwUQaLI^1hYk{GZE>l`c=b;_iGL%j?rrXdC zLwTl@Zj|Y?9ftPl+0XIWY}vA8OP0Jywk+AQE${m-Z?e4GXYVU!-s^cky`Sfc&UM++ zEz8@_(yjmf|KA5(@ZqQKeB=V~{@>vXa~HgS+jarCfWPoUWy|~bsgDEj{vPiU7l21H zkDRz(*?s}orQDzT?snz=ufXo>rhc!ifWQ0?{r&FzKYnlDy>~tG{>^^mu1C%&OWTn< zmD}Bq9DDTcM@}iXyBAI>?f19;_wD_5R#~?mIsAXOz5m?zZ~sGI<1bh9H~;W|>b=$X zRRvT5RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K z0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$ z6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90 zQ~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5 zKow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O` z1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0 zRX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1 zPz6*0RX`O`1yli5Kow90Q~^~$6;K6K0aZX1Pz6*0RX`O`1yli5Kow90Q~^~$6;K6K z0aZX1Pz6*0RX`O`1yli5Kow90Q~_1sZ2-Xd!^)lVcjqGjyhmK{U+esZ+d%5$|FsG< zpV|h_e&D~?OV4ftd$#}gdjI)tps?$|*CSuw2ClvS|K0wpZU4QZ-1n9B>;wN_`~N=h z|FiP@3*hH(xWK&Y0Qe)af19vt2l!3s^V<@;j(~U9?z?bf*D3I6^6d*xUUDrEzWwq= zPhD~de29E%`%9M`1V`QPZhu4BUL60#2gWZs48HL3f7@ZdWIH&wws0|X$)~~nzD_z4eY@N{pWl5JG%`DOy}SEP;J{P6Jj&yrzx?t`V!Lku zzqoA2?v35Y!QQuOyN_PF6TJR7e(A|eF9N&wU%ltlrKiEfn6&4mOL4GFSuZ=f=LGoa zRqL01de24RquZt&+Ti9P4Q z{>Qf;Sle?D9JB2>uc>>{Va6Y#%tk@Tr48RN4#o{QBVUE;|A~ zc>jG@qnBL-e$!)ln>1O}shk@lMr*3XvJ`09lt=;^GeMbQL>kl6{@7n=>S^4F0 z`@ZeqKkhhw3$yQ9aO}w!ZxQz$2FB>mZrOgtL2&*f$8J4*#iQVXA0E5yD_3j>#?I;6 zUcTa5F!jPyx4m`6HlR1%bo(!^H~}tTAG_Ur#a{52-~9A;kFsB}fB#A0ieuoScQ3tT z?TUTiQ}^C@$L{^Rz^xxWb;rT|5itDP&+lmOKLl=hb>WU(R~`m~XKuUe)+={`hmU{b zt}|Ee2iJf6_ES$O?GE_Jsb{Y|3M|Q~wO1Y@dH{;|!y`{?yBxXR7bFPd$Eb_sUaX<|hBW zM-LnagU`Kk_UQvV!RH@&_3X0;c7a1Tzxm;>9M}t_&sy&P{(*zwy~l6;$U6u20sU9K z=cfgj29VqG5A+Y51ae+_;D)Q71OImA>I1J`brQVuiGO`ad(|#*=}FB) z_*Hj;Ax%CkU$qD1zu0?t>#8GQ<&PhHyNyC@DMQm;5U!{ z>EIdg#>>}yG;(l1I18peDjnPge$O!XX37-2OOp^ti2# z_s~ILZ@l&~!=Zh^_O|t7%%MBM?XP;DT068IT=|pRJ`S!?KKHKGkMFwX9Jus@?WZ5R z<_MUY{;N;Cbj@R6Z}6p0K-cU9hR448N&K3<;If16Px9AX3qJXGJ3l2|a}wnCeECy{ zuDt<#Vp{&x`D?d>w~p=jn@5%96hHqrPb%Ag{kN&V`R27d!FPM#{mc)Q_B)H=&;04y zQ{bP<$Da|d-37`&=AOx1dlcwzj(ql_>$ZV+{`1$L+kV{{aKf4Y-2K-*3_kM5m!ExI z+1~s2m1p0$?kwoX!k;IuI}C2gtUZ^x?gkM2;pTJO4xa)y{_9g;IDPmA@cRpFUwHQL z4sezCj=%lV;oV@7!2kA}hYx@!{J;EPZyvrCoGjh@yy5Vtf&KGuJ-_4n)8O2{T=B*G zuYV4F>w*3k-@X16Si10qFY(u(1Fu&mzqIqnQE81@Z^zO!I#GW z^yTj#*#R#9tINLf+L68B?zJy}<((r>g3tc`2Vcz`xd?oqRr_i|dESGUf8)g+A36tq z{~P+nhd;CrU~i;f{OpHzgMV1hzxb689R*0f^Y_2_Pz?Mye*UEwZrBa}aLMOi`t}V^ zg5=NTmxvoqfG;c_|C)5eajd)7KxpaT_RCd|!V|X+Ppy z|N3W@_6NLU|M0A`+_n6~H=et3ANc(C=fCmI8~1|a=hNSO{l-_opFdFj)==61#?(XK z-hT8rsD1Tw-#K~o2>7do?|tW!N4J9<^5%CwdvqUo^6t@hUOsvT1ae#7nLN4+6n=Ec zD_Uj$Y1H*f;^jqL*m$e#sAG8hK}6;e&zYMe_AW{PWv4Uj*Er`oTZ{_U3Ki-O4v#``yh)z)e4!e+|9)S@6eH z^|ignp907eTmSO>@moPA{lx3PP}-4)fA)If_&)GYzb?HlAKwM`WuO1a+VR~0{$S!K zJ8pRoa1Z|FCzH4A0>Aq5(f_TzWjlCSsQ=V>%OS8I-}R<&%YJb0v&(N*Z`lj(+`ad$ zwOfvXAJlzs9l3Qcxc_VS|NPXg+W`Of@t>c*btjlLeEJvXmF@g!_pd&A>u&Js8(;j@ z^S9m!e9-P+zoWFdnaAJ$v$EgyN5AnK&8@!x7oYp{Z%*HK5KMO7dgtle_JQ@kEdSdJ zw><^Szj*$)&~3_bGAaMosx0rj?+5?R-?kn6?!Kje58d`0_~hkBes}W3IdHl3*S~xD z!~rmH9sT_qC-#6BF23{+zg61jU5kHMIPnYcfk&VFk2AM#13NyEfA{R|2f%Y1;=7-` zeLr~o?>_aPFDh;6j?Mpk?e>Gr-1*{^c*hxVi6~56d*?yWdE>{^XYSkw zJ{|E-KY8Z?aN`}h=@;(26SRJD)PqkH?* zd2sk~5%QmU65M(#t3P!23Bc`p+wjEQ2LX!y5`N+C8^G#EOYoa_?*+5f1IBmnJ`Qa6 zo-k5(Zv$_CgETtt-VOq9M~t4kcLQBu7D?RwG+6oZx6$LLcY*nvx0z3$ei;1vH&|y@K6}p&aOAab*uHen9&pJ^uiL(T&pz<2 zLqDpj%!Gkbi%j;MmjFLb_jW;7wMf&+PY*^GGZD46@vMcG{+J_c^`AIqNl@I~M?%P(?gKKvH=^iQ>U`-h(g z)=Q+qk^2vW@Sm;{+r zL#uS|BYy_p+jEu_1O8H;OoD=uXgA86X2%0 zr~dr;i@+ypry4JuKL!4<`-9RS&hG`c|I-VS=KMkM+P`Ea>il8wzjyqoSvtQB{NoQE zlg0BpK#cgBET2CM#Qval?1AGTE#KPyeP9Q0 zK66_aec(#~8#~iI_~0S%$G?5Dd-_4;b3Juw@5u+ZfxX5T`cFN$2OKf~y#Ke#_Lq9i z{woh21Ap>8J$UcIhk+sX@-X+{PH_C8Uk>XJUJJhUgf!go&{+`u{YOR*KC}~j|Lbpz zo_y#yzR;X^?4!56n)e)tr4Zj}7XpC8@^$TXQDvt*9UlLfL^nIGY?L~1IB7{ayL z`b47%k34sEWAzJF*OiVo7@a9AC%!|1R%>>byLaUc%V zVRD!qm;-lM9E5{PFXe^8VhJzBYNl48?Qw{Xj3evFIr5Hzqv$9(%0;n6mwaWY(P}nb zepkRHxPq=we6l!S#6(TMo1Cd{w46PW)R6P!0=Y;o#ZpN*ohsA{oAOG_&~kYsPtzlN zTAsG2OwQ?q1bQI&VPA;`DN5xTf)Esq3!y!4E4mmq27b|2XP_;MVX1h&0+4wM1 zCgunYF;6TKOT;uWLud(%&=C-!Ck(_g0TV{TM3{+jVuF|?rifW$fj|f}7LNxL+8Jim$L&s z24gx5!t|J75Tz&RNqUN&&P2q?e7hi12Wq+4Z!~1NydjS_bPcW% zYx>#-v)$}4Q)ar3wdc$>v$L#4OJ>4MnyuzQx|K2JoVj9ot~=i~>)JY5*V1(cB$aGV zd8{6r$L?`>C=cy%dR!jH?bFFdfVUv%!3@5G)1DK`~ef)`C*78EggH!EUe@><0(I zVQ>^&39bg$f~nwoa3eGxng~sXrb5#_DrQPhk}=`sVV;OB#X50g+Lad4qf9f`&kgf@ zexqP5(1mExUmle=#VK*EI$5XdQllnKNIoepC7Ze?Bq!RocBDOM4?9H1)-7}g{h9vk zaAs(tid2j$PC=U8%0gUR9lm^@@6lEnMlSwZk{ktn98XTGhzsaVkXRtVHl2CFaon;Hq4GW zM%j`DBa^d9Jh_@?vNO3+0WOV|I%T39uEblOVa?6DIk(5{b@OhY+wTrk47Ji=BiWW> z&aiG$H-|1bIj6_zb@EQ1)9(y81!vG1az>m{XUrLo*K)~HcF-u#RCSH{R;g7b4dgPZ zC3Pf3>f>|Gsyv@`r)P^vd{kf14s}+YO=s6Rbd-)xjpagh0~g=~F35$FbPg&orGT^` zPqw&jKNrpzBK}AsB1D3bP$V3QM52*cBpwMQCJIuk(_8B6206!OB|zdNNm@vvnyatN z&2rsAJDd(zCLnRmW!Veaa`k4}0+}n8Ig7?JZ&|P`T9z!!7Oh2R(OV1_*hQu`N=uc+ zN~GRtmOAZzy1(L^@M(S1KE#LeeSW|X`4PXuukvgBI={hh@>{;KLDe_zoAgcjW_+_g zjc?w!;9K%7`*c3YXYj#3W1nkl$}Lf-^lPz9AnQ$hZDQDW5bLO1|XVF=5 zmYt%r;;cGr&bqVVl$_1H#wj~n&Q4`iS*==}1Lx2=a;`X6oomi@=Z14LW|2nCg+X;R zKB~rSaZ@sz!cu%{HEmC)OQhJSKy@awSgq7pX(}h=XN$RJu(R0>c60qkU!sJZRN%9V z^|*1&IBuLUP8z3-)5aO&tZ^<@&rMcxjYcyfFUf1|WT)R>QD&PqbAghVknMUP!hGq8*wR7NG_!;DQhZ|>ZbK+ zHWSKX`KiLNB$fwaLM&9KE3?%>y&|=n?qfrn~KKuiqLt6u`)Eo$GQv zuFnm)AvfYyxYcYcXV0;s(Y;(wbZJ}+ngLcs#+D8XwA2}D(#N?zc z8Bb|)4soL~CU3QZ9j2v7Lv7a3+afR_3k?5qx@7LH=k?OG!41i z>JOPFBR3qTNfTt6GEJLiO!KA%)1qnCG-uM7mQ2egtx4C#GmeVfpoe1=OL3Hk@=|<^ zh)<{Bw5{reVxep(7s`vdx)yihE_4OQu@Sb4qqqq-V=MR)zKm;e9S-4o+Ws@XYn~)gU{m&*cQHs+i?d@;WWtM!6=##76q>RrXNe`<&S*0EtRX983)x$+g@lgqBI89Eo6LaED zi<5AYPOH-vM?`&97z&1}p=PKX8V2QMVocuGD718~UR!Rj56pw&pzB%nta;W)ftEJy zL~f5Bh$m;B{yx>O#F z3T)n32)6N2(ws2Iu{>EL>tutJV)^8BHkThZ5=f^<7|I6GP$?8TWy+!SUo_>UTogmO zGr5MV74A?um$hImT1%GV__6=EIF1PT8GX7IrQxD1TJZD6BJs*z1d{WjMZ`fa80_VT+^-@*Q{&KrE$%>7F>(2CD*b`>(aR(m)>P?!7ifXf7 zQVL0VQ-wI)p_lYc zy{vEP+xm{atMA8kxs9T>voNG#BaFZ(Y=X@&2IH^=CSVe_!nRl>Ys_sF@{J{_(3eS< z%jUAX94^X5yPPhUi*dPKtc!DbTwWLN@-b+_l1QdHc}tO~g$DdcUx~#^MYQQ{jZ;0U zPYtLcHKJCi)q$9?<;WPBXm)4&^DG4M?wY&qZn!0P(=EGO?zX$*?z(&KzI)&vx<~Gn z1d^cBNII4cmfW?uhOgD_Mzt=jKoc}cTWK3@ryc1+mFwl*OP(puv}eXM>zVUtJoBCf z&*H$79M2%4s2qq+IWUabgZ5AhA~Hml$Pq=NM3nWgsY6tVAQ2+MM1+VEN_R;lh$N9B z(nOvp5F+6t{6v5d;?9I7MWqrcDN`!v%kAoTHCdafX=_L=USE;sWub+3tetSbJ1`FN zL&MOnd}*V;ZK}IkuC}Y=>bjH;%QbKf@uV*=mHahbz0}oqUEP)88nHoa z605`-u}*A}W8^qFK~9oWrg|pTDfKd=a%eH632Buh0}2^JaL5=!L#B{9G!vQ)&4uPe z3!$aZa!4OSM0;vJMP$0UQL$8=swEnDv)9)4#(VP6g0$`H-lDhUEqg_8#as2(ymfEG zD|wq<+1v8Ay&Z4Y+l%E=rZk!s#LaHKVy$vTGmNPzOq(H0o5YzKlhT zO(q)2ZhfhqYorXi=u&h!s*UQRP*fi^WZ0$_<1q@OF(>B27|e~a7>9Wx!QqpheEZD!^MTLEi;47dW$fGI!+%mFNb2P^?1 zU=KI~RDcO>#d-l-vXN=z7s_^VzS6E18c-8&ZnkTkg3V&H+2(Ah&15s%FdJ?oY^2R< zv!|BQrrN|HG~!$%*NSV^wdPuPZMZgFTg(_U&P*_q%v9Gu>i8=OZIVd3Q&eUwL*(c4 zwPK{IueTZtjgTZa^KD~C-?Q}FLn_*ic52blQg+hsH)CepY#~FwR#B=fbhdOWx>enp zZe6#b+th7AW6-#AbsNRk6YH6FjY8chi*l$3^`boLL;Yv~70_TZp9*Ju+38}d>{<`1dC;X(}>bLpreutm((|%`4n?|IWAzvqB#zL-Dpp7{+m+|Jkg*+GS zMf=fVbQE2Qu133tTDBV-9^0#c_*4aU5bm(B>~s%*5a(Hh&jZNs){+p>?@ z$L$mL$z&lFEp{rEs=vWD9UYC9(|WZLEw81uPUW0tv~De{^=N%szc!#1v_Wl18&1X2 zj=Zj{ljD7U7#O)7Ek`>>W{bVGo*5O<44OrAXd2C<1+<8k&~nVIoV*Jetm3X&YxcUO zwahKT%bq3AvPbLDc_5G8WAMNpqX+Sz9+SuH!92Lf;vqa_XFaJcPt@_cC~e8b7S$^F zSNtQt=&$&z{+hq;Z}=s@5;po<{03Sp7Ak$Ccp@- ztynGAPW95U0$FQzXaN%R0xTE>lVBDWghgRVSQfN`PA~|FfGW^zf{O%Vp2SurQ)$;( z$tCwaUJvi_dHkM$NALtaAy3#7@kF!6?D|M3EmX}?A%=0Y++2|^dB|CEnw(Lh)!S6>HUg ztyS;WhmCbfCojq-In}bZ^=)gr*R}Px2Ajjq$fDiQP3tCfGrC#boOVsSuHDpb>Be;9 zN+w`Rr_s&p7U(#gh*#5jF)ImeT_--U4q;s!>Chv3g`>BsdG`YHXiepWxH*XZYC!z7n-r|EpDP%kbO1ENLrDTC3uVVf8d zBVvUZSX@Mx=vk~5nozn_qC@m!Y^<0_DT9is%uFtxX9_woQz=)6N}4I#Dh}#{br)K{QOy=qdCHXbcS?ojfQgc%F^%tVqXfB$M zW)il9oJ7UqunG0yDYw~;xpB9}O}I(7)opXz-3~Y9rrl1r%gwmm;mO2oJJVn4!2{Q5 zF_ujt$yUmjub0-uIWZ{q8e7te>=}iO8hM>t&_jJL8Zx z+SA&YHvay(1-Co`R;K8E6*LK=aT7vQ$R94?iF&G^+RDxq z7n-ck@)S?=PTt1bc?a*} z8QvX>4d*JQVzAh#BKDX)Y>(KZ_P9M^Pv+X_iUBql4Tu3Xm=dkpcuh|)Q)?tl8cBpi zNfT)%vDiwHl_T0Q?RcY-HMLARs{EMQ)u`y4I+u>oxpl0L(|L4W9k280{JMZn&;@lN zT{x!IMRZYJOc&QBbV*%Gmv$%@gt%SlL+DgJJ(qT8;H)hh @MN_F%o-Gf{TOuKb zs<3jtEz7mmpcCrFdyU?xukF(V-^gxA7?OrmC>76Trz9nT5T&D*C=n&2)~GXTkGi6c zs4YqlwWg)jL@)$LEC_*+h!wFRcEo{D2p!`SYgJYb_w_@6&=B0r zjTy`a%zzs#2EsrZtZA&xbelHWR(!++U>5@B0mrD#&rJiSi51m0K=nqDM;b1fv2nxYqkP6a4XV4XN2iYJO z^aQ;@KIjXEvc7h1=o`tSl`a+Ah=t=b>4o%i8qRofy|S?yspT4&-0rg7VRxn9jMlRY z(MBbqser5&X@NUd_`Z$C;BSBs!s_7eGQ-FYx-ng%h&dmN4^xEju#w-khoH@ z^cIKNC>F&FmWH!~8f*r8ZnkWzj}0P2vwPl+x=sE$zs5iBU+^#bm;B3qtzYMd{CdB^ z5BrUN#E<$-ezPC*;{lDO;GY$Yad*6*q>|3ea(29+FQk>>$3nSKnNo@&WX;tb8}x?p zk(r?wnsKIT;zG5kjs90}qJ+*`B{0=ypruT)zC{n{Azh>Ebc2@YCN0w~x=nZJF5RR1 zg^rSakM$tPfasidr^87(X{XcaaxzZ0GZ^zFYDr_IUPl^6*(GP%^F1$vF*svkh*Yvm zkD`u_qwDB7`i_BPm@4PZMR#$tLRU(aMpHAyM;h(8v2JV_C8LsvGPaCL*lz3^d&a(T zU>wrM*h0dS45S?C#dI!fEyCrdXsRif{FYW3*s|T};VRXl+OUHc_;3#8eY~F!@IgMr zM|eJNOV8)Whgd1vAe(|EXUSU%mZGI(5iBW7&=Rs#ELBU*lD1?lVN1jkwZtrOOTv=0 zWG!WjXsKHo7AejqrW0@?mx<<8jj}D}&EecdU!`-NVGltPknK`iMTNkLlz3 zgg&WH>C^g*KC92^^ZJ6m*o$WM*?K&X6jRHobk30T=2Hcm$TpDXsEu^SI%(ywpX{yl zR|l~Xk3Ob=B#tDIWZYF=t`w{5^~7*A8U^)1ZE!p|8=MPj zg7d+N;AC(rI31h`E(8~YOTp!!E(pa}(&luq?JqUTi=|9uB{`oernb_<%tkI)$W|9> z=0?9W+nwlXA?<)&TfqRcYU zT56N+bUWL1bdx=-C-jDW-vAjf!`WeBv^?t3GxRJyM{DBCS<$qGcIB;5JJbnvL%r~H z%oz)22f58MT_<|}Ub&AzG~|R_kR5VB6vRMoh=n-FqntDlt)~q%9QS8dv%?m~6qyoJ zW<;jKRGAu6XBy>cMk?jg^;|83mY@pLn(gGe3+`$6jCoV!gor62GoFQ;axcbgGF$F3_jtk6nCVAsaa+Qsq;zayTf`Q%#cWAi%9gfe z(_7hu!zGe=NkP)?|BvS!LFkb!H=1vCQJ@_!i!^ zjNt=3ix2S}-obl#AJ5}T(G@S_B3{9(cnz=P4P3&TxQw^(HeSR>_zJ#?ui+c`re)kR zVVSf{S*9&B@le8@h$j;1K)RP1=HybiOqQ)m8j!9{)o1F<^|q3!n{G(WwHDm=b^JZ1 zUmn;8>0xOEW3!kBo5vQgIcyPI!j>_uSgkgiCV2x&LvbhpC81PGpYxaG-dx{;3wRLc zaiycfLwFdE;88q=$MFQ7#FY*e&)_~+AV$Y0lN0Gm9xhFmnTk}OYw*o+S^2G7v39k+ z*N7R-WMEEd8-Dx(6M#cpv}C<|?IS{RGl!df_s$Kti{mOy+d9!?ojYnfOsowwwx z;&KCR&$g9=ZD3GJ&>6GK%$VI~*36kbX0Mqy`^-VJ-yARt=8!pTj+rCosEy9gBx(eilc*qC&p#UU6!LlsMRj3~v4a`|{&YU+F%*6~@=~N{;N-G?6 zf=<#YI-Tzogm$@6%y6uWwdUIBQ`EmSnB0jdidTOS4XvVcjgta;%5-vOMc!{cM00*r1X~b!K%vdqf|h6OrT~ ztx4AkSZ$@Al178q1JkfPR7MKEQD7=C9heEs2Ic~q(QJavm79ivC7OsP zqp4^#8jHrG>3%rwsWOeaW8_$ItUA^l>yC}YWNM{UtB2&-!6X_&!)OGJqA@g%CeS3B zBGIN+MteDC$c&hk*mSHZX&Omnfo5rr_RwCMr+u`a4)hFz3LVLWi>YF|xK>Yem`*-2 zijGCcqZ5%%q!y`18WAa?6bB=%NITMv^dkL;a&eBVL{=kfk@d(%WHYiAos6ya9KA|h z!z$Ahl2fTbs#TgT5v87z4tLhP5+$#;#dfD7^o{-EKpu%P+_T}?^lW*@yyM;p@1%Fi zJMEoGwbMn>A+L1%^h<$HJ8tqx%OJG_h0ED5^*9fghAX0i*Ses z@gh9pL;Oe}WzF{`eQ~k8R?(MS%88t4RHa(et)x@B-C}RhFAW!mvLR>)8GHu6Az%5#EmCfo>l|djxj~EabF(L?pA|}L)Xpnhi0a-+rkYz-R=rRi#Yks=glTtD?kc16k zGdL!+g^th_dO}|qC?%kgup+DqYr?v)HAG`bmq;3tOtP1nN#(P&ask{bm`c+nzM+># zo%s$qT=s7T#{8@PHUD}k;@|LZ)&qe_i4IHz#^bRBpB9U&rD1ishDyOqtC^H5tsJvV zD}f-Lqw{ouRuUw1nHF>Wa3QxQAuao0K~L+QdY7KjyY;M|(|hz@J+Jra{rZ4j&uqi$t~uz#p$AS(mL^ ztIi79OR;phTsJjc?G7e6= z%8&?Epej^@>QDocAZ4lv)N(_i^^PM~FK7y`VnNhZiQ0V4Sj)E9R*Tlr+Mpu{2aQ2{ zkPIS0G-wK%gIEv`T7pE-8nngHWH_~$TQ1_2Y%9}V8qJS_x`M9g)Hvsz3(m!aAl54O z`dTC17Y8LuM?sW6uFX~}f#ym#GGws|R>f*q9cy4x0#i!+p;ECjAcJJ6wa|#jE$xza zLOZFQ(oSnE&NX|bfMM>=FQ6b(irQGb+)x}$8Ai+ZBoC?EAj15qIw9wOp+WHuj21X2w# zr5pmI`glFtoM{eQbZgkD_E@Ec*&l2TCx^pPf+8rAvQiVuv16cM%19v;N|`7#g;6+V zp=^{r6)%=!tz@k+DHq@Y+=Kh@5FWuwzyNpPuB^;A91MniEu__J4O&=h)S_CgR+sQ; zk>q+t&NmB@YNs{Rc8-R6SZ~xLdQ@-Ho0H}8O4E$wkpfagN=O+IkqXj6sz?n{1}2Dv zG!Z$jOn*p6v;AVRN!sQhKEGTtS;N+djf+WHq$rQ3u{;*T;#dL`upkz~!dL{0Vo5B8 zrLhc_#d25yD`F+AjEUunbs}L*$*EyxDjUkCa;73xnkmg!tkq`S+nnesCBjj`F4%o` zubsF1?E%ijnK_KZISWT{BxmJpoSk!U6i0JT&c!h?F6)n*;&RfXyh*;;FRhBxV!mRN z8ZAbdG*MRuoWV}V=rS@!w-Gm5jD(RiT8%cN-RLk3z$jmt>7-opM3u_Sc2RbdgE=FIaA>-(lH4;j!>UcrrW{o(|81XTx(@G+T}iGWD)AE9d5F^G&KR=PjhK5!)3V~H;6Zj=90d*It(Ym>6IKl94EtMgp880IGuO(nw*YrF}93ye?`Z}OS^rhrK> z1!JLvA?vQz8bTY>Wpz1SURTtWl;TiExi*M8C9R~Z#RTQ2_ZOPQdc`hU&|Y(TjM|5hh3D zEyl!{%fhIvYwGH{hE5VOv0ufdIcZT^Y9(6j&a^Vgc4ib(uGVd+19jtzGT&bBLPNxA zv?5m2YOQA*ahGm1+pff-Qy}?juv=hqVt%M|DWg2rh8_tFE;X=3=r4zC2 zn377{Xr|kNPNo~{k3xe)Vzi-O&@bwj^vim!UZ;ojdgVpz7OpU=bDf$e?orZ2jTKMI zXfm3On9@VSMxzliqUp7cG63$ahw-o_OoUBgL)aSDhIL^mtPjIsV;BjeVKcN5#=>MG zlUWgml1Z6SmUHD@N|5C$xyml3*yO6ZYOcDg;gXuUR4O;91zP5AwrA~?`qFS}*ckP( zNo)$6#%7dJUf(=056vUh_$qZ4tWqE>X*mh0W_qMmcFy4T$6?hW^*dy5@o$Jq&X zlAY@L^1%{acQ?EKh(GF&`Qv`2tMjK)W>d@*HziC;g4vWdWlUL9&Xl(&;#3+nMKjeB zE8E-g(WJ}dGP^Jr?o!HUF4AQkP{mArRln64OU{CtjxC9Hmjr$SS7e&2kej?u`BE< zyT-1w8|)^##f`ViSCn zZ}Q4iU_QYo`4pe#GkliM@p-<$7kQCy@DeY_28q=+m5il4*=E6CC>5%0Z@bw|lniC8 z>?m)Dl-N!bt5|&?86~$eNM2QH$FiYiXd60)t}sIj}_yX`O}2(|I;8R=Uc+UX1F| z)_9xmH%C)mr`P3WylyY+<)m-~i)dM6#1Mfax(KA?4fx1R#1bJQNCb_r5l6%sF-2?< zV`M6_6j_Ymk?DvgG9OupEJw@{GGdL`BUFTrxFSr%9hr^HMYxD3;*I#K(Udc0NJz=a z>=N>NRVve%st`boqXLFg2hD@j+_P zA5Iu^#*z|YWsF&)GTqQvG?tB`v0|(mYu-@So6Q#o6{9S5B7*{>V<1M)7#Nr_G6;hf zqs2sXmdP_t!wMq`nI8MWLvSr{|{sD0^UTG zHjZbSUgl(So2DTRw2-uvW}22#@j_&kgmUR5$S6w%7j+Yhnut{**Q_87#WkT`8qwWG z-A^jIQe9V&>TXTlZR=%Q5DTSfrUe!hgaIi{FR8<7{Jkdy*6;u9_x-=}Oy->Tob#Uh zd*0g_IzBr6?wJ$c4xRn$cdg%jd1)Ug9eU!QfA!{9Z?(VG{&xGH+W*}CZu_40z3uO{ z?`v;vf4}{M_P?ASYJca<8)xIfpH6%xoIU=-ca5=wvF_oP_&2?vp6l)HJ=*(a?^nIi zQ=gwb@j>E)?>`VfxctGtKKS8-AOF&L<{xJ-4qO^+i684Y*CBMA@3_$MUB|_afsRWZ zgK&E6{-<#2(zjop`}=U?C&%`DxF@owW!Tknrsdm~vn}UZgqHIy7h1k+0hL|LU`woJ zsAafiq~%iQd(lJD{;v-M6R-<--}du|2HzY`fYsqo?FZUFZtrgYr2W(O&)Wad-r3&O zzQ6tR_Ji$ToOu1j!IOPozjvnfZ0|tV;E@(k5Vef)LucQ=cp`pwUu0kFzK{0(ZQtMb zwe4%)*Rk*8eV^?6tgo~0pC^u-Y(MjtbB#jt#joP~+WLWe|Eew8#<%sg9cw$@cB1W{ zZ717K@t6Ddo$SUgCPIJg?C4wXee>Sw-tSMI>i)93v%9PNNOy1d(eAIhqumF)_ksWY zXWjqk-rs$o`}6KEy1Tm%bsz5T>E^rpy8FA2bsz5rHy=I$?B#nWK0Ni#sUOe$^V|0? zy!+jW@4g%C7(6?82?n7Lu1xJ3Jv4eazIXr8{a^0?YJYS;7!CIK??1L5oViaNIyH9o zFC(qJ;GWxiy!XWUk4IiR!JqqJBswx0@9I3-8}A+K{k~T`d-VMKpge!4`R%WEf7SHW zTVK8X)t|n4=bz%&2fsNx^k&QVEn>^%mVdSU(DLIKhxjx7@e^Oem8t}|*zXcvzwpte zzs0^EIz4pe=(k7DAH8sN@M!GlrK7_~hmL-C^y1OeM+c6=6^`M-qr#Vs{e4Hz9Y1&a zjnjQ_sGSj-gorS5{_6`zE}ZyobYS0L;~=QQKie05_t=*g-s%0e_v_xXy}JbLM)jsqS0J3jAd>uB%j==iwf zla5b2KI`~LM`uS@$KPXp{J|6b-+V5-e<6NJ{P4REPk(sk!*4%4`{B6{g%8hvc!597 zpYMC~_#aRF`NW=YI=}g0Uwq%_zOjAZ?-Tc3-uJJ4KkWN)U!u9O`L*U<&967V(fr3l z!_mh6$k&74w4H4__u0A2!U0fY9UB$KF2XgS{Rclkc<|sCV3|9~_n$x7E_S@#@u!Y= zI{w`8ZpWUEy&dm$?CWTT9s5DYUpoHU(bDl@N2H^*k%PSl zj~@K;;8zFv(JnA@Sy+Yuj6OwpFsFCc%oNe`2F)|^;|@3g9oGg zIsE70t7%uO-1Fgo$MN&LI9&Yxc={gOqtE;<*{=g1mi&au2BAAY4IJNi=k=L`Ct6=Z zGTYM}5?>rfHnf=Rg*HGRkr73Gi{q^_E{&5EpH`7fkSe5EveDh8|ESLR^m^@j-4dN~ zJ9vvV|8IGx`~Oz=j@J0}f66PR{u5^7_6Xp|`4j&~+{W!UQh&Qr=ErMgs8(sPM$77k zqEs_NDqHX};fLSFD(EFx;II9I(S-i~5JAK-1`(Fl6prK&!+1H9niaBH?kB}v-0~z35Y<0vFz4133hzCdk;;jx}v)rmG zCtP>g<>f(|@UVn$F=-_{zQq?Q#H?J{T`|LgkiONfdC4K^-%k5!nZW8u?-HHbw?a4A zuWy!dDfZ`;GF~DOZIdPtU5fnSewmQsmHAk$RXd)iKSBx=j_Zc{eT$L#rvZKIL{7>n zI5ihfh;fF~H#@YXm(?P}P&BCVEtZ*37ORtaCs7)^RX2D{&-oTpoUgTI+M#CBKDY0pC#8|augg|wSEwf` z*3T$WAby2bZzqql$f`RKNmF%67@F0xL@=M?WddS+%`CwpWI#s{L)(4LVrv>#$v)k3 zG5w-a_J{chl~xnCqd#y~g5s!G&2|&Nij&%P{3>*BYB|b~70K>SB}*u-z*-{rW@e_$ zNnz2MtPh2tw_!?nnMR={704)qx=2pmA~wU@B#|q*=eTU4n#kWmrgc|PFUnp(YG(x!x5hpgKxjmU=Np+{ zEy{*{XN&1!eP*=EtyBXtp#~`jE3g5Hbun2BYQ9;4Pz7Qs(#%Tx<&umby&l#XjNjr{ z4YH%JnwM+ZSqRVY!*2)7n-wtQF_YSryfjr=B9UDrB`K3KQ9gMTG5Y2_| zh~Ck{>hEDuHLNOvXNn6mQ@J15-7Mlslfh2dNmXVhlJ;a#$DqaU`xf`eX&P!Z#FF*> z5cR!3UL%Y~9&rSfurOM9yfyamw&-D9O!%m-Mb4!m8BcH$@%A_+NW@>q84Cq7ZQ_hD zg3Duy=jA&TTsq88Hq@HS)12O($;14cq#Bx&*CTO3OwMI+XotLB5kg{FjIhgjl2Hf@ zH-l3qS48Jzxjn;PV87Ll>N7$Q$yv>6`9&!*r`boOQVZ?@$(v8Ga664 z9shDbHJ>b2EtCuAUCK}M>}fZI7VB^M$dTxaCw@J0Y6ubZC?fQ&OunLrCO; z7m}Q1hQvS~ZjS&};womS4b835LydoprM$jI& z;Pk9QM%ZuGI$fJ9#aZM0rF}V#1Z29j>d}XGLz;qz6Xh0WGh$-RBr^y!;3J^@?<*0q z!1!2f|J72l4y{Y2qe}ee2>FJ`yW0ypj}AnPwx=B=ztf@an?7%P zxv@6vp!m}Au!D>;hV;HijVXKy#0cJ0u9+EjDBulg{NqMhwAeuQOBuajGGzBR)foJK zhb(%b=05)p2g6tS0Z&w@@jEnp3L_Vn4NnwuZBlW?u<5A_+a!t_+V4o^(;#K}aE1+q zzxMC)SDO&T=MEuea*L(e&kPN;B1F7TB4$@TLifuNG^U#-Ec4e*82231OF=_-7py4y*}OGjOGYz4g~x532>5gOsfCmI{6Y;stx(Gs7Z&mB3JdwtLJPmFa5jHK z;Vt}4g>(2!X0H#=KU?LjVrfc9zBQgz6O$pEeQ>~8g$y#Dt%@i5hyFEy7%>TPoHXt7Ox+hS{k)gIXR{H{Mdm=lQZm)9$|H#NAfu*$3R;mL#8Uk*zT4I zB7n~#H|M$Xra%ZjaATXKP_BU2TZ9aM1*!7~5s%EJ6j{44Xw ze3F06KTSA!zg4@E-=Ynu6=r#3Jh5a*9->V)`;*q-j5ZfRe!S-cX7y%jMMoUerQJ> ztGlaildZuYv`E6pVC5A%Eu2hzc4VWK3i}@%og~!hr$PZoR`j(E zIA_%ZGBGhK3mdCSg)+aHqcyBH5Rr$={6RG#z8GWH$BptRP6?{z^^|z)PzsDS$*CIU z;#={1ZOZy!8S8Y=E^d1g-=r*=_!;0MLQYN|hB~3<457z8G5Q9DhFHDE zyX+Y>V(@5@=D%t&r3wr|%ugEs9F+_CKg)&3jxw_-pmuR(vsB{BAq?5;c!|feB(G;_ zdAP_1ZzpZ8pczgjRt|Zbl=N+PKt&!KgIO3gnV#r`FrE=)LQ0hGexm7#bfbw!CikkM z^<#Mo-sAGD8ey0xTmw{oMwBw9@%M4+ryHx>t_oTTtKzQV`#2**FY~NY3FA$5P-e}=fjDzv;Q055 zIDQ!su~sGUCpny+lZ!XTrSpqivOGnv#HKL?l2l`fHlLftm2pKLx%l3&$z|1@q;<*9;HURI#z6$KM{dBGH3m8a%s3%07|Renc4KlMtexW{-U z#2hWU63Xn=T?tJ&qP`N!j^+yf_36g!C|N-As)E$$#44f+(_1B+rKC{?b;1K&4OuV* zCmrTz#a0zZtl!o$8RW+?<8@Ky%08cSjqdWp->pMa3wxUYvno0hD7FP=|IQI)WcVDL zdtI;$ZDrxqbHRvc##|ifz1bi?LK!9=$z>|+sW!QA^9<6EmW-vqIlSM6^5j7I4KQ1w z#i>c2ZfM{t-kV2$NYX-o0ue3n#99%f1P-#mCMiK{FRDo6gec=eQbaMHb1n-Lu%Gh? zF1?Ac3m(R`2;PjR$)95K+na(-PKkoBH@Q*idhIW`>S?mxENiBXaKn5sC|u1*#KR*@ zEvqDtuhb%8i*{TNks816kxr#}Y2k(FrGXTt$t}1nCV~~99wu22Dn_s1(tDDn(J?3; z!V-+sco|B55tZ2#RuXE#XX)$v5y1ct;oO9P+lP9An(4iif$IB}HxH_#FvM0ew-eIb)pCUFyP8qKpN<1(Em*2YRg{!|7%&4vfT!| z0JjO_B5lZp`-s~iw^cY3O)Wsb;G1P~GgJ{Nnw~7TtNf=8nwg zGMj3?t6?*1G#a6F!$xA0=G%x7%B-Ycar7RsKesND%Ypve>>IUU=Z>>#PXN^iBYxoPn(8p8f%yf5d@x2Ow(p(6s*-uP(M?{`2>hgR z0#6yU_&mW>V}u>Ddvs^b7&B%-hZ+MXYw-J2K=8(m6u%QVJ9NnS7_)_0jpHXFKH*T~ zV_8B0Q)sd*+qewUdk7A`1!>6UO}nb~q? zz_aD-0H&8NpgpnHTrL%^PbVyy*mEmRxL%D}<5>yCasYc;fh2JfVy41#b3g&t*JAv~T`9aWb@n_ax7oq!Omg{5VgU2Rm>)*w451RncN&cCOhYPfHl*-3 z7$p2n1|`4FAO~$ppb{BQM{(~+c=R9_j3r9rW-l_ay25-3uMo_@!Jw!WbXv$5i;@QN z5bh1`71l(_xl$;R8b_c#GSJM7w)Ko*kWVve4p-=8LKT!%@m8HgCCP|IQDF*?gfz~r zWi{2hu86Wgd01wYAI1`4SA^9mje~&O2Y7KS&W};%Y%Wd6;@sD(r&5Pe{#2ecW0{OP zOy*DLk(t#MRTk#K9ygwek^%xQ+vIg8Wl5Aj8S;Xj!`u@o%tKM!c0FHIc?}ozpEO}y z-yen^!I^#<&P87{WspP}uZ(jiB|pefrZ%F(AQ_W{9i&renVdrFfdTei7Pn_DIqm2tC`Fi)PP zY?O;++{xKi*Q~Lz@ZRWOEqM%w{2Q^Xt2dFr4OEZNK%XRG;8S->8kHguBOs)N(BEPt z>`TO?fGm|^%Po_Le;8u52^hCjD?a`D;PgXY4M>>P+BY2U_QXw7XOYn6_u?dTaRAO* z4PqpBflP_l8PGOM3qrBv_~;krThy_E~UJ%Efp78}@-7g^k>b zb3F;zW6c;B-YapSm)BXhxBQ-al1mL0dG#jbcP|6(IWLRP;U33)^viySzLNZYM+f12*7jnmezVUSb)|&8%YZxe~ZI(nAJTO(FtkKtGEgNT1VQE;#y{d zQ^(REfrWj*BQ`qHq5RX4G@;fZ?frRbor5~OLKlX79xpPg_$gMhfrQbaj5$$4IOq33 zuhhfo0vS5z@7$hp1)?98g~)AWh^&)^D&SpFN7&q6#zOi~=yIkba|TF^D?mG<5|53N z4Au!@+ExuTF46jAi-OAtWpImJhcBMmkVe|9mMa7!b%7{?*BM|vit#A(YNKYoec0!DTBagKR&Jhku@5xW+=flqYRsQ!7 zBl0&MLgxE8&Ew|Ec#$MOmsf*);KDuCqkXoubyKo z6=90O{g~xPA)@jbZoc5DWQ-GeinGj|o1fo5v#i)Sy$`pYFc$Hwwu;j~Zq+Ipe11i} z-*E~{SJ11Cyxd6lBSsOn_(_lzs5J_xd-Et&#F*c)Vx3+4m?DgXB?7BG#WO-YS?3f% zV$6k7s<84}ITe(tO+AAF7gtQMz$okoE6N+&2no#-jx8_CtR zXq%OpQFDj1!M-}Mnr!G=odKzsQ-2mXb#hHDdirYmn!p-JUn394fun|=teJ(SDmonS z`S}1DS`8}^h4VQ)zev0p#$U!~)JsEzM;=Ot6;&Z@^jrKA4QaTc7q1DQzdex8-8CEM zm%kiOj1C$&&n!h)`dB=FEno8((XbI@hV?~olTqL+BD&$}L|GoIOpDp%?9@;32P^EUI{f|FylS8K<0 z#}gk6D#C{Kaf1Wo*S4B~Lw&8zMgOr*?;$5AS%VClc~d1w#gF6GWP=U{c#-;e0uAGK zz7F+B9}hx`F$o__JUOHQIn@t+HYWQ_LZ9oPW+TU1q+ta7$x5CGr5lmp6tek7kPI?- zl5ssT!Wf@G%&EUCog@q=>(*?u~U6Mb4a-gO%56*l_sHvQa z&pc-8B|L`F8qfuR#!kZ&UjkjJiM0ealBSc@BPMdAKG{n=Zn&PY#IK;1!!R~|mk^4# zZf{9_VG1{a%jeQwl!a8{S7Ucukx|Q|X&ZP{paD5>LVsE2!3bg~Y~2bMapbGiE3%M8 z+y;170v;4D%fzt#5i{spHUS-~gVtWhL4JUu@Q(u-1^RyJ4gVQS6=1m^xSwo+E|}b( z`#vbh@tSAnd*`i6@UtdD=ZAie)V2vfi@;dW+UYiSvjo(W_1 z<-n$bync$=cmvJ>rND}EwKt`Z#|XVC!tDkqDHI8e05+gxUnfJV8Zh9#vbt5;@&3BC zcpM~!2-Os9(nXWguRF^|pQ=NQ$s`NzihR&%fBZc0MYe&Izv5_Ta52T7Y^* zS1+`<#uD_1AGpA=fhTOFHwUaaq)#ed7SX<#Zk-sdZ32(XikVUN}&g-^+-X`IpKIIIY<9OJn>(HvxMvyZWdY{=tv#`z+1>{J7`f!)uZOOOenX3+*`Y>y`<-YX#7*2%b4M(!{zX zGBy{#8^DQNh$VhMrkLbUMJ|8(&S>#AjzzD;(748zk<2P^3FQg`|krkgyl`l zYh4813tjosw@RS)En`UheNw(1Ykhoyg4?@>GJ1L6Lbu=IssJAUM*cx7?Dn9^uQU_% z{kv7-=R>6N7d+#i$txdw3nqzoW3o(4*^_wiXtd=kie6QtxpNUqzR}* zCRmm##j+7BH4OHE%mcCM*J82O3=TA4B{{;3rKw6nGBsUlB>OEEB;0CIiW5gbSJiLi zEEZBQau_0ok{2T%IR^S-%@aTxKt&p`5U9l9unFV{Y)PH~Qduf^98iK%ygXX1Wq>;$ zjH0Q~9x-PS+xU04pkkd3y+Xc%Anlf@cD}F%WS{7FkAo01$TSk-*T6HG`N{K1M%YX> zPFX;Pt2kz7nJb>SVHi%X5HiYn&@{ZJx6O35fW?vo39rdJ1}#V8;@EeaNyY>_9f|kG zVgt-$7ttHPF0Gq5mG@13~)sOz)OtD6s%FcK28>bgqu{KU8DvqVSUrlwCu4D@$%pk| z$h`^d^yB$R(LJc(V1~xat1;A()h9^{sK}b^j3l{Ve(W=@7P%<9IX~|3~t-BMB`5==($Q#Kkxs%Q4Vc zTyHxEy0S$yNQWj8%dy4>qefV7Ss)?i@zT;X=FK~e%VrmGb`p32i#gw9WX>;pdzpI~ zvrHzsMhX|~^v`rzxbR{lNG7-N#?p81oGLKecKO}g?&FmES3UL6wtmeD?Mo5!QzhFb zWvL`%Xv-|JYe&jgWgL8SV<@&>wT#6{jD6qGT9PmM)%Z&|Sy(D75(?H18RO?IVVs5GZ zbu{nxR=~IlFt$2U`aRmPLv6hZl3*3M85F4y6cmVz%%FF%;pNRzg(vP*$rj>t|GhN1{hEEY~(8JwTP^*p`|XX zYZZGtE47c~RzMpGXye#G0&FT&Xnk=8*c%^#-SkMbTDZXr5UmV&y{>}19)>Fe4Sbg# zfgSjlgB~TDK3C`}$hihrLOz$hQ%^E7u{@cs1c@XG5e(er0g@>bf(4n^@*~qX0~p>^ zpzIM;T^Sf}A;@$JrUdf+8&(1^8KV(AKZ9uiMuCl>-gn}TwDS=4_~us8(HVxR#Erm0M>hq>vq$)LTe896gS;#+OTSa>i1}x zhF?MafwN3En!mWSZrNT9#@3lm(5ya48-u0|EY0fZpr=+@@41Z#x;Nl-OHd!ka`7@)sj==H_W_@e@m8=Sm)wP9rl(tS zxD3sWf;_Z36RBmeV+r6s7sX~|q6T@0*ukn5VVQV+Y=)YI6h#R3YizYzfpbB4R!kmJ z)T2zWr$VWGh>^f=lgU_7jMzcd<6Jrjp?VTR>KOP&70Qk@q36_p&w^E)8HCVEopjC{ zj^BS*fK&Yfd5M)gERSBls)^^2p4=V_%T|p zPFcM_ShIRpGYU6S<>5VT5N{P?_ssdXtkCqxZGP^fVI6?rmW)PrYf-b zZ2_M3C(tLwP4__z{FRK~CSy*BxkfSE1)+zMp+_LJ40h{R1C2oIyM_>vXsvBQr9(E^ ztH_nkkxpg9BIh$sC|F5}IiLZ?)RMRo7okRMvjCq5 z27!&i=sQ`7H4#g+r|uCdS*>u-3hh3J(6dB~UZT!5E=8DE0#0m5*r~R9NzktUlnf!m z57FIA({_L#4)|X+si`m-uJAU(j$*wSx_9(OnhNb+ienNQ>J$GsstP~rIMPcN7QwlL zEj5%;7bQb!JD4&e+_ir9(h3^dBt8%LFtox8nlCRBUm7i=De!to+tIlmr*9oq)k98@ zrLlJ;6-J?;jtD>J&>m5Qf?mouc!FC&02T7-*~4aE}Ro!P8AE2WkI@9?5@%g4I`t!V3i=^qhlEwx2ZS!kGLV|9{3e zUJ@jpyUFAz6LizvsNM%&!73r2Ug6EZ#|*z_sNe7Sspm@WLiLrAAFt)#tw!}0?mw4& zeIRMo*2!Un(UG4nq0+6w)$#2f`cE_e-q6oy9*=Wmh%A)$DC)7LiZaNf^Q~z+Y9`cF zvKll2)z|2r0&9Yzz6NaC^5~+Ur9JDo2Ud&b+G@#xk@RbNTaiU;UcdMJ0TD|Q5X;i5msBhf*e`TCj0^dZ2v%w04_ohC% zH
jDx7OQNX)O0lR7eaH$XQzY`Q@IMqT5ksg(or`4y;Tv54usY1*iMbpXf3<2+b zFYNt*ZjWPPuPh|3?^1)W%k#Bfy0W^+Qg(-Z5^eKJL5FQJNk~?cO-sQ7xyO+ay_R=} z)vK?Rnk{8_*)3%fT4^Rj60jZabx0tO!rZBrhAJw_kY$EK{O1rEj%%Bi?saq@T?j3M zQy5y-F;oC88*kU=L%3Z`vOM?*^&WuI!OD@uXTvg18k%a-({t^tcO>z}u$oRWD}{6c z<7XkqUqG%?LEQ@Rt)UO#)Wfy(9LCOu(jo_4Z6d%< zTr;K=UW!OT3rvci$4NmZilbMxU%Opk(eIOsBOn8lCaj^-3=3;X<3IR+>$2KGm(@M+ zZygi%mBjM7Lj3)pLR7^R;*LSWrY}(hVv$)O3-rY$Oqc2zH+8RUn~bdH!@?8KgZlIxw&|1s)|#ucULRglSDPG?$C4V_=}awMMkVi2gjHj~HD z8afTERVYgW)+4e}0dlL63tECzz$Jl~6#_r4G4RupFilU8%)4$6X!V87Sa!iYS_1qC zfD57asS8G>7pH4@<2OIKO^BC~|xlOR!!uU6LAsH533fE-t`Tna*BJLY*bt%kF>?I8P zMXdcba&Zf^dgpf*N{j*opVBvY#+pS}wU%`@IW8O?m$O!^a92G3c!m2T*n=X-n}i>k z<=jM0y>NlwAebs81{wGp1|!cpO8QKd1=#lmJY5L^<$h;AgEl8%jbI%VSmwp4vB_3gSy8g2T3#&V zTCG6UaqJzrPS9IxuEZ|NCkv_8wkxp`m0ploC0Tw)3NEKo+VsWpz~4Z=@s8mY^|TvK zwh}Czfltl1%$egw;0;U_68t3L7Vd|EE0ysIUQ7%&83jp4=u-=D8 zvUeLnn^tozRUuxEO~J~!_ROp<8txXEXsC6^h!l2hb~)_ZnUj_VX%hU9DZ{tX zt}NiR;YqQjlmsW#RUS_7qAT=n@NUQVHfW6sO34J7txFfEJd98l0T>b51T+?CdO2eD zqvz?K)mwoIga3{((F6Ln#R%bZ3)y^&KZ5&KdKeEGP?zZ=1hix%5goV`7$?@XYay>5dMXze4Pu>RJR!ujphXC@NMF!#lR>__nVZR>S16FYkeC4)Eh0(* zuPp_NdwH;0D=Rn)El92-khz|1fmwVZgCjf$JXgrPDWJ1P;+-)C`ZZrHb800!@Y&n| zobp26sg;>$c_vXxkm%CJ7!Ld77A%Rus3Ic zCN@vN`BadP;lOX!0+g{)CY~Gt4Rx&q_*FG{2Uu$xosu0aJp=qzajn0GT0aF#EQZTK z<2}PQiK?Jyd2s!oj*wuR!n7OL*yQ*OymtPc^fSVAfoPSPNV8Rj+w?c619|;G*^~g2 zBw?>#fyprU->ia12@gUOTTv*Dt2Qe7rPgXjE`BnoZ5~Nfjw(zpmrK+B1u{8sQ{+U8q)*Hga5;aWWJ*zYRQdP{j-%Zk-- z9|_J`J!hFWYk}wbea^i5`sv5k9j6~#J(B~u7OdDPZw{QubD*7g#;#jU=P`WgTx58D z%>=$=-UjdM-lu^6TQl1tH?4opLG^D~AIyX^V9igOO_?{XS*Z{}^ei(@7s}AXD44Y&{z&A}6x-{PmFlDC(s3M#Lz4UTKT4Vw{>+NF|S_EEM zdz|_AN#Vp>v+fSNo|XVNg*5{zn2SFSJOgLf4WMU`4#ne_VOR@LMjCT&pk%J1{;;b?M>&Jea;O`X z%ELNA9@_1~9^?1M|Lj5~9`bYbsWn}yv|~o^cVI)orZepK4vkRE=o zs<>*2I+a|a{(T_Jh5gfC@ce54-`fBg9%SHH^Ac@OM4opXyaHp*cL0rj2j=3|*6g{U z5i^GoUD*WpU{+}RBl7%2U#=j}pVY4~==;M6=$H@i?8I~e-$wvVJ7C3L8_$dyIiRA< zO-X!WYwo<;{I6B9Uak6FZ;Ktvl$NNbbVr!AR9T^zOCDAVve*+<~rbO@ZBBa}`16&=;I~4e&@H+ouVCttzT& zqbHJWbRK=DuBkKCgNnBWv%sfmx3|IZE!5w%>9c{WV}yMlf7dc*lZVG_lfrdXr<}Po zVzR@iU@h2F$gsk=8g>mKn5tyta=L?l4yEj5wOf~WMacSq<1(b7Ftc@H7%_7NlF{v4 z#rf~?Z~>IkSaFAktF3|4;WgrA%?bqGQ0RF)OX#J-ZJO6~D<1KpX$1e2E5&tLv%`^n zl&Dv|wox-tNO9G=cEG))8oz2+_6kZ+?OdUguD~+)6yYg9QQxN7s8PLU)v8xe)6$|A zlXF?#whqk_ZDwQ#$mTWRb577 z$&QSZ;3WJdZ)A+i^kLH)*zb|_FpeQXeE}r23r5)aM}{U|kb@>+w_hHj#P7%Cp&3;{ zux87`5nFIA#z7`63i+T}7NYWy(G;w4F3UGpXyhU5gsz%h%PQ<3R|@j_e85~&W3wBf z%`9Dk#^sY6U=PnWbwL@22B%cOsalR?^~>oRovdLNq;}TKhLVIvUVp8$ra<_2oBsT> zHf_7sCfv8l(56?RO@W%O8ta4#`#4@%18`S%n_VSH83o|)stLgD1r{m7!2x+FSfhBA zop7~vPYg)1G9oP?-K#hTJdSg)&Le5Z_Ofc7 zRdY^Yz>cw**TXpsRt2zOp)k1v+dyzx&{2wikF6?CV*BED2NM#+Vem1iLbCD$fc}ax&VrHY8ZOCkgGn4+zrwG|;HGWm+Mh zELq#^B55e!L`87F%OckcxOE18_VjP>G(orw+KeLDkAdLGdfe8w2-UFLj~ZrZwnhRG z7~>sS13Gt5@WTj(_C$iKz>IExPXm$}EgHFJZW^%&}RoKC5 z(E#3P$x#QtM{y`FFW>E#g(kU_0_JBit;GB+wi$&NV}HrFle4%TW-(a9D#$d@1Bj0f zDnO@=*F9oZ3ml>wgG;c#9_TXaC1GiU2I79l!@U(6NrN=(7AA!PRVsiHl@sf2_G;5; z;=Y)YD}VeRvMPTFRTlg zdB3B+hkzJ(oriaO1CGF9%vZ9oBFV5^oH1;H9+9BMLp{z*a9;>ccs!0^r8MW7DBEaa z4p?jv!t@r~m}y%I7pywzyp3L7MdlH}*`$E3A)8m^HGO^CDw}&;%a)sr>GMOu)A^3I1FF-)@wP$KfutJ7CrBhPwj3E9VNXOKCd^_RrgB z5BQTc)fs`m{|fHs;S$(m*w>8b-2(Y0CG$Po0(S~(-GEsJc50lfF`0V|{#Pp5PDLa3 zXq3N3?ZRneiNr7iTrTjge6R*2#To|cR)XI$#)EvC`LjqyoI+a<-90X=9M1+QZ>Yw29Oi_NxoZo;SF_&JGrMtnyk z)%Gvw(=*^gon|$AAFi#SF$Y=x6cVJ{@Xevo#1yz)fN?g$?FkFu+%j6m#ggs9IM%hM z&pqgTzG_94R!tV;`zT;1n2x@Fx~sCLmz#_`&&n9l!W_)wAH738qT4dazqB{sqIq_Zqa3UKn}lUrMA^E z&_m`cqskp9UlnbITo>S^8^7m}HZ}bSxAt`sJlxMrbu!7T%EO+(0YBeZd+N(^~dcgIJYdKv3rH&8DYzM3H`om># zSv)_KEp7^Uz$WhTEyi$F`HCuN5wEW#&9z{LgIoJpK1<4IIKRGCId=)%oK^8;$&;)a zb}Gf2?CN{;&AaW`7j8TcF&CL@9V-4sy6cvA);*K#m%e$0R-S(uq%GWrlH__*a1(9Y zTFBqVEu>|)LvdJ^yxEqDectD#&;15QBs;~9u@GZ z*Nu?OrGcgh64wk}fci1sXP_Tg?m>*q+GTIArmTK9mNjtOa2iMtb1QUpsGknbX0_2( zgfZ5G({Wk2HBp)~5BLG*Y&8;p1kV#ww18u8VYXtwU6puf7%|NDjPkG(c(tAs>vj~J zaXTHH^=TEW`^Ty$Py1Eyywk-~Ojqs;&hRU)9HK0jZ z1r}PTwxV(g_=33o&dQ}=*WB$Tk|!8=scy_LPCQh`VQr<83u^t_J$`Z*t83q`gc~UY zoJZjEv>NV;@WIF#SQ}JW7FLAi;nBp?BiLt&RZCWnCZ=M4*VP#&LKBEkjiZTT`1b4r zBkH*tj+mLtsa?zs_|9#%3oP>BmDN6Qy9>wfcEQSvdi-4jYLDA*3NCj!4&32U04-J( z&EnE_fP5ZTfv!)5N09|7()H;1=ft5vzfEwmR9|5`gk>SQ# zB$bN~4I9_WMbGf5tvFUW+_+vY-aecj0-ws^k;H~EwpeHNbm7Uu?)u+xL9<>Jvn3!FQL266xYIXIFS8_9;%kM}U9-KbS>-PR)6iobz?dpr?( zjJ!7+;Wnr-<47*7M2Qt{gOM9US*Rh!Te=_{YaODGIpOYPw9H9pbjF){n0YhYsD!?JLZlkNr4fcO#;(WpeJV^wn!9{2)bYB=0{q3+W5TV{Z_uZ?Uy*zGdzrccx3` zhA&2NT{m7wciqft>o?1dgCMyd+tg(jgMZo*PrNxAPn3>~JgN{!Mh&)2KHP2+e0pyb zNbyC`$X^Fs=TPF|F+cbY%EfG$3kyE8d^x+~VCMjzvC-Fz)1$zhh>yfKI2CZiX)^5F zn@1;y=491@-K43C5(^-d2 z25!@R8pxQRF^}D>dPP4UpEVhFA z$Q!%?+Y_7C%0Q0ozv$uWL41aM|M|59;~6=t193Ozu&$#5>ef_16cdW&y`sUmMxzw5lobLCEzMK=bLPv~0rHcic`BwD{iW-uJ^(1COt@2-~GLJk`?T_{E`dD)_r062APQNYb$SA#9CDg;KC; z$YHOJ?~LCMjql5!jvBWHlk1)oe*{e}0^6^$A5)GDxZzXb!jvLI!22Pnk{-kIDCja_ zKTv}*L2je470?HF`;#?o9>V(z&kv?2zE)=5+u(fxRuE8OLZvnLrneqANyl{Wcyc)VLBFQqkDDgYUbK!n6YdL+c+Q~f?fO9?oJU4i~ z%61xEqlwN@R1e+^U?&1C>x+ull(u|V(_)~T;Pd*={*lBd!+itEaihk^?G%g^-oLTd zDYhwA&!_<6Ry5df?)fa}TdiJU62-S9qR$t@?R*b<)xFWKAl* z@iA7{8NoiRTZd8wR6>@Xs+q;@W(klr&H)^+v1+Zn0CS3`0(kA?wqv}p)(P-cB@bXL zie@FTP2!n#7#n!bh}A<32eb@QbED5P3i181k;KJeuqtj&6HqBrYvBHxtmAvg9ZyUf z-J+EjUhYYo3$ao)*EMT;Z9Z4WPIk!o33S)3f7$%m+W)eDwh1^*xTB94rY@HBwZ-kg zW9w_pD9@O8{Qi^9hv0i_C{N12=2YfMLAUoB_yRqTf;T;{4&Hop6<>YQ?Q52SZv$@6 z2mg%^#P@lFaGwe8q;d*#i3L2OW2WTyT!s=(@La`TLjjFA@XJlkBKWoftJB<57h$Tf zU$wp&e?`eJ52jDy7NO4~el=;Tp|Ia3J|Pg;m5p4Z3A}X0j|Y*MKU@Y{%+DcIJdDI| z2X`_?NNENyW`ak>da!Za4QbDURoRrZ*ZtH7mPybtAaU&=x0$NUQ|NH*f(k-eDdX+_HMED?imG0YU=L7vvR$7>IE2JKgN=*@>UtJR4#0Pw;2UNTx&W=i zxRKZkPv@WQdt|qhQR&Es3afCirJjp?KmwI9aBErA9Bn4N>#>`4~?uic@e`4K0;`Tu#Cl zW@JLO_MOQ4jx&9z5Kevgl7m7ZnZpC^(4T{&E48mjWK)m#O@P^N9{DsmG6Z;lb|XA* zx54P-!{{(DIPPif@QFbUB)oqZNQ3>EZq?h$oig}lV7Z%g z!G|PC(nGoACaInB9B@sNOd=1!TWUYx3HW9Bs|!KO6mXO95b%9Lkkj-Oi>-euo7_r* zEL!1N2r?;r*CP3h4cvV<GfR4H@)o5{R?h`*71hvPRS%RCu>Gg-!etqdy0 zID+ws3n*r*!}ME|SQf^OD#bCqm139~em8u#k+B3YEp)_FY)sj+ z$#&ilzct`e0d35{m@o8UoU`MyD`nz|f@|$gnMakp;U-JR`^n((x%Gx*J(~DU$-Yj3 zzT@(fpv-uCQsz^or2(?I7`V82LX{lT=42jprH7+q#mTZU_y{&0Q(voOAz5-uKsgUu zeSKrHjo*xokLjhcTatM%fR7B$n{Jgb<<2e@S+qnkzD_Qi8|2KzGtUPQKYu-gw|S>qsM3~J4@oCJgM@j zsR7q4_^JrTBMk3xk_<})?0eka`><`?`w-*0e5KV{$yUo5q-b&*K__+d6?pGB-1c7s zZ?5_rcuN9NB2+qy_$Jf`uM^T;Y?`HEcXJ_R9gc zp9 zo}yXc7s~!*oJ#Jg_>fWP8rgoz(qR{j_O)(#(+KTrTi}FGs%K3#EEp}KSeG47M|LSzA|Cx z`p~q*`~!L}tjtRaeP*Wn6>J$XLRDi6Rvu`jVqDuzk)!V_h-9O zzijZXZ!`*JkY#t=YFo3nZ(m^986#&~voGK|XLAy6?Hb#f>Ab#n49qU7GUUTb#_YxuPu zRWTx7s^9@Kc}g^K8U>A*vTVg&chTx#XHbmx9EQh=krQWy=qeWn$$W7EF4 zZvu}Hz4M=q{r%2=Jwf%2!p1zQK>E@>qP1VeU7p%i*2wW?LidWNN4~T-`@&e>G6KzE zU{^#00#14E^RU@f3GJ7koYegJTnD~)I?th4qW#(_9}Mk(YUt7R!0Zr5?ipgwIYYoe zmJ?@jcQ)LeWsLQ3e7g`?QICF0zl~AE4uJV|xk<|7Yzmvtjh4HtuLKOpQzHSJcQNCR z5|bMmZ3=0d((;EHce}eI9Q9el9h(bD&0o%q9;f&4X@3ituv(V4EZcBHbIXCgkBtV` zIz8o2x>sSN)b=ph$0j*pvq$Ztl6a$sO5%-PchDi^JKJ>;zXNMJ*I}IvYrTe)!u5$SMzpnO*aQ9-#TTI)ycj$xtZN(wSL@MWbII#L#(9E0+Ug-kTN@j>1*Ng& z%hS$JA8y#`7Q^DQrY7$)&+^9FBEwtD8eOdmcy59A?Iy1+NXv>_>;`FUM8CzGf3txv50Ds=I$P_2mSVRh1a*0WOt7{V6k{4&4T&Q z0tvw;oY2$`jGDSw$G4S|o&<-IgQKsGDEgD0crjRbDSnFb3#HT7UPFkl`40TiKD1Q? zzZuHySiX;A%AG|0O{~*-o1%kZN&6m^dA5EvP_D6u8L?T6iKoP++yJA`&K+f(+TKZd zIwI_*x4WOyygk&rb1}y1Bdi zc4{f|Rhvyrtn?DFH_l9c#p?_04^$4{>%=YX-8*6;!NF(UVSlqkx+81CVL6UurP>vQC(M4&s+f=g+W}i6G&z@qHcgEX1IlqqJ|38 zU|aI@cyq)JY+wwr@Kqrj&(+`RunkkWmX>QNS4Nw9kqg~`iJz+D&4z?1uw}UR}w*uRsmm>t;%wa9XvPN6= zjolsa!~=q1i%t2at{h|TC-AH=PDA4fZE4Ja8c*0tW2)LS#!jWq(pYD!8FkY7=sAo_ z=NZ;&VzkDSj5tSBDgRhP--+IyVVd1)xyGjltZ4(RD9Ic}wX_9Q1 z`rj9Zx7h8K{Ovi6xIg$qJ9VmY**4&|!jM#cIrtf$=c4LR$qxGr;&K+4X z^^RzJ4vd3u{|&Tc>_W_iBQ|z$yh?EYSiORfJ(u_Ad9;pSM4}OD>p+|z(BE3vP&DFF zG4ik`vNZA)e-tyvlR%S)SLBF|;%ATrwC-CJdz2msNv9&$(@qszvpfX~EtkM+Uv%e>hJq;TPz9l^@!t|MzL55FkBkE?z^X>Sjb7VRW&^hyU{l=$P zTFNYjZ-U?3N}hWvemKrP%REQzN7qeZWS@bJvM29p!^vVk=bN<{^@>Mf^M7{0L<(c^ zT3&mAT0F}~=ks8IdEp9%R!gz8&tk+Y6ytOc+exz8(W!Sh+F!JMVPs!`IW3fk@kb(i zu-1wm^o03k*ruv1hvUCCe;;cbEl0nb|8#)|C{-%i^jyiIZp3^0zX2Xj;R9v9o){m*)lUe#*N4&gx&T{thfO zz%&32cnG#D25Sbd+Cy3>&of1}lc?IMmGoW`h2>1E_TigB|DfENwEZv!dQNWDJlKsm z0wvyyQ|~+#*FhqEEn_>*fW>dBPs#oJAZ&XO`k>C;S@I-ruG_0#<7$_2@deC3_%SGy{2#M-vXg2DUS2oNOcO4YFL zsg;pk0o|a-+8(DPADXd zr@qz+&i!bpt?!Y9^!SYoG>xQ0>sr5hHE=2}c>i})exAs!tpu(e7%VKOuJ}Rn7b65) zd3WXD$JD_DGykwNtEco0vAJ!h`T5y z$1?d`-=js+OV-}it*aKmcktxo4C$yDvj!LEPRZLdq^n_rxB-|iM396LLE=UPNuN?H zzI()wWFM(3>W!ZoaXSo&S8vn}I!wM$2q?H)Aj^V?8>h&$po!FON8M4NVM$`{$OPu0 z4Ucj_s=nT;a*FZSA3ZwqDn`O9$2&}H?I$BGd|u44ip{=0$~Zno9|QKM%NOYlIEHm2 zj#Vm$ZkTlWfKA(6^eV;~d@Deb(&IaEye{cjwGzLp5JRYzHkZ5#W>e~0VCZiNgIKg8 zNMPEkR41hUiPk(cJhddldSKjdilIHA!H&zJaW}Z3kHLPtY@`+~&3ZlPm(*TPeI{v) zdAs_+1K3>*)^5Z|j84c`j}jv(&~!hTT;o0Ub%M7VF-#^5uu}vqH&f5+24K=ROv?9; zgTp29HQ3uZ!53k817?JGSp|Q+Why?KAg*bH|3?AloZ9i}yLXi^)jMH5QFT{f9-G@W zpO1mlkIrM$@}&t{13hyp9vt5l8A?ybi=W2>YW)9?bmUp$Afg$AuKjykm zA^H+gM#E;oPsisYj5&h2IXD~y-oK08btI1O5WMgzyw@3te|_EuCxAkOrV4H6 zpIYMhm`Y)MqyB>)$eOh~Hr})O8{CaMcHFbW39-$nG%jLT>nHg>GtIV;>EAk+T6vc+ zTB6NPOc-=I<#n?f=6{_)N8>W`#H5zbm4N5QI{3rEyrPEBf1rRxnU2eq)L~M28|5Ak zL64$(U6@oaPcFw^JM&FL zGUNqDGe|hPJvt(qxS*NO99KgR!Yl!@BO~{KEsF`kyD5JUcn*4pB1+)tF&f`%HhK!^ zakTU~SjN?`ZO=e#H*`!yT-{ibx9FufzF%uIP^~&=N;XZll6I5N>@yuv--I|l2cMGj zC+jR}=fMWLuA1b`25`KmWXmM-U%<~n?QM-EwRi*9Oc?cLMYF3HTDQ8&7-S%L*Rr%T zU^^GF3}F869%ax{1}Ue?fXo>r>lhWCjGw+6FXGTkswS1vA{?dTJ|8jLKYy1VRgP^v z_unJ)?f-p_Zs%fK3kJ{m_K%fqV9oHv=SHqq!wlH3!4teTMhv7t?FVOVe{R#AE~fxH z|D+RfYXbjH1Ihm9N0ClAu(lrJtvJ={&GZ+kx9v{GU=(R}Q=V(KHUp;W?u^l!EtaVw6#i?ztgFahRm$QUaDx@FdY^ zro6s%tU~Mqd{gx}YV|lQDOg@LPDemZ&FBzuKC9%o@Tc%q*J&gjrv(S^mD2ju<`NzM zDq;drV@)E%OSv~ZzSL6B`c}U>J5aaN`x-$@Z(Q#v< zrs+yee;j382MzQ(pN#5={!2BHng-==uEIX}?i^K#sb~J_Kh#S?KIAws!nUI4++nlC zaOIcp(}te-yr|gI z^Dqu&l=e69rQ8gjROKcs8p}e)D+nOS78jKlL}_aO$3MTQKehS@n1BZ^AAI90m{ji|Z=g-4c*N>*cb1%tiTJJ_8;4Z$OvfZk6{>5V=Qv z%ntsp63qS`7ZbFF=cnjzeTw#xaK9PeqZv)qf28}uf24JlvDAYErtVtidK1>1!XbU9 z--+d4wRS9H5!>9?;cYw`xog@H|4}g}P{#M8g2{h0_+;xVtt9*Q=qs3o(Y{J;Xo%m; zrbj8O6#O^n&*~Tf=L?P2O3S-5jDlO`lzu%m!hoj~{N(2$L761&$6zdl_Xa-gQLcbw z-yP*xg5@7ZFr^hKdhZ=~!EgRy{Ns52sy7fDR|OOp#$8wzb%=?dhZ(H*4whFV&iY26UKBIPerZ&P^(tB)^(UYr{VlM2z=Sf6VN763c0-Ikg zMs{h+yZw>9kqGCfQNoYPAr#SL(((_})LQ>@g~KchJdLeir$qZx zKlisU$NJN2bFc+n*=NMQZ~oK1DOSI^%T`Epn|^@E$3^^XC02VLG>x?UTDm8qMZfJ4 z)3uzpknsmkwRkX5KGn*sr%Ps|Kd9ei=kpqxH<=nc@c(w}O&enyTliBOr+b)eJ zeD7b+`R9@=aojy2%_WZTt8pMd zFhX`qH<)cqc71V;VOgXYKL-+4#wJH0lu0ZN?ytcVUM6xW!QFkjxEmnRPWvKmwq8{WSdWTO^ zsjc)Eie%AvY;y}@RBukpYr!I*Q(DuKVY5F1){n}}e>?~AIP%ZZ1BS7L4OTFkV<*j> zh%@e+EHUta9m5w=0jn0xtfPNwOpZdn=OteWsFIFC^jTB7ZeN^P^h)5v(>44bA;G5X zUhe+VMr~wx8y!FMk%=k?90PR`whFe%Dt$r|Ic8Z`!iqVNIGPA63XuVePWnhG6C#?3 zXrU};ZafpUQBu2}!lPF=ZJ9~(wHy(MNteAl^`bzW5i)HxsZ=FIvpJIEY=UaMJ zylbnX4FLPh!uFvBAHgDNiFaFx9syRzOzTQIVkg>8nC#LmkrQq1MxSM%&<0H8oiWO> z-fQxe6iDVsN8yY@dm|~F5nB`aMVqhWQ_G3MwXyD)r{orMGL|Q~ylkv60vlrCQ-yxi z*KUr*I^mx_6|>$@-(C;8pHK&^HV$&Ond^X$fcBR)bJm9$GvYm#$?=1R1<19yetMtG?)d|)){IusPx+z2Dbjem@c^AlW@IM!r?^JR$ zOnV-4`iY7zc*x+B%1KV^y3?T^Qul}tI34<-imsl(#|g%34ALvoxlgwLao*&yEL91r z$O&@7ysNF*s!ztuXUHDD6Y~jJ-u<|@TE=OS-m~OE7yFLyVZJ6%mVC$j$@HE1nq^B& zvaMRUq^@qcL_RdVT4Qe zh81lmi)Wy7qgT;xR@ivwc*!B=5F^ZOq-deFdR<+emK8KU<}f(`TlZlGaaD*NKX5GY zSpp-JmPM{GM6F58p~A*eXKAomXjcBWIhg||v`ke|G9X0#0hH-n!_>zOy^?X28ENe} zpP78GS!h?c6M7ahpJ0Eppfa@Qv-a_X_4r$xuAE)!D%1ZKIt`Wo3}GOoSf8w5^*r0G zb7pxv`WXB5N=Cz~md)J#8wJC@V_D$LN<)bABX z`56O_#2hQ5@0`1#l5)*#cs-y49x^%N+_l84wh)Qitd~lL=wG>e+!X9dmiTH~95UG`tm%xt`VvK2HDf#L# z8WTxl+a5SR#l4};E(8anwq_8>+6RtL<`a^I9!u(AvD<6+=w=)EyR=PVaPP?fFa75t z+P@i>9nvN(e|6FcpH~BBzL52kc%OBMM}&>#LK@>fxQVpzA$%JWyCw-Qg^NWb68Lu~ zf$4M^dpuZQtV9HROd_*;B@$H`ieq5K-eQ`b0 zB+F4tHf4RMKA1FO5Ig(CcttmjF9*uM+s)-;>FTs~t3_Amg(k0P?kVfGc9nxoV143u zUh;t6aqr++53tc4XT34R?_(B(+%&Ac5d0X`$*ZM5c%4y3Y>hUHN24+ELiCh)z2u8r zh$bQTd?hxqHhR0LHn&E7mTs{(I$(B6Oyv8~Hw#aC5E(D}B7ceg$UJ}}z2cmx**shr z6*omi%Sq8D4K%h!OGOg-UX<>?O&p1~neUCBC_E^d%}&&p6n}>MQm?^m=3S~q_c!Wm zyCc6?(*+x^uOuR}U+nXW$%xSvUDK`XIVpbM`~4ey^#gZvi>cj{;ceZlON)0E8?$w3 zUvk&mx))xs;q9zQ=6BUNZW_$*v~{_`U_y_i$K8cKrhO^Dd$DBg0$+RLS#O1_E!45* zHp^j;X!=Fl(WnNDq!xIY0^_^A{}vi(t9a&=*@8%Li__BGs-TwWnU8=UM3bazhD2|) zqtMc|&U(s1=Ua2fOS?pm&sy4@-z7qWr*A3J@siaM%B2W1Sj2OXc|izi9LJLndkG@4 z&B;(3>@SJZ%l8!i;-2pMr+XSr{X%ktwmFQa%ew3#CS2Bu`A;}s+UQZWneFCeS*JRj z-&NL0XAb$@0&u)OCKhd_KIZ=0Ytgc;rSZIu1INy0q8yZl85Uj`IOQM$aF zahxCYmE?C;gZp0%%W!_TG;&y)ft;3ZbL$$so4|szQ!TgRi@Wsy(_Oxjy7vEQx%K~R z%eALUyBd_1qb*j7w^(r21)l`LC|%|GQRqb5T65`vwXov5I=v!gi_NkUw`iy<#i^> z|M!U#+F234*UcC+C>IMIcj;K0?tiFhUmw*+=J4F&`q13yH=-(sc2HAaj}eD-uSdko zsk@N@8&ZenY%ChrN(De~k&t@FW>0-+paC)TnDev9aS-%g*yXDi5plx|>75ItRo;yJ z*NIi0V^MXa17*IF-j0u=-plJ!2jnDr7np3&lG?;*=qRFF%Z8+AYxG#uZ{eaVt(1M2 zWPgcBEP5nzb>K+weslHVRHzr3Uvxt{r?v~RC(3-H;ooUJ5Xf5Qxdj2VBqVPUBG-oMC{1UTKqW+x$ zEy;V*L?k27IP{!x?1t)?Un^#>>$}YN9ny&COtP#@BOxkk6?w&g|;;iX*Nairq>lt zv-F~cIttxjFoBI|6e9}8TKaw|cY*S5w^6>j@}{{V?iyxRMRM9Qf*ic;tb)XS(Yom4 zh5Evu!yiCB;ncsQ8Rke`a~pi)6ONz*%u6c83)fe;dQOt)b zq4)GX)(%8lcR+R8;q3@CCbLC)XNtyvDc@l!e2y9UJTxD6mviY_lNlHQe5=4r`F7nL zF_<0$hV36ciIh8mWN#jwE$P0sWW!HQ%nM&HdBOCv_$~1I1^G=kvV(f% z2z{3htfsz_ePHygjQhYUj;|Q{7xlBVaeWtqa)NewY+{bWegpjqI>{7H$(e*rr9HP3 zjKTg=33t}nYe6df z*D{w1HPy_!?uE$9vGA97uC!`qVQUGtmiz~{Hd~(yd~zm>eoN|R!v>tc>ZicG&{8(B zvIJvK-Cb6G6`A!nAnCHldm#Uz)56Qi!n!HOJyuO<3d2d~r0~sRgr1%>FRz5%As;$( z+Fk~{w=M|=KjZ_WrF!5Mo`Z++jlh4Oi3i9KM`wXt_V~8SzYX51GR`bW7OM(o<|fam zODf+_Xls4enXAdn_meA2Nag4`X@sf02#&SS6rKPUSW-s1%}){9W9JY-z;p9*?V3T$ zJfqz(_yF{A8jG+-@nuZK7cikp+)*{MJXS%Io{21vv%#J403^*^XxD2nieH2O>#(kt zU=La03tfX+@T{ThF4w}M)crr>hTyAo!#+qb6GKE?RRNyVV`W1*p#uRq3C7t_Ug&$6 zMbXlAB{JSG-kstnpq%IBJX^VSIKP?<=FbMlYu5<_ypuHBrgsjZ8>=$1uD?dw1-u_Za zo>KBdr9{`=T2jM>?|iic_!@_F&J7$)4bU!_{mj&YXYl0xKI_Sc@;PH6skSA-^?+Pb zdC1eCIeVmVlLayVW;ggoW%=~vEIyyxU&zkXzgtax^SGm(RxIJ&^jM8uviyCpWJ625 zW2dz*PHp|^5jCD&JzMu(1`Lf^jCWm`yLradXFZDb!x>;}i^5ogZ^d=Ah-PY!WJ(n+ zg&71to|NyQ@r*{G0}wSbsD~en<$x?Z3$&<2k=?fT4Dl2WH+7h-G^DS&pJK%Gt7Y( zLjpoVcgphoNkk3Z5wa?lzPi6+ByvDclt-Y!B<(;zZMK5-Xce&|=EX_3KN!jOKgW}~ zEPp+8nG$#n3k^jDTGP;KzLFW_=AVgQRjD0zS56yp&(}-EeDk%&nYqJ@=l{`6eTrw| zY|SS_yU>avq8!1XapUiX(3Ze!BE}#586ISuUn|0DP)F=@!C%n=4RZG2lpV4K`eE@9 zJn`c95k|-WH~YiMT(qK^<^}|6wlr~+2$6P^SNvq;)0HvUG@DC)WTH>7RurKZ={xrX z&LR5#wDK)p`To^Gw$eU4D^xv8i%9BqB^-YkDDTpQ&6O|J%rYbk1kIcW{RP39t1p?{ z*A;-(eqBkKUW}LJsgtu-FXr9XYG!^g#8fhgnpvN~M+^2%VO>B&ebva3nQ`f)!zCgz zPC$}_gRye8yHcB|M5aP_<=>L(D%YUeMdsETtOa{bfBdHwJo}{<{5@LmFXo+SvvYBF z)+a+b!r_uaw$Lpe7T{cMe6;W2phbf@hSc(!uaTTffL9i#&tJz7MklDckKHZ`V1W>rXo6f@O4m2Z_e`Y z23h{YION3m_6_ZZ6Zt0$KtX|xX1i`r;Lk}rxU*#W(0I@srutD0^<5#Otzh?Pd~C1- zcC-%o)HJ@ggR{MJl_zC@5yN}{cl*0BR}+Jj?InYv{zc}9HhW}pJ>-Q6S)8c#h(-`s44WIvA~s;xAhCvgum@+r zXwA5eJ&O4HP9pftwVQmakF^FjZF&g6EBatW!w+9&tkR!O0;e@0pPURz8vfi>hRY?e zJC1%8CE2UARjhK%a%>e}m0QI?n?r;U9Z~rc^;+bJ9+wRhk3oANkv&qQcPX^xw~GcA zrWT0qY4&d<^UisSSKN?8nCw&I1#_ydzven$;HDMJ@BG>=U#SZ$Ewul(tu?7WS22$s z5gj+s@@dyLPa{{^Hztke7TUj-Tx`ENS#Q@TZjnOv)ydE82Kd{#NB?bPk=G~OE`^1) znB}U_Q{nVfEKG-aUL)S{e16NC-(0u8&&^(FriuW*5v3KB} zt8=0KEm+Xd0IQGl-wdQd@;1B9fK!Ikai9FfBGH{%sO=tDBE`QS zFSS3MtT?x=kv+U^sSA0TZZBaDJ-F0UTqux3^sW3PmFKFQzhd22Z(c1twEMBYgc?ou z^-0ya9gSu4${wRfd^cs>KYV21oi~T;?GGjO=PdR$cx&?#Z{m&JjW@OkGd<$Wky7$= zsTRC7lFdwPl?1Hy1`tsLmQ^M@ZJaosPkuP!RNiH9^x(*5u&!*byVdIhkB*iy>^MpG zZ)2}WQ{}gKn?pwfe@fmI)@J8{6HQygoC`nlg0xFwJB#oi33p2#Z^ym2H8PzCfyZ8J zjonK+oA2ExIV8XL?Ry))C_jaA=H50*3tQbz{CdL=Nm8-jld6ZtHb}8bR_<2m8ZXm+ zG;m+i5St#;X31Eqv<4_r_am#Mmt!j>w&sR&=fhu>n3|>MuJ@7}vXxCTH9FueG0uSB zx91TL)>b4^^0XBA1tv4#XYomH@QN9sH;&0ag|(SUF5bIDqWIERCKpI`9%Qkc{SrIS zmLt$nlR@s$InWztg8`m}r^!jJ;=CCx=Nm7Sv^A#T?9S=Zu|Uq*-uRe&TMB5M8s^Ng zfbLwnMhgp459X>PpX7N??$k>v?>oV#M{<=YiL;+f%}Hn0kKQmCDi(N1vwAbpovkB zuSWPDIWTo(9b5@m+Y{+1f6l*0+#^{1dxFzFni%!HP|r)VP|;ZGqrMn0>G-H8hH)L% zQ`Ap0kRfGQgLPvAjTAq%iCLd^-MIk!Ha07`h31WjVGCkTK7~iKu|85U6^E1eT3Ve> zU&>Iv0ajR7#0D|8c0?GhM;#2WAmqxpDt-k20_Fx8%!8nNxyj)U#04>P^6K+==6Nxm zgR$x}@FwKC_r^{2v3M2YF)6ZcQa+zrz_(fj>!e&ermU4r$|ZEIgqE46)=*Y4c0KZ3 zP)h)Co#WJ20UR9WvR8Q)Bl2?bGL7)Dac?>(Ja0?`S$xyj_gk-&LL!1kH5|ZT&e> z{{Y+H$3F)<4IS6d{yWumG)q~&8J^2%$Gdwq`+U}~JgIYBLS}kI7d={E-x1V$Swt1l z_g9Z|sSaQT-pu5+KG@xbj zFjEoT${LF`%JoFAm+kj?AL}Dq8HX2WtH(1}FK6a7AiIHi-Zf3!LTYIP6JxMv8*$tR zOGq%eQChroaidwV-TNZ23Xm!AeBLZY1?clh(c*C24*fALZ-NJnOV&UiwR_F=r-Cm( z3X3xO!A(*m7?9k%`#QppXZMc8u95P2PfHPUvw`7WIrB!G2}vEIIa)Omv^b1Tz3sry z*KU8@z1xB>=Fb!5P2x2YVqJ=mJ&^Kyo-mk`b|Dpn?|PRHd~Qq+SkcF!4fc%7IcODC zk}^IT@hffCN-sV-r(?ms9Zw<>H8T+Zj}by>zq#_xX@8;PY6$poRUKRVv9Vy8dM-K0 z0!jJ3Rw7l#$N`^m9cC!7wie97*3|kBTFC*-;ZY9n#9_7llcCUMTuSazQfK0mbGv8P zH?XkWYxuHl47K3HUT%=`9xVy43PX!V)GNcOA1w;6plD{=s zAEX%jIau$+`gD%lH`_Z;fJO1NnkQ0yP}<~E2RCxy9V9Hbm)j*!*|3+}LsW#}_B;2$ zCgXSRuK>?QH1ZatdsGZ=bmD%UVgDhJHhO9=Uq^%5EUSC3(vPag{B- z1n$O5@(UA2els$xZmug>cK6O6Wd?zW0$_AF{*t^3@%fkJS8&|dC&YMYW18#PnK}L) z{1auKqg;#Jtjwpt)3v;$X(3;6wL3<8SrKN+Ifx#yqMdY;j#k2zNmu4+1(L%-+j9o? z$zzVz>1fXitbdAi#P98!=C!w6X-`M1w5cJ2XF|@u?GXk`%joM77Rwo0?`b^ypIO}7<>wz*MaZuW)P6z7g7Rg^grT4f!6v9Yb7^BUxpQ49Uor1VqHft- zGY#|UisU8v{Ym1=K?{8YPp+GQuOF@O`^kCuEk?=tNip8DR*}5i_{gHm*F{zkA26o1 z8W*GFnt5k6S2M04G#F`J$#8r>wwZ*wYIJzG_`i_lRx9mWy&GBIhQY3$8k#kG_npLL zl=hjQG4C{2Z&_!3I1H{_#M+rnIjf0lR;4!SGY6n^gpX_Pq};Hh7)SGf?YBqzgq$0^ zetLKJjx|Jq>ldAotT0uwW^6l3IFXKu6Y}j7qsQsD-TNd1jDX>3-M82p!)aU7>=3Dj zHDY$P_C-ZLXOHKBiO?O)@g5BPzo0)D3m%GVJN9)v@v!k*zj>G$@^=uaxr5;z4sziv zmDjMZ(!AZTLRKJ-0=+n=NiFImAVYz~LiQd=JE_HIy!0ML#&DYo@z(A@oPjcH57r+i z^_Vly!B~TQ2UD>ty?fMn)+@(ei(~1C%3VG-+&{fZY7vdD_j>n~Hx9&0Lj?E?#$KL) zEh{@dQ7V;sN|)`5Rtx9vjDU$jj7K^=(FnYKEN2UAyjmyCI;HU%Fq(<;y!Zb7N}5S3 zZ|MEdXQIzTpNq;2iuqx9SfV&1I4No{KigJWJ7_h2Bi~qUOwP_Ps5T@&E-0xfP8g&! z#xn&>olz<@6y~#athCawGGAMlyP8yMk~57z$p>dAtc6c8FBxAdsPu0x`84qed6?g6 zt-SpOVEXaCD}SA6!o~vE06l0akr}`t=ru6Sa*0_0~@X#{X&XQ|L0E2E#2tn?sukw>pJDeW_fgITp*o5R#IY zPw06gm;sD)ulF8lA;S?*v)oeC<=kr7; zV`$#Q0oHAvpmBRnH8&wYez`{IC^*)HV{?^bho_F!PRQ%VBk(E14x=C)C*&Z*H( z*DNKo|3JRE_A_(tp;f_^%b41kp+mlJ0bh1c=v)4K!j=53k!P)#iez_=>-45OH@B}N zE}?~JA*MV0uHZ*PhyNq|GPPzt;$yLH=6ie|&lCO|#KqD&qIH%P)d~lFyZp7mzhJ!l zOOTl}k3Z=92$2C7f<8~#fn5(C3e*m&c109kStONG*lyY6V)(dXYhgtNcWo}Ry*3B0 z_lh@DAAW8ZX0wPKcY9yOeo-A@LiAV zAB!CEMg7-HWyRX64^DI5Kg1s<74GJhlzodu%p}H9?GaxD62vJmoKM^1V^BkH#OI`? zy&@Qc_QVO}Jm^#V3p&;Ne>3ubT}k6VCLR-5|FO$$r1w7NUm?CULdPIz*WN39jZ}Uh zNBL53MnOPlgNLC9=#QWa%<60G3UlDUl> z`2XQsOgdv91#_ee!dgp(-Ec-iJP2m>i0ODXBSm`gmTdI<#4271MvXD?wutL=|X!H zzEk1x0n1_uI0@H_YpUju!+*N9*)m*sFF%YdUrLh$2Mg7fTFHremaE&5 z1E~YCaE`})@b8%~*W}nOn#xcU&C~p+TVGs54*$q9RZp|!N=*^eB$`As%)p3JW5K$i zO9k6|JErDsrTyRUgVh1txX6P=F)ASoa9wkOdihyeZU9KZels}U) z9C5*_xd$xA&=YqQdYSLUwyxbVu(f+fscX7ND!K^Uu7y*-XnUA@(Y8(f;%!*ohGqA| zmyn5mtCK6bB>y_YItzL)$-l_ZxgN(}`_%DvJ&W4yC|KxC5{v>q`B))EP@fUMh2HO*3 z)MoM67c<$v?+xnpd4J#f`w{BsfPsOZl;Ze5jN7U|7~)iVR}|dOQ@n|z%DjSevUyC> zhHO`?21{N&k5$p7s<=Z1B-lW#nN$e`Jw&DL*Yyei^1u3Aa{Vs`)7 zyaEWtGpCFv3K&R0=Cb{Q+AaR~a@7~dQ+vlxKD*(upL}-DW3*3;7}Nfz^XOQ|O6rqk z#p+X}Y8>o7^eX_?`BYgksT#xfw*C&qJEez4*OYN1X7~4qTXkdWvkARZ*K;l2tduAD9RRjnX=6Zq=nTo2w{xF?<}^hZ8zaQ1Ax9?VQ4Q zdAuHYWU7Zydseo8X4Cijs&BXx5wlM4=~g2)`s5zfZkM3ax0`u0#h1FkkM9KAm0d#9E9Co2_L_xE``)f8f{1jyNWNXDrk50jIL;hwvlm`LWf!k=|W{VeO67Qt>4D~ zS6g#LguewilBBPsTlAEy6^C{p3!&vUk#ODOq3x8*g4+Agu1$H%f{|m9n59QJ434Vy zl8f?>CxVfqh@vd-PFSq5BEQ>FOP_MTv^_&t$z zZ4$q?T^sg?|FWa@A*qdG@-~Wg(S4jAPtVKr&xfZVi#^K{eOnkuW8zPr**e6}Y;^9_ zy>Mwmq)WJmSDEud*MvQxwr~gbxIN?m_>ACbB?lWsCNwYHj6LwN*elPH1B)Vutw+t# z_yW-sdDRNpIZTh%f-wzPxU>cQ5uOs}VDoC5-E^AzUzh_O=EEh^Li2a53vJnfOmzv= zWI9oDNq%?|_G63^@c%zVZ7`&3K(THy-TB@PyoiVlCRDoJ7rJdbymrWbrB9wL)=b%p zky}bEdDTj~Yedq;0ihybDIyc;m9|p+(y*n5`?b7%S(SG~go#AKLL~}&?|d<`&iY*Z zJK_c`563r%nM%iywr1|olO->#dIlNN{!>|&BtC2-)%i(Fjcssxt);1~_^+#SMwfvXCQQW{$Y<>#ers*J{BJ z2;aa*DdI%T%0cEJSQcxq;*Sc5rAUoK9-F{{o0d_n z1}r%XFFo*`Xn{xJk=zW7_>v-?9FRZSb^~imX zV1jU2)>Auh2zG~@CI%=(Wu`7}oqLI>6bz&WygZ1BfF8p{JXS`8J`?Fd1anB?`p$!{ zfPB-3^Cfbaj^5;;);>N&NAWBF=%Fa5yvQF8zhJRrAw?%<Yv#nS}t?{l!-g?v_ZnCfvF$1jGoK- z8qJKXw0Qer23e1d^#RF1bLsvHX zHIxsOnhiN!solhV{Jfc~e`g!)iK%t?I+w%0=daO2b`HY70~=|I!5HpFTq^6MG3!1d z7r0N`Y3lu<`a=2GC3!FfEVgoVN9vONtJG0yO-1d{J@B9DUm=u(g~W&~yz_uBKn`EZ zj@P!?QE<8kILSQjM*sUJ7Sc%#4dFw4i9z8CdpqpQ! zq=+r%fr0z;S%aVL8ADDKiX~6OnnSA9;2&2d^Q3gOA5o~Hc6zr_ntlZM68zFOzb!NU z8MP8SHYvZM+>ORD>ol3IUNT3@LpjYf+%w*b8LCQ0iX#E;G#7a-Fg+0zrgy4gKd|() z1}Ej`$1lk%Q$gXVfE+l*lX3!2zbs|J2uSrBinhPYnzw{LYfoV49N{iPw~!H|nRd?L zTN+5$Mfn!!V|n}&CGKF_IaP8)YUMnFd;fPkIlVZ@xNa-F8UAe@|CMXAU*YtHj3-FcYrq=={U=;1XEAcpx9^P`ekIG@6Zd|^g;Mg* zC;vPGtvI`33|V8N>-mm2?IB!5j2qrM)_y4NLSA$mVys-zSiCn%(N5$rWfh|JaP5CT zdP1H(eq!WJ4+ngae#jF*oQxB45+15J*vRe~rZGbU@suoPIM^MGNykS6N@k0c+%SG| zgaLBUDA9Ra3fLQb-$3`N9}@W2A0+q30)IPQ`Vkk!mH*|cW3nry{fHA%@}lwR2x5@9 z_Aj3D%Xc>pJJFvm{O|k6wNW65dv`|_gl}kBN zdgNbgTQzy$!k6!TLbjx=u#y0mJ$y3mYGcqw&!-|6()I@ubYw6}Q)RnT|JrU3Um> z={}53-4i`+8F}}FEcd65ORd0$Fphl*J(n+G#Ds;Ud*`hepub{kr6;oE<_q8&4H3r^ zz)$r&vhKp{h(?;$#kzbZ?U4!jkCZj^{)~Lz#D~@(9eIYIlU!R!?L1tKaZ}P&`pU9o?{7~;MUY?=}E~c1ku-+cdgvuNZ-Ajki9n}x!@7p zpX@+OCDFTD(Jy{A_L-Ef3gauEYAJ%&8>K8x|J1_>my#DuoRwtxTcaGVsF|pe#^ut{ z|B@^>)T77N;@)u9L$f1hNp(L9$ug~rH}zR3H;C?0{a=l(Kl@#b}Koe^pKX! zWKf{qY#PTQ;%@vDZsR zUPHDHD&=n+fgFe)YZnnka;1-R_>OxcEWUUqUJu4$UuvaPuVnBjM;^$MI}r7D7a|tFmY69u3vS_}oSV5#>e=>)kPkl^sVPh9YrLm1T7vcPBK))g z$*}=>X`t7Vgr46Yxau^#I~zV7(bplaX7-|pQED^Qn^@O`ylMPnWE%;C-R54j>R_bY8=ghzy-HnoYVoSrxo*&C=BiUrDsOCxzVFs^zb$8;EZx(@}6gI}{W z;91X194$nT!-#QFes5wQYM8QN(SAaoi}K@L@7>!+<`m6!FC#(@$;gdqqdu>2){>{e)CK$)11dz^3dp?Wr>AK{fM`{58y~VsY@cu9d9Kk22p|3vA zJ`a?jM87o=8pDya9d+OvMZNSJDV}gjGmehRP0$@8fnVagnmU8lRH}Tj^n2Y09=@~5 zpN{0>$i>Q$x`Z;WUNu|234bSz4o{;8+Q&^n^erg}ZTT8H8m^Kp1 z$TvZIWH7Hq#ujg}68S-GD)ii9a5QMU@8%2M*?{r-8<=e^N)N>KiY@It>J9hbgmE>} z*SyTFwAC9KgYNnV*0$W;_5itVx!$#q7Z-+G-oLvUzK=23aEx6xM8(@UWB29KE)_Cv zQN866?0f%iQlvJsN6v57yR;34p3mhcCN2nuE<|Z}6X*8?7o^gtd_%@7IU1Arc5b59 zfxXl^a4HM)+;*@<#U?w)X-WQ3H4z7NL60_41h|8d+MWSo~E^g~vCQ!*FX72O?2 zBilP%?IP?0eI32+YAmxI&IeNA-e?~@@Y%iGw%4|Edq%hS?x_#wb?K?x;zHrq!hI3g zw1pphC>7r!jb4!#iJ^(5Q0!i zTdTI!?LrX{1S0hSL_}*9u~oFzQn%aMV_S5)tzBBMT3dU{+V1wSlHgV8w!2wcM9#e7 zO8(zT&~}gC@Bf3(WM-Z@-e<07=6U9s8G7s8J3HBD?%bKdCPN$gKxX(?uANmocUkBe z9^C5p)%kZL1Li)i-+lhwkbug^V|TL$KX`XZ;3>EYEz~viI5ct~Z;sNJRs6owSA(=x zm`}?)@BT#%4wd+zgYM6u)8Z;w(H*xTetk}EMJKI2L;Iff%+$noc0G@mM)liY*aR*E zWl87JYsP(b69yqWRahePj%RMT7?~Sy*)!qAyfODb`d-LGuUsuSfP0%j& z|KD%YGGZlT8S19JK<&k6Vms{x0qsZiOYUQ!xg424=>B}b4<*A|#(TR)RQ?Nj6z4eS zEsSq~U--*S_P|8_4$!*uR96wSik|27&i$KxGN8F<0#ZU3Mk{4O*mBdjnmca?Az z8@LX)geey*AmhprUOJK?Ec`I%NXCcw4Z!c*w<$yj_rJn-?7(^nxBBm>3sLM?3qBC+ zCEXvQx@u0GeUn(|8i*W*?we&{n(Cmnla51r(u|&I#Jq?Z;la*RtZV{aY{U7vX9iL_ zBlVI4IT@J&6biZHGk#ddF+K7_!JC~pO9d$cM)mYd^tN1|HbK&OdK!}*s>I8!bVuFT zj@^?3bu;#sXXg7sa?&;!0G$4x+;szp)2E1~Fv$Mson&wo51!-L#7oIbx2BXmUc=!OEM!B2 zSY;2@4t|84rKW+8APZvSx6A2Fd2;Z>)SR3FoPpg3%Kv3@OeIz^RXy&*{9jWebLz7C z-Jd`=P1eq1FQV6dfIrU-xOD@4?wY}qTnn@+mIRzkhSaYR>xTZfO)}i=|0-^PruVK1 zyzg{6-5Z@$J~iNeXF!2h<=!(lrY=d+-}!s!FxO@A?&hB3o2V@HwSP;s&Ut*3A66EV z`ozi;sy{WUItTlER6lkPmD9UjJnr)T-*M;h9sf(eO}_Od&Uu8BZFEi*x7R_xNqI?) zHN;{5QIxi>e862XFjOv&{QMHVHJaWTEx*)@doteYKEged%$5ntgc$Bz`Hdc&%TqAFA=S$ajOuTpil}8rHz<(B?kg zeR^^0ul z3((I~`dl|>bV44}9S00PU$5tU{WP~voeZj78QnRRV{_biqtJkTI0NGN!b|u>_+_z) zT#tKQpRasn(C(rVQQWE6|FcAt9V!9E-`TEAhUU@GpKx|`WzYLJpr*j5ZIB&~+={to!=A0sY1#1St@0N_ux=c4=k*F-;5J6q?AVx7GlA>aDSP}x zW*qL+=iPk+OD3x?1#?qO?4xUU?#T?fqygoVeDh(X=wcx#)#|>Iav!bw5N}7ya2M-e zq4Prb=EN9pHwM?JU+R{5+iI+v@|U;vkZHYsH^4$h`-f91i`;@;?-!wwg7Y2okqdQK z_AW5_v#R#_<6(G%54Vo{y&#R3&CzmWZcT4AG|mF%CYQ^$DNzpjoJc^Gy)qqU5S;)w zVX*qevHHpnWNQmcV%Jvc_XKqouJ5eSuRmVVSyotayi8v)DQ#n{aP|l6pK^xXe|7$; zke*}dh5Mwlx3I9R1X_b7`oc;&imCpxzEZ#4Kh`+|cY5MX1Jx_m?~x?yw+r{+ZiKH` z%wLMz*#5qsjix?dSx)r(>IC-&qufi-7ij;XZz!@x#gqOPdHh`5>nywCr&q+|wJ7Xe zvx!RVH$UJUe=1=X)sLspVA%kFbZSB!q4c+}qWP<{h zJMrdYNTmF0MJN5G`Ol~F^BuBC-KF@{3+jjKuBdms`*PjA>Rii#caPMy*X_wPUY>;4 z%IHfE^hVm89WU&NTAv_%VSp3TykYD; zpUP2GF0GX7C7mK}ttGu~UxlEP=CCAC(J2g|VL8~9&8hR__SMn7G1^aGALmWzUL763 z^b7|*D=0{o;!FwKE;P}5RO!sR6Pzq)Eu`0qZ zA+PFb8ZUWnSj-jp){d(t^MelOKc zh_$?&)9-$l&npyzBV<|OdAdFVXN-FX@_Bk^=g5GZ(v3ar&<{AvNXHEgA9W{r=MFvA z)gR#gVnqtdQ0a%)is{XTR_x~cG$+NVpwY6JjAZmYw(O!@c>DcrQoD>1WjKFw8if z+1(b2w|x}J`sp9S|6=AhZ9ZAdF4PTu^98!Smgi4FDuFe%=w%5cKM~K4;qG#UB?LMW zPDqtPUfi=Go(ny~KmwHm`Ow0z=7CDityFk_Lk~{$$};HdeN^{m#)Lli2wu;U;hg*H z?`H2fmKpmM<@sjZ#~vw}98)KInM#+&+^P72@I|)F8Ts|40e#2|!YY}btBQD1_VNU8 z_zPH#e&qe$<*&mIp6d=h7>MtD?v=H$XO5ln!+tEr{LqwMKS*q;i{RF0A4~vOF#0At zq=3XA*8Ao>rJD-8eD`4jc9o5OQC_-f1l?>`S^T0zR~B%slhb#|o{_EJQ<=X0&y{=D z%PRi7KD|Nx6p5mnz<~4_G-WTo`LBWs)a>I)_4_kQi9h*r=mR=w^%}p z80+AWim*a(Debs30J4sL_ZwKR_Cjh;$6qt@cn{`QUP>+$+zY|ZqpJNUyzoxr@BT%6 z8kfG?B1=$NLJR#5%421PxF0()+_D@LP#Za^y|RqnIX9tmIrc8Kn2$guy!VevW5`zm z?;UVnE^V~}t?Q2)0;nFqaC^?=8HJEt-p5A%)K2dUnsFxMIL`j2Vzr}x0U8XCI$zAe zu56j6>>1pLOmF{M1(yP@J!Q|r<$uXJR}uTg+%dPlkM1ONvmy_^zawWyAzqe_O@zNe|0w06Ey5%05v4_TWU)zfu&~fM7stBi%1UG}XQR!W(95DH zqGY&3N`7Pv_d8JjMd&?IBnKb+SL8ggU4C#3GZ*C&1bSCD_2qeeV*U4C->BCo(*Nl7 z9UH_=675pFr=Uw_pZqZANwqw?E}NE|H7bwH!=AvgoVp3PbD2MmIbLu?aB!_m5&%ux z$nQ1?Fa24izQ#b_#zqES5<>Ggyz{*3JOe34SyyB*-buwz4oXpLnOIzx$Lq%JL3&D`<|- z^cUq0dFy|Ir9S)qjM@pua#yKqCmzi-;U3##>)3eqnV;4P4y~H#_pCg-KKsFpCnp>V zcqnjBP7+?FGH1M-8U6L)v=Ga%dv3q%2wq${kV)_I=$!V?J35{2!GT_sM0PMe!|z}! z?u!m-R~=+GQElx)%yGX5j=ec+bLH9F)phu`FyQ#Qm%ESU%5b9~=EVc%i7#}D4?bbe zoIrO(oY*@U%BjmK%eZR-O{tYJ#$8tzT?dDIg9z93)-uMw#%4`hfBtwQg6 zYCwL_lCgCH+py3g!`>9`9YXJDyR0}MWJ@otNd6#aJE--0(AuH-TE_Fen+s_FbIx08 zA+XBCjYgh{HIrqBD)DxXFW0Jp2e|V&v|pGrWCtn&(lb&g#C4v}dDA-v{u7I3z=Azs z$;jZg1JkV&D6T0P!Du~N(@uBF0M0`nIFFj)P&4eo>1ni9*#opzQ!?tZ+0J>L!2v(l z>D`y!L?092b)5N@B@^C633m6~Txaf_#tl#O;eGGq%#7{X85!b(_XlK72ml2L7_hFp z)pE3~mj(*g1#xS0&ttvpt2^3aF`a?jmpOh1-$9;Jdz6;K+&S5GYA)lQY}(goD>~i7 zgTW~Mo}Bd=X7scVCZLBsvj=I0-61^^R&+^_#vY{jy*Vg87-gyR;y1geYu(z11?Uxp zMS_DO%w)c?H*{u8io)`3&i+$PIWw~F$&i7*LmF=RHK?tAZhWrd2s97BQas7(1F8!j z#yS`C6qTjnp1!X-vkTY#3fSF~(Ug6Dyyp}aDW0S;C4rExeH|Kz*M2cRWf-5I_p(!K zF1>{@`J3d3z((Bd(uh%5m`g0vvmaMCp*=4DViYQFkHT4~C*LScx;+Z(JC{u8>t2`Z z|Ln8s>DeKcrfe?bvw-6m!=GUc--(-z(2rwPNB+6)g^7O8OwXpdUkSJ$H^aV}qqL-f zlK35XGgE#*{WYz%t-bOCez+rR`-HckOQ;whUH+hE{9xg_Y5&niZ+EK>g`m9Yo#`0s zG~V}vvHx`(oynYY>BWh(^clT)+2A0-%UFv7&fw;xTVJ80@FRSM#n@nv{3+9MnYsPF z`!gQT-X1_(_e`eb(*B$mCr$^AQ1@nKu!r89Krwg>dOA6QHQj{|FPTtSG-sTi%2V14 zLn^VJ$nv#u4$HDym~AjRm@=3snDsEzV6sbCb`I@{pG>~%%?IJ$xSV28ji$*yAOdhIRjLfF>IEiAU9*y^%sb~5bJl5Jqj zSoY!K_3Uie71it6OxPvG8(1}L;5F9(8~M&npnlk5*flj<=Fazp&x!Pf&oTPK=ZJja zbLRQN=Lh@3=Lh)0=SzLz^B4I1^CUk1JZw#}m8ck~h|%vB`NLiZM-cVH*27+dm$3+J zl(*PS?e&$#Nw7<*)|TD{dkX?M*kwh<1%a^F!=6aP^S2c&hMkw6U%3=^_Lg;3i>SZY zT5W=D%`d2)0DDX2+Oiq2iwjE1VtoGf(|!K+(Xc6Av_9j;-L$O}$KA9(!eO>lug@!n z{VSNf;(}^)1uW!gTWq1-fK7v`$}Y`;IwG42W6iGGLfy$QHCu}EE0I_R_nPbi+PrK8 zb+0Y+x>}-@M8Sk6p)`zcBy2#tJ`x-37ZSFT3br#AD_8aYgxS@~PWj>15Ycqa<+47metTWD`-VYSeZ9Z>Xtbt;7i^Qe7fjG!xUDehtIWmS-R25rSY^lzt-60J1e9Il-gRiC48|s65 z-Qgwq#WmfXEwm@x-Ehl*`W=SiJ?rOP(K6 zMl({f{*`M>QHkpXdD#WUtUoKZX6NO>7FHEk=F3rU+k7^QcBoLvt#s^EAY5TZ1IYY} z1qD7^RYq-*jNL$Of0;k<*#dmX+LDrL;5#Y1AiEm)$dPZg9QBBNsV%Rv!uDhRxA|<; zsdpH~(!PZ6h=6w)z80Ch9Q_-HR>Q47%ml&@U?vr@!aHGag?%fG+Ha2gDJ{G8SAy1} zV{z48OW6-uwzoQ`Xq?8b@zU^Z7~S6SzkcmpKg6r5E}DAKIgJ8e9p(d@HrQK@cGw#@cAG4;PdT1_`It=_`FYj@Od^Le8F|<-?nDKkPp6~ z(+9uvTOa&Rmk)mDKYj2;U;E&TMttx^Kl%I%hkgEqKf=y5t-k9+Hi*qym45e!?A(2H z983Y6b}WBieCrtO>YOc=l!kBJvZYe$^>3}DGV77WkI?K{IU`t+cF&%IknCeP8GlCa~q2<{Eo6f%=6Kg3A zD}%ZFE|V$kA@6scRmDY^dN5c4ui9GRbyHdl8sMeN-Z`C48c6J&zw)c9*KOUhp3Z43 zJ4yB{`Q3gsir@O5QhloYPUt6|Bw8djONz-O%#o1SgU@QdoN_(v$IyR7^n}YMC_3Vz>p4kJl>Et2y<|fo#bG z518v^YPLQvFZUH$Jo}raJL>-`k1(z?A3ii94~Sa7_Ve>W!J)xHo73;R@4ocSOIM{Y zPT?M0efQF=OmjvGmzA>kK`wJC?TT!`AS}B)ie$&45 z+lMM39L;mgWe!%j_;cH+&43qtTFc}&D zw|M`TycWOt|Ih2eb3eyf_=|6EXm7DSEtv2(fuKp%;ZMZ9Q38Rd`&z|{nG<`yJ@Z@A z?vdLGKY5f`NV4TVs+0`WBX-&PU>;dJ@oAo5Sc@CC2<#^;^47 z?8?$)h5V;6{wqABLQ@g4I^;W>>-7I6->LO)?tWSGzvTTNUtAsX{lDd{kSeGBC}ecC zQhkJ(IYF`AWqj25STlZChZrC0`M3E09ve99dRaqL%#pr1o~HkH8flZFcE83PGHR2a zCPZkdO%|f=hC2T9Uxaq^(-M_1OR!XBU74CXxKOH2Q5Bd~<;hHzs-QfX5UZ5vik5ts zrfy0Nd&;D2dn}?pLgG++m?;vN#IAIxzL*@WY85ArwMiU79_CI0 zlv8m*+)`q)f8uw!`P{$<%l{Cji~H5Ja{~cPT0fDBTb7$Xa_WTAF`+Xt zO`Y;~m;L@|`^POzTw~WKE0tIHchh-dlHT}a`PF99hhfC8df!Zlv$mWdyb-qfhOIn{ zC>>dUCPX(}4etfJxkyM({<{d^M>Bkf9KNN8^d|89BmZl0vQ-cidF^9vmmTXmC^ zC#hx6Sa5HZd1-HN=rcNWAn~(z`@go}3OWNHh)EA0|mPtI}_zF+H{w zEl-=IHq=j=$RTY@=NX1^ti`XS>*JNi6r|)&pEVJYy%n{-+=SFuXkMi2+{*IgxNbgU z_YH|y%#*u-(c(Z3`6!~1*UB3rsm{I(^)ki&(SYJ^DfiL9B+0pfN#xvs;vREshKwzc@|2OL}w&gb@WU_tN4KaD_hKNz6itOspKc)%W zm>3c*bdVU}nJT5_l-{Qf>k^X8F4YQkmx82q`7`)l2I04zJs3@5f;hr+XW1t6;LJ4X z(?t7OHwjX3{(#naBqs^lh?vj$(b}hNTw!26$xpwb z)|uWxpF&*Pqtz+I@Ul1M&pFdDbyHx-Mkf)gu9-DyPQuXo3`=Ef^vmkgw6za&zvF^h zTE=z{N*%ysP&caqb+O!o6MCHa2I}vIKXV`VYfhCq$sWYrcY`6}_Ai}g=}N>};=#T@ zw~~8^Gr_mWLtBN>i5)s_;dmR1Qn?$BviQ{Lsfwd(MBghKyD;g+3@cJ@Brj7WNiWde z(A~j^)ZwLRm%CMq32fS0uXG4A1sOtz!)oRk$)TG9ax__e$7`nEi>@BW$VrA#*RX%8f-U z8dUMZtETH0fyL=YXA+|{FxS6qE>CWBrZM3L>GkQ0TH(_fW%ekTX)uW}2{3UmdYD+4 zc$6UuW*ST+%v2a7i~%MQCIN;Jv{_oaN3+`x)b>k{m}og8r{upJ)q(OZ9#%OLx3&pI z7hZLyNy8J#b=_?3GINM_mEOSEiIKM%wkiew7l>Bi$XoS_GffhnfH<@AmSt&noBA%& zJferYt1*^@UkDqW3}G(lQn>P))dd@+T9GphbawlQfTQj}xOa~Tx`^44FNR+O|F#ib z9t~sR-Z*kjXjblL2_GxfZutAg)`6Ys#*NmkxiKe42YFSBZUc>}M$89B2p`PkmzkA> zmx1mH)p(I?@ZIu)d`D?P9x)2+*FAD|qf<)ul`2cgD5LwhTOrI@Luni^bO2kj)00G~ zjlQ#+kVTm1lA6S1rscrNlb)cJLfb6MvKYq7oDlLK3^A{z_qsM0)G#-Q?$sJq%I@Zu z`ohhxFJkO(n5JAbW*GN1_63^i7f9@leUnUS3ou#?K^Jq3e(+07mIX>LeCh%b?8dzK z1&n=@QDU2BVA>QqwL@zNYHQqYsINCkY=7ThT>qR&XD_L507Z7}uQ!F+{dFQfe{_-q zFNX8akNjhAOdZoDO{+Kg+2sgXHj0-F8@lRWug}#I_)|uRZolR+UDcZ&VNktEY%8e3jH;FJ;X|)hp^i7{N(B6muF{g)W-@KJ zNqSXRA}Uuo%weB4zgk7Z+Fe?N`7L8~wB2Nh5x_mbPVt?DuLRiR^bz(%eV9E~udz?l z$Jnd%279DF!Tx|g&OTosYoDv1We?SD_efDEmpjZQr6sDAI0v=OVFs^lNuA~>EeUTi zmo$tz`C!b#Q{X3tF}oKs$c#=Vf!>&^RJG4G%Y7-$z_jE^Pn5deEE#vH(zIMb9&k+~ zF)Gwe`g??&KwpdNcBRR=?G>TZ!j|l>z#R@KN1{!Onw@F`Hk^u=cs^}zENw6;u9-tV zYEI-zIbDgX=gv`W3DH^Zl{kF8DD0#}?2KYm{C#dM=lkA-v43{#@JLq> zT~`PF?xH5~v*eJgXLM-M>GCEyM(=wr5yu$)Y_w$*Her^os^#C>=B{BQSB|x$4{ttw z`$?7~S`qgL4^jWYBUUHX2XaqviL3O9)%JEz`72B!W8YXG@3`jqT(?|PZZFapQ?6k= z5-aI46Q-+`Tyi9?QYMl%^Aws&Y+s!iWPcDQ$iWz7_R}7so7HmKBi50`6*hc zxtlX<5YrpS7yCVw(#)kTj<(sj=RD6P(R9~5{W=N%$gqI>*3(EL9gHK$k?2UOkKuyD zDm3pm8&g!ga7GKy>zYD`(kN%{Sw0@?z57)}CeanQ4^RDATe9yUo4LGzqEMZ#wy zN72#U9L3OwN00;G-~F%OU5Ho|S6_^4p2mjqdW?xOTDCV$pQ9Wq-7eFY*K5Pfnsd!7 z!wJ9BL+iz5JY`32+LfGXaR6e;$u*Bgy(k5>E&a61tVWHCP>Uy-m^U<(p4~q}@nDR< zw<#UxO5gJwCI1?i;vkI?b(t9}w`jJIPeyz~PMV&uBS%Krbq@Ils_*5Pl!zD|C*-G( z6qHI8ujKC*G8cx>LL*x3`g20*1xA~{o^kB-OgRZEO&ZtBj98C*qE1FvJj4wpi0uW| zg1lj!ZvFio(nQuKHOlRO@InAk>Q$YBM?a8~r|7v0imb4*|sIm+r76Q5L{RvIQC z{%76N7@9(gukCe9qSZ0VEa?e`f6tpjXcuMq`fM#B)jxE&bpHTNZR{bcMmJGWS}MS5 zW+JCXEhKpqnbB5Bg7C63D@?cBOJV4^T&+puW^;?U=mHV{;;7b|6{0N|>>!{&bUdk> z8Y)18jfr+9USXHU``IP&YP&dol3f%ZU>7EY+h;i}5IxtM676y0u4z||<1XEm=y6x* z<&be#z_svkSCB2xQC}f52HBW+#x9KavrQ^dl~5Wj;7<=TMhU(N11^J!AGK3%!?#ut za;l2DlMUdmhm7-W+Vor0dd6*PZ5sVs6^YYdZba@vn+cRY2{o`{h!}(IZ=yftSJ64r z%87W!^;=MhnFi4{sUh$h)3uvnEh5Lvg^a=Pn%qMDq-!_%#5%KO7H2@a9ZhDv)QsrH zI&S4VZK&Vd#><9@stP8q+mmjzVD46Z=E3TCOH^huC|H0^XU**Wd~lFR>c-PIJ$q>ST%Cefdm61~0rO1}xTP`;IcnCB z28GdiRS_q(EA)T2eb=EzK4h9NzLNL2Xnb-3@yFv1AntjaDhoNQZRjIJ#hB@QD<=Nr z^cO_+GTIyB4YI9nZ9oi{Y}t#T0mXt29u64St-E zvkZy^jhKA{JdD4X|7lc(wMdFN4SB_gB^S2eNRb|DW*p3o6tP*OGWK6B3L$YfujuHi zI!(-@$sBjIh!+CrP-Sb17qNC?K{K`07#MDzfahG6tzV zop&XbC)d{3HjDXZkOvJzzfTr&ffhe6PBdPKt(L2$v})VV=35y4ZdB>TFzbKE(1sPM z88~kD<;_@#m9AMSP9jTMX&P^4((=W?CJp@PZeWKnwbV?*`KI*!{xuVuSHFE%SR-~UpVP>wV! z5l-SmUkNjY$(@Y6HB3G#9WiU(9p(9?lxYrmv@VM5-8xW!!GRJ{xlNOmU%{Hs1=3U==Ds4`8(ZCZR1$Xx1p%)@GHl zhjKn>OSwhewA;G>{d3lB?=$;K-#733&HE~gfd9wX?vTj_QJW}Bg-eVW`Enz;5lX3G z-bEjzV~cMRaRFGbyP_B?*6Ntq20fF~nd9W(f_)@90CTUD*Nu^upQe{ z-DvW+Gp`%Dfag{G51?DbF2$;uKkWjgWOVKhqU-6nwQeRctYa1GFc$T|R9-KiX)C7#MYvm>cRjIuuhwwB`_fqS7vQ#9*C6Y*~=Y5u?Y( z7?^KqNoa}6n@E(1i$scwA>uHH7$P7!)94ItyWALlJuO7yC_!40Ju4)LcQGE@11-cM z=khh?u-uT=WpwKe$*!@-HZ-oj9+N6gh`eFCwWLuy*0SKZ2E zVGEmM<ypB!^7^D$W3&#dwR9bkJ3Ik2N!1{Z5x=22A>a$# zD!7Dj`He9cccAOwws1~%k&^%Guvyb%XJYOe1V@i=ypC@~kuakGrFqTt>eclAgPR$h zKi}(SbU$<~!npVb{g~1+kGFo1P8c{|!V=fX_Zh7eWqlZB4MMK7F+YmO{huKsk_%^^FQr#Rp%7jpYd z@@v!fX)9j>$FE8W9;^+ZBeZsR+{hlWg_HuQ8O}(c;JrMdvmq@x0 zoaJ)OYK@ThAM(&%ylsSF3MTp479UYAa`7`(9BBWZmX(0gr3R%rv)-$W8krcgejdnsMp z3;4XTy&g4*XaR-ezF#uI5u%H92)k+-F=&fFf6~ox!lR_CmWZ+LOw0Q%;u7OF`{iyS z3B2Hhb~ruq>2jFi9RCPt}kvX@uA@Q<%NpVxlKoprkADC|D0 zm&qpD&pI<@0rlTVQmO#=+bzKkHP=6n05Nw4)#eGiwUtwLkEDPX720 z^D0S$R7deos{eFVro*~QXPjh*G)i(;g0XGEqG`ry7b(UnqZX3tEDen*dAht_@_fDN zW*ZIpvPEPJYx~S2Kbceyzb-9Ya$=~bdsG^&i+LqWa+L6WLy`uwMr4n1Jm7G7zZKy? zOSG)}htfEyjp$H*eBGB;h_rthl|)aCIg}+lL3ochZHFBr0`hQGqS~%=JZ_OZ54kgW zB1^hWx3Iw@YHjcc8&-H?8e6xi9kC946FkaJ3td(2%92*oI7-A(_~KNH8s2rfWTAG7 z{p@Z4!dwWmZag3XPw$*$hL2;KjbN_-EG?Otyv>!Fs2B3n~T<=6zwX(x>3@w zxn6Q~x2f~n#8v5hm=dxn#k|BR6t|?AEvcI4O_FaDB39STOIT{BZCbplBqSkWvpp`M zqW{5T`&Y#o#%zGAPkR*DHP~&6w|(O9@s7Uo_{!nx`6F=BR=5ly;0+b(-KNmn`0W3$ z_^7@G25Li#VU?M-xmwZ?NZah`!;tUjIMMU2o}b*b97i0rG+c+WdErAnKaEL_(s~g) zjounzP$TQSHIf1@brX83Og7n0xdxdXd|@Ny{&spMopkAR8)%C}bEF}hW1bT_?r~5* zX%PL6d5+4FhI(G{;;QCdWKRFWV+&AHU!6|=Mu@6*jHqa-h~atr zt#VOJX}dAcxq8BHV;Su28x&L05M+;r#EZrl>d6BYKIg4L+Gg)ur!gw}%Z^QPh<^7| z$Np6bhB^Ir-ZnluvO02+%>iZV-4W&4K3dS0#T@?CRH}mkv%_Jro zJ7SWf3ebLHEU_;N{iHdDLyQKZtpO#XJm_}EotVdIs{W32UaG(?xNVC0|2>yCkW0B8 zVU2;1kV^a`;wQER{tt1VLfl`|xF;8d#&DlB2XS*8)_8GS?)>kY0c{XDHpQ#k3Vpst zito?ZK7zFKY1&#x$0P9xv`pR@o9C05@0*!uUzzd{i*Y14raB^N+yKv>+ef1#=kY zmFu3z$%T`ko_C<`{fV*AmH~MXAwxZ#BlTD*4s}#mgf+D&yMhmPnNNuM!J%sikFzqy zr8bpL#V>W|>XiIP9_zXlpp|BuaotMT^KE!-)1L8+oJ;SoeMHb#JDtiL;v6fUjdi?c zBG;yIuQxCB&hd4lZ-9Gt^+dW?9?cESc%FoE5wR)dk_on4ts;6Bp7$&(M(_MY+6Jc5 zq9t;Xw}$qO-KwFhUY>}6mQeop%J`Zs9_u%7quxJtlM*T8?7^mBH^#&`26amr+$ZY#M zOS|W--DHc)xY~Xc{5ECE|10u3(9H%zTz+9wgnCZ<~iTHC7dJjV55MP;unk5C8&81kWEm&I08LdLT zVVD>-pxi{gVsWs&-ZMErg=1cynPs#p`1X<6Ss#1q3G=#g3iW?AqR*-?*y#~J{jsN} z;bTaR==ySGyTKwX(A6uF&V#!5f^O_Y+mE0xtXW%F`0$zyWYZ&sMQd~C5xUPp=beq~ z9)7rdUJ}WEc!Q31koAw0&!cwvrqaR8nDMNA^eii5@x7zQx5G0SUHFnmJ(HNvJXQ9P*L80s zLHgi7#&97=jV%JMn44^wWj&kBa11!eCo$&@0e`|T^&m|eqtk+`C;UU6o(_@2xRvG~ zztPn*b%^MkXh&LSv@L0y(e|YENO{%Tia7}Q56N4^@qk8AsK_g+Ug%=<5}U8o&z~(n4LXr|$TKO(&~nIQ zQ%k`?OAHd5fCoPOevb>Q1}Ou%0HOFOAscBxT*e@`HF#{0*dsRNt#o9{hJ2J}?OF9{ z8du%K@Q=F190Mw}f0$^eHoAJ|xr`Q~1^wuWcM)wQAa}T?QOG{**#Z&`NP;VxLiW3Q z!T^~9NDS;Si>oKZ6=4zbQ^q3RC)!ZJ0|1{0d$Oyso@iY?Quu@5SGeBt$OwhFhlo}V z2;)*|)yTmHzY2c$kRQHLi&nddQU-Xa)B}BbZLy9J%CE+w|I%?22bmEuKb8{{KD5WyC#SsON z$uNAIi!m12j5R!DZSnRdx1ylQEyr#!XcSi9>f7Bv5)6k#*Ik3E;}Yu4)4 z7Q`$F@}`=JR1_~G2}i2GkEc=~m9;u4jHXJYsV-BhHT0OTAJwB@Q<*u5Qap1{$Wd-T zw~Hf(RI!sTtEL7yl0wB@1tQU?>go5e<`DBMUF7){i>2R!vlmJoGK_sj{FbTfs`z${ zIo=pz8nbfCnJ?QWo-qT2GdP%eoWUc#@0==o6MzVMXE1f9{KX8hdL;otC-e+F)aXP%mXJP zk>%SSa7^$pcTu;$y*1u&Rm?9Uttz}(&(9viI*J&$rHu1=A+rUY50gi%S zzy<-6>aeREFS?!fru(Z7T|CX{?Q1kIhr29<=#N~XR2cIJlf7~)z{RD9E>+axBmr{cui$YA}8J9?tpJhd^^jbReq5dB`DdQTu77OP%wuP#?!~}8xweUF!KheDqei3BK_&k3YiF`j0?b9p?sPR~Q*X}dkp%+pJ* z3A=U*|1?GHCFC7|6e-50k{2?ZKS*Y|WX}s=giE4XTU6}NB z20Pd)zH_u7Rr-AGBxvn;q^}b%?EBlWpn~1aDEX5wKr8I+=J%Rwo29(K1zNX<5Q!zd zm*1S0Z^R6+{S+n;F=NJE+}gB!B_Nfjs2}q|`fhGP#sa($YAB$s+~~9j<(%}Og&XcU zH3rJa+lCpj(W;a)we##j(D&Reh3s;q(IagYcAb+pdc>`hwtZ3?;F+yHyiGnTpCRos z$>m*)ic5)_amo~Z9edP5ZOVuF3~XV3T?Er*lIEvG&1Uk#!_#0#&5D|FuAsGBlt-ds zxE1IT(0K9~tn~$EjlhKh4k|C;CM&T^(QBu^V))j>_fM~{6u$By z3b(>l>~&?sl>^D>rH**44eFuy7T4XAP9k@pmp{feb3>45Go|9E?cJhfO#LXNW#`E5 zZ93GztT7TZi3@jxVg)VbyN6YfYzoGGAHm1ypn;*2zHcn=UIl*4zFKp0nFDen$Fk*` z_e?)rl|XlM#Bt(5HDtUZd#~e-@T?jJ(tM}aMGSqmS07Y8N5H#?yM#&s_q>Nup9m)n z<{ApMj|fs;eGo9BdX7oKxA+f6Bn{h5*Df>qn5*O{-3h|(m@OPO&4)>WE-l{#{W5Zt z=A?SgTtoOjj4VoF8W2Y#)zMsE8i8iUQRD}?4b{zL8csknOw_Q$H02sOT3aJEh6Ae; zUcB}oFPhWyDF3be9|czMt9`juj!2$Yr9d6_8kx#q1uAPfYm!`}GoZvF^VSd1S>HBm z{O#nZRGU_QJGYemDA!3%xC59`>{FDmv2X4$L}b+%mTB<|%{z@0l7hag%Kr*If!fV* zh>q?sMR+l1jDfa)&;P&YM^iGo6ZekSZc5|5-DDItKPW! z@bUVl-}qOI|EF}vI?8CCM2ebq^$s5=k^3FD>h*_F0oRCjW*S6j_p};djrt{^RRXjN zZA){FuQkt)GJ54zd{HAch-}NURL|`X-oMHmMuO35Or1%2&D$0T%lJjucGGh7kuaJL zJtV+JkSFaesuc1(^ez9#dZuM93!(jChiSsK6XCQsOtLkGr`7DL2}(&TKl#7bl9bkH zc;kav&W+&ape>eN)I~MVEjOXfKC?3w{E-aY^vC zN~K*yE$OP2T52Q?N)ODS2NvkH)It}_Oc2VX^9t!CN1*MO>6ebDuO(~wSmx)L0;z>l zIH;!QS(B2cV8k(@7%>(uX`vYUoVz)frt!hErlu<^fwR<$bKyuFaQ0zr^A6cz3ElsSc>_nfL3@@4qiFeyf39p!!4Fvdmno% z75$5kDNkCc&IINYe%R%jj=CyuiU-ejFzI(KS}xJD!m~4$Ng!6`KABybptDO7qOc1p z#tf4>0$vhwn)1_>-y7<=czT)V@i`YFpkEY?bsxWNY?(*puZX_Gb12*tk*iflTlgj~!E4)KTIBPxEYGwbUcF zkYI6vUyGQJ8AHj_#QdtWfzV$OLQYxzh`IOdbP^?l?p>}9nh+y&*XuV!(8Pn!13p*w{03n+fPHCJOUZ8Uv< zok5<j5^jF6keK}xtjqdwB1U8OWgpeI?|{HRHLQM)Q05`&l) zf#bdRNkSNQ#*CO-4KOj#L-2E~hW^s(kgMQ4cbMdMtyhy^6;jM#qdcn1CxPh;QOw7`Yfm4Q8RVUX7jSg7{e6Bf$6cEm!~PNFD>hVvtVV;$-Jwc;N9 z5;5IXsNLY~5LwjIK*=_U3f=^F^wSXZc!EU*f9s(A2 ziqiQItZPdS#O9B=8TuVwy&3gs zl}^h4W&~O)i8xiIxP<<Y;l%l4i*ysmnQ%)Fh57z^tUjtTfX;#jL&m0p7RcZ6*^lmGfU&rA`5CP%=6hk}Qc`YUr}HPDwgVVEin# z!H*#a+oqM2@{2^+C6}bc@K_r_f?&q3xtT=JTrJ|Rb4+VU?J5;~^FWg^3oIo%X;-V{ z>b57a{(@eSvF9pecgcj%`Hfi0lYi0?l^XRT1HPh8@*$DdS zZ5=ob;;K<|B7Vsjm1Mel94-w`ym(SWIMr__aP{ElNYqSj0hdPC>`xM&^$?@VCdFD^ z0h;{TXs$*Q57`FR?HBfyykJ!NiBdLZA@pLcpe~g|RCmSvc8GDo_0yO= zsjjnY;T;&G={&29cbq6)Xcc#*NSPF6mkIP!7$ZI*;nxhE#tvxO;xOB3&t&z9QWK|2 zp*hm;Dj_5P!cH8M9lo&Tx5H)w4-UM6KC1P8y`6x-tw=F2x8Y0y_f@EGdk{Ky3CWpn0{oJb7hZd2+)(+7I5v zc=9w&&j{e2^gOInv=H=wJ2DfBUnvbsSyS~@L=3lPTbq@ECi2F&r3rI^q33k;wul6y zJ>jn3Rj0je$T;L-TK`b<_+q9lEA)%zLmo}*&c))kL!K$Eja_om3W$H}7h$h;N#xPh zuXTw;tzpmz9Tll}nV|cGcC94>Xd^^ASO@81bORl(M8UT>cQp=wb+9)r!qFPm(V<)P zw+?AEjYFO~+^mRRi2dQnp)?J#;k-#{Vlhn-l#*8^#du&+6fsGt?JCG>JYLyvt5;WV zApOykPjEKSJrP!rFO5XBsK$3XssHm4Rf`hy4Rs%bTcP8Wb*s?-g0bdrMwOk; zd_w+NH%1U7A}dBuw9p=-j=yoSOw-#;b6m!e(vzmE*Ug|sVV<>oIW+X^O&{3Ax;Hv} zr-g=l%Ez#8;5{ug+*2}^a)YE1-CwYGbF_obk>!w|i#Uh%RjU~*gbQjV&$>l?1=DEt z%Gg1R#M~I;RHli&G`G1_fdtemR*+0IwnUmXQA-5%LE)bF(AeR*d7G9OG*=#ltvRg&K3RY`0 z>#LF#tuA6q5J=Vw$$A0OS|P6@q*Wmr-J}K!ZB^3N7T(%q*AfV+eRX;XvfMJ8>-;{? zY|y^#_xt_h_s8zcoH=vm+~%C;JkRI(oS|T}2srY*{f?w_ct)7Lagm)H;?rHG7aOO0 zPX=G`3=fjW3L`rjzH_N@jj1oFDGmY8NONlcl>O(rj*L}WSl-j*0(>u8U<4^vq&HR6 z6sPxTON@QGp$5hmRQR|fG>(uDhBibg3#gktkgG8A3QM~wJ*gvQr9I%R2j<;svcFp2 z<;d)ty>X#k2YES#knx^vUh=lRa%=c2{@(YLRXG!N-kqME&F@0DjgYe&OgkIbWU}JH zetrsl8k3Wx4rWOX3)Re=E}N}Udx`>&paD+o z`HB@bc(yeb*fy8~^{tM-BR7FZPW@B8(U|#4m)bV&9&6Pt+cJpejTv^>meW*6DrCV*v*S}`m(K~i5H~re#cgwoxkvZ{{c6>bjJMXxg0ZPN zA3Cq#Ff+hYd6?Jfq-b)&@an{c&lUo2b5DI)=hNOK?|Ak;M@B!iOFZ{hnwaEm^6rC7 z(G=j0@FI6)O{N)XV6DG+y7+XUeMrY|&F0>6nUJ!Po1YYVXVPk1`0VepH<+@5`!Fjt zXS+;D-N?gdr6-uS_o=dX&mDsd10+-Z{Zg{V5BtNn!tX$9n%ZLi0oJO)q!wKHQ@+Ug z!iq7VZ9L_RN=cJ+D8RRJ(j!r5Fud=$*+!IG-{JOeX~RrB6EkrM>_T6J_*Oh?d}p#) z@Hbav^R2EKJrjRMW+ikHp0Nl$cn0C=6#LLHr?*bs>uH8G zvcI|6T~4Vxvx}gCyq2RvB}aRwa@2wx1(2f*!QYZ0>1x&8R5H+xR9M%FMgV z)uLX|BK4kT8rPgm)3RfbZ}m58UUbgT4>|Q)1`WenJ`QL^c2;E*fQn9`SrRp~$coY# zZ?-wHTB@0R6z}U%Z3&Yu&}nK2@~y8opJ=`y3O``5N2l%&l%>H|26Kb$+LJ~+=bpT~ z`pdw(u(YJZmSey=)(_nLjER8MXiM7foEdQF&$u)FL3K;&Uh@xO{VfYoZip+0>acVaoAJDwl3zK6H2yFsk|K^=NQaxif(@YtslTPR2B z)*>4hjGJhda%|J~Xj?dGR93fERDKy~8%k!`EjN3erk3Rt)0?RaPTQBbUyJr1k`wo5 zx7I;(?k>OCdnnMdoD(;SS)xkx{J@f}38HRTyW^LqeWH3lmG96{GW6-tqfW%$NwvUH zEF-=7Mm*(K@@Q6`M~Q-j3OCrO_d^elQXC4fy(QVZf{j6{pF2@|znByQtmTMu&F53d z`;%Y49oC$I(~HGeEg%O*stNQ!<^9*%Al7=@Wp(wTz&abXL9Pfnb_%~qaxmGeVrlF| zn;vX#Y=+eAW9KXQb&v_{6Po=^c9!=8F{9lor?8gyfO%<2X+L43D|cDlY1AR#Xw&Yk z5tq7Q^)qrxJj42&{qFJ_GramDgnCEs>R+Cj(4Ko_ot($2??}fQsnk||>o$k}^fI)V zdN0(495}=vpf#djlAsaV}&WS&R^8Cfr04%{Wtq zwXGPblAR`Pi?;Qyvggk{VETKot-jsSc#e8q+=O4&NPiedFJ#WLpIxl^X;v4>o}{~= zH89m?^YyT>C-eioaX$VQjzPO^Qa*hB5PYd7*m2Iw)8pvTAvYl~9Dnxd@mOi`>S z&(kk`I#JjfaHNFIk6W;Qel=S#Zb+gvLMxQ-uc$*=Qx4W^#J=D`U+gL$k^qDJp_O^z zNu{2Vm*qkweBpnbS;g{}dZ&voK??Mj8AFg?{eiN?5D)CEFLS#?b2bGYaLgEYYR82* zwkgvj8gF>O)ZzH^8NOH*I*OS|73x5&FO*qNDe<<%`3YwQU%mH#Jh}D{zv7c?eH{+| z%qG)P4<~uY{sBD95aw?azFQCKC8^rjk>PDYpEjOd>+SP4WwYX>)2eFHL59EL9MGxa zxvDXpyGQ=SY3!zF=vk@{&K)&3!lXx@PZX}M?voF|6V$k#FKBWCSA|&sa=o&~qxh;- z#*SY3fRz=2LtxHx&Ybn>o#yhK)yD2a<>dQJaf}^?Rji=Np$`8z_a(Ux(jRmJz#ptJ zX^O94rFIQ#VeLqDX>HGT8J=!)XwK=T{Pz-o?2lVH(2it;7dTE^e1nK=+ltbqt>%a+Mt~pnr*0=mxIJ~T? zD>Atuzs_m;NPg33u*hd<-9q<$9n)6gsRc~MgmVc!`|4sPz~<`t%5;;SG8pO;MzAwd82-euQZTo z3v`vNZ-thIG*9=Hs6ut7iuD_SO{opkt-k{vFYtTE%+o_CF&1x087Q?G6i+=r{Ax|W zT=9p=uQrpZfT%S<*Z4BfWUOQ;><^wtAAz4Gtc+SV7D*iyfcMrKE%vd3iyj#A1l}La@ze&) z{jeXG=xcupvD?ZTcB=Fp2VOp`_jUiD%l-Cbtla-Vx$#~6Q@LBmzA5+3|5ENnD0jnH zO7+2ElQsioq|$yexK=sy1b#7?p_DUzrFQl@4|}2bX?6amvSb{Mq$;I^-#1E0AtA&8y~Eeg{@I@dnY+YEn^uu$oO z2lr65CM9$?*5zl%+nbo4<{8Ttjnq4SVHaKfdc1wJM*3vj32n*A@zF@pNJaJWVLpx< z(yJ`Y6=nZ>nxp`{`$)1^A2Chlv;B#vB|dzi&g?a0S7iR8MBCRhe2U~^Y2`%w6R=K5f0vmM{-^P; z2K7O59br_S0nR-Env+E6h$v?>NBMc$(D@*8hpXwRM~qH5+7g?w{`(VWc=+{DaKUua>zcXCTy4&`){ng zT<_c=>((BS6M2(aJ6y%aBR`*b?e5R-{!sR>+aaIDFT5^l1_m#~oB1Ke>t*g`)v)NS zEvrrUa<%ZZ&BZ!H?lWpElf66S|6WIO=>hbJ9rC_)(Z~dkZfu8}~c}eSkP1(#?~EeFrYqumf^8%>&d%guPSR>D?69{opi8 ztv(^6LkK72F?I;E4eGCacO%ODz23(7RdFlhs&ai?{t4vit;h0xm6xaA@?B4(9I_hy z(fr+;(jMvE)F_`}mPX&vXk^RL*tbFH(|ZVWN!UxdqZIla$SFM46lt`Cr`sJ`%)o?% zB#qo+7uE79kJZiUEkI4az;qTqq>}=pg>E)`kxlI{a;tsxLrbiU3WstD%hZT(UQ;Yn zD|vRvtajZE(a5jI!FMzE=h|rG(TQw#iLKSjOFxT#{@`l)#>A4Dy!}J@fbn46p$9VT zwf9uyXbWh(Iyuf-wFMeG#hE{|B8S3$Hh!qC?Sc6-$+p}S#2r(Kos-^0%-0`)wl4RM zT-}VJyS}(P$8NBTwJ$0ClIobs8;@}~5x)fdd>wOEXz)e6fG@D!v0#9iEf_6#jPsU- zA+2)$#JJpf$1#462H$b)d)W>hGsSOnT11(Z{+QmMkMFB(CWMzeXKEaFRYT$$l>t<^eMy?dFf+2J7x;VBlw@tTiVykn7BW10JfmXc1Od4KefP3123b}fHN!SMF>jYhl^|2&Qm zHkag;6gTh1@9q|**QAHi+=P*j52aV8t>E)Y>+k9ui~I^$*jwZqSe#f||C+NM@;gc0 ziIt^qL;SxYv!wi);=*y8~hB3GJ`}>y|HZCmOMh)tEGeS0QJPq+7VcWZJ2qc$)l026UmBSLjvB`ftcUC3+udy@#}X* z3vhR_dV&onIaJ}I+?{ft@S^@eg^`LNc}(Ke2vUcc+QG zK@H)9b*kdzvujKTYc)d++{f~pR!EiX%UWNzPGC|lP**JH7*cmz9sGedIy19ZHw1-^6o;73sCBirQ^`G7 zD%f;e84Kk6I@kr990xyOYCk3|pD2^sDdh64d ze@!xJU=ntBVBcXA>@^_lWrY2D5^JXJ(Z(Rf@MfwJ(Yt$;JF(nNLw4i+1v>$&fte76(cY46B@MHuV6Lt5n~z< z_F7wpq|)%=Ukw{HF9JE9Vq2HBEvOQO`o;MAejD9nsxiG2B+iCQ@QPh*qjcBFh6RQt z?*xAqG~8gAd%4dr75g2;-keF{z}(HfjP(rF4cV!t!9sN^Ct&-g&R~biW3yuxt7zm{ zw7rwfF^YubYs82`Hmk%Uz zDXY-3T{4rt0IE`hw~&9rC8XYiFgLUeO5Xv=9(~K#-cT?ZhZ%)|GXOQMya95Hv`Try z1)L%ONH>;e5!XwR=WFR^Dw>N}dSrKH(ztvOb@B<~6;G0-^%pqHLmvMszm9OqhX=ns zvfx9%#o4G#eIw>2!K8lWY51;4NlJ~i<4moj^E%FWr1QBFKM@Qb@XOz05cxg)e(31- zawQYJ3}~0-Ya*zKJ2-Z=RX0#Qo9KGyA5VdEuX)X_t*?~Yo4cA$LF zSIFk1VZMbIq=BCmOXpiri`r@9Keb}b?5m{_dj(RavQO}abI-xqGx}^0{D&kOzM$`oz z6OqQXXVg>ASYh{4>Ru3(^e0AQb$@Y$;#!qDm)?)nx!&Cf-V_brSeuNQvhw1XV{bY2 z0{2zjq70nrTw1qru>o2ZiqAP2Fd7D?VW^|!>sGF-GG4E?g)IU-S^Y$~>f*1jaq588 zzyMAiPnyL8Kgqq7@QTbO&P(4(90#C*i=9Ighj043W3pGkJ=sH7w~y6(otK@?de6<3 zyin@Vz-Q|^g~P{c4bSt0@rC$H!Q5zIrJhnRQ;q$Rp0bZom{tjMPKDh(hHuMnfrPr* znLN|rneDz`a#k3uya%2vGtlQR`yb~$l~;K@wFqexAdO5HGv<+7i)N2`s^-j|1Xqa%?Y~U`%cbBE zyw0n-#Z)5(_alSut7d#FKc;U5^-1+=n8Q0UEi$TGV8el(P?%6`{2c8Be>K~o37;5_ z(`Y9&SN8;sM(6OEsUxd{;7MC%( zBcqBquEZ^QfheUSEgFHY$6QwKgk^&56#~rc%;bUwjCrq&sj7*YA-%3;xd@4j3&%rO zr5z)wo@9)AREE@%3dRtYEqtL#XE6@Uo0DrM z+~GFhndart{CaiF7a&Xso4Ers)a71cY$2F8FfdbV7kUTbjo9piu#x#~zRc@wuMhFb zakigBC&8V@x|rug9dX_A++I%n{V>yWEo75Z?y;$RjBnw@lf&>;Y$1I1@5}hpz$=Ja zo5zGFlXNXvVq7cP-r`$XOWZ5R6njWEa(Lb7E%uf6R~_7GZvTR;fc-U`@vZZ-RQ4oT zn!uAWuG_z>Og!CvA^OAEQ}O#~-hvk@zCRfrqh7bSI?kr{1}D?k1t&SS-BEoeIH|_b z)*l3iM{tsXv4=aGpS?bpi3VG6QfuXNPG-9@SqVE`lg$bjo&HR&X~b`DD;P82V>WR6 z2iJ?6=UT!~zo#q7@8e5=IN?8&orexV&eI2rZ2IB#`W)N$!+w+?eJme7=oQdjk47FH zT?w?yTAXX7eG|pr#Q`4v1T~rOm{{Rec%H~l^Es|eN`ZJEFO46U*BfsWql3$Bx{|;4 zEnD@>C3Gxw)4+9S_{dAnlu}mq4adcWW z$yDiHl}J)x+xXky8iBS$5Ns{W_YE@X`SCK_3R?#}MlcIADl>7d2osCE-H?o8rDlbH z>)(NPqW6j#xfvCUUN(aRcA!tAuo zYjT==4K-P;@PGQrhmrDvu^YZ3x4Um&`I+qB>#6co)~;x*+uv0o&BQ!#`xKWcFV&9u zyn-Zpd>$W0R_610Dy4;1pyk*}NP%AOtr#i29uLOqDk~1&H7avINmLrb?XN>YquH@AQ^-utSOG_Q3*&F>M0u4^n-U1LLEj-wc@{ z&+U^x80O;MQ$o5z0z&r6Zw_9YOIad~|Gbm%XV6kQZ$$ertIir-a%BnimDhGM1GT>k zN3)q3w&FK{^BROXF^*CHqVWtU-414Me1!K`_#6Ev{Lrwh(@JwDX|=?gxwf%L)z2xt zs&f17ki3}=-k(gotK5}&GDs}zG!7=(nrt&%jW*%tTAeEK!N%Do(_8ffoYXqHicH}d8 zeIw$65ob~OR=2Z$hhtt}^;J~ake%m%_~j)%T2AX+B!In=X)g)(T#+v@1KG$+qp&X+ zSdFP?3XAwC@CI=q4tI69`?m?Q2Wns=J77WztO9xmtx@btq<*yRTC6ilEFRj%=f=(t z+Q5L2*n)DmB~PXDJKWD;U5(vx8Wthi;bc{}oZ#%1<2(#ZHU?HGrkaU$0gSMG$uadC z%W_i-sJHxN0;Lk52jH6=I`EVxIE@S538MatYOohKI#POz>tWkqw_A*TG%As_NTo5{ z;6(qUlpip?48GJJ*yDeD4ri<#Ir}iD9eI0xFgmE8%HQ{qzf`F4fY`GF*(Y?%@kS~) zlP*u{Z)g~#I;Xm)de6ivWg2THZgzwE({DNEBd0W;7_NUK$mYy}7bs~n^pHOLN8See zo&H+M80qpgp~o|y!<kYO0cm&>oJOhI)dez8!%p9WqTt?+|I}GHJ2!L(l%na;XrVcX^~P_ z-?m&B_#9&$l}QB~Be0Ye86GtTrIW_AnK_;e590(69gW>a$X|*01`XA*SSsvg(41eBb%q&f=i(W&C%2pM%#=0| zh)NC&O4=D7mD}N6V{&+O)#)?7Nu9B4@hN@izpD~#2g!rj_N9VXGc2EKAKhMCN%d!P zn}1ty&lbb5V0Z=+Mf0T}2hVl_E!}fe=6Yx*d=pGv8!}y)uLPTeeDU=rNvl*|@GRqfK{w4ct$HWCv!_)*R-0ZeEW&IAomX2RwYu$6aXDJB_V7)_$$hx|)|;+| z)rarip#%}yR#n`PWz&MZberd;s zY8HFCAbH^ihLO{A}l2wapeqnJ|?Z!|7eemu*6_HdI5S3*)XJHEUPh? z58Q7ISDY%}WGjfFj1eP2PR5AKvi!kVC?St^U>cF1Ciz^bRKI*<0Cw$j9-x+<2t0$c z$1|IQY=}!dP{t1wWbX;`K&ZZp^Y3N962y)HiOHdt9IDWd9GVc};bkXTT=YMG-^-2b zF29QLiGhDM$yX<$;I`jbAeQP~47?iaW z^bxL8Tl7z~z!$^PiJ5TIiJ%5!)3@KpT4Ipm$L15cGR~G5a0MXq1gB$!!|0|zgfTZ; z*aaQ3^-Ieg8zHa9#Unhqz>*1WGcHj*JjZZ!SQV$~oo~5cVLQ_oJ=mwSC0jQ3oq_)I zJHRIXDXg>UEOqEnkA$^gJJA&Rz?hFT@KBF%hVin!UyA_^+n*$cjC$)d|T##&-hbc zP1*eLvOtD?@qJIpnIble$o2=jYDWd@!$^hidi0lKpo|NlOnXm=ln%Yo5H2WEhaW4t z5=zJ~f_H!)xZ$GJ^se*a-wbMG)|P1N8!QuR#bsiwK0MUcPg`=rGS7TqUba506}sRX z+x2js$YZ4&CypVkGysIM*XN;}1P&iQI6nB` zSmA@yrKE%}`QfMJw3azD+kz(ttwpNPA(Y#aoEWE3mN#Sd%Eowb5J+3XK?K74ra0A|8iY)cN8KR5`f+-bQ3n4C%8@|SRZfab9_ zM@e7upyiHapvd*Z8dftCv&_VSAkA3X5XCkiwkB-3V*~#0!1!ShYcdZ6GekoD@gn)* z`LQmX8J8Q@f? z|9e2`Cby(w1$vVW_`G4v7*aOo;Y*`}_jQ{yz`lMKNU;evdnW7#DPoUTJ&uoUeSK#N zo-|-&(T;1N4W=9s-HTp(tOlKgSRRj(>{?fmR&W)}>r=!2W*xmT_bokOP z93aMXCY3-A$%R~$EtF;*gWpEjM?U;cqss_Ck<)z1jMJ&Fq|fBVnPRrccJB_(nRzg1 z7~(a_z#SaPY{OXP$NTn;Vx~9}W6MBVkZ5v+Bf+*HFAa?(x3(Yq_i{Fl>Ra8N$!-5y z{*T6!r`Y;p?NW$!+S{&n?-tzCBK|+duEk%%&JWhvbda#&p@Tc0eSK#$xE5k>`V>CMv2@;yvP%=**gJm@ zFXU_Qq|~F4m!pm7ml~vU6dunX1$i+AXwX=kB`g+aSCq5qiVPta@NG<*CsQb2@YbMK zWCgQ5Mj8=zBFqEq`lShv;JGwtfE0ufqXBrkp8%&qtKX5x;jvhLw^0b=)#^`SGvg^9 zmEslXcnsiP0hdjmGc$3qAM(j6@IO>w2cdGEX3l%#m#-+hcwEh~!w-9?g>TNTynO1h z*uEYrpre7xRCZSA2^za~HmrMu>P&S}DcV5?Cc0G9oWetwCTdSX`)`$bw8tzlskj6? zrZCAOJ0(A_5;DciVnGR+ffyPvYUGyWo~0Pz_&_Vfi#L@R`{_Ck*E&IsYlCvF!ZimQ zfzdeQC0t{pynoq$V^%JE0_(Td)CSCyA-=kZe$GT;!G3g-u zM#`(qDz^^oM8#gLJO~YDN~#0Hrah@Pf>GkniVd3bQL*5<(t93z6uKs`nBvM_>Z$j(JEjkmdNo63#M90vBBxARGA4MJ;lAKm44j{? zS6%G^qLplPA7Zr+si2X3u;A~AADeTTX{!053f)IT6&ZbX9Q?R$C}7geDLjCd?(usN zPN_2~<9~&xZ>0FS2-i%7$I{XvH2ooZrV#fcAH=?MUkA1}2A97FHr>?Ii7SQrMK&Pg zfI0hi)Z_JMc|4FI&tgdgn|F#Vz?=9_G^V6feGV9Tu1(SqBWrY_* z;NpQ?h0d6) z$<){mz`qhbzEBD+UjbHx`Pcb=5ZVSGuumU1AgzSS%8MgF!ej#T!_3zqL<_!VW-h^5 zROT&}=V0aWfs<|O?j`x!T}jrkm0_B*r9KyCulsG3w_dsQR?3~WFw*-nv=Y3fJVY3W z!J7hAy`&vqnbP6hL^q$`#C2lIEcfoGW%r_&nNA@3!mG{X1N|P}s_Oehzo1#U| zQbkCxQ~4up-fLf{b*ZlqX|3gqNNbP{UChERj-ST{(goyAdK5Yf9azVvtloKO+xld&0=r0nI}P`) zgh=QGW$5oLHF*RmGyzE@edum}gmIby$4x5|;9f$cDwTxyfCC(bW} zZJ1jV!E;a>+ZC&nCk+kQB4D|eq6V@Am)^nk6@xjQ6Ai~!lr1HjLK0$iHDT{Fb?aE9 zTW!`COhsGk$%iz7{Nq-6bhoTJ~i##hwVcW6TKMwvHS|MJ*t|BZIx{-8Os{6LOa_oY3 zTkY<;imO^}e);ZNz4zlQX`J4p_a>~$F4x1-%lmo1^J*3y0~MDW9_RgyyUdsUwT(M* zjeQq*zj3NPIVZECOKsMMTQBGktp!bs=#@G?N zr^dZk{^cI6&WRh$y0Y?O{}0GJz4G$rhdz^!x7;SKw!I2}&Kqn+F0vRdgX|EE{3P0r z9P3!S|4yvgp*!yyz@9r~M?8t+0OsY`xz$Mb(372-;Y8ehx_!&7TwK2_CsTecntuW*S9JdV2uioQraIEPqbQ@=>Jk&ZObjt_) zy2AEhtwGhB41R!UeGbCS4YeVodov=Q10vWpwYoIH)E1$nJf>cpk|+m!$E z5h{ao1pctfICs+s=Mu`3XC!!hicZqlp;r1mX-VcQaf?TI^pQl5QMpgDKoY%Sw%TL1 ztwO97N~~$hf9i+@Gb$k+BE9s@sF7;yn<0b>+G=*Zhh*kxWFhz#G)jF=jB?T^z?{)| z`oEt6HzV4zM>QT&_KRGuvYiU{T=GAQu6Rx$5&BMT zNFO)|D{$00nYCY^ki$qFO)EEKp*gDJ2MTqNBTw59TBRF%}HN5U3AtR@d|d0 zbbjKnSMh>nrN|1Uj`h^9>!gv+Um{^Q)eGJeUaW`D(G0>5eQ30LV)JGx zr>l(+hH~FU`KY>rB>A z!|V0_>}-4f)@(bNn0LP`Yrto#wf@i6XJxf@)vDdH*~ibt&MH5QGXD7=)-8Bw!;?$x z{10yeONuU;<+I)S&2Pv+>bwFTizS=RE?Kp-GCugqmgi-a|AWpOEBPYmn|hX2Mz_8> zq)H@Ra&i!M)5N>&aTD9d;=&6nxuPWjBP_MK;R4apXaxJ-e>S!^x-zj^XSrfYqqp%j zIk5+Omu07C7dMt>*EKpb+YuJuqZdoF=QaAXH)VPo4MS@Fi1PG>MoY7$!Q1R@V69FI zJ6$0(1i7COOP*{ZzW~E)9HPUw8o+KB*u_tTh^+6q@En0^+~y@d8-zl8Jywx z(1|!5kOxsKLc5hKlXs@K5PX;4Co^qDwo}MVY6|mAbwPA1~ZTUpxBqwKWjcACPAG zbKPt=zq*G}iwTf5I09iK@fkcxf|7!?!OobRm%Gds@q5@l=)L#w`_hlGeNB!l zAF#mj z@Htq=73;!a_~o%brN}`Ki|@`@2YsIm&H|H2)<*t_urV^&jXm~3Yz&xl5v z#wR0H6FliC@U|zrW9%h5=|6#Q)D;c@8T=&1eyL+ySBVPt@ZEmt!tvED)yWB(YU2k{q>uo z;~ZpQthX^YkRQX84XqNmBAY*$(ZYmgo3VwrCAJ8yGi=t`ykBUgU8#9}g&!XON&MU` zp})J?lUmExfzRZw|6#)8wx7b1dLI7drJY}`;^E)IS6kM+Tl|H)3;W(s`dN6} z>Yi`n&Ivd zHj;q96Ud_2eYZc1y@AvMG&s0RPakpjJV>k%e%coiS}x$&$J@ar_aJKYhA$IarS}Tw zIR~tEs$r{gf5G^J(3~z1`MJi>zUt@Qd*oVU*JLV6vD;;_|88qgUTxH8yRc^ulWHcO zac8`IVrvV0d+xLTK6kIZYw}K^x{N=|&%H5xTPHu)0B@hw>fvb{#MU8ie`;e3Q_u$0dY0(NnJn)BR_1e`70FYUeuZk^VjG_^~u4SC6_L zbMKXF1Z-FhuoITN1%UA@_&K4-4qg&JqDAn`0gY(?GXmgIyH#x|K! zWj^j=knS*W^1UMS##a!YaCkiOJM`uS;HbD0Z>@nw!WedmypZ0Ke)v1EmI1F2O>f~X zpAR@Qwf6KDtNoY3&ju@9X{{D}=j2`3zck=je41(x02+6ztg?PngH(4G`?Y-jYSKaX zjTtZhd+j~+f2qBB!9+~Ug!iNP)Q6^b>hLa)5ziq_yU_+d z98IrA!23~3;(uL!FS*Ti zy&^?Q#IyEf0}X?JrwOtYEHm&;v#Y^P6!!I8sYI(VQG>nN z_bAWZtvq)No?D|lr~Y5hY5(atEuPcbmY1o+7jh_vT5woU4k>qs9EP)ayFj_T7g8gY z{$5$hvzRZoD|c_f-8IJBvWsCiXVPk!O2+4tcR!UXeY9IvBgQQ(1FOB{Gc0RoHkD_C z>DuUUlgtZsm7d^c6429w%Rz5>8$Dk4~=8h#Fku#G5^dSx;rX6T~|3 z1+vhS^(khhe|vJI`yKh)&TFCUrIARbJkm`up1qLID4cxVzkbiV(^q!L>)=z)ofc3w z0rXp@Sw}j2?2TuDhCK6B?xxIFv6o2!YU7jKnoL;B zPd|jROYoC>{b$lq(t*VKwp{s{{A44(%EaG7BmM2_c-#7_J>KhVdA6TB9_`)W`ofmv zHQV^%L~fTycgcV6ZjT-wc-o#uS<{o@X~0kz&OtijzIgp+b9v?5yl744_4b&Kfz}5UXFj|Rn!384PPAb+?{fz)ZFWXWSBAAQ|2sjitRt}J5q3Y@ z0X*JwJ!JVjignz&oK}Y#{BGF{_#dMx=V@T?{kz7ZyEkY|gUA1>JVV|iMSYDjJP z&&=uew}ao!RNLPP(r#y}@b$+EkL||p^5j_#kF6*#u$G0vn}g<{B{&-S8NRSwAjh&< zMY$7Y_-KR|-ka*@Q){U5=B`HUvk}0kditx3iiW3+FK61Y2jICw3NwN_tTlr_Fawrv zWfewp8I{L04*T$n__~~5v*rPl_m8QxN$0l9c3QUjE5W#U<6gCGhV2~2#pI30P19|l&MEr!r}Z!2YJV2}QU9_lYsN(5MAH6c zc8tseVDrh|7F5Ho-HNML-1AQ)4XHo~#0?w-f6BHXT{$ziD{-9Iq0m1`HB+Rpy2MTF z8n&W#tfSa#7;7B=7V3LR=zHmq4D-TEMdXNKm&JS?IF?dyg z)-fA@-l@@wE(IHRb+pjF2_9gPK3>?O*!HNMRM53^g2AVDslZ>6&W{Sbq*3$^laafj zcOd^$8doH&?M$}mqUMgj#c777KfE+!mK3M@dzOA4f7ZGH`@Ssr&FT#%{d`n&bOJE6+utNizlLy^(+#T-&%R`}DXhWtN%!3b@Y;h`;+=W(gnu^xvcRG&1ASr{SE-*NT}q?~VH+q|0}j=B{URzX)&0WJPlS zz#s=qEHADDCYF_q_xqN&4GVliiGCn^nYu(Z@FZ{{;D-Gb%qBP z%GiIhs~z#w#^pEN#y^9sF!fi$=U(VoruLNXfG``{RU+PJQ0@I~RynAXej8 zys$*vJAUb^W;{I|$6@QDn^!wCHG5gfmHxv2%bl##|K}&-{w-Xy*O6IhKDOGQsoBp; z{=0t}7|jd8%;+@DKK3%u*R+FVoUsQ!FE4ds&cl9Z@nXX11F&nfLBCXLuavAD8|GOg za$zFR_Tg|G1uJB&JW@noUO7gghpTnY@%7Jnen=u@%6SMen7bC zOz`F+U7ximwby!+2K)Y2Bpw}B$0hV#cT2sE73DgAwj=TYq!sVTHkb7tJLgT?^W2e$O*gqyB zhsK>{s?g@lqmJ|t_O#%=0k?l}Z~gQvxB!14COu@D%xaXL$z$g}C$Gmv2dgv+jCKm6RyMC$Nx-{P7#21pT^#{`v z4dHp~Umdop^mD)J<%{@G;k?gbhXx<3ca1~uk-CeIjTC6aJ(+%R0{DTMRSy)cw-)I_ zw6CVM=qh#(A#ZYCJ8!K8BYgU(1?VI96Q2x{_nhEqho!~mZ1*JNo_3V}3rArSw+paAKxpx6ppCAV z$0P5KTYr}1PQn{b$Oh0bQl11q>HQh@$xwV581JNcM}wc3s^gtUf9 zE3AP?WKfPo&d7@bkE{6e4UZY^8%=!ZImchaCE!e(!pOs+-q$^+karfruYsd-^G)TP zr@`A)-r)Hd{~vp1yJssU=0g^Ig_QU1vHU6lzGOFrg{E@IpzENi^I0t67Rzjm*x(Wa z6FK^*Zwv^fwk@NPk0ymJZJVNk@W^ynqp)xD-R`?ldM6ifUxF3VU@ZJ6WPw6`T&n}Bk8AZn_G=@2ez^Llx*h?4mZN?H zED?^}beS)_qc|n3DOuXb;0FXd8T87L$Q?45Usy29#absLb>j^DM1|oK*s)V9I7O}i zD>tDTehO-%_Aq}$C+!&}-56_O&^{n%_q8}u`f^;!0kBTAK!WLQyF^+t;y~vMQr!n1 zX8W19JU9P7=lX-Sp8M{5SlwmpPA(Zo4#2%sKzZQWBatjwm!Dpc?Bd!dBW@)R=aoDV zP9s_V%U~}J4kH9zc}d4BNFa37~G)}9Lo>&VY zZ%oKC3WHW z{zJnW9&Gi#_>w$e#&~H~$)cNYT;eEOzUsDHzO&xGGOOgm*89TAh?mN%O45`#53c^! zo#{6&VKyUUvf+Mx{|xXr6tPh&SBSgi5L=4>T6Pou?_;In{`;9YaQ|NTR4hV>pUuU8 zBYa1U&BZtivsvPM;G>y?a~*FMDYY44_To&j_p7DGXv8%#4R_A4RK!yA8KU$=9PA+R zq4q!$m@V9$;GYn~UX7Rty$Z1OVubc@YhkUP`^f7O_;9o#eY4cAB>!FGc%e2viZ-TM z?8hq;ZCZ==9ATw;b&^&P1t2%X=2H(O1l&k-RQn$!?$a__cuScwK}K78`k%Kulmq%I`WkMbh#3zA@pC} zAD=2Mxj(G!&n~$WEq7h$cW5;)T5VA%O=RXIaWe94d86A2Twc@2_r-p!?AjdD!aNvu zd1)AJ_-Od=gJ!fSm5`Ub$7;ZsQ!{6uoP&6}Fi<9D2JW3##aQ@{(dXJQqCF?`PMwqw zkD+?8RMZtd(!U*TzFXXmHgCcIee7BB@ZB508T~7{UcCSAr^NG9S5Jy_@7|0Ue)c5( z8`)Ozz$L%0>ymIk*PGaB67Cg`V)fJJcp&_yZ17BP)Jf9#-QvBX8L`9cJ`uLJ+S^60 za4p`br$r_>**f6}-^{W1}r>##HNJgh(Z>I^5@ev)w{+Yc}*W(qf79)Z=T z^70J6(K8Zx_2;oUD=J5$7e~}?jQSOvcg;)=7Ft6?z*s4X<`c4?^DU?Mq2GgNnB{#Y z|8eiLvS;0+RRicBhi&aPcV~gun7z)TJ5-&zmD~aW04;Lxj7Nq=za*hKUnYn z1DH^tMFZxCH}D0yN8DFe7{`HOdYQD1>McOW#=+|hDFfxjCuvK3=RRifh*gPLyGGco zJH+_I+|Vyrx_q6pqJC#RJT%N7)w8W9t|al`br#4k{SCRs_=fCd*++7)mVQFk6lV7& zVGj?t%Tk`Z_*d}iu=Cx}HXF8ggW>v+yr|~|SqHW(6*OIm8C*Wwn{BHF2j$;K2oawj zenI|kBR$UpfmG^-zrFxFT6Sj1^wZXylX7BP3pkU&DFkdkxIx-SBl+0RlW(7hGy^?G zJcnFZ-8vpQKepLKrQGIt`3(8|=N`kJlF;)IyEn?)#>5-NZ)#-u$jnvDoV)OL+irQO zpqk*No}k9Too9*D!-TNR59u(c=$~zBsD9@6JJaN)Gx+ix-#c=A245cMewB`twlQ6# z*oonW@|{TM9ocB+%JC%hj7GC|yZtE+s{&2QZ_Z>*X^Ib^jj5ffpOMXvyh9SKupZBP zZ8(u7!cLTA1NQRnvB(8kJDk9F26IXqgT?UHjfI|;7ujk}UK98VCzP|yu}B=9Wm1?v zc7`y`1lP6DMtT_Z_6l{uWaN*>W#9l7xLC^~_rj`$D`E4z?0-z};WsK+p8JTKAq76U zk;p6K^H$7rS>Y9v6Y_cm36dQ=Zh>aTQSg>uwJO{Kg14Ckz%d{oMjYfj_y&*=;^D<{ z?7d0*oMyUBRcuS{4cOZh+6hfKPb68helo{BL(FmgT+rqje7UX$Mu-eeB};T=`@Iy3)VgEO1|~FavVi7Vd3-BcW5rWE?onQ;92g6hH)91i1|C1@*z_uMolqYD zYQ8|AXB0rY^%?yFtp=+RveGu zNZkK1A1A!4Vu|~iF1CeGt7DPxjsC}q|5(Y-QV-{9ot@0w>3KVYqNZ`@PJyEHX;z(dRTk0cbC}XEv?DE*KKWSTo z=NWM)5E_p!5g)H}f+6rG<(XAcq4Pz|BH&OACyKnF@E10AKoVgsTz>5{!n4_^kMI~6 zp)k&wL*S2MJ*t`E*n3{YNYU|6BSriqPz@L<9v$;2BSkVs3gU{=h{%xbf*>zh+=|)w_@qb1`3O#W_>w*9(U2xn9yxaJ{t7$@K)bI}L%S z47=Fn%}&Ek!!D=fWjH=Zql00G;W=8z8FqBS28A`E^AL_$+&xA3N`wRN8O5B!;5h)# z9;`N)ak6h6MwUdj&a)09OA?N`s1N0P$68I{hCw^AEBCAYJ3vo`{;Rd6LKB=`$-EaM zk3vtGvFc)EY~o_%>2bBK26~v9Iq@qW+(bN)oPwuFgum3q$erVh@&6#=-93K%si@Gt z313R%o14JYi}x7l9qc>G&}Qrqsxn;%hEqAA(b?H`>C5}|1Ey8jT|hF{G9gVg1ZX8| z@W+W3i)LWj)Sc@EwODqs=eAh9imSVghV90>Z)(n1YitT^HwS2JoG#Y}cpTH^LjexQ zc=^kK4oAJLXx(5S5&osjDZq*V|85~K2g-M>oEdIGPI0D|;;Jq^{ATCH$Um@uVj}9} zQIu1KJ@2UGrze)-|F4r5Bj+dlL7SY17U>5!EbZTO!?kyz?7j|FzP^B0c5wP|y-+xz zAbEIkO=e$k2d?>$p;+$goAJjWE6|DC*FTFr7yGc!z+~^dyk}Qq-zaf=?vHZg?el-I z#`K5}jM4DD%*|m1N$cko>B0uP!$<3N{c6-Wv%aebp6(@YO4Iss!>X6YuUsy)YyE%p zCIr?rJy?$GE7^9v-+FX3;y6lUbK6rqFd^`6{ZR8Gu26F>qbjdH*v5NYq3jPlay7_B;)z}FQh5GWROc4BeXsH8ZZOsBa9@-j9yICpkEbTB< zkyk!rhXVLF#$xS7EPMsASO5sq7%{C%2>8_npSA^3s;95)31-yOs5%WOZum!xq>1UP zIvm{r^6D4~bUiyytz-|NWh}&zbq`wbov@y)MsM>sin9tY?|i5*yAH>C5Ou zGL`DFL-dUfIy=>i=7OfZkTBQFjAy~a>tjjqpWnCVg=074y2$!y>WD^)$9kEV%JDtp}j$i(WzpVs*$_`eIy6RO&*o6mO%HBR@tRjU&` zqh|Z3k5<(Ue}wh@xYiR?FFFt6zJx{awX8|;KCQ1*CTO1~Icvxl!w2Q0b?=;Ts7$3R zHEw}qYD7}MG5wM&(0b5r)m#Z0Q&~b~js+6CWeFCO1#~5{;ol@@l{wHO(l}qzBhu&! z8`P{7drJH0c9-s1kqUUvhK9xNXd~v{V11-r2Or#=3e(&!gZZH7lPxH84c4MP>vIb$qnysg%W?fTS_M%7xP3eOY{?3cm=wFmMO zjeHD!s}?qgl(CRId^fw*I=r3NY4okutakSFK}d-o$d5$~@IF~$V`?@ZgD*j!qM^M4 z5&^&&LKBQSWgxyZwT=Dk6CwIcY~%HN#QT>B6@*TuF^Vu2nub%cyo*PiXPr+R`$;9| zYNuECSmM&AY#`~ujj=LI@0xUazcC;-qevS|+&~^<_fdbWEOWlDlK&K^()9fc+M(&7 z3)+<0bLD|&Fz+$_+Hq^fI6bH7z2NNHaSS)=7^>og0a2=}AF7<6d(gy(Kn|uz22EB^ z$3jx32$C^H>QHj?MSn1Af+wM5O83Mj7dJUhV9O&4#67$+WKQ`zOqcJ1lPJ(uc_SiL zm!mPbpY35TWor^%i0xqtHLpw<9vf5V_B_%}f@KMd^BDfUf4VR}=LnRvZggea<^#vl`G=GMmFq`D>kTqnsV!}PeNx39AI zw-*Pc{!rB=3b$EkiKBeNrs|#eQwdX_4T7+h8?<_^MXhw^;smOdJKn(?kJXu+kYBbV zJR5Xn3QrTmO$g61Ic;H2?PjYIoHj?r0zasCK~GS*usblQ&jzE-sT|KE&rtK~guZC? z9%gs=bVFI8F>+Lz*#1(SH1q()$uea);$)bXCRCx`;GEPmtZ76WjRD*c9MRma-RnM9 zV{kdk_bl^Qw6R-T%v$jHT(FB_dJWnMR91R`chDT&Bc(@b$e56^bPCA_r;t8_tx|oK zqk=uZP?e)H>y!H>s7!H?BOR!UGpWqoetxeI-vg8T#Zq`&Qw-i8r&9-}$4#d(cd6Lv z9F1seVC(U&$$?haa`3(FWmsK|4Q8faUb!4A&9V-vxOiR&WmAdu66?qKgyxecPd3k* zHH*c>#OTF3YR5RGm?}s-d^aU%%0(RI4g?@g|j%jSmyyF@^{Q`t^% zRFpUkrEjrRRF;V?fVxwA(VD@H(-_>&mfkE$Tmf^^VG1K0&c*1uWNmp$x$FL{ z1yeNV1AeF?xu^Km)BPf1Mp-VESA)AAzv@)LAj`@C+|dqczJ4d33)p$p1#;s`<)i*n zVkh~(WxsVRC7?V|Z|SjMhURa94PqYrs&df$Jso-QtGmZ&#XO=;;C6WJa{-V$M;>zd zbpKpO9)U5?xV$1^37yMqhc-l0dF2XG-m8=`pS@cT@L^-2d9VlW2T(yz&N>!oh_BN@ zGV5bOk9`Agp<9!E4EC=zVY=P^@LwtD_Q-Y%);Z1kCst!WXj%I@PVD6weZsn=Si0S? zZngyiQ-}f%{32*9gIR<1Gusn7eYXbdG@DB2T-jiqX>*~KYa_371&?7(3m>`+rx~N- zX>NE1bRfRA&6?g~0EM0QGIWk3IT5fMrNWwuvy@?>Nt$3UNQOj0*XCeo*ivXd5Lg*| zuGw1Nem_>Ti}uK$ci}wV>+FMlp;gGSFQ+i?v9w3Wyj&I4+D|8z$0PN#xMBPclD8;Dyco#TK!=hs+8RlIIPLV|l4W4A4OoPP8MB>kNb z=U+?X^Ulr0mG9ilUHMySnNJaJCeobt_SGC`{o26wCzyr&{&8<#*3XXj`FmH89(d?J zYp}Z5NYmW4W*+>^2J7o~g-*Vw0r&qkSljJP$2QI|YK$67*dq@=lHy;O5H?W>EqB=Y z`|pWs{91OP=->@&_2I5YxbL99UE86Qa)@2L}dr%0QT!OXEWRh7X`8)S( z_&T#6Nyg#?2Wb8B6q7mCq=H^rag_7?9Xk2meu>);7?LJJ#&slgRUd<#j6pjB8sS1n zdszJFAfk+h0WRNeWj(b6dRn~k-VN`swZ08*`$1tYa7GW%BtqDEVK!1~Vkien%g6ZQ zr1y`5ZPqQw^>J2>*+7HUI23Ztnf~4bUJxqSvbaBg?GAcvR$EntTWA*@X^-y?jaZNC z-9ioGo41|e#u3spc0c9})V+!7t-$HL9l&9g<9MA7{FIGND5?E86pOrd4l%T!_6 zW!vW|i(-quD-12LEN0bNWf3@$!x+Vu}?Q=O$V2})?@Ylf!UK+Ddc6hD4LJnlTvMs&XjS~t!u;P#!EL4vB!>jLghtYw?^ zF{k_*toOIko$QJ_$ZizS?yqGz+j2srpYa<>UP&Lr@MQ(#x4e&7l@6M|@+|I__j|>k zZR}IVw&-z|#tgfx>Mvs3Qk|RjDUHF&hSZrAJjyrxY?*oa#9bAW{MS{zQ8p9yb5%3T zTKa~ZQTFM1W~tvZQ~wyJul+!@{cC?%Jf}LakM4p;X!kMRzTZBw^pU+d8~Ui_*m>CQeiaHZcD4WYj;;?5o+_tC=;a=IzX-oo?TL+LQQ9QA58ZSfVT=N==Ersx zic?iMd7@h1&!{tFT^8CfNBTiiG}f_pU>L$$)&jWMgL2T^+p&k7pICW-^;GFc6@`d0 z*O<3;nK+H`ax-|-_Hv}2+itb~+0Hlp*i3YP;M?<(p~Dt4cT;t{0h|P%d3sP9-)#57 z%um#oHtYOW&)q~PZM6rY^nVm&p-k6XzsPI{{;z7fU(i&m^*E>9Q-xE$d>`&29~x$y zveOHDHCsA8dy<3_D6J~pe9jZ*c9(Z|p?46d2F z)L8XqWvII=@%<-@{rs+=-U4~O3$y*T;b+c}`_#oTV#^EGrFOl^3#YGF*gM+%Lz~oZ zr&<89x^z%mS!+CQFrqgV-r8-rGo_Yy)bZh#$FXj-1KJ1<5&#pA^b4PxK36&qO#CH+ zlO=m`dybLE&RxMXJ?07QxfacKwLDAjkm{p0a2AM0oPzs|7^EQ?ar;EtBBhr!Z}ZP} zwSXEa>f3gO=51PK?|s+?Ni%n8+%@RqZrbaD(XD7)GMaB(V*Kd#eC32#nO!+S(P&HO z8*OP1#Bz3J`s-bOQ1$PsX!2D|jOCkrdETy!AN`ZjYxGZ-z2s%IpQpKzg{&5s={|5) z4{RJ~>6kBrz*PsTgOR{n2ZQ9Y!&y`&?uW~ae&va19DfLY3dikb7 zZTYKaih2}#LsNaTwW!%{4R3?K%|7m5y?~l0KvIiArk!Z*pPf-!B$xIKCCa zdNFl%vkd8OL2E(LK^He4oaLaiKt9P#-|vxTob+Un=u0pNXYQof(##>ng_f53NBy^> zhg1QR{C$jPs(8x`=+!EXvtLj__5dIiDc)~b$28xtzSszbrorjro;a5a(6EBLg3Ck=D;i)0tJ_UP^>y5QU@L`yGge!@i6p}ae}D0S zhloE3*0pWwngfEm$c%Heuh|UM&AsJyqoKLq9d!NX-Z8a_(7NrlQD*VlEe8(fwOfW+ zfVF!4QG;_^LBLfWM>#Ul&%G`(=$R-B()16pxFAfAGLCDnG&A3X(YlNJiudD!YE5RZ z%^KVT61XSFWCK0phP8L|m)Cfn;bfT&@+~*4zRiJ~A@K!F#-Db+rPKXg`cwXU;=cTf z=^N`w8^peX1E4o5?Ohlj+SRnlFTc9-_M?jZeb~jWCb*QxZ}Y0h`hv!2{KF_G%Ra-+ zuWr^?-rlQxtS^6Y-zd4I@|L(-W2T?2m^%h-0~@^6P0G+(-mmRcLOfb>F9YpI_5WgfZBXD;9C zYqj=nJN+xZg>45fzkT`9%dwY-T#mdPc==n)Wy?2~eU@#OwU)V->6U!UcuSIHoW*E~ zvkbLFTKZTbAUE1ve|NhM76R&Z7^m{Hr>nvi^E$!$=jIKUn~;1H(vdeFoAwE!LRU2J5!wW0rJCW$=b)Y885|WvTE@W%^~9 zMOl|C1h*m+nUzy7KTNkz7?#y?I0xX(Pq^Hp!p-7-6RH20m~`2K4W#JO8? z(S8iA+V`IJlVA?~59NJqs zn_(-n=oagj2-dpxro-O)!uo7z4d^eP^PS(A@@nN;+*ezr?=+tE7|)dzDvW&|>qDFM zN3^R!yay*h{~(=>W4z&k+8pyosts|I&RWcG=5L8hI@@>VacF4v3)*g818L!%rrr75 z&F+B?_k49kcpbA0x6lb>W6=A+S4`+_lc_^4&}7JY<3_t&K;LSig(fD-*oZT? zX^=BD#^BT_t2ANe_NJbf!klaoSS2-pq1LvQ-|j>?G%;JSYfkaoX___hWPRw9VT)*e z`>Rm)Ew5jIhxP)r7Inj^5Sei>xG3(pyHsDNjF?#4+Y)b%GT*SCu_syf%%5vk<9_(3 zsug{rFY1gaHM?Q`${ueqK*35jKS^}8gYX`?|8N~0=Zz6B5xWUOYAy}=T56NAJ{}i+^1Mm zrBO?Hjl)S98nXkC|6l43);lBK1Tmf*8gc=F*rDiJcq-dGanHIEl3(@GSfFvR4p005 z#swPx}DFcn6azE!nF3ylt1 zy=tQrGI;_)}PPF78zEf>b z3Z+v*n#6A1V)L_fNlA&*#L(MQHV+HKZb8L6TV$}kd2pL+a+{XKXM%&XpgqdOgL72| z`U~9!3KyLwnBHkVScfY&Yl(Y ztXN2c-4nKnDZ-U?#X`=;Vj+9uTjCj1)!8Gdc58;Pty*#0;HC;6T&D~lR;LJ`S0@iI zs*{E1)^Xv}>NMfg>)gZh>fFL-)J?x!EM#ot^~J#1^z)OAHk^(j{RrN5*_RjRk1{`M z)WqbN17Wgmh_dl{^&^vXC+mm_e9lI67TXmYt9+n4z3FKKeTXtK{Sr+AwG_z2jm~698 zOgl>6k#pEgyVcTsL>RNNuKroUfR@Zei}rz?13LupeN2xT?0F z9{I8=i+;Wh>$ZL-+xRSQW-hZ(TT@GGVuZ{NUz@d}oywU~-*-{J#ip4B7HYi+N9*-~ z9m84-x>`f|&V`so&|aynGUFb{TNLiwO=#8S$&I_?7M|D7>}M?PUYXZu^={vp2b=<@ zX&wTlwb9zr%o{$bn<3_HcI2IjlG&^ttq&P3nbgLO)~n63dcz_*d*8b*b0+H}`zAB4 zH>m0w=6u^-h7&Zex#@RfZ#1NJoxKT?5Zai2i&-dX`vC>Lm2SpvvW4pgPaGW74_J*J z>$uIjwpF#~Q6t+Jh_lNCRX*)sUZQ%kP}S}$^;B2Aqdfkw2~vV!KLfi=t?>jsR_H!l?ns#4r9@4yRAD4E`ibf%5%n$iWbIc0OZ zm;z^p;jBPlHZ!D}-Rej#FV&O^*%+J-0F9_D0sNwa&{kGNzWSyFM`#&^HkBn@ssEWz zRKyZ+dMmN?0I%Ny%|}i~r{}dV(#{&Yj|2IZNSvF;dBR>j>y*9XA=Rb0TEb(0z6JM3 zw?2gXWpL^R()Pzy-FVqn-z)MQ)ewg$DOYSB_JgK{$N?TjwFBE_bA!B&N=kLO4PoyEe$Gi^p(8hqWO|*fiYMjJ^c8l5mBx(AbNJEf|J0xWoV(Weq=S4;8M^Eqz zK!dG2K1YE){47W&5dYeel-T$TbZi!_0B^jN*D=hnpSHGG?d^iKrj_p3Yqzd%Z?jg} zpl6}|&zRA+v?;LyJ=peTqF}aLoo%e?3-Ard@8foD4ap0Pw_$$OoJ?IRc$LK%}I81T<+wquD)%((NWc^TG;<0jKv}kHtaDS^{J!y--RT0%{y@V1e?C+=6Kwh!()*E9#MVs8PJ}bPPNHY3O zkmXm@4HoauZMK#*6IH9#`f#fPW8RzJg|C%Gw^;w$zH7`nypO8BJHEM@eBBH`VJ*dN zaGT_>Rm(rWdAsTR`gM@Lu7j-66yfd^iOqC+z`d5vCCKXhfK@DOIe;5^Tdh4?DUAx6 zt8pVIb_}XI!RpjJ(^}T%w63pNCrZ)$hYSmD*~-TGH|w+$2dTKwsmY`W~PZ z3)Vx>!{P~yJxr*q;d^+Crxlzq1{sf2*|oD$3D*Suw~hz)q5*{lhk^vwgGv>M8<$D0 zad~ZF%9l8A?>ZsBbW7)ou4u`GdI8-5b#pm=C9nVncj5lkxp8 z1fmyz&7`)kw2gy4L5hQ1o1V0j=He0c4OXY-$ogl5?x6Zo53RPvramKhLLPcZ5#eE* zn~CzM1%>cX+hpK;8=8lw@;L82q$m}ftJ$_ztE^41eq`T=J)mHH#x}ts!D6|fts!Xh zu@hw4z_n<%_C@R~fa^CMvF8JVzH1jQjkGvnf7+9z@N+&|tOvcR#X8lFn_Ixm!wtlx z^_O}83a!>Fg5DH52D4BO?U^2E0YylpRJU9EwMnH9w@Fk})|An9hib~29tNgZQH#4U za0B5{=m3%l2QS&IBU>r=_b<^nBw9MrOFxWf8p082pG0`fA-M6^EP3EQZ;=)X9LE_? zCi%lwh~dg{%{m`&ViOGZGeyxvdsCVp4P;+D8rP*SPKt$gE#kpFAY2GCts7a`&I9Gx zOgbCUN_tn_6T#(zkN%u+`T*#X;IF#t`UF2`O#F!-#d=4ak2fv@56*5?3GBs2>&@1Y zxUovX8nKe7bRm_E*5_J#q{__O;zrdHO^v-+4sAXM1^MJe<8HxovNp`^Hpd61-n705 zUfWSS@IOlIp8(hzuFe?Sw zGck^6UYc*m=@E>mCozxc#2L;F{4SZ;JA*)Sh>E!cE{K%8V)_(~%_e zEJ3$%5ON{+JYm2XIjEwUu9&YldF>!aoD87}H-8+eJTJIwwPEGP&jgM3yx^?;413=S z<9WdcF0J+j$cU_kd~45C=i7n&O=}%WSdcZB!Wq(^JRyvZPVvOL3;D+Fbc;XvLiYP>-A7p(0wo=WXRfZ|_ zd=17Fq_ZC1$SFsnhiP~0(`;DsIJ7&w4=FeQ3ys!R+d`eWTcdR+IP)&(=@)Dwzhc+b4cZd=ekLeevtiIgky`=3evUz-2~xgz7AOiu^2BYx)K$A_9oF7}bAlxALwR z4#EYTcJbKJin{GL%9gy36Fi!;FM!@VcJyCsxrp!2K(>ZKvZeR=+J0kMk4@$P-}j)0 z;mjkdI&ELoMTLb-%Dop!IY#k)`_`TH%Pu?Rw-cvhC;4rtB5op`1T2jUJ2TJB@2QBU zyXJ`Rx}zdK@PN78kB4;Tpo*LdzY!bax||QIQ1tV;powV)jqj#4#dg3fFB)B>(z{w- z5mYB$o~N-;+Jrz*GGgRqCXrYBGU)QQVuDi|)6`F?u#0f}pj#?9^JYbjJLZ{$LLJWj zv{;veHYCxrGyM(5SJ1||=QG6=O=F*E>_0MIqupC|z{PkvEFbY_AifIp??I4}P~q+~ zXV7#vMqBGC9)oT%NDYG%(E?cvS}AG9QsC`5(63*>turs6?iG-k;rD6txGP#*&wX)Z<`Y10{-p*9~wF=`hjC4)RMNS^IVbI!3Z$`X9FUXeDI5S9E{fOu5 z3a#k}ZY0cCIDE>RZ`2e0|5km}-g4*;bLk1nDqwIuZa&cV5x(Yu&*~XuaW;0*=b6nW zK2!s2At9cFr2Bfvgt&x_!5LP9+NWBA^lal7*LVnl>5S|~LP8s8fq5o(e3ACo3S$K{ zNo;PRJKcmQut$wLKGb40*bOG!o@Z{sIiM&L(efLt2U?{V z4c0eX4W=l_e{XGVs;9MrV2EG=c~3bfn9Afv++rld4PP6f=YJ-?FxDT`s$j-?7K7@& zuk=Q#0&h_(X033>NhHYYMpZ;V1iasFU1l@j-Y3$-55_7fsb z%=Yd)paf@^)`G5r60}`%ISIVO&mArwz%ME+=rFr7z!TaS_iCN)0lsv|Mx(MHW>dW) zgs+i-GuTu~^Q-sSKl#5Ws5ZVND6l@Lv@Z#A*h<(k*b3MjY`JzYoyMe3lIaf836H%#n^~HD=^lgfp+VYmg_Eh|a$XCZDrXNjQ{%N+yG?6if0FN=YT#g;GZ< zr~9eT@VY3BtWWGCp+8|6?i~Qn4`W(UHwbfmQ2P({EjXdwRNS%7&^%A`J$QdQo-{;) zIvFL-XV8I;`HVL^r>>3zu3PIe&Sx=j)LI|tab>kBHQISyOgI;bJJo0;4~D*D9Onej z4zwGjABCqQA6Y8x;nn(wOyi?IWLj!p5f*Na|jx+;RzRj=HzXvUYTjf1zKUP60i3t^CD4r>wgK8%O34+s z0UALSI(Fkb^w>uNvoQTNv&MAYyxYu>GPn5+^E%KbjJQ2-o$w%wH@L!{$R>irzD}6H z1{##GA7Fz}1LCQwbc)-q4C}CP%?wS=cTsOy?{G%GI6WXrVP+3moH(Mi63o22$eqCZ#PJLR-lnZF{Rq<)xP*^h-pS=_G5*iN+ap%(0U z(3kF4W4sPyhkShzS9e_I|D_uHqSMtHw6Uk<#7(B%Qf*lBEg&Qu8Yq>!4Zv@1v?zD0 zwm^%paH5*_*2J-9n)%SAq3!ee8EE7iV==S*1CXa+TNG% zkVv{z8)4+O+{6hTZVSr8mu7KW%7pt9K-~l!N$u8>_(jqt<8yTLdJjnQH*IStJ%J-2 z6>-AM=a-q|WBCoH8M>M5s+(#pPC@L%-MYMP8MK`9n>(~SFvG06qe+!Bt5M&WmL_wl z*)r2PaMx(V#cJ~;@E;yG-m-qxJYlqd?QOGZ=9+x>{1tvGJ3ny8%oM*f;A{}wMQOWN z%K@RJ_pZU}-fGHjGRJ^#zatw|g6v6`FVEzm&8fY<+FXqs`(eGfWvyy%GH1;!%~$1b z@>AMXo;znw@>><~Ok8Xo3rq1odd{hf1+dNX_`oY$IB+Nwtv~rq`v< zI~^n?&zVW{g0%af-+{jw^QzqIdXph`IhE)sb%@^p+}fcL%?k0 z%r;6nuV_sYzgvcTqf{GE@(H09)vuOeI?BN8vI%jHa_#{ZOeLj!QjNSN%o1y9w*H}Y z1bxr!j+{m%9u<0)y@wVQ#F}-a;GsdVGW!p8HGn0*R-|Wxj5X$47)O_~6D{Y2J!S9t z-3+*h7Jk&f6g@(vemqtxZ@<>`Y^mp{j`em^HpRQU=XxWLOi0N_gNx$AR+urbG_1(a znd#_T9pywfvnyKL%@wFO8(%pyDyA}ft(k2`+?y(USFfqnM$%S>vofF9NRL=QV>L=R zqvhM|oEZeArmV@vmo7=;t7*#gaTr^{b>{bsC72~9nv`~Vd+5wz#x>wtU>sFu&j4MF zZjfMv-#A_PK0iCVPSBoMn!n?=N~N;9WCN1>9To1Ylwz-m+j&(bQ(pWdqycCgR@vKc zy4$z@+_`_~tHUhaW1<4# z(vGqKh9*!<-tM1b$}aOeW$qY56!W#X;JSGM)gTtSS(0O3gFdo5 zoKtgVp1{88wYU}e%6!OIh3&|8tt&Mb1nkGi!+3s3i~hykiFHMRmTc3Es2EdLq+@pisY%uIBL{!4gn8qL|z}TE3#>T-e zLc$TS3+Co9j1ZQVnZ-Er&(C5q*t3yAJnUJpym~QgF~e7!LCyH;DJ*3 zARj4wP>>Wp$VCbtbf5G-&{=vP2$m!(Lc^%Z&dFPVNb_RZceaK-;5-( z7Z+uKw#YIIbJ9k`E?K(l(*j{Hh8;lRxwEE?g`Jn1TNDF3zaYD?KfPz9&m99h zJ$KsN?yw7ra+ZvOoiQzQNgwHb@kr@?ac|gEE^5zEhnxDkr^8L{;en@M?&7=**u(MU zWlWn3P+$>wGV==v3|Jzb!u&Kd#1vUFp7i{}0&=I|nO%^TTZF_s+|%=?QTH-Wa_1}& z-Cl5~=N3-SL4pLhGt$#Dvfu`Ivh3W#%#6Y;cK^@rS!@{G=<6v+pVtlU_%E2I_B_)( z@io)T`-*Ay;@SEQ(>x3Nb=X;X`B^g%kEwD)vvQ~Bl3UI-v+TL33EaFYT~mNgDkQfe z&8?^~e;SpY@fkjIP;?pxOpy^xH||Zzq8Ao~zL_-;;{t&0GOv(A$jyfoppmDOn=x;S zGld$;8Mm}jp5*46yW>mZhw)uiR(e`delEt9(v=mMb7#$)M@gBoU{1DJAYPHqiD?Vq ztIFt6lrx3EoXHgF{G7~;yo|XSQ0K&WL@vl*l)-pqnlh^}t7r~B#_`Rnxw&()%u{Ak zo?RvX0tm`v@P#?kG7B=0k&5}jzc2&6#bNMDapsU)nU|G0B{O3-l{qZWJUxF(R$hjj zHS@C^ZUy2XkL&Mm;?rOMSVp^P{tFUm#FD&#v?g?2=~WUC6(VJn$@mSm$%#bKl)Si*N)QSK%9 znqm6GOw)>onxW%&DwAn$;7QJ4nyIi~hTRcH_79GCn#<^yiJqcyIB9eYI}O!JbInNxG(XS5R7dkE`mm7Z;mrK$1=PUV7;dz#&^$})2<*kw#^X~{CXR-E znl(4ajfsyPE4neSO&UF#=K0gi!o^KW951;O4$U>Am*G!qOAZzXnqDIDWY5T&PHuNR zbHq`O%ah?Q$jiu}!RC!;ZV|1DSkLiLeF|XH+KVY7hvu&(cpe))W=!IE@w?518Ch6% zFi_!NIA@yZrg<3SU!0T0^_&(ABo^1M+`_rpa|#yIdd65cez@u}^rU*D_7$JEy+7#s=PuuQUGZ%9;Jb5yE&)#dPTgGnINxU92K`UEuftA- z?(O-<9?L?~gN=sJ2wTLNelPc((Sd-$KiSN2Mdk_|pIc-kQUfgcRayU%IB8v~5} zzwVzG*&exKlx$?lNH${Dh-)Jr82--i(EFF)|Cjsk8&)!`c3AhJj||;B^z2Y>NdF(XHB9rv4{)Dk z8ux)r^VlGaFFbReWtvmFaHJBC?rEm^@J*(fkczb?3jW9^V-?d3{FG^W;TeYKDbVnU zmPfn-;y)1`(S(jWfleyxfu;ixcrSwe3?2gBk1#1MQ?iY97-84()B$tSIx#mFCwEt8 zjaI91BM=mS1apC1yZZFuy;+|ykdSy!W{iv+oXH2W%*m6JmhygVXamc6TUuPKECtgr%s(3KR;$t{Md1+4^DV2COR%Dc3f)oxUmnW z#>EgQvO1iNp*c1WMSCfjX|yU{Lo!icr84&AXG~MNsF~*jBmA%F-Sz!1MDYVZt=l-N z>%miTny$xd#%RtTcHvV$JTc_NkUtDkDf?bmE`zR(1b1GgRLD3D+QK<-#)wB_IL9xB zJIvK`Hx(oF5jh=o5RJr{vdmri*T>y!evTLS9zAq z*V9+tR~6ai2buc8Zr*bF(xL!uSD2B0UFEBaV*Njrtt;{fJT6~fR2y_kp15p#k9K*| zvX{f!le!LF?w<=Poy{D;?w^FI~SO zikGikziH?d*{b!+@4q5DFko$T49Yu%Q}7)%XcOGIdYOkz&M7*)9JXDMaj(BFneA|E zIC4*#B)KE4k8!=Y{?<~MiiX`VXH_ZVcjR7LB@cczVcRMN%=Fbf%#hU#rY1NfcV)t? z_qcy5-Uq8z`@PX!lgy)8?`7#b;0#26}tDUG46t7KkxpgwrD%u6Yb zBNfbggwd$Fw2DSm8p71D(^ose>~YT+``6^NBDZ*z%=xbJINwzs=ex?|e5X9p80~>E z>UnNlQ8pK#_(Y~~LQ{ypHo@S4=Fko=husUUGaN8{2d2p#EcWPnv7ekp_wr8eHKNa2 zhY$5M_nVOVEkeDy?_u`hETVY@W+HbLrW5xQOkRXA72uGdkorEG3xhdZgfoH{%Aa~) z$@#)uDZ-Xa{JKgkiBz7>CG1@CGme-v2Grsh=r4`|gE$68ieq4eI0iW-L=aR*=V_>>-V_|Bs4pFHdfGNjnL}i?a$Afzirn?BEQ5b7fyU8%eb5mfdxrbqT za#LYyxkq67agU1bKfn}3D0dP2BG}Qk_x8(hz_C@91vq|Co&`952j>3_jtOpy0ngi3 zErm%CUjqBms%8H|82_(-DsZk2_;y$QLW)bAHETBlbUI<3D2qBNuB` zr?ug~Ha2pD#x~9R6^!-&Hg0#{AEw95;eL=ca|*d*$>Z7tH^*xDvzH^t19oT3yED$^ zi7>+Y7I2MNiPTslgJIH|md5>A#OSlJ8hy^GfPKh;l_|J0+%SYr0tQJdUNF*sfRrA< zi{$tp!P?-#^@lHqa5;Ajri}XtF2ZNNfGxw?^fC4VO3nn#h`z~->tht~B?Z!|xniX4 zjS%T~9ax&=CX6Qpo0(G4Li&m!9ea#_MIOC_&-{(^UWpQL&QdvoSCfm%5t7>{ zcqLXRdZ%)vi6K-DX>RWeyyqwF^-WLz?%?-@OKYmbWnJat@7kNV0DhxoGO61;nZE_Q zgntpR5QIrP7fap^L-OxJZbuw)r*(4A65Tv77~o=2l#27AR0OHO>Yd2u z7~$lR9)y7t#L768iZF1Fa}iBf(Ii}qlXe`}6W|^N+?;$UHx(Bty8FZAxdEd4KGCE- z0#0s`o6(q3D5A&*`v&-U4i!!MuD6(vQrrb-9qwQX72VDl8F$=0;2UY3CmV=y@j6UJ z!v)!32Tm3IBqx7)Rk82Vz44e+(^n^mm{B6kZL5MscL>amoq&Xg{qt!E=Lva|`%xDB z_rG%oi&^~S7e9ioA%Ex|n0Sl(TC5qW)amzIFhRZ8jq`#T(w};I2KIC^?!M7tzpAMx z2v<&zDB21{&A~bkP(4av~SyykE94GaY)I-#- zUvXl;iukrn#J64Kgm0_V6JaWqgm1gL(w@*&#J6QK!nZl4h;MrmzU`_aSow-0Sm8ui z+2hDl{H_Z@jE@Kz1WSaO6HG|;iL^c`LdIJnWPArx>g8>#qR{gps|SlvFcfC`>LDIdcW=(}csU~yI8 zF#p~CBdF$pFOW$iniEGo2PzP`3DUcYq4M9veP}Fm(pY8^wS{JOCYNS*XE7gXEW3$r z8d)8)IeqsnANnqhEi!4&87dRMt_+9U2{;Uy+hKB@cGlO$oi!)!tVhYx5h~-Ri*brY zbE#;Sh~_fUTrQd`MDuBwUASjO_d1vg?m3tqGHQ*v;+&>}AFWksFgbmsHAfulFNkCP zRHw0iXRhD2YP>k&C%_C@{eU>`C&KJl1MZCVe>M$`^?#h^&RDNIp#OGhQCIl{8HnYM zUz^a^0RbT$UJje;++VD-vpB~^c5+LQQT%ryqvXE?8B%NBfe-mF;6uiBh7W>_rx`(p z>Mn>BA;ydRndrY%f>bYpmB3Ee0aFctk3ysxa&nsGd6|e2sA%O-%4p?K%7(+_f6UPBAyL48~4ZhW+Pk0spR`{9fu5&cH+HgK#5g*Z!CjD4ce=kycLJ;l_$P+?Btx9qxOt ze);vfqT}*lnWAIM4_by6eMx*OYWdDTY1OCR9Kgx3S1cCi{Ez>^OfJpgw7RR+G!tUi zsDzmzgGn@MGAXyWWFCxGaxa(~t_#ee+ys~g?qQhHP7zQfM_SGk=5@|Xba#PS;aGi& zMUY$y({o`7Or^^*nBM$y^6^>$ljBNZYBrU@RH|3P^yXK=^z@SBE5pU|IJiBIJW)8L zl8L5VP7o0!ILFv{clI@-t9Y9>uZL30pIT`tc ztaeKDh?L^+iJqb>eYG;tOLWN{@jc!HT7*31@v>lfy&`^MjBmV4{Mhc7_Huoi{_FuB zthK7_Emgd0yidGxePn#_kbjTwr{3gdNp*|9Aqyr~^bNU#4wQORDTaltj=te3hFw|} zeZxz1rNghwUGY8MlWNb^kB@QbzO6x~ytKCkHShN~A%RD|z2jew-_a1veY7_$k(-}- zQ#i9>>iVKn@?LjgF8?o~*ryW|uW>+eDB!Cb_aMyPe;0~196_;0Mo{d2ouJs=m7v&D zBSP^2f?|z~px9jyq1c(AxT{8l;sNv(ASW>Ai?Hk~;vJj_%Nhi9hGlX`T2n-5J|#kP z%738QF`EA0L359fzsyNo)((QM;%A|bHle3uef343b^i6j>?z3(3=lb&tHjlIfXMSx zI^2GUBdx*%esivlK%52KHJGjM`yLe4@F(!5qRhz?5+}@OWV5 zlyR>hgnW#6IFTF5iQG^Rtf_!hksBH+(&v;SH*~zn4V8=B&@Li3)Q=->sGrCU^%3!E ze~~)VU)-}9q&=I+4IL$NLr03#8H30TT_|!xokVUZFLFb9ksInNazg_-;)Z@Ia)13X z2C1B(cnl&}c(TYRE)_Y!gB{#1iouEPxzd5XkUT8x+@Cw#K8W+NxFc1Gc#LZ& zF1XYq!$r#Ge_hI86iOij^(fM+las7LK1@YJHB5Dk7Wev(NkNhx6f_~}( z@%JC-|Nk5MXZ;8I#k~*7z5RD3cK-X426y&WBMKwx!`5ZUx86mC`}d;3{39A2(OM*` zphRowpbC=z(;^KGXDKScLFhQqL5G6(~Qet?K5~EgjqQuCF z5`!}#FjY#T#K<+{VM_8dcT@S&$lpPU`R8bT9ulpO?@a64D1PO6(WLzlQFM-jiqqfP z3RBS#A-_Y>|Hss~|9vW-S475f-MU=)PMN|-nq4{U`2M#cOb}PhEVLi`#z6(Xm)7?` zf-{k>(?f(akKYZPeJa8k2MAL%4E#5Tv#<8{8mM1)O!mdEN=e*HCHi}`A;LFW*Fq|1N5 z4+s3Fyh|R&>Tk=t+}pFiChJ1IC`r0Z68o1!j~1ciN=Nz0O&nwC_X(E?2ai3E7dW;7 z*a<`cmPTQRG9LSi#~~$Sh6L#nt_+gXf5aYV7q=f2$Yb0o?l0V5u{Ubuns7Dcze5fo zD8&zeT}d`4()uZ2vA@+rPI5U9!leDeze1+wUy;ZER4&Ku;KOf4uG=d+au)@V3x)U2FY|2vyW{eCUkgKyn| zgU%6ggPkG{dLE`kALuMS@>`sp|9u?vP}2Tt<2ny{cUk9?O#d?u(rIvcXlzD;R;A=1 z$&ML)DR)wAU6NEBh}HiGJoLMQ&=pwo7l?eMo=64is>n_96s09cAeR&Hd%csirJ8$N zOzp{4!*=Fg7HMA`=6}LY8sJAfUL8ysR}cP$2CIkx>xu{BPUOylI!5q9oG2>iC4|$@ z18*9Xu`lu)1=}4dqQHgF{EY96cW|MI|J2_~{3k^N&F#OZ`FxbD@4Kbzd3o2ncD-I) zw5%S(=HB`Izs6B)z^XnNkidzpS%Kbi!Y=a_K!qH9MK93C3FmCaTL@ycz$UEV2<$Eh z`2cnde2Bx?1292-HV$hm!N3vp&3>_;t406O-2ILo_XqXR1%0Omo%3CAETz6iQv9gL z2_{Ct3_zX6as{BGGJH!3s0l?3nioEHKwL21J22k)A_Pd%w!=gySS&)phrcr@Xg?P9 z;mY+_WVgA_XXd;eQ1G+(0a}KBcS8Zq%JYAdwvB6_xz~W(_vK2&9`*z*(3m$mdbXdV zXWw%4tXv%9a`gNG#5&H^h|r-FDc@2*sU7`9Bb{(dn)RvQhoclp=v8;Xfj20@8plW{ z+>%DR5~I5(mjYXZIQIhr?u_)#{Tv|nbDG%C+ka>MT94fe(n#v%49tGI)246YBCS11@%woKgFP$DLv%DvS_pke(qRTJzPCzcofsD zsHk`K?ebmMQ0*~wFZMY+l-zK|v4Ch6js6PY&@MrCD!r%DT`WJvr`Ez>9e@f@xb!Zy zUq^iHF?`oo3P);AdxXxdNZ%9V#|F#?x+SGwj*=C7ET^2vrz1~9M*cPxdqu>mB0+@J$&KAb@X;ee~aH*?omvCY7d0_ zqPIgm0@TjzM#uL&InN`Wk?4Pv&piNri~jP64M2bSqEwFZ!j1S`P&3MfKYW|1%-uQ9 zdbH%MF2&U2K}S4>bM+`;y~psNBb2|dtIt5$5!n%+fxfP&JEC?`a`rAt2|mzu0UlW% z%ki%Cpbv<@CGF8P9K`VwiE1l~F*s@Q!cPiW(oSya7mS9ce=xlg>f8B$Cq#4bU|yHPU}f!IV}b!I0QOT&*lz z{QrrdnA(n8E*1#2ruLO7{gi&4#veg|Oy(!^6Kf>K4+XlhU*?Ju;3vTgwYcMJc2Q*Uv(QBzGR!%MYn8cjk+LIrT;Zk^O4%B&KsHOZhH^l8mda*hkorpT;jc0d662!iA<_5Vma+F$y|g;U-}^-*8-=*CUMEx%0n>pr#%u9-)DkBX&HkG}Ii zG4#Yx%2^p=RF`<1oO-bK*VEtaYrAlAYKaHcjB;{HPWt(;9!)t?o^j#JFm^vS4mo~z z+F!mcx?VoFBR8ky)e|C@pI*3nLQ--vo|98gFLceMTq(z+$T2DTAC<9j(@|e#2$hY> zHD~>z>x-`MT~E2Ko=~`}rs-hqxV(-s9`!YkB;2R=R!HXKzWqU zRgaEbKHNgEQeBmlER~SjF)qBi>X)^Yd}^9zub~)H*^(#hU0>5w)3kT}>4m2kCM6Rb zx@HbJez4Xxv&_+oRKm#RzXg%QEhncM)l%t_C#;^(xJeKeT|Y7OsIP10$*I*Xad3U(~I{v_ad!710wjus?%j0>lB z{k0qi?kMpn?Jw1q`gB~L)O!m~xgm$s3#ED$?oy8~?Ju<;_3}~Qz38=H=7*L->vi`EuCp+aOEj<2&YFYfUkDfR_$7x~W)Uy67Lsp7oFfN=%pi!Ott5DeVQOS6f@r2mB z$$&nmg)3h?zAxm=)~_#pm;O`wPa!{T{Vw?H;*&9N94q0cCWOROZsAJ55|0w!#!dIu zc+vH7>$t5Y@0{rGG$1Lt^of|Gc|YB}{bO4&{%LJn@lV4)xUJs4)t+|qgRhpo@KF-- z^E(z?GK3p{a{9gF#CA=&4ckoX(XHs;(W)1N?c43s+OD)^iup--QEp;>_F%j5OXTNw zY)DD25$i;1V5}4?WXE~Y`pPl)aO-hE1t-^dxYkcqrR%4C9iVLN1Mml#@SA^ z9JQ95JNlM#X+&ji8=n)SZn;oO}^g^14 zOT$Zz%0EV5F*cXBoNP^MEotVOA^vv7c+U8_@rdL9G4iR${~YXhxL1uUOA;wJj*API zYFyLQxT(a0=3+o;|HvmBzb?ImT$+veBfnq%uQ>Ai*tm7|3$B?;Ps+~-)N))N!Hn&K zdh}?FL7K;tl84j?!jRh1*HD*w%JrVVmCB2d&yPO8diCDz2ah*ZsYlb?Px-}#H@zna zG(&Z)Ij)&BZWh$WzsuE+{7nUp!d5;FRq`;jYsDQhqf1+b+=fqx|B+%ZBbIp)RaeD_tNaRg+?~VSZ=Fkbu-1MdC37@N*YqBZUFxHbF)XFJxe5IoQvDk_ zQp??`tL?&}+CR@-=36>+;7jlQ+G->Ws{QfPn0?U?sQhlNsktYHl$Rqn^u_Rt!)j79 zOOm2r>AC;YWy3H^@BY2tRP|oTv%xnpmwy*svfNmaSF~${2+8e$@Xoo}E{w1oIyLwu zmptS2v}3{TX}7qiPD~$i{O+1Ax;|!M@!qXi8)!y9a`J=KaT(+C_N{MvZ^T6bZ6o!= zBFl)22agx-Si5lf6VdzXuhzHKx24?*{(kEj=RCr6?)(;A|8!mSk7;6l!L;t&+Ir^5 zq0ukKJ(ag<_omrv_N~9~rGYzcY`5;(CT$zdo|>$OEO}ZkZJe-5xn%l$CHtkNj1NgSF%qm9F^3(u~OEcds9m z^N{2HHmTOdyi&67!$Th)>aoA%mC@^tKCvRhC3E)j>MD$`<5jz6txtZ6U#48Ad@+Xp z>y*pXbJxz@w|>DX3FbPNP!NV+98yzQb>EKrb~J7h|LYq!4cgI+JwiuoFTQ@Lw)ws4 zU4^>_?m!E?G-$_xT?>wP#`ep(U;dvH{kFh-6MXxVIL%%T8Rv3{!IxtjRF17uIhTwl z2hVam+wmO7^8+3ac{w)(PX?ZHJcsdI#nW9;&P~9x63-Dlt#}42%eewP`|;dX4pR-| zCx8F!bJudbZ7~re=EX-p7ThoS`M0tjg67MT^QYFNs1J;I=e?eK==t^beX5MK zKY9*N9WdgRZihbE|IMX|*EelHbLMc(7jHD(_`_xQncochI9dH>#`v#Fw@%w(`F=rJ zXe^MVsZO>Uo~e{K*`!W6(D5Tjg#!k$?T;Gw0)9 zz4&o%{SPzt=hqxv_nH5dKY91LHM#fEGetMToEC=fdgl3aLHnu)MCLzqJ?+Ax-n+j2 zpuS{NnC;xPUPtyj^V4fuDwQ#RUcEZ_#=?jF=f69ClP>O!;Q<%M4{U$;>jv|>jBA0No@cr)ns55u3I%T+!nWnZSQLAXVyQ^f8Oj1AGF?h^)KPu zo8Inz&1?Q2hktN?LFzVpM)7CG+nR>HGUUhUgSs8s{cY~+Y){XsIa9(7uPiD}?0RKT zPfe@oo6CM)t1O&i*o|-A&wuc;`tbC$b(&>Q^~k=c&pvzNr}jTBeB4?R{zP| zLzxe&2G3sFcbG@nx!1l7l_}GPHzei$pl-QUw0of6OZ9y|x!7fb<~zS*C0{-}+}HO1 zvG*;2O;lO`GkLU0)AuudK-0`jnig6LiXc8{3j}ag6hT+T6@+4VBQL=xx~{h1qkyn& z0i__WfFdozXL&8Ut2>I2K^_SLX23@Rb!}R}R8ai?&Lk;mVR7HP-~XeX%$&J%-}l^e z&pr3tbMMI=>${=8Z{efU6OT@LZpG%^6ZYJ{WcIuFrudgV|LyM$zxrZWk5#$miQdPT z*S@BoRk(NbuJ<_g-YI`**>$Wi#2c)T-8&2KeDblRcTfD*nHqcD0-Xs8LsaU0L>rH)k&!KYPOR*IZL)sP1iD#eekiR}q!xmp&)0-5Wjs$rm?&U$=fo zR@CsOcgr5D+A}h3)eV_{^#8WzV@L80QA1~B_)9ZyobbbDv7xcoxt32WYyQ09g`KTc z-|rdzP?&!=$!&i$JJ$k@8 zJwhCl@!jUno^TP}GE3bC%|L}-M>pt0fUcB{%#SdpZ*>lBxf7;*4xL}#I zjR*S+1|UD)mUKm6hGmT&uxp7{LNE!m$K>Q5b7cEF>Z_4zyH88 zgLU`6RZ>ykf6D!3d4mqF`QZM@t~Iwz`NlfurM`FF_M`8KL${c{<9oa@^yY>A#;;3% z=Dvb){#V^O@_o11?pa|v-(|_LvK_mBbM^HfuRgNtxAzT;8}{Q{EAIZ{>OYOT-*a_c z-s2U`uOFMGy2dor`SyohzHQ7bd-qATR=4U~R;AI!n~LXl>NCT;`?(~`%~b{WyfgFU zM=z-(qK!o(cP`Jpb(wI}%RR^M-}Lae@4d>|p4UbtTW?!&-1rBDfz?RxTPj<=xf8*4qkZev@Z|*&-AbN z{(kg_3;I6s!&lCYkABzu(-()={bEV?2mZLY*W@Fs?^<8-bb605;tP?nS-q#qM}K$6 z>$k7GyM9i~_f3CT+U3qS2h7ta@`EaGc;xgM|EY70yXG5GyZ&;+<7ZDeew}&EMAusb zUxYx5O;`2E_)zV>>f22FpMIekBgbC-Leo=O?~Q8}bvHkxombZF7$29@bJ2^R`4XQV z&}q~AkB`s&zTu-9{p?%5oc4Oe@8>@-_Grm@e9o5*GMn#d1=Yv?aiMijretM zTXE;o&8z+}=!wY_`dEjZ{mqseKK|9xSEEwqbh&l^S8q-~^}D+wr|$GWKX-J@gExKt z=k6bzH-53Y`eDnv?>v^!f8im{R8iQg@7{YCZ*%OfeD1gPM}F8bs^!jo>yq>Dd*zwy zuf1d7q>`1{1^rzA^XO}{{+KrSn3fUxBc>M`^$aKj*X8n-^@J0yvqEZIm;xnUD%u1 zN$hiMJ?ms+R5sNd)i%`+swDMn^(yst^(h?7*-tY;vrto~ku`(0zta9%yIL!1ztutv z$nwMjGp#@Ublb$TQPayz)5=U^raU}(;*?QiOf&5CK7Go}X`{b4D=GWYoEB+>Aif$)q(w4S36xF=Z3ccxBT~ ztrjYBIcp8A|;kydBLUCB@=BcrB0h=!gr4ec>~#<K{Em{L!-9>9`e3!n3O_#FG5DSVeW*qQNj^Mn93pwp)W2j{302&A7RtRy zn0)p(^&2&9jA`(#gNIRb4H#-t@XyrGUN(Ay>29E$iTsod?N7C2D;aiGkG@KC1j64s z1r;!P3~oS5_MT9*RB_YiOrKFU2_=|OHhRW%)1;XbXN;SQN}n-yhJwSuf>D!|8hW72 zG;`{M(?*Rc8)Jfx0QOIs0(2zAFPlAM+Nicr=UG!Ikx^r3pnXl#%SKO`3}k(v?7?x9 zVW-m2R{DQHBY#PI>ujH9RuG3k@OpK+uf)sLQ9tI z9ISZZJewHuAE;337Vu-jA3kO<46ue;GSD$?qfm`w`ixfUUg^wAhhx)2{x0szfgk~I zP=09_-5oPWk1m@&y=+Y2b3`aBrK4t!>7!@iH{d;l1c6)-h7gXZtq@*O=4N;A!>VTo zU*^z@6}mjimmbQOz{?zZu|l+?e7Q>b5_p+IFILPWlrL8+Uji?4u0|J#vIdcH*p!*0 z?WUV%PM>j}P2-r!ivNJ)9iSL!!jduL@s$Xe`ZRlNiL#2Tu=ntgp(k=yQ~1-~L+ zEOcg|@uFd%dlt()fG5G~=2)gm$1pbm9`xgHE##N{J)vTl;iX+Rt;KUK-YbqcN`~R% zalmWe$liHs(}s^;*Z`~Fm5eFE7Fiil$(r<)qsFOViSM|b&3S21<-l5d7T)s9Ul{as zsme9J{OMB7p=5+$Wu{QOH{1NFDmiD>IGwF(U}P0zjooV+H+Nt?W4FZ{BWkXFVJP#| zP<{0yFAipAWt9&7uAVLIE2#=^lGKI2lr)7$_u9)>jZ5zRRK2x)#!bn+=hjyZjHnuK zD`Cowno7e0ZROnZ+wYlrQ%Q!k+}iuLe&+F&1EVUnRTFM{s)DJ|hr3qWZ_*h{;>QkZ z7^yQ>mJZ$*S;bm=Nu$QG$USR{Kne9IU1a4d59Rmnn<&TD@@#W*?@v{8>&Y!fwko-q zTYvja$vIU6?aJ4u>OWN>kEW`D&w4_+9efkLhrWkGeX9D#6R5|S>WC`c$e3!oZO};0 z{!`OrVRu2RrxpBP|HO|Z6#Y_x6Qp*pJ8uTM`qN~-12s= z)l@@v+xH`%zE@i{w>*>sXpE1qQ;Q*9(uQX0pc-xOny9ruj= zJ^T4hIUM^Jyoh+~YM;I(jHfxMpIe)*o@ z+Z1gdX=Zb)H}utfG2vR99k|2h9JkNzTshEgE1u0*)q7EEvrSgpp;~(?%D|Y6l_ST` z9r(EA8g-T&R~?g)mt9xN9_ndhiL0IjbW#PF(=sAH_rRr-?QkgjQOV=4c@L$jVn}xDC-rf zafNF9^;F|_XPqa+Ys>?Wk-hb`8#m**9;D`hU##yx1|Po$JbdDYw+l|38nX8Ud)spx z=Gvm|ai$?YCQ1ul<4)UMwjn-NAL2QNeD~AT5Z7TXA98xoL*=EaPwnO9rRsgjCX7aM zVFQiULr%{wr7?Ux78YNYE6rOx3!09R+gzX-9%i+jX|#CZg3r+ zhjAT9ZCZfu7-wS}2O4fb$gQm!W=cDrLsPl6H5%?ZX53BTT!*Im!JBmbOX9~25?gig zy8gs>Y-wiWdWZOqT$ED3#kN}EIVi0F*FkxwRH+=XZCr9!Xjh@IVs?j@bks~9k-)q%K0lp(r;X6<&6XkxgExvz%>*$4%eP?qr^9JQA?&PJD;9 zdj5clBl8A4*Ma9i%>Zlk8(7nJukWRBexu+-YrkjgQfu^F;yW07W=_EgUkPy@(RS9N ztGmE=5XZ5Z|K`u5exs0_F=dnTIHpbff zfb$5!#CZ@*e8(2Wy*=lF+&*>ro-q}?N6m(j<}W4;IX$;KaUR5D1c<^=-vZh4CL58>WWwAK|=5T|3@m?f2HY4Lf@;CrVP}OH^hq=OF~@4mcl^ zV1m`niHsHd)1n6ZDT)t$z3D&&T(lULj~1{5eX!?7XKH{ss> z`%R--Fgt1ieBY<1H++c+>k`1XWqy|M2qJq0;eS}yW2{jRiUs$Tt5=O6t}ntia(u;x zxN*Dfa|f;*ugkH5TOTzcWkvbG_v%-UPg+r_aAKHMpk_2{BEgw4g59Q_Rb^5Wfs)5`@9llcAF;We z|H%$c*{&a#Y1UZ4$5}NJYrRpzoCdMI@noE}?_Qg!_`W#nbrNx&qb69#gY&bk9B;*} ziTFiTrFoKi4P&Yt_{9WuwaUy=ZkMPrOVM#pmyexTk)^8I0AD3p3DQnRT|Kvx-bgL3 zfzwgWy6RxM8tJF*Z1;In8Pg`uKbnKC7w4dQP;^DT zYQYvew&&zW9sb_Vh;`zv%!X3th^=#|gbj98&0t1dRbeba8S3lbm{>J% z%|ymjK71MSt*ShX`kuNe#-<;PI_=8r)!nQ%C#rI6=lxHh)>-NQe~#a`iLw7?!+`QX z+UJ%tl{&koQfFdv)s=ZNW8r0{y2v)D-?4Pn0=BYv#N3FC{hI1`(?6c1%Bchn8zd%2 zRl`=PxVa-rbwe3rF>6&HVofTU&1pgX4k}jlQ&qE7rNd@rtuJ*QelqLr(tU^3RZoFX z#oAbNESH^;WZPP7DAh4s_g9L}b@ ziZ#zGR#ALr#AlAR%*tS19h~(OGSsP=1P-aZe*rwX%j)=%n z+eY`BY+QQZ(unN+b30db)+|t0GC7*1jOkvZeo@5IUyY#pXSuCd6A9I_`ju;pWBWav zu79OCYwK{WwGlbh=6!j1wCy3=y;%{aiV@3fsxEsEGp4TcRJe^sN*|5*XQnjLR-E;W zOk^$z)PjSESp4g*!@59#vJb=911Y+q4TA^EGl&&IwPE>01wD9&H=h z|K8GNw)g|ur5_oi_N$gwmqzWqyR&xb+|KuwY8OR-W~*c-=R1$q6ey);iFy&$>9PHh zOJ~_$xi6A?wXF_Sz*L6QysCa>Xx6FWx_rmsX||zROKj{?re^7g=>tAI!kP?d@zzZm zd#rt~ovB<|{*5rS-}FhcodNe}Dt`}p`Io{1YE`svB{r-rXH0)Ksuru4e>);V=$63> z+lvdS{RCjOFxGaB@y>n^8&zn(o%P#?M_NzryEp4_ePoy8`=;6$>r9Da!p4Nksi@~? zZEEX*!{{5=sTbYR?-koVW@(0MQD!=hnlqWW-JMjg&a(A2?iwCxyQ|+e+oQvCjk>;f z^?P)9obl9f=GDH&Cyl1Q*Ufs+_JmRWYB81A`V}zaAQNNL_3RZ4SDf|eaJ|(J_g?8Y z8fO_zH(oW%V$|JuXTRdC=?HQ9Fk2O2z2Ok->zS6>SW5!R)YG=TxD)7u7I4Nb+lwcF zK16^%jI`}EG8|iZA9G(ivv{|0y{(gtF%9oG$@r#?Szc&lg-ylmD?LjiP#aqLCy$){ z48E6pOoGMupzZhQp@thDpNaZG+0P7DTfaOEobKX8Kh&UA1Z>y%%W|p9x0%lP+?*Bm zb4+>$Or9Tw-dSGs(b6oHRBEg#WsfqZ*6oamk&Cm+OMf`La^woTE~m%%ot+?IlXJ#> zQxG#OM*2o5&U&}hf7nz$eG*|o=?Hlo;RNJ2+Y8wBO~whOo;}^Bz-SoHs|mP-|rmsgNVq6jeEB4&;o$3hZAo>5!i<#?8Ag zs=B1#-NxdqN6>#X)#at9Q1{d?pUjG?dS<{$T;gh|KC zP2(xoIpfq->n7=qrtuogLKxFn8Sapk4VM^jAB__t-*_IpQO>gcJj5>*~EH8ceu)aoD&6tK7V`Q#8s`_)ru(YJ# z()%im^Gnl?a^t@qmpNiOVtco=38|>7ijAlzgw|EY;2u>SgE*MaMtcGhQ^s@-t$ewW z`3m=Yh5Nn2{r;o!?#uVFE8H(}$5*)DE8OoD?)M7!8(NjU!u?+1egjF`V)SM4Akgj|KcvsTE$tHKx3_9c;Zk6AjlL1ql{!d)war#`)kMZj zQsDPJAGF>)HzWrRq^y>nYE|Vhrg#2EDe%QP=qg>DgOcdE^{UE{6u1?-Baw$y{pUdn z4AI8Ki>1KoDpg|%OKTS)DKOg_F&9$coZYRuxu1EaZc^K#2F2Jkc1?r+<{_txr{&m; zkOR+A|8&TKwaq%D8H|m`H~zim*y!kU z5kCyhif&aG$L2LbdfVQ|?;6?YH=EfoUy*r#J{pN!j7~4gQMc-{bU82EqR+A|iga0# zRzG0O?>{(8)f#twKpqTfu!%hvaXM1YH?A6y@)A)V_V^%NOoK+?>xf>u0X3l9(X;6-&*65<85jp!SI;$3}Xja9dtdIw*8(Bko zE4ve|pkq1pS>36ulj^vTOgOd?M{u6g;zS%>tD#71J)y{ij~|XO)s1*EOVv#}%;a{J zH;ib$?_ZJ1lUb0P%zn3Y4`jgvRhBM3qO<(2leTeyer>Z}mo960j2vbg@Ws*FY%EvOc`2mk-DJjWgd8~TKtiK|)$hN3 zK-Au~%`7{&GuFTjAsMhAGGLVO{Da2Mt&t-)M|`zk`^x*xk-F4Y{Z7^raaQ+T*2xIe zn#uwxuw`ggEPUzmKRv8(W>pJpXctRj>op^99UvZw46aqvYP7~4Xa7c6SuTMh4ej@6 zP!gO|u4}wJCa?yEhhAf&CaN>mt#>v@=nQ9dXR=OesofM=aD>us7$YDF*0o067HK`P zZ%o#g^^skV?_;`6kr<0B`^l`QZ0c@@Ae~*+tc!lH@jac1k3PqKuWM9C9q6QMWFpdx zFArzVvER)Y-WgKcTl>uz9tGFb{`%I);)qt=&G=@4bhb6RSZDnj@u-@0TBh;6h(M^~ ztQnC0eg}7T<9m@e8dLjIm_SVQjpV-!=TAo!(=fh3t1H=ub%Y8w=U58nWN| z#t-9Ekp9w2Khr_}+ozrUH(HVZZh-tZryMvi&e+=B6p;SPo&=%UL;ZffBL9t4*t7((@HcrsbX3e_(+gsz~+5RN+UEZ3^Fj&>;0hw>(1g3Eyt1@fgPCl5b?yyo6 zlKH}CyqaXb{YmBvL(smT3?%c_yg@Qw_%|W7Mw~y~pJc?0Y?K=(U}XhzUxYN3j0nkn zKR(>s2K-iCEZ;RyO*BSc;!709u%~Us0~Q^Qs)>NyH>!WMY$=aiirUIaYQ3gteraku zsju%aq`m!7OOWBi>5IwP}^>@Qkj?UOkg3ya=) z1l7jD)?+>_fiw5VW9gs^Qem9&umIkbQoAJqrx+EGzl90R)vy!}w+|C=T17X4{0Ufm zEuwT6z?L}MouJ<(!L0{DCCSWgSOf(Wo5FmB(11>*F#BMe9?*xW*imo|K`Yak7`7Kd zZyTA_un!4nSUUD9UrW%$3?`QCL#aKIiRQVEpe>m=6X|-&X>1nr0&@dFOS7DPpeL90=mQZcnV`B7dDM6!i7=i6amPX6X*bdiUfjB5i51_9b zcxEGPnsV?bz_RH;(wWJ!AjBZ@SCY%*v4bfu3z=T*Z4{!gh&ioT>txK`nOoSQ@Ue}`n607d$;nn4^HjA zM=8g3*r9MQ+XT*fs?5IZXd+-W+zkF ziowiL*r*3I_9kc{VS0z${{lPs9wMmpX4t)*MtQ#a7VPbtPVv>>g8a>(QjWP5i>@=t zpZ``^Ih{pcw+~_7Lmp74Pu#}zXJ?b!`?tew4ne;j%D9kBVvw+!aK=+tiW@i^4I|SYJIL?XNL}^q%jy!KBESdQPQ^@`gm2K6Npseqbzx_{wYBUg(GZ)Yn%HQO< zsPC;5R`V3_ZyWUr=_#DTy`7+bzh>@bcM$Z-Gt5l(_vA0>S!O5xK@avl%XDVnBdGZ~ z>mi~J&&=leXo8_{RiITfpoG1q5VU2$xT&MDdHz&btYEa}nBk4=5Eo_+_+^CfePpn+>KmK`Uk>pI}y7X)>F6BgLNB*^d<=-O8VoqvmIhMWu| zanpL{I@UuJB!2@=a`DpFa~l{ZY%2r$v<^8wNzmGQglr_}rHu&r4Ms&~<~yJ%e+W?u|`TR1t! zX_mKft{9KmwSyC5{AMwdk89__9r7S`@X&CbYeDGJ1%f!uzO9JUZFX(rq?jhN5`+&# ziEl{EyA_Gy`}V;1NM4NL^}OEQM_hDW@QQ>(tb^0R^Q8h%?zjuzWr`5FrwH3}&xKcN zTB!7?Tqor}eP0vbC?&ePx?=ZqYmRpGkfJOnS#F+R5Op42RB<&Hor4$E+)Baq4lirC zH-$(6?GPbID}@MdGw)i(d$rs~-m5(8gU+#2P# zjrVG}HN0;l@6+I$TqhuJ>v?GhFH;_YZ!+>Mxb%J=$;@lweNm1cqQTM47w7KMlCCq5?#6zJSX+oRqA1spY&WN}$!8 zm=cJlhLck%=Ji~9ASpN)1Lw0!n{?zHqKCuPTQzBONSC$o{$*Yc!H z3CO?$1DXQ&WA8?N<@sC6kiEQ0tH0K1h{RXs1lKgUWpwwWN>r!d?F$>_&Le}ENA=k zP+4k*`vRl9JTeMoN^M{RHTcX{FsR%Si5dA%XqFqml3*3TF z@6S7-Z{oc=ht&mACh43ODMkPp62utLpIl$8AZ@YAF@DaqBTtHM;#_rIL<1fh`BRo? zxB`(0R|GLa5Lt^1+;0%7EmFPUsuxyT#9E6E82y?B;8xzdUhqC|ky0!ki?kP@0WX*=qq zi4*DJp*M;84fw-Y+qeToEX7LYdF_B z&if|6iAP7(2(IdjE{a00UdTzYP3Cyc8;f?1<>P>Ru^>YpkQ<;XhzQ6Io;=lDtdo_~(s z2oajSh+V|^jzN|bCl@*Z5!z@XuYP(WIv3sjW}gzj z2Mz>LMgzH^EYcgL9m*OXB*g^m_M|!WZUm1kh;Le0cSreN$R$_SSd}p7ZFkbn#*+g${iz;GERN zWnK14Xu5V&pTIxR_VRv1DTP0Y(ncN3L2DYEoWcKt!Erv?c`n-hJzed&4=@PfA;aLT z_V}J{>?W$ht}ve$z}R4zOK~|De1$=wL=rh4NV_Wvm>0zxK-;3+fc)m@Hg~W?iaYrL z#RDgy1OPp}_(LG97^MW3gOP%UUKA-M=IEGMAbauQ#ZTK$0gHVRLac+Y6XJw= z{6q}t=-kR(qC4m$JFH48bzRz&Hd-nSjzJE9DMrul8ejnjohC%dUAx{XZrM`*XeVh02w8 zN=(X?(=3uvaHaFU3|`6zN8J!61u`4wxK^z0gKN#TveAN(g7>941u4}jV6+!}sZL9p z#{w1rKfmBh*<e{%fQu9sz# zae*h~z6md6a(EBRPIge9{?e5a&a5{G(Zqr91`ikI087Y8dOSe3@rEvl!h>6vD1*xA z#%~2{&)4x12A9nkfgSuhKHkCC@=~0Gf1Q&7FXa;*`~t8A4t@zI1D?+#KZqpB!GkMI zc34v#xe}pBs>5Q$aFFHz8eqsu$JiOxJ=!55hz7OWC&6~}beEz$!f~bDz*TJ(d^(GW z8Uy_x4hhYM5t&CP20De>ZFR8SfbqBjEhtm#DXpfAoZ?2*Hp=bieLAP0cUX`@Zj|FH zZ`7Uwv~RRK{}4!t(vK_9%no1yMp3k+grBJVn(%DmGI0r+yjR~daJlq7U13GbZbuMP zscd4>!Tb{mo&qV>-%XD8@GaGDkU}tGI|NZL$RIW#G$63Nh#rB)!XyGsumuA+(B(}G z+n|SU@h*(sK0IOt&?}HZloS|Wq@F$3rbcgn{ZZg3CN55bEw=;BaHrMUDKS6v&t z!domRJd>$`38)7XP$wp!&K?qYdyt}o7OBAkK3>qF^wf9}0{Aq(p2iXBwZLGs8V!S1 z2t2&OH)k)qY;4adb0{qb{8vGz3E_Qdfr2CLoaz?M9d8m5xn!Jvk_28GQ}<)(gG{ zi@^=bi0QAvQv~!Xl;U=Sy6ysX4M*j6)YTXm+R@1I&O$N9S%iicj@NjEXquJCdJpn} znGJ9b=pul=%9sL!t@2?;tTdm}aA*b*4Z5xgYyvX4EZ>Dfc%5B|B{ox`^^ zw;APgZL|=9+zL7^$m`GnJp4x7fe#7`;940N`)idRAY)WV5*S}%&;)ORis69?If%p> zAqM!2enAMmML&&7X}kJPifbeUaVtg9tL!lF?*wr8QYkrXI{|N&O`M7@jBbbftctcPw>( zUQ3!g&v+m=!y(|F>ds4oQzAYkz)J$W;&}|umLx=xqC`beBI++LN|PKk;oYd6kHian zdeA-jBA0dnl$ZA7Ug-NmUzXdP@rhtOn49X!OFDq8ey(JdvfPsBrtBlj9_z7`CZWaH z1X@l{yr;q)C8k=S+MrrEnTqg;29Y7kPHuDd!B9Hk&!~1KODBSKi64dN6c``;7$P!= z@PMsUC>l_WxFRr0ka8%z74cUtyh~|*UIMoyfgBQLqrnng0we=SPPo2Oh;@Pmra7&= z8Jsk*mpEy}NL>U!N#`H}Pl{DI8iTK%P?L;l1l1m;xi9wSrQJwLAuth+N1@&|5K} zVCEZ%0p7uH;-m&%Y7kro@c0~rhF%Od=*7}X$RHGt%Df%2sd}aJ5~;<@X0SCFDg!SO z#OAp0BI3&$qL7&WDlcmx0B+*qggOq{ap_U1oDU)iz+i%8OqC&^pbKQu1wQpH4nkhy z`bA6)d=b1zZ;G?9#oB3Ar3!3s=@J7Vb6%8tM5_LyId?&O# zAw(wPk0ZtggHQs-c`)rVL^CbP7$;IZLQCAPTp(2Lsl9dk{SX4}?&Ioo;2KxKDE_6pq{>I3#%wy{9_B$%9}vfteR1jNGYCUTsMOja?*2DT1UHWZ;8uwU7eJ zx>A5F5e&UA5x5IREdiVhIC`**7#JW+l68(g;OTo~GTK`*T#M@VMWcuq0*I%hHj)h> z<4(+7IaeI&(9a>14^88xIM9rU5mG8b!+I2#cX|a7)y&HtwZl?CcbNn;ETs&n~;b*$_;6Rt4Y@KYu&dK5Ykf|KY84uE0> z3V8z&c6bIp>jlL#`a~cw>VY~GvEEAT22U@{im!oW^lDf9zHf`d83WWwddEuI-^8Ce zlyR`om2$9$E75axbG+YjT&(^)7t%Y-;`Ug;FYwK=Ztx2UPT;*8LR#V(!1F;EiK!XQ zAwVBe@v>0>u4QXMfL`I{>}5jsDj^&Ee)fX4pA-fM+!qPiuL;?&!@pXP)=>mol(;a} zq=qa5HDJm3!kS&VT8^Bm{Ax;d$-yDR0Bf>W8`2v2wHG8YT1 zqCfu1U+9Yeq^B!(H(Cp=7VWp3+Dk2E03}c=*Uu|WLaPGQL}0}TVQ67Pc?w>Lynsv+ zJ+=wJX+oxCEF2o&;CjzSp) z7p5R*l*6JF#IPr~Q7KuBr#BXAdMU+DQYxTBXX;2*(%sj)Hr^1tvXR8!`_o_NYPe}7NB8~eE0u68-Um|9DL9tE zON)D)fE3u#69b$>IQ3EO{#-daAA)hr<*dHAJzyYmD@hntV=Mv?7rNO{1#A_+MnsYwDd7>!@-9s&H3fE5_Q7w14vLvhfZdb*OGJ(`UN z3r}{!GR>LK+SL$VF6L6%P!9-pg#YNHuS?f<{hRaEp{7DT7gJ7JGXJ+5TgK4wjvzsLs}p>i6^w}#z%qf+gzT0kiMWH84%}0~pZq(2 zVU-#kRupnh%Oz4iGKvF=jQ5GyY;o-o% z7*9;)6+Qud!bhYk#zLF{*adJ=cw)rWgL#X?&{J=5#apCRxvqGpAiivMVL9CQe4YzE z{z$$nsmoVbU3FSzgh_T=d@t~>6pL>$?@ESD7#a=ee&9{XGYO&434IVl#p8j+LPYM< zQCfIXnvnYYC=a15fo1VgRxykyj5;PP3bWB*QFxEKKxx-ld{hOs7G+Qjt2lt|X>zQi zmupS$;1v}2g~WdU@n?9(<2p1seTxE5i`kn9rq zlk){&HOX8#agp+2ALPJQlVwp=ij1Gz&t}JSia$ z_aslQtHCNKI_V)L;e!=RA00SfYD4`+?aB&1T1VGeT$lm5bh#oDzyqs8cvxNW^vDzA zlm}El@RpCRiANVG1mGb!(KQs{W5^X1K*Y=o%Le!+f;kUD^TDVF+?GIi9Do);-yi@j zg5p*Jcq1*3)Bm=bwMNf1DQ*-^4W!gb0TM2M8rV7{Y+ z#XxaR7$D_|cVhNQWh_jE zotDp(;U_p&Z5JeE01M24gR@>NxX~DgN~8xWAnXB=R^XfBWurhjtP6yOV3y+AViA>5 zun99$8b$Q}YcaxMQhczND|X+Xdvw5+c0)ycOLmn1hinK}eA(-A#Q@SIK~H9W;jsj# zrK$Ug_&t4G@l6oUD45d(i8Eo2!-{nwU{052j9rkDbEk8G-;lkDzydr-mLxBL;6g#5 z%~BjNi1#X-F|Bz4g%r+sZ4iZMB{7IXuhZhv--JR~?ch6Lkb2el!u2WSA&2yAo)B5eM-Hmgpb{Ie0CEF@3;L04K-` zq)bYDAX^ee2yVoyWFnBKh5#$QRhd$U--EN?P}V`jDKH{a@@i4y)VnR8DSTJcb;w~K zC2{lv|5Y6jFS`Sg$|8}-XK4ouTN3y5Xo++7#JZ($N~--l7t&BjaCc+v2NV^Inuu&* zjTMV+F33hOtx5*@StCGKtB&_3Lu&z3bqLgImF(9-EMgHmgJO2J9?EiBPeBmar4fo> zg{Pn}*R3VxV3CxvztEfZ@z?pj%>7nZr-PR4=LPEazHF?6fC0wxEh-9R7IQ5UuOT%I zP%`FPVjQ?e3kFh_aUPI3PzP!$8bo|Cs2~h`82a#y zhg{y9fVzUX5A_IMJBe2Jf$dmp2a!m^SPGn?2N({>pfJL@0;u^PooN28lgoCMmfaE8 zv$G-i?rf1eIW3)=EK-)$m+7{O83HZKIysrhpoGgPEP#p#9GCDIVTmD3ad1A3kP7kp zYA6;8^}H7%Ua!&vpr_#?Om%WTMS_eT5U=PD$#HN3-yDz11Sc)U3Xmle_k^`o=*&s9 z_=r&+(qw`lvq#%NFAYo*=`$$pfS@uuT|D{&K0v(@${^_S-nG=}AdW~T{X{7l- zsl}UQm18}*n198A7j<*smciLNIZU+7UPV3W1=IrX!W&c(eQquRKHOXk?{Yxs>){si zq(}ueUykFwDy-IfxL5c%2j^N0wIu{v1Udt@c_9z3+64|AoHFz}P_-g>bEpbxFnjhu zZy7oUP=e9(@+xK2lfeDg^SH|f0i69tDDD{0V3;}31?C;z;YeR-vMFJvp@i`21;l}f zF!zMe)x&8KKU#`7QKY#5NrP#GZUIzt7txZ94-q4qOGw=ciVw&>#Q4;t$K(MKY6SFRLWSosHGt+4 zG$&+MkmGXW;R#~~&0rx94%bm>Ys8L|IH);6E+$B<#RVyuyuczRV&b++@Fh3|aXm&d zi-ZNOSgguGTL5D&=!A?BjTi|qb~LI%m_lnEScj+e8?5JJIxVgeNTJ48Blv)VE)_JZ zns^DAlV(A9qa)9kfgY6!wz-qV+ZpM00vD6%w2JBYlOu%1KQ(F7HeKS#I8&;S@4aR~e|c3`7Y1A|IB|vn&!^TyTL0#pQwzRH@>F zT*yZ#Ouz^50ohpA6{MV0%y!T!s*JVM zNYZX4LJY}?R)EBCT|m}?fdCW}JD8wd4=D=<%=zGNc&I_fyCKfNbQ5D2$R-wjFC?Q( zw(9zRg#Sy@&I>+&25PS;*1@w8%?zD+(qC7W^FjV&1+2h>n1(uUJH_>k{m|VZA;q#T zBww4?4U>FNkyw{UdR&69F1MM~mDWJ%3gv;C9ONzDHBjVI?qELvW3a(p(H-(*>jk)B z%t|9Z!V*J6Pb_BlXo+$Z9glY8|M{?p<&HLWOsvmCfPq>kULLW#puB{%M4jcN2*oC_ zhdm(4fnGHB86{rKL|-U(c*~~l=NqA(g8>U7n6BVp^gT&ZbF%t#D?~Ta)?BR3K1UsNP}=3Mt_J?0voB|1DCULJZhaA!0rYj!Fb)L@TD4 z{Xr@zVt!t41%*9UnTEhCl4)#;02gu z|MUr7ptdSjkeZ|>5WzAfwqVq61`^uQ-K$5^24o>_7j)w~t^q3O227z)U_5nc?Mi3!ZtQWiu(0+09Qk{inwb1s2whVAg!8V%r0`UR}362&p zY5xGn+T9elfTsYaqDX|VXee|N(zzq#LjpiPG?fJIya6(fg-tvZg0CXx+0)gFiks)p zb0MEKN3mrKxZ8%u7X#s~l&uagH0ij0LweV8oTnT1t#ntW<o&SAk=Ty*cF}6(XA|24S=4cOuqgOUW6U5|igwEB!_m0UZ zQmmux3AhuF4AluDeA^Vl*8u(J0O7-Ty}wH{(PxOfiSj`Y8cNkav+E1_($ifNWU&|Ce9bzj09_O0GJEwLchYQV7JJ zMf4{P6sKtu4>V`Qw*-J|1X54fC_vc^!x2DeQK9xQF~BhfXcTNW#KZ>sgsEwG5o;!( zi@p~z8*}hbO^SARg{%upFb)CJ22dv-+75TLBs}=gk{Ip~mIhahV_3ID7Q_Y%jiMl~ zh$9%aV4w%DMI$@95Jq!gJ$!V$lY86nk08MaF#aPpY;VET zej5>F8vT)GC;f8%B8a}1bn5d^^C&N~rcyg@(y zOBrwK0-$8*vU~EpH2e_b{g+S}yxSUOyU$-{_x^unCqS1$KmL)6R;Z$|V1qRwaluOe z4}z$&V$4wG(vYFDP~|V-jM*xdz?X%KF4u^95k1O&>Z^L zm-uT}0OdOb3fRUyTpD41_zc?JwxF4j1p^#f_L6`cj5n_Ov!6&4dPhlzwxNsQ)? zV2h&z^B5=hF%O#_KJ1D>8L)VP#R4Zs78kJQ0j(nk?OWwsur;uZSMy%vU#uW?C3!J6 zv%(UA56cOQFbI*t%2I4s#T*G{L?l$3M!-Z#LX|=NX*J13-r*4oR9)8czP0=(SY3qz zj2yv3Fcu+zf!J)7aIeN*^jumdt-;JP7aPW)R1R)}W?(AnOW*?`Hkv0yLDY-!=Vbw_ z*XX|zZMVcSMaPw)j@1~h1_-$?WYmx=8z2Z?0`3J-R$HPhU~!?5B5fim4yiS+r^H}X zNMT|tFbWbA3&D(oKTKn39&|1spR+=)EhZ5@q3RPoqzID-&4eQYRTamnkdK%u|DTY z!2*{Xrd#9`7;r&brh*<}k>`Ikj%W5!DgWrC5|&a(2bs3okR=pf5-J<3BhXf&y)S?J z_vBt)b?EAdBlMoGo)0nyJ*MU;sQu}oHf1m{iRwyI$w zsMH0K+{;%5upQMw)dwB}%dMzT-mnWK0|GdjgyI!Hi$reJGVlR=E##X*QRts-(qL9V ztHB5(Yq?5pDc4H&gLu?#v<$jk_A!s-<+0Mb{Fdlb>kC?Rj&rr$p<8WsRdd*^UgWAa zOIw->#Om)2pXAHhkK({zHik#o`Dd)Uh5NlU9Gvkd7kE{Hi)%1@RsYLwq0B2q3@sa9 zDbjygL;fFWrSt+X{ZkkEZ~6stMLi?~L_>9@-~V^gxc?)aB>M_=zCxY<)ojL{cvleb3gZ29*x)OD=}KR^(wDCErN1z#xk4VUkcTVe;R<>9ze*l{ zW|^k58hg&7E_va^oS+3D+D92YR0r#WSed6^+o3x+gGaewFCrwRLU0zd58!ImHF z|G_~%7bOwCC=}GpPCtz!L(XS8&t)~8&Em40KPK;M;=VIW38aYDq$r~Kux#EUF2N!g z6wS39HdsMTG`%V7Uv7e9JJ07oIgObCc$$S=74aB3-60}oL?g( zIM3nMbQU+RPKbB@h@1N?lz-#=-@~d<90&ar9QFY<&o#m_oc%*;rYr|lV5qe_&Tl63 zI$xMwuVeKd2Ei+^$-~gY8v|2tiVj-t87Y}c@k6K-osM?cIf|mUvq=TL95a-J_RH$7 zr}t_;I>LF?*U>flc{dt4pr8RwsU{A4nZh1=Z?;`H~xuBfZMJ9<&Vek-Mn9kHRz)S0ni(5FK_!!a`mw^#kl5MU0x-G3ZxT`ssT zc*VATYUhmgc2qiln*hRc0a^xS#lB!zGlhBpG*Mut1p7#^bs5{8T~HUn-p3_ElHd(5i{T$!l2_vT z$5!=~D6sGjl=()2ekt-<&>V}6S|})tl|!#dfc6dP))4IhGD4dT9UL|)(fag6HQ-5m zN2GL|cK|z+#@yyKN3JUkhEJ1s!!)py^IK`}x9fSUa-vI39te|nBP`LNyTB|utagZc zr$ycbYPH8AVWSk*)qU%*|BEclW9O5!UQiB(S({5p=iQjAP`YioEfj&ynTwEyJyxh< zVevj!p2vG*_vD_2bw?b#lkCBf2#6c`f~9g8Bv;IkQh$U-ngLov&?o1izy-St*!GNO zqm4i??pci;Ezyo55o&%?ygUB{Ebd};KCJC7w(}SEF&orrIS$IY>^WV6C@#nFlBNBR4*yF93#6_4zTqJ73Z?5Ac z{}0$QN?Sa&oC_yIao)GEj47r1%^S_loS52V-pD!3mwvMF$8R+ILc#n$(7{rO$8C-z z(_3cP29}&=X+88&%rF3~=H#`o3l8;Sn6~9$`Iq)dL6?q`)UYnBWPTMVZOm^*an_@V zq$`0U)&&X;JW%QYgCf*{IK^TUHkFeG9Z&*0C_|N)gc?mdSa32^spIe#1AI|SU~h!G z(7Uu7UC;%>5DG2q>2o=Hv#t<7h9sgQDVIy&p!~3Y%9K zxZbk<`7<4Y$2FOyIGl8~gIkIHVZ4@3A%NZ90$+U>nGEZ-VOV0=<_pSY5?@bSK+Rs5 zM2`2HU9~6^%J~`x6Ln^v7CMR`zN^R-1}8!pFP=<>$*^z*>V<9f9MtK6K5t?)MNcIK za3DH1+krmO8)^xkK;Pgk7$#PU0DYEX!=6lv8%GpTN>GEObm6*^!n!ev|7Pp%voFEBcqvGrU zAu>bPED!+a#=+uFt`vjFLXo#So+3Ll+;TqD!xbd`i}!!=FC2duN;wrJfd^4UjUN>VnqwUYoEGEr1GmNv~+%)`PE`1*Cg-9yCrN(deRTqf0 z;JtLpM&UqtJK7OaTygjWcT$G|y|zHc;eiW49H7YiCMQ1+WAOZ9n25qDlghDXFisx} zlYP+B4`?>>un&vmp~{9IPDmu&Vt0r0WFw!VR*y{i1Drk*2%qw{d5!rdJul?Tjt`o(7xt& zU(#`I>|gqy_qAD{kAJeUhAjrL;>yKy!O$V~tgy(!*^B6K^X5d`#_ywSIrE&SupT(E<3vEZ2Jnw+a(6Ih9WSo zQe6@3Et_#h78;L^3n0_6V!|Fw#t|DV^ZDpJQkZOlsVErW!n~TeUcMQdcE|)W3=|>x zCS;59?t~RYCGQ+gvGpQyOb!xZ=N|^l>8ub;Ghj>Ej7g6VlMl!N4lQuQ!XHk$^>iV; zfxQnpF*W@t-?)WGt#(q*u+2hBRK;j0rHYY|@tK&N%SObs4iM-Ug5FvP@EG)*}W6XH;8 zEP*AAz#(jqSm4YT5A2zG1PCw0RDbY?h?Mgk1s{3DBo~6iOjxhty(q5oqr7#(tQW>~ zFZy-Ncj!H|-7xeHdoBNm4xULy+h*g0n(X=DBw6AAvG*o`QC#=o|11Km`@WEbCR$0m zGrN*FjPFAQjB_uZY=H0`_7x|y*KZD-}idoueusfYj~zp z`C7Fstq!GDG~$k-Y^EI%D=wj&ex#ZQUIHA{Xw)Qz)=bny z>K-4hj#>k$^iB@F6SZ7X%av2BzosU&$+YrLgv7Y#BniyE6TkNjRt8C+3SYE{ESQ1| z8(j_{D@_vk4yT#~qLKt=#jYVqHq?509&7&XZtd-6?QM>Fo1vnjW7L-D;%lr7d6t0*^d`ljMChEQ8*5D?8uULTVYM?6iE z)m)BV71e?yEEZRB5ff=pS^Js5t$a@7)6fU4X2rcu<-JDbJ(D5jFKGcp-9<-}4Qf=Y zjp((>`WMs;9y^r928pk5Am~#Vx#b^eJM8;D2??+@Y z_>>!nEcQbiF-xe@t5GhODiVHZD+1@?)gw_45oXuo`Tzn97rVxMXyD7{gdf^!te3bf zL_;*YJaPazsd(DvhmSoZ8&CuDS$r%pnAJ;_@;|h70;ybmN}3`8!2(kTD*vN^T8#jl zSn3V%S12rzf@3M;@s@~#Ca23ESlMbAp)iwKNm+R>-WX*SdM3s(7(1Mw%ePCA=>Pej zN=G#Cu};t2fbWY2s{=3OjZZc1Y&e5v7zKR-mNoDL|Ges81H$3gXWBWJ3zL3eaUgRN zH}~PsciQekoJf43l`>0XV<5>7GzKKzw{Yq$J@UP1Nr=3@U(u509m3(pruxb_VUQyA z710HRELdQa*Sl@8AmKs$=0=o^P-BL#P>q- z%Cu=nXfo!_nxsU`a}bCTe4)MJ4f<(^M%d(l4P%Ga=@N$hy`esH*tASRp9A&P5=Aaj zUj_P{2l|}XU_3)`iiqFZ_?m}3v)^k{2_$wMJylgPoF;}~HT1?c5|HOqq=-wz1%5Q>H;+e1YS#s=?hvKv9y_gw`S9R~!$yrE$$IN4!^=Y@A0@ z&S5Fp63m33T*&ou8+Xe?c$Pd;9zFG{tn{06q!gEwZ1Ql5$UlEJ@99!67T;$G_S1Y~ zAGRs6Ma~91YaPCY5J(2FYyXR!;OSudt+K3El~@_TxEOXUd*@w5cpse zETMz;3xsVB8bn0KfbcCaEZ7VaG6hX-IunyriJxE)t?q#6nj4JG4OrTsdljFq?p7QH zN>Dmd%oK1^Z&E>Y<+#zah~YylGvXT(+_QjUMjDQym6nLk8s@Bgy-1Mi!7t$;p13zt zK@Njnh`QWl&l3m&Y5E)+&iIDPvZt66^_aph~A9v5||JDp8FtlM=kwmJ*%x%57PO&R6Yg zP_ZyUOsHZ;qONXKduh!!TJkbN@x5L-V@qP7BXX=tPmYCp9ywN3T8>rY$+2paLA5Pt zs_l@ERhLf2@3rfU?W)cbQCj6pJMh7!jrnd5>9w=r2E@9mjO(c|w^vH@e}JKH<1>c7 zy+)x0&0qMNuHGzTMZxPvMM8H_`|NLl0x)(i6kX3gF@SRbw#kw=(f6Pm!j&)pJ&5H= z{f)(wyYw+}S;!^2S^-fe0z=r6>Co!pK4bGPal{iO{KXT4B2V=6T7eG~Bx^loSg^ zEEfM6RS6iGdZ!BG0G9Z%I!dCuC^^;%g-recpHT zu&q4gAD$O&w13BH$I3Tu_e_*0jEB5U4!rDg&dYTdsyq!BPiA+$*6=+u=g1ok-!t-_ zZL$WNPUXZF7(GeCUBwrfZHrk!adIPO7=agL4e4C*Lf^>L!Yts$jEicRA$ze%a_~#f zT;cRI<_F;{F?VF)B`5_nA`GWPkl$REZVI>DAec0Z01BJ$u(lpeHo7}nL+;*I-Fl)m zFboIn|w#avy&Ul2uGFxsT>1eW8!=j|*X97Iehj0RR?_U^_5jSgYmJY;&_GY1?A ztjzcQr>gKi2#dg{-3>0kHd(h1nMb4+IG3FolUIPnjFU$HQ^IC=E4ZKU`;SHEOoKg* zGw#w8%ydNT@lRfKutbYZbTHOLda<}<6{CZ(2`(y#rh|eplfZ;Bb;4F+`gmcV&hbur7Zce?ZXJ-v5Z}mK&LB_Umwr{W(R*>GCNaS% z2Q%qn);zSFDro#p(*M>AxP@?0pjmTY!Sevtr) z3afgoE<&^q@1%328z8-(?uOyr909K8olxFs2Krqb9`5Z;)EBz_yE7=>+nmSW?bZH% zO!M#dHc(lD>2cbTG^f2NKej*?Uz+V6qwVywSmI(tH;vJL*AMr1Mgv{kF2Hmr7Pwx% z$z>H6dumWs1XVL$ddX9nhcA}JZy(B+E@$@Qssra|K0-;ipl-rNmX(fs8Nl?_m8q6c zVdS8|M%XHWI5VT#E&}5DhZ-dkXC|@~W=*_Gu`C<&{n?G?E?nL;I83@*>)l>a4d8mC zN78|Mt6$RIdS|Po84U+WOawE;Vde=P^+<#zIw#yCR1*QZBlV&?o}-I;{vctXsP0Vx z)S~rWVy{|Cysh$BU|!-XLf3aiJyn)0L+7*F z_$vF0hhgdeu9$xv^%AAfC~I(VgvgS6!f+xTMCR_6CZ~8UsXlJG{`W))#&m}$!6urx z!}<`qJTFSHiJEWTReu+EgZ%$p-2h=I+%_&Gu9;la2oL<$m%jAtpZ}Fl{`%*?^vG}i zdh_kK-*QLuqW39t73CY5?CS*j&rD^$;#V>i<>gFeo>H&mD#}=|{hL4w1bQZ$GA)!lzL%}ssVovGkVDR5fqpKBJ8u@~D>>vW z5om9Yatr@JrvU4f&MgCxmUSEpl{@I?oN4IGMC!iCD5EaYIwJt zt<0m2_Xu=vo>Is?KtCaQtpa^1kDC3MQl=;y@{~VQmP%{*FZbS8N?CqE%KY1NuPC`bCBKY1{HlEY zDuF&BH42pRlm`U*SQ({yP-^}+Wt8e6$varaw|ZEhb7l0UPs)?)%IUA4lDy^Re1lI5 z^k?Oi?-6B=qI|PlsZ~Cs%<(C9IbZ+RYJms@;c6kM@`#EX9hbm~t&&$0#E9gtV zF3_tL^sp}oR9wk7{SARWTFH~YC}r-dWTgD2JntVXdGeQ}ELJ7Y`z^U{q>_64www)1 zum2rs)1RA1+yAcQ_0OY+e_0@N9&h_Sfo4}R#{Qo?S*zl`zc0`GKUMUwKajjXs-pe= zP@cS_N-0kd~jD*i;E34#7ppq6T&uL$(Z0{xjls|5OU#iuAwRx7iV zzmU9dNZwxxwXp=vV6)QCsAWo;tAP-%H-XI{MH*$k)p9Ga|Oicq{iaina;<`>dZQ zZ7(V2>U0Jr4Q#9*@f%hy9F>e^hdOO0!_!uPa%Kaz{P5bEn+#GxfCF zE_ufn>Xiy*w?Ka>XZHy7wR(EQUb$|2J-BC|^s6`O8Rh>ZC0*J;IsRF$`(Oioe!oCJ z-vF*VAm#g91ATW;?p@VD`3@?@in6}}-1CG$8I9nhCk6WPMzG7j$aQ^4LtOWK%E+A4@r%l(!j;f3Y5^8gAOZmeM-4b=_6i!b@EJk@~3r1 z?Q;Tc(ZNjLmUf;MqHae7`f-7d3bZ!F7kplzmqU!zV*<5=IUAMw{%)B1T9UUZ%vXIu zo;Ml>cfTmm(k7tq2=rG?-1}XDjx>SKUy?FcH&goK0)4ERo)Z&{+1booV9S$_HB+M# z0_C>=ofPQ)7Os0)pg$7m6@mU)&b}&;+rkX>n#{ya3ux!KeCaPNpg%iu_G=61r>6vZ zPN35Q&60WZb%B;FB=38I6CYkkpFE?03IBYdqAG8Y=i9W9{+tl#TMNOguH12IA@3a$ zsBRJS+ps{txQH3-tUzBC=uLsXxd?3bmO$qOIww$QF=vwk{nBE-_x~r*7Z>xq5rMV| zG%Clh-AsMQ1p3*V$s3otb=*upn2@~xxS6@{za+0{3DanFqCYHNPjij;ES!z7I%y?`fYV4^$i(2Rd z&y2m_@UO31X83z2mL46$MZl)|6CdDS&t2r!#PH+R{dUCct~*e-!C7YRu3KN%?GCbE zW=hWS4{>rd``HQe)%N7@hmBNwUG}RTb<3^&Bfc{kXEM*sV!ywxkDR^sax1#OZd(#7 z1W~tSzu1O5hlkK3^!iVCChbnY^U%79)I%HUR*f!qm${L;wIll{{J2ETN**0OkXq*M z9$7Q8d#ufm5^H}lrOx-MfA|1@MH#+V?l(8N8%I~To9ecW_NV&CS2*`MJ>&hUjia0D zR=B;Ro80@%j8|yVjdd%mzPc55@937g6;4lTV`_l^jj8_B3TF#9udoN|?zcA9dAhMO zXQi?Bb(bK`51jLNbvWiamZehk>O{8pzgzFt_tvFhax)5s)>-Qf`KXY!*?jtAhtab6 z)Ia%(9A~I~?gneQ*;Tj6S#EZY^wn*)y(7sry6VJZUAO=2UW^1MjL68k(caVs%DBvZ zXt^`>b7`Ix&T3Be__=0tqqW_CRzA1doyv;gzkH_OE8~claNIx0W#Vq6HlmpkEh}mr z7|V>=2XUcl9307vnICXJ=zNg3jIA5%32u!~*q&+3>Uw)la1(hCKD?aMS#evuqU}tk zK4l(|_jZo=Oc<+1H#fT5lVe_S+QzdYPNw(U>Gj#p@!rv%@#S{U_^fkV$2&&0jz`R` z6L0Ou#r$YyB)xLpdyTPX!gzH2!N==5Q&|zDT?pRn?o?0E>WNQKy(r#$4Ss8an}g}H z`G@BQtaW2u{`=g%ROi?Vr)})v<2cDt{dz2_Xo`W_=M@* z**}pLH$R;f#pk*40i5rfnaQk(of(${UX#eyJ9Sl@El5Y*7&IQRR!?+JNWpfDJkUSU z>o;Sg8;KaOHR*RAHe>F((Z133BfY70V;e?i2VA_Udavn9j_nRSY(ARmOWo(Lt^3TQ ze*3;;<3p#`j#0|x&gPK^cGRsKeTZJRYK#RllPxF+L#1GAM)1aTQOBCfLJazHc6`j( zA0Ia}k55>c&-?l9PM+;2W0U{HK}Cvf#BG9ZkxZ`?H=u%*fi2nmvOFdbbxfZwR&Vz zU3XpQ=z|ZhcH2glJAJ9O_A;~GZ+7@QM>klH28~DEK6lk1$JXg)r~Y_d|Jb(CbtCtKOZJSkrw*hZt;;$` zUx>xctoodU?cJJl2yZ7{y7d4aXFA7sr#e$?W4luuQrlCTHLFLnmJbi4`bM{VTknL~ zm)fFP1Ki~KufX^0i6?{hrU|plZ#}rv-9j=RWrlw;hn2feEwQZ*2G1==WOpl+-`gLm?t9rZ=XGL_YErgH$ zX}@mW;&*Z8tdPaeD`jpBKa-dKIyH;m#rbVKShqY8c}e7{*Zgl9{S!1n{R@45t8-$% zzb6HLX-j=jbmMUG zHl+5Bt@2x+#9`nr|I4X^V;!kIW8JC8c;u!DJ`h*0p4gp|6%n(oW6E$MiGACj#wIq#YoRjQxeIp#5O7)DA zygoAf9LXE*z*uT|(%x8a@htq3&Z<9%AGgWoriSbNyV;z9)cWyJc6CcZiRsLw?lu#@V`21{7a& z^T>9-KVx~jW^K@|)noJv#@liyeU%*cgeYe)J>+t|vB0I^p%}ew*H~xjQ=LTJ88eAa za27BBcwmi<P?Kx%G8z zsmDOs%k8DkeQx_`+vpmw>~cHS$JCc`&UdbdUNkT=b|0_p8H2>?8k&W zKXM>TY$`OfVa9o>q%<`Fg5SJgZvF!k7m znurO}Ixcfy;%L3SKIp8OFx&jb%8|{`%Dw*e6K~X;YZ^~(9yJc8dM7+0%2Pp0@P;<% zDW{WLAe5Z8iT?2}x=1&hq@5ER$2X+9a0nZ8dXuT>BrTVw=mfP@9jdo`g6mRH?w^KA z7#yL$eQLEFwgvlzIPkiD;;8@B=Ag00Z$3J{p8l|YWD^A&V3YKr^^kgF>w}w9$*~=>7R%? zJrix?J$~NfH`>N|`Tq1y&Ci&j08>R0m3U=DX!!BYlyvxO?8kb?dwC0E9pRGA7+;;^D5;V>Szwe2UMX$3PbD{UTH5dAt*W+%mH|!tpzvzD>t?nf1oy5s;Arh*YGU>O=hSrU? zjX!ew0C5v`9v4;q`q9oL(FuB!;t#VLoRK0X&gu~`C$n?HG_#~{KK1r zn;AQ)_3%#XM`qrr78aF%kQp64=(q2GrEb?~6wI*9z0ZEMZsTaz=!Uxc+_o{O@6nAZ z)?V@O!l?b=9)GXIJ24*hTfM0i)J0$2QYUhxZuYrH>pDiF<}y2a%w1}?k1mVbtLj#d ztfeTUpXh_ijoO_P_sNo=bieEyTRYM@(KE4jWFQr_9>;&PMB%WujwcK$#ky4YSl7fB z9EMkA3=%2jQ^u~*%=jbMU)p(4Ui^0Xjji%C`RyBha_q^m{h)*(7NzqtBEvoPJD_|10DEr7RWDElV`$6-0IIM4vzyE=q&L?)8pV$XgcMPFdcL2Wr?EAA1!3;7%C&$dT z7m>$2-IaiRcnwi4Tpg0m*#Yaxx@?4%$YRD}TalL;UEB(h>j^q4%{fnXPQ)f+ZdcIg zf^;(0AoG^ZJ0PiJ^(~z}}X66y9;UgHUrsB+u<* zkBzLVd%uGy@zOc8I%Z7InwPQ3f0l&4JIBm zH`Mit%weP7UFz=epM!ER;m)!XM(4zax*d)7c7*-HBCEgP#H{g-lo!^u;?P@fnKzv= z)(t&w?;7cIu$$~~mmx=dbFF!N|44`P`UlL&O6&cW?951qyOX@7>GK`wt2c1toHIt> z(EiunK$0kQezo|~c_TiyW^|c#rfYO%{pnd}cGq={tVYT%qPyJKYImQrlp1u5>>cr) z+cgGnODe~YlRr?mTBssnbk)L1EkSldTcgV{vmq^hNx5Tv&hh2T%?@XkdAye*Qg8xz zIc;?-t+vr_FKw^uBkgeIm^$=vdKEWh9^Z0F1J~W?!O-vzde}}2DA2NJ%9yB|nV`OFB_8Z&$C%Q*gHW)EnWjpK| zctj&x!>jtUL0iqIP5$C5!Y9ILEwg*Zc8t$C!>iJPA%G2Lv5#7jCrR&2s( zM?gL6%yRRsN5E-ZKDNm798h6 z5o4K^b(W_cUtt{>;Xx~`6+?U6sRyZNGGC)eT_aMY<(3p_jr+tobW+Ismz$Yy%sx{P zEr^(mrYG(8k+#v@b-g255qgfXk8eI$cfT3!AKfK7yqt_4*!)SR4JFlQK7@lW^WYc) zmHp#cf}ad^rKd(n53RQ+q_2D}H$qe+Q+UL;`Gjar#K}$?BJy~9Pbf#4mX(N`k65y5 z?d?8ec$Im-8FvJ=zs*O)3_p$P7v%Exo{*h1vtC@4{o<;er0Ffd%O@7n_$=Le7^&>Q z7`umZV6(Dg0ai#O)}N~}#oVM>D@XETRs_#vR-z#GVyYl^ye^9{N|`L>5(P}@VR0ds z7ajSCk#(&8^u_uR11-qdH5DQ^rqcK*K?u!Xlh1i$_m#$Tq70Ba2_tu7cNQnx&^x_> zb^XYVzxIo5sZY11_-LZhoB2QM&4JN}{^Xihz1E8sgTb&D3E#~BS@EaFm%UYoN)aQ1 ztG{~8+kE&_SK0?#dr3kdGx4kdQ?tyM4J8`J}hx6niXwNT0$hf(?_+9XD381$sD%T z>@hctB2Vn}KPQ2K&0P{Y*6f#~bUqjG#>uyKyFFSQ(Fm#{d;Qo}BrRJ}Ew!iSoLh!4 zcJ{dk*Nm(id9ZtA^~ghAsdkJt+9sl?eAW~B*uT+#0=?1fa~ksUj`JGCcc2p~j~cnj zyqGO$?wvd)V&)`sxS>_Q88mb1{5+d-iA7)G?o*!KO;Es zykhR!`ndCYWlx#16|;kgGb_+G-Zi#*G~#rOZXNHM*gC!r!PxjlLQ;-@vU7Z2UFY~V zRO*k{^^En8^``n!&6rynojp*}LY&@!zM|xf?1+W##$#`88Wu6F?;iOC{@ZWtzLKOlXuAARWThRwid}}7tMmq0 ztGyPHv)^1h@`$-!B;IYYx{L+ptfsSb&OMH<%U$ze2N4vf|E;Ra;b#oBD=*K7K&7?v3fW5M=YaHKD zJ1^1)T+j``vL}pq+*~^bXEDPi5i9XjYUPN>(q2sm@}S+8v{wiF{mHRCBOe-iWzcWV zedXC>?;y!w{S6)!NO#6D*dCSG$@A__;{sph|9>@gqKF9=b#9ik-7Y{b| z)5fO_Vsft0zX-sj2d1ya2J&UMGsuUd*(dsvbzP~h5mb;Ce4r71VRSWGsnG}5BiFFI zg7+Oob;XS`a<5-uQ#=i)-N1bpx9bhOuW&j}yZ#pzUTCcwRoxW6iB5ReIMR^w%DOag z11h`AHP1I%iqE&D9&W>a=b=Y_^9!H-#FsByUsR#U`l1hFU0#KKcosI&VhOLjl7*Fa zJ(kGI?rdeRuR)+s=PLj1Ys3ayY06jrepUdRU*$-l;`oAMc|KUoY77ngcO_h+1bw{V;I~hx*HL?~d`+ds<`sQNgHQ#b9=9Pa~qCDZdPoRfy zRnGZV$k|`GUHP2ve%2i+#vPRY{n&^r3+_^E-v{Knf_s#I@O@Cq@=y0F#l8>GTFO(c z%1`<}EcaF}Rp!k4aVf$4fBiOJjAG%Me&-e+s_j5dJ)=$dwc79M9^Zk_EvE#$a z*L^=NdB5}#MV<9Ca^3I$q%!LJSvmXLKdo%_eN@V#{w!trKXUdjKB_$9`#CxL(?6&D ztMC7^I!P)180!o^CV9obp!}Qf;{rYZi?sO9%e^apS^22%7o^NRzoOjf`$d6{{3>?m zza-GNK7sA{FSA-k`Q`)ItpAF#$fxXjkX0MMDqsKS9%6OOC!|Kvhm>FTJs{96pHvR` z9+a9VKBYAI9+JH3N0gPmhXwkF&nO@EeUc~p&i)#f`Ja-!qn}kC_kCKRKmELN%=d__ zUijD-D8XlxvJBY&B`Q2Jl~N>&N{5hFwyS;_jGKW1%-^5`n%KHr}RWPTOs zPX#LN1p10VAL|18GghO_TGtKatuL}yv#Q`P$d={5$MF<1FaRPaVyZ@2=vG{puZJp$9A9|frcIf>J{jg$AS6;`tm;l ztrO^puLG?Y$hQkDw&OpA0I$?%N{Y$UVqvk-wL`$P>zUeg7a|Yx}>j{%R{L^pxAap?q=H zHgK!5^_%q5?Q&iFzbQZCdrZFNcmJKSkX~Q(AAFC;<&Nk6L)kp*AL*;U-!@oH^>tRA zDfv(Fj-7JHnWtFiu}j`@{Atzz?G~u_8P?tG5$NGVjHA8sj@J%>hxXA+e1CUXDVp_9 zQn#<0tj+spxvuOvR&4DT=&|Qm`Ex+Z_l0k>;$u+medGuu`Jjx7CypvhXFVa%#4)hS zlL9S!LHXdUf064tz5_1)hF}5XyGqRWuLAx3aoXUU0)53+UibZ*K%YMeUi)`}e&QA7 zxbHs%YI;o>@%<;Obd*L%dC~VR86W?3N;%~-9jpf8_cyge;YRzm6XJtNR2 zSLyN{k{aDQtlZ{%R-n(FRc`Se23z|!zR7rtNZ#qUlskN;Jh?upBz(^aR6L@5cGkBA z6aHaJsh)L2pq_D{qXO;uFJ-~3=LLG%=L^lE&We&Z+qZC5RNDTYxxNqkEXn(;n|yyf z>jimUX0|Wkdr_cdj_-BfcLX|_=bP|-S0KBM*L^X;m^EcS z-z-~Na(;#Hk9;QtT36}&1K&x3=2iJt`d$`jOSP}V_liJ^=KH?tdsU!s)cSgTugOgO z^Y8PO&x#8M`GVi~e|?Ue{Z_s2v%XUT-Q4K=jPJBS>jS>u^Sv%mh35NB-}jU`jXOqr*HSY0gfZjy2Cf<8xg4c zF5hO~s6e;h;~Vg$1p3aszCFG%fxh}<Ca{%{v(1@GbV>fSnoM)aJnhW&9JB`rrj`{G|Jy8j zAtp#bJi%Dog4sc5d(hag?G2g-G$iGNnlW2*p1@#U&rAmGUOiKH`*dS#XtQo@4H?+t zzrFpXh4gfbmu6mcT&&@K)hrFV*?fhPXu!_a%3@R@LO5n}vdAgba_|{0mn1K_#F@Or zN?%gKP1CM1dCVo(WXD>=+gqD1`Q>5bofQd|B?Fj9PrlJAi3D>lyiu-*QYdn`MBbPP z;3|SQYDNk7P;N@eB@$iw!X*ZmIN4fWqBZ1fZVg{?%hBX|si!=WmrOoVN<@G3p2;PY zfJ-RiWtXI1o4zDn>g&4ZqR%iLoC>!%Ew?n*sODT@+yC7+0&l*cKDy{+b$rQiMfCQe z(&$}gQS=_OAlgbmn^r%vP5neipe-J9a$?$0U!W(co7ti5fjJ?R6q-2@psx`ZW_Mt( zZtvIa?SWmodq6k02W|>w#x-Mm;0fK_s}BYSb!%>DFmOP(CE1V1dXjmv5gBJY4p}sd zeN5jSm>1RUfk0K*?!)DI$mtGLH=l?#R!5iA#BZjYx1609yX{oPv$vnBICQ&NdF)oZ z>S%JYT@zbuRmW~Ns$z}piI79m8#d;}8aIY)_K$_gm>V)GV~zWC+3(RU_PeL{D43`U zhqzn9a$>iRU4Z5cP$?se%FYc*ke|N5Hr>vSYEEBZhi>MCu%j3V<;8WgBhVKz^TL#} zJ*hkS(bl5)J%lj6bEq_SyIp?xmf@nmT%N9bTFzAucD~f` zCeraPTrpK78r}KH7Tnwf%<9M@{2w+t)sdUsqG-UVzSS<2!+7v?pKj*I0yUAKy;XDb zgLZWy;O^IO!WfvZnVHFelN+QlgW1twZagqQA)`RXqgA6>*{tN@CESY-<^aap0TbBp zV4Nz?_uwEdFO4aXch;tJ4+M=#=q42AlXqj*c4PZ1?gWwV>SyT zdNmwU1$PA1xtgt)GhL@i{m%D1WB`s zn zh%Xp02JQgI1l`W$ooIV?J9>|s8wn*^@!oywNuxI&#@XlM;hcEL%uOsb^WvfWWb;sA zT(@!~O>S{Q&yNxuj6s(SnI&<}CYPw}dS0T*EeR3!s>Lp5PS1`nzbe4WDWaoz%(N@^ZjcP<5$H+Hio7oY~-WoR6gv}hDuq)iwWUFyK88+3mw-Ai!<{@?GB1_GTHxH><@n-r{ zw8i0Yp`~t3E;iJjTU@pCHo8UlbTp){3YncDXMRjK20}(n$k?ab)jV~7s3xvq)?-#B z>0@M6vGh)NWKV`9iFBgdT;XQxW)&3_#9I~7%{{tP1N!bw>PAiE4!bsXo2x#0EB$nd zqi&H5WJRSNBGKB@gbGeCDcXBl8RM93jXO_&%qrYSK{$HS?fmJ)t=_>F!OT z{UL~y8Gq*=iOZ(d0i!%v5o>hHlZ|FsG*AH&Au*Zd%ONYuG`zb8oHETUW!&M@%Vgrl z0Tij`l*WTlBSE`VFG~i^l336#iD+dy{RAkcl}4EKb*lu*sU#63h^@}oIR5?blSKgmj;)NQ%gyNNzi%roRsaxY6$wbB>|^8ECXyjQ1tk{PE!x>RYQmRcw%c&PFd%l6v0J{0&NTXdA#0|Vv8f|pTxD3=> zDmMm+lP8bzs1RC%7uY053GGBm+>{{ACdEh>NQy?~DWyjHQC_LsBe!+@p9<%@v1c`pSz|9$vU^3l?tkHVE|HsvYTEN^ep z7%o*YsiOnUW|Re8uUoLTzdUG_MFRAhX&!zjE#xj~x*Ismem3hnWwEhO4;3A5Ab<{W z6PdmU7!aqW}iO21LWwpGGBNyVC*uAf@W3F;x~_8 zA=_m|zdV}dWtUu%k*ljYH}IPmBS^wvYiP!;@&+CzZ@!T~vBr`=)?i!3Q5-ze*9)QH zVe$%ML>~-TMUlpmSOfUJ!D2Iu14i)-%p|N^`eAQle>vBBg@;r}ZZmprzrybd*IqqK zO!21wU5iPce)aVoU0x{&M7M}&6QB^->*Ap8L2%ty%;yU733Qph0m5SP2Dvqz&q#nL zzf!(&Sw18PpZ3c6!s{mkNCDC%l2^Hu&GLi*lP9L$b>W02H%w~_&)dedoM{JLuQtLD z^(LFG`S>@jiZ2CJ7ey3@AonrYSSJAkx-($>6aYv-UtK7AY-TJ#~>p5}; z8|w;6ekdf#^G)n;y<}VX@>A8Z=96ki(~#O1w$*`+rjT_CYv$24Yum`?pEDoQ+M;q{;;|a47w%cs$0V9<6%SH0Il2EWU5`0 z+iKD^O@`W*ZSsI#wjQ=EA=9fFf(3PZ$WZ6- z%55QaP>1Q#O?7Ta%?zoG6BREn3<$;ty;sH!eGdT`!^g@D(NWwJOm|(e~{Ak$YF^HFQuU(k9+b)jZX~V0V<ESz}81Dur-isx6c-ZKTg^9GF4`s(fCTxZ@Fj>)<{w+E9$Tn(FHjFJtc@<39}Q8|wveMfPD@L-qNS12cu(3#50hsX z(YV>NH`s&FLPa4N>Wp)uFM0A(j1}R@bVj_B6V>IumCgysnyN#IsM z*o;n4_Wqz-p3t5M8tiukt%`&;H|SO-G(;5a`yuoa+U9^;1^*c&2B4OKBqpJ)4!AW5 ztu1J@z8%rtopwp`F8UnQ2xF@t zst;wxLWLohsn({}j6EYaM66AQB8^;tJS1e$C^C1uAVvl(jc*DqP$alBRLWe=KCXF4 zHL4jjGatqxDb;On@9Y$`&-ec=Lt1 z-e;HZY^Zzr6ke~e1T$snPEjZ)R79xX*GLUY(d-7B|&ysG9G?ht%hwtLtlbXr6lDzcwyEG@A*Q#g6TeZyA&?Uba+9vIh zVaAiH+D_BTw0Lac3A7ET&^Fkmi93gillSobTA>?dQjRs{#X>f-qLYJ6?r_M=V&*PD z*ATKGBh3RLk@g)FG8Nqy9Wj)qgSYC)J2Z1EJ%?^^K5^v;8ksAhA-I@zBv7>O{`Ax6 zpJsj}ByWm@%uA(73Hy#?wj58S{gdAvs%5AcaH95u6JBfLC>rmyhHxJhke75HB zVuD&PafCl$NSY;0!|jPMlXl4LPcq(^(=+4rI4Tp>5nw_Qv*j@^neZ7j=pEB@C;c@? zx^Rd|=kh&u_bBNogBeZ(;#!Doo+Vv-h^`Hh%><6Xw5S#Cf?iEo$|zGsbct1s$km%; z-!>`Z4F?Fkc=Pc5!;6Q(L3Ty*Hn)tqJSk{DG`uk$A~0dd+@I77k%@)`19`+iNTyGr zZ3Ok8EGY;{wV5!H62e39wX%esOZW0UbW|ZW=;1r@K=x9y{(H!HP`M<-Cxkz0OD;GC zec!djVis<{6@N`y^fn>{x7NdBEjYO`&Z`$7dJGv^%|kSflhtJBQ;^KCL{4-vp{BqD zH-Xo{3zE>DPlCB3I%u#gWWXI!uswPi#RA)a(JV%qBos#yxd){Agw9NEz%zmDK&N(b zC_AYMg$7dx#|#z{(kKDz!^Q^_qEpI29{>ljjww_a4V^VQk9#PH83?*Fj*cjLt2r;e z*qI-1IiYq6`8Xr(DJw#z|J}G`AmeQbNW@}X{{DMKG4HHw=@MRhzx#w*6k{24eyjlr zcr0*IW%?L~g9@Kex3>(deMs)xlM7F)?Qyt)?&QJ~YI|bgu-c8(+{^6F=5GQJnEi$SPp`(0$(Qr*{(W&a^7u(gx7o8>VboH^tC#nwJ zY*igw?47HPEwI&&=CkTR_%tZ}M4Ge9j@1vVd9iUr%|CkW8ctnt4We%9vMZ-Ki2e*j ze=}~E-d1*_H(dIFnU1GA-%RH(%P%-YI~~KB7m?)*HS2jaaf3_)YCp5T(6ELYUue|G z$2h*|MD?LXXKRivI$aZABp>MXWZp1&Cu*X6-x%YvyXh>9=}C1kbV40$8dkRp1GDI& zKGB|_*F3ryMmj!sE-90go@4>p0oNwuKsQgdTd#BZ54ZQpkA0^iV#~`a*zugg?R{&6PQw zDG`zh)N1YzF~Ngc(O3&^WtwI%WiwC5b@)r>)OZLc4T7QbXcOi-(DO;Scyx)v#aG0a zFtnKZ+Kyb4i?4k8yJxhwUVqV0YmX#vece?A8`h z}(b;V6IjO zSrQ2wOvU!TAY=)OI&OiiAl?(CGt)Je0h+N5-3ELxw6$G;W^8K^5ns^C2^C|-pXyJ5&*X9s zsv$YTPKNi2a?RMsA=)sx3pN9>j%FZc6z)0`y?Y*dDxI1GLAWvln>%4*cre-{xdg=w zrU_22?(sNYFslGPM-v|N$spDp9L0hT43HzwmP5*lY{NL95!RWvLT)&e2jd`K3-y2o zKAS3%iIpH7uR1tfpaDT(Mk$$O}-Q=CjYiq`{ujWRYN26lM{v zy_Kg~2LZG7f_N|!;ukfpl}`)L)uT%&CbHFJ5aK+#7*Yzt0(IDc=B#cxn~(aeSgI)8 z>I<+v5J`qARH4u%D)MH#oN<@Mhp&L(fjf5R!TvCj7*$E#K{AJSIT^C%g9U4oVM28y zE?Cn%Y!p3{WDE~1eEB(J&QnJc3*Zf;$HS@7iF2QAMQTv^d}}=m)t*V-byBT*Cb8r! zy}RwmtBJr{uRk}1POc-phVU%?1U`hTZq$dV3odrSIvJtWA+=Yx+bGVXy15pl;?v#U zklLQ2>y&>KjERM7WKr*e3CjAXn1xic#PEc?fY=j0I z0NqDlE>9vh3Yy*nBicNA2!oqoizB(}#3ou4W?&fhT+v zvBd!mL6(}ih=~UCgKR!*cA^=h7`}F{&?dPtgha5%Dj4?aUvFAKyBROtdgRPqM%ht1 zcL`iRR#2@0qae~M!a~|JFA6ci%g;V1j6iPFDe1Oix?2ayZG^Tl#6{gQSo+*X*n7mKqhH#G}L`1lwdm}zSj1hyhZFsT_ zaO?;-C{|I7hA%!$DNB#F)*I!AlJ^=_M_x_dehvC!O5r-=2Tq^JditdV@-q6*Q3#&Q z*lo7jceh=8xD^|#R=+)uZ|_zl_|CJRI^H}~1}lve&Mk?eJ%hC_4rA>Qva#ne%iz3W zk}D#if;a;c30BCeilI}B>hr;7*xlJRNOc&k93n+j8L$jt)rZ+3pvq@gL4q!E9CcN2 zUn!TW3`w$M%(v;?)CFZ+blK*eyl}1eMDHOyt%QlY47!AOIVzc%JRpKqkQ&zEU8OpW+0%sdtv&Og?K1ghy}WA;-o zwa_iVES0q0Q1#(ft2TDmDYftR6Y7EZqSI=g*W52(gO5OGLX%x9vLF@(TZMphm? zj|?=XLrab!)eu%Ai4^&@_cUcfF!WRwUW^Ih_r>=5Ye^_(sW`-B47LBL__eM z#sfE$@&Uc;r#+4S((fQZ&LB02aBWKq23^>o`7$7t%3NULtZIt7giK`Zl)^GT|oN!)9wP^Z@# zu$M#{J^zU>0eCzD*sJdFqYe%6KefwiZ8B!s{`(4%9chIUzUuChhP&kOI`E@MiqV;1 z?taj_Jo?m3+kbQEG6jiTeRoOIUVP{UkhnNwMmU>Et?>*qQPA3deDTToL3eB7wi8v_ zj=P;o&1`E;RX`4bRLk@T__gGgv(L>DY+Jl|xZrq`S+sDdB!+@=fmMdWqM!vOT&S>V zs9FT8O|=Z;JP2j5Ib%nS)4@ z3Ju9A=1DM= zq0XXQ$X(U;P@Y`4N;EK>XEs9iTpMz*PO<01lZs}fn&}n>+pUTUyKPq@#>KSOEoX`< zZ8D1whn+HX)dkNt!A!u&>^$1y&Wp4LA+1{*n4nrG40ZKA!|LE2!)ngaBks@G#XET6n8lt#Ail6~u9BX_3lhq5Np##j5hoaje*1Bv@1wM}cFt1a@{_)-ED zdCj4gVWj!kH(}}?y$z#}JDh^MEfiZs&xZX8*$2GUG!86{a5>Oen3vm7yxCEBP_QO~ zK{7=}i!cVW7WPi2?&Kk@z~W_kqPBrv-VNKdRy==j4IOy;Iw6{cirj}7gXE^L*hd%# z!X5{RuFfO2vXUX8KeMnu@YqMNnb2HtmxjmFC3QE=+kxH4=W~b@l8&s4p|?>G_SOuD zE~|*c!dM7762`o`BdltXuqmX)QTRd9k~oHbq@_uWT_lCPhw_Jr#u_dO$&X-2)KL{- z^I($!cXP1WsEp~(rWRu!x2#@ZRE3Q=`>1{v#X$Tn#4>kcrN5A8%#XG_s~ffPCW8m7 zNNiSe#Piqatf>hZ>&2QsWNrq3lkCtj^$)Sc%9uxjiBKhph*o(g;wiYx2x?7I7%kiz zdL>11Mh!TYk{6RoO{k$QH7un4q{c8Tt~3NRtQfW!kojIap(=GfuANlcGn-V}ISa9( zq?ysMA?<&liMdoWb~Sli!TIlfMc`UQ)$CTDJHsZ@lWkFN=Dg?$)1;t3kyC+Lq8=Sg_^;dR>2yN4+5bm07 zL4@OzhsglzzNU`$2kmt%mPLTT=|L801+l924xS8RX*CJo6to`;PTj&%u5CecXZor= z!OS2wFWwzoe=s2FnJfH%!vfdp7dSog89itd-5P7h)O*$c~ci3G8!P}m{-2l!NQzU65|1i|OLXC0EI7>y@97!z=o{-!TSp~XUsnD=p#fl68Dz^fP76|n`9niWwm zty;)Y3zDK1NzHjtFRhVt%`9eXmej0{dTFhkYhq<1hHcmLcP%@esb@f4Qs&%{Q!PoD zHF6|P-a(T+PY%G^UgCO5i&Y^<3qY!pI9{?485T#2yn{t{sT?deOT5JO68#Nttq>ZJ zQ=UEoz(LfD@b-y! zc2j*|ru1^kccv?Ij+_aIVN=nehHWW&~aw^pP&)ybwepW6!O zIWHMLl^1I=E0UohB!Olb7BnR=pGZVaB!w;$vWesnWfZIVASE#HvuZ*v${u$%CKsY!yYr zc6p@9$~)F%SBj!->vvo1s>7{f9@|*Y>`BK_}^ zRL%J0N_gx$4fJrWBPGY^ScS(B@?h5rsU|9`yd-j$+(gq!L#VhMB#%O+<Q$oCyQsrSzS7a!mj5(vU~AA?%hqUPqFZz5y#e@Aj$3(Ou>7*%3ly`g$O-Fol1_PXeodCJ7=iwOk*#de=Yj4_81Rnr%%*I8*H^E z5*QMpikY1rxHXZmz4iE_lU0YChC0!w&x<#`bQjW)*05D^xHarn#wlP$bRj*A;akD< zlpem#sLEydF0jPd69oO9WO-}#G!m$;ZzaD zc^oT-@Nzbvt{@`Z-23oj2)kyX;p3L$&G;OFdSKo1>CU*C!%EPUx z@+fn6Nwk$Ekx|g;?5Dolf-MbdI|QN_a~2&A%fw}rB1p&)`vKiSk;UQ`e1;@7>S$+1 zG`l*)pf#)GnmH%}SIvGx$4r5pw;Hb&qkB$avS94Sqyc2XjDl7^KY`6dUX-O%xrt_^ ztBWwU*eMnlJ-44UY7gIe67`^6^X%QHY7X6P&p&#XiS-h`1iD_kg+)^@EymfvGszZ6 z5w!ey$HJ;8T4g@r4Ja=oAo-+5BApPLNcN(_!}>wcHS%Jo5+OI#2-V3==oQQ-5e%%8 znuD-}h0vHci+L?Z)S}7XdIT1*IEuoz6gj(Fez+BnD|ZdgkKKk{5y57in|1m4p+q3!1A6YC#-_Uh##y5&cp$S z3=z~0#yl3S$iRS`!C#NYqA~ni0D~>lDPqv-kl?h*Jqt#X+Pg#(@Q$VZ*ZNM^F=BWG z3T|jg%oo{Us_8(? zb}2L|dWd6B{;^e2`OomX45B8CKUK z_+~a$n<`mCQ;Qh3JQ0HT#0f>SF~8X@i!|Y?skuDXsYlaAaFe^t0oVxkHS;-P(2j7}5DNKJ zyp3Uz(6SO*k=7l=69zgFY!PWF?nBtZ;uX(J27|?AF&Q2jhOu=`YESAV8dj<@O6CYt z-C{6+?2Xu5M_WpDcN4a@a5t=xG3e7JEx63la7$E%CW1j_cO!|3Heo(RAoDV8fkGxm zSRj8B2Gfe_@aGIG_o{vV;*(xn>5DV21Q+2ODI;vKh*Twh`C4!Axjo_9@U9SKBrcAi z9#LIqhUY<{AoOr5l8C*aXUj0f!JLoMx=`InGj;GFH5XG(xUvX!PRmqS0|demGEO9! z*a0$S<;X}vRqt7(83#Q3QT!K)O{w*mj*~Op>_wX%(`Q4bp<-VNa?J>RJEU$~g2DS@ zTYYjN%kd)%u*4M?OF7A~qvkb1fl-aTD8`n#Eg)e`$Fp#~rS4~8z}zM39=tO3hQ7l9 zZVS1qz$w%OsFta;msdx1XGh4a4rhj|ld=%bMV$mvrNC4V)5$WC&$CL?s|_ENwP#$1 zHiycx0aJMvwdqa?*W^Y+ z=|drV2lKPeGF40s%|YaC^aqv@qne`&IOSxDB|KcY!y^4MJ_LOT4;{LNks@u%{DZLw z*}{!s2Zt9U@k|D1#z&x~MGHtL#P$o1f|$pJjVI}+wB~L^%?Jnj!=lK`2wOP(a#v%3 zOCC+Gl6lqUzV?(+)VkQ3HN%EkI8Dc@MA!q$Ob4agX7Tom@);v zRQK~yVHGja;Ql8nkX?l9pBSEdP!APBIb3JH%vV>s{-S(C{1VBlycfs`JN<&m6K)Y6 zg1E#x!8PJO2x364x$YAzyYTLqR%aYDRVNlYdly~y(-F76n}1iT)U>MST^F*ScFRl$ zS-L2KcC%c9l@3r@&^1CQ;j=fG3$>O_4w@*4Cm^OOsI_FUAc4Xbl95$1ds!co2<~KI z3y781D1G89iuBUH?CpN~G9#{MQ|%xyorS&ygZDH17A1_TU9D1~(NF zUw4L(rjJs>l!6)lHTrdnx?DU_wK!wWIK`U zxRvbqR`SwHvVALAb|cAFdwcJ%53y`w97_b`*v3e%4M>gyP_m0UZNvNj4uBy50wU#@ zc9dYqIcM$>^Y*&U&H)86<|HR{AsI@S=>K&y7cS2`Pa1p)jdIcM#;`Q(ScpjBzq52iL<>d)@|LU^VTPfQcqw$? zMNFThgV(`eg;L#OwM=fD?ud;=yU(mWzbeCFEF3-aYq8w*JXV{q-1$vQyKmsa?W{y% z!)z~vnkLs>7U53pDMW&AW-T})cQ(boI&vM=Pm6?x$eQ^>?8LE=jCg89S1N)+0Hf4| zxGG8t?D|kv6;o~%n{ zlZ4P9>Z|aAT9W(@i&Z3HtYYMYJab(yWiV597#Lx#HC>ZLQ~+BD`;n@ugGcRM}V!{QzAlA?d^$X)d2M3D~a1zL};p1R)v&+U7uCNs33g>F($ zEi*A=ffd;lMtrcLFkPEu3ppkxR89w=vbSL2V6)vYxe;p)V^-_bXteY6(51dBD&3Z< zuX$9|557!0bsCAg2F@{%U>HEtzY>t)yaZZXMkMHPjEaY{d1_?yEMT$Em#7=KP$Q$s&}Gbdu!|O4ooIlc z-WdE&bI@)!F0Q@QY9w|JUV_<`G0Q=n6bxDU!`FP*rP@Kk<`JEdzKf{CX-u0?1Q-?LpCC#OeV>3|2jm%P6`Pqe!)^3w4g7Nv*R&U|0EB7VvzO zkF=2|dXFq#ZwKd~RlzxkwG>NPCYKbSkx8FOOtFvykvt(=;4oG^CdTsl>8{le?+XTzq>QP-ks|eh2%TmxRwz2?Z~TB6&gr=6^DEqR)Tcc%H^Wf1A80P zFT*G6d92=m_l%}-Q@94qlXYTs548{$_w1er*nWc&XQDiY1ELd5l74G%as-R%!g?5s z!HpP;CWDaWqqb-Lt1>REjqY8Sl7@^7T{@RD@4 zEVG5L{jQ$EZiBW()0a&Z*r5=#2SfW}gQ0!np?!nQ;`;`^VTAStWKQ1aPcR?v!^t7x zYxBE=Yrn$sZHM9!g?dhpoa>lcf1wqNw~dpV7>~E05Vh33*Qw-i2zQYId*!Ksb_dcHu)k$#&%`fFox@oDAX<(s zD$E2b3Q`#GV!|2Ie$TPTQy1Hc;2>OYY)v+)PprStLAh4Q77u)|t2pN9@rw0;H_#^c zC+gVCs7VgiCI=JM$)V5_!_g-$hjw7RgUO-^uL`>SlTpd+J8_;^AH99fzgl-MFavX{ zrKFqE*;Geff#=WkdEbBy(|h-bY#!dS&W7cWZO=yI;#jo7NRKxTGr=S42-6?y?hOO< zCd4`e2?&0>&Yx%$mm0Jr?kdQp@ON0rO2jJm`!AZUyoFv}(FO|=llW}O>@4j@j4F+J zMb`QljKL zQUoBEnC<3XkrC7_qA#z>i>Wrp|zHVyrVl!cJnl_e>1 z$>K;BDP@=s5r6jpGHwWy1+2OO+}#DDDA;!n!f_cOlYiA z{1^7Q#g3%+GzLv$-bB)i_0b(jzTl_?>C@$C+xl8@bm_J6KjJ1Y5#JKbzgo8{4f50- zzR<(IyYy!4O8TNpeTm&rf3({YUt+&6x`Zv`m@jmX4-NQxl)UzX+|nNu){jcC%V%Su z5(}n0n!4R*?SpSh^F8eQif_45Z=jG*-X5i`XxGC&n@l4GBBJ5Tbwr4d7zm3$?wj=0 z7@~%J+=u)Iq8~WKstIGx7BShAdZK1X_NM7B$Y%~9y=@&7sq#Pqiu6IFo?ZU54*w6C zOJPr0*bK#7fs6<=wwMmCH>=QR!IZFxbR}Z(7(|NhRLm}6^rVpAZeV;s-VaMkNT9Pn zSJ;Se;nx+WM$O;u-)-9HN?2bONlhbBC1R<@5&8jh;8C*?jx+mcam12^{)Q-kJ`kD( z{Tvkb$S1N9%mGnIlV+%jJ?!4IFUDrD>}j&g3!99c;Eu4))ZQ5ziFPCA-xJ322)(E; z?N6)>`$c|SAvnn0C#XH#n;c4X!^Q3zMPUBxiUg9HfnK4~LhPkcn|MYr#P&RSI!Ny| z6DOfm=*vh|s`*m*YW{jZGJ({)VIMIQ^l)n*x}IV4VVnlUn7*&(kogibQ>(F!KP9eG z{fWMKAc1GB#EQsZV#RO*jJmWtp1|Phksk4If%d{(Y$bU>XF9QVr>^Z`Ji8rcUIr9> z=f=0__wD#5+PXV~M#*!P-^PR*W*3<|;--e49NwnHhK zSnkF!`>7sO5A$H=cAVR+7gr&Zl)b&mk162bn#5A%ib|bV)890tZ`|J3o@+^oR(cjKajxjuJ}dUl!RcH|9N=#8}8?eWHpZ))W&@htgtU z7h4wUXmF#efnO!&DkIVQw65Z&Fe{sIfYr^VkZjj7fmy9danLF`LS=$0d8@pfbN-A- zW+l^32`CMpV-TSX(dMTZEr(JKLsr9JqHz%0c+Gyhg=#6TN<`7ztVVxe{`1QZ|D@&F zZz1c7cQk)h5?vEbae16XvA5IVhnbUVEwEgtv=pj^t zrp8l`tg-9QthZ0Bwwj(=%f8W@?Jou{*Tq6zr^Sza!xh#DOWkj8Vcv$f&8hv`*!tTy zWdFS1;CR7%ySFCR{{tUn>mpY-8)hrNQilueAC)@%?op{yhm|_~UKot8&<|yrn`4Kk zGO?7IL$6Sg#oU5Q9aida(UxMBeps1UzQ-q)%6Pay?62T*1(z$hTxPMbP-^viBwYoU zE4W<22{ZSQ!s1<6&hye7nYh%A8V}Q{Jw=^xcq+m3~<1hn0R< zS=&_BHkGx_+cgeU=9ER9Q{FC_zU51_m59(U{2!YajR^g6hMW`G&8!j_I$`o3(NS^2 zHfEwJdp7F{^&f3UpqGC%K`<6Br^SgG4o)$VDz;ihAVh52BMp z+CxO-6#c_4@+y(nBJ7OxSJMKW@ihsI9(Hyu>M?s>HuErk~&|z*N+y;ptU{b zPc_B1wk9_trah4oo045mk6!4V96q-y@XfQ@4(|nwU-x5bJWVBfZK+IZG%i1|$Q|yTrPmzVaQT^i&n9&Q zXJ`NWQOtWbIdSRG>I-$JlB4z`-$4fX1x#=*|N6?OX>inyw39wtdtAp-H1SE4GLE39 z@wk|Q!}Qy7)H@HCP)9!kock+co7?96W6}^EXl%$KY>oXmn-`?iZ(0hy_NY3KkOsSQ zHDdBG7jhqzL7NEsmz?yQ6gCj?R|i(5>abRZk_{?N^sumr%Ot#TnY4`m{JtsGGN8_8 zgt2kS78y%)$Jbrziw&LEwx3S+e{+tIe6Bv{v9gy-mW`XAT=`^E7~d=3ZV2Ojg%cFA z4!)3H{Y~ot^2w-Y-9BLN($TRwKXTTLK88NV$)FE&J(#DeON)7`G*(Fi=k`n?A5KBA z&Ycirh?oM!3ic zXxc{&J3bht5pc<1iKW9gp2NCtO?nM3XZm^9^-=@88gHF%Hd}p97FAZcpYv#(YVBdV ziS)UvJUehsRaNFJ_s%Ol(=wvPebifDSicR&Q3(4}t9bkP3htVW=q{Y-_)@q4?L<-^ z|DPR6U+Soi=Oys~A?hfMIU?nc79?|kGH8U72#!x^T3ZZZHDK5bA1Dl(0;xk`fy7DX zgfJB@stU|53|MG-oj~mi9Yx$mc9@~N8Pwu>Viz8*O_U@tr)=yrdr=!JcT~S4>L9aU zZ(e-Gli81DEM|a!czf4&CkHOCoLm>}iLIaRN@vX!iYHFMloF;OJW8q4by(HHkqqNes$p_)`f;)DI2c6*v?Ve)y-N&(41OKUDU)Nk zLSL8YOJZ6xf&-$v@kF$j^FB(rAIA;{aFB5Tw*-gL&wmuf7G`gHu5u66fI(+!h^P@O zL{t~GDXPD!a_P&47!GFSqUO;yYl&})wxuT$9qBPVPp(h&MAk+7rtlN7o0fa+Y<_#@ zU(9pVKjF{(|UNr4?8n|r=Yd2sxUR!LL_1))jN4@rK-soX*f#Xdb@p&YPtW1~rzUI?* z_@a+_pYu5syQmJ9v7+I_XXA@kNi1i`Ve`eWBwUtZIBFqnG{kTJ)V+MdDQG%-}hk4JBlr zt2-?wWriN!jsxeVo0e^gR`rdqmzfF?V>zuH48xRRdI3jv;wtsU!t2n@rcjr*2P6sS4{e5sv8RGF<%rD2cZKP zJxF>}_$27U8^Hn43AA~TMlzNg-C)uoJ<(+_RY&orh+%CEl!)DfR3{@EX0|bCh(#0e zAfDQ1c7Z5(dBtT}YQNcOhEP;z29Dk$QjUL`OtFV(xUt?u};cnhfKYdW#o=Kkgj5k3J@yB%>vIR@YKAbzEd+$qh>D78Sv>$%6iYsct zzvoyoS@4r2WQmF2m&FNK2cHOKFg$9P{IxI|ZUClU6KJc@~B;3zf%{b1miA}S9#%m^) zv-|iF>u1nzesLWZ{kgK5UP!Oy(#ycz5Z{o!s!xw)uj-QH*{j;fMCJom>STlBjcfiYDBM&jD?uz7}9HBTrUpZWI}uL<@8W!uTKr> z+J60-8q8<=?Av#BZ*brndH)W%(7S*!c)nb;pTRz4H*SzSA_Hh152czTBX*PT(k^D# zhGc*0Aic3ab==Exw_kc>eR>UDqCW(W37!*-5sND#0c3yWu9E$=vHtoEyBemxT754LNqi~TAb18^VzAKA4~<11UY|NS$`~}9 zsC#+B;NqD#l2k)PSiq`btyk0fS}s p zj>pL8PBDDMM2um4-?_H%V4`6XV-i!Cb%?=+!H!8IW*(qsF2PBnG&n12#|l5IB$=n9 zRYsJzhVI*tShgW_WE6jpBRHoUu$x%iyjs-t=Hqb`l)K!I1HNdx-hqox>J<|eSPMww z3zVfN<|V}10P6k_gIHvXU}^?ZE&s?E@%=6hN%o#jU;nzrYUv^G>nyR2*9|OGM-PsL z9`f6FkB1%#Shq|Nrs9MHv5ldJMsfNQ2px+J;&I#00x@9MVo#|i?6pZc1WB{SE2=0f$_$3IG~Ll8a&q|(Xd#@iXK`E zf)cHZLc~Q6jf&y2=%Mv+frvJ!9~%-Uu-G&fdPG7@U_}p&3t-%$`VWmmGZ3aEoRE8^ zg3N8mFG(t`c4#~#;aEz&(~@vQYI|@Xv^^NGb_M#ueZV0bs%{&U> zy`C<735r|TIY)Hs!3-I`l${g(fL@pOT6f{T59;!6MPsDCf=A{sHUL9)dQkuw&z<|k z;h#6PS9~C|A*a{j6F_+cjh&oY@8&Og+_ zLdbiZ@Ajvj@TQ>VS>Us;AcRT^r_`axeC+Be!WdflnBL9zeRgNk_qZ}=c#y#nZoH7! z%!v;vk{b*Z>uRBWFyop1ABH54>+BJVz2|)p^X4+MlO@f4SYnGPx?U0a3CMdqA3(h) z_8AcCx^=H%Db@fxiSnSZ3yv7wipa+&dI(-WIZ7PVQ#t;Eo_dTt!-ayr?~3_O=-6SD z+`@)922TRZe@9?mP^L#=UiebW@pbrCkE?StSg&gbF;S#z`><)HYdHNTyh~OU+Ad$B zL&yADYj`7gj0;cVMvMT;??zG+HIQS8#ie(9c%ubvnp&YB_bNZyEA+#x$a%0=f6NQB z*_-IovCvbmuhRDsCB4>4{ega_eXqSrzq=oEk?{2N-Cpsht;sg4ycIiD?7Xs|$3L1L zTVprqTGc?JfrqsvffQ7$tyKj=a6q+Xe)dZMFJ;3|9$bcPNqOUPJ%ynwBFexnuQ%G^ zV;{|%fH%c%YuE?=iq~g|Ot}zTP!On0?0Ex$d6mftOs346kHg`UJIiG+pO`jllK7C1 zB?|FA9i)#^mpINMz8jb967QzYB*x>Vif^Ts;RPz5{B$y$kN}qN z5JsSUJrd#Aod_4H>|ij!wDar=wuk6O*a-B6gw@pxp1=mfZ+w3OJD;m!{T5(rr3^ZE z729?y)ye9vVl>jUM>pce+gqQUh=Pk&9aMM+jZ&W+Pj%{z$#MLRd)d4gOGpt{Ms(0O zwUS|x0)~1gVWvUd|R~y<|(L0v0e%TPsbCq z7c|n@Rb*TMpL>O`=L_|cgKpjKdF5 zI46S^b-FUXLDuqGdX(W(+clbkhpc^N#6H2U_rY}F0zOTp19c+x@J(17upwZF!EjdH zN|R2iIu%UPOy{B$nNCH9vYpDO`X+q}S1q(XuVWd)1vx6{Q%A*9Jn)0EOH0hIs)}=+ z3i4KUs$G}^yTxcAtzvFql#+Weft{Ln~zz zl2%zIqY!Brd}I`oA#b;rR<#&=7=`3%K#W2R7Fv}ILiN;`wqyXGGgN(*I4lWsFa?J6E@IqkN-OI$6g=?Y*VyFw4L`I*6EH3klTi{-^j3)^hp*i25 z_ojytg#yW@*hXBTYM|8UQv|DGFglxy_< zVC%=UYLX`HWK7q`%=#qTrVJWlh?Q;h6fz^?(GaJl78^3rW8%9saa>tXOd$Y-6N#j_ z&}Ac6{*eqq2*suyE$xu09bsp8pP%hcHg(zd+#AsLvjciN=kDye3-AN%gx*WarDj5V z5Q&y$@*Z)JhjTn7IU^D=%tibTBTbWc=8DayPL%o2C0Tg9Ai99MNNM|xOKjj`br> zCFUKbhAH0dlpL?4cTx#%BemBQH>6c2HapqaNUbtb2h30(WAI~!-6zsq20{?x8Dj zVf`VEKAF-Q;ldzalWoK*dIht&rC|sn8em#rA0OD4ON_I{fOHzGz3!F(E!uR8XSVef;RChP5tgQwWjr+X6NV_k}c->gFY=baCW=CDl(B+ zxykB_ZCpjjI&KF(7FLG6*8a3%tqOaqPbFcD%V@kH`O!-IzMJjKvgCe)x&G=xHPy-j zb>5@Wy6;l!Homy}B2%z$T5EzhkhNGytLvZM-jDi1Y;~$ir0>(Kt$Wu%CG{U(lW@W# zavfi7Kd^=rku~=Azwml6s0?JrR}y%gr8HpI4jRvO*wA>txLAim^FtcClKoH9NVkM+6BjmUvcY zdNDhstR_b86Iz4W2F;^21Z9;GWVykPg4PuDX)QsPoy|dNqJ?F))?(sQJfXEB>KYHBusr!(`2!z2cAVy3|>oO6|x3z8)_ZQj< z6G`W&)?-$)m|bC>pj<1=~YRiHnQGN|WdIg6qf*~mI;1J2L;t(G(eb_;N zLu+|zfc4oRoo9%tdRS{*t097aanG6SSfe3yiA1+0K}cgCj;n}%Uh7B)wAOGyYn$|I z9jB5$4ep!P`fSpC{Vd8Iqvy3F>9Nb&uJoo$tC0KaP2+2>TL_)bbl~zcRbP8?kgaEE zS^RxrqCU|Q_qXDIp)F#jnpqllaE%iW_{Mngh(lc=V{5|I5@B9rC4Hj~vZ^nld}3St zwrg>>fFg@QbwT$~m9V!pVQwQsZ)h;KHQXZr5efst@`-E^F|-cumps+O*`&5cC*w&d zJguFVwaJ5Y9i-C}8bGvYw6IZUYGg~uz?CK(F>**Zg-R!*Ry~x!l2bjSA)@s#BA?mFuE$X>4J9G_&M!( zeB`3mAmWp6yfk04FGzT}BNiNlpLeAIvWzbOP6Z7pFqAtNFB7$4wkNL~WKay&4+97U zPAkkIp=KFd($GOHk+l{u8e*2ZqF=Pg@PxF8kU=0cPBc>)-BYNbI`D_^-S)ZI)) z!Wb4RG@-SCqzGw4ddgtc6xL}Eo3V}dK)(dqGt3~1l0!-u6fm|U=E{XEZYu3@b?x!E zaSWe01_Hq;4OZ4(`u z-r`pkC(dXWvLnkHMp#{pF?08;e;}(3tr@FXhXc&MpO2bDtBmau_Ez99q0TIpT58vTJf>21tj2MjyyOE8>nH>^EI=yn-QqYvoO9Vk~Ylp-_!4cU?y zVg-uZ(eMD<`MBjyv!h_n6+rpH?0mQ(M0oWA8$1gMAi@@?>qf$7Ur3IH`c4N!J!c?w zx?-%_J0d|}s683Pkr~@R?ClO-enu4OL-?S&*d}qnMt>&6&K}Erk+LvS-NZN}gf>Q; zz<}V?**!(OT;jOVCy^QLB@#kNA`nKPbtXHgh>u2$RT4qB$lY3~78T>(PJZIBj)?s# z=%d+4PsuY_BtYUfc-_6C&v@l%egYSS80QKI50(YqA zMcShGRB~%bd-D0$#^)oHH08H^o^`q0USX~bOG_krCGsPnK@?Cw0(Ou57zlN%D5au7 zL{|U~g;0?uN~ma9RIEbvBkIS9&0b%qeyxT7G$JftTj@RmNkCs@uWnNs z(gNFVWI=c6*w;|WmN2YluJ#&P5E|M@bW3^!x7bFMD`dB_SC68#nt>gLtj=7WKpie~ z#dbU!%<7TqFghga3YohEzvMkAz=(HLxr!hdr(mMi%e#Qp8w_6Rf+;d{)xc&X;%VG$ zl%QFyAB17_{QxuPlM3?%}6=Re%65VNp8i>Lw>VXdD*NQY=28p21i4fP3s1M>ld#pO0 z{?7Rtcq04K`bAWh(11RFr%&6zF{Lfpgc#H&?SYN#GV8lxm}`4{!Z1g^1+~j>!K>p~ z(8^YQtM1v?yl8(+1XK*#1Ea~gL>A>sH9DrlcllEVL zuVUe`cN(4o-i~3cO!`AGSKz)teKN7agNUMCCs^I@HxZ15A7!G_!eahmww|e`hYVy7v=fG{ zLL?AUSinF60b>`!C!05tH}gQ|X+m7EXJ4znvJ^%S+!k%0$(W}dG*S$1+E=h)B77b) zDA2o1%(1`{LM+6KZan z^njR8>t!LVtuW{b(lNvvx7H1U(K+BP(|7402@Pf_op~Xwipr>Q&5jy~70E)M?HaYz z$1s&Hi+xc^mgPQt5uYshwI*Snz;$HFueGq|*VvHSS|{Lp*2avp4-?m<1D9?W39a;mrJdNM)v#1JPJ|TalWF=#b<%qvZea5) z*`GN6^6J+!E1J1%9n~#L1eH1Gnw)bq?RI7Og?^&Uz`W%+(#dR1srK}@ zJ0jodlpiegArpBUTucafhDf+P9F}Zd6Zc)7m zULVEYMq50%hWxf=h=Wlsgg6+sS?EF>4B%{A5eEoA3lAbg98jmY={Bq`=pi8vAdeJv z(48Js)InDq=j$v@y5gw)LLGF*eE*!G4^RiP-9jRWO46N5Cb^R3-ZWp{{-EZ1!q3)HBN z=2fa)kr~m4xx!Ln1Y;;VQn(Ns_n~coiiYg=?!bPDbP*ARL!HHFFyROzv``-(MythW z8n(NI>==N~G+G8k!$Xt>C3fhJR+NN=?x39%-O-lDlq7UVTYPPX?w}n9qBQCNs^xkp z8AO&{w|1vDO^epo!SvWgbVs7qr_v*r`X*5yI`wi|Z4BRbJ+cE|MzY{aM+q)#spPd# zH{Lg1ve@2VcR8dTnz*3dz9q48GKdvG=%Mb2?Cyt!2z@pkK=Z}C*cgZEjG0z5JKSwt z#tjQAUZIXOD)VNv6XKHY)dLmB=3ErX4-5%~ddz0CH!jRz#4He}KoB7cdnF;};Z)25 zsn--Pa5hZq?BxlQsownl53}vE1abid7)t}YLRzP6b_(ig(iucBfkhz8Kcr-kS)i7Y zUO-+!Xoz;`{hG1NhIbr&)X)wYVpaBG-DZ17jDND%1Iy2s@<0h<;LQ>~ zQk{Vv46QyqtTn|3Erd(Zzi1Bo5lD%Mgc4KO0y&J8*8g54!pm%YVEVfDf` zG1#wZdHeq1qas~H=WDtMD9JQ>$YvNe8Jia!hEnAm@A&jA7ZLj$xY%Gr%z17sd zY^0W$C?px7y=+jK_Cw6z#xWDUSHn61lbYT0nzYfAHdyZ^SXiOQXuz6f_bF|3q)~h0 zvXzaZCKeW`ykYu?p#`a`G`nL+ z_MTT8=XLC&$eF%{-^J z@=o zH(sN-S6@wePZUgn#XpwJw@5mIa`ZFWv3TH;(9;d^;Y$!7p}H`J#by6&L+X&h4(qsm zFA=_q*fWM4XLkgv$XuK>*ey$OfgUY{1gV(-Q2h?^vVuqfu_P|Q z<)|1Eox~b4(Q!Ze&@@ZhOo+AR>Tm$Pd}++Uv}o8NT4f>aOb!Q-x+TX+6ncp4CJn--B2fv+ox%oq6zjwiiG6StLkkeg z7ABMw8<=#|R+c~2lP1H1nBbJ1oXr>_-PD6+rk==#RNv%iR6C88-y_P3cX6}N{+@@w zaabwqwi${0hN8_z;*NFXEfHCtYA`NNgzAFc`XFZiM$U)!umM*yc!_~4RWm@wX?%!k z@>%VN?;)C`vay?}HWHLJKZ<02Q7Z0X;>sdw4x6OUVSdq&9Z-a-g(mCOVJuCmRghs5=m9ab7YYXlvW|8 zFoKJqHC77hBB&f6c+t;z8@#S5jJ@{A7OQ1)@8k{Hh$CnW?u1#y~M7i^?x# z2|Nk4YJn5UV0gmN$TYinENB=|A2YS%Xc%D4Vz$cjujWzutWTkw^47-uk|8dc} zW@b7`EL6e~X6I!P36IebO3RzwTEF%v4N&r!#}s0v@=H`c=5Zc1lz|*J*?qEb?+WX( zaL3MstlL*)mhFAAYG28seJ6U;x51X&1&eY&TGMQomuw4dp3UG&W0YtNt@jL?jK_Ul z5##)WzE13ehr(X0%;2;I!x?S(ENS1wjO0!1NDf$75eeOk>1wPG&uTN4Y>TcdFA6G6 zQK~6G1H|n_N3Y_|)*Z&e*z3wb(&vogA}IjE9;c6RC$b;(1|H>YmN4Otz$M z*@ASM|9oiIl>e-GIV6r`YLZ3*S2$_kG~z!gC={z6b2Dt(gq|=Eg&h<}Rng@JTS^!! zW%YFgPJApN3osP)T2Ogx<`U6Z)UhBaA;g#ZStTV9X-c&SGxb4PgUKAqa}akZI5bW& zi5`Z|JQJu+2KDH&uRY6<@Jv3ajAKSxx zU3d_JiPakm_{gwTD+@T~5@_9}5PpHMeI49_RC;ie)f}7nmo2Q6$L#PXOjC_ocaKMV zUL3kq{USn4r^P@$nq?>k!s~xK4}@t~iYQyC57VeCVuPWc_)w@jG92no4~G~gF6}w} zCI+oi+U>fPbJwT7~+zA(r4895?JH(>|m&9v(GXS%+7#&7@;>%|v(% z4HahL9dIeOQ~7x567Z6uf9}X#ti*`f80|J=sW@&*-ERm50&$0*CXDDeCH2HI6Y4*N z6&XyvCaTTp+9VQkG4o<**XaOuwYJb=o9%|ljo1(#vs$M{qn!{YXk?af5OAetm`9uJ z)XV)MJa~HOa^KXb-SzZ1M*lXZS|gjMnY-iCO5xT8o z?+y85_RWNv#JK?^8?|=QfY!t>7B+;^G}I$h1h@nuC|cv8p#Rar|3`vm0;FlDyB|O< zlODfJlz6eK6T%=76(@~w+{8}|JsrnC25fxt+nQNj4Y|tb=x~cgH&po$>&`mI4U)d2(NJI zyRI_4!Wdq(UJ^c@@XD^GlhXAnw?r0JN<)|qOyM~wiWe@pd<}*u?Bm^oksM||GBmY$ ze4ip4P{PZ+mI^L;rSPj5_{0hF6^YR+Xq!3URWxt30;5+M;5q-&;h((<~6JX@k`2sn4_$gFX&7m3WzD5eKD zOm|Ff#7!c8{=!@FttnnDv7rDHoHY|FsG&NRP<8C8u%ePZ9@xNn z3o$k)Se2;-T6VQ|P_5lqIIAVxgKVamkV&P3que#<0xIbtLnM{#19$~v(RTp8ydJ{V zq_RSpYGn<{K3|Jz9mDPi%S(Lvq52uEVI2z5Cgj~TYf{$l0kueFVH*7Rrr>v)V_WPN zAz&u#j`aG=-C_L=?;FpFtwWZhnC_m!`r(Py3FPQQd*ax1<;D(n5YW2#7jqf|oflVz z2hVA@Ld9bEWJhu+)H}7#!ee1{1>P_w4Ib=|?l(i-t1samG}`ricK}!=-1i05Z}Ur_H0OD90l_)b*5cC$zXufILI~>w%Fc-RK`JU zeEmyceSDqGJDMUR7WQyNWRcCWwo|XcDRA0hx7Z*%rnr5Fa@;=p+l1Y|31;8M4nlTq zv0R4Osn@zUO$YsMd41a*W33nao?dsUCsu@fX*d!J`;f0>JBlqT>Bji%P0L=a%z@~L z3-;j|(x^4t7yzM7K|cG5Eb_4jn#G!f860vjO3(|J(510Yp(U<`JB%E`br6CJh64mw zjPY4?oOFm%Obm-Or0koCInx$M)3^bX1JOp=JjZ^GqFYn-X+sgN^;tp@+vr=#^Jen8 z(Qcm{x4JNa-+N~0vhra0F3?<+mbh|Dyi*ier5&!^4(}GdR%w?jw~MwaWA#$@iVpfZ zmDS6R$V5Wsj#%E@fr56%>Sag1)k|j%%DunY6MK4H!Y!6- zHbBKTPHx3;P3FWj1v@J*3eAAfNth*ptYiFY8H1fBS;o|%A}#Bf`t(4piHloV$J9lJ zWF1rId&Q{6Kz)CT6&#BhyhMbc5n0dRcEs9lL|M|*r2BDC$65t-?*0@Tg{*9j`|vZ% zLT0(oS}O5lUVE9uhrFrf5~D@0;wm&nOnA?C;}1YBcXs1vAgm{#R<`3nQx-i&;x_S4 zp$OAB{twjJC)S@54H66jh#kS|Aq%;eYP|Pg@-bB_Vo|dEp`5Y=nqB@}6zltVWeB1H zv=x00&e&G0EcnnSYSyEthcCB9`t5zs3;(`ray7D$={L2e^Cg?89B>}7mm{yh)n;XP z-+aV*+kq{kbFS$oDHp@z_6F&Z!i!|JjQcUG(}>!7z$ z&|wQnuXp^;(I&D~hf4YWi*hyH{*G+|R2u23dr_{Dy56DPgGv*<$!G^*`!eR|n!7NbN6@L# zW^cL8G)+u?BM7>nps-a6eu*X7y3^^^koi+4E_Lvu6UT{8Y#^~BGMHE~oIsiH((ZTy z4<$!>;;5%!q~I=CyB>Df#iz)fy0(XHW7*r!fTH*d$L)}bVHpc~`_wA*AXnn!X64{Y z^lpxWJ10JSd;)_ASZ*-VVHM#qs5bAEngYIvP^eUi{mn zeR#yfQ*7#C5h_MS5QJ=#}p|iGVI78BeRWoGV2S}VP!8I=Ou>`EMRY3Nfzi)L;}o%i0#7a!r2UB z8}<^j9YfD4;q%-Eg9pY-wqlVw!;=D>%X`r2xkJbMN)-75Y-HMq7lbrPC=w?~o9x7V zO~fo{kL-_(1i%TB!zO>LX9q5XzlqB~)HDMZkVJ2Z4M&CXHo5LqxNssW5DC7?>gRek zcg(YUreyJiX!z4&E>~83aP(LOqO>gwFC=W>F;jfS{zQ6)H^FTZZCm(E(j>&C{XNs8mQDjr3NZBP^p1R4OD8NQUjG5sMJ8E z1}ZgBsewujRBE771C<)6)Ig;MDm754fl3WjYM@dBl^UqjK&1x0-)f+_M1ht8^M2vZ z2VJfzu4?M4hU_K;V6@;5*K z8}ie``MKYcEBVCde&g4E^W&eCU+?9tSy?@@HZU<3SUa&kuzo|pJq9q~o>1Yq3OA~7 zlY}DycTi&atb4P%dJkbuN7a&`ZVpW3Oay4%WZYNbI zXU+1WFF8d}cN?k-^P$SXV`cK*DsOaExgRGcS0jNX@|~>$l@d(^Mn`Fs_44n2RMNPQ zsqpVqcwB`iB&0-tFR|oiI56@auCLS{PjG*gq><9(e`SeIbq1F7#pRvLN%67wEctVy zD`n}c+z+@PQ{iG{No6LJG1U#6iY~~w^maLNy<9S{>UGOVEtfS*sz&`wW@aQw4rynT z49`uHYnoR`KBsBckBsLxO-$0bUsB;Y75=jdUzU)jxghZZn}(XtHBI4H=4qP3#O_R% z&Z}(LDqM^#m1&y7yv)G?Rqs--PSdO}*)%Fiu4(d;NL$*$)-_Ba!r$$B-b>blyVg}&4%Ii`Azc+s_Y+E z;V-Fhn+iW6Ax-lsi5J*3HJgwD!fI7w@OIc z?2>qaZSzIaYVw)PswVF7qbRqcG`SW!FJ+rExUCz_ zAKbp7${$nV3o5i#cuqnZ=w*o)*g!9lHaEBxe5F+T#>cx?U-|t* zYXj~o9*|>}XeASY4I}bDr~2l8MXFsbf#t(nhUF3}OFI56R1rGznG9>;eOxgWjKfKQ zjj(ojG_Zl0U=0ZZZm$aaRp?WpE+HK`AhC30x1p}yBX79^H^C&89NB(R__a9&la%s6 zCWpCVepJ3xJVYv*c|@MEOSo5DtB zKT`??i>9!=)Y(k^q{_$#RJbUaDn`P*DJ(BHb81_44XNB&EG$jWsx%H3=B3HC&>u^*Y4chr?=uT%p}f@YOs2k|GV*y9 zE=s1Z&_a2+DcwR+xw9>lN3#M4Q&cOeG)@cUrFkD|WWg6$w{Bfv-NXi#d?3rcs-*X; z@IDnjpu)eFkft~!vBL7dk*j$*SqDg^Fq}1C!I$J6Yso?m{|oQVDX*mDRYmy!b;*P3 zUBAt}t(=r-jDc}fmPr$Vb>ji|DM{lFtMF+RS}J@-LP~T-;stiDXGxnKL4`Sar4LT3 zk36Nq@9u-y8NaYt8KzmLOXu^cic*zan@X+CcAG5GmPJ_R&0Lkrv?hhESz0x+A)sas zb=R3ha#Kqtfto}!3G(I>)d$rFojzECO8j@Jrs9Q^@NUP}I)lU;sw&@9VOoXXR^h)% zNIT9*yufz+57K63`(L8@chZPxH0{_>X?Dq4oorEP7nO^izCUzUy-R{7~-o3}|`qp`Ul)1@HNd8$W;3 z?`5(irRNRm;M(na@2`FQcYZzhSngev`PYB_JsZChOaDa%()uR3~4fWjm%z>QoitS$3JUT%lkOL{HN1r1t!Sji9dA5PyMlhBJ3atqNR@Vt58RH_WBawXCF&_qxSS1x_>v4yfcI>E)1T)RBEp?&mulOMdD( z9lRhvf)@h+coAIiLf}5qIQ^e%!3%-Qc6>fu@Iv5gN#pc?t_3dy{+FD^a6pTC$al%Y zY`^74t{vsWGVH1&3(x&5j^#aaQk2X=`Vmfn$zbdBe_+!81wL2?z7}|?_pB=e9|g{9 zGe_Qc*XLjo0}sLwk?#uk=R3KM3*3{<&p;*_Vdf&2fBBh9F7L^&pJKSAy_Sy~$b11_ zQ#VpxflHe><;}tYl{{|9LU}ZE%#%KsY_Z}ScyT?agV*Fo@LJ#vMR37uffwL4Fu`kq z{~V`-*T4j?1zv#Hzyz-a{wYoeud{GKi+bF^+okULT;|{+*Ny^r@Hz|6B`c0^$O0Vv zCB5K_z=`Jc2Z75e_te3K;L#2I_#w{x_sBRP@b{I0{|IoBWDYKJ@A<#Wz~2u%zrW?u z|7i9VD&jpd4&1^3^r#|ONpGm!Vq2wn)W}I<={Kz;U@PcswxQqh=FBk`a%QztLf^h)2i~|C1 zW3g#%vHL%u6@PZlx<-_5n7!1-AK&;2Zp17-c__Msf7!G(*50xLj zKo&Abw*Cdqr8?D(Jh`o5}h%PN!V3 z-(98CogKU;KZ5T9FTi);g6{$^z<1z+@1@{^ z?*d;%?BF%&1>Xf;fbUs2;6*)d=Iv7VWFd3#-CR3X0g+Q3dGMP7W#E4bJilM%@_8$8=OCYg?>7S|z<1z+?*hMtv($S4 z&*|qk3y@=>{XdiXdp{JO)3*F_!9tgQB5>iRJLS#70hK%?y&O(`&XYcqdhtTZ&uZG) z!FTc__%84QdOJy~;(jja9jwcct#hLgwJRxppkT_dK{flb>GjNMJ`e9egLf;Jd(&mVrN32L9DDaM9o@ z_1zO?;D>?d_p4k!Ma9fH$fw}D)5%fPKN@UH_e_1$O7z`q7OzhC9@c?P(1kWayP$!7t+0~dT3_-W2k?~!+u>i?zS z0=t$Eo6K+HbjpiBi}VwLb2$eNsN`X1p-z2f-%~R2I{=jY6!7iIkKnt&*O5tQ8~`r( zE^wjm9DW^e!FPcRA2=T__%86z5E&?h zbDs2>)QcBNe*TPhcJP|~2)+xv0N;TNz6-nn-+>Fh3%mf|feXG1yn($Q2d{w(z6-nn z-?MPQi+ad+rS8c>=HR=zb}Yd6Jh(iQpI-1tVBh9+@SXI6?*jk#GVt$|flG!;y$2c7 zlHXlY2L2}R=T_z*Ke>D^b%5LgF8D6_EpHZHu0)bvj%=hJmiN3{hvY|egB*M(|AOxVFIdk57kn3Z z!FnFJ;Cm^!;Jd(g6Fc}$dck*r7p&*A@WrkN`7Zync*J*e?O1^Cd2o4#EN2ejf=2>t z<#g~AxZu0M+snW^%fP$Kz*hh-_1)ew@D||w&&el>1+xeF6nvL_7T`ND!FPf8aXOCx z&y`nR;@~y#T)mZo&wlXQywa(FiTv``XUZ#ZE@$f@3olnnNiT;}pYx>8q+Yx*mwyM} z$&cW>z-1oEhYP+7d<)re*6pMhd@ltTd>8opN$=o0=>^{f9^@>BFJ4JAZEJ2( z5j+)`Sq2^e&VS}0z4ZTU{TQYUvd`||FG5#>zXBKet73S$@=AI+vXOfD-JHK9KR-i$ zoPJATq(7^CaxWh){aN5ok>2Ugq?i6I@L&;K`m?~V=XCll>7_pld}|3fuUOPWzRUmY zyg+_(?I<5+X`MN;@Z8VhSl%NiMadkbmwqlVF_+`u3vj^~fh#%NTt~@+i;YUykF)i`EJ2H1zhGSflGd!M}X(@FYm}@Q#yBk{S?EU?_Hx8KSTv= z%P%ix7Nooa=W@0lvhZ@nl=O0BBlYmRiPw^!1gC?)$a3ZYF8yC% zKf>wYFL1$Mfxo{D{Kv|`f1(WhgTPCD_b1E1e;7FbbMpCN2goh*Dflk=EWmf*g6{(V z5U2A)v=c#~g6u>EOQ>MHE=W-6bTv;W(98P^^-;;s9^P%LY z0N=@v;Jd)5$c}^Wzy;q0UV!hw1>Xf;fbYNs-vwTP@4yA$1+H;A_@0F?b`8jP`Jcrj zzAOD!;05@e2bX(fIdcFPd>5G5P;>AdxZu0Mf4K~NTN(H#%fNpHc&YDxstjE0yYW9K zpPzAn+#;WX?~=~~d{>omds- zS5`?chf|;Pq|c;YyioEZ{oKK8@+0^z@DFh2!v)_3E_Udgd7Siu?*ji4@5zS?z6-p7 zpGEL@7zIY|gyji}>|12KyUBUMp+*!A0;pOrp>E&?no%Dh)0wRz&-4!$e>Rsb>v$e5^(Jh7c=6%x3I3{pu=Th&HSCs1iCE)_RhL3LQU>o^& z%G;XhCj#ek4!m4ZCA}O@eP-X2fxh#hwK;Q-Ie9}vQ5_rKn zAGqMVz@?u$^E+_q-vWPw_ZPz#y9VUDQujoegZv1-3%p>Rp9hzF`RS!R0$ai9;3??^ z-v!=R2CnpCavdly{d>x!zaBXMPCj$rU0nv=16<0c4&I+jF9s}~1GwP3JzM-I;4V3feDCehKl74391IWqghFpi}voId^j3{V1B(KZ7RtPoecaGxOt4x?kn$Kch+dDc3K$ewq6IG3QS1 z$@$}(mbk{gMZU$jXL0I}<&`tx&Xlup$){YBerD$PTz^h@+nlE|Z~5XJ_^r@9Z zU1L8?*?u40y}#o8U!1vTZq6&`GEb(Qt01SrruI28TnOe^LqapjdJ{vb@<2w9>G`gGIE$-H$ zCuX1i57&2?=R9uaJ<`14?KVlHIq9}=wbdOYT&rNKoIA76&Udw~+BMdRyy}m$;P`FMJ2-RCg!0Py3)ymh zj&e$R#zXhd@x5Ox`sT;8zkfL!e=-~Y5}qu!xj*5)(fun$PvpKfGxK5hN8CT<{%Q9| z-5(>(k2>i-#nq?XpCSBt1$)19XZG3ouC~><#tu`qi>$9&SX7U4=ANi(kpOGQuQzBV)S2kt*~|B3r% z_aC|cm^7bt((U4ExBGU&|EgfW8%nWA5WcPvpKfGjqTD0rvs- zLHA#~|AsVQanhaO>T&lIgnz4GcRP1xpPlb&Tb*m{GG)`@b$^iacQ|v;G&4`;=9S;i z_S@a`TS-4N^ELNbzW035H)Gk~FJ|NO+4u$bH{7=SocksBKNmfb``XM**loF=b)R-W zDmvS<9%TbR+(iT>2 z??-Y-($CCXR$p7<$$w(@x+)7_TIT+2%Gs+o-QRZqhxv-f91?Q zCHuCyew%QA0b2gY*oXT^m!zMW+35K(zW0HmZ+-izi4}0F{`M*dr?xg!^u71YzvxGmcU}Mgm*=Ogw+SbIp(&lpgWIJnI z&b^$uXJo%>wwzPha%yf#KQr@5&rN*q^F`nM{p{~AWaB@|#=qzJUC$qQ{?PNsoYu%&j>%KU>|qx%sxBc)lJQ=v9D6L8#-po zmwQI`2Xg(kik+HU++Sj!<$1THX9e%Mhwt52=9~A=f#2(S!1LFh1D=C(?&Q9Ahv&;hTIjcw@xOJ_cR5#KlQ;KN zh7pn(hu-uYcl+Qj3!N?LXJ(FhzQ*^SD*9$P`+G7Qe?1#N?K$PKJkNNZ^_(txBKNhK znZNh^gXe#F{m!faJnf?8*+4$eHaoY2S=i8ot^ZbYBJ4H|A uzBV&+!E@2`n&(@dS3Tb(&AHihTru3^*70=(vuE$jK0N=`9e?)Hj{gInhsg{8 literal 0 HcmV?d00001 diff --git a/els-f280049c/nextion-notes.txt b/els-f280049c/nextion-notes.txt new file mode 100644 index 0000000..f070dfd --- /dev/null +++ b/els-f280049c/nextion-notes.txt @@ -0,0 +1,22 @@ +To compile the Nextion HMI file, you'll need the Nextion Editor. A precompiled +Nextion TFT file is included. To load the TFT file to the display, copy the file +to a uSD card, insert into the Nextion display, power it on, and watch +the messages. Once firmware is loaded, remove card and power cycle everything. +https://nextion.tech/nextion-editor/ + +The ELS code was built using Code Composer Studio 10.1.0 and C2000Ware 3.02.00. + +The ELS code can be compiled in legacy COFF or to the new eabi (ELF) formats. +However, until C2000Ware is fixed, references to F28x_usDelay may need to be +changed to _F28x_usDelay. Places in C2000Ware that must be updated are +f28004x_sysctrl.c and f28004x_examples.h. Here is the message about the problem. +First try without making any changes and if undefined references to F28x_usDelay +are seen, switch to COFF or make the changes. + +https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/893565/3303362?tisearch=e2e-sitesearch&keymatch=F28x_usDelay#3303362 + +BUT I only managed to get ELF files to work with RAM, not with FLASH. I only +managed to get COFF files to work with FLASH. + +August 2020 +Kent A. Vander Velden (kent.vandervelden@gmail.com) diff --git a/els-f280049c/nextion.cpp b/els-f280049c/nextion.cpp new file mode 100644 index 0000000..5abc47a --- /dev/null +++ b/els-f280049c/nextion.cpp @@ -0,0 +1,650 @@ +/* + * nextion.cpp + * + * Created on: Aug 25, 2020 + * Author: Kent A. Vander Velden (kent.vandervelden@gmail.com) + * + * Summary: The routines here translate between the existing seven + * segment display and the Nextion, leaving as much code untouched + * as possible. Two UARTS are used, SCIA for virtual COM debugging + * and SCIB which connects to the Nextion. An additional GPIO pin + * is used as a limit switch input, which may be useful as a hard + * limit to profile or thread up to a shoulder. + * + * Other than the TI routines at the end of this file, which have + * their own terms, the code is released to the public domain + * "as is" and is unsupported. + * + */ + +#include "F28x_Project.h" + +#include +#include +#include +#include +#include "driverlib.h" +#include "device.h" +#include "nextion.h" + +typedef unsigned char uchar_t; + +// Set to 1 to enable debugging of the Nextion messages over the +// virtual COM port. +#define NEXTION_DEBUG 0 + +#if NEXTION_DEBUG +#include "launchxl_ex1_sci_io.h" + +static void scia_init(); +//static void transmitSCIAChar(uint16_t a); +//static void transmitSCIAMessage(const unsigned char *msg); +//static void initSCIAFIFO(void); +#endif + +static void scib_init(); +static void transmitSCIBChar(uint16_t a); +static void transmitSCIBMessage(const unsigned char *msg); +static void initSCIBFIFO(void); + +static int nextion_read(uchar_t buf[], const int nmax) +{ + int n = 0; + + while (n < nmax && ScibRegs.SCIFFRX.bit.RXFFST) + { + uint16_t ReceivedChar = ScibRegs.SCIRXBUF.all; + buf[n++] = ReceivedChar; + + // This delay is done to increase chances that a complete message from + // the Nextion will be received in one function call. To eliminate the + // delay, add memory to the Nextion routines, continuing to + // read and tokenize per call until a valid message is gathered. + // ~208us to transmit 8-bits at 38.4kBaud + DELAY_US(500); + } + +#if NEXTION_DEBUG + if (n > 0) + { + printf("%d:", n); + for (int i = 0; i < n; i++) + { + printf(" %02x", buf[i]); + } + putchar('\r'); + putchar('\n'); + } +#endif + + return n; +} + +static void nextion_send(const uchar_t *msg) +{ + transmitSCIBMessage((const unsigned char*) msg); +} + +void nextion_init() +{ + // Configure the GPIO pin for the limit switch input + // GPIO_setPinConfig(GPIO_25_GPIO25); + GPIO_SetupPinMux(25, GPIO_MUX_CPU1, 0); + GPIO_SetupPinOptions(25, GPIO_INPUT, GPIO_OPENDRAIN | GPIO_PULLUP); + +#if NEXTION_DEBUG + GPIO_setPinConfig(GPIO_28_SCIRXDA); + GPIO_setPinConfig(GPIO_29_SCITXDA); + + GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC); + + scia_init(); +#endif + + GPIO_setPinConfig(GPIO_13_SCIRXDB); + GPIO_setPinConfig(GPIO_40_SCITXDB); + + GPIO_setPadConfig(13, GPIO_PIN_TYPE_PULLUP); + // GPIO_setPadConfig(40, GPIO_PIN_TYPE_PULLUP); + + GPIO_setQualificationMode(13, GPIO_QUAL_ASYNC); + + scib_init(); + + initSCIBFIFO(); + +#if NEXTION_DEBUG + // To help with debugging, configure the UART that is connected to + // USB port, the virtual terminal, to be stdout. + volatile int status = 0; + status = add_device("scia", _SSA, SCI_open, SCI_close, SCI_read, SCI_write, + SCI_lseek, SCI_unlink, SCI_rename); + volatile FILE *fid = fopen("scia", "w"); + freopen("scia:", "w", stdout); + setvbuf(stdout, NULL, _IONBF, 0); +#endif +} + +// Wait for the Nextion to become ready. +void nextion_wait() +{ + // The easiest way to while for the Nextion to be ready with a fixed delay + // to have a fixed delay. + // DELAY_US(250000); + // But the required time, while short, is unspecified. Instead, wait for + // the Nextion to send a ready message, eventually timing out if necessary. + // + // Nexiton will send + // 0x00 0x00 0x00 0xff 0xff 0xff + // on start up, and + // 0x88 0xff 0xff 0xff + // when ready. Often both messages will be read in a single + // nextion_read(...) call + // + // The Nextion is ready fast and I rarely saw the ready message unless + // power cycling only the Nextion. It may be better to test if the Nextion + // is ready by checking its response to a query like which page is current. + + // Timeout after 40 * 25us = 1s + for (int i = 0; i < 40; i++) + { + const int nmax = 6; + uchar_t msg[nmax]; + int n = nextion_read(msg, nmax); + if (n > 3) + { + bool has_end = msg[n - 3] == 0xff && msg[n - 2] == 0xff + && msg[n - 1] == 0xff; + if (n >= 4 && msg[n - 4] == 0x88 && has_end) + { + break; + } + } + DELAY_US(25000); + } +} + +// Update the Nextion feed display using the same information used +// to update the seven-segment display. +void nextion_feed(const FEED_THREAD *f, LED_REG leds) +{ + { + uchar_t msg2[8 + 4 + 5] = { "t1.txt=\"" }; + uchar_t *p = msg2 + 8; + for (int i = 0; i < 4; i++) + { + Uint16 a = f->display[i]; + Uint16 pnt = a & POINT; + a &= ~POINT; + switch (a) + { + case BLANK: + *p++ = ' '; + break; + case ZERO: + *p++ = '0'; + break; + case ONE: + *p++ = '1'; + break; + case TWO: + *p++ = '2'; + break; + case THREE: + *p++ = '3'; + break; + case FOUR: + *p++ = '4'; + break; + case FIVE: + *p++ = '5'; + break; + case SIX: + *p++ = '6'; + break; + case SEVEN: + *p++ = '7'; + break; + case EIGHT: + *p++ = '8'; + break; + case NINE: + *p++ = '9'; + break; + default: + *p++ = '?'; + break; + } + if (pnt) + { + *p++ = '.'; + } + } + *p++ = '"'; + *p++ = '\xff'; + *p++ = '\xff'; + *p++ = '\xff'; + *p++ = '\0'; + nextion_send(msg2); + } + + { + const uchar_t *msgs[5] = { "b8.txt=\"mm Pitch\"\xff\xff\xff", + "b8.txt=\"mm / rev\"\xff\xff\xff", + "b8.txt=\"TPI\"\xff\xff\xff", + "b8.txt=\"inch / rev\"\xff\xff\xff", + "b8.txt=\"???\"\xff\xff\xff" }; + + int i = 4; + if (leds.bit.THREAD && leds.bit.TPI) + { + i = 2; + } + else if (leds.bit.FEED && leds.bit.INCH) + { + i = 3; + } + else if (leds.bit.THREAD && leds.bit.MM) + { + i = 0; + } + else if (leds.bit.FEED && leds.bit.MM) + { + i = 1; + } + + nextion_send(msgs[i]); + } + + { + const uchar_t *msgs[5] = { "b9.txt=\"Right Hand\"\xff\xff\xff", + "b9.txt=\"Left Hand\"\xff\xff\xff", + "b9.txt=\"Forward\"\xff\xff\xff", + "b9.txt=\"Reverse\"\xff\xff\xff", + "b9.txt=\"???\"\xff\xff\xff" }; + + int i = 4; + if (leds.bit.THREAD && leds.bit.FORWARD) + { + i = 0; + } + else if (leds.bit.THREAD && leds.bit.REVERSE) + { + i = 1; + } + else if (leds.bit.FEED && leds.bit.FORWARD) + { + i = 2; + } + else if (leds.bit.FEED && leds.bit.REVERSE) + { + i = 3; + } + + nextion_send(msgs[i]); + } +} + +void nextion_rpm(Uint16 rpm) +{ + static bool do_once = true; + static Uint16 p_rpm = 0; + + if (p_rpm != rpm || do_once) + { + uchar_t msg2[32]; + sprintf((char*) msg2, "t0.txt=\"%u\"\xff\xff\xff", rpm); + nextion_send(msg2); + + p_rpm = rpm; + do_once = false; + } +} + +KEY_REG nextion_loop(bool alarm, bool &enabled, bool &at_stop, bool &init) +{ + static bool do_once = true; + bool p_enabled = enabled; + + // Check the limit switch and update the enabled state + at_stop = GPIO_ReadPin(25); + enabled = enabled && !at_stop; + + // Receive message from Nextion display + const int nmax = 12; + uchar_t msg[nmax]; + int n = nextion_read(msg, nmax); + + // Feed_mode must be initialized with the same that's initially shown on the seven-segment display. + // This is a kludge but correcting this might have involved more changes in the original code. + // Worse case is the two are initially out of sync, but will sync up once the mode is changed. + static int feed_mode = 3; + + // Decode message from Nextion display and emulate a seven-segment key presses + KEY_REG key; + key.all = 0; + if (n > 3) + { + bool has_end = msg[n - 3] == 0xff && msg[n - 2] == 0xff + && msg[n - 1] == 0xff; + + if (has_end && (n == 10 || n == 4) && msg[n - 4] == 0x88) + { + // Reinitialize the screen if the Nextion resets, through a flag + // passed back to UserInterface the feed information is reinitialized. + do_once = true; +#if NEXTION_DEBUG + printf("Reinitialize\r\n"); +#endif + } + else if (has_end && n == 7 && msg[0] == 0x65) + { + // Touch Event + uchar_t page_num = msg[1]; + uchar_t comp_id = msg[2]; + uchar_t event = msg[3]; + + if (page_num == 0 && event == 1) + { + switch (comp_id) + { + case 9: + key.bit.DOWN = 1; + break; + case 10: + key.bit.UP = 1; + break; + case 14: + // Consider the desired state of the LEDs and what keys must be pressed to move to desired state. + // Desired state for each feed_mode: + // 0: + // leds.bit.THREAD = 1; + // leds.bit.MM = 1; + // 1: + // leds.bit.FEED = 1; + // leds.bit.MM = 1; + // 2: + // leds.bit.THREAD = 1; + // leds.bit.TPI = 1; + // 3: + // leds.bit.FEED = 1; + // leds.bit.INCH = 1; + feed_mode = (feed_mode + 1) % 4; + switch (feed_mode) + { + case 0: + key.bit.FEED_THREAD = 1; + key.bit.IN_MM = 1; + break; + case 1: + key.bit.FEED_THREAD = 1; + break; + case 2: + key.bit.FEED_THREAD = 1; + key.bit.IN_MM = 1; + break; + case 3: + key.bit.FEED_THREAD = 1; + break; + } + break; + case 15: + key.bit.FWD_REV = 1; + break; + case 18: + // Remain disabled if limit switch is tripped, else toggle enable. + enabled = !at_stop && !enabled; + break; + default: + break; + } + } + } + } + + // Set credits message once + if (do_once) + { + const uchar_t *msg = { "t2.txt=\"ELS 1.1.02\r\n" + "James Clough - Clough42\r\n" + "\r\n" + "Nextion display\r\n" + "Kent A. Vander Velden" + "\"\xff\xff\xff" }; + nextion_send(msg); + } + + // Update alarm indicator + { + static bool p_alarm = true; + const uchar_t *msgs[2] = { "r1.val=0\xff\xff\xff", + "r1.val=1\xff\xff\xff" }; + + if (p_alarm != alarm || do_once) + { + // In this fast loop, update the display only if needed to avoid flicker. + nextion_send(msgs[alarm ? 1 : 0]); + p_alarm = alarm; + } + } + + // Update the enable/disable button + if (p_enabled != enabled || do_once) + { + const uchar_t *msgs[2] = { "b11.txt=\"Enable\"\xff\xff\xff", + "b11.txt=\"Disable\"\xff\xff\xff" }; + nextion_send(msgs[enabled ? 1 : 0]); + } + + init = do_once; + do_once = false; + + return key; +} + +// =========================================================================== +// The support function below are from or based on TI's C2000Ware examples. +// Most are from sci_ex1_echoback.c, and below is the associated TI license. +// =========================================================================== +// +//############################################################################# +// $TI Release: F28002x Support Library v3.02.00.00 $ +// $Release Date: Tue May 26 17:23:28 IST 2020 $ +// $Copyright: +// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#if NEXTION_DEBUG +// +// scia_init - SCIA 8-bit word, baud rate 0x001A, default, 1 STOP bit, +// no parity +// +static void scia_init() +{ + // + // Note: Clocks were turned on to the SCIA peripheral + // in the InitSysCtrl() function + // + + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + SciaRegs.SCICCR.all = 0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + SciaRegs.SCICTL1.all = 0x0003; + + SciaRegs.SCICTL2.bit.TXINTENA = 1; + SciaRegs.SCICTL2.bit.RXBKINTENA = 1; + + // + // 115200 baud @LSPCLK = 25MHz (100 MHz SYSCLK) + // + SciaRegs.SCIHBAUD.all = 0x00; + SciaRegs.SCILBAUD.all = 0x1A; + + // + // Relinquish SCI from Reset + // + SciaRegs.SCICTL1.all = 0x0023; + + return; +} +#endif + +// +// scib_init - SCIB 8-bit word, baud rate 0x001A, default, 1 STOP bit, +// no parity +// +static void scib_init() +{ + // + // Note: Clocks were turned on to the SCIB peripheral + // in the InitSysCtrl() function + // + + // + // 1 stop bit, No loopback, No parity,8 char bits, async mode, + // idle-line protocol + // + ScibRegs.SCICCR.all = 0x0007; + + // + // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE + // + ScibRegs.SCICTL1.all = 0x0003; + + ScibRegs.SCICTL2.bit.TXINTENA = 1; + ScibRegs.SCICTL2.bit.RXBKINTENA = 1; + +#if 0 + // + // 9600 baud @LSPCLK = 25MHz (100 MHz SYSCLK) + // + ScibRegs.SCIHBAUD.all = 0x01; + ScibRegs.SCILBAUD.all = 0x44; +#else + // + // 38400 baud @LSPCLK = 25MHz (100 MHz SYSCLK) + // + ScibRegs.SCIHBAUD.all = 0x00; + ScibRegs.SCILBAUD.all = 0x50; +#endif + + // + // Relinquish SCI from Reset + // + ScibRegs.SCICTL1.all = 0x0023; + + return; +} + +#if NEXTION_DEBUG +#if 0 +// +// transmitSCIAChar - Transmit a character from the SCI +// +static void transmitSCIAChar(uint16_t a) +{ + while (SciaRegs.SCIFFTX.bit.TXFFST != 0) + { + + } + SciaRegs.SCITXBUF.all = a; +} + +// +// transmitSCIAMessage - Transmit message via SCIA +// +static void transmitSCIAMessage(const unsigned char *msg) +{ + int i; + i = 0; + while (msg[i] != '\0') + { + transmitSCIAChar(msg[i]); + i++; + } +} + +// +// initSCIAFIFO - Initialize the SCI FIFO +// +static void initSCIAFIFO(void) +{ + SciaRegs.SCIFFTX.all = 0xE040; + SciaRegs.SCIFFRX.all = 0x2044; + SciaRegs.SCIFFCT.all = 0x0; +} +#endif +#endif + +// +// transmitSCIAChar - Transmit a character from the SCI +// +static void transmitSCIBChar(uint16_t a) +{ + while (ScibRegs.SCIFFTX.bit.TXFFST != 0) + { + + } + ScibRegs.SCITXBUF.all = a; +} + +// +// transmitSCIAMessage - Transmit message via SCIB +// +static void transmitSCIBMessage(const unsigned char *msg) +{ + int i; + i = 0; + while (msg[i] != '\0') + { + transmitSCIBChar(msg[i]); + i++; + } +} + +// +// initSCIBFIFO - Initialize the SCI FIFO +// +static void initSCIBFIFO(void) +{ + ScibRegs.SCIFFTX.all = 0xE040; + ScibRegs.SCIFFRX.all = 0x2044; + ScibRegs.SCIFFCT.all = 0x0; +} + +// =========================================================================== diff --git a/els-f280049c/nextion.h b/els-f280049c/nextion.h new file mode 100644 index 0000000..80f4afc --- /dev/null +++ b/els-f280049c/nextion.h @@ -0,0 +1,20 @@ +/* + * nextion.h + * + * Created on: Aug 25, 2020 + * Author: Kent A. Vander Velden (kent.vandervelden@gmail.com) + */ + +#ifndef NEXTION_H_ +#define NEXTION_H_ + +#include "Tables.h" +#include "ControlPanel.h" + +void nextion_init(); +void nextion_wait(); +void nextion_feed(const FEED_THREAD*, LED_REG leds); +void nextion_rpm(Uint16 rpm); +KEY_REG nextion_loop(bool alarm, bool &enabled, bool &at_stop, bool &init); + +#endif /* NEXTION_H_ */ diff --git a/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs b/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs index 8e309e6..70ecb0b 100644 --- a/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs +++ b/testfixture-f280049c/.settings/org.eclipse.core.resources.prefs @@ -1,15 +1,4 @@ eclipse.preferences.version=1 -encoding//Debug/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 -encoding//Debug/makefile=UTF-8 -encoding//Debug/objects.mk=UTF-8 -encoding//Debug/sources.mk=UTF-8 -encoding//Debug/subdir_rules.mk=UTF-8 -encoding//Debug/subdir_vars.mk=UTF-8 encoding//Release/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 encoding//Release/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 encoding//Release/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 From 398eef4bb7c13754179003e8e1a093445f2282d5 Mon Sep 17 00:00:00 2001 From: Kent VanderVelden Date: Tue, 13 Oct 2020 11:28:37 -0500 Subject: [PATCH 2/9] Ported to CCS10.1 and C2000Ware3.03 --- els-f280049c/.cproject | 260 +- els-f280049c/.project | 63 + .../org.eclipse.cdt.codan.core.prefs | 100 + .../org.eclipse.core.resources.prefs | 18 +- els-f280049c/28004x_generic_flash_lnk.cmd | 57 +- els-f280049c/28004x_generic_ram_lnk.cmd | 41 +- .../common/include/F28x_Project.h | 51 - .../common/include/device.h | 307 -- .../common/include/driverlib.h | 82 - .../common/include/f28004x_adc_defines.h | 83 - .../common/include/f28004x_cla_defines.h | 199 -- .../common/include/f28004x_cla_typedefs.h | 128 - .../common/include/f28004x_cputimervars.h | 143 - .../common/include/f28004x_defaultisr.h | 202 -- .../common/include/f28004x_dma_defines.h | 193 -- .../common/include/f28004x_epwm_defines.h | 342 -- .../common/include/f28004x_examples.h | 429 --- .../common/include/f28004x_globalprototypes.h | 256 -- .../common/include/f28004x_gpio_defines.h | 105 - .../common/include/f28004x_pie_defines.h | 72 - .../common/include/f28004x_sysctrl_defines.h | 59 - .../common/source/f28004x_adc.c | 102 - .../common/source/f28004x_codestartbranch.asm | 111 - .../common/source/f28004x_cputimers.c | 194 -- .../common/source/f28004x_dcsm_z1otp.asm | 186 -- .../common/source/f28004x_dcsm_z2otp.asm | 159 - .../common/source/f28004x_defaultisr.c | 2780 ----------------- .../common/source/f28004x_dma.c | 1104 ------- .../common/source/f28004x_gpio.c | 441 --- .../common/source/f28004x_piectrl.c | 124 - .../common/source/f28004x_pievect.c | 315 -- .../common/source/f28004x_spi.c | 177 -- .../common/source/f28004x_sysctrl.c | 876 ------ .../common/source/f28004x_usdelay.asm | 92 - .../headers/cmd/f28004x_headers_nonbios.cmd | 303 -- .../headers/include/f28004x_adc.h | 1048 ------- .../headers/include/f28004x_analogsubsys.h | 232 -- .../headers/include/f28004x_can.h | 607 ---- .../headers/include/f28004x_cla.h | 366 --- .../headers/include/f28004x_cla_prom_crc32.h | 157 - .../headers/include/f28004x_cmpss.h | 299 -- .../headers/include/f28004x_cputimer.h | 134 - .../headers/include/f28004x_dac.h | 156 - .../headers/include/f28004x_dcc.h | 203 -- .../headers/include/f28004x_dcsm.h | 658 ---- .../headers/include/f28004x_device.h | 276 -- .../headers/include/f28004x_dma.h | 214 -- .../headers/include/f28004x_ecap.h | 309 -- .../headers/include/f28004x_epwm.h | 1237 -------- .../headers/include/f28004x_epwm_xbar.h | 830 ----- .../headers/include/f28004x_eqep.h | 301 -- .../headers/include/f28004x_erad.h | 306 -- .../headers/include/f28004x_flash.h | 366 --- .../headers/include/f28004x_fsi.h | 660 ---- .../headers/include/f28004x_gpio.h | 1678 ---------- .../headers/include/f28004x_i2c.h | 251 -- .../headers/include/f28004x_input_xbar.h | 112 - .../headers/include/f28004x_lin.h | 576 ---- .../headers/include/f28004x_memconfig.h | 867 ----- .../headers/include/f28004x_nmiintrupt.h | 178 -- .../headers/include/f28004x_output_xbar.h | 905 ------ .../headers/include/f28004x_pga.h | 164 - .../headers/include/f28004x_piectrl.h | 702 ----- .../headers/include/f28004x_pievect.h | 297 -- .../headers/include/f28004x_pmbus.h | 291 -- .../headers/include/f28004x_sci.h | 256 -- .../headers/include/f28004x_sdfm.h | 797 ----- .../headers/include/f28004x_spi.h | 193 -- .../headers/include/f28004x_sysctrl.h | 2062 ------------ .../headers/include/f28004x_xbar.h | 372 --- .../headers/include/f28004x_xint.h | 138 - .../source/f28004x_globalvariabledefs.c | 861 ----- 72 files changed, 407 insertions(+), 28806 deletions(-) delete mode 100644 els-f280049c/device_support_f28004x/common/include/F28x_Project.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/device.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/driverlib.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_examples.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_adc.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_dma.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_spi.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c delete mode 100644 els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm delete mode 100644 els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_can.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_device.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h delete mode 100644 els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h delete mode 100644 els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c diff --git a/els-f280049c/.cproject b/els-f280049c/.cproject index bbf0e3c..5116c05 100644 --- a/els-f280049c/.cproject +++ b/els-f280049c/.cproject @@ -3,6 +3,10 @@ + + + + @@ -15,69 +19,91 @@ - - + + + + + + + + @@ -87,6 +113,10 @@ + + + + @@ -99,73 +129,102 @@ - - + + + + + + + + + @@ -178,6 +237,15 @@ - + + + + + + + + + + diff --git a/els-f280049c/.project b/els-f280049c/.project index e8c34c3..b97c5a1 100644 --- a/els-f280049c/.project +++ b/els-f280049c/.project @@ -24,4 +24,67 @@ org.eclipse.cdt.core.ccnature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + driverlib.lib + 1 + $%7BC2000WARE_DLIB_ROOT%7D/ccs/Release/driverlib.lib + + + device/f28004x_codestartbranch.asm + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_codestartbranch.asm + + + device/f28004x_cputimers.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_cputimers.c + + + device/f28004x_defaultisr.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_defaultisr.c + + + device/f28004x_globalvariabledefs.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/headers/source/f28004x_globalvariabledefs.c + + + device/f28004x_headers_nonbios.cmd + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/headers/cmd/f28004x_headers_nonbios.cmd + + + device/f28004x_piectrl.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_piectrl.c + + + device/f28004x_pievect.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_pievect.c + + + device/f28004x_spi.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_spi.c + + + device/f28004x_sysctrl.c + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_sysctrl.c + + + device/f28004x_usdelay.asm + 1 + PARENT-3-C2000WARE_DLIB_ROOT/device_support/f28004x/common/source/f28004x_usdelay.asm + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR%7D/driverlib/f28004x/driverlib + + diff --git a/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs b/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs index 98b6350..b4a10b6 100644 --- a/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs +++ b/els-f280049c/.settings/org.eclipse.cdt.codan.core.prefs @@ -1,3 +1,103 @@ eclipse.preferences.version=1 inEditor=false onBuild=false +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=-Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")"} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/els-f280049c/.settings/org.eclipse.core.resources.prefs b/els-f280049c/.settings/org.eclipse.core.resources.prefs index 8e309e6..bb9eacc 100644 --- a/els-f280049c/.settings/org.eclipse.core.resources.prefs +++ b/els-f280049c/.settings/org.eclipse.core.resources.prefs @@ -1,21 +1,15 @@ eclipse.preferences.version=1 -encoding//Debug/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Debug/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 +encoding//Debug/device/subdir_rules.mk=UTF-8 +encoding//Debug/device/subdir_vars.mk=UTF-8 encoding//Debug/makefile=UTF-8 encoding//Debug/objects.mk=UTF-8 encoding//Debug/sources.mk=UTF-8 encoding//Debug/subdir_rules.mk=UTF-8 encoding//Debug/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/common/source/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/common/source/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8 -encoding//Release/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8 +encoding//Release/device/source/subdir_rules.mk=UTF-8 +encoding//Release/device/source/subdir_vars.mk=UTF-8 +encoding//Release/device/subdir_rules.mk=UTF-8 +encoding//Release/device/subdir_vars.mk=UTF-8 encoding//Release/makefile=UTF-8 encoding//Release/objects.mk=UTF-8 encoding//Release/sources.mk=UTF-8 diff --git a/els-f280049c/28004x_generic_flash_lnk.cmd b/els-f280049c/28004x_generic_flash_lnk.cmd index aa33b0e..ae52fda 100644 --- a/els-f280049c/28004x_generic_flash_lnk.cmd +++ b/els-f280049c/28004x_generic_flash_lnk.cmd @@ -23,14 +23,13 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. - MEMORY { PAGE 0 : /* BEGIN is used for the "boot to Flash" bootloader mode */ BEGIN : origin = 0x080000, length = 0x000002 - RAMM0 : origin = 0x0000F5, length = 0x00030B + RAMM0 : origin = 0x0000F3, length = 0x00030D RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 @@ -74,12 +73,15 @@ PAGE 0 : FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */ - FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */ + FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */ + +// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ PAGE 1 : - BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 @@ -88,28 +90,53 @@ PAGE 1 : RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 - RAMGS3 : origin = 0x012000, length = 0x002000 + RAMGS3 : origin = 0x012000, length = 0x001FF8 +// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } SECTIONS { codestart : > BEGIN, PAGE = 0, ALIGN(4) - .text : >>FLASH_BANK0_SEC1 | FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3, PAGE = 0, ALIGN(4) + .text : >>FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5, PAGE = 0, ALIGN(4) .cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) - .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ - .cio : > RAMLS0, PAGE = 0 .stack : > RAMM1, PAGE = 1 - .ebss : > RAMLS5, PAGE = 1 - .esysmem : > RAMLS5, PAGE = 1 - .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4) + +#if defined(__TI_EABI__) + .init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS0, PAGE = 0 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : >>FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7, PAGE = 0, ALIGN(4) +#else + .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) + .ebss : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS0, PAGE = 0 + .econst : >>FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7, PAGE = 0, ALIGN(4) +#endif ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 + +#if defined(__TI_EABI__) + .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(4) +#else .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, LOAD_START(_RamfuncsLoadStart), @@ -119,6 +146,12 @@ SECTIONS RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0, ALIGN(4) +#endif } +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/els-f280049c/28004x_generic_ram_lnk.cmd b/els-f280049c/28004x_generic_ram_lnk.cmd index 5fd166d..bbe5d30 100644 --- a/els-f280049c/28004x_generic_ram_lnk.cmd +++ b/els-f280049c/28004x_generic_ram_lnk.cmd @@ -23,14 +23,13 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. - MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 - RAMM0 : origin = 0x0000F5, length = 0x00030B + RAMM0 : origin = 0x0000F3, length = 0x00030D RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 @@ -78,8 +77,9 @@ PAGE 0 : PAGE 1 : - BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 @@ -88,27 +88,44 @@ PAGE 1 : RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 - RAMGS3 : origin = 0x012000, length = 0x002000 + RAMGS3 : origin = 0x012000, length = 0x001FF8 +// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } /*You can arrange the .text, .cinit, .const, .pinit, .switch and .econst to FLASH when RAM is filled up.*/ SECTIONS { codestart : > BEGIN, PAGE = 0 - .TI.ramfunc : > RAMM0 PAGE = 0 - .text : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .TI.ramfunc : > RAMM0, PAGE = 0 + .text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 .cinit : > RAMM0, PAGE = 0 - .pinit : > RAMM0, PAGE = 0 .switch : > RAMM0, PAGE = 0 - .cio : > RAMLS0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .stack : > RAMM1, PAGE = 1 - .ebss : > RAMLS5|RAMLS6, PAGE = 1 - .econst : > RAMLS5|RAMLS6, PAGE = 1 - .esysmem : > RAMLS5|RAMLS6, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS5, PAGE = 1 + .init_array : > RAMM0, PAGE = 0 + .const : >> RAMLS6|RAMLS7, PAGE = 1, ALIGN(4) + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + .bss:cio : > RAMLS0, PAGE = 0 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : >> RAMLS6|RAMLS7, PAGE = 1, ALIGN(4) + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS0, PAGE = 0 +#endif ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 } +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/els-f280049c/device_support_f28004x/common/include/F28x_Project.h b/els-f280049c/device_support_f28004x/common/include/F28x_Project.h deleted file mode 100644 index daebcc0..0000000 --- a/els-f280049c/device_support_f28004x/common/include/F28x_Project.h +++ /dev/null @@ -1,51 +0,0 @@ -//############################################################################# -// -// FILE: F28x_Project.h -// -// TITLE: F28x Project Headerfile and Examples Include File -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F28X_PROJECT_H -#define F28X_PROJECT_H - -#include "f28004x_cla_typedefs.h" // f28004x CLA Type definitions -#include "f28004x_device.h" // f28004x Headerfile Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -#endif // end of F28X_PROJECT_H definition - diff --git a/els-f280049c/device_support_f28004x/common/include/device.h b/els-f280049c/device_support_f28004x/common/include/device.h deleted file mode 100644 index 26690ad..0000000 --- a/els-f280049c/device_support_f28004x/common/include/device.h +++ /dev/null @@ -1,307 +0,0 @@ -//############################################################################# -// -// FILE: device.h -// -// TITLE: Device setup for examples. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef __DEVICE_H__ -#define __DEVICE_H__ - -// -// Included Files -// -#include "driverlib.h" - -//***************************************************************************** -// -// Defines for pin numbers and other GPIO configuration -// -//***************************************************************************** -#ifdef _LAUNCHXL_F280049C -// -// LaunchPad -// - -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 34U // GPIO number for LD4 -#define DEVICE_GPIO_PIN_LED2 23U // GPIO number for LD5 -#define DEVICE_GPIO_CFG_LED1 GPIO_34_GPIO34 // "pinConfig" for LD4 -#define DEVICE_GPIO_CFG_LED2 GPIO_23_GPIO23 // "pinConfig" for LD5 - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 32U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 33U // GPIO number for CANRXA -#define DEVICE_GPIO_CFG_CANRXA GPIO_33_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_32_CANTXA // "pinConfig" for CANA TX - -// -// LINA -// -#define DEVICE_GPIO_CFG_LINTXA GPIO_37_LINTXA // "pinConfig" for LINA TX -#define DEVICE_GPIO_CFG_LINRXA GPIO_35_LINRXA // "pinConfig" for LINA RX - -// -// FSI -// -#define DEVICE_GPIO_PIN_FSI_RXCLK 33U // GPIO number for FSI RXCLK -#define DEVICE_GPIO_CFG_FSI_RXCLK GPIO_33_FSI_RXCLK // "pinConfig" for FSI RXCLK - -// -// SPI -// -#define DEVICE_GPIO_PIN_SPICLKA 56U // GPIO number for SPI CLKA -#define DEVICE_GPIO_PIN_SPISIMOA 16U // GPIO number for SPI SIMOA -#define DEVICE_GPIO_PIN_SPISOMIA 17U // GPIO number for SPI SOMIA -#define DEVICE_GPIO_PIN_SPISTEA 57U // GPIO number for SPI STEA -#define DEVICE_GPIO_CFG_SPICLKA GPIO_56_SPICLKA // "pinConfig" for SPI CLKA -#define DEVICE_GPIO_CFG_SPISIMOA GPIO_16_SPISIMOA // "pinConfig" for SPI SIMOA -#define DEVICE_GPIO_CFG_SPISOMIA GPIO_17_SPISOMIA // "pinConfig" for SPI SOMIA -#define DEVICE_GPIO_CFG_SPISTEA GPIO_57_SPISTEA // "pinConfig" for SPI STEA -#define DEVICE_GPIO_PIN_SPICLKB 26U // GPIO number for SPI CLKB -#define DEVICE_GPIO_PIN_SPISIMOB 24U // GPIO number for SPI SIMOB -#define DEVICE_GPIO_PIN_SPISOMIB 31U // GPIO number for SPI SOMIB -#define DEVICE_GPIO_PIN_SPISTEB 27U // GPIO number for SPI STEB -#define DEVICE_GPIO_CFG_SPICLKB GPIO_26_SPICLKB // "pinConfig" for SPI CLKB -#define DEVICE_GPIO_CFG_SPISIMOB GPIO_24_SPISIMOB // "pinConfig" for SPI SIMOB -#define DEVICE_GPIO_CFG_SPISOMIB GPIO_31_SPISOMIB // "pinConfig" for SPI SOMIB -#define DEVICE_GPIO_CFG_SPISTEB GPIO_27_SPISTEB // "pinConfig" for SPI STEB - -// -// I2C -// -#define DEVICE_GPIO_PIN_SDAA 35U // GPIO number for I2C SDAA -#define DEVICE_GPIO_PIN_SCLA 37U // GPIO number for I2C SCLA -#define DEVICE_GPIO_CFG_SDAA GPIO_35_SDAA // "pinConfig" for I2C SDAA -#define DEVICE_GPIO_CFG_SCLA GPIO_37_SCLA // "pinConfig" for I2C SCLA - -// -// eQEP -// -#define DEVICE_GPIO_PIN_EQEP1A 35U // GPIO number for EQEP 1A -#define DEVICE_GPIO_PIN_EQEP1B 37U // GPIO number for EQEP 1B -#define DEVICE_GPIO_PIN_EQEP1I 59U // GPIO number for EQEP 1I -#define DEVICE_GPIO_CFG_EQEP1A GPIO_35_EQEP1A // "pinConfig" for EQEP 1A -#define DEVICE_GPIO_CFG_EQEP1B GPIO_37_EQEP1B // "pinConfig" for EQEP 1B -#define DEVICE_GPIO_CFG_EQEP1I GPIO_59_EQEP1I // "pinConfig" for EQEP 1I - -// -// EPWM -// -#define DEVICE_PERIPHERAL_BASE_EPWM EPWM6_BASE // Base peripheral EPWM 6 -#define DEVICE_PERIPHERAL_INT_EPWM INT_EPWM6 // Base peripheral EPWM 6 interrupt -#define DEVICE_GPIO_PIN_EPWMxA 10U // GPIO number for EPWM6A -#define DEVICE_GPIO_PIN_EPWMxB 11U // GPIO number for EPWM6B -#define DEVICE_GPIO_PIN_IOINDEX 8U // GPIO number for IO Index -#define DEVICE_GPIO_CFG_EPWMxA GPIO_10_EPWM6A // "pinConfig" for EPWM6A -#define DEVICE_GPIO_CFG_EPWMxB GPIO_11_EPWM6B // "pinConfig" for EPWM6B -#define DEVICE_GPIO_CFG_IOINDEX GPIO_8_GPIO8 // "pinConfig" for IO Index - -#else -// -// ControlCARD -// - -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 -#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 -#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 -#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA - -// -// CAN External Loopback -// -#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX -#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX -#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX - -// -// LINA -// -#define DEVICE_GPIO_CFG_LINTXA GPIO_46_LINTXA // "pinConfig" for LINA TX -#define DEVICE_GPIO_CFG_LINRXA GPIO_47_LINRXA // "pinConfig" for LINA RX - -// -// FSI -// -#define DEVICE_GPIO_PIN_FSI_RXCLK 13U // GPIO number for FSI RXCLK -#define DEVICE_GPIO_CFG_FSI_RXCLK GPIO_13_FSI_RXCLK // "pinConfig" for FSI RXCLK - -// -// SPI -// -#define DEVICE_GPIO_PIN_SPICLKA 9U // GPIO number for SPI CLKA -#define DEVICE_GPIO_PIN_SPISIMOA 8U // GPIO number for SPI SIMOA -#define DEVICE_GPIO_PIN_SPISOMIA 10U // GPIO number for SPI SOMIA -#define DEVICE_GPIO_PIN_SPISTEA 11U // GPIO number for SPI STEA -#define DEVICE_GPIO_CFG_SPICLKA GPIO_9_SPICLKA // "pinConfig" for SPI CLKA -#define DEVICE_GPIO_CFG_SPISIMOA GPIO_8_SPISIMOA // "pinConfig" for SPI SIMOA -#define DEVICE_GPIO_CFG_SPISOMIA GPIO_10_SPISOMIA // "pinConfig" for SPI SOMIA -#define DEVICE_GPIO_CFG_SPISTEA GPIO_11_SPISTEA // "pinConfig" for SPI STEA -#define DEVICE_GPIO_PIN_SPICLKB 26U // GPIO number for SPI CLKB -#define DEVICE_GPIO_PIN_SPISIMOB 24U // GPIO number for SPI SIMOB -#define DEVICE_GPIO_PIN_SPISOMIB 25U // GPIO number for SPI SOMIB -#define DEVICE_GPIO_PIN_SPISTEB 27U // GPIO number for SPI STEB -#define DEVICE_GPIO_CFG_SPICLKB GPIO_26_SPICLKB // "pinConfig" for SPI CLKB -#define DEVICE_GPIO_CFG_SPISIMOB GPIO_24_SPISIMOB // "pinConfig" for SPI SIMOB -#define DEVICE_GPIO_CFG_SPISOMIB GPIO_25_SPISOMIB // "pinConfig" for SPI SOMIB -#define DEVICE_GPIO_CFG_SPISTEB GPIO_27_SPISTEB // "pinConfig" for SPI STEB - -// -// I2C -// -#define DEVICE_GPIO_PIN_SDAA 32U // GPIO number for I2C SDAA -#define DEVICE_GPIO_PIN_SCLA 33U // GPIO number for I2C SCLA -#define DEVICE_GPIO_CFG_SDAA GPIO_32_SDAA // "pinConfig" for I2C SDAA -#define DEVICE_GPIO_CFG_SCLA GPIO_33_SCLA // "pinConfig" for I2C SCLA - -// -// eQEP -// -#define DEVICE_GPIO_PIN_EQEP1A 6U // GPIO number for EQEP 1A -#define DEVICE_GPIO_PIN_EQEP1B 7U // GPIO number for EQEP 1B -#define DEVICE_GPIO_PIN_EQEP1I 9U // GPIO number for EQEP 1I -#define DEVICE_GPIO_CFG_EQEP1A GPIO_6_EQEP1A // "pinConfig" for EQEP 1A -#define DEVICE_GPIO_CFG_EQEP1B GPIO_7_EQEP1B // "pinConfig" for EQEP 1B -#define DEVICE_GPIO_CFG_EQEP1I GPIO_9_EQEP1I // "pinConfig" for EQEP 1I - -// -// EPWM -// -#define DEVICE_PERIPHERAL_BASE_EPWM EPWM1_BASE // Base peripheral EPWM 1 -#define DEVICE_PERIPHERAL_INT_EPWM INT_EPWM1 // Base peripheral EPWM 1 interrupt -#define DEVICE_GPIO_PIN_EPWMxA 0U // GPIO number for EPWM1A -#define DEVICE_GPIO_PIN_EPWMxB 1U // GPIO number for EPWM1B -#define DEVICE_GPIO_PIN_IOINDEX 2U // GPIO number for IO Index -#define DEVICE_GPIO_CFG_EPWMxA GPIO_0_EPWM1A // "pinConfig" for EPWM1A -#define DEVICE_GPIO_CFG_EPWMxB GPIO_1_EPWM1B // "pinConfig" for EPWM1B -#define DEVICE_GPIO_CFG_IOINDEX GPIO_2_GPIO2 // "pinConfig" for IO Index - -#endif - -// -// SCI for USB-to-UART adapter on FTDI chip -// -#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX -#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX -#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX -#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX - -//***************************************************************************** -// -// Defines related to clock configuration -// -//***************************************************************************** -// -// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). -// -#define DEVICE_OSCSRC_FREQ 20000000U - -// -// Define to pass to SysCtl_setClock(). Will configure the clock as follows: -// PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) -// -#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) | \ - SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ - SYSCTL_PLL_ENABLE) - -// -// 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the -// code below if a different clock configuration is used! -// -#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 10 * 1) / 2) - -// -// 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default -// low speed peripheral clock divider of 4. Update the code below if a -// different LSPCLK divider is used! -// -#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) - -//***************************************************************************** -// -// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro -// will convert the desired delay in microseconds to the count value expected -// by the function. \b x is the number of microseconds to delay. -// -//***************************************************************************** -#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ - (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) - -//***************************************************************************** -// -// Defines, Globals, and Header Includes related to Flash Support -// -//***************************************************************************** -#ifdef _FLASH -#include - -extern uint16_t RamfuncsLoadStart; -extern uint16_t RamfuncsLoadEnd; -extern uint16_t RamfuncsLoadSize; -extern uint16_t RamfuncsRunStart; -extern uint16_t RamfuncsRunEnd; -extern uint16_t RamfuncsRunSize; -#endif - -#define DEVICE_FLASH_WAITSTATES 4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void Device_init(void); -extern void Device_enableAllPeripherals(void); -extern void Device_initGPIO(void); -extern void __error__(char *filename, uint32_t line); - -#endif // __DEVICE_H__ diff --git a/els-f280049c/device_support_f28004x/common/include/driverlib.h b/els-f280049c/device_support_f28004x/common/include/driverlib.h deleted file mode 100644 index 54b5ba6..0000000 --- a/els-f280049c/device_support_f28004x/common/include/driverlib.h +++ /dev/null @@ -1,82 +0,0 @@ -//############################################################################# -// -// FILE: driverlib.h -// -// TITLE: C28x Driverlib Header File -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef DRIVERLIB_H -#define DRIVERLIB_H - -#include "inc/hw_memmap.h" - -#include "adc.h" -#include "asysctl.h" -#include "can.h" -#include "cla.h" -#include "clapromcrc.h" -#include "cmpss.h" -#include "cpu.h" -#include "cputimer.h" -#include "dac.h" -#include "dcc.h" -#include "dcsm.h" -#include "debug.h" -#include "dma.h" -#include "ecap.h" -#include "epwm.h" -#include "eqep.h" -#include "flash.h" -#include "fsi.h" -#include "gpio.h" -#include "hrcap.h" -#include "hrpwm.h" -#include "i2c.h" -#include "interrupt.h" -#include "lin.h" -#include "memcfg.h" -#include "pga.h" -#include "pin_map.h" -#include "pmbus.h" -#include "sci.h" -#include "sdfm.h" -#include "spi.h" -#include "sysctl.h" -#include "version.h" -#include "xbar.h" - -#endif // end of DRIVERLIB_H definition diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h deleted file mode 100644 index 4565488..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_adc_defines.h +++ /dev/null @@ -1,83 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc_defines.h -// -// TITLE: #defines used in ADC examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_ADC_DEFINES_H -#define F28004X_ADC_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// Definitions for specifying an ADC -// -#define ADC_ADCA 0 -#define ADC_ADCB 1 -#define ADC_ADCC 2 -#define ADC_ADCD 3 - -// -// Definitions for specifying reference mode -// -#define ADC_INTERNAL 0 -#define ADC_EXTERNAL 1 - -// -// Definitions for specifying reference voltage -// -#define ADC_VREF3P3 0 -#define ADC_VREF2P5 1 - - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h deleted file mode 100644 index 9b89799..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_defines.h +++ /dev/null @@ -1,199 +0,0 @@ -//############################################################################# -// -// FILE: f28004x_cla_defines.h -// -// TITLE: #defines used in CLA examples -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef F28004X_CLA_DEFINES_H_ -#define F28004X_CLA_DEFINES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// MCTL Register -// -#define CLA_FORCE_RESET 0x1 -#define CLA_IACK_ENABLE 0x1 -#define CLA_IACK_DISABLE 0x0 - -// -// MMEMCFG Register -// -#define CLA_CLA_SPACE 0x1 -#define CLA_CPU_SPACE 0x0 - -// -// MIER Interrupt Enable Register -// -#define CLA_INT_ENABLE 0x1 -#define CLA_INT_DISABLE 0x0 - -// -// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register -// -#define CLA_TRIG_NOPERPH 0 -#define CLA_TRIG_ADCAINT1 1 -#define CLA_TRIG_ADCAINT2 2 -#define CLA_TRIG_ADCAINT3 3 -#define CLA_TRIG_ADCAINT4 4 -#define CLA_TRIG_ADCAEVT 5 -#define CLA_TRIG_ADCBINT1 6 -#define CLA_TRIG_ADCBINT2 7 -#define CLA_TRIG_ADCBINT3 8 -#define CLA_TRIG_ADCBINT4 9 -#define CLA_TRIG_ADCBEVT 10 -#define CLA_TRIG_ADCCINT1 11 -#define CLA_TRIG_ADCCINT2 12 -#define CLA_TRIG_ADCCINT3 13 -#define CLA_TRIG_ADCCINT4 14 -#define CLA_TRIG_ADCCEVT 15 - -#define CLA_TRIG_XINT1 29 -#define CLA_TRIG_XINT2 30 -#define CLA_TRIG_XINT3 31 -#define CLA_TRIG_XINT4 32 -#define CLA_TRIG_XINT5 33 - -#define CLA_TRIG_EPWM1INT 36 -#define CLA_TRIG_EPWM2INT 37 -#define CLA_TRIG_EPWM3INT 38 -#define CLA_TRIG_EPWM4INT 39 -#define CLA_TRIG_EPWM5INT 40 -#define CLA_TRIG_EPWM6INT 41 -#define CLA_TRIG_EPWM7INT 42 -#define CLA_TRIG_EPWM8INT 43 - -#define CLA_TRIG_TINT0 68 -#define CLA_TRIG_TINT1 69 -#define CLA_TRIG_TINT2 70 - -#define CLA_TRIG_ECAP1INT 75 -#define CLA_TRIG_ECAP2INT 76 -#define CLA_TRIG_ECAP3INT 77 -#define CLA_TRIG_ECAP4INT 78 -#define CLA_TRIG_ECAP5INT 79 -#define CLA_TRIG_ECAP6INT 80 -#define CLA_TRIG_ECAP7INT 81 - -#define CLA_TRIG_EQEP1INT 83 -#define CLA_TRIG_EQEP2INT 84 - -#define CLA_TRIG_ECAP6INT2 92 -#define CLA_TRIG_ECAP7INT2 93 - -#define CLA_TRIG_SD1INT 95 -#define CLA_TRIG_SD1DRINT1 96 -#define CLA_TRIG_SD1DRINT2 97 -#define CLA_TRIG_SD1DRINT3 98 -#define CLA_TRIG_SD1DRINT4 99 - -#define CLA_TRIG_PMBUSAINT 105 - -#define CLA_TRIG_SPITXINTA 109 -#define CLA_TRIG_SPIRXINTA 110 -#define CLA_TRIG_SPITXINTB 111 -#define CLA_TRIG_SPIRXINTB 112 - -#define CLA_TRIG_LINA_INT1 117 -#define CLA_TRIG_LINA_INT0 118 - -#define CLA_TRIG_CLA1PROMCRC 121 - -#define CLA_TRIG_FSITXINT1 123 -#define CLA_TRIG_FSITXINT2 124 -#define CLA_TRIG_FSIRXINT1 125 -#define CLA_TRIG_FSIRXINT2 126 -#define CLA_TRIG_CLB1INT 127 -#define CLA_TRIG_CLB2INT 128 -#define CLA_TRIG_CLB3INT 129 -#define CLA_TRIG_CLB4INT 130 - -#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT1 == 1); - -#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT2 == 1); - -#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT3 == 1); - -#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT4 == 1); - -#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT5 == 1); - -#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT6 == 1); - -#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT7 == 1); - -#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT8 == 1); - -#define Cla1ForceTask1() asm(" IACK #0x0001") -#define Cla1ForceTask2() asm(" IACK #0x0002") -#define Cla1ForceTask3() asm(" IACK #0x0004") -#define Cla1ForceTask4() asm(" IACK #0x0008") -#define Cla1ForceTask5() asm(" IACK #0x0010") -#define Cla1ForceTask6() asm(" IACK #0x0020") -#define Cla1ForceTask7() asm(" IACK #0x0040") -#define Cla1ForceTask8() asm(" IACK #0x0080") - -#ifdef __cplusplus -} -#endif - - - -#endif /* F2004X_CLA_DEFINES_H_ */ diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h deleted file mode 100644 index ce918c1..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cla_typedefs.h +++ /dev/null @@ -1,128 +0,0 @@ - //########################################################################### -// -// FILE: f28004x_cla_typedefs.h -// -// TITLE: Variable type definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - - -#ifndef F28004x_CLA_TYPEDEFS_H_ -#define F28004x_CLA_TYPEDEFS_H_ - -// -// Macros to manipulate pre-processor to generate a header file name -// at compile time that is based on the test name and can be used as -// an argument to #include -// -#define XSTRINGIZE(s) STRINGIZE(s) -#define STRINGIZE(s) #s -#define XCONCAT(x,y) CONCAT(x,y) -#define CONCAT(x,y) x##y - -// -// Suppress warnings casting CLA pointers -// -#pragma diag_suppress 70,770,232 - -#ifdef __TMS320C28XX_CLA__ -// -// For Portability, User Is Recommended To Use Following Data Type Size -// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: -// -// CLA does not support 64-bit types -// This definition is only to allow inclusion of the standard header files -// which do use 64-bit types -// - -#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) -#define F28_DATA_TYPES -#define DSP28_DATA_TYPES -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else -#error f28004x_Cla_Typedefs.h must be included before f28004x_Device.h or any other header \ -file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES -#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) - -#ifndef _TI_STD_TYPES -#define _TI_STD_TYPES -// -// These types are also defined in DSP/BIOS 5.x's and the -// SYS/BIOS 6.x's files. We need to protect their -// definition with the #ifndef/#define guard to avoid the duplicate -// definition warning. -// -// SYS/BIOS requires that the file be included before -// any other .h files. -// -#endif - -// -// MSTF bit description -// -struct MSTF_SHADOW_BITS { - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Rounding Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint16 RPCL:4; // 15:12 Return PC: Low Portion - Uint16 RPCH:8; // 23:16 Return PC: High Portion - Uint16 rsvd4:8; // 31:24 Reserved -}; -extern __cregister volatile unsigned int MSTF; - -#endif - -#ifndef __TMS320C28XX__ -#define __cregister -#endif - -#endif /*f28004x_CLA_TYPEDEFS_H_*/ diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h b/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h deleted file mode 100644 index 2b92a3f..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_cputimervars.h +++ /dev/null @@ -1,143 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimervars.h -// -// TITLE: f28004x Device CPUTIMERS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_CPUTIMERVARS_H -#define F28004x_CPUTIMERVARS_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Cputimers External References & Function Declarations -// - -// -// CPU Timer Support Variables: -// -struct CPUTIMER_VARS { - volatile struct CPUTIMER_REGS *RegsAddr; - Uint32 InterruptCount; - float CPUFreqInMHz; - float PeriodInUSec; -}; - -// -// Function prototypes and external definitions: -// -void InitCpuTimers(void); -void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); - -extern struct CPUTIMER_VARS CpuTimer0; -extern struct CPUTIMER_VARS CpuTimer1; -extern struct CPUTIMER_VARS CpuTimer2; - -// -// Useful Timer Operations -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of f28004x_CPUTIMERVARS_H definition - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h b/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h deleted file mode 100644 index ddfb733..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_defaultisr.h +++ /dev/null @@ -1,202 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_defaultisr.h -// -// TITLE: f28004x Device Default Interrupt Service Routines Definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_DEFAULT_ISR_H -#define F28004x_DEFAULT_ISR_H -#ifdef __cplusplus -extern "C" { -#endif - -// -// Default Interrupt Service Routine Declarations: -// The following function prototypes are for the -// default ISR routines used with the default PIE vector table. -// This default vector table is found in the f28004x_pievect.h -// file. -// -interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt -interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt -interrupt void DATALOG_ISR(void); // Datalogging Interrupt -interrupt void RTOS_ISR(void); // RTOS Interrupt -interrupt void EMU_ISR(void); // Emulation Interrupt -interrupt void NMI_ISR(void); // Non-Maskable Interrupt -interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap -interrupt void USER1_ISR(void); // User Defined Trap 1 -interrupt void USER2_ISR(void); // User Defined Trap 2 -interrupt void USER3_ISR(void); // User Defined Trap 3 -interrupt void USER4_ISR(void); // User Defined Trap 4 -interrupt void USER5_ISR(void); // User Defined Trap 5 -interrupt void USER6_ISR(void); // User Defined Trap 6 -interrupt void USER7_ISR(void); // User Defined Trap 7 -interrupt void USER8_ISR(void); // User Defined Trap 8 -interrupt void USER9_ISR(void); // User Defined Trap 9 -interrupt void USER10_ISR(void); // User Defined Trap 10 -interrupt void USER11_ISR(void); // User Defined Trap 11 -interrupt void USER12_ISR(void); // User Defined Trap 12 -interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 -interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 -interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 -interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt -interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt -interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt -interrupt void WAKE_ISR(void); // 1.8 - Halt Wakeup Interrupt -interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt -interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt -interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt -interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt -interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt -interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt -interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt -interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt -interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt -interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt -interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt -interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt -interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt -interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt -interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt -interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt -interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt -interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt -interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt -interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt -interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt -interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt -interrupt void ECAP7_ISR(void); // 4.7 - eCAP7 Interrupt -interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt -interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt -interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt -interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt -interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt -interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt -interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt -interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt -interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt -interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt -interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt -interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt -interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 -interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 -interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt -interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt -interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt -interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt -interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 -interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 -interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 -interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 -interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt -interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 -interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 -interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 -interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt -interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 -interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 -interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 -interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 -interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 -interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 -interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 -interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 -interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 -interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 -interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 -interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt -interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt -interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt -interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt -interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt -interrupt void ECAP6_2_ISR(void); // 4.14 - eCAP6 HR Calibration Interrupt -interrupt void ECAP7_2_ISR(void); // 4.15 - eCAP6 HR Calibration Interrupt -interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt -interrupt void SD1DR1_ISR(void); // 5.13 - SDFM1 DR Interrupt 1 -interrupt void SD1DR2_ISR(void); // 5.14 - SDFM1 DR Interrupt 2 -interrupt void SD1DR3_ISR(void); // 5.15 - SDFM1 DR Interrupt 3 -interrupt void SD1DR4_ISR(void); // 5.16 - SDFM1 DR Interrupt 4 -interrupt void FSITXA1_ISR(void); // 7.11 - FSITXA1 Interrupt -interrupt void FSITXA2_ISR(void); // 7.12 - FSITXA2 Interrupt -interrupt void FSIRXA1_ISR(void); // 7.13 - FSIRXA1 Interrupt -interrupt void FSIRXA2_ISR(void); // 7.14 - FSIRXA2 Interrupt -interrupt void CLA1PROMCRC_ISR(void); // 7.15 - CLAP1ROMCRC Interrupt -interrupt void LINA_0_ISR(void); // 8.9 - LINA Interrupt 0 -interrupt void LINA_1_ISR(void); // 8.10 - LINA Interrupt 1 -interrupt void PMBUSA_ISR(void); // 8.13 - PMBUSA Interrupt -interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt -interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 -interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 -interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 -// -// 12.10 - RAM Correctable Error Interrupt -// -interrupt void RAM_CORRECTABLE_ERROR_ISR(void); - -// -// 12.11 - Flash Correctable Error Interrupt -// -interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); - -// -// 12.12 - RAM Access Violation Interrupt -// -interrupt void RAM_ACCESS_VIOLATION_ISR(void); - -interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip Interrupt -interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow Interrupt -interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow Interrupt - -// -// Catch-all for PIE Reserved Locations for testing purposes: -// -interrupt void PIE_RESERVED_ISR(void); // Reserved ISR -interrupt void EMPTY_ISR(void); // Only does a return -interrupt void NOTUSED_ISR(void); // Unused ISR -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F28004x_PIEVECT_H definition -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h deleted file mode 100644 index 75dc6fb..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_dma_defines.h +++ /dev/null @@ -1,193 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma_defines.h -// -// TITLE: #defines used in DMA examples -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F28004X_DMA_DEFINES_H_ -#define F28004X_DMA_DEFINES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// PERINTSEL bits -// -#define DMA_ADCAINT1 1 -#define DMA_ADCAINT2 2 -#define DMA_ADCAINT3 3 -#define DMA_ADCAINT4 4 -#define DMA_ADCAEVT 5 -#define DMA_ADCBINT1 6 -#define DMA_ADCBINT2 7 -#define DMA_ADCBINT3 8 -#define DMA_ADCBINT4 9 -#define DMA_ADCBEVT 10 -#define DMA_ADCCINT1 11 -#define DMA_ADCCINT2 12 -#define DMA_ADCCINT3 13 -#define DMA_ADCCINT4 14 -#define DMA_ADCCEVT 15 - -#define DMA_XINT1 29 -#define DMA_XINT2 30 -#define DMA_XINT3 31 -#define DMA_XINT4 32 -#define DMA_XINT5 33 - -#define DMA_EPWM1A 36 -#define DMA_EPWM1B 37 -#define DMA_EPWM2A 38 -#define DMA_EPWM2B 39 -#define DMA_EPWM3A 40 -#define DMA_EPWM3B 41 -#define DMA_EPWM4A 42 -#define DMA_EPWM4B 43 -#define DMA_EPWM5A 44 -#define DMA_EPWM5B 45 -#define DMA_EPWM6A 46 -#define DMA_EPWM6B 47 -#define DMA_EPWM7A 48 -#define DMA_EPWM7B 49 -#define DMA_EPWM8A 50 -#define DMA_EPWM8B 51 - -#define DMA_TINT0 68 -#define DMA_TINT1 69 -#define DMA_TINT2 70 - -#define DMA_ECAP1 75 -#define DMA_ECAP2 76 -#define DMA_ECAP3 77 -#define DMA_ECAP4 78 -#define DMA_ECAP5 79 -#define DMA_ECAP6 80 -#define DMA_ECAP7 81 - -#define DMA_SD1FLT1 96 -#define DMA_SD1FLT2 97 -#define DMA_SD1FLT3 98 -#define DMA_SD1FLT4 99 - -#define DMA_SPIATX 109 -#define DMA_SPIARX 110 -#define DMA_SPIBTX 111 -#define DMA_SPIBRX 112 - -#define DMA_LINATX 117 -#define DMA_LINARX 118 - -#define DMA_FSITXA 123 - -#define DMA_FSIRXA 125 - -#define DMA_CANAIF1 167 -#define DMA_CANAIF2 168 -#define DMA_CANAIF3 169 -#define DMA_CANBIF1 170 -#define DMA_CANBIF2 171 -#define DMA_CANBIF3 172 - -// -// OVERINTE bit -// -#define OVRFLOW_DISABLE 0x0 -#define OVEFLOW_ENABLE 0x1 - -// -// PERINTE bit -// -#define PERINT_DISABLE 0x0 -#define PERINT_ENABLE 0x1 - -// -// CHINTMODE bits -// -#define CHINT_BEGIN 0x0 -#define CHINT_END 0x1 - -// -// ONESHOT bits -// -#define ONESHOT_DISABLE 0x0 -#define ONESHOT_ENABLE 0x1 - -// -// CONTINOUS bit -// -#define CONT_DISABLE 0x0 -#define CONT_ENABLE 0x1 - -// -// SYNCE bit -// -#define SYNC_DISABLE 0x0 -#define SYNC_ENABLE 0x1 - -// -// SYNCSEL bit -// -#define SYNC_SRC 0x0 -#define SYNC_DST 0x1 - -// -// DATASIZE bit -// -#define SIXTEEN_BIT 0x0 -#define THIRTYTWO_BIT 0x1 - -// -// CHINTE bit -// -#define CHINT_DISABLE 0x0 -#define CHINT_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif - -#endif /*end of F28004X_DMA_DEFINES_H_ */ -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h deleted file mode 100644 index 2d4595f..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_epwm_defines.h +++ /dev/null @@ -1,342 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm_defines.h -// -// TITLE: f28004x Device EPWM Register Bit Defines -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_EPWM_DEFINES_H -#define F28004x_EPWM_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// TBCTL (Time-Base Control) -// - -// -// CTRMODE bits -// -#define TB_COUNT_UP 0x0 -#define TB_COUNT_DOWN 0x1 -#define TB_COUNT_UPDOWN 0x2 -#define TB_FREEZE 0x3 - -// -// PHSEN bit -// -#define TB_DISABLE 0x0 -#define TB_ENABLE 0x1 - -// -// PRDLD bit -// -#define TB_SHADOW 0x0 -#define TB_IMMEDIATE 0x1 - -// -// SYNCOSEL bits -// -#define TB_SYNC_IN 0x0 -#define TB_CTR_ZERO 0x1 -#define TB_CTR_CMPB 0x2 -#define TB_SYNC_DISABLE 0x3 - -// -// HSPCLKDIV and CLKDIV bits -// -#define TB_DIV1 0x0 -#define TB_DIV2 0x1 -#define TB_DIV4 0x2 - -// -// PHSDIR bit -// -#define TB_DOWN 0x0 -#define TB_UP 0x1 - -// -// CMPCTL (Compare Control) -// - -// -// LOADAMODE and LOADBMODE bits -// -#define CC_CTR_ZERO 0x0 -#define CC_CTR_PRD 0x1 -#define CC_CTR_ZERO_PRD 0x2 -#define CC_LD_DISABLE 0x3 - -// -// SHDWAMODE and SHDWBMODE bits -// -#define CC_SHADOW 0x0 -#define CC_IMMEDIATE 0x1 - -// -// AQCTLA and AQCTLB (Action Qualifier Control) -// - -// -// ZRO, PRD, CAU, CAD, CBU, CBD bits -// -#define AQ_NO_ACTION 0x0 -#define AQ_CLEAR 0x1 -#define AQ_SET 0x2 -#define AQ_TOGGLE 0x3 - -// -// DBCTL (Dead-Band Control) -// - -// -// OUT MODE bits -// -#define DB_DISABLE 0x0 -#define DBB_ENABLE 0x1 -#define DBA_ENABLE 0x2 -#define DB_FULL_ENABLE 0x3 - -// -// POLSEL bits -// -#define DB_ACTV_HI 0x0 -#define DB_ACTV_LOC 0x1 -#define DB_ACTV_HIC 0x2 -#define DB_ACTV_LO 0x3 - -// -// IN MODE -// -#define DBA_ALL 0x0 -#define DBB_RED_DBA_FED 0x1 -#define DBA_RED_DBB_FED 0x2 -#define DBB_ALL 0x3 - -// -// CHPCTL (chopper control) -// - -// -// CHPEN bit -// -#define CHP_DISABLE 0x0 -#define CHP_ENABLE 0x1 - -// -// CHPFREQ bits -// -#define CHP_DIV1 0x0 -#define CHP_DIV2 0x1 -#define CHP_DIV3 0x2 -#define CHP_DIV4 0x3 -#define CHP_DIV5 0x4 -#define CHP_DIV6 0x5 -#define CHP_DIV7 0x6 -#define CHP_DIV8 0x7 - -// -// CHPDUTY bits -// -#define CHP1_8TH 0x0 -#define CHP2_8TH 0x1 -#define CHP3_8TH 0x2 -#define CHP4_8TH 0x3 -#define CHP5_8TH 0x4 -#define CHP6_8TH 0x5 -#define CHP7_8TH 0x6 - -// -// TZSEL (Trip Zone Select) -// - -// -// CBCn and OSHTn bits -// -#define TZ_DISABLE 0x0 -#define TZ_ENABLE 0x1 - -// -// TZCTL (Trip Zone Control) -// - -// -// TZA and TZB bits -// -#define TZ_HIZ 0x0 -#define TZ_FORCE_HI 0x1 -#define TZ_FORCE_LO 0x2 -#define TZ_NO_CHANGE 0x3 - -// -// TZDCSEL (Trip Zone Digital Compare) -// - -// -// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits -// -#define TZ_EVT_DISABLE 0x0 -#define TZ_DCAH_LOW 0x1 -#define TZ_DCAH_HI 0x2 -#define TZ_DCAL_LOW 0x3 -#define TZ_DCAL_HI 0x4 -#define TZ_DCAL_HI_DCAH_LOW 0x5 - -#define TZ_DCBH_LOW 0x1 -#define TZ_DCBH_HI 0x2 -#define TZ_DCBL_LOW 0x3 -#define TZ_DCBL_HI 0x4 -#define TZ_DCBL_HI_DCBH_LOW 0x5 - -// -// ETSEL (Event Trigger Select) -// -#define ET_DCAEVT1SOC 0x0 -#define ET_CTR_ZERO 0x1 -#define ET_CTR_PRD 0x2 -#define ET_CTR_PRDZERO 0x3 -#define ET_CTRU_CMPA 0x4 -#define ET_CTRD_CMPA 0x5 -#define ET_CTRU_CMPB 0x6 -#define ET_CTRD_CMPB 0x7 - -// -// ETPS (Event Trigger Pre-scale) -// - -// -// INTPRD, SOCAPRD, SOCBPRD bits -// -#define ET_DISABLE 0x0 -#define ET_1ST 0x1 -#define ET_2ND 0x2 -#define ET_3RD 0x3 - -// -// HRPWM (High Resolution PWM) -// - -// -// HRCNFG -// -#define HR_DISABLE 0x0 -#define HR_REP 0x1 -#define HR_FEP 0x2 -#define HR_BEP 0x3 - -#define HR_CMP 0x0 -#define HR_PHS 0x1 - -#define HR_CTR_ZERO 0x0 -#define HR_CTR_PRD 0x1 -#define HR_CTR_ZERO_PRD 0x2 - -#define HR_NORM_B 0x0 -#define HR_INVERT_B 0x1 - -// -// DC (Digital Compare) -// - -// -// DCTRIPSEL -// -#define DC_TZ1 0x0 -#define DC_TZ2 0x1 -#define DC_TZ3 0x2 -#define DC_TRIPIN1 0x0 -#define DC_TRIPIN2 0x1 -#define DC_TRIPIN3 0x2 -#define DC_TRIPIN4 0x3 -#define DC_TRIPIN5 0x4 -#define DC_TRIPIN6 0x5 -#define DC_TRIPIN7 0x6 -#define DC_TRIPIN8 0x7 -#define DC_TRIPIN9 0x8 -#define DC_TRIPIN10 0x9 -#define DC_TRIPIN11 0xA -#define DC_TRIPIN12 0xB -// Reserved 0xC -#define DC_TRIPIN14 0xD -#define DC_TRIPIN15 0xE -#define DC_COMBINATION 0xF - -// -// DCFCTL -// -#define DC_SRC_DCAEVT1 0x0 -#define DC_SRC_DCAEVT2 0x1 -#define DC_SRC_DCBEVT1 0x2 -#define DC_SRC_DCBEVT2 0x3 - -#define DC_PULSESEL_PRD 0x0 -#define DC_PULSESEL_ZERO 0x1 -#define DC_PULSESEL_ZERO_PRD 0x2 - -#define DC_BLANK_DISABLE 0x0 -#define DC_BLANK_ENABLE 0x1 - -#define DC_BLANK_NOTINV 0x0 -#define DC_BLANK_INV 0x1 - -// -//DCACTL/DCBCTL -// -#define DC_EVT1 0x0 -#define DC_EVT2 0x0 -#define DC_EVT_FLT 0x1 -#define DC_EVT_SYNC 0x0 -#define DC_EVT_ASYNC 0x1 -#define DC_SOC_DISABLE 0x0 -#define DC_SOC_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_EPWM_DEFINES_H - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h b/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h deleted file mode 100644 index c1a6266..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_examples.h +++ /dev/null @@ -1,429 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_examples.h -// -// TITLE: f28004x Device Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_EXAMPLES_H -#define F28004x_EXAMPLES_H - -#ifdef __cplusplus -extern "C" { -#endif - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select SYSPLL integer multiplier -//***************************************************************************** - -#define IMULT_0 0 -#define IMULT_1 1 -#define IMULT_2 2 -#define IMULT_3 3 -#define IMULT_4 4 -#define IMULT_5 5 -#define IMULT_6 6 -#define IMULT_7 7 -#define IMULT_8 8 -#define IMULT_9 9 -#define IMULT_10 10 -#define IMULT_11 11 -#define IMULT_12 12 -#define IMULT_13 13 -#define IMULT_14 14 -#define IMULT_15 15 -#define IMULT_16 16 -#define IMULT_17 17 -#define IMULT_18 18 -#define IMULT_19 19 -#define IMULT_20 20 -#define IMULT_21 21 -#define IMULT_22 22 -#define IMULT_23 23 -#define IMULT_24 24 -#define IMULT_25 25 -#define IMULT_26 26 -#define IMULT_27 27 -#define IMULT_28 28 -#define IMULT_29 29 -#define IMULT_30 30 -#define IMULT_31 31 -#define IMULT_32 32 -#define IMULT_33 33 -#define IMULT_34 34 -#define IMULT_35 35 -#define IMULT_36 36 -#define IMULT_37 37 -#define IMULT_38 38 -#define IMULT_39 39 -#define IMULT_40 40 -#define IMULT_41 41 -#define IMULT_42 42 -#define IMULT_43 43 -#define IMULT_44 44 -#define IMULT_45 45 -#define IMULT_46 46 -#define IMULT_47 47 -#define IMULT_48 48 -#define IMULT_49 49 -#define IMULT_50 50 -#define IMULT_51 51 -#define IMULT_52 52 -#define IMULT_53 53 -#define IMULT_54 54 -#define IMULT_55 55 -#define IMULT_56 56 -#define IMULT_57 57 -#define IMULT_58 58 -#define IMULT_59 59 -#define IMULT_60 60 -#define IMULT_61 61 -#define IMULT_62 62 -#define IMULT_63 63 -#define IMULT_64 64 -#define IMULT_65 65 -#define IMULT_66 66 -#define IMULT_67 67 -#define IMULT_68 68 -#define IMULT_69 69 -#define IMULT_70 70 -#define IMULT_71 71 -#define IMULT_72 72 -#define IMULT_73 73 -#define IMULT_74 74 -#define IMULT_75 75 -#define IMULT_76 76 -#define IMULT_77 77 -#define IMULT_78 78 -#define IMULT_79 79 -#define IMULT_80 80 -#define IMULT_81 81 -#define IMULT_82 82 -#define IMULT_83 83 -#define IMULT_84 84 -#define IMULT_85 85 -#define IMULT_86 86 -#define IMULT_87 87 -#define IMULT_88 88 -#define IMULT_89 89 -#define IMULT_90 90 -#define IMULT_91 91 -#define IMULT_92 92 -#define IMULT_93 93 -#define IMULT_94 94 -#define IMULT_95 95 -#define IMULT_96 96 -#define IMULT_97 97 -#define IMULT_98 98 -#define IMULT_99 99 -#define IMULT_100 100 -#define IMULT_101 101 -#define IMULT_102 102 -#define IMULT_103 103 -#define IMULT_104 104 -#define IMULT_105 105 -#define IMULT_106 106 -#define IMULT_107 107 -#define IMULT_108 108 -#define IMULT_109 109 -#define IMULT_110 110 -#define IMULT_111 111 -#define IMULT_112 112 -#define IMULT_113 113 -#define IMULT_114 114 -#define IMULT_115 115 -#define IMULT_116 116 -#define IMULT_117 117 -#define IMULT_118 118 -#define IMULT_119 119 -#define IMULT_120 120 -#define IMULT_121 121 -#define IMULT_122 122 -#define IMULT_123 123 -#define IMULT_124 124 -#define IMULT_125 125 -#define IMULT_126 126 -#define IMULT_127 127 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select SYSPLL fractional multiplier -//***************************************************************************** - -#define FMULT_0 0 -#define FMULT_0pt25 1 -#define FMULT_0pt5 2 -#define FMULT_0pt75 3 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select divsel for SYSPLL -//***************************************************************************** - -#define PLLCLK_BY_1 0 -#define PLLCLK_BY_2 1 -#define PLLCLK_BY_4 2 -#define PLLCLK_BY_6 3 -#define PLLCLK_BY_8 4 -#define PLLCLK_BY_10 5 -#define PLLCLK_BY_12 6 -#define PLLCLK_BY_14 7 -#define PLLCLK_BY_16 8 -#define PLLCLK_BY_18 9 -#define PLLCLK_BY_20 10 -#define PLLCLK_BY_22 11 -#define PLLCLK_BY_24 12 -#define PLLCLK_BY_26 13 -#define PLLCLK_BY_28 14 -#define PLLCLK_BY_30 15 -#define PLLCLK_BY_32 16 -#define PLLCLK_BY_34 17 -#define PLLCLK_BY_36 18 -#define PLLCLK_BY_38 19 -#define PLLCLK_BY_40 20 -#define PLLCLK_BY_42 21 -#define PLLCLK_BY_44 22 -#define PLLCLK_BY_46 23 -#define PLLCLK_BY_48 24 -#define PLLCLK_BY_50 25 -#define PLLCLK_BY_52 26 -#define PLLCLK_BY_54 27 -#define PLLCLK_BY_56 28 -#define PLLCLK_BY_58 29 -#define PLLCLK_BY_60 30 -#define PLLCLK_BY_62 31 -#define PLLCLK_BY_64 32 -#define PLLCLK_BY_66 33 -#define PLLCLK_BY_68 34 -#define PLLCLK_BY_70 35 -#define PLLCLK_BY_72 36 -#define PLLCLK_BY_74 37 -#define PLLCLK_BY_76 38 -#define PLLCLK_BY_78 39 -#define PLLCLK_BY_80 40 -#define PLLCLK_BY_82 41 -#define PLLCLK_BY_84 42 -#define PLLCLK_BY_86 43 -#define PLLCLK_BY_88 44 -#define PLLCLK_BY_90 45 -#define PLLCLK_BY_92 46 -#define PLLCLK_BY_94 47 -#define PLLCLK_BY_96 48 -#define PLLCLK_BY_98 49 -#define PLLCLK_BY_100 50 -#define PLLCLK_BY_102 51 -#define PLLCLK_BY_104 52 -#define PLLCLK_BY_106 53 -#define PLLCLK_BY_108 54 -#define PLLCLK_BY_110 55 -#define PLLCLK_BY_112 56 -#define PLLCLK_BY_114 57 -#define PLLCLK_BY_116 58 -#define PLLCLK_BY_118 59 -#define PLLCLK_BY_120 60 -#define PLLCLK_BY_122 61 -#define PLLCLK_BY_124 62 -#define PLLCLK_BY_126 63 - -//***************************************************************************** -// The following are values that can be passed to the -// InitSysPll() to select clock source -//***************************************************************************** - -#define INT_OSC2 0 // Internal oscillator 2 -#define XTAL_OSC 1 // External oscillator, crystal mode -#define INT_OSC1 2 // Internal oscillator 1 -#define XTAL_OSC_SE 5 // External oscillator, single-ended mode - -/*----------------------------------------------------------------------------- - Specify the clock rate of the CPU (SYSCLKOUT) in nS. - - Take into account the input clock frequency and the PLL multiplier - selected in step 1. - - Use one of the values provided, or define your own. - The trailing L is required tells the compiler to treat - the number as a 64-bit value. - - Only one statement should be uncommented. - - Example: 100 MHz devices: - CLKIN is a 10 MHz crystal or internal 10 MHz oscillator - - In step 1 the user specified the PLL multiplier = 0x20 for a - 100 MHz CPU clock (SYSCLKOUT = 100 MHz). - - In this case, the CPU_RATE will be 10.000L - Uncomment the line: #define CPU_RATE 10.000L - ------------------------------------------------------------------------------*/ - -#define CPU_RATE 10.00L // for a 100MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 11.111L // for a 90MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 12.500L // for a 80MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 25.000L // for a 40MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) - -// -// The following pointer to a function call calibrates the ADC reference, -// DAC offset, and internal oscillators -// -#define Device_cal (void (*)(void))0x070282 - -// -// The following pointers to functions calibrate the ADC linearity. Use this -// in the AdcSetMode(...) function only -// -#define CalAdcaINL (void (*)(void))0x0703B4 -#define CalAdcbINL (void (*)(void))0x0703B2 -#define CalAdccINL (void (*)(void))0x0703B0 -#define CalAdcdINL (void (*)(void))0x0703AE - -// -// The following pointer to a function call looks up the ADC offset trim for a -// given condition. Use this in the AdcSetMode(...) function only. -// -#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC - -// -// Include Example Header Files: -// - -#include "f28004x_globalprototypes.h" //Prototypes for global functions - //within the .c files. -#include "f28004x_adc_defines.h" -#include "f28004x_cputimervars.h" -#include "f28004x_epwm_defines.h" -#include "f28004x_gpio_defines.h" // Macros used for GPIO support code -#include "f28004x_pie_defines.h" // Macros used for PIE examples -#include "f28004x_sysctrl_defines.h" // Macros used for LPM support code -#include "f28004x_dma_defines.h" // Macros used for DMA support code -#include "f28004x_cla_defines.h" //Macros used for CLA support code - -#define PARTNO_28004xPACKAGEHERE 0x00 - -#define CPU_FRQ_100MHZ 1 - -// -// Include files not used with F/BIOS -// -#ifndef F28_BIOS -#include "f28004x_defaultisr.h" -#endif - -extern void F28x_usDelay(long LoopCount); -// DO NOT MODIFY THIS LINE. -#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) - -// -// Useful Timer Operations -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F28004x_EXAMPLES_H definition - -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h b/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h deleted file mode 100644 index 0d6a25a..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_globalprototypes.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_globalprototypes.h -// -// TITLE: Global prototypes for f28004x Examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_GLOBALPROTOTYPES_H -#define F28004x_GLOBALPROTOTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// shared global function prototypes -// -extern void EnableInterrupts(void); -extern void InitPeripheralClocks(void); -extern void DisablePeripheralClocks(void); -extern void InitPieCtrl(void); -extern void InitPieVectTable(void); -extern void InitSpi(void); -extern void InitSpiGpio(void); -extern void InitSpiaGpio(void); -extern void InitSysCtrl(void); -extern void InitSysPll(Uint16 clock_source, - Uint16 imult, Uint16 fmult, Uint16 divsel); -extern bool IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult); - -// -// For compatibility with previous versions -// -#define KickDog ServiceDog -extern void ServiceDog(void); -extern void DisableDog(void); - -extern Uint16 CsmUnlock(void); -extern void SysIntOsc1Sel (void); -extern void SysIntOsc2Sel (void); -extern void SysXtalOscSel (void); -extern void SysXtalOscSESel (void); - -// -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -extern void InitFlash(void); -extern void FlashOff(void); - -// -// LPM functions in f28004x_sysctrl.c -// -void IDLE(void); -void HALT(void); - -// -// ADC functions -// -extern void SetVREF(int module, int mode, int ref); - -// -// DMA Functions -// -extern void DMAInitialize(void); - -// -// DMA Channel 1 -// -extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, - int16 desbstep); -extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH1(void); - -// -// DMA Channel 2 -// -extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, - Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, Uint16 chinte); -extern void StartDMACH2(void); - -// -// DMA Channel 3 -// -extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH3(void); - -// -// DMA Channel 4 -// -extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH4(void); - -// -// DMA Channel 5 -// -extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH5(void); - -// -// DMA Channel 6 -// -extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); -extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, - int16 deststep); -extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, - Uint16 deswsize, int16 deswstep); -extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, - Uint16 oneshot, Uint16 cont, Uint16 synce, - Uint16 syncsel, Uint16 ovrinte, - Uint16 datasize, Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH6(void); - -// -// GPIO Functions -// -extern void InitGpio(void); -extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, - Uint16 muxPosition); -extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, - Uint16 flags); -extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); -extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); -Uint16 GPIO_ReadPin(Uint16 gpioNumber); -void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); - -// External symbols created by the linker cmd file -// DSP28 examples will use these to relocate code from one LOAD location -// in Flash to a different RUN location in internal -// RAM -// -extern Uint16 RamfuncsLoadStart; -extern Uint16 RamfuncsLoadEnd; -extern Uint16 RamfuncsLoadSize; -extern Uint16 RamfuncsRunStart; -extern Uint16 RamfuncsRunEnd; -extern Uint16 RamfuncsRunSize; - - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_GLOBALPROTOTYPES_H - -// -// End of file. -// diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h deleted file mode 100644 index 5503c44..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_gpio_defines.h +++ /dev/null @@ -1,105 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio_defines.h -// -// TITLE: f28004x GPIO support definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_GPIO_DEFINES_H -#define F28004x_GPIO_DEFINES_H - -// -// Defines -// - -// -// CPU pin masters for GPIO_SelectPinMux() -// -#define GPIO_MUX_CPU1 0x0 -#define GPIO_MUX_CPU1CLA 0x1 - -// -// Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, -// QUAL6, and ASYNC) take up two bits and must be in the order specified. -// -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 -#define GPIO_PUSHPULL 0 -#define GPIO_PULLUP (1 << 0) -#define GPIO_INVERT (1 << 1) -#define GPIO_OPENDRAIN (1 << 2) -#define GPIO_SYNC (0x0 << 4) -#define GPIO_QUAL3 (0x1 << 4) -#define GPIO_QUAL6 (0x2 << 4) -#define GPIO_ASYNC (0x3 << 4) - -// -// Flags for GPIO_SetupLock(). -// -#define GPIO_UNLOCK 0 -#define GPIO_LOCK 1 - -// -// Helpful constants for array-based access to GPIO registers -// -#define GPY_CTRL_OFFSET (0x40/2) -#define GPY_DATA_OFFSET (0x8/2) - -#define GPYQSEL (0x2/2) -#define GPYMUX (0x6/2) -#define GPYDIR (0xA/2) -#define GPYPUD (0xC/2) -#define GPYINV (0x10/2) -#define GPYODR (0x12/2) -#define GPYGMUX (0x20/2) -#define GPYCSEL (0x28/2) -#define GPYLOCK (0x3C/2) -#define GPYCR (0x3E/2) - -#define GPYDAT (0x0/2) -#define GPYSET (0x2/2) -#define GPYCLEAR (0x4/2) -#define GPYTOGGLE (0x6/2) - -#endif // end of F28004x_GPIO_DEFINES_H definition - -// -// End of file -// - - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h deleted file mode 100644 index 2cd6101..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_pie_defines.h +++ /dev/null @@ -1,72 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pie_defines.h -// -// TITLE: #defines used in PIE examples -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_PIE_DEFINES_H -#define F28004x_PIE_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define PIEACK_GROUP1 0x0001 -#define PIEACK_GROUP2 0x0002 -#define PIEACK_GROUP3 0x0004 -#define PIEACK_GROUP4 0x0008 -#define PIEACK_GROUP5 0x0010 -#define PIEACK_GROUP6 0x0020 -#define PIEACK_GROUP7 0x0040 -#define PIEACK_GROUP8 0x0080 -#define PIEACK_GROUP9 0x0100 -#define PIEACK_GROUP10 0x0200 -#define PIEACK_GROUP11 0x0400 -#define PIEACK_GROUP12 0x0800 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F28004x_PIE_DEFINES_H - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h b/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h deleted file mode 100644 index e54a9b9..0000000 --- a/els-f280049c/device_support_f28004x/common/include/f28004x_sysctrl_defines.h +++ /dev/null @@ -1,59 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl_defines.h -// -// TITLE: f28004x LPM support definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004x_SYSCTRL_DEFINES_H -#define F28004x_SYSCTRL_DEFINES_H - -// -// Defines -// -#define LPM_IDLE 0x0 -#define LPM_HALT 0x2 -#define LPM_HIB 0x3 - -#endif // end of F28004x_SYSCTRL_DEFINES_H definition - -// -// End of file. -// - - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c b/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c deleted file mode 100644 index 1c99c84..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_adc.c +++ /dev/null @@ -1,102 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc.c -// -// TITLE: F28004x ADC Support Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Header File Include File -#include "f28004x_examples.h" // Examples Include File - -// -// SetVREF - Set Vref mode. Function to select reference mode and offset trim. -// Offset trim for Internal VREF 3.3 is unique. All other modes use the same -// offset trim. Also note that when the mode parameter is ADC_EXTERNAL, the -// ref parameter has no effect. -// -void SetVREF(int module, int mode, int ref) -{ - Uint16 *offset, offval; - - // - // Define offset locations from OTP - // - offset = (Uint16 *)(0x70594 + (module * 6)); - - if((mode == ADC_INTERNAL) && (ref == ADC_VREF3P3)) - { - offval = (*offset) >> 8; // Internal / 1.65v mode offset - } - else - { - offval = (*offset) & 0xFF; // All other modes - } - - // - // Write offset trim values and configure reference modes - // - EALLOW; - switch(module) - { - case 0: - AdcaRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFASEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFA2P5SEL = ref; - break; - case 1: - AdcbRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFBSEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFB2P5SEL = ref; - break; - case 2: - AdccRegs.ADCOFFTRIM.bit.OFFTRIM = offval; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFCSEL = mode; - AnalogSubsysRegs.ANAREFCTL.bit.ANAREFC2P5SEL = ref; - break; - default: - break; - } - EDIS; -} - -// -// End of File -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm deleted file mode 100644 index e34559f..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_codestartbranch.asm +++ /dev/null @@ -1,111 +0,0 @@ -;//########################################################################### -;// -;// FILE: f28004x_codestartbranch.asm -;// -;// TITLE: Branch for redirecting code execution after boot. -;// -;// For these examples, code_start is the first code that is executed after -;// exiting the boot ROM code. -;// -;// The codestart section in the linker cmd file is used to physically place -;// this code at the correct memory location. This section should be placed -;// at the location the BOOT ROM will re-direct the code to. For example, -;// for boot to FLASH this code will be located at 0x80000. -;// -;// In addition, the example f28004x projects are setup such that the codegen -;// entry point is also set to the codestart label. This is done by linker -;// option -e in the project build options. When the debugger loads the code, -;// it will automatically set the PC to the "entry point" address indicated by -;// the -e linker option. In this case the debugger is simply assigning the PC, -;// it is not the same as a full reset of the device. -;// -;// The compiler may warn that the entry point for the project is other then -;// _c_init00. _c_init00 is the C environment setup and is run before -;// main() is entered. The codestart code will re-direct the execution -;// to _c_init00 and thus there is no worry and this warning can be ignored. -;// -;//########################################################################### -;// $TI Release: F28004x Support Library v1.05.00.00 $ -;// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;// $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;//########################################################################### - -*********************************************************************** - -WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 - - .ref _c_int00 - .global code_start - -*********************************************************************** -* Function: codestart section -* -* Description: Branch to code starting point -*********************************************************************** - - .sect "codestart" - -code_start: - .if WD_DISABLE == 1 - LB wd_disable ;Branch to watchdog disable code - .else - LB _c_int00 ;Branch to start of boot._asm in RTS library - .endif - -;end codestart section - -*********************************************************************** -* Function: wd_disable -* -* Description: Disables the watchdog timer -*********************************************************************** - .if WD_DISABLE == 1 - - .text -wd_disable: - SETC OBJMODE ;Set OBJMODE for 28x object code - EALLOW ;Enable EALLOW protected register access - MOVZ DP, #7029h>>6 ;Set data page for WDCR register - MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD - EDIS ;Disable EALLOW protected register access - LB _c_int00 ;Branch to start of boot._asm in RTS library - - .endif - -;end wd_disable - - .end - -;// -;// End of file. -;// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c b/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c deleted file mode 100644 index a4583a3..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_cputimers.c +++ /dev/null @@ -1,194 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimers.c -// -// TITLE: f28004x CPU 32-bit Timers Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File - -// -// Globals -// -struct CPUTIMER_VARS CpuTimer0; -struct CPUTIMER_VARS CpuTimer1; -struct CPUTIMER_VARS CpuTimer2; - -// -// InitCpuTimers - This function initializes all three CPU timers -// to a known state. -// -void -InitCpuTimers(void) -{ - // - // CPU Timer 0 - // Initialize address pointers to respective timer registers - // - CpuTimer0.RegsAddr = &CpuTimer0Regs; - - // - // Initialize timer period to maximum - // - CpuTimer0Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) - // - CpuTimer0Regs.TPR.all = 0; - CpuTimer0Regs.TPRH.all = 0; - - // - // Make sure timer is stopped - // - CpuTimer0Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value - // - CpuTimer0Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters - // - CpuTimer0.InterruptCount = 0; - - // - // CPU Timer 1 and 2 - // Initialize address pointers to respective timer registers - // - CpuTimer1.RegsAddr = &CpuTimer1Regs; - CpuTimer2.RegsAddr = &CpuTimer2Regs; - - // - // Initialize timer period to maximum - // - CpuTimer1Regs.PRD.all = 0xFFFFFFFF; - CpuTimer2Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) - // - CpuTimer1Regs.TPR.all = 0; - CpuTimer1Regs.TPRH.all = 0; - CpuTimer2Regs.TPR.all = 0; - CpuTimer2Regs.TPRH.all = 0; - - // - // Make sure timers are stopped - // - CpuTimer1Regs.TCR.bit.TSS = 1; - CpuTimer2Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value - // - CpuTimer1Regs.TCR.bit.TRB = 1; - CpuTimer2Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters - // - CpuTimer1.InterruptCount = 0; - CpuTimer2.InterruptCount = 0; -} - -// -// ConfigCpuTimer - This function initializes the selected timer to the period -// specified by the "Freq" and "Period" parameters. The "Freq" is entered -// as "MHz" and the "Period" in "uSeconds". The timer is held in the stopped -// state after configuration. -// -void -ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) -{ - Uint32 temp; - - // - // Initialize timer period - // - Timer->CPUFreqInMHz = Freq; - Timer->PeriodInUSec = Period; - temp = (long) (Freq * Period); - Timer->RegsAddr->PRD.all = temp; - - // - // Set pre-scale counter to divide by 1 (SYSCLKOUT) - // - Timer->RegsAddr->TPR.all = 0; - Timer->RegsAddr->TPRH.all = 0; - - // - // Initialize timer control register - // - - // - // 1 = Stop timer, 0 = Start/Restart Timer - // - Timer->RegsAddr->TCR.bit.TSS = 1; - - // - // 1 = reload timer - // - Timer->RegsAddr->TCR.bit.TRB = 1; - Timer->RegsAddr->TCR.bit.SOFT = 0; - - // - // Timer Free Run Disabled - // - Timer->RegsAddr->TCR.bit.FREE = 0; - - // - // 0 = Disable 1 = Enable Timer Interrupt - // - Timer->RegsAddr->TCR.bit.TIE = 1; - - // - // Reset interrupt counter - // - Timer->InterruptCount = 0; -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm deleted file mode 100644 index 151c1d0..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z1otp.asm +++ /dev/null @@ -1,186 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_dcsm_z1otp.asm -;; -;; TITLE: Dual Code Security Module Zone 1 OTP -;; -;; DESCRIPTION: -;; -;; This file is used to specify Z1 DCSM OTP and zone select block -;; values to program. -;; -;; In addition, the 60 reserved values after the zone select block -;; are all programmed to 0x0000 as well. -;; -;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time -;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order -;; to program the below memory sections, user should uncomment the .long words -;; of each section and change the value to what is desired. Additionally, the -;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a -;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section -;; that is being programmed. -;; -;; -;; !!IMPORTANT!! The "bx_dcsm_otp_z1_linkpointer" section contains the -;; Z1 LINKPOINTER which determines the location of the Z1 Zone Select block. -;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z1_linkpointer" -;; section in the *_dcsm_lnk.cmd command linker file must also change to an -;; address decoded from the value specified in the Z1-LINKPOINTER location. -;; -;; -;; The "bx_dcsm_zsel_z1" section contains the actual Z1 Zone Select Block -;; values that will be linked and programmed into to the DCSM Z1 OTP Zone -;; Select block in OTP. -;; These values must be known in order to unlock the CSM module. -;; -;; It is recommended that all values be left as 0xFFFFFFFF during code -;; development. Values of 0xFFFFFFFF do not activate code security and dummy -;; reads of the Z1 DCSM PWL registers is all that is required to unlock the -;; CSM. When code development is complete, modify values to activate the -;; code security module. -;; -;; ******************************WARNING*************************************** -;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users -;; intend to comeback and re-program any of the bits to '0' in future. If user -;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would -;; get programmed to a non erased state and users won't be able to comeback -;; and re-program the OTP location to another value. Please refer to DCSM -;; chapter of device TRM for more details on ECC for the locations in DCSM. -;; -;; Hence TI ships this example commenting out the initialization of all the -;; below locations. -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .sect "b0_dcsm_otp_z1_linkpointer" -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_gpreg" -;; -;; See the ROM Code and Peripheral Booting chapter of TRM for more details. -;; -;; Below is a description of the bit fields of Z1OTP_BOOTPIN_CONFIG -;; used by Boot ROM. -;; -;; | Key (31-24) | BMSP2 (23-16) | BMSP1 (15-8) | BMSP0 (7-0) | -;; -;; Below is a description of the bit fields of Z1OTP_GPREG2 used by -;; Boot ROM. -;; -;; | Key (31-24) | RSVD (23-8) | RSVD (7-6) | ESP (5-4) | RSVD (3-0) | -;; -;; .long 0xFFFFFFFF ;Z1OTP_BOOTPIN_CONFIG -;; .long 0xFFFFFFFF ;Z1OTP_GPREG2 - - .sect "b0_dcsm_otp_z1_pswdlock" -;; .long 0xFFFFFFFF ;Z1OTP_PSWDLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_crclock" -;; .long 0xFFFFFFFF ;Z1OTP_CRCLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z1_bootctrl" -;; -;; See the ROM Code and Peripheral Booting chapter of TRM for more details. -;; -;; Below is a description of the bit fields of Z1OTP_BOOTDEF_LOW used by -;; Boot ROM. -;; -;; | BOOT_DEF3(31-24) | BOOT_DEF2(23-16) | BOOT_DEF1(15-8) | BOOT_DEF0(7-0) | -;; -;; Below is a description of the bit fields of Z1OTP_BOOTDEF_HIGH -;; used by Boot ROM. -;; -;; | BOOT_DEF7(31-24) | BOOT_DEF6(23-16) | BOOT_DEF5(15-8) | BOOT_DEF4(7-0) | -;; -;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_LOW -;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_HIGH - - .sect "b0_dcsm_zsel_z1" - -;; .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYRAM -;; .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;B0_Z1OTP_GRABRAM -;; .long 0xFFFFFFFF ;B0_Z1OTP_GRABSECT - -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD0 (LSW of 128-bit password) -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD1 -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD2 -;; .long 0xFFFFFFFF ;B0_Z1OTP_CSMPSWD3 (MSW of 128-bit password) - - .sect "b1_dcsm_otp_z1_linkpointer" -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b1_dcsm_zsel_z1" -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z1OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z1OTP_GRABSECT - -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved - -;;---------------------------------------------------------------------- - -;; For code security operation,after development has completed, prior to -;; production, all other zone select block locations should be programmed -;; to 0x0000 for maximum security. -;; If the first zone select block at offset 0x10 is used, the section -;; "dcsm_rsvd_z1" can be used to program these locations to 0x0000. -;; This code is commented out for development. - -;; .sect "dcsm_rsvd_z1" -;; .loop (1e0h) -;; .int 0x0000 -;; .endloop - - -;;############################################################################# -;; End of file -;;############################################################################# diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm deleted file mode 100644 index 99d093a..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dcsm_z2otp.asm +++ /dev/null @@ -1,159 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_dcsm_z2otp.asm -;; -;; TITLE: Dual Code Security Module Zone 2 OTP -;; -;; DESCRIPTION: -;; -;; This file is used to specify Z2 DCSM OTP and zone select block -;; values to program. -;; -;; In addition, the 60 reserved values after the zone select block -;; are all programmed to 0x0000 as well. -;; -;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time -;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order -;; to program the below memory sections, user should uncomment the .long words -;; of each section and change the value to what is desired. Additionally, the -;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a -;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section -;; that is being programmed. -;; -;; -;; !!IMPORTANT!! The "bx_dcsm_otp_z2_linkpointer" section contains the -;; Z2 LINKPOINTER which determines the location of the Z2 Zone Select block. -;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z2_linkpointer" -;; section in the *_dcsm_lnk.cmd command linker file must also change to an -;; address decoded from the value specified in the Z2-LINKPOINTER location. -;; -;; -;; The "bx_dcsm_zsel_z2" section contains the actual Z2 Zone Select Block -;; values that will be linked and programmed into to the DCSM Z2 OTP Zone -;; Select block in OTP. -;; These values must be known in order to unlock the CSM module. -;; -;; It is recommended that all values be left as 0xFFFFFFFF during code -;; development. Values of 0xFFFFFFFF do not activate code security and dummy -;; reads of the Z2 DCSM PWL registers is all that is required to unlock the -;; CSM. When code development is complete, modify values to activate the -;; code security module. -;; -;; ******************************WARNING*************************************** -;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users -;; intend to comeback and re-program any of the bits to '0' in future. If user -;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would -;; get programmed to a non erased state and users won't be able to comeback -;; and re-program the OTP location to another value. Please refer to DCSM -;; chapter of device TRM for more details on ECC for the locations in DCSM. -;; -;; Hence TI ships this example commenting out the initialization of all the -;; below locations. -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .sect "b0_dcsm_otp_z2_linkpointer" -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B0_Z2OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_gpreg" -;; .long 0xFFFFFFFF ;Z2OTP_BOOTPIN_CONFIG -;; .long 0xFFFFFFFF ;Z2OTP_GPREG2 - - .sect "b0_dcsm_otp_z2_pswdlock" -;; .long 0xFFFFFFFF ;Z2OTP_PSWDLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_crclock" -;; .long 0xFFFFFFFF ;Z2OTP_CRCLOCK -;; .long 0xFFFFFFFF ;Reserved - - .sect "b0_dcsm_otp_z2_bootctrl" -;; .long 0xFFFFFFFF ;Z2OTP_GPREG3 -;; .long 0xFFFFFFFF ;Z2OTP_BOOTCTRL - - .sect "b0_dcsm_zsel_z2" -;; .long 0xFFFFFFFF ;B0_Z2OTP_EXEONLYRAM -;; .long 0xFFFFFFFF ;B0_Z2OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;B0_Z2OTP_GRABRAM -;; .long 0xFFFFFFFF ;B0_Z2OTP_GRABSECT - -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD0 (LSW of 128-bit password) -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD1 -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD2 -;; .long 0xFFFFFFFF ;B0_Z2OTP_CSMPSWD3 (MSW of 128-bit password) - - .sect "b1_dcsm_otp_z2_linkpointer" -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER1 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER2 -;; .long 0xFFFFFFFF ;Reserved -;; .long 0x1FFFFFFF ;B1_Z2OTP_LINKPOINTER3 -;; .long 0xFFFFFFFF ;Reserved - - .sect "b1_dcsm_zsel_z2" -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z2OTP_EXEONLYSECT -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;B1_Z2OTP_GRABSECT - -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved -;; .long 0xFFFFFFFF ;Reserved - -;;---------------------------------------------------------------------- - -;; For code security operation,after development has completed, prior to -;; production, all other zone select block locations should be programmed -;; to 0x0000 for maximum security. -;; If the first zone select block at offset 0x10 is used, the section -;; "dcsm_rsvd_z2" can be used to program these locations to 0x0000. -;; This code is commented out for development. - -;; .sect "dcsm_rsvd_z2" -;; .loop (1e0h) -;; .int 0x0000 -;; .endloop - - -;;############################################################################# -;; End of file -;;############################################################################# diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c b/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c deleted file mode 100644 index 06b2643..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_defaultisr.c +++ /dev/null @@ -1,2780 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_defaultisr.c -// -// TITLE: f28004x Device Default Interrupt Service Routines -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // F28004x Header File Include File -#include "f28004x_examples.h" // F28004x Examples Include File - -// -// TIMER1_ISR - CPU Timer 1 Interrupt -// -interrupt void -TIMER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// TIMER2_ISR - CPU Timer 2 Interrupt -// -interrupt void -TIMER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DATALOG_ISR - Datalogging Interrupt -// -interrupt void -DATALOG_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RTOS_ISR - RTOS Interrupt -// -interrupt void -RTOS_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EMU_ISR - Emulation Interrupt -// -interrupt void -EMU_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// NMI_ISR - Non-Maskable Interrupt -// -interrupt void -NMI_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ILLEGAL_ISR - Illegal Operation Trap -// -interrupt void -ILLEGAL_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER1_ISR - User Defined Trap 1 -// -interrupt void -USER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER2_ISR - User Defined Trap 2 -// -interrupt void -USER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER3_ISR - User Defined Trap 3 -// -interrupt void -USER3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER4_ISR - User Defined Trap 4 -// -interrupt void -USER4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER5_ISR - User Defined Trap 5 -// -interrupt void -USER5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER6_ISR - User Defined Trap 6 -// -interrupt void -USER6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER7_ISR - User Defined Trap 7 -// -interrupt void -USER7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER8_ISR - User Defined Trap 8 -// -interrupt void -USER8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER9_ISR - User Defined Trap 9 -// -interrupt void -USER9_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER10_ISR - User Defined Trap 10 -// -interrupt void -USER10_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER11_ISR - User Defined Trap 11 -// -interrupt void -USER11_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// USER12_ISR - User Defined Trap 12 -// -interrupt void -USER12_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA1_ISR - ADCA Interrupt 1 -// -interrupt void -ADCA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB1_ISR - ADCB Interrupt 1 -// -interrupt void -ADCB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC1_ISR - ADCC Interrupt 1 -// -interrupt void -ADCC1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT1_ISR - XINT1 Interrupt -// -interrupt void -XINT1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT2_ISR - XINT2 Interrupt -// -interrupt void -XINT2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// TIMER0_ISR - Timer 0 Interrupt -// -interrupt void -TIMER0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// WAKE_ISR - Halt Wakeup Interrupt -// -interrupt void -WAKE_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM1_TZ_ISR - ePWM1 Trip Zone Interrupt -// -interrupt void -EPWM1_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM2_TZ_ISR - ePWM2 Trip Zone Interrupt -// -interrupt void -EPWM2_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM3_TZ_ISR - ePWM3 Trip Zone Interrupt -// -interrupt void -EPWM3_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM4_TZ_ISR - ePWM4 Trip Zone Interrupt -// -interrupt void -EPWM4_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM5_TZ_ISR - ePWM5 Trip Zone Interrupt -// -interrupt void -EPWM5_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM6_TZ_ISR - ePWM6 Trip Zone Interrupt -// -interrupt void -EPWM6_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM7_TZ_ISR - ePWM7 Trip Zone Interrupt -// -interrupt void -EPWM7_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM8_TZ_ISR - ePWM8 Trip Zone Interrupt -// -interrupt void -EPWM8_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM1_ISR - ePWM1 Interrupt -// -interrupt void -EPWM1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM2_ISR - ePWM2 Interrupt -// -interrupt void -EPWM2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM3_ISR - ePWM3 Interrupt -// -interrupt void -EPWM3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM4_ISR - ePWM4 Interrupt -// -interrupt void -EPWM4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM5_ISR - ePWM5 Interrupt -// -interrupt void -EPWM5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM6_ISR - ePWM6 Interrupt -// -interrupt void -EPWM6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM7_ISR - ePWM7 Interrupt -// -interrupt void -EPWM7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EPWM8_ISR - ePWM8 Interrupt -// -interrupt void -EPWM8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP1_ISR - eCAP1 Interrupt -// -interrupt void -ECAP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP2_ISR - eCAP2 Interrupt -// -interrupt void -ECAP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP3_ISR - eCAP3 Interrupt -// -interrupt void -ECAP3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP4_ISR - eCAP4 Interrupt -// -interrupt void -ECAP4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP5_ISR - eCAP5 Interrupt -// -interrupt void -ECAP5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP6_ISR - eCAP6 Interrupt -// -interrupt void -ECAP6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP7_ISR - eCAP7 Interrupt -// -interrupt void -ECAP7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP6_2_ISR - eCAP6_2 Interrupt -// -interrupt void -ECAP6_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ECAP7_2_ISR - eCAP7_2 Interrupt -// -interrupt void -ECAP7_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EQEP1_ISR - eQEP1 Interrupt -// -interrupt void -EQEP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// EQEP2_ISR - eQEP2 Interrupt -// -interrupt void -EQEP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIA_RX_ISR - SPIA Receive Interrupt -// -interrupt void -SPIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIA_TX_ISR - SPIA Transmit Interrupt -// -interrupt void -SPIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIB_RX_ISR - SPIB Receive Interrupt -// -interrupt void -SPIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SPIB_TX_ISR - SPIB Transmit Interrupt -// -interrupt void -SPIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH1_ISR - DMA Channel 1 Interrupt -// -interrupt void -DMA_CH1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH2_ISR - DMA Channel 2 Interrupt -// -interrupt void -DMA_CH2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH3_ISR - DMA Channel 3 Interrupt -// -interrupt void -DMA_CH3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH4_ISR - DMA Channel 4 Interrupt -// -interrupt void -DMA_CH4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH5_ISR - DMA Channel 5 Interrupt -// -interrupt void -DMA_CH5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// DMA_CH6_ISR - DMA Channel 6 Interrupt -// -interrupt void -DMA_CH6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// I2CA_ISR - I2CA Interrupt 1 -// -interrupt void -I2CA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// I2CA_FIFO_ISR - I2CA Interrupt 2 -// -interrupt void -I2CA_FIFO_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIA_RX_ISR - SCIA Receive Interrupt -// -interrupt void -SCIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIA_TX_ISR - SCIA Transmit Interrupt -// -interrupt void -SCIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIB_RX_ISR - SCIB Receive Interrupt -// -interrupt void -SCIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SCIB_TX_ISR - SCIB Transmit Interrupt -// -interrupt void -SCIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANA0_ISR - CANA Interrupt 0 -// -interrupt void -CANA0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANA1_ISR - CANA Interrupt 1 -// -interrupt void -CANA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANB0_ISR - CANB Interrupt 0 -// -interrupt void -CANB0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CANB1_ISR - CANB Interrupt 1 -// -interrupt void -CANB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA_EVT_ISR - ADCA Event Interrupt -// -interrupt void -ADCA_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA2_ISR - ADCA Interrupt 2 -// -interrupt void -ADCA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA3_ISR - ADCA Interrupt 3 -// -interrupt void -ADCA3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCA4_ISR - ADCA Interrupt 4 -// -interrupt void -ADCA4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB_EVT_ISR - ADCB Event Interrupt -// -interrupt void -ADCB_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB2_ISR - ADCB Interrupt 2 -// -interrupt void -ADCB2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB3_ISR - ADCB Interrupt 3 -// -interrupt void -ADCB3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCB4_ISR - ADCB Interrupt 4 -// -interrupt void -ADCB4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_1_ISR - CLA1 Interrupt 1 -// -interrupt void -CLA1_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_2_ISR - CLA1 Interrupt 2 -// -interrupt void -CLA1_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_3_ISR - CLA1 Interrupt 3 -// -interrupt void -CLA1_3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_4_ISR - CLA1 Interrupt 4 -// -interrupt void -CLA1_4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_5_ISR - CLA1 Interrupt 5 -// -interrupt void -CLA1_5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_6_ISR - CLA1 Interrupt 6 -// -interrupt void -CLA1_6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_7_ISR - CLA1 Interrupt 7 -// -interrupt void -CLA1_7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1_8_ISR - CLA1 Interrupt 8 -// -interrupt void -CLA1_8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT3_ISR - XINT3 Interrupt -// -interrupt void -XINT3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT4_ISR - XINT4 Interrupt -// -interrupt void -XINT4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// XINT5_ISR - XINT5 Interrupt -// -interrupt void -XINT5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FPU_OVERFLOW_ISR - FPU Overflow Interrupt -// -interrupt void -FPU_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FPU_UNDERFLOW_ISR - FPU Underflow Interrupt -// -interrupt void -FPU_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1_ISR - SDFM1 Interrupt -// -interrupt void -SD1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR1_ISR - SDFM1 DR Interrupt 1 -// -interrupt void -SD1DR1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR2_ISR - SDFM1 DR Interrupt 2 -// -interrupt void -SD1DR2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR3_ISR - SDFM1 DR Interrupt 3 -// -interrupt void -SD1DR3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SD1DR4_ISR - SDFM1 DR Interrupt 4 -// -interrupt void -SD1DR4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - - -// -// FSITXA1_ISR - FSITXA1_ISR Interrupt -// -interrupt void -FSITXA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSITXA2_ISR - FSITXA2_ISR Interrupt -// -interrupt void -FSITXA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSIRXA1_ISR - FSIRXA1_ISR Interrupt -// -interrupt void -FSIRXA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FSIRXA2_ISR - FSIRXA2_ISR Interrupt -// -interrupt void -FSIRXA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA1PROMCRC - CLA1PROMCRC Interrupt -// -interrupt void -CLA1PROMCRC_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// LINA_0 - LINA Interrupt 0 -// -interrupt void -LINA_0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// LINA_1 - LINA Interrupt 1 -// -interrupt void -LINA_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// PMBUSA - PMBUSA Interrupt -// -interrupt void -PMBUSA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC_EVT_ISR - ADCC Event Interrupt -// -interrupt void -ADCC_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC2_ISR - ADCC Interrupt 2 -// -interrupt void -ADCC2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC3_ISR - ADCC Interrupt 3 -// -interrupt void -ADCC3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// ADCC4_ISR - ADCC Interrupt 4 -// -interrupt void -ADCC4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RAM_CORRECTABLE_ERROR_ISR - RAM Correctable Error Interrupt -// -interrupt void -RAM_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// FLASH_CORRECTABLE_ERROR_ISR - Flash Correctable Error Interrupt -// -interrupt void -FLASH_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RAM_ACCESS_VIOLATION_ISR - RAM Access Violation Interrupt -// -interrupt void -RAM_ACCESS_VIOLATION_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// SYS_PLL_SLIP_ISR - System PLL Slip Interrupt -// -interrupt void -SYS_PLL_SLIP_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA_OVERFLOW_ISR - CLA Overflow Interrupt -// -interrupt void -CLA_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CLA_UNDERFLOW_ISR - CLA Underflow Interrupt -// -interrupt void -CLA_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Catch-all Default ISRs -// - -// -// PIE_RESERVED_ISR - Reserved ISR -// -interrupt void -PIE_RESERVED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// EMPTY_ISR - Only does a return -// -interrupt void -EMPTY_ISR(void) -{ - -} - -// -// NOTUSED_ISR - Unused ISR -// -interrupt void -NOTUSED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c b/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c deleted file mode 100644 index 3a245db..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_dma.c +++ /dev/null @@ -1,1104 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma.c -// -// TITLE: f28004x DMA Initialization & Support Functions. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "f28004x_device.h" -#include "f28004x_examples.h" - -// -// DMAInitialize - This function initializes the DMA to a known state. -// -void DMAInitialize(void) -{ - EALLOW; - - // - // Perform a hard reset on DMA - // - DmaRegs.DMACTRL.bit.HARDRESET = 1; - __asm (" nop"); // one NOP required after HARDRESET - - // - // Allow DMA to run free on emulation suspend - // - DmaRegs.DEBUGCTRL.bit.FREE = 1; - - EDIS; -} - -// -// DMACH1AddrConfig - DMA Channel 1 Address Configuration -// -void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to - // beginning of - // destination buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH1BurstConfig - DMA Channel 1 Burst size configuration -// -void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) - // x-ferred in a burst. - DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between - // each word x-ferred. - - EDIS; -} - -// -// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration -// -void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored - // when WRAP occurs. - DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored - // when WRAP occurs. - - EDIS; -} - -// -// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration -// -void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap - DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH1ModeConfig - DMA Channel 1 Mode configuration -// -void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; - DmaRegs.CH1.MODE.bit.PERINTSEL = 1; - DmaRegs.CH1.MODE.bit.PERINTE = perinte; - DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH1.MODE.bit.DATASIZE = datasize; - DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH1.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt and sync error flags - // - DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH1 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx1 = 1; - - EDIS; -} - -// -// StartDMACH1 - This function starts DMA Channel 1. -// -void StartDMACH1(void) -{ - EALLOW; - DmaRegs.CH1.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH2AddrConfig - DMA Channel 2 Address Configuration -// -void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer. - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2BurstConfig - DMA Channel 2 Burst size configuration -// -void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration -// -void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration -// -void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH2ModeConfig - DMA Channel 2 Mode configuration -// -void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; - DmaRegs.CH2.MODE.bit.PERINTSEL = 2; - DmaRegs.CH2.MODE.bit.PERINTE = perinte; - DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH2.MODE.bit.DATASIZE = datasize; - DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH2.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH2 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx2 = 1; - - EDIS; -} - -// -// StartDMACH2 - This function starts DMA Channel 2. -// -void StartDMACH2(void) -{ - EALLOW; - DmaRegs.CH2.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH3AddrConfig - DMA Channel 3 Address configuration -// -void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3BurstConfig - DMA Channel 3 burst size configuration -// -void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH3TransferConfig - DMA channel 3 transfer size configuration -// -void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH3WrapConfig - DMA Channel 3 wrap size configuration -// -void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH3ModeConfig - DMA Channel 3 mode configuration -// -void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; - DmaRegs.CH3.MODE.bit.PERINTSEL = 3; - DmaRegs.CH3.MODE.bit.PERINTE = perinte; - DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH3.MODE.bit.DATASIZE = datasize; - DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH3.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt flags and sync error flags - // - DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH3 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx3 = 1; - - EDIS; -} - -// -// StartDMACH3 - This function starts DMA Channel 3. -// -void StartDMACH3(void) -{ - EALLOW; - DmaRegs.CH3.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH4AddrConfig - DMA Channel 4 address configuration -// -void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4BurstConfig - DMA Channel 4 burst size configuration -// -void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH4TransferConfig - DMA channel 4 transfer size configuration -// -void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH4WrapConfig - DMA channel 4 wrap size configuration -// -void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH4ModeConfig - DMA Channel 4 mode configuration -// -void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; - DmaRegs.CH4.MODE.bit.PERINTSEL = 4; - DmaRegs.CH4.MODE.bit.PERINTE = perinte; - DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH4.MODE.bit.DATASIZE = datasize; - DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH4.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH4 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx4 = 1; - - EDIS; -} - -// -// StartDMACH4 - This function starts DMA Channel 4. -// -void StartDMACH4(void) -{ - EALLOW; - DmaRegs.CH4.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH5AddrConfig - DMA channel 5 address configuration -// -void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5BurstConfig - DMA Channel 5 burst size configuration -// -void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH5TransferConfig - DMA channel 5 transfer size configuration -// -void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH5WrapConfig - DMA Channel 5 wrap size configuration -// -void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH5ModeConfig - DMA Channel 5 mode configuration -// -void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; - DmaRegs.CH5.MODE.bit.PERINTSEL = 5; - DmaRegs.CH5.MODE.bit.PERINTE = perinte; - DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH5.MODE.bit.DATASIZE = datasize; - DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH5.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH5 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx5 = 1; - - EDIS; -} - -// -// StartDMACH5 - This function starts DMA Channel 5. -// -void StartDMACH5(void) -{ - EALLOW; - DmaRegs.CH5.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH6AddrConfig - DMA Channel 6 address configuration -// -void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer. - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6BurstConfig - DMA Channel 6 burst size configuration -// -void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH6TransferConfig - DMA channel 6 transfer size configuration -// -void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH6WrapConfig - DMA Channel 6 wrap size configuration -// -void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH6ModeConfig - DMA Channel 6 mode configuration -// -void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; - DmaRegs.CH6.MODE.bit.PERINTSEL = 6; - DmaRegs.CH6.MODE.bit.PERINTE = perinte; - DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH6.MODE.bit.DATASIZE = datasize; - DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH6.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH6 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx6 = 1; - - EDIS; -} - -// -// StartDMACH6 - This function starts DMA Channel 6. -// -void StartDMACH6(void) -{ - EALLOW; - DmaRegs.CH6.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit -// -void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit -// -void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit -// -void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit -// -void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; - // Point to beginning - // of destination - // buffer - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit -// -void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; - // Point to beginning - // of destination - // buffer - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit -// -void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; - // Point to beginning - // of source buffer - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c b/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c deleted file mode 100644 index 9f3573e..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_gpio.c +++ /dev/null @@ -1,441 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio.c -// -// TITLE: f28004x GPIO module support functions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" -#include "f28004x_examples.h" - -// -// Low-level functions for GPIO configuration -// - -// -// InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups -// enabled.Also resets CPU control to CPU1 and disables open drain -// and polarity inversion and sets the qualification to synchronous. -// Also unlocks all GPIOs. Only one CPU should call this function. -// -void -InitGpio() -{ - volatile Uint32 *gpioBaseAddr; - Uint16 regOffset; - - // - // Disable pin locks - // - EALLOW; - GpioCtrlRegs.GPALOCK.all = 0x00000000; - GpioCtrlRegs.GPBLOCK.all = 0x00000000; - GpioCtrlRegs.GPHLOCK.all = 0x00000000; - - // - // Fill all registers with zeros. Writing to each register separately - // for three GPIO modules would make this function *very* long. - // Fortunately, we'd be writing them all with zeros anyway, - // so this saves a lot of space. - // - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; - for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) - { - // - // Must avoid enabling pull-ups on all pins. GPyPUD is offset - // 0x0C in each register group of 0x40 words. Since this is a - // 32-bit pointer, the addresses must be divided by 2. - // - // Also, to avoid changing pin muxing of the emulator pins to regular - // GPIOs, skip GPBMUX1 (0x46) and GPBGMUX1 (0x60). - // - if ((regOffset % (0x40/2) != (0x0C/2)) && (regOffset != (0x46/2)) && - (regOffset != (0x60/2))) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - } - - gpioBaseAddr = (Uint32 *)&GpioDataRegs; - for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - - EDIS; -} - -// -// GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. -// The appropriate parameters can be found in the pinout spreadsheet. -// -void -GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *mux, *gmux, *csel; - Uint16 pin32, pin16, pin8; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pin8 = gpioNumber % 8; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Sanity check for valid cpu and peripheral values - // - if (cpu > GPIO_MUX_CPU1CLA || muxPosition > 0xF) - { - return; - } - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyCSEL1-4. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - mux = gpioBaseAddr + GPYMUX + pin32/16; - gmux = gpioBaseAddr + GPYGMUX + pin32/16; - csel = gpioBaseAddr + GPYCSEL + pin32/8; - - // - // Now for the actual function - // - EALLOW; - - // - // To change the muxing, set the peripheral mux to 0/GPIO first to avoid - // glitches, then change the group mux, then set the peripheral mux to - // its target value. Finally, set the CPU select. This procedure is - // described in the TRM. Unfortunately, since we don't know the pin in - // advance we can't hardcode a bitfield reference, so there's some tricky - // bit twiddling here. - // - *mux &= ~(0x3UL << (2*pin16)); - *gmux &= ~(0x3UL << (2*pin16)); - *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); - *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); - - *csel &= ~(0x3L << (4*pin8)); - *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); - - // - // WARNING: This code does not touch the analog mode select registers. - // - - EDIS; -} - -// -// GPIO_SetupPinOptions - Setup up the GPIO input/output options for the -// specified pin. The flags are a 16-bit mask produced by ORing together -// options. For input pins, the valid flags are: -// GPIO_PULLUP Enable pull-up -// GPIO_INVERT Enable input polarity inversion -// GPIO_SYNC Synchronize the input latch to PLLSYSCLK -// (default -- you don't need to specify this) -// GPIO_QUAL3 Use 3-sample qualification -// GPIO_QUAL6 Use 6-sample qualification -// GPIO_ASYNC Do not use synchronization or qualification -// (Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) -// -// For output pins, the valid flags are: -// GPIO_OPENDRAIN Output in open drain mode -// GPIO_PULLUP If open drain enabled, also enable the pull-up -// and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. -// -// With no flags, the default input state is synchronous with no -// pull-up or polarity inversion. The default output state is -// the standard digital output. -// -void -GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *dir, *pud, *inv, *odr, *qsel; - Uint32 pin32, pin16, pinMask, qual; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyQSEL1-2. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - dir = gpioBaseAddr + GPYDIR; - pud = gpioBaseAddr + GPYPUD; - inv = gpioBaseAddr + GPYINV; - odr = gpioBaseAddr + GPYODR; - qsel = gpioBaseAddr + GPYQSEL + pin32/16; - - EALLOW; - - // - // Set the data direction - // - *dir &= ~pinMask; - if (output == 1) - { - // - // Output, with optional open drain mode and pull-up - // - *dir |= pinMask; - - // - // Enable open drain if necessary - // - if (flags & GPIO_OPENDRAIN) - { - *odr |= pinMask; - } - else - { - *odr &= ~pinMask; - } - - // - // Enable pull-up if necessary. Open drain mode must be active. - // - if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - } - - else - { - // - // Input, with optional pull-up, qualification, and polarity inversion - // - *dir &= ~pinMask; - - // - // Enable pull-up if necessary - // - if (flags & GPIO_PULLUP) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - - // - // Invert polarity if necessary - // - if (flags & GPIO_INVERT) - { - *inv |= pinMask; - } - else - { - *inv &= ~pinMask; - } - } - - // - // Extract the qualification parameter and load it into the register. - // This is also needed for open drain outputs, so we might as well do it - // all the time. - // - qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; - *qsel &= ~(0x3L << (2 * pin16)); - if (qual != 0x0) - { - *qsel |= qual << (2 * pin16); - } - - EDIS; -} - -// -// GPIO_SetupLock - Enable or disable the GPIO register bit lock for the -// specified pin. The valid flags are: -// GPIO_UNLOCK Unlock the pin setup register bits for the specified pin -// GPIO_LOCK Lock the pin setup register bits for the specified pin -// -void -GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *lock; - Uint32 pin32, pinMask; - - pin32 = gpioNumber % 32; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - // Create pointers to the appropriate registers. This is a workaround - // for the way GPIO registers are defined. The standard definition - // in the header file makes it very easy to do named accesses of one - // register or bit, but hard to do arbitrary numerical accesses. It's - // easier to have an array of GPIO modules with identical registers, - // including arrays for multi-register groups like GPyQSEL1-2. But - // the header file doesn't define anything we can turn into an array, - // so manual pointer arithmetic is used instead. - // - lock = gpioBaseAddr + GPYLOCK; - - EALLOW; - - if(flags) - { - // - // Lock the pin - // - *lock |= pinMask; - } - - else - { - // - // Unlock the pin - // - *lock &= ~pinMask; - } - EDIS; -} - -// -// External interrupt setup -// -void -GPIO_SetupXINT1Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT4SELECT = gpioNumber; // Set XINT1 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT2Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT5SELECT = gpioNumber; // Set XINT2 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT3Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT6SELECT = gpioNumber; // Set XINT3 source to GPIO-pin - EDIS; -} -void -GPIO_SetupXINT4Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT13SELECT = gpioNumber; // Set XINT4 source to GPIO-pin - EDIS; -} - -void -GPIO_SetupXINT5Gpio(Uint16 gpioNumber) -{ - EALLOW; - InputXbarRegs.INPUT14SELECT = gpioNumber; // Set XINT5 source to GPIO-pin - EDIS; -} - -// -// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. -// Note that this returns the actual state of the pin, not the state of the -// output latch. -// -Uint16 -GPIO_ReadPin(Uint16 gpioNumber) -{ - volatile Uint32 *gpioDataReg; - Uint16 pinVal; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; - - return pinVal; -} - -// -// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. -// -void -GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) -{ - volatile Uint32 *gpioDataReg; - Uint32 pinMask; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinMask = 1UL << (gpioNumber % 32); - - if (outVal == 0) - { - gpioDataReg[GPYCLEAR] = pinMask; - } - - else - { - gpioDataReg[GPYSET] = pinMask; - } -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c b/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c deleted file mode 100644 index 624955d..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_piectrl.c +++ /dev/null @@ -1,124 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_piectrl.c -// -// TITLE: f28004x Device PIE Control Register Initialization Functions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // f28004x Headerfile Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -// -// InitPieCtrl - This function initializes the PIE control registers -// to a known state. -// -void -InitPieCtrl(void) -{ - // - // Disable Interrupts at the CPU level: - // - DINT; - - // - // Disable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 0; - - // - // Clear all PIEIER registers: - // - PieCtrlRegs.PIEIER1.all = 0; - PieCtrlRegs.PIEIER2.all = 0; - PieCtrlRegs.PIEIER3.all = 0; - PieCtrlRegs.PIEIER4.all = 0; - PieCtrlRegs.PIEIER5.all = 0; - PieCtrlRegs.PIEIER6.all = 0; - PieCtrlRegs.PIEIER7.all = 0; - PieCtrlRegs.PIEIER8.all = 0; - PieCtrlRegs.PIEIER9.all = 0; - PieCtrlRegs.PIEIER10.all = 0; - PieCtrlRegs.PIEIER11.all = 0; - PieCtrlRegs.PIEIER12.all = 0; - - // - // Clear all PIEIFR registers: - // - PieCtrlRegs.PIEIFR1.all = 0; - PieCtrlRegs.PIEIFR2.all = 0; - PieCtrlRegs.PIEIFR3.all = 0; - PieCtrlRegs.PIEIFR4.all = 0; - PieCtrlRegs.PIEIFR5.all = 0; - PieCtrlRegs.PIEIFR6.all = 0; - PieCtrlRegs.PIEIFR7.all = 0; - PieCtrlRegs.PIEIFR8.all = 0; - PieCtrlRegs.PIEIFR9.all = 0; - PieCtrlRegs.PIEIFR10.all = 0; - PieCtrlRegs.PIEIFR11.all = 0; - PieCtrlRegs.PIEIFR12.all = 0; -} - -// -// EnableInterrupts - This function enables the PIE module and CPU __interrupts -// -void -EnableInterrupts() -{ - // - // Enable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; - - // - // Enables PIE to drive a pulse into the CPU - // - PieCtrlRegs.PIEACK.all = 0xFFFF; - - // - // Enable Interrupts at the CPU level - // - EINT; -} - -// -// End of file. -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c b/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c deleted file mode 100644 index 467f60f..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_pievect.c +++ /dev/null @@ -1,315 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pievect.c -// -// TITLE: f28004x Device PIE Vector Initialization Functions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // f28004x Header File Include File -#include "f28004x_examples.h" // f28004x Examples Include File - -// -// Define PIE Vector Table: -// -const struct PIE_VECT_TABLE PieVectTableInit = { - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - TIMER1_ISR, // CPU Timer 1 Interrupt - TIMER2_ISR, // CPU Timer 2 Interrupt - DATALOG_ISR, // Datalogging Interrupt - RTOS_ISR, // RTOS Interrupt - EMU_ISR, // Emulation Interrupt - NMI_ISR, // Non-Maskable Interrupt - ILLEGAL_ISR, // Illegal Operation Trap - USER1_ISR, // User Defined Trap 1 - USER2_ISR, // User Defined Trap 2 - USER3_ISR, // User Defined Trap 3 - USER4_ISR, // User Defined Trap 4 - USER5_ISR, // User Defined Trap 5 - USER6_ISR, // User Defined Trap 6 - USER7_ISR, // User Defined Trap 7 - USER8_ISR, // User Defined Trap 8 - USER9_ISR, // User Defined Trap 9 - USER10_ISR, // User Defined Trap 10 - USER11_ISR, // User Defined Trap 11 - USER12_ISR, // User Defined Trap 12 - ADCA1_ISR, // 1.1 - ADCA Interrupt 1 - ADCB1_ISR, // 1.2 - ADCB Interrupt 1 - ADCC1_ISR, // 1.3 - ADCC Interrupt 1 - XINT1_ISR, // 1.4 - XINT1 Interrupt - XINT2_ISR, // 1.5 - XINT2 Interrupt - PIE_RESERVED_ISR, // 1.6 - Reserved - TIMER0_ISR, // 1.7 - Timer 0 Interrupt - WAKE_ISR, // 1.8 - Halt Wakeup Interrupt - EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt - EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt - EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt - EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt - EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt - EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt - EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt - EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt - EPWM1_ISR, // 3.1 - ePWM1 Interrupt - EPWM2_ISR, // 3.2 - ePWM2 Interrupt - EPWM3_ISR, // 3.3 - ePWM3 Interrupt - EPWM4_ISR, // 3.4 - ePWM4 Interrupt - EPWM5_ISR, // 3.5 - ePWM5 Interrupt - EPWM6_ISR, // 3.6 - ePWM6 Interrupt - EPWM7_ISR, // 3.7 - ePWM7 Interrupt - EPWM8_ISR, // 3.8 - ePWM8 Interrupt - ECAP1_ISR, // 4.1 - eCAP1 Interrupt - ECAP2_ISR, // 4.2 - eCAP2 Interrupt - ECAP3_ISR, // 4.3 - eCAP3 Interrupt - ECAP4_ISR, // 4.4 - eCAP4 Interrupt - ECAP5_ISR, // 4.5 - eCAP5 Interrupt - ECAP6_ISR, // 4.6 - eCAP6 Interrupt - ECAP7_ISR, // 4.7 - eCAP7 Interrupt - PIE_RESERVED_ISR, // 4.8 - Reserved - EQEP1_ISR, // 5.1 - eQEP1 Interrupt - EQEP2_ISR, // 5.2 - eQEP2 Interrupt - PIE_RESERVED_ISR, // 5.3 - Reserved - PIE_RESERVED_ISR, // 5.4 - Reserved - PIE_RESERVED_ISR, // 5.5 - Reserved - PIE_RESERVED_ISR, // 5.6 - Reserved - PIE_RESERVED_ISR, // 5.7 - Reserved - PIE_RESERVED_ISR, // 5.8 - Reserved - SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt - SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt - SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt - SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt - PIE_RESERVED_ISR, // 6.5 - Reserved - PIE_RESERVED_ISR, // 6.6 - Reserved - PIE_RESERVED_ISR, // 6.7 - Reserved - PIE_RESERVED_ISR, // 6.8 - Reserved - DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt - DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt - DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt - DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt - DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt - DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt - PIE_RESERVED_ISR, // 7.7 - Reserved - PIE_RESERVED_ISR, // 7.8 - Reserved - I2CA_ISR, // 8.1 - I2CA Interrupt 1 - I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 - PIE_RESERVED_ISR, // 8.3 - Reserved - PIE_RESERVED_ISR, // 8.4 - Reserved - PIE_RESERVED_ISR, // 8.5 - Reserved - PIE_RESERVED_ISR, // 8.6 - Reserved - PIE_RESERVED_ISR, // 8.7 - Reserved - PIE_RESERVED_ISR, // 8.8 - Reserved - SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt - SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt - SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt - SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt - CANA0_ISR, // 9.5 - CANA Interrupt 0 - CANA1_ISR, // 9.6 - CANA Interrupt 1 - CANB0_ISR, // 9.7 - CANB Interrupt 0 - CANB1_ISR, // 9.8 - CANB Interrupt 1 - ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt - ADCA2_ISR, // 10.2 - ADCA Interrupt 2 - ADCA3_ISR, // 10.3 - ADCA Interrupt 3 - ADCA4_ISR, // 10.4 - ADCA Interrupt 4 - ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt - ADCB2_ISR, // 10.6 - ADCB Interrupt 2 - ADCB3_ISR, // 10.7 - ADCB Interrupt 3 - ADCB4_ISR, // 10.8 - ADCB Interrupt 4 - CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 - CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 - CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 - CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 - CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 - CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 - CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 - CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 - XINT3_ISR, // 12.1 - XINT3 Interrupt - XINT4_ISR, // 12.2 - XINT4 Interrupt - XINT5_ISR, // 12.3 - XINT5 Interrupt - PIE_RESERVED_ISR, // 12.4 - Reserved - PIE_RESERVED_ISR, // 12.5 - Reserved - PIE_RESERVED_ISR, // 12.6 - Reserved - FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt - FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt - PIE_RESERVED_ISR, // 1.9 - Reserved - PIE_RESERVED_ISR, // 1.10 - Reserved - PIE_RESERVED_ISR, // 1.11 - Reserved - PIE_RESERVED_ISR, // 1.12 - Reserved - PIE_RESERVED_ISR, // 1.13 - Reserved - PIE_RESERVED_ISR, // 1.14 - Reserved - PIE_RESERVED_ISR, // 1.15 - Reserved - PIE_RESERVED_ISR, // 1.16 - Reserved - PIE_RESERVED_ISR, // 2.9 - Reserved - PIE_RESERVED_ISR, // 2.10 - Reserved - PIE_RESERVED_ISR, // 2.11 - Reserved - PIE_RESERVED_ISR, // 2.12 - Reserved - PIE_RESERVED_ISR, // 2.13 - Reserved - PIE_RESERVED_ISR, // 2.14 - Reserved - PIE_RESERVED_ISR, // 2.15 - Reserved - PIE_RESERVED_ISR, // 2.16 - Reserved - PIE_RESERVED_ISR, // 3.9 - Reserved - PIE_RESERVED_ISR, // 3.10 - Reserved - PIE_RESERVED_ISR, // 3.11 - Reserved - PIE_RESERVED_ISR, // 3.12 - Reserved - PIE_RESERVED_ISR, // 3.13 - Reserved - PIE_RESERVED_ISR, // 3.14 - Reserved - PIE_RESERVED_ISR, // 3.15 - Reserved - PIE_RESERVED_ISR, // 3.16 - Reserved - PIE_RESERVED_ISR, // 4.9 - Reserved - PIE_RESERVED_ISR, // 4.10 - Reserved - PIE_RESERVED_ISR, // 4.11 - Reserved - PIE_RESERVED_ISR, // 4.12 - Reserved - PIE_RESERVED_ISR, // 4.13 - Reserved - ECAP6_2_ISR, // 4.14 - eCAP6_2 Interrupt - ECAP7_2_ISR, // 4.15 - eCAP7_2 Interrupt - PIE_RESERVED_ISR, // 4.16 - Reserved - SD1_ISR, // 5.9 - SD1 Interrupt - PIE_RESERVED_ISR, // 5.10 - Reserved - PIE_RESERVED_ISR, // 5.11 - Reserved - PIE_RESERVED_ISR, // 5.12 - Reserved - SD1DR1_ISR, // 5.13 - SD1DR1 Interrupt - SD1DR2_ISR, // 5.14 - SD1DR2 Interrupt - SD1DR3_ISR, // 5.15 - SD1DR3 Interrupt - SD1DR4_ISR, // 5.16 - SD1DR4 Interrupt - PIE_RESERVED_ISR, // 6.9 - Reserved - PIE_RESERVED_ISR, // 6.10 - Reserved - PIE_RESERVED_ISR, // 6.11 - Reserved - PIE_RESERVED_ISR, // 6.12 - Reserved - PIE_RESERVED_ISR, // 6.13 - Reserved - PIE_RESERVED_ISR, // 6.14 - Reserved - PIE_RESERVED_ISR, // 6.15 - Reserved - PIE_RESERVED_ISR, // 6.16 - Reserved - PIE_RESERVED_ISR, // 7.9 - Reserved - PIE_RESERVED_ISR, // 7.10 - Reserved - FSITXA1_ISR, // 7.11 - FSITXA1 Interrupt - FSITXA2_ISR, // 7.12 - FSITXA2 Interrupt - FSIRXA1_ISR, // 7.13 - FSIRXA1 Interrupt - FSIRXA2_ISR, // 7.14 - FSIRXA2 Interrupt - CLA1PROMCRC_ISR, // 7.15 - CLA1PROMCRC Interrupt - PIE_RESERVED_ISR, // 7.16 - Reserved - LINA_0_ISR, // 8.9 - LINA Interrupt0 - LINA_1_ISR, // 8.10 - LINA Interrupt1 - PIE_RESERVED_ISR, // 8.11 - Reserved - PIE_RESERVED_ISR, // 8.12 - Reserved - PMBUSA_ISR, // 8.13 - PMBUSA Interrupt - PIE_RESERVED_ISR, // 8.14 - Reserved - PIE_RESERVED_ISR, // 8.15 - Reserved - PIE_RESERVED_ISR, // 8.16 - Reserved - PIE_RESERVED_ISR, // 9.9 - Reserved - PIE_RESERVED_ISR, // 9.10 - Reserved - PIE_RESERVED_ISR, // 9.11 - Reserved - PIE_RESERVED_ISR, // 9.12 - Reserved - PIE_RESERVED_ISR, // 9.13 - Reserved - PIE_RESERVED_ISR, // 9.14 - Reserved - PIE_RESERVED_ISR, // 9.15 - Reserved - PIE_RESERVED_ISR, // 9.16 - Reserved - ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt - ADCC2_ISR, // 10.10 - ADCC Interrupt 2 - ADCC3_ISR, // 10.11 - ADCC Interrupt 3 - ADCC4_ISR, // 10.12 - ADCC Interrupt 4 - PIE_RESERVED_ISR, // 10.13 - Reserved - PIE_RESERVED_ISR, // 10.14 - Reserved - PIE_RESERVED_ISR, // 10.15 - Reserved - PIE_RESERVED_ISR, // 10.16 - Reserved - PIE_RESERVED_ISR, // 11.9 - Reserved - PIE_RESERVED_ISR, // 11.10 - Reserved - PIE_RESERVED_ISR, // 11.11 - Reserved - PIE_RESERVED_ISR, // 11.12 - Reserved - PIE_RESERVED_ISR, // 11.13 - Reserved - PIE_RESERVED_ISR, // 11.14 - Reserved - PIE_RESERVED_ISR, // 11.15 - Reserved - PIE_RESERVED_ISR, // 11.16 - Reserved - PIE_RESERVED_ISR, // 12.9 - Reserved - RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt - FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt - RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt - SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt - PIE_RESERVED_ISR, // 12.14 - Reserved - CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt - CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt -}; - -// -// InitPieVectTable - This function initializes the PIE vector table to a known -// state. This function must be executed after boot time. -// -void -InitPieVectTable(void) -{ - Uint16 i; - Uint32 *Source = (void *) &PieVectTableInit; - Uint32 *Dest = (void *) &PieVectTable; - - // - // Do not write over first 3 32-bit locations (these locations are - // initialized by Boot ROM with boot variables) - // - Source = Source + 3; - Dest = Dest + 3; - - EALLOW; - - for(i = 0; i < 221; i++) - { - *Dest++ = *Source++; - } - - EDIS; - - // - // Enable the PIE Vector Table - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; -} - -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c b/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c deleted file mode 100644 index 75b951c..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_spi.c +++ /dev/null @@ -1,177 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_Spi.c -// -// TITLE: f28004x SPI Initialization & Support Functions. -// -//############################################################################# -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File - -// -// Calculate BRR: 7-bit baud rate register value -// SPI CLK freq = 500 kHz -// LSPCLK freq = CPU freq / 4 (by default) -// BRR = (LSPCLK freq / SPI CLK freq) - 1 -// -#if CPU_FRQ_100MHZ -#define SPI_BRR ((100E6 / 4) / 500E3) - 1 -#endif - -// -// InitSPI - This function initializes the SPI to a known state -// -void InitSpi(void) -{ - // - // Initialize SPI-A - // - // Set reset low before configuration changes - // Clock polarity (0 == rising, 1 == falling) - // 16-bit character - // Enable loop-back - // - SpiaRegs.SPICCR.bit.SPISWRESET = 0; - SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; - SpiaRegs.SPICCR.bit.SPICHAR = (16-1); - SpiaRegs.SPICCR.bit.SPILBK = 1; - - // - // Enable master (0 == slave, 1 == master) - // Enable transmission (Talk) - // Clock phase (0 == normal, 1 == delayed) - // SPI interrupts are disabled - // - SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; - SpiaRegs.SPICTL.bit.TALK = 1; - SpiaRegs.SPICTL.bit.CLK_PHASE = 0; - SpiaRegs.SPICTL.bit.SPIINTENA = 0; - - // - // Set the baud rate - // - SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; - - // - // Set FREE bit - // Halting on a breakpoint will not halt the SPI - // - SpiaRegs.SPIPRI.bit.FREE = 1; - - // - // Release the SPI from reset - // - SpiaRegs.SPICCR.bit.SPISWRESET = 1; -} - -// -// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. -// Each GPIO pin can be configured as a GPIO pin or up to 3 -// different peripheral functional pins. By default all pins come -// up as GPIO inputs after reset. -// -// Caution: -// For each SPI peripheral -// Only one GPIO pin should be enabled for SPISOMO operation. -// Only one GPIO pin should be enabled for SPISOMI operation. -// Only one GPIO pin should be enabled for SPICLK operation. -// Only one GPIO pin should be enabled for SPISTE operation. -// Comment out other unwanted lines. -// -void InitSpiGpio() -{ - InitSpiaGpio(); -} - -// -// InitSpiaGpio - Initialize SPIA GPIOs -// -void InitSpiaGpio() -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) - // GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) - // GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) - GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) - // GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) - // GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) - - // - //Configure SPI-A pins using GPIO regs - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA - // GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA - GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA - // GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA - GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA - GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA - - EDIS; -} - -// -// End of file -// diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c b/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c deleted file mode 100644 index 542c0cd..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_sysctrl.c +++ /dev/null @@ -1,876 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl.c -// -// TITLE: f28004x Device System Control Initialization & Support Functions. -// -// DESCRIPTION: Example initialization of system resources. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "f28004x_device.h" // Headerfile Include File -#include "f28004x_examples.h" // Examples Include File -#ifdef __cplusplus -using std::memcpy; -#endif - -// -// Functions that will be run from RAM need to be assigned to -// a different section. This section will then be mapped to a load and -// run address using the linker cmd file. -// -// *IMPORTANT* -// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM FLASH -// TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM THROWING -// AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. -// -#ifndef __cplusplus -#pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); -#pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); -#endif - -// -// The following values are used to validate PLL Frequency using DCC -// -#define PLL_RETRIES 100 -#define PLL_LOCK_TIMEOUT 2000 -#define DCC_COUNTER0_WINDOW 100 - -// -// InitSysCtrl - -// -void -InitSysCtrl(void) -{ - // - // Disable the watchdog - // - DisableDog(); - -#ifdef _FLASH - // - // Copy time critical code and Flash setup code to RAM - // This includes the following functions: InitFlash(); - // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart - // symbols are created by the linker. Refer to the device .cmd file. - // - memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); -#endif - - // - // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) - // - InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2); - - // - // Call Flash Initialization to setup flash waitstates - // This function must reside in RAM - // - InitFlash(); - - // - // Turn on all peripherals - // - InitPeripheralClocks(); -} - -// -// InitPeripheralClocks - This function initializes the clocks for the -// peripherals. Note: In order to reduce power consumption, turn off the -// clocks to any peripheral that is not specified for your part-number or is -// not used in the application -// -void -InitPeripheralClocks() -{ - EALLOW; - - CpuSysRegs.PCLKCR0.bit.CLA1 = 1; - CpuSysRegs.PCLKCR0.bit.DMA = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; - CpuSysRegs.PCLKCR0.bit.HRPWM = 1; - CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; - - CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; - - CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP7 = 1; - - CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; - CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; - - CpuSysRegs.PCLKCR6.bit.SD1 = 1; - - CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - CpuSysRegs.PCLKCR7.bit.SCI_B = 1; - - CpuSysRegs.PCLKCR8.bit.SPI_A = 1; - CpuSysRegs.PCLKCR8.bit.SPI_B = 1; - - CpuSysRegs.PCLKCR9.bit.I2C_A = 1; - - CpuSysRegs.PCLKCR10.bit.CAN_A = 1; - CpuSysRegs.PCLKCR10.bit.CAN_B = 1; - - CpuSysRegs.PCLKCR13.bit.ADC_A = 1; - CpuSysRegs.PCLKCR13.bit.ADC_B = 1; - CpuSysRegs.PCLKCR13.bit.ADC_C = 1; - - CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; - - CpuSysRegs.PCLKCR15.bit.PGA1 = 1; - CpuSysRegs.PCLKCR15.bit.PGA2 = 1; - CpuSysRegs.PCLKCR15.bit.PGA3 = 1; - CpuSysRegs.PCLKCR15.bit.PGA4 = 1; - CpuSysRegs.PCLKCR15.bit.PGA5 = 1; - CpuSysRegs.PCLKCR15.bit.PGA6 = 1; - CpuSysRegs.PCLKCR15.bit.PGA7 = 1; - - CpuSysRegs.PCLKCR16.bit.DAC_A = 1; - CpuSysRegs.PCLKCR16.bit.DAC_B = 1; - - CpuSysRegs.PCLKCR19.bit.LIN_A = 1; - - CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1; - - CpuSysRegs.PCLKCR21.bit.DCC_0 = 1; - - EDIS; -} - -// -// DisablePeripheralClocks - -// -void -DisablePeripheralClocks() -{ - EALLOW; - - CpuSysRegs.PCLKCR0.all = 0; - CpuSysRegs.PCLKCR2.all = 0; - CpuSysRegs.PCLKCR3.all = 0; - CpuSysRegs.PCLKCR4.all = 0; - CpuSysRegs.PCLKCR6.all = 0; - CpuSysRegs.PCLKCR7.all = 0; - CpuSysRegs.PCLKCR8.all = 0; - CpuSysRegs.PCLKCR9.all = 0; - CpuSysRegs.PCLKCR10.all = 0; - CpuSysRegs.PCLKCR13.all = 0; - CpuSysRegs.PCLKCR14.all = 0; - CpuSysRegs.PCLKCR15.all = 0; - CpuSysRegs.PCLKCR16.all = 0; - CpuSysRegs.PCLKCR19.all = 0; - CpuSysRegs.PCLKCR20.all = 0; - CpuSysRegs.PCLKCR21.all = 0; - - EDIS; -} - -// -// InitFlash - This function initializes the Flash Control registers -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -#ifdef __cplusplus -#pragma CODE_SECTION(".TI.ramfunc"); -#endif -void -InitFlash(void) -{ - EALLOW; - - // - // At reset bank and pump are in sleep - // A Flash access will power up the bank and pump automatically - // After a Flash access, bank and pump go to low power mode (configurable - // in FBFALLBACK/FPAC1 registers)- if there is no further access to flash - // Power up Flash bank and pump and this also sets the fall back mode of - // flash and pump as active - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0x3; - - // - // Disable Cache and prefetch mechanism before changing wait states - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; - - // - // Set waitstates according to frequency - // CAUTION - // Minimum waitstates required for the flash operating - // at a given CPU rate must be characterized by TI. - // Refer to the datasheet for the latest information. - // -#if CPU_FRQ_100MHZ - if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x0) || - (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x2) || - (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x3)) - { - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x5; - } - else - { - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x4; - } -#endif - - // - // Enable Cache and prefetch mechanism to improve performance - // of code executed from Flash. - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; - - // - // At reset, ECC is enabled. If it is disabled by application software - // and if application again wants to enable ECC - // - Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; - - EDIS; - - // - // Force a pipeline flush to ensure that the write to - // the last register configured occurs before returning. - // - __asm(" RPT #7 || NOP"); -} - -// -// FlashOff - This function powers down the flash -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results. -// Note: a flash access after the flash pump and banks are powered down will -// wake the pump and bank -// -#ifdef __cplusplus -#pragma CODE_SECTION(".TI.ramfunc"); -#endif -void -FlashOff(void) -{ - EALLOW; - - // - // Configure the fallback power mode as sleep - // - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0; - - // - // Configure the fallback power mode as sleep - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; - - EDIS; -} - -// -// ServiceDog - This function resets the watchdog timer. -// Enable this function for using ServiceDog in the application -// -void -ServiceDog(void) -{ - EALLOW; - WdRegs.WDKEY.bit.WDKEY = 0x0055; - WdRegs.WDKEY.bit.WDKEY = 0x00AA; - EDIS; -} - -// -// DisableDog - This function disables the watchdog timer. -// -void -DisableDog(void) -{ - volatile Uint16 temp; - EALLOW; - - // - // Grab the clock config so we don't clobber it - // - temp = WdRegs.WDCR.all & 0x0007; - WdRegs.WDCR.all = 0x0068 | temp; - EDIS; -} - -// -// InitPll - This function initializes the PLL registers. -// -// Note: This function uses the DCC to check that the PLLRAWCLK is running at -// the expected rate. If you are using the DCC, you must back up its -// configuration before calling this function and restore it afterward. -// -void -InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) -{ - Uint32 timeout, retries, temp_syspllmult, pllLockStatus; - bool status; - - if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && - (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE) && - (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && - (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && - (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) - { - // - // Everything is set as required, so just return - // - return; - } - - if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) || - (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE)) - { - switch (clock_source) - { - case INT_OSC1: - SysIntOsc1Sel(); - break; - - case INT_OSC2: - SysIntOsc2Sel(); - break; - - case XTAL_OSC: - SysXtalOscSel(); - break; - - case XTAL_OSC_SE: - SysXtalOscSESel(); - break; - } - } - - EALLOW; - - // - // First modify the PLL multipliers - // - if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || - fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) - { - // - // Bypass PLL and set dividers to /1 - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; - - // - // Evaluate PLL multipliers - // - temp_syspllmult = ((fmult << 8U) | imult); - - // - // Loop to retry locking the PLL should the DCC module indicate - // that it was not successful. - // - for(retries = 0; (retries < PLL_RETRIES); retries++) - { - // - // Bypass PLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - - // - // Program PLL multipliers - // - ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult; - - // - // Enable SYSPLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; - - timeout = PLL_LOCK_TIMEOUT; - pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; - - // - // Wait for the SYSPLL lock - // - while((pllLockStatus != 1) && (timeout != 0U)) - { - pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS; - timeout--; - } - - EDIS; - - status = IsPLLValid(clock_source, imult, fmult); - - // - // Check DCC Status, if no error break the loop - // - if(status) - { - break; - } - } - } - else - { - status = true; - } - - if(status) - { - EALLOW; - // - // Set divider to produce slower output frequency to limit current increase - // - if(divsel != PLLCLK_BY_126) - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; - } - else - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - } - - // - // Enable PLLSYSCLK is fed from system PLL clock - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; - - // - // Small 100 cycle delay - // - asm(" RPT #100 || NOP"); - - // - // Set the divider to user value - // - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - EDIS; - } -} - -// -// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with -// current password for the DSP. -// -Uint16 -CsmUnlock() -{ - // - // Write to the key registers to unlock the device. The 0x0FFFFFFFF's - // are dummmy passwords. User should replace them with the correct password - // for the DSP. - // Note: F28004x has default password keys which are not all 0xFFFFFFFF. - // See DCSM chapter of Technical Reference Manual for default passwords. - EALLOW; - - DcsmBank0Z1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; - DcsmBank0Z1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; - - DcsmBank0Z2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; - DcsmBank0Z2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; - EDIS; - - return 0; -} - -// -// SysIntOsc1Sel - This function switches to Internal Oscillator 1 and turns -// off all other clock sources to minimize power consumption -// -void -SysIntOsc1Sel (void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 - ClkCfgRegs.XTALCR.bit.OSCOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// SysIntOsc2Sel - This function switches to Internal oscillator 2 from -// External Oscillator and turns off all other clock sources to minimize -// power consumption -// NOTE: If there is no external clock connection, when switching from -// INTOSC1 to INTOSC2, EXTOSC and XLCKIN must be turned OFF prior -// to switching to internal oscillator 1 -// -void -SysIntOsc2Sel (void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 - ClkCfgRegs.XTALCR.bit.OSCOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate -// four times. -// -static void -PollX1Counter(void) -{ - Uint16 loopCount = 0; - - // - // Delay for 1 ms while the XTAL powers up - // - // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles - // - F28x_usDelay(2000); - - // - // Clear and saturate X1CNT 4 times to guarantee operation - // - do - { - // - // Keep clearing the counter until it is no longer saturated - // - while(ClkCfgRegs.X1CNT.all > 0x1FF) - { - ClkCfgRegs.X1CNT.bit.CLR = 1; - } - - // - // Wait for the X1 clock to saturate - // - while(ClkCfgRegs.X1CNT.all != 0x3FFU) - { - ; - } - - // - // Increment the counter - // - loopCount++; - }while(loopCount < 4); -} - -// -// SysXtalOscSel - This function switches to External CRYSTAL oscillator and -// turns off all other clock sources to minimize power consumption. This option -// may not be available on all device packages -// -void -SysXtalOscSel (void) -{ - EALLOW; - ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC - ClkCfgRegs.XTALCR.bit.SE = 0; // Select crystal mode - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTAL as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - - // - // If a missing clock failure was detected, try waiting for the X1 counter - // to saturate again. Consider modifying this code to add a 10ms timeout. - // - while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) - { - EALLOW; - ClkCfgRegs.MCDCR.bit.MCLKCLR = 1; - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTAL as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - } -} - -// -// SysXtalOscSESel - This function switches to external oscillator in -// single-ended mode and turns off all other clock sources to minimize power -// consumption. This option may not be available on all device packages -// -void -SysXtalOscSESel (void) -{ - EALLOW; - ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Turn on XTALOSC - ClkCfgRegs.XTALCR.bit.SE = 1; // Select single-ended mode - EDIS; - - // - // Wait for the X1 clock to saturate - // - PollX1Counter(); - - // - // Select XTALOSC as the oscillator source - // - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; - EDIS; - - // - // If missing clock detected, there is something wrong with the oscillator - // module. - // - if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0) - { - ESTOP0; - } -} - -// -// IDLE - Enter IDLE mode -// -void -IDLE() -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; - EDIS; - asm(" IDLE"); -} - -// -// HALT - Enter HALT mode -// -void -HALT() -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - EDIS; - asm(" IDLE"); -} - -//***************************************************************************** -// -// SysCtl_isPLLValid() -// -//***************************************************************************** -bool -IsPLLValid(Uint16 oscSource, Uint16 imult, Uint16 fmult) -{ - Uint32 dccCounterSeed0, dccCounterSeed1, dccValidSeed0; - - // - // Setting Counter0 & Valid Seed Value with +/-2% tolerance - // - dccCounterSeed0 = DCC_COUNTER0_WINDOW - 2U; - dccValidSeed0 = 4U; - - // - // Multiplying Counter-0 window with PLL Integer Multiplier - // - dccCounterSeed1 = DCC_COUNTER0_WINDOW * imult; - - // - // Multiplying Counter-0 window with PLL Fractional Multiplier - // - switch(fmult) - { - case FMULT_0pt25: - // - // FMULT * CNTR0 Window = 0.25 * 100 = 25, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 25U; - break; - case FMULT_0pt5: - // - // FMULT * CNTR0 Window = 0.5 * 100 = 50, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 50U; - break; - case FMULT_0pt75: - // - // FMULT * CNTR0 Window = 0.75 * 100 = 75, gets added to cntr0 - // seed value - // - dccCounterSeed1 = dccCounterSeed1 + 75U; - break; - default: - // - // No fractional multiplier - // - dccCounterSeed1 = dccCounterSeed1; - break; - } - - // - // Enable Peripheral Clock Domain PCLKCR21 for DCC - // - EALLOW; - CpuSysRegs.PCLKCR21.bit.DCC_0 = 1; - - // - // Clear Error & Done Flag - // - Dcc0Regs.DCCSTATUS.bit.ERR = 1; - Dcc0Regs.DCCSTATUS.bit.DONE = 1; - - // - // Disable DCC - // - Dcc0Regs.DCCGCTRL.bit.DCCENA = 0x5; - - // - // Disable Error Signal - // - Dcc0Regs.DCCGCTRL.bit.ERRENA = 0x5; - - // - // Disable Done Signal - // - Dcc0Regs.DCCGCTRL.bit.DONEENA = 0x5; - - // - // Configure Clock Source0 to whatever is set as a clock source for PLL - // - switch(oscSource) - { - case INT_OSC1: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 1; // Clk Src0 = INTOSC1 - break; - - case INT_OSC2: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 2; // Clk Src0 = INTOSC2 - break; - - case XTAL_OSC: - case XTAL_OSC_SE: - Dcc0Regs.DCCCLKSRC0.bit.CLKSRC0 = 0; // Clk Src0 = XTAL - break; - } - - // - // Configure Clock Source1 to PLL - // - Dcc0Regs.DCCCLKSRC1.bit.KEY = 0xA; // Clk Src1 Key to enable clock source selection for count1 - Dcc0Regs.DCCCLKSRC1.bit.CLKSRC1 = 0; // Clk Src1 = PLL - - // - // Configure COUNTER-0, COUNTER-1 & Valid Window - // - Dcc0Regs.DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value - Dcc0Regs.DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0; // Loaded Valid Value - Dcc0Regs.DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value - - // - // Enable Single Shot Mode - // - Dcc0Regs.DCCGCTRL.bit.SINGLESHOT = 0xA; - - // - // Enable Error Signal - // - Dcc0Regs.DCCGCTRL.bit.ERRENA = 0xA; - - // - // Enable Done Signal - // - Dcc0Regs.DCCGCTRL.bit.DONEENA = 0xA; - - // - // Enable DCC to start counting - // - Dcc0Regs.DCCGCTRL.bit.DCCENA = 0xA; - EDIS; - - // - // Wait until Error or Done Flag is generated - // - while((Dcc0Regs.DCCSTATUS.all & 3) == 0) - { - } - - // - // Returns true if DCC completes without error - // - return((Dcc0Regs.DCCSTATUS.all & 3) == 2); - -} -// -// End of File -// - diff --git a/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm b/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm deleted file mode 100644 index b46339d..0000000 --- a/els-f280049c/device_support_f28004x/common/source/f28004x_usdelay.asm +++ /dev/null @@ -1,92 +0,0 @@ -;;############################################################################# -;; -;; FILE: f28004x_usdelay.asm -;; -;; TITLE: Simple Delay Function -;; -;; DESCRIPTION: -;; -;; This is a simple delay function that can be used to insert a specified -;; delay into code. -;; This function is only accurate if executed from internal zero-waitstate -;; SARAM. If it is executed from waitstate memory then the delay will be -;; longer then specified. -;; To use this function: -;; 1 - update the CPU clock speed in the f28004x_examples.h -;; file. -;; 2 - Call this function by using the DELAY_US(A) macro -;; that is defined in the f28004x_device.h file. This macro -;; will convert the number of microseconds specified -;; into a loop count for use with this function. -;; This count will be based on the CPU frequency you specify. -;; 3 - For the most accurate delay -;; - Execute this function in 0 waitstate RAM. -;; - Disable interrupts before calling the function -;; If you do not disable interrupts, then think of -;; this as an "at least" delay function as the actual -;; delay may be longer. -;; The C assembly call from the DELAY_US(time) macro will -;; look as follows: -;; extern void Delay(long LoopCount); -;; MOV AL,#LowLoopCount -;; MOV AH,#HighLoopCount -;; LCR _Delay -;; Or as follows (if count is less then 16-bits): -;; MOV ACC,#LoopCount -;; LCR _Delay -;;############################################################################# -;; $TI Release: F28004x Support Library v1.05.00.00 $ -;; $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -;; $Copyright: -;// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;;############################################################################# - - .def _F28x_usDelay - .sect ".TI.ramfunc" - - .global __F28x_usDelay -_F28x_usDelay: - SUB ACC,#1 - BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 - LRETR - -;There is a 9/10 cycle overhead and each loop -;takes five cycles. The LoopCount is given by -;the following formula: -; DELAY_CPU_CYCLES = 9 + 5*LoopCount -; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 -; The macro DELAY_US(A) performs this calculation for you - -;;############################################################################# -;; End of file -;;############################################################################# - diff --git a/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd b/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd deleted file mode 100644 index 31cd63d..0000000 --- a/els-f280049c/device_support_f28004x/headers/cmd/f28004x_headers_nonbios.cmd +++ /dev/null @@ -1,303 +0,0 @@ -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - - ANALOG_SUBSYS : origin = 0x05D700, length = 0x000100 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000080 /* CLA registers */ - - CLAPROMCRC : origin = 0x0061C0, length = 0x000020 - - CLB_XBAR : origin = 0x007A40, length = 0x000040 - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - - DCC0 : origin = 0x05E700, length = 0x000040 - - DCSM_BANK0_Z1 : origin = 0x05F000, length = 0x000030 - DCSM_BANK0_Z2 : origin = 0x05F040, length = 0x000030 - DCSM_BANK1_Z1 : origin = 0x05F100, length = 0x000030 - DCSM_BANK1_Z2 : origin = 0x05F140, length = 0x000030 - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - - DMA : origin = 0x001000, length = 0x000200 - - ECAP1 : origin = 0x005200, length = 0x000040 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005240, length = 0x000040 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005280, length = 0x000040 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x0052C0, length = 0x000040 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005300, length = 0x000040 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x005340, length = 0x000040 /* Enhanced Capture 6 registers */ - ECAP7 : origin = 0x005380, length = 0x000040 /* Enhanced Capture 7 registers */ - - PGA1 : origin = 0x005B00, length = 0x000010 - PGA2 : origin = 0x005B10, length = 0x000010 - PGA3 : origin = 0x005B20, length = 0x000010 - PGA4 : origin = 0x005B30, length = 0x000010 - PGA5 : origin = 0x005B40, length = 0x000010 - PGA6 : origin = 0x005B50, length = 0x000010 - PGA7 : origin = 0x005B60, length = 0x000010 - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - - EPWM_XBAR : origin = 0x007A00, length = 0x000040 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - FSITXA : origin = 0x006600, length = 0x000080 - FSIRXA : origin = 0x006680, length = 0x000080 - - GPIOCTRL : origin = 0x007C00, length = 0x000200 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000040 /* GPIO data registers */ - - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - - INPUT_XBAR : origin = 0x007900, length = 0x000020 - - LINA : origin = 0x006A00, length = 0x000100 - LINB : origin = 0x006B00, length = 0x000100 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - - PMBUSA : origin = 0x006400, length = 0x000020 - - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - - WD : origin = 0x007000, length = 0x000040 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - DEV_CFG : origin = 0x05D000, length = 0x000180 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - PERIPH_AC : origin = 0x05D500, length = 0x000200 - - ERAD_GLOBAL : origin = 0x05E800, length = 0x000013 - ERAD_HWBP1 : origin = 0x05E900, length = 0x000008 - ERAD_HWBP2 : origin = 0x05E908, length = 0x000008 - ERAD_HWBP3 : origin = 0x05E910, length = 0x000008 - ERAD_HWBP4 : origin = 0x05E918, length = 0x000008 - ERAD_HWBP5 : origin = 0x05E920, length = 0x000008 - ERAD_HWBP6 : origin = 0x05E928, length = 0x000008 - ERAD_HWBP7 : origin = 0x05E930, length = 0x000008 - ERAD_HWBP8 : origin = 0x05E938, length = 0x000008 - ERAD_CTR1 : origin = 0x05E980, length = 0x000010 - ERAD_CTR2 : origin = 0x05E990, length = 0x000010 - ERAD_CTR3 : origin = 0x05E9A0, length = 0x000010 - ERAD_CTR4 : origin = 0x05E9B0, length = 0x000010 - - XBAR : origin = 0x007920, length = 0x000020 - SYNC_SOC : origin = 0x007940, length = 0x000010 - - XINT : origin = 0x007070, length = 0x000010 -} - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile - GROUP - { - EmuKeyVar - EmuBModeVar - FlashCallbackVar - FlashScalingVar - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - - AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - ClaPromCrc0RegsFile : > CLAPROMCRC, PAGE = 1 - - ClbXbarRegsFile : > CLB_XBAR, PAGE = 1 - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - - Dcc0RegsFile : > DCC0 PAGE = 1 - - DcsmBank0Z1RegsFile : > DCSM_BANK0_Z1, PAGE = 1 - DcsmBank0Z2RegsFile : > DCSM_BANK0_Z2, PAGE = 1 - DcsmBank1Z1RegsFile : > DCSM_BANK1_Z1, PAGE = 1 - DcsmBank1Z2RegsFile : > DCSM_BANK1_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA, PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - ECap7RegsFile : > ECAP7, PAGE = 1 - - Pga1RegsFile : > PGA1, PAGE = 1 - Pga2RegsFile : > PGA2, PAGE = 1 - Pga3RegsFile : > PGA3, PAGE = 1 - Pga4RegsFile : > PGA4, PAGE = 1 - Pga5RegsFile : > PGA5, PAGE = 1 - Pga6RegsFile : > PGA6, PAGE = 1 - Pga7RegsFile : > PGA7, PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - - EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - - EnhancedDebugGlobalRegsFile : > ERAD_GLOBAL, PAGE = 1 - EnhancedDebugHWBP1RegsFile : > ERAD_HWBP1, PAGE = 1 - EnhancedDebugHWBP2RegsFile : > ERAD_HWBP2, PAGE = 1 - EnhancedDebugHWBP3RegsFile : > ERAD_HWBP3, PAGE = 1 - EnhancedDebugHWBP4RegsFile : > ERAD_HWBP4, PAGE = 1 - EnhancedDebugHWBP5RegsFile : > ERAD_HWBP5, PAGE = 1 - EnhancedDebugHWBP6RegsFile : > ERAD_HWBP6, PAGE = 1 - EnhancedDebugHWBP7RegsFile : > ERAD_HWBP7, PAGE = 1 - EnhancedDebugHWBP8RegsFile : > ERAD_HWBP8, PAGE = 1 - EnhancedDebugCounter1RegsFile : > ERAD_CTR1, PAGE = 1 - EnhancedDebugCounter2RegsFile : > ERAD_CTR2, PAGE = 1 - EnhancedDebugCounter3RegsFile : > ERAD_CTR3, PAGE = 1 - EnhancedDebugCounter4RegsFile : > ERAD_CTR4, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - FsiTxaRegsFile : > FSITXA PAGE = 1 - FsiRxaRegsFile : > FSIRXA PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - I2caRegsFile : > I2CA, PAGE = 1 - - InputXbarRegsFile : > INPUT_XBAR PAGE = 1 - XbarRegsFile : > XBAR PAGE = 1 - - LinaRegsFile : > LINA, PAGE = 1 - LinbRegsFile : > LINB, PAGE = 1 - - MemCfgRegsFile : > MEMCFG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - - OutputXbarRegsFile : > OUTPUT_XBAR, PAGE = 1 - - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - PmbusaRegsFile : > PMBUSA, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - DevCfgRegsFile : > DEV_CFG, PAGE = 1 - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - SysPeriphAcRegsFile : > PERIPH_AC, PAGE = 1 - - SyncSocRegsFile : > SYNC_SOC, PAGE = 1 - - XintRegsFile : > XINT, PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h deleted file mode 100644 index d064fc1..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_adc.h +++ /dev/null @@ -1,1048 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_adc.h -// -// TITLE: ADC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ADC_H__ -#define __F28004X_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ADC Individual Register Bit Definitions: - -struct ADCCTL1_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position - Uint16 rsvd2:4; // 6:3 Reserved - Uint16 ADCPWDNZ:1; // 7 ADC Power Down - Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel - Uint16 rsvd3:1; // 12 Reserved - Uint16 ADCBSY:1; // 13 ADC Busy - Uint16 rsvd4:2; // 15:14 Reserved -}; - -union ADCCTL1_REG { - Uint16 all; - struct ADCCTL1_BITS bit; -}; - -struct ADCCTL2_BITS { // bits description - Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:5; // 12:8 Reserved - Uint16 rsvd5:3; // 15:13 Reserved -}; - -union ADCCTL2_REG { - Uint16 all; - struct ADCCTL2_BITS bit; -}; - -struct ADCBURSTCTL_BITS { // bits description - Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable -}; - -union ADCBURSTCTL_REG { - Uint16 all; - struct ADCBURSTCTL_BITS bit; -}; - -struct ADCINTFLG_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLG_REG { - Uint16 all; - struct ADCINTFLG_BITS bit; -}; - -struct ADCINTFLGCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLGCLR_REG { - Uint16 all; - struct ADCINTFLGCLR_BITS bit; -}; - -struct ADCINTOVF_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVF_REG { - Uint16 all; - struct ADCINTOVF_BITS bit; -}; - -struct ADCINTOVFCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVFCLR_REG { - Uint16 all; - struct ADCINTOVFCLR_BITS bit; -}; - -struct ADCINTSEL1N2_BITS { // bits description - Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable - Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable - Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL1N2_REG { - Uint16 all; - struct ADCINTSEL1N2_BITS bit; -}; - -struct ADCINTSEL3N4_BITS { // bits description - Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable - Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable - Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL3N4_REG { - Uint16 all; - struct ADCINTSEL3N4_BITS bit; -}; - -struct ADCSOCPRICTL_BITS { // bits description - Uint16 SOCPRIORITY:5; // 4:0 SOC Priority - Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCSOCPRICTL_REG { - Uint16 all; - struct ADCSOCPRICTL_BITS bit; -}; - -struct ADCINTSOCSEL1_BITS { // bits description - Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select - Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select - Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select - Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select - Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select - Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select - Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select - Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL1_REG { - Uint16 all; - struct ADCINTSOCSEL1_BITS bit; -}; - -struct ADCINTSOCSEL2_BITS { // bits description - Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select - Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select - Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select - Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select - Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select - Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select - Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select - Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL2_REG { - Uint16 all; - struct ADCINTSOCSEL2_BITS bit; -}; - -struct ADCSOCFLG1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag -}; - -union ADCSOCFLG1_REG { - Uint16 all; - struct ADCSOCFLG1_BITS bit; -}; - -struct ADCSOCFRC1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit - Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit - Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit - Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit - Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit - Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit - Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit - Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit - Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit - Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit - Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit - Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit - Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit - Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit - Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit - Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit -}; - -union ADCSOCFRC1_REG { - Uint16 all; - struct ADCSOCFRC1_BITS bit; -}; - -struct ADCSOCOVF1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag -}; - -union ADCSOCOVF1_REG { - Uint16 all; - struct ADCSOCOVF1_BITS bit; -}; - -struct ADCSOCOVFCLR1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit - Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit - Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit - Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit - Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit - Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit - Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit - Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit - Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit - Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit - Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit - Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit - Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit - Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit - Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit - Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit -}; - -union ADCSOCOVFCLR1_REG { - Uint16 all; - struct ADCSOCOVFCLR1_BITS bit; -}; - -struct ADCSOC0CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC0 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC0CTL_REG { - Uint32 all; - struct ADCSOC0CTL_BITS bit; -}; - -struct ADCSOC1CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC1 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC1CTL_REG { - Uint32 all; - struct ADCSOC1CTL_BITS bit; -}; - -struct ADCSOC2CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC2 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC2CTL_REG { - Uint32 all; - struct ADCSOC2CTL_BITS bit; -}; - -struct ADCSOC3CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC3 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC3CTL_REG { - Uint32 all; - struct ADCSOC3CTL_BITS bit; -}; - -struct ADCSOC4CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC4 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC4CTL_REG { - Uint32 all; - struct ADCSOC4CTL_BITS bit; -}; - -struct ADCSOC5CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC5 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC5CTL_REG { - Uint32 all; - struct ADCSOC5CTL_BITS bit; -}; - -struct ADCSOC6CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC6 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC6CTL_REG { - Uint32 all; - struct ADCSOC6CTL_BITS bit; -}; - -struct ADCSOC7CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC7 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC7CTL_REG { - Uint32 all; - struct ADCSOC7CTL_BITS bit; -}; - -struct ADCSOC8CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC8 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC8CTL_REG { - Uint32 all; - struct ADCSOC8CTL_BITS bit; -}; - -struct ADCSOC9CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC9 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC9CTL_REG { - Uint32 all; - struct ADCSOC9CTL_BITS bit; -}; - -struct ADCSOC10CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC10 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC10CTL_REG { - Uint32 all; - struct ADCSOC10CTL_BITS bit; -}; - -struct ADCSOC11CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC11 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC11CTL_REG { - Uint32 all; - struct ADCSOC11CTL_BITS bit; -}; - -struct ADCSOC12CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC12 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC12CTL_REG { - Uint32 all; - struct ADCSOC12CTL_BITS bit; -}; - -struct ADCSOC13CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC13 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC13CTL_REG { - Uint32 all; - struct ADCSOC13CTL_BITS bit; -}; - -struct ADCSOC14CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC14 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC14CTL_REG { - Uint32 all; - struct ADCSOC14CTL_BITS bit; -}; - -struct ADCSOC15CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC15 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC15CTL_REG { - Uint32 all; - struct ADCSOC15CTL_BITS bit; -}; - -struct ADCEVTSTAT_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSTAT_REG { - Uint16 all; - struct ADCEVTSTAT_BITS bit; -}; - -struct ADCEVTCLR_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTCLR_REG { - Uint16 all; - struct ADCEVTCLR_BITS bit; -}; - -struct ADCEVTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSEL_REG { - Uint16 all; - struct ADCEVTSEL_BITS bit; -}; - -struct ADCEVTINTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTINTSEL_REG { - Uint16 all; - struct ADCEVTINTSEL_BITS bit; -}; - -struct ADCCOUNTER_BITS { // bits description - Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCCOUNTER_REG { - Uint16 all; - struct ADCCOUNTER_BITS bit; -}; - -struct ADCREV_BITS { // bits description - Uint16 TYPE:8; // 7:0 ADC Type - Uint16 REV:8; // 15:8 ADC Revision -}; - -union ADCREV_REG { - Uint16 all; - struct ADCREV_BITS bit; -}; - -struct ADCOFFTRIM_BITS { // bits description - Uint16 OFFTRIM:12; // 11:0 ADC Offset Trim - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCOFFTRIM_REG { - Uint16 all; - struct ADCOFFTRIM_BITS bit; -}; - -struct ADCPPB1CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB1CONFIG_REG { - Uint16 all; - struct ADCPPB1CONFIG_BITS bit; -}; - -struct ADCPPB1STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB1STAMP_REG { - Uint16 all; - struct ADCPPB1STAMP_BITS bit; -}; - -struct ADCPPB1OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB1OFFCAL_REG { - Uint16 all; - struct ADCPPB1OFFCAL_BITS bit; -}; - -struct ADCPPB1TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB1TRIPHI_REG { - Uint32 all; - struct ADCPPB1TRIPHI_BITS bit; -}; - -struct ADCPPB1TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp -}; - -union ADCPPB1TRIPLO_REG { - Uint32 all; - struct ADCPPB1TRIPLO_BITS bit; -}; - -struct ADCPPB2CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB2CONFIG_REG { - Uint16 all; - struct ADCPPB2CONFIG_BITS bit; -}; - -struct ADCPPB2STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB2STAMP_REG { - Uint16 all; - struct ADCPPB2STAMP_BITS bit; -}; - -struct ADCPPB2OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB2OFFCAL_REG { - Uint16 all; - struct ADCPPB2OFFCAL_BITS bit; -}; - -struct ADCPPB2TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB2TRIPHI_REG { - Uint32 all; - struct ADCPPB2TRIPHI_BITS bit; -}; - -struct ADCPPB2TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp -}; - -union ADCPPB2TRIPLO_REG { - Uint32 all; - struct ADCPPB2TRIPLO_BITS bit; -}; - -struct ADCPPB3CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB3CONFIG_REG { - Uint16 all; - struct ADCPPB3CONFIG_BITS bit; -}; - -struct ADCPPB3STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB3STAMP_REG { - Uint16 all; - struct ADCPPB3STAMP_BITS bit; -}; - -struct ADCPPB3OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB3OFFCAL_REG { - Uint16 all; - struct ADCPPB3OFFCAL_BITS bit; -}; - -struct ADCPPB3TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB3TRIPHI_REG { - Uint32 all; - struct ADCPPB3TRIPHI_BITS bit; -}; - -struct ADCPPB3TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp -}; - -union ADCPPB3TRIPLO_REG { - Uint32 all; - struct ADCPPB3TRIPLO_BITS bit; -}; - -struct ADCPPB4CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable - Uint16 CBCEN:1; // 5 Cycle By Cycle Enable - Uint16 rsvd1:10; // 15:6 Reserved -}; - -union ADCPPB4CONFIG_REG { - Uint16 all; - struct ADCPPB4CONFIG_BITS bit; -}; - -struct ADCPPB4STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB4STAMP_REG { - Uint16 all; - struct ADCPPB4STAMP_BITS bit; -}; - -struct ADCPPB4OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB4OFFCAL_REG { - Uint16 all; - struct ADCPPB4OFFCAL_BITS bit; -}; - -struct ADCPPB4TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB4TRIPHI_REG { - Uint32 all; - struct ADCPPB4TRIPHI_BITS bit; -}; - -struct ADCPPB4TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp -}; - -union ADCPPB4TRIPLO_REG { - Uint32 all; - struct ADCPPB4TRIPLO_BITS bit; -}; - -struct ADC_REGS { - union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register - union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register - union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register - union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register - union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register - union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register - union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register - union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register - union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register - union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register - union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register - union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register - union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register - union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register - union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register - union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register - union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register - union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register - union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register - union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register - union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register - union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register - union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register - union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register - union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register - union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register - union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register - union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register - union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register - union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register - union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register - union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register - union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register - Uint16 rsvd1; // Reserved - union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register - Uint16 rsvd2; // Reserved - union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register - Uint16 rsvd3; // Reserved - union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register - Uint16 rsvd4[2]; // Reserved - union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register - union ADCREV_REG ADCREV; // ADC Revision Register - union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register - Uint16 rsvd5[4]; // Reserved - union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register - union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register - union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register - Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register - union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register - union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register - union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register - union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register - union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register - Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register - union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register - union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register - union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register - union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register - union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register - Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register - union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register - union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register - union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register - union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register - union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register - Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register - union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register - union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register - Uint16 rsvd6[15]; // Reserved - Uint16 ADCINTCYCLE; // ADC Early Interrupt Generation Cycle - Uint16 rsvd7[16]; // Reserved -}; - -struct ADCPPB1RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB1RESULT_REG { - Uint32 all; - struct ADCPPB1RESULT_BITS bit; -}; - -struct ADCPPB2RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB2RESULT_REG { - Uint32 all; - struct ADCPPB2RESULT_BITS bit; -}; - -struct ADCPPB3RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB3RESULT_REG { - Uint32 all; - struct ADCPPB3RESULT_BITS bit; -}; - -struct ADCPPB4RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB4RESULT_REG { - Uint32 all; - struct ADCPPB4RESULT_BITS bit; -}; - -struct ADC_RESULT_REGS { - Uint16 ADCRESULT0; // ADC Result 0 Register - Uint16 ADCRESULT1; // ADC Result 1 Register - Uint16 ADCRESULT2; // ADC Result 2 Register - Uint16 ADCRESULT3; // ADC Result 3 Register - Uint16 ADCRESULT4; // ADC Result 4 Register - Uint16 ADCRESULT5; // ADC Result 5 Register - Uint16 ADCRESULT6; // ADC Result 6 Register - Uint16 ADCRESULT7; // ADC Result 7 Register - Uint16 ADCRESULT8; // ADC Result 8 Register - Uint16 ADCRESULT9; // ADC Result 9 Register - Uint16 ADCRESULT10; // ADC Result 10 Register - Uint16 ADCRESULT11; // ADC Result 11 Register - Uint16 ADCRESULT12; // ADC Result 12 Register - Uint16 ADCRESULT13; // ADC Result 13 Register - Uint16 ADCRESULT14; // ADC Result 14 Register - Uint16 ADCRESULT15; // ADC Result 15 Register - union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register - union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register - union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register - union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register -}; - -//--------------------------------------------------------------------------- -// ADC External References & Function Declarations: -// -extern volatile struct ADC_RESULT_REGS AdcaResultRegs; -extern volatile struct ADC_RESULT_REGS AdcbResultRegs; -extern volatile struct ADC_RESULT_REGS AdccResultRegs; -extern volatile struct ADC_REGS AdcaRegs; -extern volatile struct ADC_REGS AdcbRegs; -extern volatile struct ADC_REGS AdccRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h deleted file mode 100644 index ce95230..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_analogsubsys.h +++ /dev/null @@ -1,232 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_analogsubsys.h -// -// TITLE: ANALOGSUBSYS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ANALOGSUBSYS_H__ -#define __F28004X_ANALOGSUBSYS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS Individual Register Bit Definitions: - -struct ANAREFPP_BITS { // bits description - Uint16 ANAREFBDIS:1; // 0 Disable ANAREFB - Uint16 ANAREFCDIS:1; // 1 Disable ANAREFC - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union ANAREFPP_REG { - Uint16 all; - struct ANAREFPP_BITS bit; -}; - -struct TSNSCTL_BITS { // bits description - Uint16 ENABLE:1; // 0 Temperature Sensor Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TSNSCTL_REG { - Uint16 all; - struct TSNSCTL_BITS bit; -}; - -struct ANAREFCTL_BITS { // bits description - Uint16 ANAREFASEL:1; // 0 Analog Reference A Select - Uint16 ANAREFBSEL:1; // 1 Analog Reference B Select - Uint16 ANAREFCSEL:1; // 2 Analog Reference C Select - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 ANAREFA2P5SEL:1; // 8 Analog Reference A Select - Uint16 ANAREFB2P5SEL:1; // 9 Analog Reference B Select - Uint16 ANAREFC2P5SEL:1; // 10 Analog Reference B Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union ANAREFCTL_REG { - Uint16 all; - struct ANAREFCTL_BITS bit; -}; - -struct DCDCCTL_BITS { // bits description - Uint16 DCDCEN:1; // 0 DCDC Enable - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:15; // 30:16 Reserved - Uint16 rsvd3:1; // 31 Reserved -}; - -union DCDCCTL_REG { - Uint32 all; - struct DCDCCTL_BITS bit; -}; - -struct DCDCSTS_BITS { // bits description - Uint16 INDDETECT:1; // 0 Inductor Detected - Uint16 SWSEQDONE:1; // 1 Switch sequence to DC-DC done. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:13; // 15:3 Reserved -}; - -union DCDCSTS_REG { - Uint16 all; - struct DCDCSTS_BITS bit; -}; - -struct CMPHPMXSEL_BITS { // bits description - Uint16 CMP1HPMXSEL:3; // 2:0 CMP1HPMXSEL bits - Uint16 CMP2HPMXSEL:3; // 5:3 CMP2HPMXSEL bits - Uint16 CMP3HPMXSEL:3; // 8:6 CMP3HPMXSEL bits - Uint16 CMP4HPMXSEL:3; // 11:9 CMP4HPMXSEL bits - Uint16 CMP5HPMXSEL:3; // 14:12 CMP5HPMXSEL bits - Uint16 rsvd1:1; // 15 Reserved - Uint16 CMP6HPMXSEL:3; // 18:16 CMP6HPMXSEL bits - Uint16 CMP7HPMXSEL:3; // 21:19 CMP7HPMXSEL bits - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union CMPHPMXSEL_REG { - Uint32 all; - struct CMPHPMXSEL_BITS bit; -}; - -struct CMPLPMXSEL_BITS { // bits description - Uint16 CMP1LPMXSEL:3; // 2:0 CMP1LPMXSEL bits - Uint16 CMP2LPMXSEL:3; // 5:3 CMP2LPMXSEL bits - Uint16 CMP3LPMXSEL:3; // 8:6 CMP3LPMXSEL bits - Uint16 CMP4LPMXSEL:3; // 11:9 CMP4LPMXSEL bits - Uint16 CMP5LPMXSEL:3; // 14:12 CMP5LPMXSEL bits - Uint16 rsvd1:1; // 15 Reserved - Uint16 CMP6LPMXSEL:3; // 18:16 CMP6LPMXSEL bits - Uint16 CMP7LPMXSEL:3; // 21:19 CMP7LPMXSEL bits - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union CMPLPMXSEL_REG { - Uint32 all; - struct CMPLPMXSEL_BITS bit; -}; - -struct CMPHNMXSEL_BITS { // bits description - Uint16 CMP1HNMXSEL:1; // 0 CMP1HNMXSEL bits - Uint16 CMP2HNMXSEL:1; // 1 CMP2HNMXSEL bits - Uint16 CMP3HNMXSEL:1; // 2 CMP3HNMXSEL bits - Uint16 CMP4HNMXSEL:1; // 3 CMP4HNMXSEL bits - Uint16 CMP5HNMXSEL:1; // 4 CMP5HNMXSEL bits - Uint16 CMP6HNMXSEL:1; // 5 CMP6HNMXSEL bits - Uint16 CMP7HNMXSEL:1; // 6 CMP7HNMXSEL bits - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union CMPHNMXSEL_REG { - Uint16 all; - struct CMPHNMXSEL_BITS bit; -}; - -struct CMPLNMXSEL_BITS { // bits description - Uint16 CMP1LNMXSEL:1; // 0 CMP1LNMXSEL bits - Uint16 CMP2LNMXSEL:1; // 1 CMP2LNMXSEL bits - Uint16 CMP3LNMXSEL:1; // 2 CMP3LNMXSEL bits - Uint16 CMP4LNMXSEL:1; // 3 CMP4LNMXSEL bits - Uint16 CMP5LNMXSEL:1; // 4 CMP5LNMXSEL bits - Uint16 CMP6LNMXSEL:1; // 5 CMP6LNMXSEL bits - Uint16 CMP7LNMXSEL:1; // 6 CMP7LNMXSEL bits - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union CMPLNMXSEL_REG { - Uint16 all; - struct CMPLNMXSEL_BITS bit; -}; - -struct LOCK_BITS { // bits description - Uint16 TSNSCTL:1; // 0 TSNSCTL Register lock bit - Uint16 ANAREFCTL:1; // 1 ANAREFCTL Register lock bit - Uint16 VMONCTL:1; // 2 VMONCTL Register lock bit - Uint16 DCDCCTL:1; // 3 DCDCCTL Register lock bit - Uint16 ADCINMXSEL:1; // 4 ADCINMXSEL Register lock bit - Uint16 CMPHPMXSEL:1; // 5 CMPHPMXSEL Register lock bit - Uint16 CMPLPMXSEL:1; // 6 CMPLPMXSEL Register lock bit - Uint16 CMPHNMXSEL:1; // 7 CMPHNMXSEL Register lock bit - Uint16 CMPLNMXSEL:1; // 8 CMPLNMXSEL Register lock bit - Uint16 VREGCTL:1; // 9 VREGCTL Register lock bit - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOCK_REG { - Uint32 all; - struct LOCK_BITS bit; -}; - -struct ANALOG_SUBSYS_REGS { - Uint16 rsvd1[30]; // Reserved - union ANAREFPP_REG ANAREFPP; // ADC Analog Reference Peripheral Properties register - Uint16 rsvd2[65]; // Reserved - union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register - Uint16 rsvd3[7]; // Reserved - union ANAREFCTL_REG ANAREFCTL; // Analog Reference Control Register - Uint16 rsvd4[15]; // Reserved - union DCDCCTL_REG DCDCCTL; // DC-DC control register. - union DCDCSTS_REG DCDCSTS; // DC-DC status register. - Uint16 rsvd5[7]; // Reserved - union CMPHPMXSEL_REG CMPHPMXSEL; // Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details. - union CMPLPMXSEL_REG CMPLPMXSEL; // Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details. - union CMPHNMXSEL_REG CMPHNMXSEL; // Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details. - union CMPLNMXSEL_REG CMPLNMXSEL; // Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details. - Uint16 rsvd6[6]; // Reserved - union LOCK_REG LOCK; // Lock Register -}; - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS External References & Function Declarations: -// -extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h deleted file mode 100644 index 6417951..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_can.h +++ /dev/null @@ -1,607 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_can.h -// -// TITLE: CAN Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CAN_H__ -#define __F28004X_CAN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CAN Individual Register Bit Definitions: - -struct CAN_CTL_BITS { // bits description - bp_16 Init:1; // 0 Initialization - bp_16 IE0:1; // 1 Interrupt line 0 Enable - bp_16 SIE:1; // 2 Status Change Interrupt Enable - bp_16 EIE:1; // 3 Error Interrupt Enable - bp_16 rsvd1:1; // 4 Reserved - bp_16 DAR:1; // 5 Disable Automatic Retransmission - bp_16 CCE:1; // 6 Configuration Change Enable - bp_16 Test:1; // 7 Test Mode Enable - bp_16 IDS:1; // 8 Interruption Debug Support Enable - bp_16 ABO:1; // 9 Auto-Bus-On Enable - bp_16 PMD:4; // 13:10 Parity on/off - bp_16 rsvd2:1; // 14 Reserved - bp_16 SWR:1; // 15 SW Reset Enable - bp_32 INITDBG:1; // 16 Debug Mode Status - bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled - bp_32 DE1:1; // 18 Enable DMA request line - bp_32 DE2:1; // 19 Enable DMA request line - bp_32 DE3:1; // 20 Enable DMA request line - bp_32 rsvd3:3; // 23:21 Reserved - bp_32 rsvd4:1; // 24 Reserved - bp_32 rsvd5:1; // 25 Reserved - bp_32 rsvd6:6; // 31:26 Reserved -}; - -union CAN_CTL_REG { - bp_32 all; - struct CAN_CTL_BITS bit; -}; - -struct CAN_ES_BITS { // bits description - bp_16 LEC:3; // 2:0 Last Error Code - bp_16 TxOk:1; // 3 Transmission status - bp_16 RxOk:1; // 4 Reception status - bp_16 EPass:1; // 5 Error Passive State - bp_16 EWarn:1; // 6 Warning State - bp_16 BOff:1; // 7 Bus-Off State - bp_16 PER:1; // 8 Parity Error Detected - bp_16 rsvd1:1; // 9 Reserved - bp_16 rsvd2:1; // 10 Reserved - bp_16 rsvd3:5; // 15:11 Reserved - bp_32 rsvd4:16; // 31:16 Reserved -}; - -union CAN_ES_REG { - bp_32 all; - struct CAN_ES_BITS bit; -}; - -struct CAN_ERRC_BITS { // bits description - bp_16 TEC:8; // 7:0 Transmit Error Counter - bp_16 REC:7; // 14:8 Receive Error Counter - bp_16 RP:1; // 15 Receive Error Passive - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union CAN_ERRC_REG { - bp_32 all; - struct CAN_ERRC_BITS bit; -}; - -struct CAN_BTR_BITS { // bits description - bp_16 BRP:6; // 5:0 Baud Rate Prescaler - bp_16 SJW:2; // 7:6 Synchronization Jump Width - bp_16 TSEG1:4; // 11:8 Time segment - bp_16 TSEG2:3; // 14:12 Time segment - bp_16 rsvd1:1; // 15 Reserved - bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension - bp_32 rsvd2:12; // 31:20 Reserved -}; - -union CAN_BTR_REG { - bp_32 all; - struct CAN_BTR_BITS bit; -}; - -struct CAN_INT_BITS { // bits description - bp_16 INT0ID:16; // 15:0 Interrupt Identifier - bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union CAN_INT_REG { - bp_32 all; - struct CAN_INT_BITS bit; -}; - -struct CAN_TEST_BITS { // bits description - bp_16 rsvd1:3; // 2:0 Reserved - bp_16 SILENT:1; // 3 Silent Mode - bp_16 LBACK:1; // 4 Loopback Mode - bp_16 TX:2; // 6:5 CANTX Pin Control - bp_16 RX:1; // 7 CANRX Pin Status - bp_16 EXL:1; // 8 External Loopback Mode - bp_16 RDA:1; // 9 RAM Direct Access Enable: - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_TEST_REG { - bp_32 all; - struct CAN_TEST_BITS bit; -}; - -struct CAN_PERR_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 WORD_NUM:3; // 10:8 Word Number - bp_16 rsvd1:5; // 15:11 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_PERR_REG { - bp_32 all; - struct CAN_PERR_BITS bit; -}; - -struct CAN_RAM_INIT_BITS { // bits description - bp_16 KEY0:1; // 0 KEY0 - bp_16 KEY1:1; // 1 KEY1 - bp_16 KEY2:1; // 2 KEY2 - bp_16 KEY3:1; // 3 KEY3 - bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM - bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete - bp_16 rsvd1:10; // 15:6 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_RAM_INIT_REG { - bp_32 all; - struct CAN_RAM_INIT_BITS bit; -}; - -struct CAN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_EN_REG { - bp_32 all; - struct CAN_GLB_INT_EN_BITS bit; -}; - -struct CAN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_FLG_REG { - bp_32 all; - struct CAN_GLB_INT_FLG_BITS bit; -}; - -struct CAN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_CLR_REG { - bp_32 all; - struct CAN_GLB_INT_CLR_BITS bit; -}; - -struct CAN_TXRQ_X_BITS { // bits description - bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 - bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_TXRQ_X_REG { - bp_32 all; - struct CAN_TXRQ_X_BITS bit; -}; - -struct CAN_NDAT_X_BITS { // bits description - bp_16 NewDatReg1:2; // 1:0 New Data Register 1 - bp_16 NewDatReg2:2; // 3:2 New Data Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_NDAT_X_REG { - bp_32 all; - struct CAN_NDAT_X_BITS bit; -}; - -struct CAN_IPEN_X_BITS { // bits description - bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 - bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IPEN_X_REG { - bp_32 all; - struct CAN_IPEN_X_BITS bit; -}; - -struct CAN_MVAL_X_BITS { // bits description - bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 - bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_MVAL_X_REG { - bp_32 all; - struct CAN_MVAL_X_BITS bit; -}; - -struct CAN_IF1CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 DMAactive:1; // 14 DMA Status - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TXRQST:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union CAN_IF1CMD_REG { - bp_32 all; - struct CAN_IF1CMD_BITS bit; -}; - -struct CAN_IF1MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF1MSK_REG { - bp_32 all; - struct CAN_IF1MSK_BITS bit; -}; - -struct CAN_IF1ARB_BITS { // bits description - bp_32 ID:29; // 28:0 ` - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF1ARB_REG { - bp_32 all; - struct CAN_IF1ARB_BITS bit; -}; - -struct CAN_IF1MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF1MCTL_REG { - bp_32 all; - struct CAN_IF1MCTL_BITS bit; -}; - -struct CAN_IF1DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF1DATA_REG { - bp_32 all; - struct CAN_IF1DATA_BITS bit; -}; - -struct CAN_IF1DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF1DATB_REG { - bp_32 all; - struct CAN_IF1DATB_BITS bit; -}; - -struct CAN_IF2CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 DMAactive:1; // 14 DMA Status - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TxRqst:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union CAN_IF2CMD_REG { - bp_32 all; - struct CAN_IF2CMD_BITS bit; -}; - -struct CAN_IF2MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF2MSK_REG { - bp_32 all; - struct CAN_IF2MSK_BITS bit; -}; - -struct CAN_IF2ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF2ARB_REG { - bp_32 all; - struct CAN_IF2ARB_BITS bit; -}; - -struct CAN_IF2MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF2MCTL_REG { - bp_32 all; - struct CAN_IF2MCTL_BITS bit; -}; - -struct CAN_IF2DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF2DATA_REG { - bp_32 all; - struct CAN_IF2DATA_BITS bit; -}; - -struct CAN_IF2DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF2DATB_REG { - bp_32 all; - struct CAN_IF2DATB_BITS bit; -}; - -struct CAN_IF3OBS_BITS { // bits description - bp_16 Mask:1; // 0 Mask data read observation - bp_16 Arb:1; // 1 Arbitration data read observation - bp_16 Ctrl:1; // 2 Ctrl read observation - bp_16 Data_A:1; // 3 Data A read observation - bp_16 Data_B:1; // 4 Data B read observation - bp_16 rsvd1:3; // 7:5 Reserved - bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access - bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access - bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access - bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access - bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access - bp_16 rsvd2:2; // 14:13 Reserved - bp_16 IF3Upd:1; // 15 IF3 Update Data - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_IF3OBS_REG { - bp_32 all; - struct CAN_IF3OBS_BITS bit; -}; - -struct CAN_IF3MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF3MSK_REG { - bp_32 all; - struct CAN_IF3MSK_BITS bit; -}; - -struct CAN_IF3ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF3ARB_REG { - bp_32 all; - struct CAN_IF3ARB_BITS bit; -}; - -struct CAN_IF3MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF3MCTL_REG { - bp_32 all; - struct CAN_IF3MCTL_BITS bit; -}; - -struct CAN_IF3DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF3DATA_REG { - bp_32 all; - struct CAN_IF3DATA_BITS bit; -}; - -struct CAN_IF3DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF3DATB_REG { - bp_32 all; - struct CAN_IF3DATB_BITS bit; -}; - -struct CAN_REGS { - union CAN_CTL_REG CAN_CTL; // CAN Control Register - union CAN_ES_REG CAN_ES; // Error and Status Register - union CAN_ERRC_REG CAN_ERRC; // Error Counter Register - union CAN_BTR_REG CAN_BTR; // Bit Timing Register - union CAN_INT_REG CAN_INT; // Interrupt Register - union CAN_TEST_REG CAN_TEST; // Test Register - uint32_t rsvd6[2]; // Reserved - union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register - uint32_t rsvd7[16]; // Reserved - union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register - uint32_t rsvd8[6]; // Reserved - union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register - union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register - union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register - uint32_t rsvd11[18]; // Reserved - bp_32 CAN_ABOTR; // Auto-Bus-On Time Register - union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register - bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register - uint32_t rsvd14[6]; // Reserved - union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register - bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register - uint32_t rsvd16[6]; // Reserved - union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register - bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register - uint32_t rsvd18[6]; // Reserved - union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register - bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register - uint32_t rsvd20[8]; // Reserved - bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register - uint32_t rsvd21[18]; // Reserved - union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register - union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register - union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register - union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register - union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register - union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register - uint32_t rsvd27[4]; // Reserved - union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register - union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register - union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register - union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register - union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register - union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register - uint32_t rsvd33[4]; // Reserved - union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register - union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register - union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register - union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register - union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register - union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register - uint32_t rsvd39[4]; // Reserved - bp_32 CAN_IF3UPD; // IF3 Update Enable Register - uint32_t rsvd40[78]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CAN External References & Function Declarations: -// -extern volatile struct CAN_REGS CanaRegs; -extern volatile struct CAN_REGS CanbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h deleted file mode 100644 index 9a64068..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla.h +++ /dev/null @@ -1,366 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cla.h -// -// TITLE: CLA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CLA_H__ -#define __F28004X_CLA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA Individual Register Bit Definitions: - -struct MCTL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset - Uint16 SOFTRESET:1; // 1 Soft Reset - Uint16 IACKE:1; // 2 IACK enable - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union MCTL_REG { - Uint16 all; - struct MCTL_BITS bit; -}; - -struct SOFTINTEN_BITS { // bits description - Uint16 TASK1:1; // 0 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK2:1; // 1 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK3:1; // 2 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK4:1; // 3 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK5:1; // 4 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK6:1; // 5 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK7:1; // 6 Configure Software Interrupt or End of Task interrupt. - Uint16 TASK8:1; // 7 Configure Software Interrupt or End of Task interrupt. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SOFTINTEN_REG { - Uint16 all; - struct SOFTINTEN_BITS bit; -}; - -struct _MSTSBGRND_BITS { // bits description - Uint16 RUN:1; // 0 Background task run status bit. - Uint16 _BGINTM:1; // 1 Indicates whether background task can be interrupted. - Uint16 BGOVF:1; // 2 background task harware trigger overflow. - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union _MSTSBGRND_REG { - Uint16 all; - struct _MSTSBGRND_BITS bit; -}; - -struct _MCTLBGRND_BITS { // bits description - Uint16 BGSTART:1; // 0 Background task start bit - Uint16 TRIGEN:1; // 1 Background task hardware trigger enable - Uint16 rsvd1:13; // 14:2 Reserved - Uint16 BGEN:1; // 15 Enable background task -}; - -union _MCTLBGRND_REG { - Uint16 all; - struct _MCTLBGRND_BITS bit; -}; - -struct MIFR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFR_REG { - Uint16 all; - struct MIFR_BITS bit; -}; - -struct MIOVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIOVF_REG { - Uint16 all; - struct MIOVF_BITS bit; -}; - -struct MIFRC_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Force - Uint16 INT2:1; // 1 Task 2 Interrupt Force - Uint16 INT3:1; // 2 Task 3 Interrupt Force - Uint16 INT4:1; // 3 Task 4 Interrupt Force - Uint16 INT5:1; // 4 Task 5 Interrupt Force - Uint16 INT6:1; // 5 Task 6 Interrupt Force - Uint16 INT7:1; // 6 Task 7 Interrupt Force - Uint16 INT8:1; // 7 Task 8 Interrupt Force - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFRC_REG { - Uint16 all; - struct MIFRC_BITS bit; -}; - -struct MICLR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLR_REG { - Uint16 all; - struct MICLR_BITS bit; -}; - -struct MICLROVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLROVF_REG { - Uint16 all; - struct MICLROVF_BITS bit; -}; - -struct MIER_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Enable - Uint16 INT2:1; // 1 Task 2 Interrupt Enable - Uint16 INT3:1; // 2 Task 3 Interrupt Enable - Uint16 INT4:1; // 3 Task 4 Interrupt Enable - Uint16 INT5:1; // 4 Task 5 Interrupt Enable - Uint16 INT6:1; // 5 Task 6 Interrupt Enable - Uint16 INT7:1; // 6 Task 7 Interrupt Enable - Uint16 INT8:1; // 7 Task 8 Interrupt Enable - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIER_REG { - Uint16 all; - struct MIER_BITS bit; -}; - -struct MIRUN_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Run Status - Uint16 INT2:1; // 1 Task 2 Run Status - Uint16 INT3:1; // 2 Task 3 Run Status - Uint16 INT4:1; // 3 Task 4 Run Status - Uint16 INT5:1; // 4 Task 5 Run Status - Uint16 INT6:1; // 5 Task 6 Run Status - Uint16 INT7:1; // 6 Task 7 Run Status - Uint16 INT8:1; // 7 Task 8 Run Status - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIRUN_REG { - Uint16 all; - struct MIRUN_BITS bit; -}; - -struct _MSTF_BITS { // bits description - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint32 _RPC:16; // 27:12 Return PC - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union _MSTF_REG { - Uint32 all; - struct _MSTF_BITS bit; -}; - -struct _MPSACTL_BITS { // bits description - Uint16 MPABSTART:1; // 0 Start logging PAB onto PSA1 - Uint16 MPABCYC:1; // 1 PAB logging into PSA1 is on every cycle or when PAB changes. - Uint16 MDWDBSTART:1; // 2 Start logging DWDB onto PSA2 - Uint16 MDWDBCYC:1; // 3 DWDB logging into PSA2 is on every cycle. - Uint16 MPSA1CLEAR:1; // 4 PSA1 clear - Uint16 MPSA2CLEAR:1; // 5 PSA2 Clear - Uint16 MPSA2CFG:2; // 7:6 PSA2 Polynomial Configuration - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union _MPSACTL_REG { - Uint16 all; - struct _MPSACTL_BITS bit; -}; - -union MR_REG { - Uint32 i32; - float f32; -}; - -struct CLA_REGS { - Uint16 MVECT1; // Task Interrupt Vector - Uint16 MVECT2; // Task Interrupt Vector - Uint16 MVECT3; // Task Interrupt Vector - Uint16 MVECT4; // Task Interrupt Vector - Uint16 MVECT5; // Task Interrupt Vector - Uint16 MVECT6; // Task Interrupt Vector - Uint16 MVECT7; // Task Interrupt Vector - Uint16 MVECT8; // Task Interrupt Vector - Uint16 rsvd1[8]; // Reserved - union MCTL_REG MCTL; // Control Register - Uint16 rsvd2[10]; // Reserved - Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - union _MSTSBGRND_REG _MSTSBGRND; // Status register for the back ground task. - union _MCTLBGRND_REG _MCTLBGRND; // Control register for the back ground task. - Uint16 _MVECTBGRND; // Vector for the back ground task. - union MIFR_REG MIFR; // Interrupt Flag Register - union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register - union MIFRC_REG MIFRC; // Interrupt Force Register - union MICLR_REG MICLR; // Interrupt Flag Clear Register - union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register - union MIER_REG MIER; // Interrupt Enable Register - union MIRUN_REG MIRUN; // Interrupt Run Status Register - Uint16 rsvd3; // Reserved - Uint16 _MPC; // CLA Program Counter - Uint16 rsvd4; // Reserved - Uint16 _MAR0; // CLA Auxiliary Register 0 - Uint16 _MAR1; // CLA Auxiliary Register 1 - Uint16 rsvd5[2]; // Reserved - union _MSTF_REG _MSTF; // CLA Floating-Point Status Register - union MR_REG _MR0; // CLA Floating-Point Result Register 0 - Uint16 rsvd6[2]; // Reserved - union MR_REG _MR1; // CLA Floating-Point Result Register 1 - Uint16 rsvd7[2]; // Reserved - union MR_REG _MR2; // CLA Floating-Point Result Register 2 - Uint16 rsvd8[2]; // Reserved - union MR_REG _MR3; // CLA Floating-Point Result Register 3 - Uint16 rsvd9[4]; // Reserved - union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register - Uint16 rsvd10; // Reserved - Uint32 _MPSA1; // CLA PSA1 Register - Uint32 _MPSA2; // CLA PSA2 Register - Uint16 rsvd11[56]; // Reserved -}; - -struct SOFTINTFRC_BITS { // bits description - Uint16 TASK1:1; // 0 Force CLA software interrupt for the corresponding task. - Uint16 TASK2:1; // 1 Force CLA software interrupt for the corresponding task. - Uint16 TASK3:1; // 2 Force CLA software interrupt for the corresponding task. - Uint16 TASK4:1; // 3 Force CLA software interrupt for the corresponding task. - Uint16 TASK5:1; // 4 Force CLA software interrupt for the corresponding task. - Uint16 TASK6:1; // 5 Force CLA software interrupt for the corresponding task. - Uint16 TASK7:1; // 6 Force CLA software interrupt for the corresponding task. - Uint16 TASK8:1; // 7 Force CLA software interrupt for the corresponding task. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SOFTINTFRC_REG { - Uint16 all; - struct SOFTINTFRC_BITS bit; -}; - -struct CLA_ONLY_REGS { - Uint16 rsvd1[128]; // Reserved - Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. - Uint16 rsvd2[63]; // Reserved - union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register - Uint16 rsvd3; // Reserved - Uint32 _MPSA1; // CLA PSA1 Register - Uint32 _MPSA2; // CLA PSA2 Register - Uint16 rsvd4[26]; // Reserved - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - Uint16 rsvd5; // Reserved - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register - Uint16 rsvd6[12]; // Reserved -}; - -struct CLA_SOFTINT_REGS { - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - Uint16 rsvd1; // Reserved - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register - Uint16 rsvd2[12]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CLA External References & Function Declarations: -// -extern volatile struct CLA_ONLY_REGS Cla1OnlyRegs; -extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; -extern volatile struct CLA_REGS Cla1Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h deleted file mode 100644 index 0409187..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cla_prom_crc32.h +++ /dev/null @@ -1,157 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cla_prom_crc32.h -// -// TITLE: CLA_PROM_CRC32 Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CLA_PROM_CRC32_H__ -#define __F28004X_CLA_PROM_CRC32_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA_PROM_CRC32 Individual Register Bit Definitions: - -struct CRC32_CONTROLREG_BITS { // bits description - Uint16 START:1; // 0 Start Bit - Uint16 rsvd1:3; // 3:1 Reserved - Uint16 FREE_SOFT:1; // 4 emulation control bit - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 HALT:1; // 8 Halt Bit - Uint16 rsvd3:7; // 15:9 Reserved - Uint16 BLOCKSIZE:7; // 22:16 Block size of ROM for which CRC is to be calculated - Uint16 rsvd4:9; // 31:23 Reserved -}; - -union CRC32_CONTROLREG_REG { - Uint32 all; - struct CRC32_CONTROLREG_BITS bit; -}; - -struct CRC32_STATUSREG_BITS { // bits description - Uint16 CURRENTADDR:16; // 15:0 Point to the data fetch unit current address - Uint16 rsvd1:7; // 22:16 Reserved - Uint16 CRCCHECKSTATUS:1; // 23 CRC active status - Uint16 rsvd2:7; // 30:24 Reserved - Uint16 RUNSTATUS:1; // 31 CRC active status -}; - -union CRC32_STATUSREG_REG { - Uint32 all; - struct CRC32_STATUSREG_BITS bit; -}; - -struct CRC32_INTEN_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CRCDONE:1; // 1 CRCDONE interrupt enable register - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CRC32_INTEN_REG { - Uint32 all; - struct CRC32_INTEN_BITS bit; -}; - -struct CRC32_FLG_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt status flag - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt status flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CRC32_FLG_REG { - Uint32 all; - struct CRC32_FLG_BITS bit; -}; - -struct CRC32_CLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt clear - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CRC32_CLR_REG { - Uint32 all; - struct CRC32_CLR_BITS bit; -}; - -struct CRC32_FRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CRCDONE:1; // 1 CRCDONE Interrupt force - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CRC32_FRC_REG { - Uint32 all; - struct CRC32_FRC_BITS bit; -}; - -struct CLA_PROM_CRC32_REGS { - union CRC32_CONTROLREG_REG CRC32_CONTROLREG; // CRC32-Control Register - Uint32 CRC32_STARTADDRESS; // CRC32-Start address register - Uint32 CRC32_SEED; // CRC32-Seed Register - union CRC32_STATUSREG_REG CRC32_STATUSREG; // CRC32-Status Register - Uint32 CRC32_CRCRESULT; // CRC32-CRC result Register - Uint32 CRC32_GOLDENCRC; // CRC32-Golden CRC register - Uint16 rsvd1[12]; // Reserved - union CRC32_INTEN_REG CRC32_INTEN; // CRC32-Interrupt enable register - union CRC32_FLG_REG CRC32_FLG; // CRC32-Interrupt Flag Register - union CRC32_CLR_REG CRC32_CLR; // CRC32-Interrupt Clear Register - union CRC32_FRC_REG CRC32_FRC; // CRC32-Interrupt Force Register -}; - -//--------------------------------------------------------------------------- -// CLA_PROM_CRC32 External References & Function Declarations: -// -extern volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h deleted file mode 100644 index 29c5717..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cmpss.h +++ /dev/null @@ -1,299 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cmpss.h -// -// TITLE: CMPSS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CMPSS_H__ -#define __F28004X_CMPSS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CMPSS Individual Register Bit Definitions: - -struct COMPCTL_BITS { // bits description - Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select - Uint16 COMPHINV:1; // 1 High Comparator Invert Select - Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select - Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select - Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable - Uint16 rsvd1:1; // 7 Reserved - Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select - Uint16 COMPLINV:1; // 9 Low Comparator Invert Select - Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select - Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select - Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable - Uint16 COMPDACE:1; // 15 Comparator/DAC Enable -}; - -union COMPCTL_REG { - Uint16 all; - struct COMPCTL_BITS bit; -}; - -struct COMPHYSCTL_BITS { // bits description - Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union COMPHYSCTL_REG { - Uint16 all; - struct COMPHYSCTL_BITS bit; -}; - -struct COMPSTS_BITS { // bits description - Uint16 COMPHSTS:1; // 0 High Comparator Status - Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 COMPLSTS:1; // 8 Low Comparator Status - Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status - Uint16 rsvd2:6; // 15:10 Reserved -}; - -union COMPSTS_REG { - Uint16 all; - struct COMPSTS_BITS bit; -}; - -struct COMPSTSCLR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear - Uint16 HSYNCCLREN:1; // 2 High Comparator EPWMSYNCO Clear Enable - Uint16 rsvd2:6; // 8:3 Reserved - Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear - Uint16 LSYNCCLREN:1; // 10 Low Comparator EPWMSYNCO Clear Enable - Uint16 rsvd3:5; // 15:11 Reserved -}; - -union COMPSTSCLR_REG { - Uint16 all; - struct COMPSTSCLR_BITS bit; -}; - -struct COMPDACCTL_BITS { // bits description - Uint16 DACSOURCE:1; // 0 DAC Source Control - Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control - Uint16 SELREF:1; // 5 DAC Reference Select - Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select - Uint16 SWLOADSEL:1; // 7 Software Load Select - Uint16 BLANKSOURCE:4; // 11:8 EPWMBLANK Source Select - Uint16 BLANKEN:1; // 12 EPWMBLANK Enable - Uint16 rsvd1:1; // 13 Reserved - Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits -}; - -union COMPDACCTL_REG { - Uint16 all; - struct COMPDACCTL_BITS bit; -}; - -struct DACHVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALS_REG { - Uint16 all; - struct DACHVALS_BITS bit; -}; - -struct DACHVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALA_REG { - Uint16 all; - struct DACHVALA_BITS bit; -}; - -struct DACLVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALS_REG { - Uint16 all; - struct DACLVALS_BITS bit; -}; - -struct DACLVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALA_REG { - Uint16 all; - struct DACLVALA_BITS bit; -}; - -struct RAMPDLYA_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYA_REG { - Uint16 all; - struct RAMPDLYA_BITS bit; -}; - -struct RAMPDLYS_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYS_REG { - Uint16 all; - struct RAMPDLYS_BITS bit; -}; - -struct CTRIPLFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPLFILCTL_REG { - Uint16 all; - struct CTRIPLFILCTL_BITS bit; -}; - -struct CTRIPLFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPLFILCLKCTL_REG { - Uint16 all; - struct CTRIPLFILCLKCTL_BITS bit; -}; - -struct CTRIPHFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPHFILCTL_REG { - Uint16 all; - struct CTRIPHFILCTL_BITS bit; -}; - -struct CTRIPHFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPHFILCLKCTL_REG { - Uint16 all; - struct CTRIPHFILCLKCTL_BITS bit; -}; - -struct COMPLOCK_BITS { // bits description - Uint16 COMPCTL:1; // 0 COMPCTL Lock - Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock - Uint16 DACCTL:1; // 2 DACCTL Lock - Uint16 CTRIP:1; // 3 CTRIP Lock - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union COMPLOCK_REG { - Uint16 all; - struct COMPLOCK_BITS bit; -}; - -struct CMPSS_REGS { - union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register - union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register - union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register - union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register - union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register - Uint16 rsvd1; // Reserved - union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register - union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register - Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register - Uint16 rsvd2; // Reserved - Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register - Uint16 rsvd3; // Reserved - Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register - Uint16 rsvd4; // Reserved - Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register - Uint16 rsvd5; // Reserved - Uint16 RAMPSTS; // CMPSS Ramp Status Register - Uint16 rsvd6; // Reserved - union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register - union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register - union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register - union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register - union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register - union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register - union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register - union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register - union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register - Uint16 rsvd7[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CMPSS External References & Function Declarations: -// -extern volatile struct CMPSS_REGS Cmpss1Regs; -extern volatile struct CMPSS_REGS Cmpss2Regs; -extern volatile struct CMPSS_REGS Cmpss3Regs; -extern volatile struct CMPSS_REGS Cmpss4Regs; -extern volatile struct CMPSS_REGS Cmpss5Regs; -extern volatile struct CMPSS_REGS Cmpss6Regs; -extern volatile struct CMPSS_REGS Cmpss7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h deleted file mode 100644 index 378c166..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_cputimer.h +++ /dev/null @@ -1,134 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_cputimer.h -// -// TITLE: CPUTIMER Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_CPUTIMER_H__ -#define __F28004X_CPUTIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CPUTIMER Individual Register Bit Definitions: - -struct TIM_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers - Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High -}; - -union TIM_REG { - Uint32 all; - struct TIM_BITS bit; -}; - -struct PRD_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Period Registers - Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High -}; - -union PRD_REG { - Uint32 all; - struct PRD_BITS bit; -}; - -struct TCR_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 TSS:1; // 4 CPU-Timer stop status bit. - Uint16 TRB:1; // 5 Timer reload - Uint16 rsvd2:4; // 9:6 Reserved - Uint16 SOFT:1; // 10 Emulation modes - Uint16 FREE:1; // 11 Emulation modes - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. - Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. -}; - -union TCR_REG { - Uint16 all; - struct TCR_BITS bit; -}; - -struct TPR_BITS { // bits description - Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPR_REG { - Uint16 all; - struct TPR_BITS bit; -}; - -struct TPRH_BITS { // bits description - Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPRH_REG { - Uint16 all; - struct TPRH_BITS bit; -}; - -struct CPUTIMER_REGS { - union TIM_REG TIM; // CPU-Timer, Counter Register - union PRD_REG PRD; // CPU-Timer, Period Register - union TCR_REG TCR; // CPU-Timer, Control Register - Uint16 rsvd1; // Reserved - union TPR_REG TPR; // CPU-Timer, Prescale Register - union TPRH_REG TPRH; // CPU-Timer, Prescale Register High -}; - -//--------------------------------------------------------------------------- -// CPUTIMER External References & Function Declarations: -// -extern volatile struct CPUTIMER_REGS CpuTimer0Regs; -extern volatile struct CPUTIMER_REGS CpuTimer1Regs; -extern volatile struct CPUTIMER_REGS CpuTimer2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h deleted file mode 100644 index d76444d..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dac.h +++ /dev/null @@ -1,156 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dac.h -// -// TITLE: DAC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DAC_H__ -#define __F28004X_DAC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DAC Individual Register Bit Definitions: - -struct DACREV_BITS { // bits description - Uint16 REV:8; // 7:0 DAC Revision Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union DACREV_REG { - Uint16 all; - struct DACREV_BITS bit; -}; - -struct DACCTL_BITS { // bits description - Uint16 DACREFSEL:1; // 0 DAC Reference Select - Uint16 MODE:1; // 1 DAC Mode Select - Uint16 LOADMODE:1; // 2 DACVALA Load Mode - Uint16 rsvd1:1; // 3 Reserved - Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union DACCTL_REG { - Uint16 all; - struct DACCTL_BITS bit; -}; - -struct DACVALA_BITS { // bits description - Uint16 DACVALA:12; // 11:0 DAC Active Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALA_REG { - Uint16 all; - struct DACVALA_BITS bit; -}; - -struct DACVALS_BITS { // bits description - Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALS_REG { - Uint16 all; - struct DACVALS_BITS bit; -}; - -struct DACOUTEN_BITS { // bits description - Uint16 DACOUTEN:1; // 0 DAC Output Code - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union DACOUTEN_REG { - Uint16 all; - struct DACOUTEN_BITS bit; -}; - -struct DACLOCK_BITS { // bits description - Uint16 DACCTL:1; // 0 DAC Control Register Lock - Uint16 DACVAL:1; // 1 DAC Value Register Lock - Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock - Uint16 rsvd1:9; // 11:3 Reserved - Uint16 KEY:4; // 15:12 DAC Register Lock Key -}; - -union DACLOCK_REG { - Uint16 all; - struct DACLOCK_BITS bit; -}; - -struct DACTRIM_BITS { // bits description - Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim - Uint16 rsvd1:4; // 11:8 Reserved - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union DACTRIM_REG { - Uint16 all; - struct DACTRIM_BITS bit; -}; - -struct DAC_REGS { - union DACREV_REG DACREV; // DAC Revision Register - union DACCTL_REG DACCTL; // DAC Control Register - union DACVALA_REG DACVALA; // DAC Value Register - Active - union DACVALS_REG DACVALS; // DAC Value Register - Shadow - union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register - union DACLOCK_REG DACLOCK; // DAC Lock Register - union DACTRIM_REG DACTRIM; // DAC Trim Register - Uint16 rsvd1; // Reserved -}; - -//--------------------------------------------------------------------------- -// DAC External References & Function Declarations: -// -extern volatile struct DAC_REGS DacaRegs; -extern volatile struct DAC_REGS DacbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h deleted file mode 100644 index e422cf2..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcc.h +++ /dev/null @@ -1,203 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dcc.h -// -// TITLE: DCC Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DCC_H__ -#define __F28004X_DCC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCC Individual Register Bit Definitions: - -struct DCCGCTRL_BITS { // bits description - bp_16 DCCENA:4; // 3:0 DCC Enable - bp_16 ERRENA:4; // 7:4 Error Enable - bp_16 SINGLESHOT:4; // 11:8 Single-Shot Enable - bp_16 DONEENA:4; // 15:12 DONE Enable - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCGCTRL_REG { - bp_32 all; - struct DCCGCTRL_BITS bit; -}; - -struct DCCREV_BITS { // bits description - bp_16 MINOR:6; // 5:0 Minor Revision Number - bp_16 CUSTOM:2; // 7:6 Custom Module Number - bp_16 MAJOR:3; // 10:8 Major Revision Number - bp_16 RTL:5; // 15:11 Design Release Number - bp_32 FUNC:12; // 27:16 Functional Release Number - bp_32 rsvd1:2; // 29:28 Reserved - bp_32 SCHEME:2; // 31:30 Defines Scheme for Module -}; - -union DCCREV_REG { - bp_32 all; - struct DCCREV_BITS bit; -}; - -struct DCCCNTSEED0_BITS { // bits description - bp_32 COUNTSEED0:20; // 19:0 Seed Value for Counter 0 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNTSEED0_REG { - bp_32 all; - struct DCCCNTSEED0_BITS bit; -}; - -struct DCCVALIDSEED0_BITS { // bits description - bp_16 VALIDSEED:16; // 15:0 Seed Value for Valid Duration Counter 0 - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCVALIDSEED0_REG { - bp_32 all; - struct DCCVALIDSEED0_BITS bit; -}; - -struct DCCCNTSEED1_BITS { // bits description - bp_32 COUNTSEED1:20; // 19:0 Seed Value for Counter 1 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNTSEED1_REG { - bp_32 all; - struct DCCCNTSEED1_BITS bit; -}; - -struct DCCSTATUS_BITS { // bits description - bp_16 ERR:1; // 0 Error Flag - bp_16 DONE:1; // 1 Single-Shot Done Flag - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCSTATUS_REG { - bp_32 all; - struct DCCSTATUS_BITS bit; -}; - -struct DCCCNT0_BITS { // bits description - bp_32 COUNT0:20; // 19:0 Current Value of Counter 0 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNT0_REG { - bp_32 all; - struct DCCCNT0_BITS bit; -}; - -struct DCCVALID0_BITS { // bits description - bp_16 VALID0:16; // 15:0 Current Value of Valid 0 - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union DCCVALID0_REG { - bp_32 all; - struct DCCVALID0_BITS bit; -}; - -struct DCCCNT1_BITS { // bits description - bp_32 COUNT1:20; // 19:0 Current Value of Counter 1 - bp_32 rsvd1:12; // 31:20 Reserved -}; - -union DCCCNT1_REG { - bp_32 all; - struct DCCCNT1_BITS bit; -}; - -struct DCCCLKSRC1_BITS { // bits description - bp_16 CLKSRC1:4; // 3:0 Clock Source Select for Counter 1 - bp_16 rsvd1:8; // 11:4 Reserved - bp_16 KEY:4; // 15:12 Enables or Disables Clock Source Selection for COUNT1 - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCCLKSRC1_REG { - bp_32 all; - struct DCCCLKSRC1_BITS bit; -}; - -struct DCCCLKSRC0_BITS { // bits description - bp_16 CLKSRC0:4; // 3:0 Clock Source Select for Counter 0 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union DCCCLKSRC0_REG { - bp_32 all; - struct DCCCLKSRC0_BITS bit; -}; - -struct DCC_REGS { - union DCCGCTRL_REG DCCGCTRL; // Global Control Register - union DCCREV_REG DCCREV; // DCC Revision Register - union DCCCNTSEED0_REG DCCCNTSEED0; // Counter 0 seed value - union DCCVALIDSEED0_REG DCCVALIDSEED0; // Valid 0 seed value - union DCCCNTSEED1_REG DCCCNTSEED1; // Counter 1 Seed Value - union DCCSTATUS_REG DCCSTATUS; // DCC Status - union DCCCNT0_REG DCCCNT0; // Counter 0 Value - union DCCVALID0_REG DCCVALID0; // Valid Value 0 - union DCCCNT1_REG DCCCNT1; // Counter 1 Value - union DCCCLKSRC1_REG DCCCLKSRC1; // Clock Source 1 - union DCCCLKSRC0_REG DCCCLKSRC0; // Clock Source 0 -}; - -//--------------------------------------------------------------------------- -// DCC External References & Function Declarations: -// -extern volatile struct DCC_REGS Dcc0Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h deleted file mode 100644 index 87c1033..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dcsm.h +++ /dev/null @@ -1,658 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dcsm.h -// -// TITLE: DCSM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DCSM_H__ -#define __F28004X_DCSM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCSM Individual Register Bit Definitions: - -struct B0_Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer for zone Flash BANK0 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z1_LINKPOINTER_REG { - Uint32 all; - struct B0_Z1_LINKPOINTER_BITS bit; -}; - -struct Z1_OTPSECLOCK_BITS { // bits description - Uint16 JTAGLOCK:4; // 3:0 Zone1 JTAG Lock. - Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_OTPSECLOCK_REG { - Uint32 all; - struct Z1_OTPSECLOCK_BITS bit; -}; - -struct B0_Z1_LINKPOINTERERR_BITS { // bits description - Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z1_LINKPOINTERERR_REG { - Uint32 all; - struct B0_Z1_LINKPOINTERERR_BITS bit; -}; - -struct Z1_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Passwords Read Status - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z1_CR_REG { - Uint16 all; - struct Z1_CR_BITS bit; -}; - -struct B0_Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK0 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK0 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK0 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK0 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK0 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK0 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK0 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK0 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK0 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK0 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK0 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK0 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK0 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK0 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK0 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK0 -}; - -union B0_Z1_GRABSECTR_REG { - Uint32 all; - struct B0_Z1_GRABSECTR_BITS bit; -}; - -struct Z1_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union Z1_GRABRAMR_REG { - Uint32 all; - struct Z1_GRABRAMR_BITS bit; -}; - -struct B0_Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B0_Z1_EXEONLYSECTR_REG { - Uint32 all; - struct B0_Z1_EXEONLYSECTR_BITS bit; -}; - -struct Z1_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_EXEONLYRAMR_REG { - Uint32 all; - struct Z1_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_BANK0_Z1_REGS { - union B0_Z1_LINKPOINTER_REG B0_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK0 - union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock - Uint32 Z1_BOOTDEF_HIGH; // Boot definition (high 32bit) - union B0_Z1_LINKPOINTERERR_REG B0_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK0 - Uint32 Z1_BOOTPIN_CONFIG; // Boot Pin Configuration - Uint32 Z1_GPREG2; // Zone1 General Purpose Register-2 - Uint32 Z1_BOOTDEF_LOW; // Boot definition (low 32bit) - Uint16 rsvd1[2]; // Reserved - Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 - Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 - Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 - Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 - Uint16 rsvd2; // Reserved - union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register - union B0_Z1_GRABSECTR_REG B0_Z1_GRABSECTR; // Zone 1 Grab Flash BANK0 Sectors Register - union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register - union B0_Z1_EXEONLYSECTR_REG B0_Z1_EXEONLYSECTR; // Zone 1 Flash BANK0 Execute_Only Sector Register - union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register - Uint16 rsvd3; // Reserved -}; - -struct B0_Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK0 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z2_LINKPOINTER_REG { - Uint32 all; - struct B0_Z2_LINKPOINTER_BITS bit; -}; - -struct Z2_OTPSECLOCK_BITS { // bits description - Uint16 JTAGLOCK:4; // 3:0 Zone2 JTAG Lock. - Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_OTPSECLOCK_REG { - Uint32 all; - struct Z2_OTPSECLOCK_BITS bit; -}; - -struct B0_Z2_LINKPOINTERERR_BITS { // bits description - Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B0_Z2_LINKPOINTERERR_REG { - Uint32 all; - struct B0_Z2_LINKPOINTERERR_BITS bit; -}; - -struct Z2_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Passwords Read Status - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z2_CR_REG { - Uint16 all; - struct Z2_CR_BITS bit; -}; - -struct B0_Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK0 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK0 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK0 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK0 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK0 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK0 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK0 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK0 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK0 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK0 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK0 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK0 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK0 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK0 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK0 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK0 -}; - -union B0_Z2_GRABSECTR_REG { - Uint32 all; - struct B0_Z2_GRABSECTR_BITS bit; -}; - -struct Z2_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union Z2_GRABRAMR_REG { - Uint32 all; - struct Z2_GRABRAMR_BITS bit; -}; - -struct B0_Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B0_Z2_EXEONLYSECTR_REG { - Uint32 all; - struct B0_Z2_EXEONLYSECTR_BITS bit; -}; - -struct Z2_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_EXEONLYRAMR_REG { - Uint32 all; - struct Z2_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_BANK0_Z2_REGS { - union B0_Z2_LINKPOINTER_REG B0_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK0 - union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock - Uint16 rsvd1[2]; // Reserved - union B0_Z2_LINKPOINTERERR_REG B0_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK0 - Uint16 rsvd2[8]; // Reserved - Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 - Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 - Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 - Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 - Uint16 rsvd3; // Reserved - union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register - union B0_Z2_GRABSECTR_REG B0_Z2_GRABSECTR; // Zone 2 Grab Flash BANK0 Sectors Register - union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register - union B0_Z2_EXEONLYSECTR_REG B0_Z2_EXEONLYSECTR; // Zone 2 Flash BANK0 Execute_Only Sector Register - union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register - Uint16 rsvd4; // Reserved -}; - -struct FLSEM_BITS { // bits description - Uint16 SEM:2; // 1:0 Flash Semaphore Bit - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Semaphore Key - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FLSEM_REG { - Uint32 all; - struct FLSEM_BITS bit; -}; - -struct B0_SECTSTAT_BITS { // bits description - Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK0 Sector 0 - Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK0 sector 1 - Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK0 Sector 2 - Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK0 Sector 3 - Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK0 Sector 4 - Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK0 Sector 5 - Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK0 Sector 6 - Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK0 Sector 7 - Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK0 sector 8 - Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK0 Sector 9 - Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK0 Sector 10 - Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK0 Sector 11 - Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK0 Sector 12 - Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK0 Sector 13 - Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK0 Sector 14 - Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK0 Sector 15 -}; - -union B0_SECTSTAT_REG { - Uint32 all; - struct B0_SECTSTAT_BITS bit; -}; - -struct RAMSTAT_BITS { // bits description - Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 - Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 - Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 - Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 - Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 - Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 - Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM LS6 - Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM LS7 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union RAMSTAT_REG { - Uint32 all; - struct RAMSTAT_BITS bit; -}; - -struct B1_SECTSTAT_BITS { // bits description - Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK1 Sector 0 - Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK1 sector 1 - Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK1 Sector 2 - Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK1 Sector 3 - Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK1 Sector 4 - Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK1 Sector 5 - Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK1 Sector 6 - Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK1 Sector 7 - Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK1 sector 8 - Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK1 Sector 9 - Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK1 Sector 10 - Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK1 Sector 11 - Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK1 Sector 12 - Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK1 Sector 13 - Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK1 Sector 14 - Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK1 Sector 15 -}; - -union B1_SECTSTAT_REG { - Uint32 all; - struct B1_SECTSTAT_BITS bit; -}; - -struct SECERRSTAT_BITS { // bits description - Uint16 ERR:1; // 0 Security Configuration load Error Status - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRSTAT_REG { - Uint32 all; - struct SECERRSTAT_BITS bit; -}; - -struct SECERRCLR_BITS { // bits description - Uint16 ERR:1; // 0 Clear Security Configuration Load Error Status Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRCLR_REG { - Uint32 all; - struct SECERRCLR_BITS bit; -}; - -struct SECERRFRC_BITS { // bits description - Uint16 ERR:1; // 0 Set Security Configuration Load Error Status Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SECERRFRC_REG { - Uint32 all; - struct SECERRFRC_BITS bit; -}; - -struct DCSM_COMMON_REGS { - union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register - union B0_SECTSTAT_REG B0_SECTSTAT; // Flash BANK0 Sectors Status Register - union RAMSTAT_REG RAMSTAT; // RAM Status Register - Uint16 rsvd1[2]; // Reserved - union B1_SECTSTAT_REG B1_SECTSTAT; // Flash BANK1 Sectors Status Register - union SECERRSTAT_REG SECERRSTAT; // Security Error Status Register - union SECERRCLR_REG SECERRCLR; // Security Error Clear Register - union SECERRFRC_REG SECERRFRC; // Security Error Force Register -}; - -struct B1_Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer in Flash BANK1 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z1_LINKPOINTER_REG { - Uint32 all; - struct B1_Z1_LINKPOINTER_BITS bit; -}; - -struct B1_Z1_LINKPOINTERERR_BITS { // bits description - Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z1_LINKPOINTERERR_REG { - Uint32 all; - struct B1_Z1_LINKPOINTERERR_BITS bit; -}; - -struct B1_Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK1 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK1 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK1 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK1 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK1 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK1 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK1 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK1 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK1 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK1 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK1 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK1 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK1 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK1 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK1 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK1 -}; - -union B1_Z1_GRABSECTR_REG { - Uint32 all; - struct B1_Z1_GRABSECTR_BITS bit; -}; - -struct B1_Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B1_Z1_EXEONLYSECTR_REG { - Uint32 all; - struct B1_Z1_EXEONLYSECTR_BITS bit; -}; - -struct DCSM_BANK1_Z1_REGS { - union B1_Z1_LINKPOINTER_REG B1_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK1 - Uint16 rsvd1[4]; // Reserved - union B1_Z1_LINKPOINTERERR_REG B1_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK1 - Uint16 rsvd2[18]; // Reserved - union B1_Z1_GRABSECTR_REG B1_Z1_GRABSECTR; // Zone 1 Grab Flash BANK1 Sectors Register - Uint16 rsvd3[2]; // Reserved - union B1_Z1_EXEONLYSECTR_REG B1_Z1_EXEONLYSECTR; // Zone 1 Flash BANK1 Execute_Only Sector Register - Uint16 rsvd4[3]; // Reserved -}; - -struct B1_Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK1 - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z2_LINKPOINTER_REG { - Uint32 all; - struct B1_Z2_LINKPOINTER_BITS bit; -}; - -struct B1_Z2_LINKPOINTERERR_BITS { // bits description - Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union B1_Z2_LINKPOINTERERR_REG { - Uint32 all; - struct B1_Z2_LINKPOINTERERR_BITS bit; -}; - -struct B1_Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK1 - Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK1 - Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK1 - Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK1 - Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK1 - Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK1 - Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK1 - Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK1 - Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK1 - Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK1 - Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK1 - Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK1 - Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK1 - Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK1 - Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK1 - Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK1 -}; - -union B1_Z2_GRABSECTR_REG { - Uint32 all; - struct B1_Z2_GRABSECTR_BITS bit; -}; - -struct B1_Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 - Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 - Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 - Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 - Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 - Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 - Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 - Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 - Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 - Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 - Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 - Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 - Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 - Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 - Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 - Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union B1_Z2_EXEONLYSECTR_REG { - Uint32 all; - struct B1_Z2_EXEONLYSECTR_BITS bit; -}; - -struct DCSM_BANK1_Z2_REGS { - union B1_Z2_LINKPOINTER_REG B1_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK1 - Uint16 rsvd1[4]; // Reserved - union B1_Z2_LINKPOINTERERR_REG B1_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK1 - Uint16 rsvd2[18]; // Reserved - union B1_Z2_GRABSECTR_REG B1_Z2_GRABSECTR; // Zone 2 Grab Flash BANK1 Sectors Register - Uint16 rsvd3[2]; // Reserved - union B1_Z2_EXEONLYSECTR_REG B1_Z2_EXEONLYSECTR; // Zone 2 Flash BANK1 Execute_Only Sector Register - Uint16 rsvd4[3]; // Reserved -}; - -//--------------------------------------------------------------------------- -// DCSM External References & Function Declarations: -// -extern volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; -extern volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; -extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; -extern volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; -extern volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h deleted file mode 100644 index 9548456..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_device.h +++ /dev/null @@ -1,276 +0,0 @@ -//########################################################################### -// -// FILE: F28004x_device.h -// -// TITLE: F28004x Device Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_DEVICE_H -#define F28004X_DEVICE_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Common CPU Definitions: -// -#ifdef __TMS320C28XX_CLA__ -// -// There are only two assembly instructions that can access the MSTF register -// - MMOV32 mem32, MSTF -// - MMOV32 mem32, MSTF -// The CLA C compiler allows 'C' access to this control register through the __cregister -// keyword. In order to access the register's contents, the user must copy it to the -// shadow object defined below -// Note that _MSTF is the only __cregister recognized by the CLA C compiler; IER and IFR -// are not accessible (therefore not recognized), therefore __cregister must be redefined to -// null to prevent a cla C compiler error -// -struct MSTF_SHADOW_BITS { // bits description - unsigned short LVF:1; // 0 Latched Overflow Flag - unsigned short LUF:1; // 1 Latched Underflow Flag - unsigned short NF:1; // 2 Negative Float Flag - unsigned short ZF:1; // 3 Zero Float Flag - unsigned short rsvd1:2; // 5:4 Reserved - unsigned short TF:1; // 6 Test Flag - unsigned short rsvd2:2; // 8:7 Reserved - unsigned short RNDF32:1; // 9 Rounding Mode - unsigned short rsvd3:1; // 10 Reserved - unsigned short MEALLOW:1; // 11 MEALLOW Status - unsigned short RPCL:4; // 15:12 Return PC: Low Portion - unsigned short RPCH:12; // 27:16 Return PC: High Portion - unsigned short rsvd4:4; // 31:28 Reserved -}; -extern __cregister volatile unsigned int MSTF; -#endif //__TMS320C28XX_CLA__ - -#ifndef __TMS320C28XX__ -#define __cregister -#endif //__TMS320C28xx__ - -extern __cregister volatile unsigned int IFR; -extern __cregister volatile unsigned int IER; - -#define EINT __asm(" clrc INTM") -#define DINT __asm(" setc INTM") -#define ERTM __asm(" clrc DBGM") -#define DRTM __asm(" setc DBGM") -#define EALLOW __eallow() -#define EDIS __edis() -#define ESTOP0 __asm(" ESTOP0") - -#define M_INT1 0x0001 -#define M_INT2 0x0002 -#define M_INT3 0x0004 -#define M_INT4 0x0008 -#define M_INT5 0x0010 -#define M_INT6 0x0020 -#define M_INT7 0x0040 -#define M_INT8 0x0080 -#define M_INT9 0x0100 -#define M_INT10 0x0200 -#define M_INT11 0x0400 -#define M_INT12 0x0800 -#define M_INT13 0x1000 -#define M_INT14 0x2000 -#define M_DLOG 0x4000 -#define M_RTOS 0x8000 - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -// -// For Portability, User Is Recommended To Use the C99 Standard integer types -// -#if !defined(__TMS320C28XX_CLA__) -#include -#include -#endif //__TMS320C28XX_CLA__ -#include -#include -#include - -#if defined(__cplusplus) -typedef bool _Bool; -#endif - -// -// C99 defines boolean type to be _Bool, but this doesn't match the format of -// the other standard integer types. bool_t has been defined to fill this gap. -// -typedef _Bool bool_t; - -// -// Used for a bool function return status -// -typedef _Bool status_t; - -#ifndef SUCCESS -#define SUCCESS true -#endif - -#ifndef FAIL -#define FAIL false -#endif - -// -// The following data types are included for compatibility with legacy code, -// they are not recommended for use in new software. Please use the C99 -// types included above -// -#if (!defined(DSP28_DATA_TYPES) && !defined(F28_DATA_TYPES)) -#define DSP28_DATA_TYPES -#define F28_DATA_TYPES - -#ifdef __TMS320C28XX_CLA__ -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else // __TMS320C28XX__ -typedef int int16; -typedef long int32; -typedef long long int64; -typedef unsigned int Uint16; -typedef unsigned long Uint32; -typedef unsigned long long Uint64; -typedef float float32; -typedef long double float64; -#endif //__TMS320C28XX_CLA__ - -#endif //(!defined(DSP28_DATA_TYPES) && !defined(F28_DATA_TYPES)) - -// -// The following data types are for use with byte addressable peripherals. -// See compiler documentation on the byte_peripheral type attribute. -// -#ifndef __TMS320C28XX_CLA__ -typedef unsigned int bp_16 __attribute__((byte_peripheral)); -typedef unsigned long bp_32 __attribute__((byte_peripheral)); -#endif - -// -// Include All Peripheral Header Files: -// -#include "f28004x_adc.h" -#include "f28004x_analogsubsys.h" -#include "f28004x_cla.h" -#include "f28004x_cla_prom_crc32.h" -#include "f28004x_cmpss.h" -#include "f28004x_cputimer.h" -#include "f28004x_dac.h" -#include "f28004x_dcsm.h" -#include "f28004x_dma.h" -#include "f28004x_ecap.h" -#include "f28004x_epwm.h" -#include "f28004x_epwm_xbar.h" -#include "f28004x_eqep.h" -#include "f28004x_erad.h" -#include "f28004x_flash.h" -#include "f28004x_fsi.h" -#include "f28004x_gpio.h" -#include "f28004x_i2c.h" -#include "f28004x_input_xbar.h" -#include "f28004x_memconfig.h" -#include "f28004x_nmiintrupt.h" -#include "f28004x_output_xbar.h" -#include "f28004x_pga.h" -#include "f28004x_piectrl.h" -#include "f28004x_pievect.h" -#include "f28004x_pmbus.h" -#include "f28004x_sci.h" -#include "f28004x_sdfm.h" -#include "f28004x_spi.h" -#include "f28004x_sysctrl.h" -#include "f28004x_xbar.h" -#include "f28004x_xint.h" - -// -// byte_peripheral attribute is only supported on the C28 -// -#ifndef __TMS320C28XX_CLA__ -#include "f28004x_can.h" -#include "f28004x_dcc.h" -#include "f28004x_lin.h" -#endif - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F28004X_DEVICE_H definition - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h deleted file mode 100644 index ffc9ec8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_dma.h +++ /dev/null @@ -1,214 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_dma.h -// -// TITLE: F28004x Device DMA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_DMA_H__ -#define __F28004X_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DMA Individual Register Bit Definitions: - -struct MODE_BITS { // bits description - Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable - Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable - Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode - Uint16 ONESHOT:1; // 10 One Shot Mode Bit - Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 DATASIZE:1; // 14 Data Size Mode Bit - Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit -}; - -union MODE_REG { - Uint16 all; - struct MODE_BITS bit; -}; - -struct CONTROL_BITS { // bits description - Uint16 RUN:1; // 0 Run Bit - Uint16 HALT:1; // 1 Halt Bit - Uint16 SOFTRESET:1; // 2 Soft Reset Bit - Uint16 PERINTFRC:1; // 3 Interrupt Force Bit - Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 ERRCLR:1; // 7 Error Clear Bit - Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit - Uint16 SYNCFLG:1; // 9 Sync Flag Bit - Uint16 SYNCERR:1; // 10 Sync Error Flag Bit - Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit - Uint16 BURSTSTS:1; // 12 Burst Status Bit - Uint16 RUNSTS:1; // 13 Run Status Bit - Uint16 OVRFLG:1; // 14 Overflow Flag Bit - Uint16 rsvd1:1; // 15 Reserved -}; - -union CONTROL_REG { - Uint16 all; - struct CONTROL_BITS bit; -}; - -struct DMACTRL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset Bit - Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union DMACTRL_REG { - Uint16 all; - struct DMACTRL_BITS bit; -}; - -struct DEBUGCTRL_BITS { // bits description - Uint16 rsvd1:15; // 14:0 Reserved - Uint16 FREE:1; // 15 Debug Mode Bit -}; - -union DEBUGCTRL_REG { - Uint16 all; - struct DEBUGCTRL_BITS bit; -}; - -struct PRIORITYCTRL1_BITS { // bits description - Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union PRIORITYCTRL1_REG { - Uint16 all; - struct PRIORITYCTRL1_BITS bit; -}; - -struct PRIORITYSTAT_BITS { // bits description - Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits - Uint16 rsvd1:1; // 3 Reserved - Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union PRIORITYSTAT_REG { - Uint16 all; - struct PRIORITYSTAT_BITS bit; -}; - -struct BURST_SIZE_BITS { // bits description - Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_SIZE_REG { - Uint16 all; - struct BURST_SIZE_BITS bit; -}; - -struct BURST_COUNT_BITS { // bits description - Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_COUNT_REG { - Uint16 all; - struct BURST_COUNT_BITS bit; -}; - -struct CH_REGS { - union MODE_REG MODE; // Mode Register - union CONTROL_REG CONTROL; // Control Register - union BURST_SIZE_REG BURST_SIZE; // Burst Size Register - union BURST_COUNT_REG BURST_COUNT; // Burst Count Register - int16 SRC_BURST_STEP; // Source Burst Step Register - int16 DST_BURST_STEP; // Destination Burst Step Register - Uint16 TRANSFER_SIZE; // Transfer Size Register - Uint16 TRANSFER_COUNT; // Transfer Count Register - int16 SRC_TRANSFER_STEP; // Source Transfer Step Register - int16 DST_TRANSFER_STEP; // Destination Transfer Step Register - Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register - Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register - int16 SRC_WRAP_STEP; // Source Wrap Step Register - Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register - Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register - int16 DST_WRAP_STEP; // Destination Wrap Step Register - Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register - Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register - Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register - Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register - Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register - Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register - Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register - Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register -}; - -struct DMA_REGS { - union DMACTRL_REG DMACTRL; // DMA Control Register - union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register - Uint16 rsvd0; // Reserved - Uint16 rsvd1; // Reserved - union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register - Uint16 rsvd2; // Reserved - union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register - Uint16 rsvd3[25]; // Reserved - struct CH_REGS CH1; // DMA Channel 1 Registers - struct CH_REGS CH2; // DMA Channel 2 Registers - struct CH_REGS CH3; // DMA Channel 3 Registers - struct CH_REGS CH4; // DMA Channel 4 Registers - struct CH_REGS CH5; // DMA Channel 5 Registers - struct CH_REGS CH6; // DMA Channel 6 Registers -}; - -//--------------------------------------------------------------------------- -// DMA External References & Function Declarations: -// -extern volatile struct DMA_REGS DmaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h deleted file mode 100644 index a6e3605..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_ecap.h +++ /dev/null @@ -1,309 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_ecap.h -// -// TITLE: ECAP Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ECAP_H__ -#define __F28004X_ECAP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ECAP Individual Register Bit Definitions: - -struct ECCTL0_BITS { // bits description - Uint16 INPUTSEL:7; // 6:0 INPUT source select - Uint16 rsvd1:9; // 15:7 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECCTL0_REG { - Uint32 all; - struct ECCTL0_BITS bit; -}; - -struct ECCTL1_BITS { // bits description - Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select - Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 - Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select - Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 - Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select - Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 - Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select - Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 - Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event - Uint16 PRESCALE:5; // 13:9 Event Filter prescale select - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union ECCTL1_REG { - Uint16 all; - struct ECCTL1_BITS bit; -}; - -struct ECCTL2_BITS { // bits description - Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot - Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous - Uint16 REARM:1; // 3 One-shot re-arm - Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop - Uint16 SYNCI_EN:1; // 5 Counter sync-in select - Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode - Uint16 SWSYNC:1; // 8 SW forced counter sync - Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select - Uint16 APWMPOL:1; // 10 APWM output polarity select - Uint16 CTRFILTRESET:1; // 11 Reset event filter, modulus counter, and interrupt flags. - Uint16 DMAEVTSEL:2; // 13:12 DMA event select - Uint16 MODCNTRSTS:2; // 15:14 modulo counter status -}; - -union ECCTL2_REG { - Uint16 all; - struct ECCTL2_BITS bit; -}; - -struct ECEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable - Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable - Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:7; // 15:9 Reserved -}; - -union ECEINT_REG { - Uint16 all; - struct ECEINT_BITS bit; -}; - -struct ECFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Flag - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag - Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag - Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union ECFLG_REG { - Uint16 all; - struct ECFLG_BITS bit; -}; - -struct ECCLR_BITS { // bits description - Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear - Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear - Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear - Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear - Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear - Uint16 CTROVF:1; // 5 Counter Overflow Status Clear - Uint16 CTR_PRD:1; // 6 Period Equal Status Clear - Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union ECCLR_REG { - Uint16 all; - struct ECCLR_BITS bit; -}; - -struct ECFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt - Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt - Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt - Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt - Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt - Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt - Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:7; // 15:9 Reserved -}; - -union ECFRC_REG { - Uint16 all; - struct ECFRC_BITS bit; -}; - -struct ECAPSYNCINSEL_BITS { // bits description - Uint16 SEL:5; // 4:0 SYNCIN source select - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAPSYNCINSEL_REG { - Uint32 all; - struct ECAPSYNCINSEL_BITS bit; -}; - -struct ECAP_REGS { - Uint32 TSCTR; // Time-Stamp Counter - Uint32 CTRPHS; // Counter Phase Offset Value Register - Uint32 CAP1; // Capture 1 Register - Uint32 CAP2; // Capture 2 Register - Uint32 CAP3; // Capture 3 Register - Uint32 CAP4; // Capture 4 Register - Uint16 rsvd1[6]; // Reserved - union ECCTL0_REG ECCTL0; // Capture Control Register 0 - union ECCTL1_REG ECCTL1; // Capture Control Register 1 - union ECCTL2_REG ECCTL2; // Capture Control Register 2 - union ECEINT_REG ECEINT; // Capture Interrupt Enable Register - union ECFLG_REG ECFLG; // Capture Interrupt Flag Register - union ECCLR_REG ECCLR; // Capture Interrupt Clear Register - union ECFRC_REG ECFRC; // Capture Interrupt Force Register - Uint16 rsvd2[4]; // Reserved - union ECAPSYNCINSEL_REG ECAPSYNCINSEL; // SYNC source select register -}; - -struct HRCTL_BITS { // bits description - Uint16 HRE:1; // 0 High Resolution Enable - Uint16 HRCLKE:1; // 1 High Resolution Clock Enable - Uint16 PRDSEL:1; // 2 Calibration Period Match - Uint16 CALIBSTART:1; // 3 Calibration start - Uint16 CALIBSTS:1; // 4 Calibration status - Uint16 CALIBCONT:1; // 5 Continuous mode Calibration Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRCTL_REG { - Uint32 all; - struct HRCTL_BITS bit; -}; - -struct HRINTEN_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CALIBDONE:1; // 1 Calibration doe interrupt enable - Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status enable - Uint16 rsvd2:13; // 15:3 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union HRINTEN_REG { - Uint32 all; - struct HRINTEN_BITS bit; -}; - -struct HRFLG_BITS { // bits description - Uint16 CALIBINT:1; // 0 Global calibration Interrupt Status Flag - Uint16 CALIBDONE:1; // 1 Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status Flag Bi - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRFLG_REG { - Uint32 all; - struct HRFLG_BITS bit; -}; - -struct HRCLR_BITS { // bits description - Uint16 CALIBINT:1; // 0 Clear Global calibration Interrupt Flag - Uint16 CALIBDONE:1; // 1 Clear Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Clear Calibration period check status Flag Bit: - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRCLR_REG { - Uint32 all; - struct HRCLR_BITS bit; -}; - -struct HRFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CALIBDONE:1; // 1 Force Calibration Done Interrupt Flag Bit - Uint16 CALPRDCHKSTS:1; // 2 Force Calibration period check status Flag Bit: - Uint16 rsvd2:13; // 15:3 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union HRFRC_REG { - Uint32 all; - struct HRFRC_BITS bit; -}; - -struct HRCAP_REGS { - union HRCTL_REG HRCTL; // High-Res Control Register - Uint16 rsvd1[2]; // Reserved - union HRINTEN_REG HRINTEN; // High-Res Calibration Interrupt Enable Register - union HRFLG_REG HRFLG; // High-Res Calibration Interrupt Flag Register - union HRCLR_REG HRCLR; // High-Res Calibration Interrupt Clear Register - union HRFRC_REG HRFRC; // High-Res Calibration Interrupt Force Register - Uint32 HRCALPRD; // High-Res Calibration Period Register - Uint32 HRSYSCLKCTR; // High-Res Calibration SYSCLK Counter Register - Uint32 HRSYSCLKCAP; // High-Res Calibration SYSCLK Capture Register - Uint32 HRCLKCTR; // High-Res Calibration HRCLK Counter Register - Uint32 HRCLKCAP; // High-Res Calibration HRCLK Capture Register - Uint16 rsvd2[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ECAP External References & Function Declarations: -// -extern volatile struct ECAP_REGS ECap1Regs; -extern volatile struct ECAP_REGS ECap2Regs; -extern volatile struct ECAP_REGS ECap3Regs; -extern volatile struct ECAP_REGS ECap4Regs; -extern volatile struct ECAP_REGS ECap5Regs; -extern volatile struct ECAP_REGS ECap6Regs; -extern volatile struct ECAP_REGS ECap7Regs; -extern volatile struct HRCAP_REGS HRCap6Regs; -extern volatile struct HRCAP_REGS HRCap7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h deleted file mode 100644 index e7219dc..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm.h +++ /dev/null @@ -1,1237 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm.h -// -// TITLE: EPWM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EPWM_H__ -#define __F28004X_EPWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM Individual Register Bit Definitions: - -struct TBCTL_BITS { // bits description - Uint16 CTRMODE:2; // 1:0 Counter Mode - Uint16 PHSEN:1; // 2 Phase Load Enable - Uint16 PRDLD:1; // 3 Active Period Load - Uint16 SYNCOSEL:2; // 5:4 Sync Output Select - Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse - Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler - Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler - Uint16 PHSDIR:1; // 13 Phase Direction Bit - Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits -}; - -union TBCTL_REG { - Uint16 all; - struct TBCTL_BITS bit; -}; - -struct TBCTL2_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode - Uint16 OSHTSYNC:1; // 7 One shot sync - Uint16 rsvd3:4; // 11:8 Reserved - Uint16 SYNCOSELX:2; // 13:12 Syncout selection - Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event -}; - -union TBCTL2_REG { - Uint16 all; - struct TBCTL2_BITS bit; -}; - -struct TBSTS_BITS { // bits description - Uint16 CTRDIR:1; // 0 Counter Direction Status - Uint16 SYNCI:1; // 1 External Input Sync Status - Uint16 CTRMAX:1; // 2 Counter Max Latched Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union TBSTS_REG { - Uint16 all; - struct TBSTS_BITS bit; -}; - -struct CMPCTL_BITS { // bits description - Uint16 LOADAMODE:2; // 1:0 Active Compare A Load - Uint16 LOADBMODE:2; // 3:2 Active Compare B Load - Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status - Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status - Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC - Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL_REG { - Uint16 all; - struct CMPCTL_BITS bit; -}; - -struct CMPCTL2_BITS { // bits description - Uint16 LOADCMODE:2; // 1:0 Active Compare C Load - Uint16 LOADDMODE:2; // 3:2 Active Compare D load - Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode - Uint16 rsvd2:3; // 9:7 Reserved - Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC - Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL2_REG { - Uint16 all; - struct CMPCTL2_BITS bit; -}; - -struct DBCTL_BITS { // bits description - Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control - Uint16 POLSEL:2; // 3:2 Polarity Select Control - Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control - Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode - Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode - Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode - Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode - Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control - Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control - Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable -}; - -union DBCTL_REG { - Uint16 all; - struct DBCTL_BITS bit; -}; - -struct DBCTL2_BITS { // bits description - Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select - Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union DBCTL2_REG { - Uint16 all; - struct DBCTL2_BITS bit; -}; - -struct AQCTL_BITS { // bits description - Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select - Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select - Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC - Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC - Uint16 rsvd3:4; // 15:12 Reserved -}; - -union AQCTL_REG { - Uint16 all; - struct AQCTL_BITS bit; -}; - -struct AQTSRCSEL_BITS { // bits description - Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits - Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQTSRCSEL_REG { - Uint16 all; - struct AQTSRCSEL_BITS bit; -}; - -struct PCCTL_BITS { // bits description - Uint16 CHPEN:1; // 0 PWM chopping enable - Uint16 OSHTWTH:4; // 4:1 One-shot pulse width - Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency - Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union PCCTL_REG { - Uint16 all; - struct PCCTL_BITS bit; -}; - -struct VCAPCTL_BITS { // bits description - Uint16 VCAPE:1; // 0 Valley Capture mode - Uint16 VCAPSTART:1; // 1 Valley Capture Start - Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable - Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union VCAPCTL_REG { - Uint16 all; - struct VCAPCTL_BITS bit; -}; - -struct VCNTCFG_BITS { // bits description - Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection - Uint16 rsvd1:3; // 6:4 Reserved - Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit - Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit -}; - -union VCNTCFG_REG { - Uint16 all; - struct VCNTCFG_BITS bit; -}; - -struct HRCNFG_BITS { // bits description - Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits - Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits - Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits - Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit - Uint16 AUTOCONV:1; // 6 Autoconversion Bit - Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit - Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits - Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits - Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits - Uint16 rsvd1:1; // 13 Reserved - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union HRCNFG_REG { - Uint16 all; - struct HRCNFG_BITS bit; -}; - -struct HRPWR_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:4; // 9:6 Reserved - Uint16 rsvd7:5; // 14:10 Reserved - Uint16 CALPWRON:1; // 15 Calibration Power On -}; - -union HRPWR_REG { - Uint16 all; - struct HRPWR_BITS bit; -}; - -struct HRMSTEP_BITS { // bits description - Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union HRMSTEP_REG { - Uint16 all; - struct HRMSTEP_BITS bit; -}; - -struct HRCNFG2_BITS { // bits description - Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits - Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits - Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits - Uint16 rsvd1:8; // 13:6 Reserved - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union HRCNFG2_REG { - Uint16 all; - struct HRCNFG2_BITS bit; -}; - -struct HRPCTL_BITS { // bits description - Uint16 HRPE:1; // 0 High Resolution Period Enable - Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select - Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union HRPCTL_REG { - Uint16 all; - struct HRPCTL_BITS bit; -}; - -struct TRREM_BITS { // bits description - Uint16 TRREM:11; // 10:0 Translator Remainder Bits - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union TRREM_REG { - Uint16 all; - struct TRREM_BITS bit; -}; - -struct GLDCTL_BITS { // bits description - Uint16 GLD:1; // 0 Global Shadow to Active load event control - Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection - Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register - Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union GLDCTL_REG { - Uint16 all; - struct GLDCTL_BITS bit; -}; - -struct GLDCFG_BITS { // bits description - Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR - Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR - Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR - Uint16 CMPC:1; // 3 Global load event configuration for CMPC - Uint16 CMPD:1; // 4 Global load event configuration for CMPD - Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR - Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR - Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL - Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 - Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 - Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union GLDCFG_REG { - Uint16 all; - struct GLDCFG_BITS bit; -}; - -struct EPWMXLINK_BITS { // bits description - Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link - Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link - Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link - Uint16 CMPCLINK:4; // 15:12 CMPC Link - Uint16 CMPDLINK:4; // 19:16 CMPD Link - Uint16 rsvd1:8; // 27:20 Reserved - Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link -}; - -union EPWMXLINK_REG { - Uint32 all; - struct EPWMXLINK_BITS bit; -}; - -struct EPWMREV_BITS { // bits description - Uint16 REV:8; // 7:0 EPWM Silicon Revision bits - Uint16 TYPE:8; // 15:8 EPWM Type Bits -}; - -union EPWMREV_REG { - Uint16 all; - struct EPWMREV_BITS bit; -}; - -struct AQCTLA_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLA_REG { - Uint16 all; - struct AQCTLA_BITS bit; -}; - -struct AQCTLA2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLA2_REG { - Uint16 all; - struct AQCTLA2_BITS bit; -}; - -struct AQCTLB_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLB_REG { - Uint16 all; - struct AQCTLB_BITS bit; -}; - -struct AQCTLB2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLB2_REG { - Uint16 all; - struct AQCTLB2_BITS bit; -}; - -struct AQSFRC_BITS { // bits description - Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked - Uint16 OTSFA:1; // 2 One-time SW Force A Output - Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked - Uint16 OTSFB:1; // 5 One-time SW Force A Output - Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQSFRC_REG { - Uint16 all; - struct AQSFRC_BITS bit; -}; - -struct AQCSFRC_BITS { // bits description - Uint16 CSFA:2; // 1:0 Continuous Software Force on output A - Uint16 CSFB:2; // 3:2 Continuous Software Force on output B - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union AQCSFRC_REG { - Uint16 all; - struct AQCSFRC_BITS bit; -}; - -struct DBREDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits -}; - -union DBREDHR_REG { - Uint16 all; - struct DBREDHR_BITS bit; -}; - -struct DBRED_BITS { // bits description - Uint16 DBRED:14; // 13:0 Rising edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBRED_REG { - Uint16 all; - struct DBRED_BITS bit; -}; - -struct DBFEDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits -}; - -union DBFEDHR_REG { - Uint16 all; - struct DBFEDHR_BITS bit; -}; - -struct DBFED_BITS { // bits description - Uint16 DBFED:14; // 13:0 Falling edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBFED_REG { - Uint16 all; - struct DBFED_BITS bit; -}; - -struct TBPHS_BITS { // bits description - Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) - Uint16 TBPHS:16; // 31:16 Phase Offset Register -}; - -union TBPHS_REG { - Uint32 all; - struct TBPHS_BITS bit; -}; - -struct CMPA_BITS { // bits description - Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register - Uint16 CMPA:16; // 31:16 Compare A Register -}; - -union CMPA_REG { - Uint32 all; - struct CMPA_BITS bit; -}; - -struct CMPB_BITS { // bits description - Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits - Uint16 CMPB:16; // 31:16 Compare B Register -}; - -union CMPB_REG { - Uint32 all; - struct CMPB_BITS bit; -}; - -struct GLDCTL2_BITS { // bits description - Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode - Uint16 GFRCLD:1; // 1 Force reload event in one shot mode - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLDCTL2_REG { - Uint16 all; - struct GLDCTL2_BITS bit; -}; - -struct TZSEL_BITS { // bits description - Uint16 CBC1:1; // 0 TZ1 CBC select - Uint16 CBC2:1; // 1 TZ2 CBC select - Uint16 CBC3:1; // 2 TZ3 CBC select - Uint16 CBC4:1; // 3 TZ4 CBC select - Uint16 CBC5:1; // 4 TZ5 CBC select - Uint16 CBC6:1; // 5 TZ6 CBC select - Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select - Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select - Uint16 OSHT1:1; // 8 One-shot TZ1 select - Uint16 OSHT2:1; // 9 One-shot TZ2 select - Uint16 OSHT3:1; // 10 One-shot TZ3 select - Uint16 OSHT4:1; // 11 One-shot TZ4 select - Uint16 OSHT5:1; // 12 One-shot TZ5 select - Uint16 OSHT6:1; // 13 One-shot TZ6 select - Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select - Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select -}; - -union TZSEL_REG { - Uint16 all; - struct TZSEL_BITS bit; -}; - -struct TZDCSEL_BITS { // bits description - Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 - Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 - Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 - Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZDCSEL_REG { - Uint16 all; - struct TZDCSEL_BITS bit; -}; - -struct TZCTL_BITS { // bits description - Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA - Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB - Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 - Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 - Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 - Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTL_REG { - Uint16 all; - struct TZCTL_BITS bit; -}; - -struct TZCTL2_BITS { // bits description - Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP - Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN - Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP - Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN - Uint16 rsvd1:3; // 14:12 Reserved - Uint16 ETZE:1; // 15 TZCTL2 Enable -}; - -union TZCTL2_REG { - Uint16 all; - struct TZCTL2_BITS bit; -}; - -struct TZCTLDCA_BITS { // bits description - Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCA_REG { - Uint16 all; - struct TZCTLDCA_BITS bit; -}; - -struct TZCTLDCB_BITS { // bits description - Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCB_REG { - Uint16 all; - struct TZCTLDCB_BITS bit; -}; - -struct TZEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable - Uint16 OST:1; // 2 Trip Zones One Shot Int Enable - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZEINT_REG { - Uint16 all; - struct TZEINT_BITS bit; -}; - -struct TZFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Int Status Flag - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag - Uint16 OST:1; // 2 Trip Zones One Shot Flag - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TZFLG_REG { - Uint16 all; - struct TZFLG_BITS bit; -}; - -struct TZCBCFLG_BITS { // bits description - Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch - Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch - Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch - Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch - Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch - Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch - Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 - Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCFLG_REG { - Uint16 all; - struct TZCBCFLG_BITS bit; -}; - -struct TZOSTFLG_BITS { // bits description - Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch - Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch - Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch - Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch - Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch - Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch - Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 - Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTFLG_REG { - Uint16 all; - struct TZOSTFLG_BITS bit; -}; - -struct TZCLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt Clear Flag - Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear - Uint16 OST:1; // 2 One-Shot Flag Clear - Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear - Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear - Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear - Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear - Uint16 rsvd1:7; // 13:7 Reserved - Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch -}; - -union TZCLR_REG { - Uint16 all; - struct TZCLR_BITS bit; -}; - -struct TZCBCCLR_BITS { // bits description - Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch - Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch - Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch - Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch - Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch - Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch - Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC - Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCCLR_REG { - Uint16 all; - struct TZCBCCLR_BITS bit; -}; - -struct TZOSTCLR_BITS { // bits description - Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch - Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch - Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch - Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch - Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch - Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch - Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST - Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTCLR_REG { - Uint16 all; - struct TZOSTCLR_BITS bit; -}; - -struct TZFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event - Uint16 OST:1; // 2 Force Trip Zones One Shot Event - Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 - Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 - Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 - Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZFRC_REG { - Uint16 all; - struct TZFRC_BITS bit; -}; - -struct ETSEL_BITS { // bits description - Uint16 INTSEL:3; // 2:0 EPWMxINTn Select - Uint16 INTEN:1; // 3 EPWMxINTn Enable - Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select - Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select - Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select - Uint16 SOCAEN:1; // 11 Start of Conversion A Enable - Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select - Uint16 SOCBEN:1; // 15 Start of Conversion B Enable -}; - -union ETSEL_REG { - Uint16 all; - struct ETSEL_BITS bit; -}; - -struct ETPS_BITS { // bits description - Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select - Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register - Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits - Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select - Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register - Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select - Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter -}; - -union ETPS_REG { - Uint16 all; - struct ETPS_BITS bit; -}; - -struct ETFLG_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Flag - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Flag - Uint16 SOCB:1; // 3 EPWMxSOCB Flag - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFLG_REG { - Uint16 all; - struct ETFLG_BITS bit; -}; - -struct ETCLR_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Clear - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Clear - Uint16 SOCB:1; // 3 EPWMxSOCB Clear - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETCLR_REG { - Uint16 all; - struct ETCLR_BITS bit; -}; - -struct ETFRC_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Force - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Force - Uint16 SOCB:1; // 3 EPWMxSOCB Force - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFRC_REG { - Uint16 all; - struct ETFRC_BITS bit; -}; - -struct ETINTPS_BITS { // bits description - Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select - Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ETINTPS_REG { - Uint16 all; - struct ETINTPS_BITS bit; -}; - -struct ETSOCPS_BITS { // bits description - Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select - Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register - Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select - Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register -}; - -union ETSOCPS_REG { - Uint16 all; - struct ETSOCPS_BITS bit; -}; - -struct ETCNTINITCTL_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force - Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force - Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force - Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable - Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable - Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable -}; - -union ETCNTINITCTL_REG { - Uint16 all; - struct ETCNTINITCTL_BITS bit; -}; - -struct ETCNTINIT_BITS { // bits description - Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits - Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits - Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ETCNTINIT_REG { - Uint16 all; - struct ETCNTINIT_BITS bit; -}; - -struct DCTRIPSEL_BITS { // bits description - Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select - Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select - Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select - Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select -}; - -union DCTRIPSEL_REG { - Uint16 all; - struct DCTRIPSEL_BITS bit; -}; - -struct DCACTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCACTL_REG { - Uint16 all; - struct DCACTL_BITS bit; -}; - -struct DCBCTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCBCTL_REG { - Uint16 all; - struct DCBCTL_BITS bit; -}; - -struct DCFCTL_BITS { // bits description - Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select - Uint16 BLANKE:1; // 2 Blanking Enable/Disable - Uint16 BLANKINV:1; // 3 Blanking Window Inversion - Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment - Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 EDGEMODE:2; // 9:8 Edge Mode - Uint16 EDGECOUNT:3; // 12:10 Edge Count - Uint16 EDGESTATUS:3; // 15:13 Edge Status -}; - -union DCFCTL_REG { - Uint16 all; - struct DCFCTL_BITS bit; -}; - -struct DCCAPCTL_BITS { // bits description - Uint16 CAPE:1; // 0 Counter Capture Enable - Uint16 SHDWMODE:1; // 1 Counter Capture Mode - Uint16 rsvd1:11; // 12:2 Reserved - Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event - Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag - Uint16 CAPMODE:1; // 15 Counter Capture Mode -}; - -union DCCAPCTL_REG { - Uint16 all; - struct DCCAPCTL_BITS bit; -}; - -struct DCAHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCAHTRIPSEL_REG { - Uint16 all; - struct DCAHTRIPSEL_BITS bit; -}; - -struct DCALTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCALTRIPSEL_REG { - Uint16 all; - struct DCALTRIPSEL_BITS bit; -}; - -struct DCBHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBHTRIPSEL_REG { - Uint16 all; - struct DCBHTRIPSEL_BITS bit; -}; - -struct DCBLTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBLTRIPSEL_REG { - Uint16 all; - struct DCBLTRIPSEL_BITS bit; -}; - -struct EPWMLOCK_BITS { // bits description - Uint16 HRLOCK:1; // 0 HRPWM Register Set Lock - Uint16 GLLOCK:1; // 1 Global Load Register Set Lock - Uint16 TZCFGLOCK:1; // 2 TripZone Register Set Lock - Uint16 TZCLRLOCK:1; // 3 TripZone Clear Register Set Lock - Uint16 DCLOCK:1; // 4 Digital Compare Register Set Lock - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 KEY:16; // 31:16 Key to write to this register -}; - -union EPWMLOCK_REG { - Uint32 all; - struct EPWMLOCK_BITS bit; -}; - -struct EPWM_REGS { - union TBCTL_REG TBCTL; // Time Base Control Register - union TBCTL2_REG TBCTL2; // Time Base Control Register 2 - Uint16 rsvd1[2]; // Reserved - Uint16 TBCTR; // Time Base Counter Register - union TBSTS_REG TBSTS; // Time Base Status Register - Uint16 rsvd2[2]; // Reserved - union CMPCTL_REG CMPCTL; // Counter Compare Control Register - union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 - Uint16 rsvd3[2]; // Reserved - union DBCTL_REG DBCTL; // Dead-Band Generator Control Register - union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 - Uint16 rsvd4[2]; // Reserved - union AQCTL_REG AQCTL; // Action Qualifier Control Register - union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register - Uint16 rsvd5[2]; // Reserved - union PCCTL_REG PCCTL; // PWM Chopper Control Register - Uint16 rsvd6[3]; // Reserved - union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register - union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register - Uint16 rsvd7[6]; // Reserved - union HRCNFG_REG HRCNFG; // HRPWM Configuration Register - union HRPWR_REG HRPWR; // HRPWM Power Register - Uint16 rsvd8[4]; // Reserved - union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register - union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register - Uint16 rsvd9[5]; // Reserved - union HRPCTL_REG HRPCTL; // High Resolution Period Control Register - union TRREM_REG TRREM; // Translator High Resolution Remainder Register - Uint16 rsvd10[5]; // Reserved - union GLDCTL_REG GLDCTL; // Global PWM Load Control Register - union GLDCFG_REG GLDCFG; // Global PWM Load Config Register - Uint16 rsvd11[2]; // Reserved - union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register - Uint16 rsvd12[4]; // Reserved - union EPWMREV_REG EPWMREV; // EPWM Revision Register - Uint16 rsvd13; // Reserved - union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A - union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A - union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B - union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B - Uint16 rsvd14[3]; // Reserved - union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register - Uint16 rsvd15; // Reserved - union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register - Uint16 rsvd16[6]; // Reserved - union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register - union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register - Uint16 rsvd17[12]; // Reserved - union TBPHS_REG TBPHS; // Time Base Phase High - Uint16 TBPRDHR; // Time Base Period High Resolution Register - Uint16 TBPRD; // Time Base Period Register - Uint16 rsvd18[6]; // Reserved - union CMPA_REG CMPA; // Counter Compare A Register - union CMPB_REG CMPB; // Compare B Register - Uint16 rsvd19; // Reserved - Uint16 CMPC; // Counter Compare C Register - Uint16 rsvd20; // Reserved - Uint16 CMPD; // Counter Compare D Register - Uint16 rsvd21[2]; // Reserved - union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 - Uint16 rsvd22[2]; // Reserved - Uint16 SWVDELVAL; // Software Valley Mode Delay Register - Uint16 rsvd23[8]; // Reserved - union TZSEL_REG TZSEL; // Trip Zone Select Register - Uint16 rsvd24; // Reserved - union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register - Uint16 rsvd25; // Reserved - union TZCTL_REG TZCTL; // Trip Zone Control Register - union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register - union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A - union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B - Uint16 rsvd26[5]; // Reserved - union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register - Uint16 rsvd27[5]; // Reserved - union TZFLG_REG TZFLG; // Trip Zone Flag Register - union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register - union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register - Uint16 rsvd28; // Reserved - union TZCLR_REG TZCLR; // Trip Zone Clear Register - union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register - union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register - Uint16 rsvd29; // Reserved - union TZFRC_REG TZFRC; // Trip Zone Force Register - Uint16 rsvd30[8]; // Reserved - union ETSEL_REG ETSEL; // Event Trigger Selection Register - Uint16 rsvd31; // Reserved - union ETPS_REG ETPS; // Event Trigger Pre-Scale Register - Uint16 rsvd32; // Reserved - union ETFLG_REG ETFLG; // Event Trigger Flag Register - Uint16 rsvd33; // Reserved - union ETCLR_REG ETCLR; // Event Trigger Clear Register - Uint16 rsvd34; // Reserved - union ETFRC_REG ETFRC; // Event Trigger Force Register - Uint16 rsvd35; // Reserved - union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register - Uint16 rsvd36; // Reserved - union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register - Uint16 rsvd37; // Reserved - union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register - Uint16 rsvd38; // Reserved - union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register - Uint16 rsvd39[11]; // Reserved - union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register - Uint16 rsvd40[2]; // Reserved - union DCACTL_REG DCACTL; // Digital Compare A Control Register - union DCBCTL_REG DCBCTL; // Digital Compare B Control Register - Uint16 rsvd41[2]; // Reserved - union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register - union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register - Uint16 DCFOFFSET; // Digital Compare Filter Offset Register - Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register - Uint16 DCFWINDOW; // Digital Compare Filter Window Register - Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register - Uint16 rsvd42[2]; // Reserved - Uint16 DCCAP; // Digital Compare Counter Capture Register - Uint16 rsvd43[2]; // Reserved - union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select - union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select - union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select - union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select - Uint16 rsvd44[36]; // Reserved - union EPWMLOCK_REG EPWMLOCK; // EPWM Lock Register - Uint16 rsvd45; // Reserved - Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register - Uint16 VCNTVAL; // Hardware Valley Counter Register - Uint16 rsvd46; // Reserved -}; - -//--------------------------------------------------------------------------- -// EPWM External References & Function Declarations: -// -extern volatile struct EPWM_REGS EPwm1Regs; -extern volatile struct EPWM_REGS EPwm2Regs; -extern volatile struct EPWM_REGS EPwm3Regs; -extern volatile struct EPWM_REGS EPwm4Regs; -extern volatile struct EPWM_REGS EPwm5Regs; -extern volatile struct EPWM_REGS EPwm6Regs; -extern volatile struct EPWM_REGS EPwm7Regs; -extern volatile struct EPWM_REGS EPwm8Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h deleted file mode 100644 index d0ebfd7..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_epwm_xbar.h +++ /dev/null @@ -1,830 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_epwm_xbar.h -// -// TITLE: EPWM_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EPWM_XBAR_H__ -#define __F28004X_EPWM_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM_XBAR Individual Register Bit Definitions: - -struct TRIP4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX0TO15CFG_REG { - Uint32 all; - struct TRIP4MUX0TO15CFG_BITS bit; -}; - -struct TRIP4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX16TO31CFG_REG { - Uint32 all; - struct TRIP4MUX16TO31CFG_BITS bit; -}; - -struct TRIP5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX0TO15CFG_REG { - Uint32 all; - struct TRIP5MUX0TO15CFG_BITS bit; -}; - -struct TRIP5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX16TO31CFG_REG { - Uint32 all; - struct TRIP5MUX16TO31CFG_BITS bit; -}; - -struct TRIP7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX0TO15CFG_REG { - Uint32 all; - struct TRIP7MUX0TO15CFG_BITS bit; -}; - -struct TRIP7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX16TO31CFG_REG { - Uint32 all; - struct TRIP7MUX16TO31CFG_BITS bit; -}; - -struct TRIP8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX0TO15CFG_REG { - Uint32 all; - struct TRIP8MUX0TO15CFG_BITS bit; -}; - -struct TRIP8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX16TO31CFG_REG { - Uint32 all; - struct TRIP8MUX16TO31CFG_BITS bit; -}; - -struct TRIP9MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX0TO15CFG_REG { - Uint32 all; - struct TRIP9MUX0TO15CFG_BITS bit; -}; - -struct TRIP9MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX16TO31CFG_REG { - Uint32 all; - struct TRIP9MUX16TO31CFG_BITS bit; -}; - -struct TRIP10MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX0TO15CFG_REG { - Uint32 all; - struct TRIP10MUX0TO15CFG_BITS bit; -}; - -struct TRIP10MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX16TO31CFG_REG { - Uint32 all; - struct TRIP10MUX16TO31CFG_BITS bit; -}; - -struct TRIP11MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX0TO15CFG_REG { - Uint32 all; - struct TRIP11MUX0TO15CFG_BITS bit; -}; - -struct TRIP11MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX16TO31CFG_REG { - Uint32 all; - struct TRIP11MUX16TO31CFG_BITS bit; -}; - -struct TRIP12MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX0TO15CFG_REG { - Uint32 all; - struct TRIP12MUX0TO15CFG_BITS bit; -}; - -struct TRIP12MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX16TO31CFG_REG { - Uint32 all; - struct TRIP12MUX16TO31CFG_BITS bit; -}; - -struct TRIP4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR -}; - -union TRIP4MUXENABLE_REG { - Uint32 all; - struct TRIP4MUXENABLE_BITS bit; -}; - -struct TRIP5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR -}; - -union TRIP5MUXENABLE_REG { - Uint32 all; - struct TRIP5MUXENABLE_BITS bit; -}; - -struct TRIP7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR -}; - -union TRIP7MUXENABLE_REG { - Uint32 all; - struct TRIP7MUXENABLE_BITS bit; -}; - -struct TRIP8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR -}; - -union TRIP8MUXENABLE_REG { - Uint32 all; - struct TRIP8MUXENABLE_BITS bit; -}; - -struct TRIP9MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR -}; - -union TRIP9MUXENABLE_REG { - Uint32 all; - struct TRIP9MUXENABLE_BITS bit; -}; - -struct TRIP10MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR -}; - -union TRIP10MUXENABLE_REG { - Uint32 all; - struct TRIP10MUXENABLE_BITS bit; -}; - -struct TRIP11MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR -}; - -union TRIP11MUXENABLE_REG { - Uint32 all; - struct TRIP11MUXENABLE_BITS bit; -}; - -struct TRIP12MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR -}; - -union TRIP12MUXENABLE_REG { - Uint32 all; - struct TRIP12MUXENABLE_BITS bit; -}; - -struct TRIPOUTINV_BITS { // bits description - Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR - Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR - Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR - Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR - Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR - Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR - Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR - Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TRIPOUTINV_REG { - Uint32 all; - struct TRIPOUTINV_BITS bit; -}; - -struct TRIPLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write protection KEY -}; - -union TRIPLOCK_REG { - Uint32 all; - struct TRIPLOCK_BITS bit; -}; - -struct EPWM_XBAR_REGS { - union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 - union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 - union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 - union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 - union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 - union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 - union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 - union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 - Uint16 rsvd1[8]; // Reserved - union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register - Uint16 rsvd2[4]; // Reserved - union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// EPWM_XBAR External References & Function Declarations: -// -extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h deleted file mode 100644 index e14b9c8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_eqep.h +++ /dev/null @@ -1,301 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_eqep.h -// -// TITLE: EQEP Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_EQEP_H__ -#define __F28004X_EQEP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EQEP Individual Register Bit Definitions: - -struct QDECCTL_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 QSP:1; // 5 QEPS input polarity - Uint16 QIP:1; // 6 QEPI input polarity - Uint16 QBP:1; // 7 QEPB input polarity - Uint16 QAP:1; // 8 QEPA input polarity - Uint16 IGATE:1; // 9 Index pulse gating option - Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter - Uint16 XCR:1; // 11 External Clock Rate - Uint16 SPSEL:1; // 12 Sync output pin selection - Uint16 SOEN:1; // 13 Sync output-enable - Uint16 QSRC:2; // 15:14 Position-counter source selection -}; - -union QDECCTL_REG { - Uint16 all; - struct QDECCTL_BITS bit; -}; - -struct QEPCTL_BITS { // bits description - Uint16 WDE:1; // 0 QEP watchdog enable - Uint16 UTE:1; // 1 QEP unit timer enable - Uint16 QCLM:1; // 2 QEP capture latch mode - Uint16 QPEN:1; // 3 Quadrature postotion counter enable - Uint16 IEL:2; // 5:4 Index event latch - Uint16 SEL:1; // 6 Strobe event latch - Uint16 SWI:1; // 7 Software init position counter - Uint16 IEI:2; // 9:8 Index event init of position count - Uint16 SEI:2; // 11:10 Strobe event init - Uint16 PCRM:2; // 13:12 Postion counter reset - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union QEPCTL_REG { - Uint16 all; - struct QEPCTL_BITS bit; -}; - -struct QCAPCTL_BITS { // bits description - Uint16 UPPS:4; // 3:0 Unit position event prescaler - Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler - Uint16 rsvd1:8; // 14:7 Reserved - Uint16 CEN:1; // 15 Enable eQEP capture -}; - -union QCAPCTL_REG { - Uint16 all; - struct QCAPCTL_BITS bit; -}; - -struct QPOSCTL_BITS { // bits description - Uint16 PCSPW:12; // 11:0 Position compare sync pulse width - Uint16 PCE:1; // 12 Position compare enable/disable - Uint16 PCPOL:1; // 13 Polarity of sync output - Uint16 PCLOAD:1; // 14 Position compare of shadow load - Uint16 PCSHDW:1; // 15 Position compare of shadow enable -}; - -union QPOSCTL_REG { - Uint16 all; - struct QPOSCTL_BITS bit; -}; - -struct QEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Position counter error interrupt enable - Uint16 QPE:1; // 2 Quadrature phase error interrupt enable - Uint16 QDC:1; // 3 Quadrature direction change interrupt enable - Uint16 WTO:1; // 4 Watchdog time out interrupt enable - Uint16 PCU:1; // 5 Position counter underflow interrupt enable - Uint16 PCO:1; // 6 Position counter overflow interrupt enable - Uint16 PCR:1; // 7 Position-compare ready interrupt enable - Uint16 PCM:1; // 8 Position-compare match interrupt enable - Uint16 SEL:1; // 9 Strobe event latch interrupt enable - Uint16 IEL:1; // 10 Index event latch interrupt enable - Uint16 UTO:1; // 11 Unit time out interrupt enable - Uint16 QMAE:1; // 12 QMA error interrupt enable - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union QEINT_REG { - Uint16 all; - struct QEINT_BITS bit; -}; - -struct QFLG_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt status flag - Uint16 PCE:1; // 1 Position counter error interrupt flag - Uint16 PHE:1; // 2 Quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Position counter underflow interrupt flag - Uint16 PCO:1; // 6 Position counter overflow interrupt flag - Uint16 PCR:1; // 7 Position-compare ready interrupt flag - Uint16 PCM:1; // 8 eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Strobe event latch interrupt flag - Uint16 IEL:1; // 10 Index event latch interrupt flag - Uint16 UTO:1; // 11 Unit time out interrupt flag - Uint16 QMAE:1; // 12 QMA error interrupt flag - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union QFLG_REG { - Uint16 all; - struct QFLG_BITS bit; -}; - -struct QCLR_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt clear flag - Uint16 PCE:1; // 1 Clear position counter error interrupt flag - Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag - Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag - Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag - Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag - Uint16 IEL:1; // 10 Clear index event latch interrupt flag - Uint16 UTO:1; // 11 Clear unit time out interrupt flag - Uint16 QMAE:1; // 12 Clear QMA error interrupt flag - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union QCLR_REG { - Uint16 all; - struct QCLR_BITS bit; -}; - -struct QFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Force position counter error interrupt - Uint16 PHE:1; // 2 Force quadrature phase error interrupt - Uint16 QDC:1; // 3 Force quadrature direction change interrupt - Uint16 WTO:1; // 4 Force watchdog time out interrupt - Uint16 PCU:1; // 5 Force position counter underflow interrupt - Uint16 PCO:1; // 6 Force position counter overflow interrupt - Uint16 PCR:1; // 7 Force position-compare ready interrupt - Uint16 PCM:1; // 8 Force position-compare match interrupt - Uint16 SEL:1; // 9 Force strobe event latch interrupt - Uint16 IEL:1; // 10 Force index event latch interrupt - Uint16 UTO:1; // 11 Force unit time out interrupt - Uint16 QMAE:1; // 12 Force QMA error interrupt - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union QFRC_REG { - Uint16 all; - struct QFRC_BITS bit; -}; - -struct QEPSTS_BITS { // bits description - Uint16 PCEF:1; // 0 Position counter error flag. - Uint16 FIMF:1; // 1 First index marker flag - Uint16 CDEF:1; // 2 Capture direction error flag - Uint16 COEF:1; // 3 Capture overflow error flag - Uint16 QDLF:1; // 4 eQEP direction latch flag - Uint16 QDF:1; // 5 Quadrature direction flag - Uint16 FIDF:1; // 6 The first index marker - Uint16 UPEVNT:1; // 7 Unit position event flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union QEPSTS_REG { - Uint16 all; - struct QEPSTS_BITS bit; -}; - -struct REV_BITS { // bits description - Uint16 MAJOR:3; // 2:0 Major Revision Number - Uint16 MINOR:3; // 5:3 Minor Revision Number - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union REV_REG { - Uint32 all; - struct REV_BITS bit; -}; - -struct QEPSTROBESEL_BITS { // bits description - Uint16 STROBESEL:2; // 1:0 QMA Mode Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union QEPSTROBESEL_REG { - Uint32 all; - struct QEPSTROBESEL_BITS bit; -}; - -struct QMACTRL_BITS { // bits description - Uint16 MODE:3; // 2:0 QMA Mode Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union QMACTRL_REG { - Uint32 all; - struct QMACTRL_BITS bit; -}; - -struct EQEP_REGS { - Uint32 QPOSCNT; // Position Counter - Uint32 QPOSINIT; // Position Counter Init - Uint32 QPOSMAX; // Maximum Position Count - Uint32 QPOSCMP; // Position Compare - Uint32 QPOSILAT; // Index Position Latch - Uint32 QPOSSLAT; // Strobe Position Latch - Uint32 QPOSLAT; // Position Latch - Uint32 QUTMR; // QEP Unit Timer - Uint32 QUPRD; // QEP Unit Period - Uint16 QWDTMR; // QEP Watchdog Timer - Uint16 QWDPRD; // QEP Watchdog Period - union QDECCTL_REG QDECCTL; // Quadrature Decoder Control - union QEPCTL_REG QEPCTL; // QEP Control - union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control - union QPOSCTL_REG QPOSCTL; // Position Compare Control - union QEINT_REG QEINT; // QEP Interrupt Control - union QFLG_REG QFLG; // QEP Interrupt Flag - union QCLR_REG QCLR; // QEP Interrupt Clear - union QFRC_REG QFRC; // QEP Interrupt Force - union QEPSTS_REG QEPSTS; // QEP Status - Uint16 QCTMR; // QEP Capture Timer - Uint16 QCPRD; // QEP Capture Period - Uint16 QCTMRLAT; // QEP Capture Latch - Uint16 QCPRDLAT; // QEP Capture Period Latch - Uint16 rsvd1[15]; // Reserved - union REV_REG REV; // QEP Revision Number - union QEPSTROBESEL_REG QEPSTROBESEL; // QEP Strobe select register - union QMACTRL_REG QMACTRL; // QMA Control register - Uint16 rsvd2[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// EQEP External References & Function Declarations: -// -extern volatile struct EQEP_REGS EQep1Regs; -extern volatile struct EQEP_REGS EQep2Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h deleted file mode 100644 index e113533..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_erad.h +++ /dev/null @@ -1,306 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_erad.h -// -// TITLE: ERAD Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_ERAD_H__ -#define __F28004X_ERAD_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ERAD Individual Register Bit Definitions: - -struct GLBL_EVENT_STAT_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Event Status - Uint16 HWBP2:1; // 1 Bus Comparator Module Event Status - Uint16 HWBP3:1; // 2 Bus Comparator Module Event Status - Uint16 HWBP4:1; // 3 Bus Comparator Module Event Status - Uint16 HWBP5:1; // 4 Bus Comparator Module Event Status - Uint16 HWBP6:1; // 5 Bus Comparator Module Event Status - Uint16 HWBP7:1; // 6 Bus Comparator Module Event Status - Uint16 HWBP8:1; // 7 Bus Comparator Module Event Status - Uint16 CTM1:1; // 8 Counter Module Event Status - Uint16 CTM2:1; // 9 Counter Module Event Status - Uint16 CTM3:1; // 10 Counter Module Event Status - Uint16 CTM4:1; // 11 Counter Module Event Status - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_EVENT_STAT_REG { - Uint16 all; - struct GLBL_EVENT_STAT_BITS bit; -}; - -struct GLBL_HALT_STAT_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Halt Status - Uint16 HWBP2:1; // 1 Bus Comparator Module Halt Status - Uint16 HWBP3:1; // 2 Bus Comparator Module Halt Status - Uint16 HWBP4:1; // 3 Bus Comparator Module Halt Status - Uint16 HWBP5:1; // 4 Bus Comparator Module Halt Status - Uint16 HWBP6:1; // 5 Bus Comparator Module Halt Status - Uint16 HWBP7:1; // 6 Bus Comparator Module Halt Status - Uint16 HWBP8:1; // 7 Bus Comparator Module Halt Status - Uint16 CTM1:1; // 8 Counter Module Halt Status - Uint16 CTM2:1; // 9 Counter Module Halt Status - Uint16 CTM3:1; // 10 Counter Module Halt Status - Uint16 CTM4:1; // 11 Counter Module Halt Status - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_HALT_STAT_REG { - Uint16 all; - struct GLBL_HALT_STAT_BITS bit; -}; - -struct GLBL_ENABLE_BITS { // bits description - Uint16 HWBP1:1; // 0 Bus Comparator Module Global Enable - Uint16 HWBP2:1; // 1 Bus Comparator Module Global Enable - Uint16 HWBP3:1; // 2 Bus Comparator Module Global Enable - Uint16 HWBP4:1; // 3 Bus Comparator Module Global Enable - Uint16 HWBP5:1; // 4 Bus Comparator Module Global Enable - Uint16 HWBP6:1; // 5 Bus Comparator Module Global Enable - Uint16 HWBP7:1; // 6 Bus Comparator Module Global Enable - Uint16 HWBP8:1; // 7 Bus Comparator Module Global Enable - Uint16 CTM1:1; // 8 Counter Module Global Enable - Uint16 CTM2:1; // 9 Counter Module Global Enable - Uint16 CTM3:1; // 10 Counter Module Global Enable - Uint16 CTM4:1; // 11 Counter Module Global Enable - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union GLBL_ENABLE_REG { - Uint16 all; - struct GLBL_ENABLE_BITS bit; -}; - -struct GLBL_CTM_RESET_BITS { // bits description - Uint16 CTM1:1; // 0 Global Reset for the counters - Uint16 CTM2:1; // 1 Global Reset for the counters - Uint16 CTM3:1; // 2 Global Reset for the counters - Uint16 CTM4:1; // 3 Global Reset for the counters - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union GLBL_CTM_RESET_REG { - Uint16 all; - struct GLBL_CTM_RESET_BITS bit; -}; - -struct GLBL_OWNER_BITS { // bits description - Uint16 OWNER:2; // 1:0 Global Ownership Bits - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLBL_OWNER_REG { - Uint16 all; - struct GLBL_OWNER_BITS bit; -}; - -struct ERAD_GLOBAL_REGS { - union GLBL_EVENT_STAT_REG GLBL_EVENT_STAT; // Global Event Status Register - Uint16 rsvd1; // Reserved - union GLBL_HALT_STAT_REG GLBL_HALT_STAT; // Global Halt Status Register - Uint16 rsvd2; // Reserved - union GLBL_ENABLE_REG GLBL_ENABLE; // Global Enable Register - Uint16 rsvd3; // Reserved - union GLBL_CTM_RESET_REG GLBL_CTM_RESET; // Global Counter Reset - Uint16 rsvd4[3]; // Reserved - union GLBL_OWNER_REG GLBL_OWNER; // Global Ownership - Uint16 rsvd5[8]; // Reserved -}; - -struct HWBP_CLEAR_BITS { // bits description - Uint16 EVENT_CLR:1; // 0 Event Clear register - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union HWBP_CLEAR_REG { - Uint16 all; - struct HWBP_CLEAR_BITS bit; -}; - -struct HWBP_CNTL_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 BUS_SEL:3; // 4:2 Bus select bits - Uint16 STOP:1; // 5 Stop bit (Halt/No Halt of CPU) - Uint16 RTOSINT:1; // 6 RTOSINT bit - Uint16 COMP_MODE:3; // 9:7 Compare mode - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union HWBP_CNTL_REG { - Uint16 all; - struct HWBP_CNTL_BITS bit; -}; - -struct HWBP_STATUS_BITS { // bits description - Uint16 EVENT_FIRED:1; // 0 HWBP Event Fired bits - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 MODULE_ID:6; // 13:8 Identification bits - Uint16 STATUS:2; // 15:14 Status bits -}; - -union HWBP_STATUS_REG { - Uint16 all; - struct HWBP_STATUS_BITS bit; -}; - -struct ERAD_HWBP_REGS { - Uint32 HWBP_MASK; // HWBP Mask Register - Uint32 HWBP_REF; // HWBP Reference Register - union HWBP_CLEAR_REG HWBP_CLEAR; // HWBP Clear Register - Uint16 rsvd1; // Reserved - union HWBP_CNTL_REG HWBP_CNTL; // HWBP Control Register - union HWBP_STATUS_REG HWBP_STATUS; // HWBP Status Register -}; - -struct CTM_CNTL_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 START_STOP_MODE:1; // 2 Start_stop mode bit - Uint16 EVENT_MODE:1; // 3 Event mode bit - Uint16 RST_ON_MATCH:1; // 4 Reset_on_match bit - Uint16 rsvd2:1; // 5 Reserved - Uint16 STOP:1; // 6 Stop bit (Halt/No Halt of CPU) - Uint16 RTOSINT:1; // 7 RTOSINT bit - Uint16 START_STOP_CUMULATIVE:1; // 8 Start stop cumulative bit - Uint16 rsvd3:1; // 9 Reserved - Uint16 RST_EN:1; // 10 Enable Reset - Uint16 RST_INP_SEL:5; // 15:11 Reset Input select -}; - -union CTM_CNTL_REG { - Uint16 all; - struct CTM_CNTL_BITS bit; -}; - -struct CTM_STATUS_BITS { // bits description - Uint16 EVENT_FIRED:1; // 0 Counter Event Fired bits - Uint16 OVERFLOW:1; // 1 Counter Overflowed - Uint16 MODULE_ID:10; // 11:2 Identification bits - Uint16 STATUS:4; // 15:12 Status bits -}; - -union CTM_STATUS_REG { - Uint16 all; - struct CTM_STATUS_BITS bit; -}; - -struct CTM_INPUT_SEL_BITS { // bits description - Uint16 CTM_INP_SEL_EN:1; // 0 Count input select enable - Uint16 CNT_INP_SEL:5; // 5:1 Count input select - Uint16 STA_INP_SEL:5; // 10:6 Start input select - Uint16 STO_INP_SEL:5; // 15:11 Stop input select -}; - -union CTM_INPUT_SEL_REG { - Uint16 all; - struct CTM_INPUT_SEL_BITS bit; -}; - -struct CTM_CLEAR_BITS { // bits description - Uint16 EVENT_CLEAR:1; // 0 Clear EVENT_FIRED - Uint16 OVERFLOW_CLEAR:1; // 1 Clear OVERFLOW - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union CTM_CLEAR_REG { - Uint16 all; - struct CTM_CLEAR_BITS bit; -}; - -struct CTM_INPUT_SEL_MSB_BITS { // bits description - Uint16 CTM_INP_SEL_MSB:1; // 0 Count input select - Uint16 rsvd1:3; // 3:1 Reserved - Uint16 STA_INP_SEL_MSB:1; // 4 Start input select - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 STO_INP_SEL_MSB:1; // 8 Stop input select - Uint16 rsvd3:3; // 11:9 Reserved - Uint16 RST_INP_SEL_MSB:1; // 12 Reset Input Select - Uint16 rsvd4:3; // 15:13 Reserved -}; - -union CTM_INPUT_SEL_MSB_REG { - Uint16 all; - struct CTM_INPUT_SEL_MSB_BITS bit; -}; - -struct ERAD_COUNTER_REGS { - union CTM_CNTL_REG CTM_CNTL; // Counter Control Register - union CTM_STATUS_REG CTM_STATUS; // Counter Status Register - Uint32 CTM_REF; // Counter Reference Register - Uint32 CTM_COUNT; // Counter Current Value Register - Uint32 CTM_MAX_COUNT; // Counter Max Count Value Register - union CTM_INPUT_SEL_REG CTM_INPUT_SEL; // Counter Input Select Register - union CTM_CLEAR_REG CTM_CLEAR; // Counter Clear Register - union CTM_INPUT_SEL_MSB_REG CTM_INPUT_SEL_MSB; // Counter Input Select Extension Register - Uint16 rsvd1[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ERAD External References & Function Declarations: -// -extern volatile struct ERAD_GLOBAL_REGS EnhancedDebugGlobalRegs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP1Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP2Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP3Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP4Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP5Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP6Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP7Regs; -extern volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP8Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter1Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter2Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter3Regs; -extern volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter4Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h deleted file mode 100644 index c91a491..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_flash.h +++ /dev/null @@ -1,366 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_flash.h -// -// TITLE: FLASH Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_FLASH_H__ -#define __F28004X_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FLASH Individual Register Bit Definitions: - -struct FRDCNTL_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 RWAIT:4; // 11:8 Random Read Waitstate - Uint16 rsvd2:4; // 15:12 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union FRDCNTL_REG { - Uint32 all; - struct FRDCNTL_BITS bit; -}; - -struct FBAC_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 BAGP:8; // 15:8 Bank Active Grace Period - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBAC_REG { - Uint32 all; - struct FBAC_BITS bit; -}; - -struct FBFALLBACK_BITS { // bits description - Uint16 BNKPWR0:2; // 1:0 Bank Power Mode of BANK0 - Uint16 BNKPWR1:2; // 3:2 Bank Power Mode of BANK1 - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBFALLBACK_REG { - Uint32 all; - struct FBFALLBACK_BITS bit; -}; - -struct FBPRDY_BITS { // bits description - Uint16 BANK0RDY:1; // 0 Flash Bank Active Power State - Uint16 BANK1RDY:1; // 1 Flash Bank Active Power State - Uint16 rsvd1:13; // 14:2 Reserved - Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBPRDY_REG { - Uint32 all; - struct FBPRDY_BITS bit; -}; - -struct FPAC1_BITS { // bits description - Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count - Uint16 rsvd2:4; // 31:28 Reserved -}; - -union FPAC1_REG { - Uint32 all; - struct FPAC1_BITS bit; -}; - -struct FPAC2_BITS { // bits description - Uint16 PAGP:16; // 15:0 Pump Active Grace Period - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union FPAC2_REG { - Uint32 all; - struct FPAC2_BITS bit; -}; - -struct FMSTAT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status - Uint16 CSTAT:1; // 4 Command Fail Status - Uint16 INVDAT:1; // 5 Invalid Data - Uint16 PGM:1; // 6 Program Operation Status - Uint16 ERS:1; // 7 Erase Operation Status - Uint16 BUSY:1; // 8 Busy Bit - Uint16 rsvd4:1; // 9 Reserved - Uint16 EV:1; // 10 Erase Verify Status - Uint16 rsvd5:1; // 11 Reserved - Uint16 PGV:1; // 12 Programming Verify Status - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:1; // 16 Reserved - Uint16 rsvd10:1; // 17 Reserved - Uint16 rsvd11:14; // 31:18 Reserved -}; - -union FMSTAT_REG { - Uint32 all; - struct FMSTAT_BITS bit; -}; - -struct FRD_INTF_CTRL_BITS { // bits description - Uint16 PREFETCH_EN:1; // 0 Prefetch Enable - Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FRD_INTF_CTRL_REG { - Uint32 all; - struct FRD_INTF_CTRL_BITS bit; -}; - -struct FLASH_CTRL_REGS { - union FRDCNTL_REG FRDCNTL; // Flash Read Control Register - Uint16 rsvd1[28]; // Reserved - union FBAC_REG FBAC; // Flash Bank Access Control Register - union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register - union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register - union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 - union FPAC2_REG FPAC2; // Flash Pump Access Control Register 2 - Uint16 rsvd2[2]; // Reserved - union FMSTAT_REG FMSTAT; // Flash Module Status Register - Uint16 rsvd3[340]; // Reserved - union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register -}; - -struct ECC_ENABLE_BITS { // bits description - Uint16 ENABLE:4; // 3:0 Enable ECC - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECC_ENABLE_REG { - Uint32 all; - struct ECC_ENABLE_BITS bit; -}; - -struct ERR_STATUS_BITS { // bits description - Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_REG { - Uint32 all; - struct ERR_STATUS_BITS bit; -}; - -struct ERR_POS_BITS { // bits description - Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits - Uint16 rsvd2:7; // 15:9 Reserved - Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits - Uint16 rsvd4:7; // 31:25 Reserved -}; - -union ERR_POS_REG { - Uint32 all; - struct ERR_POS_BITS bit; -}; - -struct ERR_STATUS_CLR_BITS { // bits description - Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_CLR_REG { - Uint32 all; - struct ERR_STATUS_CLR_BITS bit; -}; - -struct ERR_CNT_BITS { // bits description - Uint16 ERR_CNT:16; // 15:0 Error counter - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_CNT_REG { - Uint32 all; - struct ERR_CNT_BITS bit; -}; - -struct ERR_THRESHOLD_BITS { // bits description - Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_THRESHOLD_REG { - Uint32 all; - struct ERR_THRESHOLD_BITS bit; -}; - -struct ERR_INTFLG_BITS { // bits description - Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag - Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTFLG_REG { - Uint32 all; - struct ERR_INTFLG_BITS bit; -}; - -struct ERR_INTCLR_BITS { // bits description - Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear - Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTCLR_REG { - Uint32 all; - struct ERR_INTCLR_BITS bit; -}; - -struct FADDR_TEST_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ADDRL:13; // 15:3 ECC Address Low - Uint16 ADDRH:6; // 21:16 ECC Address High - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union FADDR_TEST_REG { - Uint32 all; - struct FADDR_TEST_BITS bit; -}; - -struct FECC_TEST_BITS { // bits description - Uint16 ECC:8; // 7:0 ECC Control Bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_TEST_REG { - Uint32 all; - struct FECC_TEST_BITS bit; -}; - -struct FECC_CTRL_BITS { // bits description - Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic - Uint16 ECC_SELECT:1; // 1 ECC Bit Select - Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_CTRL_REG { - Uint32 all; - struct FECC_CTRL_BITS bit; -}; - -struct FECC_STATUS_BITS { // bits description - Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error - Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error - Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error - Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error - Uint16 rsvd1:7; // 15:9 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_STATUS_REG { - Uint32 all; - struct FECC_STATUS_BITS bit; -}; - -struct FLASH_ECC_REGS { - union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable - Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low - Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High - Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low - Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High - union ERR_STATUS_REG ERR_STATUS; // Error Status - union ERR_POS_REG ERR_POS; // Error Position - union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear - union ERR_CNT_REG ERR_CNT; // Error Control - union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold - union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag - union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear - Uint32 FDATAH_TEST; // Data High Test - Uint32 FDATAL_TEST; // Data Low Test - union FADDR_TEST_REG FADDR_TEST; // ECC Test Address - union FECC_TEST_REG FECC_TEST; // ECC Test Address - union FECC_CTRL_REG FECC_CTRL; // ECC Control - Uint32 FOUTH_TEST; // Test Data Out High - Uint32 FOUTL_TEST; // Test Data Out Low - union FECC_STATUS_REG FECC_STATUS; // ECC Status -}; - -//--------------------------------------------------------------------------- -// FLASH External References & Function Declarations: -// -extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; -extern volatile struct FLASH_ECC_REGS Flash0EccRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h deleted file mode 100644 index 3b7a7e9..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_fsi.h +++ /dev/null @@ -1,660 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_fsi.h -// -// TITLE: FSI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_FSI_H__ -#define __F28004X_FSI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FSI Individual Register Bit Definitions: - -struct TX_MASTER_CTRL_BITS { // bits description - Uint16 CORE_RST:1; // 0 Transmitter Master Core Reset - Uint16 FLUSH:1; // 1 Flush Operation Start - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union TX_MASTER_CTRL_REG { - Uint16 all; - struct TX_MASTER_CTRL_BITS bit; -}; - -struct TX_CLK_CTRL_BITS { // bits description - Uint16 CLK_RST:1; // 0 Soft Reset for the Clock Divider - Uint16 CLK_EN:1; // 1 Clock Divider Enable - Uint16 PRESCALE_VAL:8; // 9:2 Prescale value - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union TX_CLK_CTRL_REG { - Uint16 all; - struct TX_CLK_CTRL_BITS bit; -}; - -struct TX_OPER_CTRL_LO_BITS { // bits description - Uint16 DATA_WIDTH:2; // 1:0 Transmit Data width - Uint16 rsvd1:1; // 2 Reserved - Uint16 START_MODE:3; // 5:3 Transmission Start Mode Select - Uint16 SW_CRC:1; // 6 CRC Source Select - Uint16 PING_TO_MODE:1; // 7 Ping Counter Reset Mode Select - Uint16 SEL_PLLCLK:1; // 8 Input Clock Select - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union TX_OPER_CTRL_LO_REG { - Uint16 all; - struct TX_OPER_CTRL_LO_BITS bit; -}; - -struct TX_OPER_CTRL_HI_BITS { // bits description - Uint16 EXT_TRIG_SEL:5; // 4:0 External Trigger Select - Uint16 FORCE_ERR:1; // 5 Error Frame Force - Uint16 ECC_SEL:1; // 6 ECC Data Width Select - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TX_OPER_CTRL_HI_REG { - Uint16 all; - struct TX_OPER_CTRL_HI_BITS bit; -}; - -struct TX_FRAME_CTRL_BITS { // bits description - Uint16 FRAME_TYPE:4; // 3:0 Transmit Frame Type - Uint16 N_WORDS:4; // 7:4 Number of Words to be Transmitted - Uint16 rsvd1:7; // 14:8 Reserved - Uint16 START:1; // 15 Start Transmission -}; - -union TX_FRAME_CTRL_REG { - Uint16 all; - struct TX_FRAME_CTRL_BITS bit; -}; - -struct TX_FRAME_TAG_UDATA_BITS { // bits description - Uint16 FRAME_TAG:4; // 3:0 Frame Tag - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 USER_DATA:8; // 15:8 User Data -}; - -union TX_FRAME_TAG_UDATA_REG { - Uint16 all; - struct TX_FRAME_TAG_UDATA_BITS bit; -}; - -struct TX_BUF_PTR_LOAD_BITS { // bits description - Uint16 BUF_PTR_LOAD:4; // 3:0 Buffer Pointer Force Load - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_BUF_PTR_LOAD_REG { - Uint16 all; - struct TX_BUF_PTR_LOAD_BITS bit; -}; - -struct TX_BUF_PTR_STS_BITS { // bits description - Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 CURR_WORD_CNT:5; // 12:8 Remaining Words in Buffer - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union TX_BUF_PTR_STS_REG { - Uint16 all; - struct TX_BUF_PTR_STS_BITS bit; -}; - -struct TX_PING_CTRL_BITS { // bits description - Uint16 CNT_RST:1; // 0 Ping Counter Reset - Uint16 TIMER_EN:1; // 1 Ping Counter Enable - Uint16 EXT_TRIG_EN:1; // 2 External Trigger Enable - Uint16 EXT_TRIG_SEL:5; // 7:3 External Trigger Select - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_PING_CTRL_REG { - Uint16 all; - struct TX_PING_CTRL_BITS bit; -}; - -struct TX_PING_TAG_BITS { // bits description - Uint16 TAG:4; // 3:0 Ping Frame Tag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_PING_TAG_REG { - Uint16 all; - struct TX_PING_TAG_BITS bit; -}; - -struct TX_INT_CTRL_BITS { // bits description - Uint16 INT1_EN_FRAME_DONE:1; // 0 Enable Frame Done Interrupt to INT1 - Uint16 INT1_EN_BUF_UNDERRUN:1; // 1 Enable Buffer Underrun Interrupt to INT1 - Uint16 INT1_EN_BUF_OVERRUN:1; // 2 Enable Buffer Overrun Interrupt to INT1 - Uint16 INT1_EN_PING_TO:1; // 3 Enable Ping Timer Interrupt to INT1 - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 INT2_EN_FRAME_DONE:1; // 8 Enable Frame Done Interrupt to INT2 - Uint16 INT2_EN_BUF_UNDERRUN:1; // 9 Enable Buffer Underrun Interrupt to INT2 - Uint16 INT2_EN_BUF_OVERRUN:1; // 10 Enable Buffer Overrun Interrupt to INT2 - Uint16 INT2_EN_PING_TO:1; // 11 Enable Ping Timer Interrupt to INT2 - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union TX_INT_CTRL_REG { - Uint16 all; - struct TX_INT_CTRL_BITS bit; -}; - -struct TX_DMA_CTRL_BITS { // bits description - Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TX_DMA_CTRL_REG { - Uint16 all; - struct TX_DMA_CTRL_BITS bit; -}; - -struct TX_LOCK_CTRL_BITS { // bits description - Uint16 LOCK:1; // 0 Control Register Lock Enable - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union TX_LOCK_CTRL_REG { - Uint16 all; - struct TX_LOCK_CTRL_BITS bit; -}; - -struct TX_EVT_STS_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_STS_REG { - Uint16 all; - struct TX_EVT_STS_BITS bit; -}; - -struct TX_EVT_CLR_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag Clear - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Clear - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Clear - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_CLR_REG { - Uint16 all; - struct TX_EVT_CLR_BITS bit; -}; - -struct TX_EVT_FRC_BITS { // bits description - Uint16 FRAME_DONE:1; // 0 Frame Done Flag Force - Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Force - Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Force - Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Force - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union TX_EVT_FRC_REG { - Uint16 all; - struct TX_EVT_FRC_BITS bit; -}; - -struct TX_USER_CRC_BITS { // bits description - Uint16 USER_CRC:8; // 7:0 User-defined CRC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_USER_CRC_REG { - Uint16 all; - struct TX_USER_CRC_BITS bit; -}; - -struct TX_ECC_DATA_BITS { // bits description - Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits - Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits -}; - -union TX_ECC_DATA_REG { - Uint32 all; - struct TX_ECC_DATA_BITS bit; -}; - -struct TX_ECC_VAL_BITS { // bits description - Uint16 ECC_VAL:8; // 7:0 Computed ECC Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TX_ECC_VAL_REG { - Uint16 all; - struct TX_ECC_VAL_BITS bit; -}; - -struct FSI_TX_REGS { - union TX_MASTER_CTRL_REG TX_MASTER_CTRL; // Transmit master control register - Uint16 rsvd1; // Reserved - union TX_CLK_CTRL_REG TX_CLK_CTRL; // Transmit clock control register - Uint16 rsvd2; // Reserved - union TX_OPER_CTRL_LO_REG TX_OPER_CTRL_LO; // Transmit operation control register low - union TX_OPER_CTRL_HI_REG TX_OPER_CTRL_HI; // Transmit operation control register high - union TX_FRAME_CTRL_REG TX_FRAME_CTRL; // Transmit frame control register - union TX_FRAME_TAG_UDATA_REG TX_FRAME_TAG_UDATA; // Transmit frame tag and user data register - union TX_BUF_PTR_LOAD_REG TX_BUF_PTR_LOAD; // Transmit buffer pointer control load register - union TX_BUF_PTR_STS_REG TX_BUF_PTR_STS; // Transmit buffer pointer control status register - union TX_PING_CTRL_REG TX_PING_CTRL; // Transmit ping control register - union TX_PING_TAG_REG TX_PING_TAG; // Transmit ping tag register - Uint32 TX_PING_TO_REF; // Transmit ping timeout counter reference - Uint32 TX_PING_TO_CNT; // Transmit ping timeout current count - union TX_INT_CTRL_REG TX_INT_CTRL; // Transmit interrupt event control register - union TX_DMA_CTRL_REG TX_DMA_CTRL; // Transmit DMA event control register - union TX_LOCK_CTRL_REG TX_LOCK_CTRL; // Transmit lock control register - Uint16 rsvd3; // Reserved - union TX_EVT_STS_REG TX_EVT_STS; // Transmit event and error status flag register - Uint16 rsvd4; // Reserved - union TX_EVT_CLR_REG TX_EVT_CLR; // Transmit event and error clear register - union TX_EVT_FRC_REG TX_EVT_FRC; // Transmit event and error flag force register - union TX_USER_CRC_REG TX_USER_CRC; // Transmit user-defined CRC register - Uint16 rsvd5[7]; // Reserved - union TX_ECC_DATA_REG TX_ECC_DATA; // Transmit ECC data register - union TX_ECC_VAL_REG TX_ECC_VAL; // Transmit ECC value register - Uint16 rsvd6[29]; // Reserved - Uint16 TX_BUF_BASE; // Base address for transmit buffer -}; - -struct RX_MASTER_CTRL_BITS { // bits description - Uint16 CORE_RST:1; // 0 Receiver Master Core Reset - Uint16 INT_LOOPBACK:1; // 1 Internal Loopback Enable - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:5; // 7:3 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union RX_MASTER_CTRL_REG { - Uint16 all; - struct RX_MASTER_CTRL_BITS bit; -}; - -struct RX_OPER_CTRL_BITS { // bits description - Uint16 DATA_WIDTH:2; // 1:0 Receive Data Width Select - Uint16 rsvd1:1; // 2 Reserved - Uint16 N_WORDS:4; // 6:3 Number of Words to be Received - Uint16 ECC_SEL:1; // 7 ECC Data Width Select - Uint16 PING_WD_RST_MODE:1; // 8 Ping Watchdog Timeout Mode Select - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union RX_OPER_CTRL_REG { - Uint16 all; - struct RX_OPER_CTRL_BITS bit; -}; - -struct RX_FRAME_INFO_BITS { // bits description - Uint16 FRAME_TYPE:4; // 3:0 Received Frame Type - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RX_FRAME_INFO_REG { - Uint16 all; - struct RX_FRAME_INFO_BITS bit; -}; - -struct RX_FRAME_TAG_UDATA_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 FRAME_TAG:4; // 4:1 Received Frame Tag - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 USER_DATA:8; // 15:8 Received User Data -}; - -union RX_FRAME_TAG_UDATA_REG { - Uint16 all; - struct RX_FRAME_TAG_UDATA_BITS bit; -}; - -struct RX_DMA_CTRL_BITS { // bits description - Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union RX_DMA_CTRL_REG { - Uint16 all; - struct RX_DMA_CTRL_BITS bit; -}; - -struct RX_EVT_STS_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag. - Uint16 CRC_ERR:1; // 2 CRC Error Flag - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag - Uint16 FRAME_DONE:1; // 6 Frame Done Flag - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag - Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_STS_REG { - Uint16 all; - struct RX_EVT_STS_BITS bit; -}; - -struct RX_CRC_INFO_BITS { // bits description - Uint16 RX_CRC:8; // 7:0 Received CRC Value - Uint16 CALC_CRC:8; // 15:8 Hardware Calculated CRC -}; - -union RX_CRC_INFO_REG { - Uint16 all; - struct RX_CRC_INFO_BITS bit; -}; - -struct RX_EVT_CLR_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Clear - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Clear - Uint16 CRC_ERR:1; // 2 CRC Error Flag Clear - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Clear - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Clear - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Clear - Uint16 FRAME_DONE:1; // 6 Frame Done Flag Clear - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Clear - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Clear - Uint16 PING_FRAME:1; // 9 PING Frame Received Flag Clear - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Clear - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Clear - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_CLR_REG { - Uint16 all; - struct RX_EVT_CLR_BITS bit; -}; - -struct RX_EVT_FRC_BITS { // bits description - Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Force - Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Force - Uint16 CRC_ERR:1; // 2 CRC Error Flag Force - Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Force - Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Force - Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Force - Uint16 FRAME_DONE:1; // 6 Frame Done Flag Force - Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Force - Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Force - Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Force - Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Force - Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Force - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_EVT_FRC_REG { - Uint16 all; - struct RX_EVT_FRC_BITS bit; -}; - -struct RX_BUF_PTR_LOAD_BITS { // bits description - Uint16 BUF_PTR_LOAD:4; // 3:0 Load value for receive buffer pointer - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RX_BUF_PTR_LOAD_REG { - Uint16 all; - struct RX_BUF_PTR_LOAD_BITS bit; -}; - -struct RX_BUF_PTR_STS_BITS { // bits description - Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 CURR_WORD_CNT:5; // 12:8 Available Words in Buffer - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union RX_BUF_PTR_STS_REG { - Uint16 all; - struct RX_BUF_PTR_STS_BITS bit; -}; - -struct RX_FRAME_WD_CTRL_BITS { // bits description - Uint16 FRAME_WD_CNT_RST:1; // 0 Frame Watchdog Counter Reset - Uint16 FRAME_WD_EN:1; // 1 Frame Watchdog Counter Enable - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_FRAME_WD_CTRL_REG { - Uint16 all; - struct RX_FRAME_WD_CTRL_BITS bit; -}; - -struct RX_PING_WD_CTRL_BITS { // bits description - Uint16 PING_WD_RST:1; // 0 Ping Watchdog Counter Reset - Uint16 PING_WD_EN:1; // 1 Ping Watchdog Counter Enable - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_PING_WD_CTRL_REG { - Uint16 all; - struct RX_PING_WD_CTRL_BITS bit; -}; - -struct RX_PING_TAG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PING_TAG:4; // 4:1 Ping Frame Tag - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union RX_PING_TAG_REG { - Uint16 all; - struct RX_PING_TAG_BITS bit; -}; - -struct RX_INT1_CTRL_BITS { // bits description - Uint16 INT1_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT1 - Uint16 INT1_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT1 - Uint16 INT1_EN_CRC_ERR:1; // 2 Enable CRC Error Interrupt to INT1 - Uint16 INT1_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT1 - Uint16 INT1_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT1 - Uint16 INT1_EN_OVERRUN:1; // 5 Enable Receive Buffer Overrun Interrupt to INT1 - Uint16 INT1_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT1 - Uint16 INT1_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT1 - Uint16 INT1_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT1 - Uint16 INT1_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT1 - Uint16 INT1_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT1 - Uint16 INT1_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT1 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_INT1_CTRL_REG { - Uint16 all; - struct RX_INT1_CTRL_BITS bit; -}; - -struct RX_INT2_CTRL_BITS { // bits description - Uint16 INT2_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT2 - Uint16 INT2_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT2 - Uint16 INT2_EN_CRC_ERR:1; // 2 Enable CRC Errror Interrupt to INT2 - Uint16 INT2_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT2 - Uint16 INT2_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT2 - Uint16 INT2_EN_OVERRUN:1; // 5 Enable Buffer Overrun Interrupt to INT2 - Uint16 INT2_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT2 - Uint16 INT2_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT2 - Uint16 INT2_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT2 - Uint16 INT2_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT2 - Uint16 INT2_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT2 - Uint16 INT2_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union RX_INT2_CTRL_REG { - Uint16 all; - struct RX_INT2_CTRL_BITS bit; -}; - -struct RX_LOCK_CTRL_BITS { // bits description - Uint16 LOCK:1; // 0 Control Register Lock Enable - Uint16 rsvd1:7; // 7:1 Reserved - Uint16 KEY:8; // 15:8 Write Key -}; - -union RX_LOCK_CTRL_REG { - Uint16 all; - struct RX_LOCK_CTRL_BITS bit; -}; - -struct RX_ECC_DATA_BITS { // bits description - Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits - Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits -}; - -union RX_ECC_DATA_REG { - Uint32 all; - struct RX_ECC_DATA_BITS bit; -}; - -struct RX_ECC_VAL_BITS { // bits description - Uint16 ECC_VAL:8; // 7:0 Computed ECC Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union RX_ECC_VAL_REG { - Uint16 all; - struct RX_ECC_VAL_BITS bit; -}; - -struct RX_ECC_LOG_BITS { // bits description - Uint16 SBE:1; // 0 Single Bit Error Detected - Uint16 MBE:1; // 1 Multiple Bit Errors Detected - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union RX_ECC_LOG_REG { - Uint16 all; - struct RX_ECC_LOG_BITS bit; -}; - -struct RX_DLYLINE_CTRL_BITS { // bits description - Uint16 RXCLK_DLY:5; // 4:0 Delay Line Tap Select for RXCLK - Uint16 RXD0_DLY:5; // 9:5 Delay Line Tap Select for RXD0 - Uint16 RXD1_DLY:5; // 14:10 Delay Line Tap Select for RXD1 - Uint16 rsvd1:1; // 15 Reserved -}; - -union RX_DLYLINE_CTRL_REG { - Uint16 all; - struct RX_DLYLINE_CTRL_BITS bit; -}; - -struct RX_VIS_1_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 RX_CORE_STS:1; // 3 Receiver Core Status - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union RX_VIS_1_REG { - Uint32 all; - struct RX_VIS_1_BITS bit; -}; - -struct FSI_RX_REGS { - union RX_MASTER_CTRL_REG RX_MASTER_CTRL; // Receive master control register - Uint16 rsvd1[3]; // Reserved - union RX_OPER_CTRL_REG RX_OPER_CTRL; // Receive operation control register - Uint16 rsvd2; // Reserved - union RX_FRAME_INFO_REG RX_FRAME_INFO; // Receive frame control register - union RX_FRAME_TAG_UDATA_REG RX_FRAME_TAG_UDATA; // Receive frame tag and user data register - union RX_DMA_CTRL_REG RX_DMA_CTRL; // Receive DMA event control register - Uint16 rsvd3; // Reserved - union RX_EVT_STS_REG RX_EVT_STS; // Receive event and error status flag register - union RX_CRC_INFO_REG RX_CRC_INFO; // Receive CRC info of received and computed CRC - union RX_EVT_CLR_REG RX_EVT_CLR; // Receive event and error clear register - union RX_EVT_FRC_REG RX_EVT_FRC; // Receive event and error flag force register - union RX_BUF_PTR_LOAD_REG RX_BUF_PTR_LOAD; // Receive buffer pointer load register - union RX_BUF_PTR_STS_REG RX_BUF_PTR_STS; // Receive buffer pointer status register - union RX_FRAME_WD_CTRL_REG RX_FRAME_WD_CTRL; // Receive frame watchdog control register - Uint16 rsvd4; // Reserved - Uint32 RX_FRAME_WD_REF; // Receive frame watchdog counter reference - Uint32 RX_FRAME_WD_CNT; // Receive frame watchdog current count - union RX_PING_WD_CTRL_REG RX_PING_WD_CTRL; // Receive ping watchdog control register - union RX_PING_TAG_REG RX_PING_TAG; // Receive ping tag register - Uint32 RX_PING_WD_REF; // Receive ping watchdog counter reference - Uint32 RX_PING_WD_CNT; // Receive pingwatchdog current count - union RX_INT1_CTRL_REG RX_INT1_CTRL; // Receive interrupt control register for RX_INT1 - union RX_INT2_CTRL_REG RX_INT2_CTRL; // Receive interrupt control register for RX_INT2 - union RX_LOCK_CTRL_REG RX_LOCK_CTRL; // Receive lock control register - Uint16 rsvd5; // Reserved - union RX_ECC_DATA_REG RX_ECC_DATA; // Receive ECC data register - union RX_ECC_VAL_REG RX_ECC_VAL; // Receive ECC value register - Uint16 rsvd6; // Reserved - Uint32 RX_ECC_SEC_DATA; // Receive ECC corrected data register - union RX_ECC_LOG_REG RX_ECC_LOG; // Receive ECC log and status register - Uint16 rsvd7[9]; // Reserved - union RX_DLYLINE_CTRL_REG RX_DLYLINE_CTRL; // Receive delay line control register - Uint16 rsvd8[7]; // Reserved - union RX_VIS_1_REG RX_VIS_1; // Receive debug visibility register 1 - Uint16 rsvd9[6]; // Reserved - Uint16 RX_BUF_BASE; // Base address for receive data buffer -}; - -//--------------------------------------------------------------------------- -// FSI External References & Function Declarations: -// -extern volatile struct FSI_TX_REGS FsiTxaRegs; -extern volatile struct FSI_RX_REGS FsiRxaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h deleted file mode 100644 index 0c05ef1..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_gpio.h +++ /dev/null @@ -1,1678 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_gpio.h -// -// TITLE: GPIO Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_GPIO_H__ -#define __F28004X_GPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// GPIO Individual Register Bit Definitions: - -struct GPACTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 -}; - -union GPACTRL_REG { - Uint32 all; - struct GPACTRL_BITS bit; -}; - -struct GPAQSEL1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 - Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 - Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 - Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 - Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 - Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 - Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 - Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 - Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 - Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 - Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 - Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 - Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 - Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 - Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 - Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 -}; - -union GPAQSEL1_REG { - Uint32 all; - struct GPAQSEL1_BITS bit; -}; - -struct GPAQSEL2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 - Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 - Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 - Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 - Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 - Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 - Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 - Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 - Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 - Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 - Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 - Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 - Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 - Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 - Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 - Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 -}; - -union GPAQSEL2_REG { - Uint32 all; - struct GPAQSEL2_BITS bit; -}; - -struct GPAMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAMUX1_REG { - Uint32 all; - struct GPAMUX1_BITS bit; -}; - -struct GPAMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAMUX2_REG { - Uint32 all; - struct GPAMUX2_BITS bit; -}; - -struct GPADIR_BITS { // bits description - Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPADIR_REG { - Uint32 all; - struct GPADIR_BITS bit; -}; - -struct GPAPUD_BITS { // bits description - Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin -}; - -union GPAPUD_REG { - Uint32 all; - struct GPAPUD_BITS bit; -}; - -struct GPAINV_BITS { // bits description - Uint16 GPIO0:1; // 0 Input inversion control for this pin - Uint16 GPIO1:1; // 1 Input inversion control for this pin - Uint16 GPIO2:1; // 2 Input inversion control for this pin - Uint16 GPIO3:1; // 3 Input inversion control for this pin - Uint16 GPIO4:1; // 4 Input inversion control for this pin - Uint16 GPIO5:1; // 5 Input inversion control for this pin - Uint16 GPIO6:1; // 6 Input inversion control for this pin - Uint16 GPIO7:1; // 7 Input inversion control for this pin - Uint16 GPIO8:1; // 8 Input inversion control for this pin - Uint16 GPIO9:1; // 9 Input inversion control for this pin - Uint16 GPIO10:1; // 10 Input inversion control for this pin - Uint16 GPIO11:1; // 11 Input inversion control for this pin - Uint16 GPIO12:1; // 12 Input inversion control for this pin - Uint16 GPIO13:1; // 13 Input inversion control for this pin - Uint16 GPIO14:1; // 14 Input inversion control for this pin - Uint16 GPIO15:1; // 15 Input inversion control for this pin - Uint16 GPIO16:1; // 16 Input inversion control for this pin - Uint16 GPIO17:1; // 17 Input inversion control for this pin - Uint16 GPIO18:1; // 18 Input inversion control for this pin - Uint16 GPIO19:1; // 19 Input inversion control for this pin - Uint16 GPIO20:1; // 20 Input inversion control for this pin - Uint16 GPIO21:1; // 21 Input inversion control for this pin - Uint16 GPIO22:1; // 22 Input inversion control for this pin - Uint16 GPIO23:1; // 23 Input inversion control for this pin - Uint16 GPIO24:1; // 24 Input inversion control for this pin - Uint16 GPIO25:1; // 25 Input inversion control for this pin - Uint16 GPIO26:1; // 26 Input inversion control for this pin - Uint16 GPIO27:1; // 27 Input inversion control for this pin - Uint16 GPIO28:1; // 28 Input inversion control for this pin - Uint16 GPIO29:1; // 29 Input inversion control for this pin - Uint16 GPIO30:1; // 30 Input inversion control for this pin - Uint16 GPIO31:1; // 31 Input inversion control for this pin -}; - -union GPAINV_REG { - Uint32 all; - struct GPAINV_BITS bit; -}; - -struct GPAODR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Open-Drain control for this pin - Uint16 GPIO1:1; // 1 Output Open-Drain control for this pin - Uint16 GPIO2:1; // 2 Output Open-Drain control for this pin - Uint16 GPIO3:1; // 3 Output Open-Drain control for this pin - Uint16 GPIO4:1; // 4 Output Open-Drain control for this pin - Uint16 GPIO5:1; // 5 Output Open-Drain control for this pin - Uint16 GPIO6:1; // 6 Output Open-Drain control for this pin - Uint16 GPIO7:1; // 7 Output Open-Drain control for this pin - Uint16 GPIO8:1; // 8 Output Open-Drain control for this pin - Uint16 GPIO9:1; // 9 Output Open-Drain control for this pin - Uint16 GPIO10:1; // 10 Output Open-Drain control for this pin - Uint16 GPIO11:1; // 11 Output Open-Drain control for this pin - Uint16 GPIO12:1; // 12 Output Open-Drain control for this pin - Uint16 GPIO13:1; // 13 Output Open-Drain control for this pin - Uint16 GPIO14:1; // 14 Output Open-Drain control for this pin - Uint16 GPIO15:1; // 15 Output Open-Drain control for this pin - Uint16 GPIO16:1; // 16 Output Open-Drain control for this pin - Uint16 GPIO17:1; // 17 Output Open-Drain control for this pin - Uint16 GPIO18:1; // 18 Output Open-Drain control for this pin - Uint16 GPIO19:1; // 19 Output Open-Drain control for this pin - Uint16 GPIO20:1; // 20 Output Open-Drain control for this pin - Uint16 GPIO21:1; // 21 Output Open-Drain control for this pin - Uint16 GPIO22:1; // 22 Output Open-Drain control for this pin - Uint16 GPIO23:1; // 23 Output Open-Drain control for this pin - Uint16 GPIO24:1; // 24 Output Open-Drain control for this pin - Uint16 GPIO25:1; // 25 Output Open-Drain control for this pin - Uint16 GPIO26:1; // 26 Output Open-Drain control for this pin - Uint16 GPIO27:1; // 27 Output Open-Drain control for this pin - Uint16 GPIO28:1; // 28 Output Open-Drain control for this pin - Uint16 GPIO29:1; // 29 Output Open-Drain control for this pin - Uint16 GPIO30:1; // 30 Output Open-Drain control for this pin - Uint16 GPIO31:1; // 31 Output Open-Drain control for this pin -}; - -union GPAODR_REG { - Uint32 all; - struct GPAODR_BITS bit; -}; - -struct GPAAMSEL_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:1; // 8 Reserved - Uint16 rsvd10:1; // 9 Reserved - Uint16 rsvd11:1; // 10 Reserved - Uint16 rsvd12:1; // 11 Reserved - Uint16 rsvd13:1; // 12 Reserved - Uint16 rsvd14:1; // 13 Reserved - Uint16 rsvd15:1; // 14 Reserved - Uint16 rsvd16:1; // 15 Reserved - Uint16 rsvd17:1; // 16 Reserved - Uint16 rsvd18:1; // 17 Reserved - Uint16 rsvd19:1; // 18 Reserved - Uint16 rsvd20:1; // 19 Reserved - Uint16 rsvd21:1; // 20 Reserved - Uint16 rsvd22:1; // 21 Reserved - Uint16 GPIO22:1; // 22 Analog Mode select for this pin - Uint16 GPIO23:1; // 23 Analog Mode select for this pin - Uint16 rsvd23:1; // 24 Reserved - Uint16 rsvd24:1; // 25 Reserved - Uint16 rsvd25:1; // 26 Reserved - Uint16 rsvd26:1; // 27 Reserved - Uint16 rsvd27:1; // 28 Reserved - Uint16 rsvd28:1; // 29 Reserved - Uint16 rsvd29:1; // 30 Reserved - Uint16 rsvd30:1; // 31 Reserved -}; - -union GPAAMSEL_REG { - Uint32 all; - struct GPAAMSEL_BITS bit; -}; - -struct GPAGMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAGMUX1_REG { - Uint32 all; - struct GPAGMUX1_BITS bit; -}; - -struct GPAGMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAGMUX2_REG { - Uint32 all; - struct GPAGMUX2_BITS bit; -}; - -struct GPACSEL1_BITS { // bits description - Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select - Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select - Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select - Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select - Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select - Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select - Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select - Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select -}; - -union GPACSEL1_REG { - Uint32 all; - struct GPACSEL1_BITS bit; -}; - -struct GPACSEL2_BITS { // bits description - Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select - Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select - Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select - Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select - Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select - Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select - Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select - Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select -}; - -union GPACSEL2_REG { - Uint32 all; - struct GPACSEL2_BITS bit; -}; - -struct GPACSEL3_BITS { // bits description - Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select - Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select - Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select - Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select - Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select - Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select - Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select - Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select -}; - -union GPACSEL3_REG { - Uint32 all; - struct GPACSEL3_BITS bit; -}; - -struct GPACSEL4_BITS { // bits description - Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select - Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select - Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select - Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select - Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select - Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select - Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select - Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select -}; - -union GPACSEL4_REG { - Uint32 all; - struct GPACSEL4_BITS bit; -}; - -struct GPALOCK_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin -}; - -union GPALOCK_REG { - Uint32 all; - struct GPALOCK_BITS bit; -}; - -struct GPACR_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin -}; - -union GPACR_REG { - Uint32 all; - struct GPACR_BITS bit; -}; - -struct GPBCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 -}; - -union GPBCTRL_REG { - Uint32 all; - struct GPBCTRL_BITS bit; -}; - -struct GPBQSEL1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 - Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 - Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 - Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 - Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 - Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 - Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 - Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 - Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 - Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 - Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 - Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 -}; - -union GPBQSEL1_REG { - Uint32 all; - struct GPBQSEL1_BITS bit; -}; - -struct GPBQSEL2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 - Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 - Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 - Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 - Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 - Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 - Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 - Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 - Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 - Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 - Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 - Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBQSEL2_REG { - Uint32 all; - struct GPBQSEL2_BITS bit; -}; - -struct GPBMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBMUX1_REG { - Uint32 all; - struct GPBMUX1_BITS bit; -}; - -struct GPBMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBMUX2_REG { - Uint32 all; - struct GPBMUX2_BITS bit; -}; - -struct GPBDIR_BITS { // bits description - Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBDIR_REG { - Uint32 all; - struct GPBDIR_BITS bit; -}; - -struct GPBPUD_BITS { // bits description - Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBPUD_REG { - Uint32 all; - struct GPBPUD_BITS bit; -}; - -struct GPBINV_BITS { // bits description - Uint16 GPIO32:1; // 0 Input inversion control for this pin - Uint16 GPIO33:1; // 1 Input inversion control for this pin - Uint16 GPIO34:1; // 2 Input inversion control for this pin - Uint16 GPIO35:1; // 3 Input inversion control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Input inversion control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Input inversion control for this pin - Uint16 GPIO40:1; // 8 Input inversion control for this pin - Uint16 GPIO41:1; // 9 Input inversion control for this pin - Uint16 GPIO42:1; // 10 Input inversion control for this pin - Uint16 GPIO43:1; // 11 Input inversion control for this pin - Uint16 GPIO44:1; // 12 Input inversion control for this pin - Uint16 GPIO45:1; // 13 Input inversion control for this pin - Uint16 GPIO46:1; // 14 Input inversion control for this pin - Uint16 GPIO47:1; // 15 Input inversion control for this pin - Uint16 GPIO48:1; // 16 Input inversion control for this pin - Uint16 GPIO49:1; // 17 Input inversion control for this pin - Uint16 GPIO50:1; // 18 Input inversion control for this pin - Uint16 GPIO51:1; // 19 Input inversion control for this pin - Uint16 GPIO52:1; // 20 Input inversion control for this pin - Uint16 GPIO53:1; // 21 Input inversion control for this pin - Uint16 GPIO54:1; // 22 Input inversion control for this pin - Uint16 GPIO55:1; // 23 Input inversion control for this pin - Uint16 GPIO56:1; // 24 Input inversion control for this pin - Uint16 GPIO57:1; // 25 Input inversion control for this pin - Uint16 GPIO58:1; // 26 Input inversion control for this pin - Uint16 GPIO59:1; // 27 Input inversion control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBINV_REG { - Uint32 all; - struct GPBINV_BITS bit; -}; - -struct GPBODR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Open-Drain control for this pin - Uint16 GPIO33:1; // 1 Output Open-Drain control for this pin - Uint16 GPIO34:1; // 2 Output Open-Drain control for this pin - Uint16 GPIO35:1; // 3 Output Open-Drain control for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Open-Drain control for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Open-Drain control for this pin - Uint16 GPIO40:1; // 8 Output Open-Drain control for this pin - Uint16 GPIO41:1; // 9 Output Open-Drain control for this pin - Uint16 GPIO42:1; // 10 Output Open-Drain control for this pin - Uint16 GPIO43:1; // 11 Output Open-Drain control for this pin - Uint16 GPIO44:1; // 12 Output Open-Drain control for this pin - Uint16 GPIO45:1; // 13 Output Open-Drain control for this pin - Uint16 GPIO46:1; // 14 Output Open-Drain control for this pin - Uint16 GPIO47:1; // 15 Output Open-Drain control for this pin - Uint16 GPIO48:1; // 16 Output Open-Drain control for this pin - Uint16 GPIO49:1; // 17 Output Open-Drain control for this pin - Uint16 GPIO50:1; // 18 Output Open-Drain control for this pin - Uint16 GPIO51:1; // 19 Output Open-Drain control for this pin - Uint16 GPIO52:1; // 20 Output Open-Drain control for this pin - Uint16 GPIO53:1; // 21 Output Open-Drain control for this pin - Uint16 GPIO54:1; // 22 Output Open-Drain control for this pin - Uint16 GPIO55:1; // 23 Output Open-Drain control for this pin - Uint16 GPIO56:1; // 24 Output Open-Drain control for this pin - Uint16 GPIO57:1; // 25 Output Open-Drain control for this pin - Uint16 GPIO58:1; // 26 Output Open-Drain control for this pin - Uint16 GPIO59:1; // 27 Output Open-Drain control for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBODR_REG { - Uint32 all; - struct GPBODR_BITS bit; -}; - -struct GPBGMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBGMUX1_REG { - Uint32 all; - struct GPBGMUX1_BITS bit; -}; - -struct GPBGMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 rsvd1:2; // 25:24 Reserved - Uint16 rsvd2:2; // 27:26 Reserved - Uint16 rsvd3:2; // 29:28 Reserved - Uint16 rsvd4:2; // 31:30 Reserved -}; - -union GPBGMUX2_REG { - Uint32 all; - struct GPBGMUX2_BITS bit; -}; - -struct GPBCSEL1_BITS { // bits description - Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select - Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select - Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select - Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select - Uint16 rsvd1:4; // 19:16 Reserved - Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select - Uint16 rsvd2:4; // 27:24 Reserved - Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select -}; - -union GPBCSEL1_REG { - Uint32 all; - struct GPBCSEL1_BITS bit; -}; - -struct GPBCSEL2_BITS { // bits description - Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select - Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select - Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select - Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select - Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select - Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select - Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select - Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select -}; - -union GPBCSEL2_REG { - Uint32 all; - struct GPBCSEL2_BITS bit; -}; - -struct GPBCSEL3_BITS { // bits description - Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select - Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select - Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select - Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select - Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select - Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select - Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select - Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select -}; - -union GPBCSEL3_REG { - Uint32 all; - struct GPBCSEL3_BITS bit; -}; - -struct GPBCSEL4_BITS { // bits description - Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select - Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select - Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select - Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select - Uint16 rsvd1:4; // 19:16 Reserved - Uint16 rsvd2:4; // 23:20 Reserved - Uint16 rsvd3:4; // 27:24 Reserved - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union GPBCSEL4_REG { - Uint32 all; - struct GPBCSEL4_BITS bit; -}; - -struct GPBLOCK_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBLOCK_REG { - Uint32 all; - struct GPBLOCK_BITS bit; -}; - -struct GPBCR_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBCR_REG { - Uint32 all; - struct GPBCR_BITS bit; -}; - -struct GPHCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO224 to GPIO231 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO232 to GPIO239 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO240 to GPIO247 - Uint16 rsvd1:8; // 31:24 Reserved -}; - -union GPHCTRL_REG { - Uint32 all; - struct GPHCTRL_BITS bit; -}; - -struct GPHQSEL1_BITS { // bits description - Uint16 GPIO224:2; // 1:0 Select input qualification type for this GPIO Pin - Uint16 GPIO225:2; // 3:2 Select input qualification type for this GPIO Pin - Uint16 GPIO226:2; // 5:4 Select input qualification type for this GPIO Pin - Uint16 GPIO227:2; // 7:6 Select input qualification type for this GPIO Pin - Uint16 GPIO228:2; // 9:8 Select input qualification type for this GPIO Pin - Uint16 GPIO229:2; // 11:10 Select input qualification type for this GPIO Pin - Uint16 GPIO230:2; // 13:12 Select input qualification type for this GPIO Pin - Uint16 GPIO231:2; // 15:14 Select input qualification type for this GPIO Pin - Uint16 GPIO232:2; // 17:16 Select input qualification type for this GPIO Pin - Uint16 GPIO233:2; // 19:18 Select input qualification type for this GPIO Pin - Uint16 GPIO234:2; // 21:20 Select input qualification type for this GPIO Pin - Uint16 GPIO235:2; // 23:22 Select input qualification type for this GPIO Pin - Uint16 GPIO236:2; // 25:24 Select input qualification type for this GPIO Pin - Uint16 GPIO237:2; // 27:26 Select input qualification type for this GPIO Pin - Uint16 GPIO238:2; // 29:28 Select input qualification type for this GPIO Pin - Uint16 GPIO239:2; // 31:30 Select input qualification type for this GPIO Pin -}; - -union GPHQSEL1_REG { - Uint32 all; - struct GPHQSEL1_BITS bit; -}; - -struct GPHQSEL2_BITS { // bits description - Uint16 GPIO240:2; // 1:0 Select input qualification type for this GPIO Pin - Uint16 GPIO241:2; // 3:2 Select input qualification type for this GPIO Pin - Uint16 GPIO242:2; // 5:4 Select input qualification type for this GPIO Pin - Uint16 GPIO243:2; // 7:6 Select input qualification type for this GPIO Pin - Uint16 GPIO244:2; // 9:8 Select input qualification type for this GPIO Pin - Uint16 GPIO245:2; // 11:10 Select input qualification type for this GPIO Pin - Uint16 GPIO246:2; // 13:12 Select input qualification type for this GPIO Pin - Uint16 GPIO247:2; // 15:14 Select input qualification type for this GPIO Pin - Uint16 rsvd1:2; // 17:16 Reserved - Uint16 rsvd2:2; // 19:18 Reserved - Uint16 rsvd3:2; // 21:20 Reserved - Uint16 rsvd4:2; // 23:22 Reserved - Uint16 rsvd5:2; // 25:24 Reserved - Uint16 rsvd6:2; // 27:26 Reserved - Uint16 rsvd7:2; // 29:28 Reserved - Uint16 rsvd8:2; // 31:30 Reserved -}; - -union GPHQSEL2_REG { - Uint32 all; - struct GPHQSEL2_BITS bit; -}; - -struct GPHINV_BITS { // bits description - Uint16 GPIO224:1; // 0 Input inversion control for this pin - Uint16 GPIO225:1; // 1 Input inversion control for this pin - Uint16 GPIO226:1; // 2 Input inversion control for this pin - Uint16 GPIO227:1; // 3 Input inversion control for this pin - Uint16 GPIO228:1; // 4 Input inversion control for this pin - Uint16 GPIO229:1; // 5 Input inversion control for this pin - Uint16 GPIO230:1; // 6 Input inversion control for this pin - Uint16 GPIO231:1; // 7 Input inversion control for this pin - Uint16 GPIO232:1; // 8 Input inversion control for this pin - Uint16 GPIO233:1; // 9 Input inversion control for this pin - Uint16 GPIO234:1; // 10 Input inversion control for this pin - Uint16 GPIO235:1; // 11 Input inversion control for this pin - Uint16 GPIO236:1; // 12 Input inversion control for this pin - Uint16 GPIO237:1; // 13 Input inversion control for this pin - Uint16 GPIO238:1; // 14 Input inversion control for this pin - Uint16 GPIO239:1; // 15 Input inversion control for this pin - Uint16 GPIO240:1; // 16 Input inversion control for this pin - Uint16 GPIO241:1; // 17 Input inversion control for this pin - Uint16 GPIO242:1; // 18 Input inversion control for this pin - Uint16 GPIO243:1; // 19 Input inversion control for this pin - Uint16 GPIO244:1; // 20 Input inversion control for this pin - Uint16 GPIO245:1; // 21 Input inversion control for this pin - Uint16 GPIO246:1; // 22 Input inversion control for this pin - Uint16 GPIO247:1; // 23 Input inversion control for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHINV_REG { - Uint32 all; - struct GPHINV_BITS bit; -}; - -struct GPHAMSEL_BITS { // bits description - Uint16 GPIO224:1; // 0 Analog Mode select for this pin - Uint16 GPIO225:1; // 1 Analog Mode select for this pin - Uint16 GPIO226:1; // 2 Analog Mode select for this pin - Uint16 GPIO227:1; // 3 Analog Mode select for this pin - Uint16 GPIO228:1; // 4 Analog Mode select for this pin - Uint16 GPIO229:1; // 5 Analog Mode select for this pin - Uint16 GPIO230:1; // 6 Analog Mode select for this pin - Uint16 GPIO231:1; // 7 Analog Mode select for this pin - Uint16 GPIO232:1; // 8 Analog Mode select for this pin - Uint16 GPIO233:1; // 9 Analog Mode select for this pin - Uint16 GPIO234:1; // 10 Analog Mode select for this pin - Uint16 GPIO235:1; // 11 Analog Mode select for this pin - Uint16 GPIO236:1; // 12 Analog Mode select for this pin - Uint16 GPIO237:1; // 13 Analog Mode select for this pin - Uint16 GPIO238:1; // 14 Analog Mode select for this pin - Uint16 GPIO239:1; // 15 Analog Mode select for this pin - Uint16 GPIO240:1; // 16 Analog Mode select for this pin - Uint16 GPIO241:1; // 17 Analog Mode select for this pin - Uint16 GPIO242:1; // 18 Analog Mode select for this pin - Uint16 GPIO243:1; // 19 Analog Mode select for this pin - Uint16 GPIO244:1; // 20 Analog Mode select for this pin - Uint16 GPIO245:1; // 21 Analog Mode select for this pin - Uint16 GPIO246:1; // 22 Analog Mode select for this pin - Uint16 GPIO247:1; // 23 Analog Mode select for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHAMSEL_REG { - Uint32 all; - struct GPHAMSEL_BITS bit; -}; - -struct GPHLOCK_BITS { // bits description - Uint16 GPIO224:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO225:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO226:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO227:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO228:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO229:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO230:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO231:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO232:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO233:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO234:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO235:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO236:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO237:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO238:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO239:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO240:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO241:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO242:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO243:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO244:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO245:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO246:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO247:1; // 23 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHLOCK_REG { - Uint32 all; - struct GPHLOCK_BITS bit; -}; - -struct GPHCR_BITS { // bits description - Uint16 GPIO224:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO225:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO226:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO227:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO228:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO229:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO230:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO231:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO232:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO233:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO234:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO235:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO236:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO237:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO238:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO239:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO240:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO241:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO242:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO243:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO244:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO245:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO246:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO247:1; // 23 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHCR_REG { - Uint32 all; - struct GPHCR_BITS bit; -}; - -struct GPIO_CTRL_REGS { - union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period (GPIO0 to GPIO31) - union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualification Type (GPIO0 to GPIO15) - union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualification Type (GPIO16 to GPIO31) - union GPAMUX1_REG GPAMUX1; // GPIO A Peripheral Mux (GPIO0 to GPIO15) - union GPAMUX2_REG GPAMUX2; // GPIO A Peripheral Mux (GPIO16 to GPIO31) - union GPADIR_REG GPADIR; // GPIO A Direction (GPIO0 to GPIO31) - union GPAPUD_REG GPAPUD; // GPIO A Pull-Up Disable (GPIO0 to GPIO31) - Uint16 rsvd1[2]; // Reserved - union GPAINV_REG GPAINV; // GPIO A Input Inversion (GPIO0 to GPIO31) - union GPAODR_REG GPAODR; // GPIO A Open Drain Output Mode (GPIO0 to GPIO31) - union GPAAMSEL_REG GPAAMSEL; // GPIO A Analog Mode Select (GPIO0 to GPIO31) - Uint16 rsvd2[10]; // Reserved - union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to GPIO15) - union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to GPIO31) - Uint16 rsvd3[4]; // Reserved - union GPACSEL1_REG GPACSEL1; // GPIO A Master Core Select (GPIO0 to GPIO7) - union GPACSEL2_REG GPACSEL2; // GPIO A Master Core Select (GPIO8 to GPIO15) - union GPACSEL3_REG GPACSEL3; // GPIO A Master Core Select (GPIO16 to GPIO23) - union GPACSEL4_REG GPACSEL4; // GPIO A Master Core Select (GPIO24 to GPIO31) - Uint16 rsvd4[12]; // Reserved - union GPALOCK_REG GPALOCK; // GPIO A Lock Register (GPIO0 to GPIO31) - union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to GPIO31) - union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period (GPIO32 to GPIO63) - union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualification Type (GPIO32 to GPIO47) - union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualification Type (GPIO48 to GPIO63) - union GPBMUX1_REG GPBMUX1; // GPIO B Peripheral Mux (GPIO32 to GPIO47) - union GPBMUX2_REG GPBMUX2; // GPIO B Peripheral Mux (GPIO48 to GPIO63) - union GPBDIR_REG GPBDIR; // GPIO B Direction (GPIO32 to GPIO63) - union GPBPUD_REG GPBPUD; // GPIO B Pull-Up Disable (GPIO32 to GPIO63) - Uint16 rsvd5[2]; // Reserved - union GPBINV_REG GPBINV; // GPIO B Input Inversion (GPIO32 to GPIO63) - union GPBODR_REG GPBODR; // GPIO B Open Drain Output Mode (GPIO32 to GPIO63) - Uint16 rsvd6[12]; // Reserved - union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to GPIO47) - union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to GPIO63) - Uint16 rsvd7[4]; // Reserved - union GPBCSEL1_REG GPBCSEL1; // GPIO B Master Core Select (GPIO32 to GPIO39) - union GPBCSEL2_REG GPBCSEL2; // GPIO B Master Core Select (GPIO40 to GPIO47) - union GPBCSEL3_REG GPBCSEL3; // GPIO B Master Core Select (GPIO48 to GPIO55) - union GPBCSEL4_REG GPBCSEL4; // GPIO B Master Core Select (GPIO56 to GPIO63) - Uint16 rsvd8[12]; // Reserved - union GPBLOCK_REG GPBLOCK; // GPIO B Lock Register (GPIO32 to GPIO63) - union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to GPIO63) - Uint16 rsvd9[320]; // Reserved - union GPHCTRL_REG GPHCTRL; // GPIO H Qualification Sampling Period (GPIO224 to GPIO255) - union GPHQSEL1_REG GPHQSEL1; // GPIO H Qualification Type (GPIO224 to GPIO239) - union GPHQSEL2_REG GPHQSEL2; // GPIO H Qualification Type (GPIO240 to GPIO255) - Uint16 rsvd10[10]; // Reserved - union GPHINV_REG GPHINV; // GPIO H Input Inversion (GPIO224 to GPIO255) - Uint16 rsvd11[2]; // Reserved - union GPHAMSEL_REG GPHAMSEL; // GPIO H Analog Mode Select (GPIO224 to GPIO255) - Uint16 rsvd12[38]; // Reserved - union GPHLOCK_REG GPHLOCK; // GPIO H Lock Register (GPIO224 to GPIO255) - union GPHCR_REG GPHCR; // GPIO H Lock Commit Register (GPIO224 to GPIO255) -}; - -struct GPADAT_BITS { // bits description - Uint16 GPIO0:1; // 0 Data Register for this pin - Uint16 GPIO1:1; // 1 Data Register for this pin - Uint16 GPIO2:1; // 2 Data Register for this pin - Uint16 GPIO3:1; // 3 Data Register for this pin - Uint16 GPIO4:1; // 4 Data Register for this pin - Uint16 GPIO5:1; // 5 Data Register for this pin - Uint16 GPIO6:1; // 6 Data Register for this pin - Uint16 GPIO7:1; // 7 Data Register for this pin - Uint16 GPIO8:1; // 8 Data Register for this pin - Uint16 GPIO9:1; // 9 Data Register for this pin - Uint16 GPIO10:1; // 10 Data Register for this pin - Uint16 GPIO11:1; // 11 Data Register for this pin - Uint16 GPIO12:1; // 12 Data Register for this pin - Uint16 GPIO13:1; // 13 Data Register for this pin - Uint16 GPIO14:1; // 14 Data Register for this pin - Uint16 GPIO15:1; // 15 Data Register for this pin - Uint16 GPIO16:1; // 16 Data Register for this pin - Uint16 GPIO17:1; // 17 Data Register for this pin - Uint16 GPIO18:1; // 18 Data Register for this pin - Uint16 GPIO19:1; // 19 Data Register for this pin - Uint16 GPIO20:1; // 20 Data Register for this pin - Uint16 GPIO21:1; // 21 Data Register for this pin - Uint16 GPIO22:1; // 22 Data Register for this pin - Uint16 GPIO23:1; // 23 Data Register for this pin - Uint16 GPIO24:1; // 24 Data Register for this pin - Uint16 GPIO25:1; // 25 Data Register for this pin - Uint16 GPIO26:1; // 26 Data Register for this pin - Uint16 GPIO27:1; // 27 Data Register for this pin - Uint16 GPIO28:1; // 28 Data Register for this pin - Uint16 GPIO29:1; // 29 Data Register for this pin - Uint16 GPIO30:1; // 30 Data Register for this pin - Uint16 GPIO31:1; // 31 Data Register for this pin -}; - -union GPADAT_REG { - Uint32 all; - struct GPADAT_BITS bit; -}; - -struct GPASET_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Set bit for this pin - Uint16 GPIO1:1; // 1 Output Set bit for this pin - Uint16 GPIO2:1; // 2 Output Set bit for this pin - Uint16 GPIO3:1; // 3 Output Set bit for this pin - Uint16 GPIO4:1; // 4 Output Set bit for this pin - Uint16 GPIO5:1; // 5 Output Set bit for this pin - Uint16 GPIO6:1; // 6 Output Set bit for this pin - Uint16 GPIO7:1; // 7 Output Set bit for this pin - Uint16 GPIO8:1; // 8 Output Set bit for this pin - Uint16 GPIO9:1; // 9 Output Set bit for this pin - Uint16 GPIO10:1; // 10 Output Set bit for this pin - Uint16 GPIO11:1; // 11 Output Set bit for this pin - Uint16 GPIO12:1; // 12 Output Set bit for this pin - Uint16 GPIO13:1; // 13 Output Set bit for this pin - Uint16 GPIO14:1; // 14 Output Set bit for this pin - Uint16 GPIO15:1; // 15 Output Set bit for this pin - Uint16 GPIO16:1; // 16 Output Set bit for this pin - Uint16 GPIO17:1; // 17 Output Set bit for this pin - Uint16 GPIO18:1; // 18 Output Set bit for this pin - Uint16 GPIO19:1; // 19 Output Set bit for this pin - Uint16 GPIO20:1; // 20 Output Set bit for this pin - Uint16 GPIO21:1; // 21 Output Set bit for this pin - Uint16 GPIO22:1; // 22 Output Set bit for this pin - Uint16 GPIO23:1; // 23 Output Set bit for this pin - Uint16 GPIO24:1; // 24 Output Set bit for this pin - Uint16 GPIO25:1; // 25 Output Set bit for this pin - Uint16 GPIO26:1; // 26 Output Set bit for this pin - Uint16 GPIO27:1; // 27 Output Set bit for this pin - Uint16 GPIO28:1; // 28 Output Set bit for this pin - Uint16 GPIO29:1; // 29 Output Set bit for this pin - Uint16 GPIO30:1; // 30 Output Set bit for this pin - Uint16 GPIO31:1; // 31 Output Set bit for this pin -}; - -union GPASET_REG { - Uint32 all; - struct GPASET_BITS bit; -}; - -struct GPACLEAR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Clear bit for this pin - Uint16 GPIO1:1; // 1 Output Clear bit for this pin - Uint16 GPIO2:1; // 2 Output Clear bit for this pin - Uint16 GPIO3:1; // 3 Output Clear bit for this pin - Uint16 GPIO4:1; // 4 Output Clear bit for this pin - Uint16 GPIO5:1; // 5 Output Clear bit for this pin - Uint16 GPIO6:1; // 6 Output Clear bit for this pin - Uint16 GPIO7:1; // 7 Output Clear bit for this pin - Uint16 GPIO8:1; // 8 Output Clear bit for this pin - Uint16 GPIO9:1; // 9 Output Clear bit for this pin - Uint16 GPIO10:1; // 10 Output Clear bit for this pin - Uint16 GPIO11:1; // 11 Output Clear bit for this pin - Uint16 GPIO12:1; // 12 Output Clear bit for this pin - Uint16 GPIO13:1; // 13 Output Clear bit for this pin - Uint16 GPIO14:1; // 14 Output Clear bit for this pin - Uint16 GPIO15:1; // 15 Output Clear bit for this pin - Uint16 GPIO16:1; // 16 Output Clear bit for this pin - Uint16 GPIO17:1; // 17 Output Clear bit for this pin - Uint16 GPIO18:1; // 18 Output Clear bit for this pin - Uint16 GPIO19:1; // 19 Output Clear bit for this pin - Uint16 GPIO20:1; // 20 Output Clear bit for this pin - Uint16 GPIO21:1; // 21 Output Clear bit for this pin - Uint16 GPIO22:1; // 22 Output Clear bit for this pin - Uint16 GPIO23:1; // 23 Output Clear bit for this pin - Uint16 GPIO24:1; // 24 Output Clear bit for this pin - Uint16 GPIO25:1; // 25 Output Clear bit for this pin - Uint16 GPIO26:1; // 26 Output Clear bit for this pin - Uint16 GPIO27:1; // 27 Output Clear bit for this pin - Uint16 GPIO28:1; // 28 Output Clear bit for this pin - Uint16 GPIO29:1; // 29 Output Clear bit for this pin - Uint16 GPIO30:1; // 30 Output Clear bit for this pin - Uint16 GPIO31:1; // 31 Output Clear bit for this pin -}; - -union GPACLEAR_REG { - Uint32 all; - struct GPACLEAR_BITS bit; -}; - -struct GPATOGGLE_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Toggle bit for this pin - Uint16 GPIO1:1; // 1 Output Toggle bit for this pin - Uint16 GPIO2:1; // 2 Output Toggle bit for this pin - Uint16 GPIO3:1; // 3 Output Toggle bit for this pin - Uint16 GPIO4:1; // 4 Output Toggle bit for this pin - Uint16 GPIO5:1; // 5 Output Toggle bit for this pin - Uint16 GPIO6:1; // 6 Output Toggle bit for this pin - Uint16 GPIO7:1; // 7 Output Toggle bit for this pin - Uint16 GPIO8:1; // 8 Output Toggle bit for this pin - Uint16 GPIO9:1; // 9 Output Toggle bit for this pin - Uint16 GPIO10:1; // 10 Output Toggle bit for this pin - Uint16 GPIO11:1; // 11 Output Toggle bit for this pin - Uint16 GPIO12:1; // 12 Output Toggle bit for this pin - Uint16 GPIO13:1; // 13 Output Toggle bit for this pin - Uint16 GPIO14:1; // 14 Output Toggle bit for this pin - Uint16 GPIO15:1; // 15 Output Toggle bit for this pin - Uint16 GPIO16:1; // 16 Output Toggle bit for this pin - Uint16 GPIO17:1; // 17 Output Toggle bit for this pin - Uint16 GPIO18:1; // 18 Output Toggle bit for this pin - Uint16 GPIO19:1; // 19 Output Toggle bit for this pin - Uint16 GPIO20:1; // 20 Output Toggle bit for this pin - Uint16 GPIO21:1; // 21 Output Toggle bit for this pin - Uint16 GPIO22:1; // 22 Output Toggle bit for this pin - Uint16 GPIO23:1; // 23 Output Toggle bit for this pin - Uint16 GPIO24:1; // 24 Output Toggle bit for this pin - Uint16 GPIO25:1; // 25 Output Toggle bit for this pin - Uint16 GPIO26:1; // 26 Output Toggle bit for this pin - Uint16 GPIO27:1; // 27 Output Toggle bit for this pin - Uint16 GPIO28:1; // 28 Output Toggle bit for this pin - Uint16 GPIO29:1; // 29 Output Toggle bit for this pin - Uint16 GPIO30:1; // 30 Output Toggle bit for this pin - Uint16 GPIO31:1; // 31 Output Toggle bit for this pin -}; - -union GPATOGGLE_REG { - Uint32 all; - struct GPATOGGLE_BITS bit; -}; - -struct GPBDAT_BITS { // bits description - Uint16 GPIO32:1; // 0 Data Register for this pin - Uint16 GPIO33:1; // 1 Data Register for this pin - Uint16 GPIO34:1; // 2 Data Register for this pin - Uint16 GPIO35:1; // 3 Data Register for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Data Register for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Data Register for this pin - Uint16 GPIO40:1; // 8 Data Register for this pin - Uint16 GPIO41:1; // 9 Data Register for this pin - Uint16 GPIO42:1; // 10 Data Register for this pin - Uint16 GPIO43:1; // 11 Data Register for this pin - Uint16 GPIO44:1; // 12 Data Register for this pin - Uint16 GPIO45:1; // 13 Data Register for this pin - Uint16 GPIO46:1; // 14 Data Register for this pin - Uint16 GPIO47:1; // 15 Data Register for this pin - Uint16 GPIO48:1; // 16 Data Register for this pin - Uint16 GPIO49:1; // 17 Data Register for this pin - Uint16 GPIO50:1; // 18 Data Register for this pin - Uint16 GPIO51:1; // 19 Data Register for this pin - Uint16 GPIO52:1; // 20 Data Register for this pin - Uint16 GPIO53:1; // 21 Data Register for this pin - Uint16 GPIO54:1; // 22 Data Register for this pin - Uint16 GPIO55:1; // 23 Data Register for this pin - Uint16 GPIO56:1; // 24 Data Register for this pin - Uint16 GPIO57:1; // 25 Data Register for this pin - Uint16 GPIO58:1; // 26 Data Register for this pin - Uint16 GPIO59:1; // 27 Data Register for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBDAT_REG { - Uint32 all; - struct GPBDAT_BITS bit; -}; - -struct GPBSET_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Set bit for this pin - Uint16 GPIO33:1; // 1 Output Set bit for this pin - Uint16 GPIO34:1; // 2 Output Set bit for this pin - Uint16 GPIO35:1; // 3 Output Set bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Set bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Set bit for this pin - Uint16 GPIO40:1; // 8 Output Set bit for this pin - Uint16 GPIO41:1; // 9 Output Set bit for this pin - Uint16 GPIO42:1; // 10 Output Set bit for this pin - Uint16 GPIO43:1; // 11 Output Set bit for this pin - Uint16 GPIO44:1; // 12 Output Set bit for this pin - Uint16 GPIO45:1; // 13 Output Set bit for this pin - Uint16 GPIO46:1; // 14 Output Set bit for this pin - Uint16 GPIO47:1; // 15 Output Set bit for this pin - Uint16 GPIO48:1; // 16 Output Set bit for this pin - Uint16 GPIO49:1; // 17 Output Set bit for this pin - Uint16 GPIO50:1; // 18 Output Set bit for this pin - Uint16 GPIO51:1; // 19 Output Set bit for this pin - Uint16 GPIO52:1; // 20 Output Set bit for this pin - Uint16 GPIO53:1; // 21 Output Set bit for this pin - Uint16 GPIO54:1; // 22 Output Set bit for this pin - Uint16 GPIO55:1; // 23 Output Set bit for this pin - Uint16 GPIO56:1; // 24 Output Set bit for this pin - Uint16 GPIO57:1; // 25 Output Set bit for this pin - Uint16 GPIO58:1; // 26 Output Set bit for this pin - Uint16 GPIO59:1; // 27 Output Set bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBSET_REG { - Uint32 all; - struct GPBSET_BITS bit; -}; - -struct GPBCLEAR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Clear bit for this pin - Uint16 GPIO33:1; // 1 Output Clear bit for this pin - Uint16 GPIO34:1; // 2 Output Clear bit for this pin - Uint16 GPIO35:1; // 3 Output Clear bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Clear bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Clear bit for this pin - Uint16 GPIO40:1; // 8 Output Clear bit for this pin - Uint16 GPIO41:1; // 9 Output Clear bit for this pin - Uint16 GPIO42:1; // 10 Output Clear bit for this pin - Uint16 GPIO43:1; // 11 Output Clear bit for this pin - Uint16 GPIO44:1; // 12 Output Clear bit for this pin - Uint16 GPIO45:1; // 13 Output Clear bit for this pin - Uint16 GPIO46:1; // 14 Output Clear bit for this pin - Uint16 GPIO47:1; // 15 Output Clear bit for this pin - Uint16 GPIO48:1; // 16 Output Clear bit for this pin - Uint16 GPIO49:1; // 17 Output Clear bit for this pin - Uint16 GPIO50:1; // 18 Output Clear bit for this pin - Uint16 GPIO51:1; // 19 Output Clear bit for this pin - Uint16 GPIO52:1; // 20 Output Clear bit for this pin - Uint16 GPIO53:1; // 21 Output Clear bit for this pin - Uint16 GPIO54:1; // 22 Output Clear bit for this pin - Uint16 GPIO55:1; // 23 Output Clear bit for this pin - Uint16 GPIO56:1; // 24 Output Clear bit for this pin - Uint16 GPIO57:1; // 25 Output Clear bit for this pin - Uint16 GPIO58:1; // 26 Output Clear bit for this pin - Uint16 GPIO59:1; // 27 Output Clear bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBCLEAR_REG { - Uint32 all; - struct GPBCLEAR_BITS bit; -}; - -struct GPBTOGGLE_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Toggle bit for this pin - Uint16 GPIO33:1; // 1 Output Toggle bit for this pin - Uint16 GPIO34:1; // 2 Output Toggle bit for this pin - Uint16 GPIO35:1; // 3 Output Toggle bit for this pin - Uint16 rsvd1:1; // 4 Reserved - Uint16 GPIO37:1; // 5 Output Toggle bit for this pin - Uint16 rsvd2:1; // 6 Reserved - Uint16 GPIO39:1; // 7 Output Toggle bit for this pin - Uint16 GPIO40:1; // 8 Output Toggle bit for this pin - Uint16 GPIO41:1; // 9 Output Toggle bit for this pin - Uint16 GPIO42:1; // 10 Output Toggle bit for this pin - Uint16 GPIO43:1; // 11 Output Toggle bit for this pin - Uint16 GPIO44:1; // 12 Output Toggle bit for this pin - Uint16 GPIO45:1; // 13 Output Toggle bit for this pin - Uint16 GPIO46:1; // 14 Output Toggle bit for this pin - Uint16 GPIO47:1; // 15 Output Toggle bit for this pin - Uint16 GPIO48:1; // 16 Output Toggle bit for this pin - Uint16 GPIO49:1; // 17 Output Toggle bit for this pin - Uint16 GPIO50:1; // 18 Output Toggle bit for this pin - Uint16 GPIO51:1; // 19 Output Toggle bit for this pin - Uint16 GPIO52:1; // 20 Output Toggle bit for this pin - Uint16 GPIO53:1; // 21 Output Toggle bit for this pin - Uint16 GPIO54:1; // 22 Output Toggle bit for this pin - Uint16 GPIO55:1; // 23 Output Toggle bit for this pin - Uint16 GPIO56:1; // 24 Output Toggle bit for this pin - Uint16 GPIO57:1; // 25 Output Toggle bit for this pin - Uint16 GPIO58:1; // 26 Output Toggle bit for this pin - Uint16 GPIO59:1; // 27 Output Toggle bit for this pin - Uint16 rsvd3:1; // 28 Reserved - Uint16 rsvd4:1; // 29 Reserved - Uint16 rsvd5:1; // 30 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union GPBTOGGLE_REG { - Uint32 all; - struct GPBTOGGLE_BITS bit; -}; - -struct GPHDAT_BITS { // bits description - Uint16 GPIO224:1; // 0 Data Register for this pin - Uint16 GPIO225:1; // 1 Data Register for this pin - Uint16 GPIO226:1; // 2 Data Register for this pin - Uint16 GPIO227:1; // 3 Data Register for this pin - Uint16 GPIO228:1; // 4 Data Register for this pin - Uint16 GPIO229:1; // 5 Data Register for this pin - Uint16 GPIO230:1; // 6 Data Register for this pin - Uint16 GPIO231:1; // 7 Data Register for this pin - Uint16 GPIO232:1; // 8 Data Register for this pin - Uint16 GPIO233:1; // 9 Data Register for this pin - Uint16 GPIO234:1; // 10 Data Register for this pin - Uint16 GPIO235:1; // 11 Data Register for this pin - Uint16 GPIO236:1; // 12 Data Register for this pin - Uint16 GPIO237:1; // 13 Data Register for this pin - Uint16 GPIO238:1; // 14 Data Register for this pin - Uint16 GPIO239:1; // 15 Data Register for this pin - Uint16 GPIO240:1; // 16 Data Register for this pin - Uint16 GPIO241:1; // 17 Data Register for this pin - Uint16 GPIO242:1; // 18 Data Register for this pin - Uint16 GPIO243:1; // 19 Data Register for this pin - Uint16 GPIO244:1; // 20 Data Register for this pin - Uint16 GPIO245:1; // 21 Data Register for this pin - Uint16 GPIO246:1; // 22 Data Register for this pin - Uint16 GPIO247:1; // 23 Data Register for this pin - Uint16 rsvd1:1; // 24 Reserved - Uint16 rsvd2:1; // 25 Reserved - Uint16 rsvd3:1; // 26 Reserved - Uint16 rsvd4:1; // 27 Reserved - Uint16 rsvd5:1; // 28 Reserved - Uint16 rsvd6:1; // 29 Reserved - Uint16 rsvd7:1; // 30 Reserved - Uint16 rsvd8:1; // 31 Reserved -}; - -union GPHDAT_REG { - Uint32 all; - struct GPHDAT_BITS bit; -}; - -struct GPIO_DATA_REGS { - union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to GPIO31) - union GPASET_REG GPASET; // GPIO A Output Set (GPIO0 to GPIO31) - union GPACLEAR_REG GPACLEAR; // GPIO A Output Clear (GPIO0 to GPIO31) - union GPATOGGLE_REG GPATOGGLE; // GPIO A Output Toggle (GPIO0 to GPIO31) - union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to GPIO64) - union GPBSET_REG GPBSET; // GPIO B Output Set (GPIO32 to GPIO64) - union GPBCLEAR_REG GPBCLEAR; // GPIO B Output Clear (GPIO32 to GPIO64) - union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Output Toggle (GPIO32 to GPIO64) - Uint16 rsvd1[40]; // Reserved - union GPHDAT_REG GPHDAT; // GPIO H Data Register (GPIO0 to GPIO255) - Uint16 rsvd2[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// GPIO External References & Function Declarations: -// -extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; -extern volatile struct GPIO_DATA_REGS GpioDataRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h deleted file mode 100644 index ee13416..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_i2c.h +++ /dev/null @@ -1,251 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_i2c.h -// -// TITLE: I2C Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_I2C_H__ -#define __F28004X_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// I2C Individual Register Bit Definitions: - -struct I2COAR_BITS { // bits description - Uint16 OAR:10; // 9:0 I2C Own address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2COAR_REG { - Uint16 all; - struct I2COAR_BITS bit; -}; - -struct I2CIER_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable - Uint16 NACK:1; // 1 No-acknowledgment interrupt enable - Uint16 ARDY:1; // 2 Register-access-ready interrupt enable - Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable - Uint16 SCD:1; // 5 Stop condition detected interrupt enable - Uint16 AAS:1; // 6 Addressed as slave interrupt enable - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union I2CIER_REG { - Uint16 all; - struct I2CIER_BITS bit; -}; - -struct I2CSTR_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit - Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. - Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit - Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. - Uint16 SCD:1; // 5 Stop condition detected bit. - Uint16 BYTESENT:1; // 6 Byte transmit over indication - Uint16 rsvd1:1; // 7 Reserved - Uint16 AD0:1; // 8 Address 0 bits - Uint16 AAS:1; // 9 Addressed-as-slave bit - Uint16 XSMT:1; // 10 Transmit shift register empty bit. - Uint16 RSFULL:1; // 11 Receive shift register full bit. - Uint16 BB:1; // 12 Bus busy bit. - Uint16 NACKSNT:1; // 13 NACK sent bit. - Uint16 SDIR:1; // 14 Slave direction bit - Uint16 rsvd2:1; // 15 Reserved -}; - -union I2CSTR_REG { - Uint16 all; - struct I2CSTR_BITS bit; -}; - -struct I2CDRR_BITS { // bits description - Uint16 DATA:8; // 7:0 Receive data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDRR_REG { - Uint16 all; - struct I2CDRR_BITS bit; -}; - -struct I2CSAR_BITS { // bits description - Uint16 SAR:10; // 9:0 Slave Address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2CSAR_REG { - Uint16 all; - struct I2CSAR_BITS bit; -}; - -struct I2CDXR_BITS { // bits description - Uint16 DATA:8; // 7:0 Transmit data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDXR_REG { - Uint16 all; - struct I2CDXR_BITS bit; -}; - -struct I2CMDR_BITS { // bits description - Uint16 BC:3; // 2:0 Bit count bits. - Uint16 FDF:1; // 3 Free Data Format - Uint16 STB:1; // 4 START Byte Mode - Uint16 IRS:1; // 5 I2C Module Reset - Uint16 DLB:1; // 6 Digital Loopback Mode - Uint16 RM:1; // 7 Repeat Mode - Uint16 XA:1; // 8 Expanded Address Mode - Uint16 TRX:1; // 9 Transmitter Mode - Uint16 MST:1; // 10 Master Mode - Uint16 STP:1; // 11 STOP Condition - Uint16 rsvd1:1; // 12 Reserved - Uint16 STT:1; // 13 START condition bit - Uint16 FREE:1; // 14 Debug Action - Uint16 NACKMOD:1; // 15 NACK mode bit -}; - -union I2CMDR_REG { - Uint16 all; - struct I2CMDR_BITS bit; -}; - -struct I2CISRC_BITS { // bits description - Uint16 INTCODE:3; // 2:0 Interrupt code bits. - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 WRITE_ZEROS:4; // 11:8 Always write all 0s to this field - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union I2CISRC_REG { - Uint16 all; - struct I2CISRC_BITS bit; -}; - -struct I2CEMDR_BITS { // bits description - Uint16 BC:1; // 0 Backwards compatibility mode - Uint16 FCM:1; // 1 Forward Compatibility for Tx behav in Type1 - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union I2CEMDR_REG { - Uint16 all; - struct I2CEMDR_BITS bit; -}; - -struct I2CPSC_BITS { // bits description - Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CPSC_REG { - Uint16 all; - struct I2CPSC_BITS bit; -}; - -struct I2CFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear - Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFFRST:1; // 13 Transmit FIFO Reset - Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable - Uint16 rsvd1:1; // 15 Reserved -}; - -union I2CFFTX_REG { - Uint16 all; - struct I2CFFTX_BITS bit; -}; - -struct I2CFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear - Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFFRST:1; // 13 Receive FIFO Reset - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union I2CFFRX_REG { - Uint16 all; - struct I2CFFRX_BITS bit; -}; - -struct I2C_REGS { - union I2COAR_REG I2COAR; // I2C Own address - union I2CIER_REG I2CIER; // I2C Interrupt Enable - union I2CSTR_REG I2CSTR; // I2C Status - Uint16 I2CCLKL; // I2C Clock low-time divider - Uint16 I2CCLKH; // I2C Clock high-time divider - Uint16 I2CCNT; // I2C Data count - union I2CDRR_REG I2CDRR; // I2C Data receive - union I2CSAR_REG I2CSAR; // I2C Slave address - union I2CDXR_REG I2CDXR; // I2C Data Transmit - union I2CMDR_REG I2CMDR; // I2C Mode - union I2CISRC_REG I2CISRC; // I2C Interrupt Source - union I2CEMDR_REG I2CEMDR; // I2C Extended Mode - union I2CPSC_REG I2CPSC; // I2C Prescaler - Uint16 rsvd1[19]; // Reserved - union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit - union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive -}; - -//--------------------------------------------------------------------------- -// I2C External References & Function Declarations: -// -extern volatile struct I2C_REGS I2caRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h deleted file mode 100644 index 856c66a..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_input_xbar.h +++ /dev/null @@ -1,112 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_input_xbar.h -// -// TITLE: INPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_INPUT_XBAR_H__ -#define __F28004X_INPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// INPUT_XBAR Individual Register Bit Definitions: - -struct INPUTSELECTLOCK_BITS { // bits description - Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register - Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register - Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register - Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register - Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register - Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register - Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register - Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register - Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register - Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register - Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register - Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register - Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register - Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register - Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register - Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union INPUTSELECTLOCK_REG { - Uint32 all; - struct INPUTSELECTLOCK_BITS bit; -}; - -struct INPUT_XBAR_REGS { - Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) - Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) - Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) - Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) - Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) - Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) - Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) - Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) - Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) - Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) - Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) - Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) - Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) - Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) - Uint16 INPUT15SELECT; // INPUT15 Input Select Register (GPIO0 to x) - Uint16 INPUT16SELECT; // INPUT16 Input Select Register (GPIO0 to x) - Uint16 rsvd1[14]; // Reserved - union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register -}; - -//--------------------------------------------------------------------------- -// INPUT_XBAR External References & Function Declarations: -// -extern volatile struct INPUT_XBAR_REGS InputXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h deleted file mode 100644 index 88e1971..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_lin.h +++ /dev/null @@ -1,576 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_lin.h -// -// TITLE: LIN Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_LIN_H__ -#define __F28004X_LIN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// LIN Individual Register Bit Definitions: - -struct SCIGCR0_BITS { // bits description - bp_16 RESET:1; // 0 LIN Module reset bit - bp_16 rsvd1:15; // 15:1 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIGCR0_REG { - bp_32 all; - struct SCIGCR0_BITS bit; -}; - -struct SCIGCR1_BITS { // bits description - bp_16 COMMMODE:1; // 0 SCI/LIN communications mode bit - bp_16 TIMINGMODE:1; // 1 SCI timing mode bit. Should be set to 1 for SCI mode. - bp_16 PARITYENA:1; // 2 Parity enable - bp_16 PARITY:1; // 3 SCI parity odd/even selection - bp_16 STOP:1; // 4 SCI number of stop bits - bp_16 CLK_MASTER:1; // 5 LIN Master/Slave selection and SCI clock enable - bp_16 LINMODE:1; // 6 LIN Mode enable/disable - bp_16 SWnRST:1; // 7 Software reset - bp_16 SLEEP:1; // 8 SCI sleep (SCI compatibility mode) - bp_16 ADAPT:1; // 9 Automatic baudrate adjustment control(LIN mode) - bp_16 MBUFMODE:1; // 10 Multi-buffer mode - bp_16 CTYPE:1; // 11 Checksum type (LIN mode) - bp_16 HGENCTRL:1; // 12 Mask filtering comparison control (LIN mode) - bp_16 STOPEXTFRAME:1; // 13 Stop extended frame communication (LIN mode) - bp_16 rsvd1:2; // 15:14 Reserved - bp_32 LOOPBACK:1; // 16 Digital loopback mode - bp_32 CONT:1; // 17 Continue on suspend - bp_32 rsvd2:6; // 23:18 Reserved - bp_32 RXENA:1; // 24 SCI mode receiver enable - bp_32 TXENA:1; // 25 SCI mode transmitter enable - bp_32 rsvd3:6; // 31:26 Reserved -}; - -union SCIGCR1_REG { - bp_32 all; - struct SCIGCR1_BITS bit; -}; - -struct SCIGCR2_BITS { // bits description - bp_16 POWERDOWN:1; // 0 Low-power mode PowerDown bit - bp_16 rsvd1:7; // 7:1 Reserved - bp_16 GENWU:1; // 8 Generate Wakeup - bp_16 rsvd2:7; // 15:9 Reserved - bp_32 SC:1; // 16 Send Checksum (LIN mode) - bp_32 CC:1; // 17 Compare Checksum (LIN mode) - bp_32 rsvd3:14; // 31:18 Reserved -}; - -union SCIGCR2_REG { - bp_32 all; - struct SCIGCR2_BITS bit; -}; - -struct SCISETINT_BITS { // bits description - bp_16 SETBRKDTINT:1; // 0 Set Break-detect Interrupt (SCI compatible mode) - bp_16 SETWAKEUPINT:1; // 1 Set Wake-up Interrupt - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 SETTIMEOUTINT:1; // 4 Set Timeout Interrupt (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 SETTOAWUSINT:1; // 6 Set Timeout After Wakeup Signal Interrupt (LIN only) - bp_16 SETTOA3WUSINT:1; // 7 Set Timeout After 3 Wakeup Signals Interrupt (LIN only) - bp_16 SETTXINT:1; // 8 Set Transmitter Interrupt - bp_16 SETRXINT:1; // 9 Receiver Interrupt Enable - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 SETIDINT:1; // 13 Set Identifier Interrupt (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 SETPEINT:1; // 24 Set Parity Interrupt - bp_32 SETOEINT:1; // 25 Set Overrun-Error Interrupt - bp_32 SETFEINT:1; // 26 Set Framing-Error Interrupt - bp_32 SETNREINT:1; // 27 Set No-Response-Error Interrupt (LIN only) - bp_32 SETISFEINT:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt (LIN only) - bp_32 SETCEINT:1; // 29 Set Checksum-error Interrupt (LIN only) - bp_32 SETPBEINT:1; // 30 Set Physical Bus Error Interrupt (LIN only) - bp_32 SETBEINT:1; // 31 Set Bit Error Interrupt (LIN only) -}; - -union SCISETINT_REG { - bp_32 all; - struct SCISETINT_BITS bit; -}; - -struct SCICLEARINT_BITS { // bits description - bp_16 CLRBRKDTINT:1; // 0 Clear Break-detect Interrupt (SCI compatible mode - bp_16 CLRWAKEUPINT:1; // 1 Clear Wake-up Interrupt - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 CLRTIMEOUTINT:1; // 4 Clear Timeout Interrupt (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 CLRTOAWUSINT:1; // 6 Clear Timeout After Wakeup Signal Interrupt (LIN only) - bp_16 CLRTOA3WUSINT:1; // 7 Clear Timeout After 3 Wakeup Signals Interrupt (LIN only) - bp_16 CLRTXINT:1; // 8 Clear Transmitter Interrupt - bp_16 CLRRXINT:1; // 9 Clear Receiver Interrupt - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 CLRIDINT:1; // 13 Clear Identifier Interrupt (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 CLRPEINT:1; // 24 Clear Parity Interrupt - bp_32 CLROEINT:1; // 25 Clear Overrun-Error Interrupt - bp_32 CLRFEINT:1; // 26 Clear Framing-Error Interrupt - bp_32 CLRNREINT:1; // 27 Clear No-Response-Error Interrupt (LIN only) - bp_32 CLRISFEINT:1; // 28 Clear Inconsistent-Synch-Field-Error Interrupt (LIN only) - bp_32 CLRCEINT:1; // 29 Clear Checksum-error Interrupt (LIN only) - bp_32 CLRPBEINT:1; // 30 Clear Physical Bus Error Interrupt (LIN only) - bp_32 CLRBEINT:1; // 31 Clear Bit Error Interrupt (LIN only) -}; - -union SCICLEARINT_REG { - bp_32 all; - struct SCICLEARINT_BITS bit; -}; - -struct SCISETINTLVL_BITS { // bits description - bp_16 SETBRKDTINTLVL:1; // 0 Set Break-detect Interrupt Level (SCI compatible mode) - bp_16 SETWAKEUPINTLVL:1; // 1 Set Wake-up Interrupt Level - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 SETTIMEOUTINTLVL:1; // 4 Set Timeout Interrupt Level (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 SETTOAWUSINTLVL:1; // 6 Set Timeout After Wakeup Signal Interrupt Level (LIN only) - bp_16 SETTOA3WUSINTLVL:1; // 7 Set Timeout After 3 Wakeup Signals - bp_16 SETTXINTLVL:1; // 8 Set Transmitter Interrupt Level - bp_16 SETRXINTOVO:1; // 9 Receiver Interrupt Enable Level - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 SETIDINTLVL:1; // 13 Set Identifier Interrupt Level (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 SETPEINTLVL:1; // 24 Set Parity Interrupt Level - bp_32 SETOEINTLVL:1; // 25 Set Overrun-Error Interrupt Level - bp_32 SETFEINTLVL:1; // 26 Set Framing-Error Interrupt Level - bp_32 SETNREINTLVL:1; // 27 Set No-Response-Error Interrupt Level (LIN only) - bp_32 SETISFEINTLVL:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt Level - bp_32 SETCEINTLVL:1; // 29 Set Checksum-error Interrupt Level (LIN only) - bp_32 SETPBEINTLVL:1; // 30 Set Physical Bus Error Interrupt Level (LIN only) - bp_32 SETBEINTLVL:1; // 31 Set Bit Error Interrupt Level(LIN only) -}; - -union SCISETINTLVL_REG { - bp_32 all; - struct SCISETINTLVL_BITS bit; -}; - -struct SCICLEARINTLVL_BITS { // bits description - bp_16 CLRBRKDTINTLVL:1; // 0 Clear Break-detect Interrupt Level (SCI compatible mode) - bp_16 CLRWAKEUPINTLVL:1; // 1 Clear Wake-up Interrupt Level - bp_16 rsvd1:2; // 3:2 Reserved - bp_16 CLRTIMEOUTINTLVL:1; // 4 Clear Timeout Interrupt Level (LIN only) - bp_16 rsvd2:1; // 5 Reserved - bp_16 CLRTOAWUSINTLVL:1; // 6 Clear Timeout After Wakeup Signal Interrupt Level (LIN only) - bp_16 CLRTOA3WUSINTLVL:1; // 7 Clear Timeout After 3 Wakeup Signals - bp_16 CLRTXINTLVL:1; // 8 Clear Transmitter Interrupt Level - bp_16 CLRRXINTLVL:1; // 9 Clear Receiver interrupt Level. - bp_16 rsvd3:3; // 12:10 Reserved - bp_16 CLRIDINTLVL:1; // 13 Clear Identifier Interrupt Level (LIN only) - bp_16 rsvd4:2; // 15:14 Reserved - bp_32 rsvd5:2; // 17:16 Reserved - bp_32 rsvd6:1; // 18 Reserved - bp_32 rsvd7:5; // 23:19 Reserved - bp_32 CLRPEINTLVL:1; // 24 Clear Parity Interrupt Level - bp_32 CLROEINTLVL:1; // 25 Clear Overrun-Error Interrupt Level - bp_32 CLRFEINTLVL:1; // 26 Clear Framing-Error Interrupt Level - bp_32 CLRNREINTLVL:1; // 27 Clear No-Response-Error Interrupt Level (LIN only) - bp_32 CLRISFEINTLVL:1; // 28 Clear Inconsistent-Synch-Field-Error - bp_32 CLRCEINTLVL:1; // 29 Clear Checksum-error Interrupt Level (LIN only) - bp_32 CLRPBEINTLVL:1; // 30 Clear Physical Bus Error Interrupt Level (LIN only) - bp_32 CLRBEINTLVL:1; // 31 Clear Bit Error Interrupt Level (LIN only) -}; - -union SCICLEARINTLVL_REG { - bp_32 all; - struct SCICLEARINTLVL_BITS bit; -}; - -struct SCIFLR_BITS { // bits description - bp_16 BRKDT:1; // 0 Break-detect Flag (SCI compatible mode) - bp_16 WAKEUP:1; // 1 Wake-up Flag - bp_16 IDLE:1; // 2 SCI receiver in idle state (SCI compatible mode) - bp_16 BUSY:1; // 3 Busy Flag - bp_16 TIMEOUT:1; // 4 LIN Bus IDLE timeout Flag (LIN only) - bp_16 rsvd1:1; // 5 Reserved - bp_16 TOAWUS:1; // 6 Timeout After Wakeup Signal Flag (LIN only) - bp_16 TOA3WUS:1; // 7 Timeout After 3 Wakeup Signals Flag (LIN only) - bp_16 TXRDY:1; // 8 Transmitter Buffer Ready Flag - bp_16 RXRDY:1; // 9 Receiver Buffer Ready Flag - bp_16 TXWAKE:1; // 10 SCI Transmitter Wakeup Method Select - bp_16 TXEMPTY:1; // 11 Transmitter Empty Clag - bp_16 RXWAKE:1; // 12 Receiver Wakeup Detect Flag - bp_16 IDTXFLAG:1; // 13 Identifier On Transmit Flag (LIN only) - bp_16 IDRXFLAG:1; // 14 Identifier on Receive Flag - bp_16 rsvd2:1; // 15 Reserved - bp_32 rsvd3:8; // 23:16 Reserved - bp_32 PE:1; // 24 Parity Error Flag - bp_32 OE:1; // 25 Overrun Error Flag - bp_32 FE:1; // 26 Framing Error Flag - bp_32 NRE:1; // 27 No-Response Error Flag (LIN only) - bp_32 ISFE:1; // 28 Inconsistent Synch Field Error Flag (LIN only) - bp_32 CE:1; // 29 Checksum Error Flag (LIN only) - bp_32 PBE:1; // 30 Physical Bus Error Flag (LIN only) - bp_32 BE:1; // 31 Bit Error Flag (LIN only) -}; - -union SCIFLR_REG { - bp_32 all; - struct SCIFLR_BITS bit; -}; - -struct SCIINTVECT0_BITS { // bits description - bp_16 INTVECT0:5; // 4:0 LIN Module reset bit - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIINTVECT0_REG { - bp_32 all; - struct SCIINTVECT0_BITS bit; -}; - -struct SCIINTVECT1_BITS { // bits description - bp_16 INTVECT1:5; // 4:0 LIN Module reset bit - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIINTVECT1_REG { - bp_32 all; - struct SCIINTVECT1_BITS bit; -}; - -struct SCIFORMAT_BITS { // bits description - bp_16 CHAR:5; // 4:0 Character Length Control Bits - bp_16 rsvd1:11; // 15:5 Reserved - bp_32 LENGTH:3; // 18:16 Frame Length Control Bits - bp_32 rsvd2:13; // 31:19 Reserved -}; - -union SCIFORMAT_REG { - bp_32 all; - struct SCIFORMAT_BITS bit; -}; - -struct BRSR_BITS { // bits description - bp_16 SCI_LIN_PSL:16; // 15:0 Character Length Control Bits - bp_32 SCI_LIN_PSH:8; // 23:16 24-Bit Integer Prescaler Select - bp_32 M:4; // 27:24 Frame Length Control Bits - bp_32 rsvd1:4; // 31:28 Reserved -}; - -union BRSR_REG { - bp_32 all; - struct BRSR_BITS bit; -}; - -struct SCIED_BITS { // bits description - bp_16 ED:8; // 7:0 Receiver Emulation Data. - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIED_REG { - bp_32 all; - struct SCIED_BITS bit; -}; - -struct SCIRD_BITS { // bits description - bp_16 RD:8; // 7:0 Received Data. - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCIRD_REG { - bp_32 all; - struct SCIRD_BITS bit; -}; - -struct SCITD_BITS { // bits description - bp_16 TD:8; // 7:0 Transmit data - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union SCITD_REG { - bp_32 all; - struct SCITD_BITS bit; -}; - -struct SCIPIO0_BITS { // bits description - bp_16 rsvd1:1; // 0 Reserved - bp_16 RXFUNC:1; // 1 LINRX pin function - bp_16 TXFUNC:1; // 2 LINTX pin function - bp_16 rsvd2:13; // 15:3 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union SCIPIO0_REG { - bp_32 all; - struct SCIPIO0_BITS bit; -}; - -struct SCIPIO2_BITS { // bits description - bp_16 rsvd1:1; // 0 Reserved - bp_16 RXIN:1; // 1 SCIRX pin value - bp_16 TXIN:1; // 2 SCITX pin value - bp_16 rsvd2:13; // 15:3 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union SCIPIO2_REG { - bp_32 all; - struct SCIPIO2_BITS bit; -}; - -struct LINCOMP_BITS { // bits description - bp_16 SBREAK:3; // 2:0 Synch Break Extend - bp_16 rsvd1:5; // 7:3 Reserved - bp_16 SDEL:2; // 9:8 Sync Delimiter Compare - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union LINCOMP_REG { - bp_32 all; - struct LINCOMP_BITS bit; -}; - -struct LINRD0_BITS { // bits description - bp_16 RD3:8; // 7:0 Receive Buffer 3 - bp_16 RD2:8; // 15:8 Receive Buffer 2 - bp_32 RD1:8; // 23:16 Receive Buffer 1 - bp_32 RD0:8; // 31:24 Receive Buffer 0 -}; - -union LINRD0_REG { - bp_32 all; - struct LINRD0_BITS bit; -}; - -struct LINRD1_BITS { // bits description - bp_16 RD7:8; // 7:0 Receive Buffer 3 - bp_16 RD6:8; // 15:8 Receive Buffer 2 - bp_32 RD5:8; // 23:16 Receive Buffer 1 - bp_32 RD4:8; // 31:24 Receive Buffer 0 -}; - -union LINRD1_REG { - bp_32 all; - struct LINRD1_BITS bit; -}; - -struct LINMASK_BITS { // bits description - bp_16 TXIDMASK:8; // 7:0 TX ID Mask bits (LIN only) - bp_16 rsvd1:8; // 15:8 Reserved - bp_32 RXIDMASK:8; // 23:16 RX ID Mask bits (LIN only) - bp_32 rsvd2:8; // 31:24 Reserved -}; - -union LINMASK_REG { - bp_32 all; - struct LINMASK_BITS bit; -}; - -struct LINID_BITS { // bits description - bp_16 IDBYTE:8; // 7:0 LIN message ID (LIN only) - bp_16 IDSLAVETASKBYTE:8; // 15:8 Received ID comparison ID (LIN only) - bp_32 RECEIVEDID:8; // 23:16 Current Message ID (LIN only) - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union LINID_REG { - bp_32 all; - struct LINID_BITS bit; -}; - -struct LINTD0_BITS { // bits description - bp_16 TD3:8; // 7:0 TRANSMIT Buffer 3 - bp_16 TD2:8; // 15:8 TRANSMIT Buffer 2 - bp_32 TD1:8; // 23:16 TRANSMIT Buffer 1 - bp_32 TD0:8; // 31:24 TRANSMIT Buffer 0 -}; - -union LINTD0_REG { - bp_32 all; - struct LINTD0_BITS bit; -}; - -struct LINTD1_BITS { // bits description - bp_16 TD7:8; // 7:0 TRANSMIT Buffer 7 - bp_16 TD6:8; // 15:8 TRANSMIT Buffer 6 - bp_32 TD5:8; // 23:16 TRANSMIT Buffer 5 - bp_32 TD4:8; // 31:24 TRANSMIT Buffer 4 -}; - -union LINTD1_REG { - bp_32 all; - struct LINTD1_BITS bit; -}; - -struct MBRSR_BITS { // bits description - bp_16 MBR:13; // 12:0 Received Data. - bp_16 rsvd1:3; // 15:13 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union MBRSR_REG { - bp_32 all; - struct MBRSR_BITS bit; -}; - -struct IODFTCTRL_BITS { // bits description - bp_16 RXPENA:1; // 0 Analog Loopback Via Receive Pin Enable - bp_16 LPBENA:1; // 1 Module Loopback Enable - bp_16 rsvd1:6; // 7:2 Reserved - bp_16 IODFTENA:4; // 11:8 IO DFT Enable Key - bp_16 rsvd2:4; // 15:12 Reserved - bp_32 TXSHIFT:3; // 18:16 Transmit Delay Shift - bp_32 PINSAMPLEMASK:2; // 20:19 TX Pin Sample Mask - bp_32 rsvd3:3; // 23:21 Reserved - bp_32 BRKDTERRENA:1; // 24 Break Detect Error Enable (SCI compatibility mode) - bp_32 PERRENA:1; // 25 Parity Error Enable (SCI compatibility mode) - bp_32 FERRENA:1; // 26 Frame Error Enable (SCI compatibility mode) - bp_32 rsvd4:1; // 27 Reserved - bp_32 ISFERRENA:1; // 28 Inconsistent Synch Field Error Enable (LIN mode) - bp_32 CERRENA:1; // 29 Checksum Error Enable(LIN mode) - bp_32 PBERRENA:1; // 30 Physical Bus Error Enable (LIN mode) - bp_32 BERRENA:1; // 31 Bit Error Enable (LIN mode) -}; - -union IODFTCTRL_REG { - bp_32 all; - struct IODFTCTRL_BITS bit; -}; - -struct LIN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for LIN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_EN_REG { - bp_32 all; - struct LIN_GLB_INT_EN_BITS bit; -}; - -struct LIN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for LIN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_FLG_REG { - bp_32 all; - struct LIN_GLB_INT_FLG_BITS bit; -}; - -struct LIN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for LIN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for LIN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union LIN_GLB_INT_CLR_REG { - bp_32 all; - struct LIN_GLB_INT_CLR_BITS bit; -}; - -struct LIN_REGS { - union SCIGCR0_REG SCIGCR0; // Global Control Register 0 - union SCIGCR1_REG SCIGCR1; // Global Control Register 1 - union SCIGCR2_REG SCIGCR2; // Global Control Register 2 - union SCISETINT_REG SCISETINT; // Interrupt Enable Register - union SCICLEARINT_REG SCICLEARINT; // Interrupt Disable Register - union SCISETINTLVL_REG SCISETINTLVL; // Set Interrupt Level Register - union SCICLEARINTLVL_REG SCICLEARINTLVL; // Clear Interrupt Level Register - union SCIFLR_REG SCIFLR; // Flag Register - union SCIINTVECT0_REG SCIINTVECT0; // Interrupt Vector Offset Register 0 - union SCIINTVECT1_REG SCIINTVECT1; // Interrupt Vector Offset Register 1 - union SCIFORMAT_REG SCIFORMAT; // Length Control Register - union BRSR_REG BRSR; // Baud Rate Selection Register - union SCIED_REG SCIED; // Emulation buffer Register - union SCIRD_REG SCIRD; // Receiver data buffer Register - union SCITD_REG SCITD; // Transmit data buffer Register - union SCIPIO0_REG SCIPIO0; // Pin control Register 0 - uint32_t rsvd1[2]; // Reserved - union SCIPIO2_REG SCIPIO2; // Pin control Register 2 - uint32_t rsvd2[12]; // Reserved - union LINCOMP_REG LINCOMP; // Compare register - union LINRD0_REG LINRD0; // Receive data register 0 - union LINRD1_REG LINRD1; // Receive data register 1 - union LINMASK_REG LINMASK; // Acceptance mask register - union LINID_REG LINID; // LIN ID Register - union LINTD0_REG LINTD0; // Transmit Data Register 0 - union LINTD1_REG LINTD1; // Transmit Data Register 1 - union MBRSR_REG MBRSR; // Baud Rate Selection Register - uint32_t rsvd3[8]; // Reserved - union IODFTCTRL_REG IODFTCTRL; // IODFT for LIN - uint32_t rsvd4[38]; // Reserved - union LIN_GLB_INT_EN_REG LIN_GLB_INT_EN; // LIN Global Interrupt Enable Register - union LIN_GLB_INT_FLG_REG LIN_GLB_INT_FLG; // LIN Global Interrupt Flag Register - union LIN_GLB_INT_CLR_REG LIN_GLB_INT_CLR; // LIN Global Interrupt Clear Register -}; - -//--------------------------------------------------------------------------- -// LIN External References & Function Declarations: -// -extern volatile struct LIN_REGS LinaRegs; -extern volatile struct LIN_REGS LinbRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h deleted file mode 100644 index 7debf52..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_memconfig.h +++ /dev/null @@ -1,867 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_memconfig.h -// -// TITLE: MEMCONFIG Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_MEMCONFIG_H__ -#define __F28004X_MEMCONFIG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// MEMCONFIG Individual Register Bit Definitions: - -struct DxLOCK_BITS { // bits description - Uint16 LOCK_M0:1; // 0 M0 RAM Lock bits - Uint16 LOCK_M1:1; // 1 M1 RAM Lock bits - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxLOCK_REG { - Uint32 all; - struct DxLOCK_BITS bit; -}; - -struct DxCOMMIT_BITS { // bits description - Uint16 COMMIT_M0:1; // 0 M0 RAM Permanent Lock bits - Uint16 COMMIT_M1:1; // 1 M1 RAM Permanent Lock bits - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxCOMMIT_REG { - Uint32 all; - struct DxCOMMIT_BITS bit; -}; - -struct DxTEST_BITS { // bits description - Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM - Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxTEST_REG { - Uint32 all; - struct DxTEST_BITS bit; -}; - -struct DxINIT_BITS { // bits description - Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. - Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxINIT_REG { - Uint32 all; - struct DxINIT_BITS bit; -}; - -struct DxINITDONE_BITS { // bits description - Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. - Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DxINITDONE_REG { - Uint32 all; - struct DxINITDONE_BITS bit; -}; - -struct LSxLOCK_BITS { // bits description - Uint16 LOCK_LS0:1; // 0 LS0 RAM Lock bits - Uint16 LOCK_LS1:1; // 1 LS1 RAM Lock bits - Uint16 LOCK_LS2:1; // 2 LS2 RAM Lock bits - Uint16 LOCK_LS3:1; // 3 LS3 RAM Lock bits - Uint16 LOCK_LS4:1; // 4 LS4 RAM Lock bits - Uint16 LOCK_LS5:1; // 5 LS5 RAM Lock bits - Uint16 LOCK_LS6:1; // 6 LS6 RAM Lock bits - Uint16 LOCK_LS7:1; // 7 LS7 RAM Lock bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxLOCK_REG { - Uint32 all; - struct LSxLOCK_BITS bit; -}; - -struct LSxCOMMIT_BITS { // bits description - Uint16 COMMIT_LS0:1; // 0 LS0 RAM Permanent Lock bits - Uint16 COMMIT_LS1:1; // 1 LS1 RAM Permanent Lock bits - Uint16 COMMIT_LS2:1; // 2 LS2 RAM Permanent Lock bits - Uint16 COMMIT_LS3:1; // 3 LS3 RAM Permanent Lock bits - Uint16 COMMIT_LS4:1; // 4 LS4 RAM Permanent Lock bits - Uint16 COMMIT_LS5:1; // 5 LS5 RAM Permanent Lock bits - Uint16 COMMIT_LS6:1; // 6 LS6 RAM Permanent Lock bits - Uint16 COMMIT_LS7:1; // 7 LS7 RAM Permanent Lock bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCOMMIT_REG { - Uint32 all; - struct LSxCOMMIT_BITS bit; -}; - -struct LSxMSEL_BITS { // bits description - Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM - Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM - Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM - Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM - Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM - Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM - Uint16 MSEL_LS6:2; // 13:12 Master Select for LS6 RAM - Uint16 MSEL_LS7:2; // 15:14 Master Select for LS7 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union LSxMSEL_REG { - Uint32 all; - struct LSxMSEL_BITS bit; -}; - -struct LSxCLAPGM_BITS { // bits description - Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS6:1; // 6 Selects LS6 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS7:1; // 7 Selects LS7 RAM as program vs data memory for CLA - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCLAPGM_REG { - Uint32 all; - struct LSxCLAPGM_BITS bit; -}; - -struct LSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM - Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM - Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM - Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM - Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT0_REG { - Uint32 all; - struct LSxACCPROT0_BITS bit; -}; - -struct LSxACCPROT1_BITS { // bits description - Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM - Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM - Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS6:1; // 16 Fetch Protection For LS6 RAM - Uint16 CPUWRPROT_LS6:1; // 17 CPU WR Protection For LS6 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS7:1; // 24 Fetch Protection For LS7 RAM - Uint16 CPUWRPROT_LS7:1; // 25 CPU WR Protection For LS7 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT1_REG { - Uint32 all; - struct LSxACCPROT1_BITS bit; -}; - -struct LSxTEST_BITS { // bits description - Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM - Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM - Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM - Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM - Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM - Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM - Uint16 TEST_LS6:2; // 13:12 Selects the different modes for LS6 RAM - Uint16 TEST_LS7:2; // 15:14 Selects the different modes for LS7 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union LSxTEST_REG { - Uint32 all; - struct LSxTEST_BITS bit; -}; - -struct LSxINIT_BITS { // bits description - Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. - Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. - Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. - Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. - Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. - Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. - Uint16 INIT_LS6:1; // 6 RAM Initialization control for LS6 RAM. - Uint16 INIT_LS7:1; // 7 RAM Initialization control for LS7 RAM. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINIT_REG { - Uint32 all; - struct LSxINIT_BITS bit; -}; - -struct LSxINITDONE_BITS { // bits description - Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. - Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. - Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. - Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. - Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. - Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. - Uint16 INITDONE_LS6:1; // 6 RAM Initialization status for LS6 RAM. - Uint16 INITDONE_LS7:1; // 7 RAM Initialization status for LS7 RAM. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINITDONE_REG { - Uint32 all; - struct LSxINITDONE_BITS bit; -}; - -struct GSxLOCK_BITS { // bits description - Uint16 LOCK_GS0:1; // 0 GS0 RAM Lock bits - Uint16 LOCK_GS1:1; // 1 GS1 RAM Lock bits - Uint16 LOCK_GS2:1; // 2 GS2 RAM Lock bits - Uint16 LOCK_GS3:1; // 3 GS3 RAM Lock bits - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxLOCK_REG { - Uint32 all; - struct GSxLOCK_BITS bit; -}; - -struct GSxCOMMIT_BITS { // bits description - Uint16 COMMIT_GS0:1; // 0 GS0 RAM Permanent Lock bits - Uint16 COMMIT_GS1:1; // 1 GS1 RAM Permanent Lock bits - Uint16 COMMIT_GS2:1; // 2 GS2 RAM Permanent Lock bits - Uint16 COMMIT_GS3:1; // 3 GS3 RAM Permanent Lock bits - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxCOMMIT_REG { - Uint32 all; - struct GSxCOMMIT_BITS bit; -}; - -struct GSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM - Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM - Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM - Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM - Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM - Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM - Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM - Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM - Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT0_REG { - Uint32 all; - struct GSxACCPROT0_BITS bit; -}; - -struct GSxTEST_BITS { // bits description - Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM - Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM - Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM - Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM - Uint16 rsvd1:2; // 9:8 Reserved - Uint16 rsvd2:2; // 11:10 Reserved - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 rsvd4:2; // 15:14 Reserved - Uint16 rsvd5:2; // 17:16 Reserved - Uint16 rsvd6:2; // 19:18 Reserved - Uint16 rsvd7:2; // 21:20 Reserved - Uint16 rsvd8:2; // 23:22 Reserved - Uint16 rsvd9:2; // 25:24 Reserved - Uint16 rsvd10:2; // 27:26 Reserved - Uint16 rsvd11:2; // 29:28 Reserved - Uint16 rsvd12:2; // 31:30 Reserved -}; - -union GSxTEST_REG { - Uint32 all; - struct GSxTEST_BITS bit; -}; - -struct GSxINIT_BITS { // bits description - Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. - Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. - Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. - Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxINIT_REG { - Uint32 all; - struct GSxINIT_BITS bit; -}; - -struct GSxINITDONE_BITS { // bits description - Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. - Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. - Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. - Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 rsvd10:1; // 13 Reserved - Uint16 rsvd11:1; // 14 Reserved - Uint16 rsvd12:1; // 15 Reserved - Uint16 rsvd13:16; // 31:16 Reserved -}; - -union GSxINITDONE_REG { - Uint32 all; - struct GSxINITDONE_BITS bit; -}; - -struct MSGxLOCK_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 LOCK_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM Lock bits - Uint16 LOCK_CLA1TOCPU:1; // 2 CLA1TOCPU RAM Lock bits - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxLOCK_REG { - Uint32 all; - struct MSGxLOCK_BITS bit; -}; - -struct MSGxCOMMIT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 COMMIT_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM control fields COMMIT bit - Uint16 COMMIT_CLA1TOCPU:1; // 2 CLA1TOCPU RAM control fields COMMIT bit - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxCOMMIT_REG { - Uint32 all; - struct MSGxCOMMIT_BITS bit; -}; - -struct MSGxTEST_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select - Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxTEST_REG { - Uint32 all; - struct MSGxTEST_BITS bit; -}; - -struct MSGxINIT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM - Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxINIT_REG { - Uint32 all; - struct MSGxINIT_BITS bit; -}; - -struct MSGxINITDONE_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM - Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union MSGxINITDONE_REG { - Uint32 all; - struct MSGxINITDONE_BITS bit; -}; - -struct MEM_CFG_REGS { - union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register - union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register - Uint16 rsvd1[12]; // Reserved - union DxTEST_REG DxTEST; // Dedicated RAM TEST Register - union DxINIT_REG DxINIT; // Dedicated RAM Init Register - union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register - Uint16 rsvd2[10]; // Reserved - union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register - union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register - union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register - union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register - union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 - union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 - Uint16 rsvd3[4]; // Reserved - union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register - union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register - union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register - Uint16 rsvd4[10]; // Reserved - union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register - union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register - Uint16 rsvd5[4]; // Reserved - union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 - Uint16 rsvd6[6]; // Reserved - union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register - union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register - union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register - Uint16 rsvd7[10]; // Reserved - union MSGxLOCK_REG MSGxLOCK; // Message RAM Config Lock Register - union MSGxCOMMIT_REG MSGxCOMMIT; // Message RAM Config Lock Commit Register - Uint16 rsvd8[12]; // Reserved - union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register - union MSGxINIT_REG MSGxINIT; // Message RAM Init Register - union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register - Uint16 rsvd9[10]; // Reserved -}; - -struct NMAVFLG_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVFLG_REG { - Uint32 all; - struct NMAVFLG_BITS bit; -}; - -struct NMAVSET_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVSET_REG { - Uint32 all; - struct NMAVSET_BITS bit; -}; - -struct NMAVCLR_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVCLR_REG { - Uint32 all; - struct NMAVCLR_BITS bit; -}; - -struct NMAVINTEN_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:6; // 15:10 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union NMAVINTEN_REG { - Uint32 all; - struct NMAVINTEN_BITS bit; -}; - -struct MAVFLG_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVFLG_REG { - Uint32 all; - struct MAVFLG_BITS bit; -}; - -struct MAVSET_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVSET_REG { - Uint32 all; - struct MAVSET_BITS bit; -}; - -struct MAVCLR_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVCLR_REG { - Uint32 all; - struct MAVCLR_BITS bit; -}; - -struct MAVINTEN_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVINTEN_REG { - Uint32 all; - struct MAVINTEN_BITS bit; -}; - -struct ACCESS_PROTECTION_REGS { - union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register - union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register - union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register - union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register - Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address - Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address - Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address - Uint16 rsvd1[2]; // Reserved - Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address - Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address - Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address - Uint16 rsvd2[10]; // Reserved - union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register - union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register - union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register - union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register - Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address - Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address - Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address - Uint16 rsvd3[18]; // Reserved -}; - -struct UCERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRFLG_REG { - Uint32 all; - struct UCERRFLG_BITS bit; -}; - -struct UCERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRSET_REG { - Uint32 all; - struct UCERRSET_BITS bit; -}; - -struct UCERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRCLR_REG { - Uint32 all; - struct UCERRCLR_BITS bit; -}; - -struct CERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRFLG_REG { - Uint32 all; - struct CERRFLG_BITS bit; -}; - -struct CERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRSET_REG { - Uint32 all; - struct CERRSET_BITS bit; -}; - -struct CERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRCLR_REG { - Uint32 all; - struct CERRCLR_BITS bit; -}; - -struct CEINTFLG_BITS { // bits description - Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTFLG_REG { - Uint32 all; - struct CEINTFLG_BITS bit; -}; - -struct CEINTCLR_BITS { // bits description - Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTCLR_REG { - Uint32 all; - struct CEINTCLR_BITS bit; -}; - -struct CEINTSET_BITS { // bits description - Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTSET_REG { - Uint32 all; - struct CEINTSET_BITS bit; -}; - -struct CEINTEN_BITS { // bits description - Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTEN_REG { - Uint32 all; - struct CEINTEN_BITS bit; -}; - -struct MEMORY_ERROR_REGS { - union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register - union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register - union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register - Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address - Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address - Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address - Uint16 rsvd1[20]; // Reserved - union CERRFLG_REG CERRFLG; // Correctable Error Flag Register - union CERRSET_REG CERRSET; // Correctable Error Flag Set Register - union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register - Uint32 CCPUREADDR; // Correctable CPU Read Error Address - Uint16 rsvd2[6]; // Reserved - Uint32 CERRCNT; // Correctable Error Count Register - Uint32 CERRTHRES; // Correctable Error Threshold Value Register - union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register - union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register - union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register - union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register - Uint16 rsvd3[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// MEMCONFIG External References & Function Declarations: -// -extern volatile struct MEM_CFG_REGS MemCfgRegs; -extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; -extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h deleted file mode 100644 index 73c40c6..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_nmiintrupt.h +++ /dev/null @@ -1,178 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_nmiintrupt.h -// -// TITLE: NMIINTRUPT Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_NMIINTRUPT_H__ -#define __F28004X_NMIINTRUPT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// NMIINTRUPT Individual Register Bit Definitions: - -struct NMICFG_BITS { // bits description - Uint16 NMIE:1; // 0 Global NMI Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union NMICFG_REG { - Uint16 all; - struct NMICFG_BITS bit; -}; - -struct NMIFLG_BITS { // bits description - Uint16 NMIINT:1; // 0 NMI Interrupt Flag - Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag - Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag - Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 rsvd7:1; // 11 Reserved - Uint16 rsvd8:1; // 12 Reserved - Uint16 SWERR:1; // 13 SW Error Force NMI Flag - Uint16 rsvd9:2; // 15:14 Reserved -}; - -union NMIFLG_REG { - Uint16 all; - struct NMIFLG_BITS bit; -}; - -struct NMIFLGCLR_BITS { // bits description - Uint16 NMIINT:1; // 0 NMIINT Flag Clear - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 rsvd7:1; // 11 Reserved - Uint16 rsvd8:1; // 12 Reserved - Uint16 SWERR:1; // 13 SWERR Flag Clear - Uint16 rsvd9:2; // 15:14 Reserved -}; - -union NMIFLGCLR_REG { - Uint16 all; - struct NMIFLGCLR_BITS bit; -}; - -struct NMIFLGFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 SWERR:1; // 13 SWERR Flag Force - Uint16 rsvd10:2; // 15:14 Reserved -}; - -union NMIFLGFRC_REG { - Uint16 all; - struct NMIFLGFRC_BITS bit; -}; - -struct NMISHDFLG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag - Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag - Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:1; // 8 Reserved - Uint16 rsvd6:1; // 9 Reserved - Uint16 rsvd7:1; // 10 Reserved - Uint16 rsvd8:1; // 11 Reserved - Uint16 rsvd9:1; // 12 Reserved - Uint16 SWERR:1; // 13 SW Error Force NMI Flag - Uint16 rsvd10:2; // 15:14 Reserved -}; - -union NMISHDFLG_REG { - Uint16 all; - struct NMISHDFLG_BITS bit; -}; - -struct NMI_INTRUPT_REGS { - union NMICFG_REG NMICFG; // NMI Configuration Register - union NMIFLG_REG NMIFLG; // NMI Flag Register (SYSRsn Clear) - union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register - union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register - Uint16 NMIWDCNT; // NMI Watchdog Counter Register - Uint16 NMIWDPRD; // NMI Watchdog Period Register - union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register -}; - -//--------------------------------------------------------------------------- -// NMIINTRUPT External References & Function Declarations: -// -extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h deleted file mode 100644 index 461cfdf..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_output_xbar.h +++ /dev/null @@ -1,905 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_output_xbar.h -// -// TITLE: OUTPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_OUTPUT_XBAR_H__ -#define __F28004X_OUTPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR Individual Register Bit Definitions: - -struct OUTPUT1MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT1MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT1MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT1MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT2MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT2MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT2MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT2MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT3MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT3MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT3MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT3MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT4MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT4MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT5MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT5MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT6MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT6MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT6MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT6MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT7MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT7MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT8MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT8MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT1MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUXENABLE_REG { - Uint32 all; - struct OUTPUT1MUXENABLE_BITS bit; -}; - -struct OUTPUT2MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUXENABLE_REG { - Uint32 all; - struct OUTPUT2MUXENABLE_BITS bit; -}; - -struct OUTPUT3MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUXENABLE_REG { - Uint32 all; - struct OUTPUT3MUXENABLE_BITS bit; -}; - -struct OUTPUT4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUXENABLE_REG { - Uint32 all; - struct OUTPUT4MUXENABLE_BITS bit; -}; - -struct OUTPUT5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUXENABLE_REG { - Uint32 all; - struct OUTPUT5MUXENABLE_BITS bit; -}; - -struct OUTPUT6MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUXENABLE_REG { - Uint32 all; - struct OUTPUT6MUXENABLE_BITS bit; -}; - -struct OUTPUT7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUXENABLE_REG { - Uint32 all; - struct OUTPUT7MUXENABLE_BITS bit; -}; - -struct OUTPUT8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUXENABLE_REG { - Uint32 all; - struct OUTPUT8MUXENABLE_BITS bit; -}; - -struct OUTPUTLATCH_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCH_REG { - Uint32 all; - struct OUTPUTLATCH_BITS bit; -}; - -struct OUTPUTLATCHCLR_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHCLR_REG { - Uint32 all; - struct OUTPUTLATCHCLR_BITS bit; -}; - -struct OUTPUTLATCHFRC_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHFRC_REG { - Uint32 all; - struct OUTPUTLATCHFRC_BITS bit; -}; - -struct OUTPUTLATCHENABLE_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHENABLE_REG { - Uint32 all; - struct OUTPUTLATCHENABLE_BITS bit; -}; - -struct OUTPUTINV_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTINV_REG { - Uint32 all; - struct OUTPUTINV_BITS bit; -}; - -struct OUTPUTLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write Protection KEY -}; - -union OUTPUTLOCK_REG { - Uint32 all; - struct OUTPUTLOCK_BITS bit; -}; - -struct OUTPUT_XBAR_REGS { - union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 - union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 - union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 - union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 - union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 - union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 - union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 - union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 - union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch - union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear - union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear - union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable - union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion - Uint16 rsvd1[4]; // Reserved - union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR External References & Function Declarations: -// -extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h deleted file mode 100644 index d4adbd8..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pga.h +++ /dev/null @@ -1,164 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pga.h -// -// TITLE: PGA Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PGA_H__ -#define __F28004X_PGA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PGA Individual Register Bit Definitions: - -struct PGACTL_BITS { // bits description - Uint16 PGAEN:1; // 0 PGA Enable - Uint16 FILTRESSEL:4; // 4:1 Filter Resistor Select - Uint16 GAIN:3; // 7:5 PGA gain setting - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGACTL_REG { - Uint32 all; - struct PGACTL_BITS bit; -}; - -struct PGALOCK_BITS { // bits description - Uint16 PGACTL:1; // 0 Lock bit for PGACTL. - Uint16 rsvd1:1; // 1 Reserved - Uint16 PGAGAIN3TRIM:1; // 2 Lock bit for PGAGAIN3TRIM. - Uint16 PGAGAIN6TRIM:1; // 3 Lock bit for PGAGAIN6TRIM. - Uint16 PGAGAIN12TRIM:1; // 4 Lock bit for PGAGAIN12TRIM. - Uint16 PGAGAIN24TRIM:1; // 5 Lock bit for PGAGAIN24TRIM. - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:8; // 15:8 Reserved -}; - -union PGALOCK_REG { - Uint16 all; - struct PGALOCK_BITS bit; -}; - -struct PGAGAIN3TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 3 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 3 -}; - -union PGAGAIN3TRIM_REG { - Uint16 all; - struct PGAGAIN3TRIM_BITS bit; -}; - -struct PGAGAIN6TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 6 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 6 -}; - -union PGAGAIN6TRIM_REG { - Uint16 all; - struct PGAGAIN6TRIM_BITS bit; -}; - -struct PGAGAIN12TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 12 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 12 -}; - -union PGAGAIN12TRIM_REG { - Uint16 all; - struct PGAGAIN12TRIM_BITS bit; -}; - -struct PGAGAIN24TRIM_BITS { // bits description - Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 24 - Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 24 -}; - -union PGAGAIN24TRIM_REG { - Uint16 all; - struct PGAGAIN24TRIM_BITS bit; -}; - -struct PGATYPE_BITS { // bits description - Uint16 REV:8; // 7:0 PGA Revision Field - Uint16 TYPE:8; // 15:8 PGA Type Field -}; - -union PGATYPE_REG { - Uint16 all; - struct PGATYPE_BITS bit; -}; - -struct PGA_REGS { - union PGACTL_REG PGACTL; // PGA Control Register - union PGALOCK_REG PGALOCK; // PGA Lock Register - Uint16 rsvd1; // Reserved - union PGAGAIN3TRIM_REG PGAGAIN3TRIM; // PGA Gain Trim Register for a gain setting of 3 - union PGAGAIN6TRIM_REG PGAGAIN6TRIM; // PGA Gain Trim Register for a gain setting of 6 - union PGAGAIN12TRIM_REG PGAGAIN12TRIM; // PGA Gain Trim Register for a gain setting of 12 - union PGAGAIN24TRIM_REG PGAGAIN24TRIM; // PGA Gain Trim Register for a gain setting of 24 - union PGATYPE_REG PGATYPE; // PGA Type Register - Uint16 rsvd2[7]; // Reserved -}; - -//--------------------------------------------------------------------------- -// PGA External References & Function Declarations: -// -extern volatile struct PGA_REGS Pga1Regs; -extern volatile struct PGA_REGS Pga2Regs; -extern volatile struct PGA_REGS Pga3Regs; -extern volatile struct PGA_REGS Pga4Regs; -extern volatile struct PGA_REGS Pga5Regs; -extern volatile struct PGA_REGS Pga6Regs; -extern volatile struct PGA_REGS Pga7Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h deleted file mode 100644 index 2c44154..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_piectrl.h +++ /dev/null @@ -1,702 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_piectrl.h -// -// TITLE: PIECTRL Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PIECTRL_H__ -#define __F28004X_PIECTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PIECTRL Individual Register Bit Definitions: - -struct PIECTRL_BITS { // bits description - Uint16 ENPIE:1; // 0 PIE Enable - Uint16 PIEVECT:15; // 15:1 PIE Vector Address -}; - -union PIECTRL_REG { - Uint16 all; - struct PIECTRL_BITS bit; -}; - -struct PIEACK_BITS { // bits description - Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 - Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 - Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 - Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 - Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 - Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 - Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 - Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 - Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 - Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 - Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 - Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union PIEACK_REG { - Uint16 all; - struct PIEACK_BITS bit; -}; - -struct PIEIER1_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 -}; - -union PIEIER1_REG { - Uint16 all; - struct PIEIER1_BITS bit; -}; - -struct PIEIFR1_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 -}; - -union PIEIFR1_REG { - Uint16 all; - struct PIEIFR1_BITS bit; -}; - -struct PIEIER2_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 -}; - -union PIEIER2_REG { - Uint16 all; - struct PIEIER2_BITS bit; -}; - -struct PIEIFR2_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 -}; - -union PIEIFR2_REG { - Uint16 all; - struct PIEIFR2_BITS bit; -}; - -struct PIEIER3_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 -}; - -union PIEIER3_REG { - Uint16 all; - struct PIEIER3_BITS bit; -}; - -struct PIEIFR3_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 -}; - -union PIEIFR3_REG { - Uint16 all; - struct PIEIFR3_BITS bit; -}; - -struct PIEIER4_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 -}; - -union PIEIER4_REG { - Uint16 all; - struct PIEIER4_BITS bit; -}; - -struct PIEIFR4_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 -}; - -union PIEIFR4_REG { - Uint16 all; - struct PIEIFR4_BITS bit; -}; - -struct PIEIER5_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 -}; - -union PIEIER5_REG { - Uint16 all; - struct PIEIER5_BITS bit; -}; - -struct PIEIFR5_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 -}; - -union PIEIFR5_REG { - Uint16 all; - struct PIEIFR5_BITS bit; -}; - -struct PIEIER6_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 -}; - -union PIEIER6_REG { - Uint16 all; - struct PIEIER6_BITS bit; -}; - -struct PIEIFR6_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 -}; - -union PIEIFR6_REG { - Uint16 all; - struct PIEIFR6_BITS bit; -}; - -struct PIEIER7_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 -}; - -union PIEIER7_REG { - Uint16 all; - struct PIEIER7_BITS bit; -}; - -struct PIEIFR7_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 -}; - -union PIEIFR7_REG { - Uint16 all; - struct PIEIFR7_BITS bit; -}; - -struct PIEIER8_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 -}; - -union PIEIER8_REG { - Uint16 all; - struct PIEIER8_BITS bit; -}; - -struct PIEIFR8_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 -}; - -union PIEIFR8_REG { - Uint16 all; - struct PIEIFR8_BITS bit; -}; - -struct PIEIER9_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 -}; - -union PIEIER9_REG { - Uint16 all; - struct PIEIER9_BITS bit; -}; - -struct PIEIFR9_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 -}; - -union PIEIFR9_REG { - Uint16 all; - struct PIEIFR9_BITS bit; -}; - -struct PIEIER10_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 -}; - -union PIEIER10_REG { - Uint16 all; - struct PIEIER10_BITS bit; -}; - -struct PIEIFR10_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 -}; - -union PIEIFR10_REG { - Uint16 all; - struct PIEIFR10_BITS bit; -}; - -struct PIEIER11_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 -}; - -union PIEIER11_REG { - Uint16 all; - struct PIEIER11_BITS bit; -}; - -struct PIEIFR11_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 -}; - -union PIEIFR11_REG { - Uint16 all; - struct PIEIFR11_BITS bit; -}; - -struct PIEIER12_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 -}; - -union PIEIER12_REG { - Uint16 all; - struct PIEIER12_BITS bit; -}; - -struct PIEIFR12_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 -}; - -union PIEIFR12_REG { - Uint16 all; - struct PIEIFR12_BITS bit; -}; - -struct PIE_CTRL_REGS { - union PIECTRL_REG PIECTRL; // ePIE Control Register - union PIEACK_REG PIEACK; // Interrupt Acknowledge Register - union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register - union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register - union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register - union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register - union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register - union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register - union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register - union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register - union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register - union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register - union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register - union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register - union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register - union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register - union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register - union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register - union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register - union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register - union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register - union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register - union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register - union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register - union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register - union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register -}; - -//--------------------------------------------------------------------------- -// PIECTRL External References & Function Declarations: -// -extern volatile struct PIE_CTRL_REGS PieCtrlRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h deleted file mode 100644 index 54899af..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pievect.h +++ /dev/null @@ -1,297 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pievect.h -// -// TITLE: F28004x Device PIE Vector Table Definitions -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28004X_PIEVECT_H -#define F28004X_PIEVECT_H -#ifdef __cplusplus -extern "C" { -#endif - -//--------------------------------------------------------------------------- -// PIE Interrupt Vector Table Definition: -// Create a user type called PINT (pointer to interrupt): - -typedef __interrupt void (*PINT)(void); - -// Define Vector Table: -struct PIE_VECT_TABLE { - PINT PIE1_RESERVED_INT; // Reserved - PINT PIE2_RESERVED_INT; // Reserved - PINT PIE3_RESERVED_INT; // Reserved - PINT PIE4_RESERVED_INT; // Reserved - PINT PIE5_RESERVED_INT; // Reserved - PINT PIE6_RESERVED_INT; // Reserved - PINT PIE7_RESERVED_INT; // Reserved - PINT PIE8_RESERVED_INT; // Reserved - PINT PIE9_RESERVED_INT; // Reserved - PINT PIE10_RESERVED_INT; // Reserved - PINT PIE11_RESERVED_INT; // Reserved - PINT PIE12_RESERVED_INT; // Reserved - PINT PIE13_RESERVED_INT; // Reserved - PINT TIMER1_INT; // CPU Timer 1 Interrupt - PINT TIMER2_INT; // CPU Timer 2 Interrupt - PINT DATALOG_INT; // Datalogging Interrupt - PINT RTOS_INT; // RTOS Interrupt - PINT EMU_INT; // Emulation Interrupt - PINT NMI_INT; // Non-Maskable Interrupt - PINT ILLEGAL_INT; // Illegal Operation Trap - PINT USER1_INT; // User Defined Trap 1 - PINT USER2_INT; // User Defined Trap 2 - PINT USER3_INT; // User Defined Trap 3 - PINT USER4_INT; // User Defined Trap 4 - PINT USER5_INT; // User Defined Trap 5 - PINT USER6_INT; // User Defined Trap 6 - PINT USER7_INT; // User Defined Trap 7 - PINT USER8_INT; // User Defined Trap 8 - PINT USER9_INT; // User Defined Trap 9 - PINT USER10_INT; // User Defined Trap 10 - PINT USER11_INT; // User Defined Trap 11 - PINT USER12_INT; // User Defined Trap 12 - PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 - PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 - PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 - PINT XINT1_INT; // 1.4 - XINT1 Interrupt - PINT XINT2_INT; // 1.5 - XINT2 Interrupt - PINT PIE14_RESERVED_INT; // 1.6 - Reserved - PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt - PINT WAKE_INT; // 1.8 - Halt Wakeup Interrupt - PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt - PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt - PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt - PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt - PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt - PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt - PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt - PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt - PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt - PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt - PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt - PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt - PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt - PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt - PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt - PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt - PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt - PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt - PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt - PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt - PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt - PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt - PINT ECAP7_INT; // 4.7 - eCAP7 Interrupt - PINT PIE15_RESERVED_INT; // 4.8 - Reserved - PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt - PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt - PINT PIE16_RESERVED_INT; // 5.3 - Reserved - PINT PIE17_RESERVED_INT; // 5.4 - Reserved - PINT PIE18_RESERVED_INT; // 5.5 - Reserved - PINT PIE19_RESERVED_INT; // 5.6 - Reserved - PINT PIE20_RESERVED_INT; // 5.7 - Reserved - PINT PIE21_RESERVED_INT; // 5.8 - Reserved - PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt - PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt - PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt - PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt - PINT PIE22_RESERVED_INT; // 6.5 - Reserved - PINT PIE23_RESERVED_INT; // 6.6 - Reserved - PINT PIE24_RESERVED_INT; // 6.7 - Reserved - PINT PIE25_RESERVED_INT; // 6.8 - Reserved - PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt - PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt - PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt - PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt - PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt - PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt - PINT PIE26_RESERVED_INT; // 7.7 - Reserved - PINT PIE27_RESERVED_INT; // 7.8 - Reserved - PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 - PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 - PINT PIE28_RESERVED_INT; // 8.3 - Reserved - PINT PIE29_RESERVED_INT; // 8.4 - Reserved - PINT PIE30_RESERVED_INT; // 8.5 - Reserved - PINT PIE31_RESERVED_INT; // 8.6 - Reserved - PINT PIE32_RESERVED_INT; // 8.7 - Reserved - PINT PIE33_RESERVED_INT; // 8.8 - Reserved - PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt - PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt - PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt - PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt - PINT CANA0_INT; // 9.5 - CANA Interrupt 0 - PINT CANA1_INT; // 9.6 - CANA Interrupt 1 - PINT CANB0_INT; // 9.7 - CANB Interrupt 0 - PINT CANB1_INT; // 9.8 - CANB Interrupt 1 - PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt - PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 - PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 - PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 - PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt - PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 - PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 - PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 - PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 - PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 - PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 - PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 - PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 - PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 - PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 - PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 - PINT XINT3_INT; // 12.1 - XINT3 Interrupt - PINT XINT4_INT; // 12.2 - XINT4 Interrupt - PINT XINT5_INT; // 12.3 - XINT5 Interrupt - PINT PIE34_RESERVED_INT; // 12.4 - Reserved - PINT PIE35_RESERVED_INT; // 12.5 - Reserved - PINT PIE36_RESERVED_INT; // 12.6 - Reserved - PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt - PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt - PINT PIE37_RESERVED_INT; // 1.9 - Reserved - PINT PIE38_RESERVED_INT; // 1.10 - Reserved - PINT PIE39_RESERVED_INT; // 1.11 - Reserved - PINT PIE40_RESERVED_INT; // 1.12 - Reserved - PINT PIE41_RESERVED_INT; // 1.13 - Reserved - PINT PIE42_RESERVED_INT; // 1.14 - Reserved - PINT PIE43_RESERVED_INT; // 1.15 - Reserved - PINT PIE44_RESERVED_INT; // 1.16 - Reserved - PINT PIE45_RESERVED_INT; // 2.9 - Reserved - PINT PIE46_RESERVED_INT; // 2.10 - Reserved - PINT PIE47_RESERVED_INT; // 2.11 - Reserved - PINT PIE48_RESERVED_INT; // 2.12 - Reserved - PINT PIE49_RESERVED_INT; // 2.13 - Reserved - PINT PIE50_RESERVED_INT; // 2.14 - Reserved - PINT PIE51_RESERVED_INT; // 2.15 - Reserved - PINT PIE52_RESERVED_INT; // 2.16 - Reserved - PINT PIE53_RESERVED_INT; // 3.9 - Reserved - PINT PIE54_RESERVED_INT; // 3.10 - Reserved - PINT PIE55_RESERVED_INT; // 3.11 - Reserved - PINT PIE56_RESERVED_INT; // 3.12 - Reserved - PINT PIE57_RESERVED_INT; // 3.13 - Reserved - PINT PIE58_RESERVED_INT; // 3.14 - Reserved - PINT PIE59_RESERVED_INT; // 3.15 - Reserved - PINT PIE60_RESERVED_INT; // 3.16 - Reserved - PINT PIE61_RESERVED_INT; // 4.9 - Reserved - PINT PIE62_RESERVED_INT; // 4.10 - Reserved - PINT PIE63_RESERVED_INT; // 4.11 - Reserved - PINT PIE64_RESERVED_INT; // 4.12 - Reserved - PINT PIE65_RESERVED_INT; // 4.13 - Reserved - PINT ECAP6_2_INT; // 4.14 - eCAP6_2 Interrupt - PINT ECAP7_2_INT; // 4.15 - eCAP7_2 Interrupt - PINT PIE66_RESERVED_INT; // 4.16 - Reserved - PINT SD1_INT; // 5.9 - SD1 Interrupt - PINT PIE67_RESERVED_INT; // 5.10 - Reserved - PINT PIE68_RESERVED_INT; // 5.11 - Reserved - PINT PIE69_RESERVED_INT; // 5.12 - Reserved - PINT SD1DR1_INT; // 5.13 - SD1DR1 Interrupt - PINT SD1DR2_INT; // 5.14 - SD1DR2 Interrupt - PINT SD1DR3_INT; // 5.15 - SD1DR3 Interrupt - PINT SD1DR4_INT; // 5.16 - SD1DR4 Interrupt - PINT PIE70_RESERVED_INT; // 6.9 - Reserved - PINT PIE71_RESERVED_INT; // 6.10 - Reserved - PINT PIE72_RESERVED_INT; // 6.11 - Reserved - PINT PIE73_RESERVED_INT; // 6.12 - Reserved - PINT PIE74_RESERVED_INT; // 6.13 - Reserved - PINT PIE75_RESERVED_INT; // 6.14 - Reserved - PINT PIE76_RESERVED_INT; // 6.15 - Reserved - PINT PIE77_RESERVED_INT; // 6.16 - Reserved - PINT PIE78_RESERVED_INT; // 7.9 - Reserved - PINT PIE79_RESERVED_INT; // 7.10 - Reserved - PINT PIE80_RESERVED_INT; // 7.11 - Reserved - PINT PIE81_RESERVED_INT; // 7.12 - Reserved - PINT PIE82_RESERVED_INT; // 7.13 - Reserved - PINT PIE83_RESERVED_INT; // 7.14 - Reserved - PINT CLA1PROMCRC_INT; // 7.15 - CLA1PROMCRC Interrupt - PINT PIE84_RESERVED_INT; // 7.16 - Reserved - PINT LINA_0_INT; // 8.9 - LINA Interrupt0 - PINT LINA_1_INT; // 8.10 - LINA Interrupt1 - PINT PIE85_RESERVED_INT; // 8.11 - Reserved - PINT PIE86_RESERVED_INT; // 8.12 - Reserved - PINT PMBUSA_INT; // 8.13 - PMBUSA Interrupt - PINT PIE87_RESERVED_INT; // 8.14 - Reserved - PINT PIE88_RESERVED_INT; // 8.15 - Reserved - PINT PIE89_RESERVED_INT; // 8.16 - Reserved - PINT PIE90_RESERVED_INT; // 9.9 - Reserved - PINT PIE91_RESERVED_INT; // 9.10 - Reserved - PINT PIE92_RESERVED_INT; // 9.11 - Reserved - PINT PIE93_RESERVED_INT; // 9.12 - Reserved - PINT PIE94_RESERVED_INT; // 9.13 - Reserved - PINT PIE95_RESERVED_INT; // 9.14 - Reserved - PINT PIE96_RESERVED_INT; // 9.15 - Reserved - PINT PIE97_RESERVED_INT; // 9.16 - Reserved - PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt - PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 - PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 - PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 - PINT PIE98_RESERVED_INT; // 10.13 - Reserved - PINT PIE99_RESERVED_INT; // 10.14 - Reserved - PINT PIE100_RESERVED_INT; // 10.15 - Reserved - PINT PIE101_RESERVED_INT; // 10.16 - Reserved - PINT PIE102_RESERVED_INT; // 11.9 - Reserved - PINT PIE103_RESERVED_INT; // 11.10 - Reserved - PINT PIE104_RESERVED_INT; // 11.11 - Reserved - PINT PIE105_RESERVED_INT; // 11.12 - Reserved - PINT PIE106_RESERVED_INT; // 11.13 - Reserved - PINT PIE107_RESERVED_INT; // 11.14 - Reserved - PINT PIE108_RESERVED_INT; // 11.15 - Reserved - PINT PIE109_RESERVED_INT; // 11.16 - Reserved - PINT PIE110_RESERVED_INT; // 12.9 - Reserved - PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt - PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt - PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt - PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt - PINT PIE111_RESERVED_INT; // 12.14 - Reserved - PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt - PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt -}; - -//--------------------------------------------------------------------------- -// PieVect External References & Function Declarations: -// - -extern volatile struct PIE_VECT_TABLE PieVectTable; - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F28004X_PIEVECT_H definition -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h deleted file mode 100644 index 0f55745..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_pmbus.h +++ /dev/null @@ -1,291 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_pmbus.h -// -// TITLE: PMBUS Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_PMBUS_H__ -#define __F28004X_PMBUS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PMBUS Individual Register Bit Definitions: - -struct PMBMC_BITS { // bits description - Uint16 RW:1; // 0 RnW bit of the Message - Uint16 SLAVE_ADDR:7; // 7:1 Slave Address - Uint16 BYTE_COUNT:8; // 15:8 Number of Bytes Transmitted - Uint16 CMD_ENA:1; // 16 Master Command Code Enable - Uint16 EXT_CMD:1; // 17 Master Extended Command Code Enable - Uint16 PEC_ENA:1; // 18 Master PEC Processing Enable - Uint16 GRP_CMD:1; // 19 Master Group Command Message Enable - Uint16 PRC_CALL:1; // 20 Master Process Call Message Enable - Uint16 rsvd1:11; // 31:21 Reserved -}; - -union PMBMC_REG { - Uint32 all; - struct PMBMC_BITS bit; -}; - -struct PMBACK_BITS { // bits description - Uint16 ACK:1; // 0 Allows firmware to ack/nack received data - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBACK_REG { - Uint32 all; - struct PMBACK_BITS bit; -}; - -struct PMBSTS_BITS { // bits description - Uint16 RD_BYTE_COUNT:3; // 2:0 Number of Data Bytes available in Receive Data Register - Uint16 DATA_READY:1; // 3 Data Ready Flag - Uint16 DATA_REQUEST:1; // 4 Data Request Flag - Uint16 EOM:1; // 5 End of Message Indicator - Uint16 NACK:1; // 6 Not Acknowledge Flag Status - Uint16 PEC_VALID:1; // 7 PEC Valid Indicator - Uint16 CLK_LOW_TIMEOUT:1; // 8 Clock Low Timeout Status - Uint16 CLK_HIGH_DETECTED:1; // 9 Clock High Detection Status - Uint16 SLAVE_ADDR_READY:1; // 10 Slave Address Ready - Uint16 RPT_START:1; // 11 Repeated Start Flag - Uint16 UNIT_BUSY:1; // 12 PMBus Busy Indicator - Uint16 BUS_FREE:1; // 13 PMBus Free Indicator - Uint16 LOST_ARB:1; // 14 Lost Arbitration Flag - Uint16 MASTER:1; // 15 Master Indicator - Uint16 ALERT_EDGE:1; // 16 Alert Edge Detection Status - Uint16 CONTROL_EDGE:1; // 17 Control Edge Detection Status - Uint16 ALERT_RAW:1; // 18 Alert Pin Real Time Status - Uint16 CONTROL_RAW:1; // 19 Control Pin Real Time Status - Uint16 SDA_RAW:1; // 20 PMBus Data Pin Real Time Status - Uint16 SCL_RAW:1; // 21 PMBus Clock Pin Real Time Status - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PMBSTS_REG { - Uint32 all; - struct PMBSTS_BITS bit; -}; - -struct PMBINTM_BITS { // bits description - Uint16 BUS_FREE:1; // 0 Bus Free Interrupt Mask - Uint16 BUS_LOW_TIMEOUT:1; // 1 Clock Low Timeout Interrupt Mask - Uint16 DATA_READY:1; // 2 Data Ready Interrupt Mask - Uint16 DATA_REQUEST:1; // 3 Data Request Interrupt Mask - Uint16 SLAVE_ADDR_READY:1; // 4 Slave Address Ready Interrupt Mask - Uint16 EOM:1; // 5 End of Message Interrupt Mask - Uint16 ALERT:1; // 6 Alert Detection Interrupt Mask - Uint16 CONTROL:1; // 7 Control Detection Interrupt Mask - Uint16 LOST_ARB:1; // 8 Lost Arbitration Interrupt Mask - Uint16 CLK_HIGH_DETECT:1; // 9 Clock High Detection Interrupt Mask - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBINTM_REG { - Uint32 all; - struct PMBINTM_BITS bit; -}; - -struct PMBSC_BITS { // bits description - Uint16 SLAVE_ADDR:7; // 6:0 Configures the current device address of the slave. - Uint16 MAN_SLAVE_ACK:1; // 7 Manual Slave Address Acknowledgement Mode - Uint16 SLAVE_MASK:7; // 14:8 Slave address mask - Uint16 PEC_ENA:1; // 15 PEC Processing Enable - Uint16 TX_COUNT:3; // 18:16 Number of valid bytes in Transmit Data Register - Uint16 TX_PEC:1; // 19 send a PEC byte at end of message - Uint16 MAN_CMD:1; // 20 Manual Command Acknowledgement Mode - Uint16 RX_BYTE_ACK_CNT:2; // 22:21 Number of data bytes to automatically acknowledge - Uint16 rsvd1:9; // 31:23 Reserved -}; - -union PMBSC_REG { - Uint32 all; - struct PMBSC_BITS bit; -}; - -struct PMBHSA_BITS { // bits description - Uint16 SLAVE_RW:1; // 0 Stored R/W bit - Uint16 SLAVE_ADDR:7; // 7:1 Stored device address - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBHSA_REG { - Uint32 all; - struct PMBHSA_BITS bit; -}; - -struct PMBCTRL_BITS { // bits description - Uint16 RESET:1; // 0 PMBus Interface Synchronous Reset - Uint16 ALERT_EN:1; // 1 Slave Alert Enable - Uint16 BUS_LO_INT_EDGE:1; // 2 Clock Low Timeout Interrupt Edge Select - Uint16 FAST_MODE:1; // 3 Fast Mode Enable - Uint16 FAST_MODE_PLUS:1; // 4 Fast Mode Plus Enable - Uint16 CNTL_INT_EDGE:1; // 5 Control Interrupt Edge Select - Uint16 ALERT_MODE:1; // 6 Configures mode of Alert pin - Uint16 ALERT_VALUE:1; // 7 Configures output value of Alert pin in GPIO Mode - Uint16 ALERT_DIR:1; // 8 Configures direction of Alert pin in GPIO mode - Uint16 CNTL_MODE:1; // 9 Configures mode of Control pin - Uint16 CNTL_VALUE:1; // 10 Configures output value of Control pin in GPIO Mode - Uint16 CNTL_DIR:1; // 11 Configures direction of Control pin in GPIO mode - Uint16 SDA_MODE:1; // 12 Configures mode of PMBus Data pin - Uint16 SDA_VALUE:1; // 13 Configures output value of PMBus data pin in GPIO Mode - Uint16 SDA_DIR:1; // 14 Configures direction of PMBus data pin in GPIO mode - Uint16 SCL_MODE:1; // 15 Configures mode of PMBus Clock pin - Uint16 SCL_VALUE:1; // 16 Configures output value of PMBus clock pin in GPIO Mode - Uint16 SCL_DIR:1; // 17 Configures direction of PMBus clock pin in GPIO mode - Uint16 IBIAS_A_EN:1; // 18 PMBus Current Source A Control - Uint16 IBIAS_B_EN:1; // 19 PMBus Current Source B Control - Uint16 CLK_LO_DIS:1; // 20 Clock Low Timeout Disable - Uint16 SLAVE_EN:1; // 21 PMBus Slave Enable - Uint16 MASTER_EN:1; // 22 PMBus Master Enable - Uint16 CLKDIV:5; // 27:23 PMBUS IP Clock Divide Value - Uint16 rsvd1:3; // 30:28 Reserved - Uint16 I2CMODE:1; // 31 Bit to enable I2C mode -}; - -union PMBCTRL_REG { - Uint32 all; - struct PMBCTRL_BITS bit; -}; - -struct PMBTIMCTL_BITS { // bits description - Uint16 TIM_OVERRIDE:1; // 0 Overide the default settings of the timing parameters. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMCTL_REG { - Uint32 all; - struct PMBTIMCTL_BITS bit; -}; - -struct PMBTIMCLK_BITS { // bits description - Uint16 CLK_HIGH_LIMIT:8; // 7:0 Determines the PMBUS master clock high pulse width. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 CLK_FREQ:8; // 23:16 Determines the PMBUS master clock frequency. - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union PMBTIMCLK_REG { - Uint32 all; - struct PMBTIMCLK_BITS bit; -}; - -struct PMBTIMSTSETUP_BITS { // bits description - Uint16 TSU_STA:8; // 7:0 Setup time, rise edge of PMBUS master clock to start edge. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMSTSETUP_REG { - Uint32 all; - struct PMBTIMSTSETUP_BITS bit; -}; - -struct PMBTIMBIDLE_BITS { // bits description - Uint16 BUSIDLE:10; // 9:0 Determines the Bus Idle Limit - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMBIDLE_REG { - Uint32 all; - struct PMBTIMBIDLE_BITS bit; -}; - -struct PMBTIMLOWTIMOUT_BITS { // bits description - Uint32 CLKLOWTIMOUT:20; // 19:0 Determines the clock low timeout value - Uint16 rsvd1:12; // 31:20 Reserved -}; - -union PMBTIMLOWTIMOUT_REG { - Uint32 all; - struct PMBTIMLOWTIMOUT_BITS bit; -}; - -struct PMBTIMHIGHTIMOUT_BITS { // bits description - Uint16 CLKHIGHTIMOUT:10; // 9:0 Determines the clock high timeout value - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBTIMHIGHTIMOUT_REG { - Uint32 all; - struct PMBTIMHIGHTIMOUT_BITS bit; -}; - -struct PMBUS_REGS { - union PMBMC_REG PMBMC; // PMBUS Master Mode Control Register - Uint32 PMBTXBUF; // PMBUS Transmit Buffer - Uint32 PMBRXBUF; // PMBUS Receive buffer - union PMBACK_REG PMBACK; // PMBUS Acknowledge Register - union PMBSTS_REG PMBSTS; // PMBUS Status Register - union PMBINTM_REG PMBINTM; // PMBUS Interrupt Mask Register - union PMBSC_REG PMBSC; // PMBUS Slave Mode Configuration Register - union PMBHSA_REG PMBHSA; // PMBUS Hold Slave Address Register - union PMBCTRL_REG PMBCTRL; // PMBUS Control Register - union PMBTIMCTL_REG PMBTIMCTL; // PMBUS Timing Control Register - union PMBTIMCLK_REG PMBTIMCLK; // PMBUS Clock Timing Register - union PMBTIMSTSETUP_REG PMBTIMSTSETUP; // PMBUS Start Setup Time Register - union PMBTIMBIDLE_REG PMBTIMBIDLE; // PMBUS Bus Idle Time Register - union PMBTIMLOWTIMOUT_REG PMBTIMLOWTIMOUT; // PMBUS Clock Low Timeout Value Register - union PMBTIMHIGHTIMOUT_REG PMBTIMHIGHTIMOUT; // PMBUS Clock High Timeout Value Register - Uint16 rsvd1[2]; // Reserved -}; - -//--------------------------------------------------------------------------- -// PMBUS External References & Function Declarations: -// -extern volatile struct PMBUS_REGS PmbusaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h deleted file mode 100644 index cbb8c2c..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sci.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sci.h -// -// TITLE: SCI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SCI_H__ -#define __F28004X_SCI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SCI Individual Register Bit Definitions: - -struct SCICCR_BITS { // bits description - Uint16 SCICHAR:3; // 2:0 Character length control - Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control - Uint16 LOOPBKENA:1; // 4 Loop Back enable - Uint16 PARITYENA:1; // 5 Parity enable - Uint16 PARITY:1; // 6 Even or Odd Parity - Uint16 STOPBITS:1; // 7 Number of Stop Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCICCR_REG { - Uint16 all; - struct SCICCR_BITS bit; -}; - -struct SCICTL1_BITS { // bits description - Uint16 RXENA:1; // 0 SCI receiver enable - Uint16 TXENA:1; // 1 SCI transmitter enable - Uint16 SLEEP:1; // 2 SCI sleep - Uint16 TXWAKE:1; // 3 Transmitter wakeup method - Uint16 rsvd1:1; // 4 Reserved - Uint16 SWRESET:1; // 5 Software reset - Uint16 RXERRINTENA:1; // 6 Receive __interrupt enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union SCICTL1_REG { - Uint16 all; - struct SCICTL1_BITS bit; -}; - -struct SCIHBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIHBAUD_REG { - Uint16 all; - struct SCIHBAUD_BITS bit; -}; - -struct SCILBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCILBAUD_REG { - Uint16 all; - struct SCILBAUD_BITS bit; -}; - -struct SCICTL2_BITS { // bits description - Uint16 TXINTENA:1; // 0 Transmit __interrupt enable - Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable - Uint16 rsvd1:4; // 5:2 Reserved - Uint16 TXEMPTY:1; // 6 Transmitter empty flag - Uint16 TXRDY:1; // 7 Transmitter ready flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCICTL2_REG { - Uint16 all; - struct SCICTL2_BITS bit; -}; - -struct SCIRXST_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag - Uint16 PE:1; // 2 Parity error flag - Uint16 OE:1; // 3 Overrun error flag - Uint16 FE:1; // 4 Framing error flag - Uint16 BRKDT:1; // 5 Break-detect flag - Uint16 RXRDY:1; // 6 Receiver ready flag - Uint16 RXERROR:1; // 7 Receiver error flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCIRXST_REG { - Uint16 all; - struct SCIRXST_BITS bit; -}; - -struct SCIRXEMU_BITS { // bits description - Uint16 ERXDT:8; // 7:0 Receive emulation buffer data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIRXEMU_REG { - Uint16 all; - struct SCIRXEMU_BITS bit; -}; - -struct SCIRXBUF_BITS { // bits description - Uint16 SAR:8; // 7:0 Receive Character bits - Uint16 rsvd1:6; // 13:8 Reserved - Uint16 SCIFFPE:1; // 14 Receiver error flag - Uint16 SCIFFFE:1; // 15 Receiver error flag -}; - -union SCIRXBUF_REG { - Uint16 all; - struct SCIRXBUF_BITS bit; -}; - -struct SCITXBUF_BITS { // bits description - Uint16 TXDT:8; // 7:0 Transmit data buffer - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCITXBUF_REG { - Uint16 all; - struct SCITXBUF_BITS bit; -}; - -struct SCIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Interrupt level - Uint16 TXFFIENA:1; // 5 Interrupt enable - Uint16 TXFFINTCLR:1; // 6 Clear INT flag - Uint16 TXFFINT:1; // 7 INT flag - Uint16 TXFFST:5; // 12:8 FIFO status - Uint16 TXFIFORESET:1; // 13 FIFO reset - Uint16 SCIFFENA:1; // 14 Enhancement enable - Uint16 SCIRST:1; // 15 SCI reset rx/tx channels -}; - -union SCIFFTX_REG { - Uint16 all; - struct SCIFFTX_BITS bit; -}; - -struct SCIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Interrupt level - Uint16 RXFFIENA:1; // 5 Interrupt enable - Uint16 RXFFINTCLR:1; // 6 Clear INT flag - Uint16 RXFFINT:1; // 7 INT flag - Uint16 RXFFST:5; // 12:8 FIFO status - Uint16 RXFIFORESET:1; // 13 FIFO reset - Uint16 RXFFOVRCLR:1; // 14 Clear overflow - Uint16 RXFFOVF:1; // 15 FIFO overflow -}; - -union SCIFFRX_REG { - Uint16 all; - struct SCIFFRX_BITS bit; -}; - -struct SCIFFCT_BITS { // bits description - Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay - Uint16 rsvd1:5; // 12:8 Reserved - Uint16 CDC:1; // 13 Auto baud mode enable - Uint16 ABDCLR:1; // 14 Auto baud clear - Uint16 ABD:1; // 15 Auto baud detect -}; - -union SCIFFCT_REG { - Uint16 all; - struct SCIFFCT_BITS bit; -}; - -struct SCIPRI_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 FREESOFT:2; // 4:3 Emulation modes - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 rsvd3:8; // 15:8 Reserved -}; - -union SCIPRI_REG { - Uint16 all; - struct SCIPRI_BITS bit; -}; - -struct SCI_REGS { - union SCICCR_REG SCICCR; // Communications control register - union SCICTL1_REG SCICTL1; // Control register 1 - union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register - union SCILBAUD_REG SCILBAUD; // Baud rate (low) register - union SCICTL2_REG SCICTL2; // Control register 2 - union SCIRXST_REG SCIRXST; // Receive status register - union SCIRXEMU_REG SCIRXEMU; // Receive emulation buffer register - union SCIRXBUF_REG SCIRXBUF; // Receive data buffer - Uint16 rsvd1; // Reserved - union SCITXBUF_REG SCITXBUF; // Transmit data buffer - union SCIFFTX_REG SCIFFTX; // FIFO transmit register - union SCIFFRX_REG SCIFFRX; // FIFO Receive register - union SCIFFCT_REG SCIFFCT; // FIFO control register - Uint16 rsvd2[2]; // Reserved - union SCIPRI_REG SCIPRI; // SCI Priority control -}; - -//--------------------------------------------------------------------------- -// SCI External References & Function Declarations: -// -extern volatile struct SCI_REGS SciaRegs; -extern volatile struct SCI_REGS ScibRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h deleted file mode 100644 index 340903e..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sdfm.h +++ /dev/null @@ -1,797 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sdfm.h -// -// TITLE: SDFM Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SDFM_H__ -#define __F28004X_SDFM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SDFM Individual Register Bit Definitions: - -struct SDIFLG_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 - Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 - Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 - Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 - Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 - Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 - Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 - Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 SDFFOVF1:1; // 16 FIFO Overflow Flag for Ch1. - Uint16 SDFFOVF2:1; // 17 FIFO Overflow Flag for Ch2 - Uint16 SDFFOVF3:1; // 18 FIFO Overflow Flag for Ch3 - Uint16 SDFFOVF4:1; // 19 FIFO Overflow Flag for Ch4 - Uint16 SDFFINT1:1; // 20 SDFIFO interrupt for Ch1 - Uint16 SDFFINT2:1; // 21 SDFIFO interrupt for Ch2 - Uint16 SDFFINT3:1; // 22 SDFIFO interrupt for Ch3 - Uint16 SDFFINT4:1; // 23 SDFIFO interrupt for Ch4 - Uint16 rsvd1:7; // 30:24 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLG_REG { - Uint32 all; - struct SDIFLG_BITS bit; -}; - -struct SDIFLGCLR_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 - Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 - Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 - Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 - Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 - Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 - Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 - Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 SDFFOVF1:1; // 16 SDFIFO overflow clear Ch1 - Uint16 SDFFOVF2:1; // 17 SDFIFO overflow clear Ch2 - Uint16 SDFFOVF3:1; // 18 SDFIFO overflow clear Ch3 - Uint16 SDFFOVF4:1; // 19 SDFIFO overflow clear Ch4 - Uint16 SDFFINT1:1; // 20 SDFIFO Interrupt flag-clear bit for Ch1 - Uint16 SDFFINT2:1; // 21 SDFIFO Interrupt flag-clear bit for Ch2 - Uint16 SDFFINT3:1; // 22 SDFIFO Interrupt flag-clear bit for Ch3 - Uint16 SDFFINT4:1; // 23 SDFIFO Interrupt flag-clear bit for Ch4 - Uint16 rsvd1:7; // 30:24 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLGCLR_REG { - Uint32 all; - struct SDIFLGCLR_BITS bit; -}; - -struct SDCTL_BITS { // bits description - Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 - Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 - Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 - Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 - Uint16 rsvd1:9; // 12:4 Reserved - Uint16 MIE:1; // 13 Master SDy_ERR Interrupt enable - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union SDCTL_REG { - Uint16 all; - struct SDCTL_BITS bit; -}; - -struct SDMFILEN_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:3; // 6:4 Reserved - Uint16 rsvd3:2; // 8:7 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:1; // 10 Reserved - Uint16 MFE:1; // 11 Master Filter Enable. - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:3; // 15:13 Reserved -}; - -union SDMFILEN_REG { - Uint16 all; - struct SDMFILEN_BITS bit; -}; - -struct SDSTATUS_BITS { // bits description - Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 - Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 - Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 - Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:1; // 10 Reserved - Uint16 rsvd5:1; // 11 Reserved - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:1; // 13 Reserved - Uint16 rsvd8:1; // 14 Reserved - Uint16 rsvd9:1; // 15 Reserved -}; - -union SDSTATUS_REG { - Uint16 all; - struct SDSTATUS_BITS bit; -}; - -struct SDCTLPARM1_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM1_REG { - Uint16 all; - struct SDCTLPARM1_BITS bit; -}; - -struct SDDFPARM1_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM1_REG { - Uint16 all; - struct SDDFPARM1_BITS bit; -}; - -struct SDDPARM1_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM1_REG { - Uint16 all; - struct SDDPARM1_BITS bit; -}; - -struct SDCMPH1_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH1_REG { - Uint16 all; - struct SDCMPH1_BITS bit; -}; - -struct SDCMPL1_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL1_REG { - Uint16 all; - struct SDCMPL1_BITS bit; -}; - -struct SDCPARM1_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM1_REG { - Uint16 all; - struct SDCPARM1_BITS bit; -}; - -struct SDDATA1_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA1_REG { - Uint32 all; - struct SDDATA1_BITS bit; -}; - -struct SDDATFIFO1_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO1_REG { - Uint32 all; - struct SDDATFIFO1_BITS bit; -}; - -struct SDCMPHZ1_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ1_REG { - Uint16 all; - struct SDCMPHZ1_BITS bit; -}; - -struct SDFIFOCTL1_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL1_REG { - Uint16 all; - struct SDFIFOCTL1_BITS bit; -}; - -struct SDSYNC1_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC1_REG { - Uint16 all; - struct SDSYNC1_BITS bit; -}; - -struct SDCTLPARM2_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM2_REG { - Uint16 all; - struct SDCTLPARM2_BITS bit; -}; - -struct SDDFPARM2_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM2_REG { - Uint16 all; - struct SDDFPARM2_BITS bit; -}; - -struct SDDPARM2_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM2_REG { - Uint16 all; - struct SDDPARM2_BITS bit; -}; - -struct SDCMPH2_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH2_REG { - Uint16 all; - struct SDCMPH2_BITS bit; -}; - -struct SDCMPL2_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL2_REG { - Uint16 all; - struct SDCMPL2_BITS bit; -}; - -struct SDCPARM2_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM2_REG { - Uint16 all; - struct SDCPARM2_BITS bit; -}; - -struct SDDATA2_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA2_REG { - Uint32 all; - struct SDDATA2_BITS bit; -}; - -struct SDDATFIFO2_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO2_REG { - Uint32 all; - struct SDDATFIFO2_BITS bit; -}; - -struct SDCMPHZ2_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ2_REG { - Uint16 all; - struct SDCMPHZ2_BITS bit; -}; - -struct SDFIFOCTL2_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL2_REG { - Uint16 all; - struct SDFIFOCTL2_BITS bit; -}; - -struct SDSYNC2_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC2_REG { - Uint16 all; - struct SDSYNC2_BITS bit; -}; - -struct SDCTLPARM3_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM3_REG { - Uint16 all; - struct SDCTLPARM3_BITS bit; -}; - -struct SDDFPARM3_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM3_REG { - Uint16 all; - struct SDDFPARM3_BITS bit; -}; - -struct SDDPARM3_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM3_REG { - Uint16 all; - struct SDDPARM3_BITS bit; -}; - -struct SDCMPH3_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH3_REG { - Uint16 all; - struct SDCMPH3_BITS bit; -}; - -struct SDCMPL3_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL3_REG { - Uint16 all; - struct SDCMPL3_BITS bit; -}; - -struct SDCPARM3_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM3_REG { - Uint16 all; - struct SDCPARM3_BITS bit; -}; - -struct SDDATA3_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA3_REG { - Uint32 all; - struct SDDATA3_BITS bit; -}; - -struct SDDATFIFO3_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO3_REG { - Uint32 all; - struct SDDATFIFO3_BITS bit; -}; - -struct SDCMPHZ3_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ3_REG { - Uint16 all; - struct SDCMPHZ3_BITS bit; -}; - -struct SDFIFOCTL3_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL3_REG { - Uint16 all; - struct SDFIFOCTL3_BITS bit; -}; - -struct SDSYNC3_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC3_REG { - Uint16 all; - struct SDSYNC3_BITS bit; -}; - -struct SDCTLPARM4_BITS { // bits description - Uint16 MOD:2; // 1:0 Modulator clocking modes - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM4_REG { - Uint16 all; - struct SDCTLPARM4_BITS bit; -}; - -struct SDDFPARM4_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM4_REG { - Uint16 all; - struct SDDFPARM4_BITS bit; -}; - -struct SDDPARM4_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM4_REG { - Uint16 all; - struct SDDPARM4_BITS bit; -}; - -struct SDCMPH4_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH4_REG { - Uint16 all; - struct SDCMPH4_BITS bit; -}; - -struct SDCMPL4_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL4_REG { - Uint16 all; - struct SDCMPL4_BITS bit; -}; - -struct SDCPARM4_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 - Uint16 IEH:1; // 5 High-level Interrupt enable. - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable - Uint16 rsvd1:2; // 12:11 Reserved - Uint16 CEN:1; // 13 Comparator Enable - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union SDCPARM4_REG { - Uint16 all; - struct SDCPARM4_BITS bit; -}; - -struct SDDATA4_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATA4_REG { - Uint32 all; - struct SDDATA4_BITS bit; -}; - -struct SDDATFIFO4_BITS { // bits description - Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode -}; - -union SDDATFIFO4_REG { - Uint32 all; - struct SDDATFIFO4_BITS bit; -}; - -struct SDCMPHZ4_BITS { // bits description - Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPHZ4_REG { - Uint16 all; - struct SDCMPHZ4_BITS bit; -}; - -struct SDFIFOCTL4_BITS { // bits description - Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level - Uint16 rsvd1:1; // 5 Reserved - Uint16 SDFFST:5; // 10:6 SDFIFO Status - Uint16 rsvd2:1; // 11 Reserved - Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable - Uint16 FFEN:1; // 13 SDFIFO Enable - Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select - Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable -}; - -union SDFIFOCTL4_REG { - Uint16 all; - struct SDFIFOCTL4_BITS bit; -}; - -struct SDSYNC4_BITS { // bits description - Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select - Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable - Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag - Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear - Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable - Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union SDSYNC4_REG { - Uint16 all; - struct SDSYNC4_BITS bit; -}; - -struct SDFM_REGS { - union SDIFLG_REG SDIFLG; // SD Interrupt Flag Register - union SDIFLGCLR_REG SDIFLGCLR; // SD Interrupt Flag Clear Register - union SDCTL_REG SDCTL; // SD Control Register - Uint16 rsvd1; // Reserved - union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable - union SDSTATUS_REG SDSTATUS; // SD Status Register - Uint16 rsvd2[8]; // Reserved - union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 - union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 - union SDDPARM1_REG SDDPARM1; // Data Parameter Register for Ch1 - union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 - union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 - union SDCPARM1_REG SDCPARM1; // Comparator Filter Parameter Register for Ch1 - union SDDATA1_REG SDDATA1; // Data Filter Data Register (16 or 32bit) for Ch1 - union SDDATFIFO1_REG SDDATFIFO1; // Filter Data FIFO Output(32b) for Ch1 - Uint16 SDCDATA1; // Comparator Filter Data Register (16b) for Ch1 - Uint16 rsvd3; // Reserved - union SDCMPHZ1_REG SDCMPHZ1; // High-level (Z) Threshold Register for Ch1 - union SDFIFOCTL1_REG SDFIFOCTL1; // FIFO Control Register for Ch1 - union SDSYNC1_REG SDSYNC1; // SD Filter Sync control for Ch1 - Uint16 rsvd4; // Reserved - union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 - union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 - union SDDPARM2_REG SDDPARM2; // Data Parameter Register for Ch2 - union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 - union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 - union SDCPARM2_REG SDCPARM2; // Comparator Filter Parameter Register for Ch2 - union SDDATA2_REG SDDATA2; // Data Filter Data Register (16 or 32bit) for Ch2 - union SDDATFIFO2_REG SDDATFIFO2; // Filter Data FIFO Output(32b) for Ch2 - Uint16 SDCDATA2; // Comparator Filter Data Register (16b) for Ch2 - Uint16 rsvd5; // Reserved - union SDCMPHZ2_REG SDCMPHZ2; // High-level (Z) Threshold Register for Ch2 - union SDFIFOCTL2_REG SDFIFOCTL2; // FIFO Control Register for Ch2 - union SDSYNC2_REG SDSYNC2; // SD Filter Sync control for Ch2 - Uint16 rsvd6; // Reserved - union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 - union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 - union SDDPARM3_REG SDDPARM3; // Data Parameter Register for Ch3 - union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 - union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 - union SDCPARM3_REG SDCPARM3; // Comparator Filter Parameter Register for Ch3 - union SDDATA3_REG SDDATA3; // Data Filter Data Register (16 or 32bit) for Ch3 - union SDDATFIFO3_REG SDDATFIFO3; // Filter Data FIFO Output(32b) for Ch3 - Uint16 SDCDATA3; // Comparator Filter Data Register (16b) for Ch3 - Uint16 rsvd7; // Reserved - union SDCMPHZ3_REG SDCMPHZ3; // High-level (Z) Threshold Register for Ch3 - union SDFIFOCTL3_REG SDFIFOCTL3; // FIFO Control Register for Ch3 - union SDSYNC3_REG SDSYNC3; // SD Filter Sync control for Ch3 - Uint16 rsvd8; // Reserved - union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 - union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 - union SDDPARM4_REG SDDPARM4; // Data Parameter Register for Ch4 - union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 - union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 - union SDCPARM4_REG SDCPARM4; // Comparator Filter Parameter Register for Ch4 - union SDDATA4_REG SDDATA4; // Data Filter Data Register (16 or 32bit) for Ch4 - union SDDATFIFO4_REG SDDATFIFO4; // Filter Data FIFO Output(32b) for Ch4 - Uint16 SDCDATA4; // Comparator Filter Data Register (16b) for Ch4 - Uint16 rsvd9; // Reserved - union SDCMPHZ4_REG SDCMPHZ4; // High-level (Z) Threshold Register for Ch4 - union SDFIFOCTL4_REG SDFIFOCTL4; // FIFO Control Register for Ch4 - union SDSYNC4_REG SDSYNC4; // SD Filter Sync control for Ch4 - Uint16 rsvd10[33]; // Reserved -}; - -//--------------------------------------------------------------------------- -// SDFM External References & Function Declarations: -// -extern volatile struct SDFM_REGS Sdfm1Regs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h deleted file mode 100644 index 27721ed..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_spi.h +++ /dev/null @@ -1,193 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_spi.h -// -// TITLE: SPI Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SPI_H__ -#define __F28004X_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SPI Individual Register Bit Definitions: - -struct SPICCR_BITS { // bits description - Uint16 SPICHAR:4; // 3:0 Character Length Control - Uint16 SPILBK:1; // 4 SPI Loopback - Uint16 HS_MODE:1; // 5 High Speed mode control - Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity - Uint16 SPISWRESET:1; // 7 SPI Software Reset - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPICCR_REG { - Uint16 all; - struct SPICCR_BITS bit; -}; - -struct SPICTL_BITS { // bits description - Uint16 SPIINTENA:1; // 0 SPI Interupt Enable - Uint16 TALK:1; // 1 Master/Slave Transmit Enable - Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control - Uint16 CLK_PHASE:1; // 3 SPI Clock Phase - Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union SPICTL_REG { - Uint16 all; - struct SPICTL_BITS bit; -}; - -struct SPISTS_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag - Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag - Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SPISTS_REG { - Uint16 all; - struct SPISTS_BITS bit; -}; - -struct SPIBRR_BITS { // bits description - Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union SPIBRR_REG { - Uint16 all; - struct SPIBRR_BITS bit; -}; - -struct SPIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear - Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFIFO:1; // 13 TXFIFO Reset - Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable - Uint16 SPIRST:1; // 15 SPI Reset -}; - -union SPIFFTX_REG { - Uint16 all; - struct SPIFFTX_BITS bit; -}; - -struct SPIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear - Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFIFORESET:1; // 13 RXFIFO Reset - Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear - Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag -}; - -union SPIFFRX_REG { - Uint16 all; - struct SPIFFRX_BITS bit; -}; - -struct SPIFFCT_BITS { // bits description - Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPIFFCT_REG { - Uint16 all; - struct SPIFFCT_BITS bit; -}; - -struct SPIPRI_BITS { // bits description - Uint16 TRIWIRE:1; // 0 3-wire mode select bit - Uint16 STEINV:1; // 1 SPISTE inversion bit - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 FREE:1; // 4 Free emulation mode - Uint16 SOFT:1; // 5 Soft emulation mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:9; // 15:7 Reserved -}; - -union SPIPRI_REG { - Uint16 all; - struct SPIPRI_BITS bit; -}; - -struct SPI_REGS { - union SPICCR_REG SPICCR; // SPI Configuration Control Register - union SPICTL_REG SPICTL; // SPI Operation Control Register - union SPISTS_REG SPISTS; // SPI Status Register - Uint16 rsvd1; // Reserved - union SPIBRR_REG SPIBRR; // SPI Baud Rate Register - Uint16 rsvd2; // Reserved - Uint16 SPIRXEMU; // SPI Emulation Buffer Register - Uint16 SPIRXBUF; // SPI Serial Input Buffer Register - Uint16 SPITXBUF; // SPI Serial Output Buffer Register - Uint16 SPIDAT; // SPI Serial Data Register - union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register - union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register - union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register - Uint16 rsvd3[2]; // Reserved - union SPIPRI_REG SPIPRI; // SPI Priority Control Register -}; - -//--------------------------------------------------------------------------- -// SPI External References & Function Declarations: -// -extern volatile struct SPI_REGS SpiaRegs; -extern volatile struct SPI_REGS SpibRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h deleted file mode 100644 index adbdf64..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_sysctrl.h +++ /dev/null @@ -1,2062 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_sysctrl.h -// -// TITLE: SYSCTRL Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_SYSCTRL_H__ -#define __F28004X_SYSCTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SYSCTRL Individual Register Bit Definitions: - -struct PARTIDL_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 rsvd2:2; // 4:3 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 QUAL:2; // 7:6 Qualification Status - Uint16 PIN_COUNT:3; // 10:8 Device Pin Count - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 INSTASPIN:2; // 14:13 Instaspin feature set - Uint16 rsvd6:1; // 15 Reserved - Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB - Uint16 rsvd7:4; // 27:24 Reserved - Uint16 rsvd8:4; // 31:28 Reserved -}; - -union PARTIDL_REG { - Uint32 all; - struct PARTIDL_BITS bit; -}; - -struct PARTIDH_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:4; // 7:4 Reserved - Uint16 FAMILY:8; // 15:8 Device family - Uint16 PARTNO:8; // 23:16 Device part number - Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID -}; - -union PARTIDH_REG { - Uint32 all; - struct PARTIDH_BITS bit; -}; - -struct REVID_BITS { // bits description - Uint16 REVID:16; // 15:0 Device Revision ID. This is specific to the Device - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union REVID_REG { - Uint32 all; - struct REVID_BITS bit; -}; - -struct FUSEERR_BITS { // bits description - Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status - Uint16 ERR:1; // 5 Efuse Self Test Error Status - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FUSEERR_REG { - Uint32 all; - struct FUSEERR_BITS bit; -}; - -struct SOFTPRES0_BITS { // bits description - Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES0_REG { - Uint32 all; - struct SOFTPRES0_BITS bit; -}; - -struct SOFTPRES2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 software reset bit - Uint16 EPWM2:1; // 1 EPWM2 software reset bit - Uint16 EPWM3:1; // 2 EPWM3 software reset bit - Uint16 EPWM4:1; // 3 EPWM4 software reset bit - Uint16 EPWM5:1; // 4 EPWM5 software reset bit - Uint16 EPWM6:1; // 5 EPWM6 software reset bit - Uint16 EPWM7:1; // 6 EPWM7 software reset bit - Uint16 EPWM8:1; // 7 EPWM8 software reset bit - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union SOFTPRES2_REG { - Uint32 all; - struct SOFTPRES2_BITS bit; -}; - -struct SOFTPRES3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 software reset bit - Uint16 ECAP2:1; // 1 ECAP2 software reset bit - Uint16 ECAP3:1; // 2 ECAP3 software reset bit - Uint16 ECAP4:1; // 3 ECAP4 software reset bit - Uint16 ECAP5:1; // 4 ECAP5 software reset bit - Uint16 ECAP6:1; // 5 ECAP6 software reset bit - Uint16 ECAP7:1; // 6 ECAP7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES3_REG { - Uint32 all; - struct SOFTPRES3_BITS bit; -}; - -struct SOFTPRES4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 software reset bit - Uint16 EQEP2:1; // 1 EQEP2 software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES4_REG { - Uint32 all; - struct SOFTPRES4_BITS bit; -}; - -struct SOFTPRES6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint16 rsvd7:1; // 7 Reserved - Uint16 rsvd8:8; // 15:8 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union SOFTPRES6_REG { - Uint32 all; - struct SOFTPRES6_BITS bit; -}; - -struct SOFTPRES7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A software reset bit - Uint16 SCI_B:1; // 1 SCI_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES7_REG { - Uint32 all; - struct SOFTPRES7_BITS bit; -}; - -struct SOFTPRES8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A software reset bit - Uint16 SPI_B:1; // 1 SPI_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:1; // 16 Reserved - Uint16 rsvd5:1; // 17 Reserved - Uint16 rsvd6:14; // 31:18 Reserved -}; - -union SOFTPRES8_REG { - Uint32 all; - struct SOFTPRES8_BITS bit; -}; - -struct SOFTPRES9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES9_REG { - Uint32 all; - struct SOFTPRES9_BITS bit; -}; - -struct SOFTPRES10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A software reset bit - Uint16 CAN_B:1; // 1 CAN_B software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES10_REG { - Uint32 all; - struct SOFTPRES10_BITS bit; -}; - -struct SOFTPRES13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A software reset bit - Uint16 ADC_B:1; // 1 ADC_B software reset bit - Uint16 ADC_C:1; // 2 ADC_C software reset bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES13_REG { - Uint32 all; - struct SOFTPRES13_BITS bit; -}; - -struct SOFTPRES14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit - Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit - Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit - Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit - Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit - Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit - Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES14_REG { - Uint32 all; - struct SOFTPRES14_BITS bit; -}; - -struct SOFTPRES15_BITS { // bits description - Uint16 PGA1:1; // 0 PGA1 software reset bit - Uint16 PGA2:1; // 1 PGA2 software reset bit - Uint16 PGA3:1; // 2 PGA3 software reset bit - Uint16 PGA4:1; // 3 PGA4 software reset bit - Uint16 PGA5:1; // 4 PGA5 software reset bit - Uint16 PGA6:1; // 5 PGA6 software reset bit - Uint16 PGA7:1; // 6 PGA7 software reset bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES15_REG { - Uint32 all; - struct SOFTPRES15_BITS bit; -}; - -struct SOFTPRES16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit - Uint16 rsvd6:1; // 18 Reserved - Uint16 rsvd7:1; // 19 Reserved - Uint16 rsvd8:12; // 31:20 Reserved -}; - -union SOFTPRES16_REG { - Uint32 all; - struct SOFTPRES16_BITS bit; -}; - -struct SOFTPRES19_BITS { // bits description - Uint16 LIN_A:1; // 0 LIN_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES19_REG { - Uint32 all; - struct SOFTPRES19_BITS bit; -}; - -struct SOFTPRES20_BITS { // bits description - Uint16 PMBUS_A:1; // 0 PMBUS_A software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES20_REG { - Uint32 all; - struct SOFTPRES20_BITS bit; -}; - -struct TAP_STATUS_BITS { // bits description - Uint16 TAP_STATE:16; // 15:0 Present TAP State - Uint16 rsvd1:15; // 30:16 Reserved - Uint16 DCON:1; // 31 Debugger Connect Indication -}; - -union TAP_STATUS_REG { - Uint32 all; - struct TAP_STATUS_BITS bit; -}; - -struct DEV_CFG_REGS { - Uint16 rsvd1[8]; // Reserved - union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number - union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number - union REVID_REG REVID; // Device Revision Number - Uint16 rsvd2[102]; // Reserved - union FUSEERR_REG FUSEERR; // e-Fuse error Status register - Uint16 rsvd3[12]; // Reserved - union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register - Uint16 rsvd4[2]; // Reserved - union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register - union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register - union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register - Uint16 rsvd5[2]; // Reserved - union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register - union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register - union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register - union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register - union SOFTPRES10_REG SOFTPRES10; // Peripheral Software Reset register - Uint16 rsvd6[4]; // Reserved - union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register - union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register - union SOFTPRES15_REG SOFTPRES15; // Peripheral Software Reset register - union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register - Uint16 rsvd7[4]; // Reserved - union SOFTPRES19_REG SOFTPRES19; // Peripheral Software Reset register - union SOFTPRES20_REG SOFTPRES20; // Peripheral Software Reset register - Uint16 rsvd8[132]; // Reserved - union TAP_STATUS_REG TAP_STATUS; // Status of JTAG State machine & Debugger Connect - Uint16 rsvd9[78]; // Reserved -}; - -struct CLKCFGLOCK1_BITS { // bits description - Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register - Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register - Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register - Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register - Uint16 rsvd3:1; // 7 Reserved - Uint16 rsvd4:1; // 8 Reserved - Uint16 rsvd5:1; // 9 Reserved - Uint16 rsvd6:1; // 10 Reserved - Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register - Uint16 rsvd7:1; // 12 Reserved - Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register - Uint16 rsvd8:1; // 14 Reserved - Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register - Uint16 XTALCR:1; // 16 Lock bit for XTALCR register - Uint16 rsvd9:15; // 31:17 Reserved -}; - -union CLKCFGLOCK1_REG { - Uint32 all; - struct CLKCFGLOCK1_BITS bit; -}; - -struct CLKSRCCTL1_BITS { // bits description - Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit - Uint16 rsvd2:1; // 4 Reserved - Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit - Uint16 rsvd3:10; // 15:6 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CLKSRCCTL1_REG { - Uint32 all; - struct CLKSRCCTL1_BITS bit; -}; - -struct CLKSRCCTL2_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit - Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union CLKSRCCTL2_REG { - Uint32 all; - struct CLKSRCCTL2_BITS bit; -}; - -struct CLKSRCCTL3_BITS { // bits description - Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLKSRCCTL3_REG { - Uint32 all; - struct CLKSRCCTL3_BITS bit; -}; - -struct SYSPLLCTL1_BITS { // bits description - Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit - Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLCTL1_REG { - Uint32 all; - struct SYSPLLCTL1_BITS bit; -}; - -struct SYSPLLMULT_BITS { // bits description - Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier - Uint16 rsvd1:1; // 7 Reserved - Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 ODIV:3; // 18:16 Output Clock Divider - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 rsvd4:6; // 29:24 Reserved - Uint16 rsvd5:2; // 31:30 Reserved -}; - -union SYSPLLMULT_REG { - Uint32 all; - struct SYSPLLMULT_BITS bit; -}; - -struct SYSPLLSTS_BITS { // bits description - Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit - Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLSTS_REG { - Uint32 all; - struct SYSPLLSTS_BITS bit; -}; - -struct SYSCLKDIVSEL_BITS { // bits description - Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSCLKDIVSEL_REG { - Uint32 all; - struct SYSCLKDIVSEL_BITS bit; -}; - -struct XCLKOUTDIVSEL_BITS { // bits description - Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XCLKOUTDIVSEL_REG { - Uint32 all; - struct XCLKOUTDIVSEL_BITS bit; -}; - -struct LOSPCP_BITS { // bits description - Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOSPCP_REG { - Uint32 all; - struct LOSPCP_BITS bit; -}; - -struct MCDCR_BITS { // bits description - Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit - Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit - Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit - Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MCDCR_REG { - Uint32 all; - struct MCDCR_BITS bit; -}; - -struct X1CNT_BITS { // bits description - Uint16 X1CNT:10; // 9:0 X1 Counter - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 CLR:1; // 16 X1 Counter Clear - Uint16 rsvd2:15; // 31:17 Reserved -}; - -union X1CNT_REG { - Uint32 all; - struct X1CNT_BITS bit; -}; - -struct XTALCR_BITS { // bits description - Uint16 OSCOFF:1; // 0 XTAL Oscillator powered-down - Uint16 SE:1; // 1 XTAL Oscilator in Single-Ended mode - Uint16 SWH:1; // 2 XTAL Oscilator Operation range - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XTALCR_REG { - Uint32 all; - struct XTALCR_BITS bit; -}; - -struct CLK_CFG_REGS { - Uint16 rsvd1[2]; // Reserved - union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers - Uint16 rsvd2[4]; // Reserved - union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 - union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 - union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 - union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 - Uint16 rsvd3[4]; // Reserved - union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register - union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register - Uint16 rsvd4[10]; // Reserved - union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register - Uint16 rsvd5[4]; // Reserved - union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register - Uint16 rsvd6[2]; // Reserved - union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar - union MCDCR_REG MCDCR; // Missing Clock Detect Control Register - union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock - union XTALCR_REG XTALCR; // XTAL Control Register - Uint16 rsvd7[2]; // Reserved -}; - -struct CPUSYSLOCK1_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register - Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register - Uint16 rsvd3:1; // 4 Reserved - Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register - Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register - Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register - Uint16 rsvd4:1; // 8 Reserved - Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register - Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register - Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register - Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register - Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register - Uint16 rsvd5:1; // 14 Reserved - Uint16 rsvd6:1; // 15 Reserved - Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register - Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register - Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register - Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register - Uint16 rsvd7:1; // 20 Reserved - Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register - Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register - Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register - Uint16 PCLKCR17:1; // 24 Lock bit for PCLKCR17 Register - Uint16 PCLKCR18:1; // 25 Lock bit for PCLKCR18 Register - Uint16 PCLKCR19:1; // 26 Lock bit for PCLKCR19 Register - Uint16 PCLKCR20:1; // 27 Lock bit for PCLKCR20 Register - Uint16 PCLKCR21:1; // 28 Lock bit for PCLKCR21 Register - Uint16 rsvd8:1; // 29 Reserved - Uint16 rsvd9:1; // 30 Reserved - Uint16 rsvd10:1; // 31 Reserved -}; - -union CPUSYSLOCK1_REG { - Uint32 all; - struct CPUSYSLOCK1_BITS bit; -}; - -struct PIEVERRADDR_BITS { // bits description - Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PIEVERRADDR_REG { - Uint32 all; - struct PIEVERRADDR_BITS bit; -}; - -struct PCLKCR0_BITS { // bits description - Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 DMA:1; // 2 DMA Clock Enable bit - Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit - Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit - Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit - Uint16 rsvd3:1; // 17 Reserved - Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync - Uint16 rsvd4:1; // 19 Reserved - Uint16 rsvd5:12; // 31:20 Reserved -}; - -union PCLKCR0_REG { - Uint32 all; - struct PCLKCR0_BITS bit; -}; - -struct PCLKCR2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit - Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit - Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit - Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit - Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit - Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit - Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit - Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union PCLKCR2_REG { - Uint32 all; - struct PCLKCR2_BITS bit; -}; - -struct PCLKCR3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit - Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit - Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit - Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit - Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit - Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit - Uint16 ECAP7:1; // 6 ECAP7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR3_REG { - Uint32 all; - struct PCLKCR3_BITS bit; -}; - -struct PCLKCR4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit - Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR4_REG { - Uint32 all; - struct PCLKCR4_BITS bit; -}; - -struct PCLKCR6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint16 rsvd7:1; // 7 Reserved - Uint16 rsvd8:8; // 15:8 Reserved - Uint16 rsvd9:16; // 31:16 Reserved -}; - -union PCLKCR6_REG { - Uint32 all; - struct PCLKCR6_BITS bit; -}; - -struct PCLKCR7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit - Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR7_REG { - Uint32 all; - struct PCLKCR7_BITS bit; -}; - -struct PCLKCR8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit - Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:1; // 16 Reserved - Uint16 rsvd5:1; // 17 Reserved - Uint16 rsvd6:14; // 31:18 Reserved -}; - -union PCLKCR8_REG { - Uint32 all; - struct PCLKCR8_BITS bit; -}; - -struct PCLKCR9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR9_REG { - Uint32 all; - struct PCLKCR9_BITS bit; -}; - -struct PCLKCR10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit - Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR10_REG { - Uint32 all; - struct PCLKCR10_BITS bit; -}; - -struct PCLKCR13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit - Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit - Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR13_REG { - Uint32 all; - struct PCLKCR13_BITS bit; -}; - -struct PCLKCR14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit - Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit - Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit - Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit - Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit - Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit - Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR14_REG { - Uint32 all; - struct PCLKCR14_BITS bit; -}; - -struct PCLKCR15_BITS { // bits description - Uint16 PGA1:1; // 0 PGA1 Clock Enable bit - Uint16 PGA2:1; // 1 PGA2 Clock Enable bit - Uint16 PGA3:1; // 2 PGA3 Clock Enable bit - Uint16 PGA4:1; // 3 PGA4 Clock Enable bit - Uint16 PGA5:1; // 4 PGA5 Clock Enable bit - Uint16 PGA6:1; // 5 PGA6 Clock Enable bit - Uint16 PGA7:1; // 6 PGA7 Clock Enable bit - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR15_REG { - Uint32 all; - struct PCLKCR15_BITS bit; -}; - -struct PCLKCR16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit - Uint16 rsvd6:1; // 18 Reserved - Uint16 rsvd7:1; // 19 Reserved - Uint16 rsvd8:12; // 31:20 Reserved -}; - -union PCLKCR16_REG { - Uint32 all; - struct PCLKCR16_BITS bit; -}; - -struct PCLKCR19_BITS { // bits description - Uint16 LIN_A:1; // 0 LIN_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:12; // 15:4 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union PCLKCR19_REG { - Uint32 all; - struct PCLKCR19_BITS bit; -}; - -struct PCLKCR20_BITS { // bits description - Uint16 PMBUS_A:1; // 0 PMBUS_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR20_REG { - Uint32 all; - struct PCLKCR20_BITS bit; -}; - -struct PCLKCR21_BITS { // bits description - Uint16 DCC_0:1; // 0 DCC_0 Clock Enable Bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR21_REG { - Uint32 all; - struct PCLKCR21_BITS bit; -}; - -struct LPMCR_BITS { // bits description - Uint16 LPM:2; // 1:0 Low Power Mode setting - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 rsvd2:7; // 14:8 Reserved - Uint16 rsvd3:1; // 15 Reserved - Uint16 rsvd4:2; // 17:16 Reserved - Uint16 rsvd5:13; // 30:18 Reserved - Uint16 rsvd6:1; // 31 Reserved -}; - -union LPMCR_REG { - Uint32 all; - struct LPMCR_BITS bit; -}; - -struct GPIOLPMSEL0_BITS { // bits description - Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup - Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup - Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup - Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup - Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup - Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup - Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup - Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup - Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup - Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup - Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup - Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup - Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup - Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup - Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup - Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup - Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup - Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup - Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup - Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup - Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup - Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup - Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup - Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup - Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup - Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup - Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup - Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup - Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup - Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup - Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup - Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup -}; - -union GPIOLPMSEL0_REG { - Uint32 all; - struct GPIOLPMSEL0_BITS bit; -}; - -struct GPIOLPMSEL1_BITS { // bits description - Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup - Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup - Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup - Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup - Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup - Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup - Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup - Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup - Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup - Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup - Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup - Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup - Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup - Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup - Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup - Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup - Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup - Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup - Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup - Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup - Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup - Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup - Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup - Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup - Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup - Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup - Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup - Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup - Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup - Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup - Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup - Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup -}; - -union GPIOLPMSEL1_REG { - Uint32 all; - struct GPIOLPMSEL1_BITS bit; -}; - -struct TMR2CLKCTL_BITS { // bits description - Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit - Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TMR2CLKCTL_REG { - Uint32 all; - struct TMR2CLKCTL_BITS bit; -}; - -struct RESCCLR_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd5:7; // 15:9 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union RESCCLR_REG { - Uint32 all; - struct RESCCLR_BITS bit; -}; - -struct RESC_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd5:7; // 15:9 Reserved - Uint16 rsvd6:14; // 29:16 Reserved - Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status - Uint16 DCON:1; // 31 Debugger conntion status to C28x -}; - -union RESC_REG { - Uint32 all; - struct RESC_BITS bit; -}; - -struct CPU_SYS_REGS { - union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers - Uint16 rsvd1[8]; // Reserved - union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register - Uint16 rsvd2[22]; // Reserved - union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers - Uint16 rsvd3[2]; // Reserved - union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers - union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers - union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers - Uint16 rsvd4[2]; // Reserved - union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers - union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers - union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers - union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers - union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers - Uint16 rsvd5[4]; // Reserved - union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers - union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers - union PCLKCR15_REG PCLKCR15; // Peripheral Clock Gating Registers - union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers - Uint16 rsvd6[4]; // Reserved - union PCLKCR19_REG PCLKCR19; // Peripheral Clock Gating Registers - union PCLKCR20_REG PCLKCR20; // Peripheral Clock Gating Registers - union PCLKCR21_REG PCLKCR21; // Peripheral Clock Gating Registers - Uint16 rsvd7[40]; // Reserved - union LPMCR_REG LPMCR; // LPM Control Register - union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers - union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers - union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register - union RESCCLR_REG RESCCLR; // Reset Cause Clear Register - union RESC_REG RESC; // Reset Cause register -}; - -struct SCSR_BITS { // bits description - Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit - Uint16 WDENINT:1; // 1 WD Interrupt Enable - Uint16 WDINTS:1; // 2 WD Interrupt Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union SCSR_REG { - Uint16 all; - struct SCSR_BITS bit; -}; - -struct WDCNTR_BITS { // bits description - Uint16 WDCNTR:8; // 7:0 WD Counter - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDCNTR_REG { - Uint16 all; - struct WDCNTR_BITS bit; -}; - -struct WDKEY_BITS { // bits description - Uint16 WDKEY:8; // 7:0 Key to pet the watchdog timer. - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDKEY_REG { - Uint16 all; - struct WDKEY_BITS bit; -}; - -struct WDCR_BITS { // bits description - Uint16 WDPS:3; // 2:0 WD Clock Prescalar - Uint16 WDCHK:3; // 5:3 WD Check Bits - Uint16 WDDIS:1; // 6 WD Disable - Uint16 rsvd1:1; // 7 Reserved - Uint16 WDPRECLKDIV:4; // 11:8 WD Pre Clock Divider - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union WDCR_REG { - Uint16 all; - struct WDCR_BITS bit; -}; - -struct WDWCR_BITS { // bits description - Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:7; // 15:9 Reserved -}; - -union WDWCR_REG { - Uint16 all; - struct WDWCR_BITS bit; -}; - -struct WD_REGS { - Uint16 rsvd1[34]; // Reserved - union SCSR_REG SCSR; // System Control & Status Register - union WDCNTR_REG WDCNTR; // Watchdog Counter Register - Uint16 rsvd2; // Reserved - union WDKEY_REG WDKEY; // Watchdog Reset Key Register - Uint16 rsvd3[3]; // Reserved - union WDCR_REG WDCR; // Watchdog Control Register - union WDWCR_REG WDWCR; // Watchdog Windowed Control Register -}; - -struct CLA1TASKSRCSELLOCK_BITS { // bits description - Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit - Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLA1TASKSRCSELLOCK_REG { - Uint32 all; - struct CLA1TASKSRCSELLOCK_BITS bit; -}; - -struct DMACHSRCSELLOCK_BITS { // bits description - Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit - Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DMACHSRCSELLOCK_REG { - Uint32 all; - struct DMACHSRCSELLOCK_BITS bit; -}; - -struct CLA1TASKSRCSEL1_BITS { // bits description - Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 - Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 - Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 - Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 -}; - -union CLA1TASKSRCSEL1_REG { - Uint32 all; - struct CLA1TASKSRCSEL1_BITS bit; -}; - -struct CLA1TASKSRCSEL2_BITS { // bits description - Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 - Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 - Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 - Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 -}; - -union CLA1TASKSRCSEL2_REG { - Uint32 all; - struct CLA1TASKSRCSEL2_BITS bit; -}; - -struct DMACHSRCSEL1_BITS { // bits description - Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA - Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA - Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA - Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA -}; - -union DMACHSRCSEL1_REG { - Uint32 all; - struct DMACHSRCSEL1_BITS bit; -}; - -struct DMACHSRCSEL2_BITS { // bits description - Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA - Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union DMACHSRCSEL2_REG { - Uint32 all; - struct DMACHSRCSEL2_BITS bit; -}; - -struct DMA_CLA_SRC_SEL_REGS { - union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register - Uint16 rsvd1[2]; // Reserved - union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register - union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 - union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 - Uint16 rsvd2[12]; // Reserved - union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 - union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 -}; - -struct ADCA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCA_AC_REG { - Uint32 all; - struct ADCA_AC_BITS bit; -}; - -struct ADCB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCB_AC_REG { - Uint32 all; - struct ADCB_AC_BITS bit; -}; - -struct ADCC_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ADCC_AC_REG { - Uint32 all; - struct ADCC_AC_BITS bit; -}; - -struct CMPSS1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS1_AC_REG { - Uint32 all; - struct CMPSS1_AC_BITS bit; -}; - -struct CMPSS2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS2_AC_REG { - Uint32 all; - struct CMPSS2_AC_BITS bit; -}; - -struct CMPSS3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS3_AC_REG { - Uint32 all; - struct CMPSS3_AC_BITS bit; -}; - -struct CMPSS4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS4_AC_REG { - Uint32 all; - struct CMPSS4_AC_BITS bit; -}; - -struct CMPSS5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS5_AC_REG { - Uint32 all; - struct CMPSS5_AC_BITS bit; -}; - -struct CMPSS6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS6_AC_REG { - Uint32 all; - struct CMPSS6_AC_BITS bit; -}; - -struct CMPSS7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CMPSS7_AC_REG { - Uint32 all; - struct CMPSS7_AC_BITS bit; -}; - -struct DACA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DACA_AC_REG { - Uint32 all; - struct DACA_AC_BITS bit; -}; - -struct DACB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DACB_AC_REG { - Uint32 all; - struct DACB_AC_BITS bit; -}; - -struct PGA1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA1_AC_REG { - Uint32 all; - struct PGA1_AC_BITS bit; -}; - -struct PGA2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA2_AC_REG { - Uint32 all; - struct PGA2_AC_BITS bit; -}; - -struct PGA3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA3_AC_REG { - Uint32 all; - struct PGA3_AC_BITS bit; -}; - -struct PGA4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA4_AC_REG { - Uint32 all; - struct PGA4_AC_BITS bit; -}; - -struct PGA5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA5_AC_REG { - Uint32 all; - struct PGA5_AC_BITS bit; -}; - -struct PGA6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA6_AC_REG { - Uint32 all; - struct PGA6_AC_BITS bit; -}; - -struct PGA7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PGA7_AC_REG { - Uint32 all; - struct PGA7_AC_BITS bit; -}; - -struct EPWM1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM1_AC_REG { - Uint32 all; - struct EPWM1_AC_BITS bit; -}; - -struct EPWM2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM2_AC_REG { - Uint32 all; - struct EPWM2_AC_BITS bit; -}; - -struct EPWM3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM3_AC_REG { - Uint32 all; - struct EPWM3_AC_BITS bit; -}; - -struct EPWM4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM4_AC_REG { - Uint32 all; - struct EPWM4_AC_BITS bit; -}; - -struct EPWM5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM5_AC_REG { - Uint32 all; - struct EPWM5_AC_BITS bit; -}; - -struct EPWM6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM6_AC_REG { - Uint32 all; - struct EPWM6_AC_BITS bit; -}; - -struct EPWM7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM7_AC_REG { - Uint32 all; - struct EPWM7_AC_BITS bit; -}; - -struct EPWM8_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EPWM8_AC_REG { - Uint32 all; - struct EPWM8_AC_BITS bit; -}; - -struct EQEP1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EQEP1_AC_REG { - Uint32 all; - struct EQEP1_AC_BITS bit; -}; - -struct EQEP2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EQEP2_AC_REG { - Uint32 all; - struct EQEP2_AC_BITS bit; -}; - -struct ECAP1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP1_AC_REG { - Uint32 all; - struct ECAP1_AC_BITS bit; -}; - -struct ECAP2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP2_AC_REG { - Uint32 all; - struct ECAP2_AC_BITS bit; -}; - -struct ECAP3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP3_AC_REG { - Uint32 all; - struct ECAP3_AC_BITS bit; -}; - -struct ECAP4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP4_AC_REG { - Uint32 all; - struct ECAP4_AC_BITS bit; -}; - -struct ECAP5_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP5_AC_REG { - Uint32 all; - struct ECAP5_AC_BITS bit; -}; - -struct ECAP6_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP6_AC_REG { - Uint32 all; - struct ECAP6_AC_BITS bit; -}; - -struct ECAP7_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECAP7_AC_REG { - Uint32 all; - struct ECAP7_AC_BITS bit; -}; - -struct SDFM1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SDFM1_AC_REG { - Uint32 all; - struct SDFM1_AC_BITS bit; -}; - -struct CLB1_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB1_AC_REG { - Uint32 all; - struct CLB1_AC_BITS bit; -}; - -struct CLB2_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB2_AC_REG { - Uint32 all; - struct CLB2_AC_BITS bit; -}; - -struct CLB3_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB3_AC_REG { - Uint32 all; - struct CLB3_AC_BITS bit; -}; - -struct CLB4_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLB4_AC_REG { - Uint32 all; - struct CLB4_AC_BITS bit; -}; - -struct CLA1PROMCRC_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLA1PROMCRC_AC_REG { - Uint32 all; - struct CLA1PROMCRC_AC_BITS bit; -}; - -struct SPIA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SPIA_AC_REG { - Uint32 all; - struct SPIA_AC_BITS bit; -}; - -struct SPIB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SPIB_AC_REG { - Uint32 all; - struct SPIB_AC_BITS bit; -}; - -struct PMBUS_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PMBUS_A_AC_REG { - Uint32 all; - struct PMBUS_A_AC_BITS bit; -}; - -struct LIN_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LIN_A_AC_REG { - Uint32 all; - struct LIN_A_AC_BITS bit; -}; - -struct DCANA_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DCANA_AC_REG { - Uint32 all; - struct DCANA_AC_BITS bit; -}; - -struct DCANB_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DCANB_AC_REG { - Uint32 all; - struct DCANB_AC_BITS bit; -}; - -struct FSIATX_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FSIATX_AC_REG { - Uint32 all; - struct FSIATX_AC_BITS bit; -}; - -struct FSIARX_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FSIARX_AC_REG { - Uint32 all; - struct FSIARX_AC_BITS bit; -}; - -struct HRPWM_A_AC_BITS { // bits description - Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral - Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral - Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union HRPWM_A_AC_REG { - Uint32 all; - struct HRPWM_A_AC_BITS bit; -}; - -struct PERIPH_AC_LOCK_BITS { // bits description - Uint16 LOCK_AC_WR:1; // 0 Lock control for Access control registers write. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PERIPH_AC_LOCK_REG { - Uint32 all; - struct PERIPH_AC_LOCK_BITS bit; -}; - -struct PERIPH_AC_REGS { - union ADCA_AC_REG ADCA_AC; // ADCA Master Access Control Register - union ADCB_AC_REG ADCB_AC; // ADCB Master Access Control Register - union ADCC_AC_REG ADCC_AC; // ADCC Master Access Control Register - Uint16 rsvd1[10]; // Reserved - union CMPSS1_AC_REG CMPSS1_AC; // CMPSS1 Master Access Control Register - union CMPSS2_AC_REG CMPSS2_AC; // CMPSS2 Master Access Control Register - union CMPSS3_AC_REG CMPSS3_AC; // CMPSS3 Master Access Control Register - union CMPSS4_AC_REG CMPSS4_AC; // CMPSS4 Master Access Control Register - union CMPSS5_AC_REG CMPSS5_AC; // CMPSS5 Master Access Control Register - union CMPSS6_AC_REG CMPSS6_AC; // CMPSS6 Master Access Control Register - union CMPSS7_AC_REG CMPSS7_AC; // CMPSS7 Master Access Control Register - Uint16 rsvd2[10]; // Reserved - union DACA_AC_REG DACA_AC; // DACA Master Access Control Register - union DACB_AC_REG DACB_AC; // DACB Master Access Control Register - Uint16 rsvd3[12]; // Reserved - union PGA1_AC_REG PGA1_AC; // PGAA Master Access Control Register - union PGA2_AC_REG PGA2_AC; // PGAB Master Access Control Register - union PGA3_AC_REG PGA3_AC; // PGAC Master Access Control Register - union PGA4_AC_REG PGA4_AC; // PGAD Master Access Control Register - union PGA5_AC_REG PGA5_AC; // PGAE Master Access Control Register - union PGA6_AC_REG PGA6_AC; // PGAF Master Access Control Register - union PGA7_AC_REG PGA7_AC; // PGAG Master Access Control Register - Uint16 rsvd4[2]; // Reserved - union EPWM1_AC_REG EPWM1_AC; // EPWM1 Master Access Control Register - union EPWM2_AC_REG EPWM2_AC; // EPWM2 Master Access Control Register - union EPWM3_AC_REG EPWM3_AC; // EPWM3 Master Access Control Register - union EPWM4_AC_REG EPWM4_AC; // EPWM4 Master Access Control Register - union EPWM5_AC_REG EPWM5_AC; // EPWM5 Master Access Control Register - union EPWM6_AC_REG EPWM6_AC; // EPWM6 Master Access Control Register - union EPWM7_AC_REG EPWM7_AC; // EPWM7 Master Access Control Register - union EPWM8_AC_REG EPWM8_AC; // EPWM8 Master Access Control Register - Uint16 rsvd5[24]; // Reserved - union EQEP1_AC_REG EQEP1_AC; // EQEP1 Master Access Control Register - union EQEP2_AC_REG EQEP2_AC; // EQEP2 Master Access Control Register - Uint16 rsvd6[12]; // Reserved - union ECAP1_AC_REG ECAP1_AC; // ECAP1 Master Access Control Register - union ECAP2_AC_REG ECAP2_AC; // ECAP2 Master Access Control Register - union ECAP3_AC_REG ECAP3_AC; // ECAP3 Master Access Control Register - union ECAP4_AC_REG ECAP4_AC; // ECAP4 Master Access Control Register - union ECAP5_AC_REG ECAP5_AC; // ECAP5 Master Access Control Register - union ECAP6_AC_REG ECAP6_AC; // ECAP6 Master Access Control Register - union ECAP7_AC_REG ECAP7_AC; // ECAP7 Master Access Control Register - Uint16 rsvd7[26]; // Reserved - union SDFM1_AC_REG SDFM1_AC; // SDFM1 Master Access Control Register - Uint16 rsvd8[6]; // Reserved - union CLB1_AC_REG CLB1_AC; // CLB1 Master Access Control Register - union CLB2_AC_REG CLB2_AC; // CLB2 Master Access Control Register - union CLB3_AC_REG CLB3_AC; // CLB3 Master Access Control Register - union CLB4_AC_REG CLB4_AC; // CLB4 Master Access Control Register - Uint16 rsvd9[8]; // Reserved - union CLA1PROMCRC_AC_REG CLA1PROMCRC_AC; // CLA1PROMCRC Master Access Control Register - Uint16 rsvd10[78]; // Reserved - union SPIA_AC_REG SPIA_AC; // SPIA Master Access Control Register - union SPIB_AC_REG SPIB_AC; // SPIB Master Access Control Register - Uint16 rsvd11[28]; // Reserved - union PMBUS_A_AC_REG PMBUS_A_AC; // PMBUSA Master Access Control Register - Uint16 rsvd12[6]; // Reserved - union LIN_A_AC_REG LIN_A_AC; // LINA Master Access Control Register - Uint16 rsvd13[6]; // Reserved - union DCANA_AC_REG DCANA_AC; // DCANA Master Access Control Register - union DCANB_AC_REG DCANB_AC; // DCANB Master Access Control Register - Uint16 rsvd14[20]; // Reserved - union FSIATX_AC_REG FSIATX_AC; // FSIA Master Access Control Register - union FSIARX_AC_REG FSIARX_AC; // FSIB Master Access Control Register - Uint16 rsvd15[78]; // Reserved - union HRPWM_A_AC_REG HRPWM_A_AC; // HRPWM Master Access Control Register - Uint16 rsvd16[82]; // Reserved - union PERIPH_AC_LOCK_REG PERIPH_AC_LOCK; // Lock Register to stop Write access to peripheral Access register. -}; - -struct SYNCSELECT_BITS { // bits description - Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 - Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 - Uint16 rsvd1:3; // 8:6 Reserved - Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 - Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 - Uint32 ECAP6SYNCIN:3; // 17:15 Selects Sync Input Source for ECAP6 - Uint16 rsvd2:9; // 26:18 Reserved - Uint16 SYNCOUT:2; // 28:27 Select Syncout Source - Uint16 EPWM1SYNCIN:3; // 31:29 Selects Sync Input Source for EPWM1 -}; - -union SYNCSELECT_REG { - Uint32 all; - struct SYNCSELECT_BITS bit; -}; - -struct ADCSOCOUTSELECT_BITS { // bits description - Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAOn - Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAOn - Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAOn - Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAOn - Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAOn - Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAOn - Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAOn - Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAOn - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:4; // 15:12 Reserved - Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBOn - Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBOn - Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBOn - Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBOn - Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBOn - Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBOn - Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBOn - Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBOn - Uint16 rsvd6:1; // 24 Reserved - Uint16 rsvd7:1; // 25 Reserved - Uint16 rsvd8:1; // 26 Reserved - Uint16 rsvd9:1; // 27 Reserved - Uint16 rsvd10:4; // 31:28 Reserved -}; - -union ADCSOCOUTSELECT_REG { - Uint32 all; - struct ADCSOCOUTSELECT_BITS bit; -}; - -struct SYNCSOCLOCK_BITS { // bits description - Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit - Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYNCSOCLOCK_REG { - Uint32 all; - struct SYNCSOCLOCK_BITS bit; -}; - -struct SYNC_SOC_REGS { - union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register - union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADCSOC Select Register - union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register -}; - -//--------------------------------------------------------------------------- -// SYSCTRL External References & Function Declarations: -// -extern volatile struct WD_REGS WdRegs; -extern volatile struct SYNC_SOC_REGS SyncSocRegs; -extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; -extern volatile struct DEV_CFG_REGS DevCfgRegs; -extern volatile struct CLK_CFG_REGS ClkCfgRegs; -extern volatile struct CPU_SYS_REGS CpuSysRegs; -extern volatile struct PERIPH_AC_REGS SysPeriphAcRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h deleted file mode 100644 index e3cdff0..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_xbar.h +++ /dev/null @@ -1,372 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_xbar.h -// -// TITLE: XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_XBAR_H__ -#define __F28004X_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XBAR Individual Register Bit Definitions: - -struct XBARFLG1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal -}; - -union XBARFLG1_REG { - Uint32 all; - struct XBARFLG1_BITS bit; -}; - -struct XBARFLG2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal - Uint16 ADCSOCA:1; // 6 Input Flag for ADCSOCA Signal - Uint16 ADCSOCB:1; // 7 Input Flag for ADCSOCB Signal - Uint16 INPUT7:1; // 8 Input Flag for INPUT7 Signal - Uint16 INPUT8:1; // 9 Input Flag for INPUT8 Signal - Uint16 INPUT9:1; // 10 Input Flag for INPUT9 Signal - Uint16 INPUT10:1; // 11 Input Flag for INPUT10\ Signal - Uint16 INPUT11:1; // 12 Input Flag for INPUT11 Signal - Uint16 INPUT12:1; // 13 Input Flag for INPUT12 Signal - Uint16 INPUT13:1; // 14 Input Flag for INPUT13 Signal - Uint16 INPUT14:1; // 15 Input Flag for INPUT14 Signal - Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal -}; - -union XBARFLG2_REG { - Uint32 all; - struct XBARFLG2_BITS bit; -}; - -struct XBARFLG3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 rsvd4:1; // 6 Reserved - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:1; // 17 Reserved - Uint16 rsvd8:1; // 18 Reserved - Uint16 rsvd9:1; // 19 Reserved - Uint16 rsvd10:1; // 20 Reserved - Uint16 rsvd11:1; // 21 Reserved - Uint16 rsvd12:1; // 22 Reserved - Uint16 ECAP7_OUT:1; // 23 Input Flag for ECAP7.OUT Signal - Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag for SD1FLT1.COMPZ Signal - Uint16 SD1FLT1_DRINT:1; // 25 Input Flag for SD1FLT1.DRINT Signal - Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag for SD1FLT2.COMPZ Signal - Uint16 SD1FLT2_DRINT:1; // 27 Input Flag for SD1FLT2.DRINT Signal - Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag for SD1FLT3.COMPZ Signal - Uint16 SD1FLT3_DRINT:1; // 29 Input Flag for SD1FLT3.DRINT Signal - Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag for SD1FLT4.COMPZ Signal - Uint16 SD1FLT4_DRINT:1; // 31 Input Flag for SD1FLT4.DRINT Signal -}; - -union XBARFLG3_REG { - Uint32 all; - struct XBARFLG3_BITS bit; -}; - -struct XBARFLG4_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:8; // 15:8 Reserved - Uint16 rsvd10:1; // 16 Reserved - Uint16 rsvd11:1; // 17 Reserved - Uint16 rsvd12:1; // 18 Reserved - Uint16 rsvd13:1; // 19 Reserved - Uint16 rsvd14:1; // 20 Reserved - Uint16 rsvd15:1; // 21 Reserved - Uint16 rsvd16:1; // 22 Reserved - Uint16 rsvd17:1; // 23 Reserved - Uint16 rsvd18:7; // 30:24 Reserved - Uint16 CLAHALT:1; // 31 Input Flag for CLAHALT Signal -}; - -union XBARFLG4_REG { - Uint32 all; - struct XBARFLG4_BITS bit; -}; - -struct XBARCLR1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal -}; - -union XBARCLR1_REG { - Uint32 all; - struct XBARCLR1_BITS bit; -}; - -struct XBARCLR2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag Clear for INPUT6 Signal - Uint16 ADCSOCA:1; // 6 Input Flag Clear for ADCSOCA Signal - Uint16 ADCSOCB:1; // 7 Input Flag Clear for ADCSOCB Signal - Uint16 INPUT7:1; // 8 Input Flag Clear for INPUT7 Signal - Uint16 INPUT8:1; // 9 Input Flag Clear for INPUT8 Signal - Uint16 INPUT9:1; // 10 Input Flag Clear for INPUT9 Signal - Uint16 INPUT10:1; // 11 Input Flag Clear for INPUT10 Signal - Uint16 INPUT11:1; // 12 Input Flag Clear for INPUT11 Signal - Uint16 INPUT12:1; // 13 Input Flag Clear for INPUT12 Signal - Uint16 INPUT13:1; // 14 Input Flag Clear for INPUT13 Signal - Uint16 INPUT14:1; // 15 Input Flag Clear for INPUT14 Signal - Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal -}; - -union XBARCLR2_REG { - Uint32 all; - struct XBARCLR2_BITS bit; -}; - -struct XBARCLR3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 rsvd4:1; // 6 Reserved - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:1; // 17 Reserved - Uint16 rsvd8:1; // 18 Reserved - Uint16 rsvd9:1; // 19 Reserved - Uint16 rsvd10:1; // 20 Reserved - Uint16 rsvd11:1; // 21 Reserved - Uint16 rsvd12:1; // 22 Reserved - Uint16 ECAP7_OUT:1; // 23 Input Flag clear for ECAP7.OUT Signal - Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag clear for SD1FLT1.COMPZ Signal - Uint16 SD1FLT1_DRINT:1; // 25 Input Flag clear for SD1FLT1.DRINT Signal - Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag clear for SD1FLT2.COMPZ Signal - Uint16 SD1FLT2_DRINT:1; // 27 Input Flag clear for SD1FLT2.DRINT Signal - Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag clear for SD1FLT3.COMPZ Signal - Uint16 SD1FLT3_DRINT:1; // 29 Input Flag clear for SD1FLT3.DRINT Signal - Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag clear for SD1FLT4.COMPZ Signal - Uint16 SD1FLT4_DRINT:1; // 31 Input Flag clear for SD1FLT4.DRINT Signal -}; - -union XBARCLR3_REG { - Uint32 all; - struct XBARCLR3_BITS bit; -}; - -struct XBARCLR4_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:8; // 15:8 Reserved - Uint16 rsvd10:1; // 16 Reserved - Uint16 rsvd11:1; // 17 Reserved - Uint16 rsvd12:1; // 18 Reserved - Uint16 rsvd13:1; // 19 Reserved - Uint16 rsvd14:1; // 20 Reserved - Uint16 rsvd15:1; // 21 Reserved - Uint16 rsvd16:1; // 22 Reserved - Uint16 rsvd17:1; // 23 Reserved - Uint16 rsvd18:7; // 30:24 Reserved - Uint16 CLAHALT:1; // 31 Input Flag clear for CLAHALT Signal -}; - -union XBARCLR4_REG { - Uint32 all; - struct XBARCLR4_BITS bit; -}; - -struct XBAR_REGS { - union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 - union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 - union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 - union XBARFLG4_REG XBARFLG4; // X-Bar Input Flag Register 4 - union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 - union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 - union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 - union XBARCLR4_REG XBARCLR4; // X-Bar Input Flag Clear Register 4 - Uint16 rsvd1[16]; // Reserved -}; - -//--------------------------------------------------------------------------- -// XBAR External References & Function Declarations: -// -extern volatile struct XBAR_REGS XbarRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h b/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h deleted file mode 100644 index 15fd43b..0000000 --- a/els-f280049c/device_support_f28004x/headers/include/f28004x_xint.h +++ /dev/null @@ -1,138 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_xint.h -// -// TITLE: XINT Register Definitions. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F28004X_XINT_H__ -#define __F28004X_XINT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XINT Individual Register Bit Definitions: - -struct XINT1CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT1 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT1 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT1CR_REG { - Uint16 all; - struct XINT1CR_BITS bit; -}; - -struct XINT2CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT2 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT2 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT2CR_REG { - Uint16 all; - struct XINT2CR_BITS bit; -}; - -struct XINT3CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT3 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT3 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT3CR_REG { - Uint16 all; - struct XINT3CR_BITS bit; -}; - -struct XINT4CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT4 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT4 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT4CR_REG { - Uint16 all; - struct XINT4CR_BITS bit; -}; - -struct XINT5CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT5 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT5 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT5CR_REG { - Uint16 all; - struct XINT5CR_BITS bit; -}; - -struct XINT_REGS { - union XINT1CR_REG XINT1CR; // XINT1 configuration register - union XINT2CR_REG XINT2CR; // XINT2 configuration register - union XINT3CR_REG XINT3CR; // XINT3 configuration register - union XINT4CR_REG XINT4CR; // XINT4 configuration register - union XINT5CR_REG XINT5CR; // XINT5 configuration register - Uint16 rsvd1[3]; // Reserved - Uint16 XINT1CTR; // XINT1 counter register - Uint16 XINT2CTR; // XINT2 counter register - Uint16 XINT3CTR; // XINT3 counter register -}; - -//--------------------------------------------------------------------------- -// XINT External References & Function Declarations: -// -extern volatile struct XINT_REGS XintRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c b/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c deleted file mode 100644 index 7c862ee..0000000 --- a/els-f280049c/device_support_f28004x/headers/source/f28004x_globalvariabledefs.c +++ /dev/null @@ -1,861 +0,0 @@ -//########################################################################### -// -// FILE: f28004x_globalvariabledefs.c -// -// TITLE: F28004x Global Variables and Data Section Pragmas. -// -//########################################################################### -// $TI Release: F28004x Support Library v1.05.00.00 $ -// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ -// $Copyright: -// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#include "f28004x_device.h" // F28004x Headerfile Include File - -//--------------------------------------------------------------------------- -// Define Global Peripheral Variables: -// -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaResultFile") -#else -#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcaResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbResultFile") -#else -#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcbResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccResultFile") -#else -#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdccResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaRegsFile") -#else -#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); -#endif -volatile struct ADC_REGS AdcaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbRegsFile") -#else -#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); -#endif -volatile struct ADC_REGS AdcbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccRegsFile") -#else -#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); -#endif -volatile struct ADC_REGS AdccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AnalogSubsysRegsFile") -#else -#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); -#endif -volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanaRegsFile") -#else -#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); -#endif -volatile struct CAN_REGS CanaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanbRegsFile") -#else -#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); -#endif -volatile struct CAN_REGS CanbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1RegsFile") -#else -#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); -#endif -volatile struct CLA_REGS Cla1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1SoftIntRegsFile") -#else -#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); -#endif -volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClaPromCrc0RegsFile") -#else -#pragma DATA_SECTION(ClaPromCrc0Regs,"ClaPromCrc0RegsFile"); -#endif -volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss1RegsFile") -#else -#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss2RegsFile") -#else -#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss3RegsFile") -#else -#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss4RegsFile") -#else -#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss5RegsFile") -#else -#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss6RegsFile") -#else -#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss7RegsFile") -#else -#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer0RegsFile") -#else -#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer1RegsFile") -#else -#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer2RegsFile") -#else -#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacaRegsFile") -#else -#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); -#endif -volatile struct DAC_REGS DacaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacbRegsFile") -#else -#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); -#endif -volatile struct DAC_REGS DacbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Dcc0RegsFile") -#else -#pragma DATA_SECTION(Dcc0Regs,"Dcc0RegsFile"); -#endif -volatile struct DCC_REGS Dcc0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank0Z1RegsFile") -#else -#pragma DATA_SECTION(DcsmBank0Z1Regs,"DcsmBank0Z1RegsFile"); -#endif -volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank0Z2RegsFile") -#else -#pragma DATA_SECTION(DcsmBank0Z2Regs,"DcsmBank0Z2RegsFile"); -#endif -volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank1Z1RegsFile") -#else -#pragma DATA_SECTION(DcsmBank1Z1Regs,"DcsmBank1Z1RegsFile"); -#endif -volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmBank1Z2RegsFile") -#else -#pragma DATA_SECTION(DcsmBank1Z2Regs,"DcsmBank1Z2RegsFile"); -#endif -volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmCommonRegsFile") -#else -#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); -#endif -volatile struct DCSM_COMMON_REGS DcsmCommonRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaRegsFile") -#else -#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); -#endif -volatile struct DMA_REGS DmaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap1RegsFile") -#else -#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); -#endif -volatile struct ECAP_REGS ECap1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap2RegsFile") -#else -#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); -#endif -volatile struct ECAP_REGS ECap2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap3RegsFile") -#else -#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); -#endif -volatile struct ECAP_REGS ECap3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap4RegsFile") -#else -#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); -#endif -volatile struct ECAP_REGS ECap4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap5RegsFile") -#else -#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); -#endif -volatile struct ECAP_REGS ECap5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap6RegsFile") -#else -#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); -#endif -volatile struct ECAP_REGS ECap6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap7RegsFile") -#else -#pragma DATA_SECTION(ECap7Regs,"ECap7RegsFile"); -#endif -volatile struct ECAP_REGS ECap7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga1RegsFile") -#else -#pragma DATA_SECTION(Pga1Regs,"Pga1RegsFile"); -#endif -volatile struct PGA_REGS Pga1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga2RegsFile") -#else -#pragma DATA_SECTION(Pga2Regs,"Pga2RegsFile"); -#endif -volatile struct PGA_REGS Pga2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga3RegsFile") -#else -#pragma DATA_SECTION(Pga3Regs,"Pga3RegsFile"); -#endif -volatile struct PGA_REGS Pga3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga4RegsFile") -#else -#pragma DATA_SECTION(Pga4Regs,"Pga4RegsFile"); -#endif -volatile struct PGA_REGS Pga4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga5RegsFile") -#else -#pragma DATA_SECTION(Pga5Regs,"Pga5RegsFile"); -#endif -volatile struct PGA_REGS Pga5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga6RegsFile") -#else -#pragma DATA_SECTION(Pga6Regs,"Pga6RegsFile"); -#endif -volatile struct PGA_REGS Pga6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Pga7RegsFile") -#else -#pragma DATA_SECTION(Pga7Regs,"Pga7RegsFile"); -#endif -volatile struct PGA_REGS Pga7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm1RegsFile") -#else -#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); -#endif -volatile struct EPWM_REGS EPwm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm2RegsFile") -#else -#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); -#endif -volatile struct EPWM_REGS EPwm2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm3RegsFile") -#else -#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); -#endif -volatile struct EPWM_REGS EPwm3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm4RegsFile") -#else -#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); -#endif -volatile struct EPWM_REGS EPwm4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm5RegsFile") -#else -#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); -#endif -volatile struct EPWM_REGS EPwm5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm6RegsFile") -#else -#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); -#endif -volatile struct EPWM_REGS EPwm6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm7RegsFile") -#else -#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); -#endif -volatile struct EPWM_REGS EPwm7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm8RegsFile") -#else -#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); -#endif -volatile struct EPWM_REGS EPwm8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwmXbarRegsFile") -#else -#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); -#endif -volatile struct EPWM_XBAR_REGS EPwmXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep1RegsFile") -#else -#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); -#endif -volatile struct EQEP_REGS EQep1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep2RegsFile") -#else -#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); -#endif -volatile struct EQEP_REGS EQep2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0CtrlRegsFile") -#else -#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); -#endif -volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0EccRegsFile") -#else -#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); -#endif -volatile struct FLASH_ECC_REGS Flash0EccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("FsiTxaRegsFile") -#else -#pragma DATA_SECTION(FsiTxaRegs,"FsiTxaRegsFile"); -#endif -volatile struct FSI_TX_REGS FsiTxaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("FsiRxaRegsFile") -#else -#pragma DATA_SECTION(FsiRxaRegs,"FsiRxaRegsFile"); -#endif -volatile struct FSI_RX_REGS FsiRxaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioCtrlRegsFile") -#else -#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); -#endif -volatile struct GPIO_CTRL_REGS GpioCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioDataRegsFile") -#else -#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); -#endif -volatile struct GPIO_DATA_REGS GpioDataRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XbarRegsFile") -#else -#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); -#endif -volatile struct XBAR_REGS XbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("I2caRegsFile") -#else -#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); -#endif -volatile struct I2C_REGS I2caRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("InputXbarRegsFile") -#else -#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); -#endif -volatile struct INPUT_XBAR_REGS InputXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("LinaRegsFile") -#else -#pragma DATA_SECTION(LinaRegs,"LinaRegsFile"); -#endif -volatile struct LIN_REGS LinaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("LinbRegsFile") -#else -#pragma DATA_SECTION(LinbRegs,"LinbRegsFile"); -#endif -volatile struct LIN_REGS LinbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemCfgRegsFile") -#else -#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); -#endif -volatile struct MEM_CFG_REGS MemCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AccessProtectionRegsFile") -#else -#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); -#endif -volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemoryErrorRegsFile") -#else -#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); -#endif -volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("NmiIntruptRegsFile") -#else -#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); -#endif -volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("OutputXbarRegsFile") -#else -#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); -#endif -volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieCtrlRegsFile") -#else -#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); -#endif -volatile struct PIE_CTRL_REGS PieCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieVectTableFile") -#else -#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); -#endif -volatile struct PIE_VECT_TABLE PieVectTable; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PmbusaRegsFile") -#else -#pragma DATA_SECTION(PmbusaRegs,"PmbusaRegsFile"); -#endif -volatile struct PMBUS_REGS PmbusaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SciaRegsFile") -#else -#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); -#endif -volatile struct SCI_REGS SciaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ScibRegsFile") -#else -#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); -#endif -volatile struct SCI_REGS ScibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Sdfm1RegsFile") -#else -#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); -#endif -volatile struct SDFM_REGS Sdfm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpiaRegsFile") -#else -#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); -#endif -volatile struct SPI_REGS SpiaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpibRegsFile") -#else -#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); -#endif -volatile struct SPI_REGS SpibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("WdRegsFile") -#else -#pragma DATA_SECTION(WdRegs,"WdRegsFile"); -#endif -volatile struct WD_REGS WdRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaClaSrcSelRegsFile") -#else -#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); -#endif -volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DevCfgRegsFile") -#else -#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); -#endif -volatile struct DEV_CFG_REGS DevCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClkCfgRegsFile") -#else -#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); -#endif -volatile struct CLK_CFG_REGS ClkCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuSysRegsFile") -#else -#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); -#endif -volatile struct CPU_SYS_REGS CpuSysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SysPeriphAcRegsFile") -#else -#pragma DATA_SECTION(SysPeriphAcRegs,"SysPeriphAcRegsFile"); -#endif -volatile struct PERIPH_AC_REGS SysPeriphAcRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugGlobalRegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugGlobalRegs,"EnhancedDebugGlobalRegsFile"); -#endif -volatile struct ERAD_GLOBAL_REGS EnhancedDebugGlobalRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP1RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP1Regs,"EnhancedDebugHWBP1RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP2RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP2Regs,"EnhancedDebugHWBP2RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP3RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP3Regs,"EnhancedDebugHWBP3RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP4RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP4Regs,"EnhancedDebugHWBP4RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP5RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP5Regs,"EnhancedDebugHWBP5RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP6RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP6Regs,"EnhancedDebugHWBP6RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP7RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP7Regs,"EnhancedDebugHWBP7RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugHWBP8RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugHWBP8Regs,"EnhancedDebugHWBP8RegsFile"); -#endif -volatile struct ERAD_HWBP_REGS EnhancedDebugHWBP8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter1RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter1Regs,"EnhancedDebugCounter1RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter2RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter2Regs,"EnhancedDebugCounter2RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter3RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter3Regs,"EnhancedDebugCounter3RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EnhancedDebugCounter4RegsFile") -#else -#pragma DATA_SECTION(EnhancedDebugCounter4Regs,"EnhancedDebugCounter4RegsFile"); -#endif -volatile struct ERAD_COUNTER_REGS EnhancedDebugCounter4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SyncSocRegsFile") -#else -#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); -#endif -volatile struct SYNC_SOC_REGS SyncSocRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XintRegsFile") -#else -#pragma DATA_SECTION(XintRegs,"XintRegsFile"); -#endif -volatile struct XINT_REGS XintRegs; - - - -//=========================================================================== -// End of file. -//=========================================================================== - From f7cb10673be35069fe501224fd6b620a79bf9571 Mon Sep 17 00:00:00 2001 From: Kent VanderVelden Date: Tue, 13 Oct 2020 11:50:50 -0500 Subject: [PATCH 3/9] Need placeholder for linked cware2000 files --- els-f280049c/.launches/els-f280049c.launch | 16 ++++++++++++++++ els-f280049c/device/placeholder.txt | 0 2 files changed, 16 insertions(+) create mode 100644 els-f280049c/.launches/els-f280049c.launch create mode 100644 els-f280049c/device/placeholder.txt diff --git a/els-f280049c/.launches/els-f280049c.launch b/els-f280049c/.launches/els-f280049c.launch new file mode 100644 index 0000000..45e287b --- /dev/null +++ b/els-f280049c/.launches/els-f280049c.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/els-f280049c/device/placeholder.txt b/els-f280049c/device/placeholder.txt new file mode 100644 index 0000000..e69de29 From 6f5162b66a649a16c256c1f83b2b68d345cbe574 Mon Sep 17 00:00:00 2001 From: Kent VanderVelden Date: Tue, 13 Oct 2020 12:35:26 -0500 Subject: [PATCH 4/9] Add debug symbols to Debug, and remove from Release --- els-f280049c/.cproject | 11 +++++++++-- els-f280049c/.launches/els-f280049c.launch | 12 ++++++++++++ .../.settings/com.ti.ccstudio.project.core.prefs | 4 ++++ 3 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 els-f280049c/.settings/com.ti.ccstudio.project.core.prefs diff --git a/els-f280049c/.cproject b/els-f280049c/.cproject index 5116c05..b46fcc9 100644 --- a/els-f280049c/.cproject +++ b/els-f280049c/.cproject @@ -42,7 +42,7 @@ -