From 7acc5b9eea89e74e27529684b98e03c3a13e509c Mon Sep 17 00:00:00 2001 From: Comma Device Date: Wed, 4 Sep 2024 12:21:05 +0000 Subject: [PATCH] the DMA from SAI1 -> SAI4 doesn't work yet --- board/boards/cuatro.h | 4 ++-- board/drivers/sound.h | 35 ++++++++++++++++++++++++++++++----- board/main.c | 5 ++++- board/stm32h7/peripherals.h | 1 + 4 files changed, 37 insertions(+), 8 deletions(-) diff --git a/board/boards/cuatro.h b/board/boards/cuatro.h index fd797799b2..123ab5e95b 100644 --- a/board/boards/cuatro.h +++ b/board/boards/cuatro.h @@ -139,8 +139,8 @@ void cuatro_init(void) { set_gpio_alternate(GPIOC, 0, GPIO_AF8_SAI4); // SAI4_FS_B set_gpio_alternate(GPIOD, 11, GPIO_AF10_SAI4); // SAI4_SD_A set_gpio_alternate(GPIOE, 3, GPIO_AF8_SAI4); // SAI4_SD_B - set_gpio_alternate(GPIOE, 4, GPIO_AF10_SAI4); // SAI4_D2 - set_gpio_alternate(GPIOE, 5, GPIO_AF10_SAI4); // SAI4_CK2 + set_gpio_alternate(GPIOE, 4, GPIO_AF2_SAI1); // SAI1_D2 + set_gpio_alternate(GPIOE, 5, GPIO_AF2_SAI1); // SAI1_CK2 set_gpio_alternate(GPIOE, 6, GPIO_AF10_SAI4); // SAI4_MCLK_B sound_init(); } diff --git a/board/drivers/sound.h b/board/drivers/sound.h index 57f5d9aef4..1afb69f0a6 100644 --- a/board/drivers/sound.h +++ b/board/drivers/sound.h @@ -24,8 +24,15 @@ void BDMA_Channel0_IRQ_Handler(void) { DMA1_Stream1->CR |= DMA_SxCR_EN; } +void BDMA_Channel1_IRQ_Handler(void) { + BDMA->IFCR |= BDMA_IFCR_CGIF1; // clear flag + + print("mic DMA\n"); +} + void sound_init(void) { REGISTER_INTERRUPT(BDMA_Channel0_IRQn, BDMA_Channel0_IRQ_Handler, 64U, FAULT_INTERRUPT_RATE_SOUND_DMA) + REGISTER_INTERRUPT(BDMA_Channel1_IRQn, BDMA_Channel1_IRQ_Handler, 64U, FAULT_INTERRUPT_RATE_SOUND_DMA) // Init DAC register_set(&DAC1->MCR, 0U, 0xFFFFFFFFU); @@ -48,7 +55,9 @@ void sound_init(void) { TIM7->SR = 0U; TIM7->CR1 |= TIM_CR1_CEN; - register_set(&SAI4->GCR, 0U, SAI_GCR_SYNCIN_Msk | SAI_GCR_SYNCOUT_Msk); + // sync both SAIs + register_set(&SAI4->GCR, (0b10 << SAI_GCR_SYNCOUT_Pos), SAI_GCR_SYNCIN_Msk | SAI_GCR_SYNCOUT_Msk); + register_set(&SAI1->GCR, (3U << SAI_GCR_SYNCIN_Pos), SAI_GCR_SYNCIN_Msk | SAI_GCR_SYNCOUT_Msk); // stereo audio in register_set(&SAI4_Block_B->CR1, SAI_xCR1_DMAEN | (0b00 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b11 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU); @@ -56,14 +65,20 @@ void sound_init(void) { register_set(&SAI4_Block_B->FRCR, (31U << SAI_xFRCR_FRL_Pos), 0x7FFFFU); register_set(&SAI4_Block_B->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague - // mono mic out - register_set(&SAI4->PDMCR, (0b1 << SAI_PDMCR_CKEN2_Pos) | (0b01 << SAI_PDMCR_MICNBR_Pos) | (0b1 << SAI_PDMCR_PDMEN_Pos), 0x331); - register_set(&SAI4_Block_A->CR1, (26U << SAI_xCR1_MCKDIV_Pos) | SAI_xCR1_NODIV | (0b00 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b01 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU); + // mono mic in + register_set(&SAI1->PDMCR, (0b1 << SAI_PDMCR_CKEN2_Pos) | (0b01 << SAI_PDMCR_MICNBR_Pos) | (0b1 << SAI_PDMCR_PDMEN_Pos), 0x331); + register_set(&SAI1_Block_A->CR1, SAI_xCR1_DMAEN | (26U << SAI_xCR1_MCKDIV_Pos) | SAI_xCR1_NODIV | (0b00 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b01 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU); + register_set(&SAI1_Block_A->CR2, 0U, 0xFFFBU); + register_set(&SAI1_Block_A->FRCR, (31U << SAI_xFRCR_FRL_Pos), 0x7FFFFU); + register_set(&SAI1_Block_A->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague + + // mono mic out (slave transmitter) + register_set(&SAI4_Block_A->CR1, SAI_xCR1_DMAEN | (0b01 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b10 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU); register_set(&SAI4_Block_A->CR2, 0U, 0xFFFBU); register_set(&SAI4_Block_A->FRCR, (31U << SAI_xFRCR_FRL_Pos), 0x7FFFFU); register_set(&SAI4_Block_A->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague - // init DMA (SAI4_B -> memory, double buffers) + // init sound DMA (SAI4_B -> memory, double buffers) register_set(&BDMA_Channel0->CPAR, (uint32_t) &(SAI4_Block_B->DR), 0xFFFFFFFFU); register_set(&BDMA_Channel0->CM0AR, (uint32_t) rx_buf[0], 0xFFFFFFFFU); register_set(&BDMA_Channel0->CM1AR, (uint32_t) rx_buf[1], 0xFFFFFFFFU); @@ -72,8 +87,18 @@ void sound_init(void) { register_set(&DMAMUX2_Channel0->CCR, 16U, DMAMUX_CxCR_DMAREQ_ID_Msk); // SAI4_B_DMA register_set_bits(&BDMA_Channel0->CCR, BDMA_CCR_EN); + // init mic DMA (SAI1_A -> SAI4_A) + register_set(&BDMA_Channel1->CPAR, (uint32_t) &(SAI1_Block_A->DR), 0xFFFFFFFFU); + register_set(&BDMA_Channel1->CM0AR, (uint32_t) &(SAI4_Block_A->DR), 0xFFFFFFFFU); + BDMA_Channel1->CNDTR = 8U; + register_set(&BDMA_Channel1->CCR, (0b10 << BDMA_CCR_MSIZE_Pos) | (0b10 << BDMA_CCR_PSIZE_Pos), 0xFFFFU); + register_set(&DMAMUX2_Channel1->CCR, 16U, DMAMUX_CxCR_DMAREQ_ID_Msk); // SAI4_A_DMA + register_set_bits(&BDMA_Channel1->CCR, BDMA_CCR_EN); + // enable all initted blocks + register_set_bits(&SAI1_Block_A->CR1, SAI_xCR1_SAIEN); register_set_bits(&SAI4_Block_A->CR1, SAI_xCR1_SAIEN); register_set_bits(&SAI4_Block_B->CR1, SAI_xCR1_SAIEN); NVIC_EnableIRQ(BDMA_Channel0_IRQn); + NVIC_EnableIRQ(BDMA_Channel1_IRQn); } \ No newline at end of file diff --git a/board/main.c b/board/main.c index d267e678b7..14ec9c0b2c 100644 --- a/board/main.c +++ b/board/main.c @@ -172,7 +172,10 @@ static void tick_handler(void) { #ifdef STM32H7 //while((SAI4_Block_A->SR & SAI_xSR_FLVL) != 0U) { - puth4(SAI4_Block_A->DR); print("\n"); + // uint32_t dat = SAI1_Block_A->DR; + // SAI4_Block_A->DR = 0x1234U; + //puth4(dat); print("\n"); + puth(BDMA->ISR); print("\n"); //} // if(rx_buf[0].buf[0] != 0U) { diff --git a/board/stm32h7/peripherals.h b/board/stm32h7/peripherals.h index f0bd727fdf..f7695d24de 100644 --- a/board/stm32h7/peripherals.h +++ b/board/stm32h7/peripherals.h @@ -124,6 +124,7 @@ void peripherals_init(void) { RCC->APB1LENR |= RCC_APB1LENR_DAC12EN; // DAC // Audio + RCC->APB2ENR |= RCC_APB2ENR_SAI1EN; // SAI1 RCC->APB4ENR |= RCC_APB4ENR_SAI4EN; // SAI4 // Timers