From 77d86a4cdb02386e220d045b68c2ee5f75911d0e Mon Sep 17 00:00:00 2001 From: daquintero Date: Mon, 17 Jun 2024 14:50:11 +0200 Subject: [PATCH] not working --- .../02_digital_design_simulation.py | 22 ++++---- .../our_truth_table_module.vcd | 6 +- .../full_flow_demo/full_flow_demo/config.json | 55 +++++++++++++++++++ piel/tools/openlane/defaults.py | 19 +++++-- 4 files changed, 81 insertions(+), 21 deletions(-) create mode 100644 docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/config.json diff --git a/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py b/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py index dccea29a..36d28c88 100644 --- a/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py +++ b/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py @@ -20,12 +20,10 @@ verify_amaranth_truth_table, ) -# + # # Uncomment this if you want to run it for the first time. -# piel.create_empty_piel_project( -# project_name="amaranth_driven_flow", parent_directory="../designs/" -# ) -# - +piel.create_empty_piel_project( + project_name="amaranth_driven_flow", parent_directory="../designs/" +) # We can also automate the `pip` installation of our local module: @@ -82,7 +80,7 @@ generate_verilog_from_amaranth_truth_table( amaranth_module=our_truth_table_module, truth_table=detector_phase_truth_table, - target_file_name="our_truth_table_module.v", + target_file_name="truth_table_module.v", target_directory=".", ) @@ -105,12 +103,12 @@ generate_verilog_from_amaranth_truth_table( amaranth_module=our_truth_table_module, truth_table=detector_phase_truth_table, - target_file_name="our_truth_table_module.v", + target_file_name="truth_table_module.v", target_directory=amaranth_driven_flow_src_folder, ) # ``` -# Verilog file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/our_truth_table_module.v +# Verilog file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/truth_table_module.v # ``` # Another thing we can do is verify that our implemented logic is valid. Creating a simulation is also useful in the future when we simulate our extracted place-and-route netlist in relation to the expected applied logic. @@ -118,12 +116,12 @@ verify_amaranth_truth_table( truth_table_amaranth_module=our_truth_table_module, truth_table=detector_phase_truth_table, - vcd_file_name="our_truth_table_module.vcd", + vcd_file_name="truth_table_module.vcd", target_directory=".", ) # ``` -# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd +# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/02_digital_design_simulation/truth_table_module.vcd # ``` # You can also use the module directory to automatically save the testbench in these functions. @@ -131,12 +129,12 @@ verify_amaranth_truth_table( truth_table_amaranth_module=our_truth_table_module, truth_table=detector_phase_truth_table, - vcd_file_name="our_truth_table_module.vcd", + vcd_file_name="truth_table_module.vcd", target_directory=amaranth_driven_flow, ) # ``` -# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/tb/our_truth_table_module.vcd +# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/tb/truth_table_module.vcd # ``` # You can observe the design directory of the provided `amaranth_driven_flow` folder to verify that the files have been included in the other flow. diff --git a/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd b/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd index 411fcd10..d39de761 100644 --- a/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd +++ b/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd @@ -1,5 +1,5 @@ $comment Generated by Amaranth $end -$date 2024-06-17 13:50:14.247813 $end +$date 2024-06-17 14:23:05.506643 $end $timescale 1 ps $end $scope module bench $end $scope module top $end @@ -14,11 +14,11 @@ b0 ! b0 " $end #1000000 -b1 ! b10 " +b1 ! #2000000 -b10 ! b11 " +b10 ! #3000000 b11 ! #4000000 diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/config.json b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/config.json new file mode 100644 index 00000000..07c1f9f1 --- /dev/null +++ b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/config.json @@ -0,0 +1,55 @@ +{ + "meta": { + "version": 2, + "flow": [ + "Yosys.Synthesis", + "OpenROAD.CheckSDCFiles", + "OpenROAD.Floorplan", + "OpenROAD.TapEndcapInsertion", + "OpenROAD.GeneratePDN", + "OpenROAD.IOPlacement", + "OpenROAD.GlobalPlacement", + "OpenROAD.RepairDesign", + "OpenROAD.DetailedPlacement", + "OpenROAD.GlobalRouting", + "OpenROAD.DetailedRouting", + "OpenROAD.FillInsertion", + "Magic.StreamOut", + "Magic.DRC", + "Checker.MagicDRC", + "Magic.SpiceExtraction", + "Netgen.LVS", + "Checker.LVS" + ] + }, + "DESIGN_NAME": "top", + "VERILOG_FILES": "dir::src/*.v", + "CLOCK_PORT": "clk", + "CLOCK_PERIOD": 100, + "RUN_CTS": "false", + "DIE_AREA": [ + 0, + 0, + 50, + 50 + ], + "FP_PDN_VPITCH": 25, + "FP_PDN_HPITCH": 25, + "FP_PDN_VOFFSET": 5, + "FP_PDN_HOFFSET": 5, + "FP_SIZING": "absolute", + "PDK": "sky130A", + "pdk::sky130A": { + "MAX_FANOUT_CONSTRAINT": 6, + "FP_CORE_UTIL": 40, + "PL_TARGET_DENSITY_PCT": "expr::($FP_CORE_UTIL + 10.0)", + "scl::sky130_fd_sc_hd": { + "CLOCK_PERIOD": 15 + } + }, + "//": "With those two defined, the repair design step should do nothing:", + "RSZ_DONT_TOUCH_RX": "^in$", + "RSZ_DONT_TOUCH_LIST": [ + "out" + ] +} diff --git a/piel/tools/openlane/defaults.py b/piel/tools/openlane/defaults.py index e7c9c88e..5ed74234 100644 --- a/piel/tools/openlane/defaults.py +++ b/piel/tools/openlane/defaults.py @@ -56,28 +56,35 @@ ] }, "DESIGN_NAME": "top", - "PDK": "sky130A", "VERILOG_FILES": "dir::src/*.v", - "CLOCK_PORT": None, - "FP_SIZING": "absolute", + "CLOCK_PORT": "clk", + "CLOCK_PERIOD": 100, + "RUN_CTS": False, "DIE_AREA": [ 0, 0, 50, 50 ], - "PL_TARGET_DENSITY": 0.75, - "FP_PDN_AUTO_ADJUST": None, "FP_PDN_VPITCH": 25, "FP_PDN_HPITCH": 25, "FP_PDN_VOFFSET": 5, "FP_PDN_HOFFSET": 5, + "FP_SIZING": "absolute", + "PDK": "sky130A", + "pdk::sky130A": { + "MAX_FANOUT_CONSTRAINT": 6, + "FP_CORE_UTIL": 40, + "PL_TARGET_DENSITY_PCT": "expr::($FP_CORE_UTIL + 10.0)", + "scl::sky130_fd_sc_hd": { + "CLOCK_PERIOD": 15 + } + }, "//": "With those two defined, the repair design step should do nothing:", "RSZ_DONT_TOUCH_RX": "^in$", "RSZ_DONT_TOUCH_LIST": [ "out" ], - "RUN_LINTER": False, } example_open_lane_configuration = {