|
| 1 | +from __future__ import annotations |
| 2 | + |
| 3 | +import atexit |
| 4 | +import os |
| 5 | +import shutil |
| 6 | +import subprocess |
| 7 | +import sys |
| 8 | +import tempfile |
| 9 | +import textwrap |
| 10 | +from pathlib import Path |
| 11 | + |
| 12 | +import pytest |
| 13 | + |
| 14 | +REPO_ROOT = Path(__file__).resolve().parents[2] |
| 15 | +AMARANTH_REPO = REPO_ROOT / "amaranth" |
| 16 | + |
| 17 | +if str(REPO_ROOT) not in sys.path: |
| 18 | + sys.path.insert(0, str(REPO_ROOT)) |
| 19 | +if str(AMARANTH_REPO) not in sys.path: |
| 20 | + sys.path.insert(0, str(AMARANTH_REPO)) |
| 21 | + |
| 22 | + |
| 23 | +_VERILATOR_RUNTIME_CACHE: dict[int, tuple[Path, Path]] = {} |
| 24 | +CROSS_SIM_CYCLES = int(os.getenv("DAU_BENCH_CYCLES", "5000")) |
| 25 | + |
| 26 | + |
| 27 | +@atexit.register |
| 28 | +def _cleanup_verilator_runtime_cache() -> None: |
| 29 | + for td, _exe in _VERILATOR_RUNTIME_CACHE.values(): |
| 30 | + shutil.rmtree(td, ignore_errors=True) |
| 31 | + |
| 32 | + |
| 33 | +def _make_counter(): |
| 34 | + from amaranth import Elaboratable, Module as AModule, Signal |
| 35 | + |
| 36 | + class Counter(Elaboratable): |
| 37 | + def __init__(self): |
| 38 | + self.en = Signal(1) |
| 39 | + self.count = Signal(32) |
| 40 | + |
| 41 | + def elaborate(self, platform): |
| 42 | + m = AModule() |
| 43 | + with m.If(self.en): |
| 44 | + m.d.sync += self.count.eq(self.count + 1) |
| 45 | + return m |
| 46 | + |
| 47 | + return Counter |
| 48 | + |
| 49 | + |
| 50 | +def _run_dau_sim(cycles: int) -> None: |
| 51 | + from dau_sim.compiler import compile_module |
| 52 | + from dau_sim.frontends import from_amaranth |
| 53 | + |
| 54 | + Counter = _make_counter() |
| 55 | + dut = Counter() |
| 56 | + ir_mod = from_amaranth(dut) |
| 57 | + cm = compile_module(ir_mod) |
| 58 | + cm.run(cycles=cycles, inputs={"en": 1}, trace_signals=["count"], return_traces=False) |
| 59 | + |
| 60 | + |
| 61 | +def _run_amaranth_sim(cycles: int) -> None: |
| 62 | + from amaranth.sim import Simulator, Tick |
| 63 | + |
| 64 | + Counter = _make_counter() |
| 65 | + dut = Counter() |
| 66 | + sim = Simulator(dut) |
| 67 | + sim.add_clock(1e-6) |
| 68 | + |
| 69 | + def proc(): |
| 70 | + yield dut.en.eq(1) |
| 71 | + for _ in range(cycles): |
| 72 | + yield Tick() |
| 73 | + |
| 74 | + sim.add_process(proc) |
| 75 | + sim.run() |
| 76 | + |
| 77 | + |
| 78 | +def _run_amaranth_cxxsim(cycles: int) -> None: |
| 79 | + from amaranth.sim import Simulator, Tick |
| 80 | + |
| 81 | + Counter = _make_counter() |
| 82 | + dut = Counter() |
| 83 | + sim = Simulator(dut, engine="cxxsim") |
| 84 | + |
| 85 | + sim.add_clock(1e-6) |
| 86 | + |
| 87 | + def proc(): |
| 88 | + yield dut.en.eq(1) |
| 89 | + for _ in range(cycles): |
| 90 | + yield Tick() |
| 91 | + |
| 92 | + sim.add_process(proc) |
| 93 | + sim.run() |
| 94 | + |
| 95 | + |
| 96 | +def _compile_verilator_binary(cycles: int, *, persist: bool = False) -> tuple[Path, Path]: |
| 97 | + verilator = shutil.which("verilator") |
| 98 | + if not verilator: |
| 99 | + raise RuntimeError("verilator not found on PATH") |
| 100 | + |
| 101 | + verilog = textwrap.dedent( |
| 102 | + f""" |
| 103 | + `timescale 1ns/1ps |
| 104 | + module counter( |
| 105 | + input wire clk, |
| 106 | + input wire rst, |
| 107 | + input wire en, |
| 108 | + output reg [31:0] count |
| 109 | + ); |
| 110 | + always @(posedge clk) begin |
| 111 | + if (rst) count <= 32'd0; |
| 112 | + else if (en) count <= count + 32'd1; |
| 113 | + end |
| 114 | + endmodule |
| 115 | +
|
| 116 | + module tb; |
| 117 | + reg clk = 0; |
| 118 | + reg rst = 1; |
| 119 | + reg en = 1; |
| 120 | + wire [31:0] count; |
| 121 | + integer i; |
| 122 | +
|
| 123 | + counter dut( |
| 124 | + .clk(clk), |
| 125 | + .rst(rst), |
| 126 | + .en(en), |
| 127 | + .count(count) |
| 128 | + ); |
| 129 | +
|
| 130 | + initial begin |
| 131 | + #1 rst = 0; |
| 132 | + for (i = 0; i < {cycles}; i = i + 1) begin |
| 133 | + #1 clk = 1; |
| 134 | + #1 clk = 0; |
| 135 | + end |
| 136 | + $finish; |
| 137 | + end |
| 138 | + endmodule |
| 139 | + """ |
| 140 | + ) |
| 141 | + |
| 142 | + if persist: |
| 143 | + td = Path(tempfile.mkdtemp(prefix="dau_sim_verilator_rt_")) |
| 144 | + else: |
| 145 | + td = Path(tempfile.mkdtemp(prefix="dau_sim_verilator_")) |
| 146 | + src = td / "tb.v" |
| 147 | + src.write_text(verilog) |
| 148 | + cp = subprocess.run([verilator, "--binary", "--timing", "-Wno-fatal", str(src)], cwd=td, capture_output=True, text=True) |
| 149 | + if cp.returncode != 0: |
| 150 | + shutil.rmtree(td, ignore_errors=True) |
| 151 | + raise RuntimeError("verilator compile failed") |
| 152 | + exe = td / "obj_dir" / "Vtb" |
| 153 | + if not exe.exists(): |
| 154 | + shutil.rmtree(td, ignore_errors=True) |
| 155 | + raise RuntimeError("verilator binary missing") |
| 156 | + return td, exe |
| 157 | + |
| 158 | + |
| 159 | +def _run_verilator_compiled(exe: Path) -> None: |
| 160 | + rp = subprocess.run([str(exe)], cwd=exe.parent.parent, capture_output=True, text=True) |
| 161 | + if rp.returncode != 0: |
| 162 | + raise RuntimeError("verilator run failed") |
| 163 | + |
| 164 | + |
| 165 | +def _run_verilator(cycles: int) -> None: |
| 166 | + td, exe = _compile_verilator_binary(cycles, persist=False) |
| 167 | + try: |
| 168 | + _run_verilator_compiled(exe) |
| 169 | + finally: |
| 170 | + shutil.rmtree(td, ignore_errors=True) |
| 171 | + |
| 172 | + |
| 173 | +def _run_verilator_runtime(cycles: int) -> None: |
| 174 | + if cycles not in _VERILATOR_RUNTIME_CACHE: |
| 175 | + _VERILATOR_RUNTIME_CACHE[cycles] = _compile_verilator_binary(cycles, persist=True) |
| 176 | + _td, exe = _VERILATOR_RUNTIME_CACHE[cycles] |
| 177 | + _run_verilator_compiled(exe) |
| 178 | + |
| 179 | + |
| 180 | +def _prepare_verilator_runtime(cycles: int) -> None: |
| 181 | + if cycles not in _VERILATOR_RUNTIME_CACHE: |
| 182 | + _VERILATOR_RUNTIME_CACHE[cycles] = _compile_verilator_binary(cycles, persist=True) |
| 183 | + |
| 184 | + |
| 185 | +def _ensure_backend_available(backend: str) -> None: |
| 186 | + if backend in {"dau-sim", "amaranth-sim", "cxxsim"}: |
| 187 | + try: |
| 188 | + _make_counter() |
| 189 | + if backend == "cxxsim": |
| 190 | + import inspect |
| 191 | + |
| 192 | + from amaranth.sim import Simulator |
| 193 | + |
| 194 | + if "cxxsim" not in inspect.getsource(Simulator.__init__): |
| 195 | + pytest.skip("cxxsim unavailable: this Amaranth build exposes only pysim") |
| 196 | + except Exception as exc: |
| 197 | + pytest.skip(f"{backend} unavailable: {exc}") |
| 198 | + |
| 199 | + if backend in {"verilator-compile-run", "verilator-runtime"} and shutil.which("verilator") is None: |
| 200 | + pytest.skip("verilator unavailable: not found on PATH") |
| 201 | + |
| 202 | + |
| 203 | +@pytest.mark.parametrize( |
| 204 | + "backend,runner", |
| 205 | + [ |
| 206 | + ("dau-sim", _run_dau_sim), |
| 207 | + ("amaranth-sim", _run_amaranth_sim), |
| 208 | + ("cxxsim", _run_amaranth_cxxsim), |
| 209 | + ("verilator-compile-run", _run_verilator), |
| 210 | + ("verilator-runtime", _run_verilator_runtime), |
| 211 | + ], |
| 212 | +) |
| 213 | +def test_benchmark_cross_simulators(benchmark, backend: str, runner) -> None: |
| 214 | + _ensure_backend_available(backend) |
| 215 | + if backend == "verilator-runtime": |
| 216 | + # Compile once outside the measured region; benchmark only executable runtime. |
| 217 | + _prepare_verilator_runtime(CROSS_SIM_CYCLES) |
| 218 | + benchmark.name = f"cross_simulators.{backend}" |
| 219 | + benchmark(lambda: runner(CROSS_SIM_CYCLES)) |
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