Merge pull request #4 from dau-dev/tkp/amstd

Add regression test for mixed clock edge, add amaranth shim for combined triggers

Author: timkpaine

dau_sim/tests/test_cocotb_backend.py

@@ -956,3 +956,45 @@ async def test_coro():
             assert results == [1, 0]
         finally:
             self._teardown_cocotb()
+
+    def test_timer_and_edge_same_timestep(self):
+        """Timer+edge combination should complete when both happen together."""
+        import cocotb
+
+        engine = self._setup_cocotb(_make_comb_module())
+        try:
+            from cocotb._gpi_triggers import RisingEdge, Timer
+            from cocotb.task import Task
+            from cocotb.triggers import Combine
+
+            result = []
+
+            async def driver():
+                # Schedule a rising edge at the exact same time as Timer(100).
+                await Timer(100, unit="step")
+                cocotb.top.a.value = 1
+
+            async def waiter():
+                await Combine(
+                    Timer(100, unit="step"),
+                    RisingEdge(cocotb.top.a),
+                )
+                result.append(engine._sim_time)
+                engine.stop()
+
+            t1 = Task(driver())
+            t2 = Task(waiter())
+            cocotb._scheduler_inst._schedule_task_internal(t1)
+            cocotb._scheduler_inst._schedule_task_internal(t2)
+            cocotb.handle._start_write_scheduler()
+            cocotb._scheduler_inst._event_loop()
+
+            engine._running = True
+            engine.run(max_steps=100_000)
+
+            cocotb.handle._stop_write_scheduler()
+
+            assert len(result) == 1
+            assert result[0] == 100
+        finally:
+            self._teardown_cocotb()

dau_sim/tests/test_sim_seq.py

@@ -491,6 +491,66 @@ def test_different_rates(self):
         assert slow_vals[-1] == 5, f"Expected slow_count=5, got {slow_vals[-1]}"
 
 
+def _make_mixed_edge_single_clock() -> Module:
+    """Two counters sharing one clock, one posedge and one negedge."""
+    return Module(
+        name="mixed_edge",
+        ports=(
+            Port(Signal("clk", Shape(1)), PortDirection.INPUT),
+            Port(Signal("pos_count", Shape(8), init=0), PortDirection.OUTPUT),
+            Port(Signal("neg_count", Shape(8), init=0), PortDirection.OUTPUT),
+        ),
+        clock_domains=(
+            ClockDomain("pos", clk="clk", edge=EdgePolarity.POSEDGE),
+            ClockDomain("neg", clk="clk", edge=EdgePolarity.NEGEDGE),
+        ),
+        seq_blocks=(
+            SeqBlock(
+                "pos",
+                stmts=(
+                    Assign(
+                        "pos_count",
+                        Binary(
+                            Shape(8),
+                            BinaryOp.ADD,
+                            SignalRef(Shape(8), "pos_count"),
+                            Const(Shape(8), 1),
+                        ),
+                    ),
+                ),
+            ),
+            SeqBlock(
+                "neg",
+                stmts=(
+                    Assign(
+                        "neg_count",
+                        Binary(
+                            Shape(8),
+                            BinaryOp.ADD,
+                            SignalRef(Shape(8), "neg_count"),
+                            Const(Shape(8), 1),
+                        ),
+                    ),
+                ),
+            ),
+        ),
+    )
+
+
+class TestMixedClockEdges:
+    def test_posedge_and_negedge_domains_progress_equally(self):
+        """Both domains should tick once per full period on shared clock."""
+        m = _make_mixed_edge_single_clock()
+        cm = compile_module(m)
+        traces = cm.run(cycles=8)
+
+        pos_vals = [v for _, v in traces["pos_count"]]
+        neg_vals = [v for _, v in traces["neg_count"]]
+
+        assert pos_vals[-1] == 8, f"Expected pos_count=8, got {pos_vals[-1]}"
+        assert neg_vals[-1] == 8, f"Expected neg_count=8, got {neg_vals[-1]}"
+
+
 class TestLongRunCounter:
     def test_100_cycle_counter(self):
         """Simulate 4-bit counter with reset for 100 cycles."""