From 20bf88a6d405296cb28906dc85a245bb9a45b0a4 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Tue, 3 Dec 2024 16:43:04 +0200 Subject: [PATCH 1/2] bugfix: changed TIMING_VIOLATION_CORNERS to a PDK variable (#609) ## Steps * `Checker.*Violations` * Changed `TIMING_VIOLATION_CORNERS` to a PDK variable --- Changelog.md | 8 ++++++++ openlane/config/pdk_compat.py | 1 + openlane/steps/checker.py | 2 +- pyproject.toml | 2 +- test/steps/excluded_step_tests | 2 ++ 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/Changelog.md b/Changelog.md index 4fcc82ada..b992f8f3b 100644 --- a/Changelog.md +++ b/Changelog.md @@ -13,6 +13,14 @@ ## API Breaks ## Documentation --> +# 2.2.8 + +## Steps + +* `Checker.*Violations` + + * Changed `TIMING_VIOLATION_CORNERS` to a PDK variable + # 2.2.7 ## Steps diff --git a/openlane/config/pdk_compat.py b/openlane/config/pdk_compat.py index 0b0b5056a..8f9d7681d 100644 --- a/openlane/config/pdk_compat.py +++ b/openlane/config/pdk_compat.py @@ -228,6 +228,7 @@ def process_sta(key: str): ] new["DEFAULT_CORNER"] = f"nom_{default_pvt}" + new["TIMING_VIOLATION_CORNERS"] = ["*tt*"] new["LIB"] = lib_sta # x4. Constraints (sky130/gf180mcu) diff --git a/openlane/steps/checker.py b/openlane/steps/checker.py index b22a07dd2..cab542e05 100644 --- a/openlane/steps/checker.py +++ b/openlane/steps/checker.py @@ -464,7 +464,7 @@ def __init_subclass__(cls, **kwargs): cls.base_corner_var_name, List[str], "A list of wildcards matching IPVT corners to use during checking for timing violations.", - default=["*tt*"], + pdk=True, deprecated_names=["TIMING_VIOLATIONS_CORNERS"], ), cls.get_corner_variable(), diff --git a/pyproject.toml b/pyproject.toml index 6be5fcd3d..8b52b7f86 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,6 +1,6 @@ [tool.poetry] name = "openlane" -version = "2.2.7" +version = "2.2.8" description = "An infrastructure for implementing chip design flows" authors = ["Efabless Corporation and Contributors "] readme = "Readme.md" diff --git a/test/steps/excluded_step_tests b/test/steps/excluded_step_tests index e69de29bb..1ea9c89ee 100644 --- a/test/steps/excluded_step_tests +++ b/test/steps/excluded_step_tests @@ -0,0 +1,2 @@ +checker.holdviolations/004-success-hold-overwrite +checker.holdviolations/005-fail-different-corner From df6079da3dab69ddeb0d6ac7e654df8c958c5b6a Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Wed, 4 Dec 2024 17:59:01 +0200 Subject: [PATCH 2/2] bugfix: VERILOG_INCLUDE_DIRS not a list of Paths (#616) * `Yosys.JsonHeader`, `Yosys.Synthesis` * Fixed `VERILOG_INCLUDE_DIRS` being a list of strings instead of a list of `Path`s. --- Changelog.md | 21 ++++++++++++++++----- openlane/steps/pyosys.py | 40 +--------------------------------------- pyproject.toml | 2 +- 3 files changed, 18 insertions(+), 45 deletions(-) diff --git a/Changelog.md b/Changelog.md index b992f8f3b..5e4944483 100644 --- a/Changelog.md +++ b/Changelog.md @@ -13,13 +13,24 @@ ## API Breaks ## Documentation --> + +# 2.2.9 + +## Steps + +* `Yosys.JsonHeader`, `Yosys.Synthesis` + + * Fixed `VERILOG_INCLUDE_DIRS` being a list of strings instead of a list of + `Path`s. + # 2.2.8 ## Steps * `Checker.*Violations` - * Changed `TIMING_VIOLATION_CORNERS` to a PDK variable + * Changed `TIMING_VIOLATION_CORNERS` to a PDK variable to avoid breaking PDKs + without `tt` in corner names. # 2.2.7 @@ -35,13 +46,13 @@ * `OpenROAD.ResizerTimingPostGRT` - * Fixed `GRT_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead - of setup fixing. + * Fixed `GRT_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead + of setup fixing. * `OpenROAD.ResizerTimingPostCTS` - * Fixed `PL_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead - of setup fixing. + * Fixed `PL_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead + of setup fixing. # 2.2.5 diff --git a/openlane/steps/pyosys.py b/openlane/steps/pyosys.py index 96e13bf29..8f76ddc21 100644 --- a/openlane/steps/pyosys.py +++ b/openlane/steps/pyosys.py @@ -28,44 +28,6 @@ from ..logging import debug, verbose from ..common import Path, get_script_dir, process_list_file -verilog_rtl_cfg_vars = [ - Variable( - "VERILOG_FILES", - List[Path], - "The paths of the design's Verilog files.", - ), - Variable( - "VERILOG_DEFINES", - Optional[List[str]], - "Preprocessor defines for input Verilog files.", - deprecated_names=["SYNTH_DEFINES"], - ), - Variable( - "VERILOG_POWER_DEFINE", - Optional[str], - "Specifies the name of the define used to guard power and ground connections in the input RTL.", - deprecated_names=["SYNTH_USE_PG_PINS_DEFINES", "SYNTH_POWER_DEFINE"], - default="USE_POWER_PINS", - ), - Variable( - "VERILOG_INCLUDE_DIRS", - Optional[List[str]], - "Specifies the Verilog `include` directories.", - ), - Variable( - "USE_SYNLIG", - bool, - "Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes.", - default=False, - ), - Variable( - "SYNLIG_DEFER", - bool, - "Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental.", - default=False, - ), -] - starts_with_whitespace = re.compile(r"^\s+.+$") yosys_cell_rx = r"cell\s+\S+\s+\((\S+)\)" @@ -149,7 +111,7 @@ def _parse_yosys_check( ), Variable( "VERILOG_INCLUDE_DIRS", - Optional[List[str]], + Optional[List[Path]], "Specifies the Verilog `include` directories.", ), Variable( diff --git a/pyproject.toml b/pyproject.toml index 8b52b7f86..4ce86e2be 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,6 +1,6 @@ [tool.poetry] name = "openlane" -version = "2.2.8" +version = "2.2.9" description = "An infrastructure for implementing chip design flows" authors = ["Efabless Corporation and Contributors "] readme = "Readme.md"