diff --git a/.github/ci/build.sh b/.github/ci/build.sh index e7c48f31f..2fbbda947 100755 --- a/.github/ci/build.sh +++ b/.github/ci/build.sh @@ -29,6 +29,7 @@ set -e mv /ci/cache/sources ./sources || true ./d ci +./d check # move the sources directory into the cache mv ./sources /ci/cache/sources diff --git a/d b/d index be4f74eea..1d5d70b9e 100755 --- a/d +++ b/d @@ -56,10 +56,105 @@ case "$CMD" in cargo run --release --bin stm32-data-gen cargo run --release --bin stm32-metapac-gen cd build/stm32-metapac - #find . -name '*.rs' -not -path '*target*' | xargs rustfmt --skip-children --unstable-features --edition 2021 - cargo check --features stm32h755zi-cm7,pac,metadata - cargo check --features stm32f777zi,pac - cargo check --features stm32u585zi,metadata + find . -name '*.rs' -not -path '*target*' | xargs rustfmt --skip-children --unstable-features --edition 2021 + ;; + check) + cargo batch \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32c031c6 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f030c6 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f030r8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f030rc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f031k6 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f058t8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f070f6 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f078vb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f091rc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f100c4 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f103c8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f103re \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f107vc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f207zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f217zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f303c8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f303ze \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f378cc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f398ve \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f405zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f407zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f410tb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f411ce \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f412zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f413vh \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f415zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f417zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f423zh \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f427zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f437zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f439zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f446re \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f446ze \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f469zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f479zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f730i8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32f767zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32g071rb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32g0c1ve \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32g474pe \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h503rb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h523cc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h562ag \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h563zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h725re \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h735zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h753zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi-cm7 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi-cm4 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7a3zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7b3ai \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7r3z8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7r7a8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7s3a8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7s3l8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32h7s7z8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l041f6 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l051k8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l072cz \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l073cz \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l073rz \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l151cb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l152re \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l422cb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l431cb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l476vg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l496zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l4a6zg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l4r5zi \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32l552ze \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u031r8 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u073mb \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u083rc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u5a5zj \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u5f9zj \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32u5g9nj \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wb15cc \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wb35ce \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wba50ke \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wba52cg \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wba55ug \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wl54jc-cm4 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wl54jc-cm0p \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc-cm4 \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc-cm0p \ + --- build --release --manifest-path build/stm32-metapac/Cargo.toml --target thumbv7em-none-eabi --features stm32wle5jb \ + ;; *) echo "unknown command" diff --git a/d.ps1 b/d.ps1 index af2d8a17b..cc293fe40 100644 --- a/d.ps1 +++ b/d.ps1 @@ -6,7 +6,7 @@ param ( [string]$peri ) -$REV="74b97817d4c4ed0db9d19a8eac46720b3c5b0d57" +$REV="709c1060ac2ec57f6042f2b4eb9cf8c1821a6c57" Switch ($CMD) { diff --git a/data/registers/adc_g4.yaml b/data/registers/adc_g4.yaml index df7cc910e..a3ddde0b7 100644 --- a/data/registers/adc_g4.yaml +++ b/data/registers/adc_g4.yaml @@ -129,16 +129,16 @@ fieldset/CALFACT: fieldset/CFGR: description: configuration register 1 fields: - - name: DMACFG - description: Direct memory access configuration - bit_offset: 0 - bit_size: 1 - enum: DMACFG - name: DMAEN description: Direct memory access enable bit_offset: 0 bit_size: 1 enum: DMAEN + - name: DMACFG + description: Direct memory access configuration + bit_offset: 1 + bit_size: 1 + enum: DMACFG - name: RES description: data resolution bit_offset: 3 diff --git a/data/registers/dbgmcu_u0.yaml b/data/registers/dbgmcu_u0.yaml new file mode 100644 index 000000000..5e2a9e118 --- /dev/null +++ b/data/registers/dbgmcu_u0.yaml @@ -0,0 +1,267 @@ +block/DBGMCU: + description: DBGMCU register block. + items: + - name: IDCODE + description: DBGMCU device ID code register. + byte_offset: 0 + fieldset: IDCODE + - name: CR + description: DBGMCU configuration register. + byte_offset: 4 + fieldset: CR + - name: APB1FZR + description: DBGMCU APB1 freeze register. + byte_offset: 8 + fieldset: APB1FZR + - name: APB2FZR + description: DBG APB2 freeze register. + byte_offset: 12 + fieldset: APB2FZR + - name: SR + description: DBGMCU status register. + byte_offset: 252 + fieldset: SR + - name: DBG_AUTH_HOST + description: DBGMCU debug authentication mailbox host register. + byte_offset: 256 + fieldset: DBG_AUTH_HOST + - name: DBG_AUTH_DEVICE + description: DBGMCU debug authentication mailbox device register. + byte_offset: 260 + fieldset: DBG_AUTH_DEVICE + - name: PIDR4 + description: DBGMCU CoreSight peripheral identity register 4. + byte_offset: 4048 + fieldset: PIDR4 + - name: PIDR0 + description: DBGMCU CoreSight peripheral identity register 0. + byte_offset: 4064 + fieldset: PIDR0 + - name: PIDR1 + description: DBGMCU CoreSight peripheral identity register 1. + byte_offset: 4068 + fieldset: PIDR1 + - name: PIDR2 + description: DBGMCU CoreSight peripheral identity register 2. + byte_offset: 4072 + fieldset: PIDR2 + - name: PIDR3 + description: DBGMCU CoreSight peripheral identity register 3. + byte_offset: 4076 + fieldset: PIDR3 + - name: CIDR0 + description: DBGMCU CoreSight component identity register 0. + byte_offset: 4080 + fieldset: CIDR0 + - name: CIDR1 + description: DBGMCU CoreSight component identity register 1. + byte_offset: 4084 + fieldset: CIDR1 + - name: CIDR2 + description: DBGMCU CoreSight component identity register 2. + byte_offset: 4088 + fieldset: CIDR2 + - name: CIDR3 + description: DBGMCU CoreSight component identity register 3. + byte_offset: 4092 + fieldset: CIDR3 +fieldset/APB1FZR: + description: DBGMCU APB1 freeze register. + fields: + - name: DBG_TIM2_STOP + description: TIM2 stop in debug. + bit_offset: 0 + bit_size: 1 + - name: DBG_TIM3_STOP + description: TIM3 stop in debug. + bit_offset: 1 + bit_size: 1 + - name: DBG_TIM6_STOP + description: TIM6 stop in debug. + bit_offset: 4 + bit_size: 1 + - name: DBG_TIM7_STOP + description: TIM7 stop in debug. + bit_offset: 5 + bit_size: 1 + - name: DBG_RTC_STOP + description: RTC stop in debug. + bit_offset: 10 + bit_size: 1 + - name: DBG_WWDG_STOP + description: WWDG stop in debug. + bit_offset: 11 + bit_size: 1 + - name: DBG_IWDG_STOP + description: IWDG stop in debug. + bit_offset: 12 + bit_size: 1 + - name: DBG_LPTIM2_STOP + description: LPTIM2 stop in debug. + bit_offset: 30 + bit_size: 1 + - name: DBG_LPTIM1_STOP + description: LPTIM1 stop in debug. + bit_offset: 31 + bit_size: 1 +fieldset/APB2FZR: + description: DBG APB2 freeze register. + fields: + - name: DBG_TIM1_STOP + description: TIM1 stop in debug. + bit_offset: 11 + bit_size: 1 + - name: DBG_TIM15_STOP + description: TIM15 stop in debug. + bit_offset: 16 + bit_size: 1 + - name: DBG_TIM16_STOP + description: TIM16 stop in debug. + bit_offset: 17 + bit_size: 1 + - name: DBG_LPTIM3_STOP + description: LPTIM3 stop in debug. + bit_offset: 18 + bit_size: 1 +fieldset/CIDR0: + description: DBGMCU CoreSight component identity register 0. + fields: + - name: PREAMBLE + description: component identification bits [7:0]. + bit_offset: 0 + bit_size: 8 +fieldset/CIDR1: + description: DBGMCU CoreSight component identity register 1. + fields: + - name: PREAMBLE + description: component identification bits [11:8]. + bit_offset: 0 + bit_size: 4 + - name: CLASS + description: component identification bits [15:12] - component class. + bit_offset: 4 + bit_size: 4 +fieldset/CIDR2: + description: DBGMCU CoreSight component identity register 2. + fields: + - name: PREAMBLE + description: component identification bits [23:16]. + bit_offset: 0 + bit_size: 8 +fieldset/CIDR3: + description: DBGMCU CoreSight component identity register 3. + fields: + - name: PREAMBLE + description: component identification bits [31:24]. + bit_offset: 0 + bit_size: 8 +fieldset/CR: + description: DBGMCU configuration register. + fields: + - name: DBG_STOP + description: Debug Stop mode Debug options in Stop mode. + bit_offset: 1 + bit_size: 1 + - name: DBG_STANDBY + description: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode. + bit_offset: 2 + bit_size: 1 +fieldset/DBG_AUTH_DEVICE: + description: DBGMCU debug authentication mailbox device register. + fields: + - name: MESSAGE + description: Device to debug host mailbox message. During debug authentication the device communicates with the debug host via this register. + bit_offset: 0 + bit_size: 32 +fieldset/DBG_AUTH_HOST: + description: DBGMCU debug authentication mailbox host register. + fields: + - name: MESSAGE + description: Debug host to device mailbox message. During debug authentication the debug host communicates with the device via this register. + bit_offset: 0 + bit_size: 32 +fieldset/IDCODE: + description: DBGMCU device ID code register. + fields: + - name: DEV_ID + description: Device identifier This field indicates the device ID. + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: Revision identifier This field indicates the revision of the device. + bit_offset: 16 + bit_size: 16 +fieldset/PIDR0: + description: DBGMCU CoreSight peripheral identity register 0. + fields: + - name: PARTNUM + description: part number bits [7:0]. + bit_offset: 0 + bit_size: 8 +fieldset/PIDR1: + description: DBGMCU CoreSight peripheral identity register 1. + fields: + - name: PARTNUM + description: part number bits [11:8]. + bit_offset: 0 + bit_size: 4 + - name: JEP106ID + description: JEP106 identity code bits [3:0]. + bit_offset: 4 + bit_size: 4 +fieldset/PIDR2: + description: DBGMCU CoreSight peripheral identity register 2. + fields: + - name: JEP106ID + description: JEP106 identity code bits [6:4]. + bit_offset: 0 + bit_size: 3 + - name: JEDEC + description: JEDEC assigned value. + bit_offset: 3 + bit_size: 1 + - name: REVISION + description: component revision number. + bit_offset: 4 + bit_size: 4 +fieldset/PIDR3: + description: DBGMCU CoreSight peripheral identity register 3. + fields: + - name: CMOD + description: customer modified. + bit_offset: 0 + bit_size: 4 + - name: REVAND + description: metal fix version. + bit_offset: 4 + bit_size: 4 +fieldset/PIDR4: + description: DBGMCU CoreSight peripheral identity register 4. + fields: + - name: JEP106CON + description: JEP106 continuation code. + bit_offset: 0 + bit_size: 4 + - name: SIZE + description: register file size. + bit_offset: 4 + bit_size: 4 +fieldset/SR: + description: DBGMCU status register. + fields: + - name: AP1_PRESENT + description: Identifies whether access port AP1 is present in device. + bit_offset: 0 + bit_size: 1 + - name: AP0_PRESENT + description: Identifies whether access port AP0 is present in device. + bit_offset: 1 + bit_size: 1 + - name: AP1_ENABLED + description: Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked). + bit_offset: 16 + bit_size: 1 + - name: AP0_ENABLED + description: Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked). + bit_offset: 17 + bit_size: 1 diff --git a/data/registers/flash_u5.yaml b/data/registers/flash_u5.yaml index 16c3584a3..6e66134fe 100644 --- a/data/registers/flash_u5.yaml +++ b/data/registers/flash_u5.yaml @@ -276,7 +276,7 @@ fieldset/NSCR: - name: PNB description: "Non-secure page number selection\r These bits select the page to erase.\r ..." bit_offset: 3 - bit_size: 7 + bit_size: 8 - name: BKER description: Non-secure bank selection for page erase bit_offset: 11 @@ -2692,7 +2692,7 @@ fieldset/SECCR: - name: PNB description: "Secure page number selection\r These bits select the page to erase:\r ..." bit_offset: 3 - bit_size: 7 + bit_size: 8 - name: BKER description: Secure bank selection for page erase bit_offset: 11 diff --git a/data/registers/fmpi2c_v2.yaml b/data/registers/fmpi2c_v2.yaml new file mode 100644 index 000000000..31548cda2 --- /dev/null +++ b/data/registers/fmpi2c_v2.yaml @@ -0,0 +1,512 @@ +block/FMPI2C: + description: Inter-integrated circuit + items: + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: OAR1 + description: Own address register 1 + byte_offset: 8 + fieldset: OAR1 + - name: OAR2 + description: Own address register 2 + byte_offset: 12 + fieldset: OAR2 + - name: TIMINGR + description: Timing register + byte_offset: 16 + fieldset: TIMINGR + - name: TIMEOUTR + description: Timeout register + byte_offset: 20 + fieldset: TIMEOUTR + - name: ISR + description: Interrupt and Status register + byte_offset: 24 + fieldset: ISR + - name: ICR + description: Interrupt clear register + byte_offset: 28 + fieldset: ICR + - name: PECR + description: PEC register + byte_offset: 32 + fieldset: PECR + - name: RXDR + description: Receive data register + byte_offset: 36 + fieldset: RXDR + - name: TXDR + description: Transmit data register + byte_offset: 40 + fieldset: TXDR +fieldset/CR1: + description: Control register 1 + fields: + - name: PE + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: TXIE + description: TX Interrupt enable + bit_offset: 1 + bit_size: 1 + - name: RXIE + description: RX Interrupt enable + bit_offset: 2 + bit_size: 1 + - name: ADDRIE + description: Address match interrupt enable (slave only) + bit_offset: 3 + bit_size: 1 + - name: NACKIE + description: Not acknowledge received interrupt enable + bit_offset: 4 + bit_size: 1 + - name: STOPIE + description: STOP detection Interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transfer Complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: ERRIE + description: Error interrupts enable + bit_offset: 7 + bit_size: 1 + - name: DNF + description: Digital noise filter + bit_offset: 8 + bit_size: 4 + enum: DNF + - name: ANFOFF + description: Analog noise filter OFF + bit_offset: 12 + bit_size: 1 + - name: TXDMAEN + description: DMA transmission requests enable + bit_offset: 14 + bit_size: 1 + - name: RXDMAEN + description: DMA reception requests enable + bit_offset: 15 + bit_size: 1 + - name: SBC + description: Slave byte control + bit_offset: 16 + bit_size: 1 + - name: NOSTRETCH + description: Clock stretching disable + bit_offset: 17 + bit_size: 1 + - name: GCEN + description: General call enable + bit_offset: 19 + bit_size: 1 + - name: SMBHEN + description: SMBus Host address enable + bit_offset: 20 + bit_size: 1 + - name: SMBDEN + description: SMBus Device Default address enable + bit_offset: 21 + bit_size: 1 + - name: ALERTEN + description: SMBUS alert enable + bit_offset: 22 + bit_size: 1 + - name: PECEN + description: PEC enable + bit_offset: 23 + bit_size: 1 +fieldset/CR2: + description: Control register 2 + fields: + - name: SADD + description: Slave address bit (master mode) + bit_offset: 0 + bit_size: 10 + - name: DIR + description: Transfer direction (master mode) + bit_offset: 10 + bit_size: 1 + enum: DIR + - name: ADD10 + description: 10-bit addressing mode (master mode) + bit_offset: 11 + bit_size: 1 + enum: ADDMODE + - name: HEAD10R + description: 10-bit address header only read direction (master receiver mode) + bit_offset: 12 + bit_size: 1 + enum: HEADR + - name: START + description: Start generation + bit_offset: 13 + bit_size: 1 + - name: STOP + description: Stop generation (master mode) + bit_offset: 14 + bit_size: 1 + - name: NACK + description: NACK generation (slave mode) + bit_offset: 15 + bit_size: 1 + - name: NBYTES + description: Number of bytes + bit_offset: 16 + bit_size: 8 + - name: RELOAD + description: NBYTES reload mode + bit_offset: 24 + bit_size: 1 + enum: RELOAD + - name: AUTOEND + description: Automatic end mode (master mode) + bit_offset: 25 + bit_size: 1 + enum: AUTOEND + - name: PECBYTE + description: Packet error checking byte + bit_offset: 26 + bit_size: 1 +fieldset/ICR: + description: Interrupt clear register + fields: + - name: ADDRCF + description: Address Matched flag clear + bit_offset: 3 + bit_size: 1 + - name: NACKCF + description: Not Acknowledge flag clear + bit_offset: 4 + bit_size: 1 + - name: STOPCF + description: Stop detection flag clear + bit_offset: 5 + bit_size: 1 + - name: BERRCF + description: Bus error flag clear + bit_offset: 8 + bit_size: 1 + - name: ARLOCF + description: Arbitration lost flag clear + bit_offset: 9 + bit_size: 1 + - name: OVRCF + description: Overrun/Underrun flag clear + bit_offset: 10 + bit_size: 1 + - name: PECCF + description: PEC Error flag clear + bit_offset: 11 + bit_size: 1 + - name: TIMOUTCF + description: Timeout detection flag clear + bit_offset: 12 + bit_size: 1 + - name: ALERTCF + description: Alert flag clear + bit_offset: 13 + bit_size: 1 +fieldset/ISR: + description: Interrupt and Status register + fields: + - name: TXE + description: Transmit data register empty (transmitters) + bit_offset: 0 + bit_size: 1 + - name: TXIS + description: Transmit interrupt status (transmitters) + bit_offset: 1 + bit_size: 1 + - name: RXNE + description: Receive data register not empty (receivers) + bit_offset: 2 + bit_size: 1 + - name: ADDR + description: Address matched (slave mode) + bit_offset: 3 + bit_size: 1 + - name: NACKF + description: Not acknowledge received flag + bit_offset: 4 + bit_size: 1 + - name: STOPF + description: Stop detection flag + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transfer Complete (master mode) + bit_offset: 6 + bit_size: 1 + - name: TCR + description: Transfer Complete Reload + bit_offset: 7 + bit_size: 1 + - name: BERR + description: Bus error + bit_offset: 8 + bit_size: 1 + - name: ARLO + description: Arbitration lost + bit_offset: 9 + bit_size: 1 + - name: OVR + description: Overrun/Underrun (slave mode) + bit_offset: 10 + bit_size: 1 + - name: PECERR + description: PEC Error in reception + bit_offset: 11 + bit_size: 1 + - name: TIMEOUT + description: Timeout or t_low detection flag + bit_offset: 12 + bit_size: 1 + - name: ALERT + description: SMBus alert + bit_offset: 13 + bit_size: 1 + - name: BUSY + description: Bus busy + bit_offset: 15 + bit_size: 1 + - name: DIR + description: Transfer direction (Slave mode) + bit_offset: 16 + bit_size: 1 + enum: DIR + - name: ADDCODE + description: Address match code (Slave mode) + bit_offset: 17 + bit_size: 7 +fieldset/OAR1: + description: Own address register 1 + fields: + - name: OA1 + description: Interface address + bit_offset: 0 + bit_size: 10 + - name: OA1MODE + description: Own Address 1 10-bit mode + bit_offset: 10 + bit_size: 1 + enum: ADDMODE + - name: OA1EN + description: Own Address 1 enable + bit_offset: 15 + bit_size: 1 +fieldset/OAR2: + description: Own address register 2 + fields: + - name: OA2 + description: Interface address + bit_offset: 1 + bit_size: 7 + - name: OA2MSK + description: Own Address 2 masks + bit_offset: 8 + bit_size: 3 + enum: OAMSK + - name: OA2EN + description: Own Address 2 enable + bit_offset: 15 + bit_size: 1 +fieldset/PECR: + description: PEC register + fields: + - name: PEC + description: Packet error checking register + bit_offset: 0 + bit_size: 8 +fieldset/RXDR: + description: Receive data register + fields: + - name: RXDATA + description: 8-bit receive data + bit_offset: 0 + bit_size: 8 +fieldset/TIMEOUTR: + description: Timeout register + fields: + - name: TIMEOUTA + description: Bus timeout A + bit_offset: 0 + bit_size: 12 + - name: TIDLE + description: Idle clock timeout detection + bit_offset: 12 + bit_size: 1 + - name: TIMOUTEN + description: Clock timeout enable + bit_offset: 15 + bit_size: 1 + - name: TIMEOUTB + description: Bus timeout B + bit_offset: 16 + bit_size: 12 + - name: TEXTEN + description: Extended clock timeout enable + bit_offset: 31 + bit_size: 1 +fieldset/TIMINGR: + description: Timing register + fields: + - name: SCLL + description: SCL low period (master mode) + bit_offset: 0 + bit_size: 8 + - name: SCLH + description: SCL high period (master mode) + bit_offset: 8 + bit_size: 8 + - name: SDADEL + description: Data hold time + bit_offset: 16 + bit_size: 4 + - name: SCLDEL + description: Data setup time + bit_offset: 20 + bit_size: 4 + - name: PRESC + description: Timing prescaler + bit_offset: 28 + bit_size: 4 +fieldset/TXDR: + description: Transmit data register + fields: + - name: TXDATA + description: 8-bit transmit data + bit_offset: 0 + bit_size: 8 +enum/ADDMODE: + bit_size: 1 + variants: + - name: Bit7 + description: 7-bit addressing mode + value: 0 + - name: Bit10 + description: 10-bit addressing mode + value: 1 +enum/AUTOEND: + bit_size: 1 + variants: + - name: Software + description: 'Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low' + value: 0 + - name: Automatic + description: 'Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred' + value: 1 +enum/DIR: + bit_size: 1 + variants: + - name: Write + description: Write transfer, slave enters receiver mode + value: 0 + - name: Read + description: Read transfer, slave enters transmitter mode + value: 1 +enum/DNF: + bit_size: 4 + variants: + - name: NoFilter + description: Digital filter disabled + value: 0 + - name: Filter1 + description: Digital filter enabled and filtering capability up to 1 tI2CCLK + value: 1 + - name: Filter2 + description: Digital filter enabled and filtering capability up to 2 tI2CCLK + value: 2 + - name: Filter3 + description: Digital filter enabled and filtering capability up to 3 tI2CCLK + value: 3 + - name: Filter4 + description: Digital filter enabled and filtering capability up to 4 tI2CCLK + value: 4 + - name: Filter5 + description: Digital filter enabled and filtering capability up to 5 tI2CCLK + value: 5 + - name: Filter6 + description: Digital filter enabled and filtering capability up to 6 tI2CCLK + value: 6 + - name: Filter7 + description: Digital filter enabled and filtering capability up to 7 tI2CCLK + value: 7 + - name: Filter8 + description: Digital filter enabled and filtering capability up to 8 tI2CCLK + value: 8 + - name: Filter9 + description: Digital filter enabled and filtering capability up to 9 tI2CCLK + value: 9 + - name: Filter10 + description: Digital filter enabled and filtering capability up to 10 tI2CCLK + value: 10 + - name: Filter11 + description: Digital filter enabled and filtering capability up to 11 tI2CCLK + value: 11 + - name: Filter12 + description: Digital filter enabled and filtering capability up to 12 tI2CCLK + value: 12 + - name: Filter13 + description: Digital filter enabled and filtering capability up to 13 tI2CCLK + value: 13 + - name: Filter14 + description: Digital filter enabled and filtering capability up to 14 tI2CCLK + value: 14 + - name: Filter15 + description: Digital filter enabled and filtering capability up to 15 tI2CCLK + value: 15 +enum/HEADR: + bit_size: 1 + variants: + - name: Complete + description: The master sends the complete 10 bit slave address read sequence + value: 0 + - name: Partial + description: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + value: 1 +enum/OAMSK: + bit_size: 3 + variants: + - name: NoMask + description: No mask + value: 0 + - name: Mask1 + description: OA2[1] is masked and don’t care. Only OA2[7:2] are compared + value: 1 + - name: Mask2 + description: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + value: 2 + - name: Mask3 + description: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + value: 3 + - name: Mask4 + description: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + value: 4 + - name: Mask5 + description: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + value: 5 + - name: Mask6 + description: OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + value: 6 + - name: Mask7 + description: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + value: 7 +enum/RELOAD: + bit_size: 1 + variants: + - name: Completed + description: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + value: 0 + - name: NotCompleted + description: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + value: 1 diff --git a/data/registers/hrtim_v1.yaml b/data/registers/hrtim_v1.yaml index 6d97499f8..1fe0497ac 100644 --- a/data/registers/hrtim_v1.yaml +++ b/data/registers/hrtim_v1.yaml @@ -1191,12 +1191,10 @@ fieldset/TIMXCCR: description: Software Capture bit_offset: 0 bit_size: 1 - enum: CAPTUREEFFECT - name: UPDCPT description: Update Capture bit_offset: 1 bit_size: 1 - enum: CAPTUREEFFECT - name: EXEVCPT description: External Event X Capture bit_offset: 2 @@ -1204,17 +1202,14 @@ fieldset/TIMXCCR: array: len: 10 stride: 1 - enum: CAPTUREEFFECT - name: TXSET description: Timer X output Set bit_offset: 16 bit_size: 1 - enum: CAPTUREEFFECT - name: TXRST description: Timer X output Reset bit_offset: 17 bit_size: 1 - enum: CAPTUREEFFECT - name: TXCMP description: Timer X Compare X bit_offset: 18 @@ -1222,17 +1217,14 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT - name: TYSET description: Timer Y output Set bit_offset: 20 bit_size: 1 - enum: CAPTUREEFFECT - name: TYRST description: Timer Y output Reset bit_offset: 21 bit_size: 1 - enum: CAPTUREEFFECT - name: TYCMP description: Timer Y Compare X bit_offset: 22 @@ -1240,17 +1232,14 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT - name: TZSET description: Timer Z output Set bit_offset: 24 bit_size: 1 - enum: CAPTUREEFFECT - name: TZRST description: Timer Z output Reset bit_offset: 25 bit_size: 1 - enum: CAPTUREEFFECT - name: TZCMP description: Timer Z Compare X bit_offset: 26 @@ -1258,17 +1247,14 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT - name: TTSET description: Timer T output Set bit_offset: 28 bit_size: 1 - enum: CAPTUREEFFECT - name: TTRST description: Timer T output Reset bit_offset: 29 bit_size: 1 - enum: CAPTUREEFFECT - name: TTCMP description: Timer T Compare X bit_offset: 30 @@ -1276,7 +1262,6 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT fieldset/TIMXCHP: description: Timerx Chopper Register fields: @@ -1351,12 +1336,10 @@ fieldset/TIMXCR: description: Synchronization Resets Timer X bit_offset: 10 bit_size: 1 - enum: SYNCRST - name: SYNCSTRT description: Synchronization Starts Timer X bit_offset: 11 bit_size: 1 - enum: SYNCSTRT - name: DELCMP2 description: Delayed CMP2 mode bit_offset: 12 @@ -1375,26 +1358,13 @@ fieldset/TIMXCR: description: Timer X reset update bit_offset: 18 bit_size: 1 - - name: TAU - description: Timer A update + - name: TU + description: Timer X update bit_offset: 19 bit_size: 1 - - name: TBU - description: Timer B update - bit_offset: 20 - bit_size: 1 - - name: TCU - description: Timer C update - bit_offset: 21 - bit_size: 1 - - name: TDU - description: Timer D update - bit_offset: 22 - bit_size: 1 - - name: TEU - description: Timer E update - bit_offset: 23 - bit_size: 1 + array: + len: 5 + stride: 1 - name: MSTU description: Master Timer update bit_offset: 24 @@ -1519,7 +1489,7 @@ fieldset/TIMXDT: description: Sign Deadtime Rising value bit_offset: 9 bit_size: 1 - enum: SDTR + enum: SDT - name: DTPRSC description: Deadtime Prescaler bit_offset: 10 @@ -1540,7 +1510,7 @@ fieldset/TIMXDT: description: Sign Deadtime Falling value bit_offset: 25 bit_size: 1 - enum: SDTF + enum: SDT - name: DTFSLK description: Deadtime Falling Sign Lock bit_offset: 30 @@ -1577,7 +1547,6 @@ fieldset/TIMXFLT: array: len: 5 stride: 1 - enum: FLTEN - name: FLTLCK description: Fault sources Lock bit_offset: 31 @@ -1680,7 +1649,6 @@ fieldset/TIMXISR: description: Delayed Protection Flag bit_offset: 14 bit_size: 1 - enum: TIMAISR_DLYPRT - name: CPPSTAT description: Current Push Pull Status bit_offset: 16 @@ -1698,7 +1666,6 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum: OUTPUTSTATE - name: OCPY description: Output X Copy bit_offset: 20 @@ -1706,7 +1673,6 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum: OUTPUTSTATE fieldset/TIMXOUTR: description: Timerx Output Register fields: @@ -1735,7 +1701,7 @@ fieldset/TIMXOUTR: offsets: - 0 - 16 - - name: FAULTX + - name: FAULT description: Output X Fault state bit_offset: 4 bit_size: 2 @@ -1794,7 +1760,6 @@ fieldset/TIMXRST: description: Timer X Update reset bit_offset: 1 bit_size: 1 - enum: RESETEFFECT - name: CMP description: Timer X compare X reset bit_offset: 2 @@ -1802,12 +1767,10 @@ fieldset/TIMXRST: array: len: 2 stride: 1 - enum: RESETEFFECT - name: MSTPER description: Master timer Period bit_offset: 4 bit_size: 1 - enum: RESETEFFECT - name: MSTCMP description: Master compare X bit_offset: 5 @@ -1815,7 +1778,6 @@ fieldset/TIMXRST: array: len: 4 stride: 1 - enum: RESETEFFECT - name: EXTEVNT description: External Event X bit_offset: 9 @@ -1823,7 +1785,6 @@ fieldset/TIMXRST: array: len: 10 stride: 1 - enum: RESETEFFECT - name: TCMP1 description: Timer X compare 1 event bit_offset: 19 @@ -1834,7 +1795,6 @@ fieldset/TIMXRST: - 3 - 6 - 9 - enum: RESETEFFECT - name: TCMP2 description: Timer X compare 2 event bit_offset: 20 @@ -1845,7 +1805,6 @@ fieldset/TIMXRST: - 3 - 6 - 9 - enum: RESETEFFECT - name: TCMP4 description: Timer X compare 4 event bit_offset: 21 @@ -1856,7 +1815,6 @@ fieldset/TIMXRST: - 3 - 6 - 9 - enum: RESETEFFECT fieldset/TIMXRSTR: description: Timerx OutputX Reset Register fields: @@ -1864,17 +1822,14 @@ fieldset/TIMXRSTR: description: Software Reset trigger bit_offset: 0 bit_size: 1 - enum: INACTIVEEFFECT - name: RESYNC description: Timer X resynchronizaton bit_offset: 1 bit_size: 1 - enum: INACTIVEEFFECT - name: PER description: Timer X Period bit_offset: 2 bit_size: 1 - enum: INACTIVEEFFECT - name: CMP description: Timer X compare X bit_offset: 3 @@ -1882,12 +1837,10 @@ fieldset/TIMXRSTR: array: len: 4 stride: 1 - enum: INACTIVEEFFECT - name: MSTPER description: Master Period bit_offset: 7 bit_size: 1 - enum: INACTIVEEFFECT - name: MSTCMP description: Master Compare X bit_offset: 8 @@ -1895,7 +1848,6 @@ fieldset/TIMXRSTR: array: len: 4 stride: 1 - enum: INACTIVEEFFECT - name: TIMEVNT description: Timer Event X bit_offset: 12 @@ -1903,7 +1855,6 @@ fieldset/TIMXRSTR: array: len: 9 stride: 1 - enum: INACTIVEEFFECT - name: EXTEVNT description: External Event X bit_offset: 21 @@ -1911,12 +1862,10 @@ fieldset/TIMXRSTR: array: len: 10 stride: 1 - enum: INACTIVEEFFECT - name: UPDATE description: Registers update (transfer preload to active) bit_offset: 31 bit_size: 1 - enum: INACTIVEEFFECT fieldset/TIMXSETR: description: Timerx OutputX Set Register fields: @@ -1924,17 +1873,14 @@ fieldset/TIMXSETR: description: Software Set trigger bit_offset: 0 bit_size: 1 - enum: ACTIVEEFFECT - name: RESYNC description: Timer X resynchronizaton bit_offset: 1 bit_size: 1 - enum: ACTIVEEFFECT - name: PER description: Timer X Period bit_offset: 2 bit_size: 1 - enum: ACTIVEEFFECT - name: CMP description: Timer X compare X bit_offset: 3 @@ -1942,12 +1888,10 @@ fieldset/TIMXSETR: array: len: 4 stride: 1 - enum: ACTIVEEFFECT - name: MSTPER description: Master Period bit_offset: 7 bit_size: 1 - enum: ACTIVEEFFECT - name: MSTCMPX description: Master Compare X bit_offset: 8 @@ -1955,7 +1899,6 @@ fieldset/TIMXSETR: array: len: 4 stride: 1 - enum: ACTIVEEFFECT - name: TIMEVNT description: Timer Event X bit_offset: 12 @@ -1963,7 +1906,6 @@ fieldset/TIMXSETR: array: len: 9 stride: 1 - enum: ACTIVEEFFECT - name: EXTEVNT description: External Event X bit_offset: 21 @@ -1971,21 +1913,10 @@ fieldset/TIMXSETR: array: len: 10 stride: 1 - enum: ACTIVEEFFECT - name: UPDATE description: Registers update (transfer preload to active) bit_offset: 31 bit_size: 1 - enum: ACTIVEEFFECT -enum/ACTIVEEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetActive - description: Timer event forces the output to its active state - value: 1 enum/BRSTDMA: bit_size: 2 variants: @@ -1998,15 +1929,6 @@ enum/BRSTDMA: - name: Rollover description: Update done on master timer roll-over following a DMA burst transfer completion value: 2 -enum/CAPTUREEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: TriggerCapture - description: Timer event triggers capture - value: 1 enum/CPPSTAT: bit_size: 1 variants: @@ -2139,24 +2061,6 @@ enum/FAULT: - name: SetHighZ description: Output goes to high-z state after a fault event value: 3 -enum/FLTEN: - bit_size: 1 - variants: - - name: Ignored - description: Fault input ignored - value: 0 - - name: Active - description: Fault input is active and can disable HRTIM outputs - value: 1 -enum/INACTIVEEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetInactive - description: Timer event forces the output to its inactive state - value: 1 enum/IPPSTAT: bit_size: 1 variants: @@ -2166,15 +2070,6 @@ enum/IPPSTAT: - name: Output2Active description: Protection occurred when the output 2 was active and output 1 forced inactive value: 1 -enum/OUTPUTSTATE: - bit_size: 1 - variants: - - name: Inactive - description: Output is or was inactive - value: 0 - - name: Active - description: Output is or was active - value: 1 enum/POL: bit_size: 1 variants: @@ -2184,32 +2079,14 @@ enum/POL: - name: ActiveLow description: Negative polarity (output active low) value: 1 -enum/RESETEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer Y compare Z event has no effect - value: 0 - - name: ResetCounter - description: Timer X counter is reset upon timer Y compare Z event - value: 1 -enum/SDTF: - bit_size: 1 - variants: - - name: Positive - description: Positive deadtime on falling edge - value: 0 - - name: Negative - description: Negative deadtime on falling edge - value: 1 -enum/SDTR: +enum/SDT: bit_size: 1 variants: - name: Positive - description: Positive deadtime on rising edge + description: Positive deadtime (both outputs inactive during deadtime) value: 0 - name: Negative - description: Negative deadtime on rising edge + description: Negative deadtime (both outputs active during deadtime) value: 1 enum/SYNCIN: bit_size: 2 @@ -2235,15 +2112,6 @@ enum/SYNCOUT: - name: NegativePulse description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) value: 3 -enum/SYNCRST: - bit_size: 1 - variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Reset - description: Synchronization event resets Timer x - value: 1 enum/SYNCSRC: bit_size: 2 variants: @@ -2259,24 +2127,6 @@ enum/SYNCSRC: - name: TimerACompare1 description: Timer A Compare 1 event value: 3 -enum/SYNCSTRT: - bit_size: 1 - variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Start - description: Synchronization event starts Timer x - value: 1 -enum/TIMAISR_DLYPRT: - bit_size: 1 - variants: - - name: Inactive - description: Not in delayed idle or balanced idle mode - value: 0 - - name: Active - description: Delayed idle or balanced idle mode entry - value: 1 enum/UPDGAT: bit_size: 4 variants: diff --git a/data/registers/hrtim_v2.yaml b/data/registers/hrtim_v2.yaml index 530e98326..bd63357e3 100644 --- a/data/registers/hrtim_v2.yaml +++ b/data/registers/hrtim_v2.yaml @@ -1188,12 +1188,10 @@ fieldset/TIMXCCR: description: Software Capture bit_offset: 0 bit_size: 1 - enum: CAPTUREEFFECT - name: UPDCPT description: Update Capture bit_offset: 1 bit_size: 1 - enum: CAPTUREEFFECT - name: EXEVCPT description: External Event X Capture bit_offset: 2 @@ -1201,17 +1199,14 @@ fieldset/TIMXCCR: array: len: 10 stride: 1 - enum: CAPTUREEFFECT - name: TXSET description: Timer X output Set bit_offset: 16 bit_size: 1 - enum: CAPTUREEFFECT - name: TXRST description: Timer X output Reset bit_offset: 17 bit_size: 1 - enum: CAPTUREEFFECT - name: TXCMP description: Timer X Compare X bit_offset: 18 @@ -1219,17 +1214,14 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT - name: TYSET description: Timer Y output Set bit_offset: 20 bit_size: 1 - enum: CAPTUREEFFECT - name: TYRST description: Timer Y output Reset bit_offset: 21 bit_size: 1 - enum: CAPTUREEFFECT - name: TYCMP description: Timer Y Compare X bit_offset: 22 @@ -1237,17 +1229,14 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT - name: TZSET description: Timer Z output Set bit_offset: 24 bit_size: 1 - enum: CAPTUREEFFECT - name: TZRST description: Timer Z output Reset bit_offset: 25 bit_size: 1 - enum: CAPTUREEFFECT - name: TZCMP description: Timer Z Compare X bit_offset: 26 @@ -1255,17 +1244,14 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT - name: TTSET description: Timer T output Set bit_offset: 28 bit_size: 1 - enum: CAPTUREEFFECT - name: TTRST description: Timer T output Reset bit_offset: 29 bit_size: 1 - enum: CAPTUREEFFECT - name: TTCMP description: Timer T Compare X bit_offset: 30 @@ -1273,7 +1259,6 @@ fieldset/TIMXCCR: array: len: 2 stride: 1 - enum: CAPTUREEFFECT fieldset/TIMXCHP: description: Timerx Chopper Register fields: @@ -1348,12 +1333,10 @@ fieldset/TIMXCR: description: Synchronization Resets Timer X bit_offset: 10 bit_size: 1 - enum: SYNCRST - name: SYNCSTRT description: Synchronization Starts Timer X bit_offset: 11 bit_size: 1 - enum: SYNCSTRT - name: DELCMP2 description: Delayed CMP2 mode bit_offset: 12 @@ -1372,26 +1355,13 @@ fieldset/TIMXCR: description: Timer X reset update bit_offset: 18 bit_size: 1 - - name: TAU - description: Timer A update + - name: TU + description: Timer X update bit_offset: 19 bit_size: 1 - - name: TBU - description: Timer B update - bit_offset: 20 - bit_size: 1 - - name: TCU - description: Timer C update - bit_offset: 21 - bit_size: 1 - - name: TDU - description: Timer D update - bit_offset: 22 - bit_size: 1 - - name: TEU - description: Timer E update - bit_offset: 23 - bit_size: 1 + array: + len: 5 + stride: 1 - name: MSTU description: Master Timer update bit_offset: 24 @@ -1516,7 +1486,7 @@ fieldset/TIMXDT: description: Sign Deadtime Rising value bit_offset: 9 bit_size: 1 - enum: SDTR + enum: SDT - name: DTPRSC description: Deadtime Prescaler bit_offset: 10 @@ -1537,7 +1507,7 @@ fieldset/TIMXDT: description: Sign Deadtime Falling value bit_offset: 25 bit_size: 1 - enum: SDTF + enum: SDT - name: DTFSLK description: Deadtime Falling Sign Lock bit_offset: 30 @@ -1574,7 +1544,6 @@ fieldset/TIMXFLT: array: len: 5 stride: 1 - enum: FLTEN - name: FLTLCK description: Fault sources Lock bit_offset: 31 @@ -1677,7 +1646,6 @@ fieldset/TIMXISR: description: Delayed Protection Flag bit_offset: 14 bit_size: 1 - enum: TIMAISR_DLYPRT - name: CPPSTAT description: Current Push Pull Status bit_offset: 16 @@ -1695,7 +1663,6 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum: OUTPUTSTATE - name: OCPY description: Output X Copy bit_offset: 20 @@ -1703,7 +1670,6 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum: OUTPUTSTATE fieldset/TIMXOUTR: description: Timerx Output Register fields: @@ -1732,7 +1698,7 @@ fieldset/TIMXOUTR: offsets: - 0 - 16 - - name: FAULTX + - name: FAULT description: Output X Fault state bit_offset: 4 bit_size: 2 @@ -1798,12 +1764,10 @@ fieldset/TIMXRST: - 25 - 28 - 0 - enum: RESETEFFECT - name: UPDT description: Timer X Update reset bit_offset: 1 bit_size: 1 - enum: RESETEFFECT - name: CMP description: Timer X compare X reset bit_offset: 2 @@ -1811,12 +1775,10 @@ fieldset/TIMXRST: array: len: 2 stride: 1 - enum: RESETEFFECT - name: MSTPER description: Master timer Period bit_offset: 4 bit_size: 1 - enum: RESETEFFECT - name: MSTCMP description: Master compare X bit_offset: 5 @@ -1824,7 +1786,6 @@ fieldset/TIMXRST: array: len: 4 stride: 1 - enum: RESETEFFECT - name: EXTEVNT description: External Event X bit_offset: 9 @@ -1832,7 +1793,6 @@ fieldset/TIMXRST: array: len: 10 stride: 1 - enum: RESETEFFECT - name: TCMP2 description: Timer X compare 2 event bit_offset: 20 @@ -1844,7 +1804,6 @@ fieldset/TIMXRST: - 6 - 9 - 11 - enum: RESETEFFECT - name: TCMP4 description: Timer X compare 4 event bit_offset: 21 @@ -1855,7 +1814,6 @@ fieldset/TIMXRST: - 3 - 6 - 9 - enum: RESETEFFECT fieldset/TIMXRSTR: description: Timerx OutputX Reset Register fields: @@ -1863,17 +1821,14 @@ fieldset/TIMXRSTR: description: Software Reset trigger bit_offset: 0 bit_size: 1 - enum: INACTIVEEFFECT - name: RESYNC description: Timer X resynchronizaton bit_offset: 1 bit_size: 1 - enum: INACTIVEEFFECT - name: PER description: Timer X Period bit_offset: 2 bit_size: 1 - enum: INACTIVEEFFECT - name: CMP description: Timer X compare X bit_offset: 3 @@ -1881,12 +1836,10 @@ fieldset/TIMXRSTR: array: len: 4 stride: 1 - enum: INACTIVEEFFECT - name: MSTPER description: Master Period bit_offset: 7 bit_size: 1 - enum: INACTIVEEFFECT - name: MSTCMP description: Master Compare X bit_offset: 8 @@ -1894,7 +1847,6 @@ fieldset/TIMXRSTR: array: len: 4 stride: 1 - enum: INACTIVEEFFECT - name: TIMEVNT description: Timer Event X bit_offset: 12 @@ -1902,7 +1854,6 @@ fieldset/TIMXRSTR: array: len: 9 stride: 1 - enum: INACTIVEEFFECT - name: EXTEVNT description: External Event X bit_offset: 21 @@ -1910,12 +1861,10 @@ fieldset/TIMXRSTR: array: len: 10 stride: 1 - enum: INACTIVEEFFECT - name: UPDATE description: Registers update (transfer preload to active) bit_offset: 31 bit_size: 1 - enum: INACTIVEEFFECT fieldset/TIMXSETR: description: Timerx OutputX Set Register fields: @@ -1923,17 +1872,14 @@ fieldset/TIMXSETR: description: Software Set trigger bit_offset: 0 bit_size: 1 - enum: ACTIVEEFFECT - name: RESYNC description: Timer X resynchronizaton bit_offset: 1 bit_size: 1 - enum: ACTIVEEFFECT - name: PER description: Timer X Period bit_offset: 2 bit_size: 1 - enum: ACTIVEEFFECT - name: CMP description: Timer X compare X bit_offset: 3 @@ -1941,12 +1887,10 @@ fieldset/TIMXSETR: array: len: 4 stride: 1 - enum: ACTIVEEFFECT - name: MSTPER description: Master Period bit_offset: 7 bit_size: 1 - enum: ACTIVEEFFECT - name: MSTCMPX description: Master Compare X bit_offset: 8 @@ -1954,7 +1898,6 @@ fieldset/TIMXSETR: array: len: 4 stride: 1 - enum: ACTIVEEFFECT - name: TIMEVNT description: Timer Event X bit_offset: 12 @@ -1962,7 +1905,6 @@ fieldset/TIMXSETR: array: len: 9 stride: 1 - enum: ACTIVEEFFECT - name: EXTEVNT description: External Event X bit_offset: 21 @@ -1970,21 +1912,10 @@ fieldset/TIMXSETR: array: len: 10 stride: 1 - enum: ACTIVEEFFECT - name: UPDATE description: Registers update (transfer preload to active) bit_offset: 31 bit_size: 1 - enum: ACTIVEEFFECT -enum/ACTIVEEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetActive - description: Timer event forces the output to its active state - value: 1 enum/BRSTDMA: bit_size: 2 variants: @@ -1997,15 +1928,6 @@ enum/BRSTDMA: - name: Rollover description: Update done on master timer roll-over following a DMA burst transfer completion value: 2 -enum/CAPTUREEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: TriggerCapture - description: Timer event triggers capture - value: 1 enum/CPPSTAT: bit_size: 1 variants: @@ -2138,24 +2060,6 @@ enum/FAULT: - name: SetHighZ description: Output goes to high-z state after a fault event value: 3 -enum/FLTEN: - bit_size: 1 - variants: - - name: Ignored - description: Fault input ignored - value: 0 - - name: Active - description: Fault input is active and can disable HRTIM outputs - value: 1 -enum/INACTIVEEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer event has no effect - value: 0 - - name: SetInactive - description: Timer event forces the output to its inactive state - value: 1 enum/IPPSTAT: bit_size: 1 variants: @@ -2165,15 +2069,6 @@ enum/IPPSTAT: - name: Output2Active description: Protection occurred when the output 2 was active and output 1 forced inactive value: 1 -enum/OUTPUTSTATE: - bit_size: 1 - variants: - - name: Inactive - description: Output is or was inactive - value: 0 - - name: Active - description: Output is or was active - value: 1 enum/POL: bit_size: 1 variants: @@ -2183,32 +2078,14 @@ enum/POL: - name: ActiveLow description: Negative polarity (output active low) value: 1 -enum/RESETEFFECT: - bit_size: 1 - variants: - - name: NoEffect - description: Timer Y compare Z event has no effect - value: 0 - - name: ResetCounter - description: Timer X counter is reset upon timer Y compare Z event - value: 1 -enum/SDTF: - bit_size: 1 - variants: - - name: Positive - description: Positive deadtime on falling edge - value: 0 - - name: Negative - description: Negative deadtime on falling edge - value: 1 -enum/SDTR: +enum/SDT: bit_size: 1 variants: - name: Positive - description: Positive deadtime on rising edge + description: Positive deadtime (both outputs inactive during deadtime) value: 0 - name: Negative - description: Negative deadtime on rising edge + description: Negative deadtime (both outputs active during deadtime) value: 1 enum/SYNCIN: bit_size: 2 @@ -2234,15 +2111,6 @@ enum/SYNCOUT: - name: NegativePulse description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) value: 3 -enum/SYNCRST: - bit_size: 1 - variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Reset - description: Synchronization event resets Timer x - value: 1 enum/SYNCSRC: bit_size: 2 variants: @@ -2258,24 +2126,6 @@ enum/SYNCSRC: - name: TimerACompare1 description: Timer A Compare 1 event value: 3 -enum/SYNCSTRT: - bit_size: 1 - variants: - - name: Disabled - description: Synchronization event has no effect on Timer x - value: 0 - - name: Start - description: Synchronization event starts Timer x - value: 1 -enum/TIMAISR_DLYPRT: - bit_size: 1 - variants: - - name: Inactive - description: Not in delayed idle or balanced idle mode - value: 0 - - name: Active - description: Delayed idle or balanced idle mode entry - value: 1 enum/UPDGAT: bit_size: 4 variants: diff --git a/data/registers/otg_v1.yaml b/data/registers/otg_v1.yaml index ac9d980ba..36038f3d7 100644 --- a/data/registers/otg_v1.yaml +++ b/data/registers/otg_v1.yaml @@ -1,5 +1,5 @@ block/OTG: - description: USB on the go + description: USB OTG core by Synopsys (more docs at ) items: - name: GOTGCTL description: Control and status register @@ -76,10 +76,35 @@ block/OTG: description: Core ID register byte_offset: 60 fieldset: CID + - name: SNPSID + description: Synopsis ID Register + byte_offset: 64 + - name: HWCFG1 + description: User HW Config 1 Register + byte_offset: 68 + - name: HWCFG2 + description: User HW Config 2 Register + byte_offset: 72 + - name: HWCFG3 + description: User HW Config 3 Register + byte_offset: 76 + - name: HWCFG4 + description: User HW Config 4 Register + byte_offset: 80 - name: GLPMCFG description: OTG core LPM configuration register byte_offset: 84 fieldset: GLPMCFG + - name: GPWRDN + description: Global PowerDn Register + byte_offset: 88 + - name: GDFIFOCFG + description: Global DFIFO SW Config Register + byte_offset: 92 + - name: ADPCTL + description: ADP (Attach Detection Protocol) Control Register + byte_offset: 96 + fieldset: ADPCTL - name: HPTXFSIZ description: Host periodic transmit FIFO size register byte_offset: 256 @@ -117,6 +142,9 @@ block/OTG: description: Host all channels interrupt mask register byte_offset: 1048 fieldset: HAINTMSK + - name: HFLBADDR + description: Host Frame Scheduling List Register + byte_offset: 1052 - name: HPRT description: Host port control and status register byte_offset: 1088 @@ -155,6 +183,19 @@ block/OTG: stride: 32 byte_offset: 1296 fieldset: HCTSIZ + - name: HCDMA + description: Host channel DMA address register (config for scatter/gather) + array: + len: 12 + stride: 32 + byte_offset: 1300 + fieldset: HCDMA + - name: HCDMAB + description: Host channel DMA address register (address for current transfer; debug) + array: + len: 12 + stride: 32 + byte_offset: 1308 - name: DCFG description: Device configuration register byte_offset: 2048 @@ -247,6 +288,12 @@ block/OTG: stride: 32 byte_offset: 2832 fieldset: DOEPTSIZ + - name: DOEPDMA + description: Device OUT/IN endpoint DMA address register + array: + len: 16 + stride: 32 + byte_offset: 2836 - name: PCGCCTL description: Power and clock gating control register byte_offset: 3584 @@ -1048,6 +1095,10 @@ fieldset/GINTSTS: description: Data fetch suspended bit_offset: 22 bit_size: 1 + - name: RESETDET + description: Reset detected + bit_offset: 23 + bit_size: 1 - name: HPRTINT description: Host port interrupt bit_offset: 24 @@ -1139,6 +1190,65 @@ fieldset/GLPMCFG: description: Enable best effort service latency bit_offset: 28 bit_size: 1 +fieldset/ADPCTL: + description: ADP (Attach Detection Protocol) Control Register + fields: + - name: PRB_DSCHG + description: Probe Discharge time (times for TADP_DSCHG) + bit_offset: 0 + bit_size: 2 + - name: PRB_DELTA + description: Probe Delta (resolution for RTIM) + bit_offset: 2 + bit_size: 2 + - name: PRB_PER + description: Probe Period (TADP_PRD) + bit_offset: 4 + bit_size: 2 + - name: RTIM + description: Probe Period (TADP_PRD) + bit_offset: 6 + bit_size: 11 + - name: ENAPRB + description: Enable Probe + bit_offset: 17 + bit_size: 1 + - name: ENASNS + description: Enable Sense + bit_offset: 18 + bit_size: 1 + - name: ADPRES + description: ADP Reset + bit_offset: 19 + bit_size: 1 + - name: ADPEN + description: ADP Enable + bit_offset: 20 + bit_size: 1 + - name: ADP_PRB_INT + description: ADP Probe Interrupt Enable + bit_offset: 21 + bit_size: 1 + - name: ADP_SNS_INT + description: ADP Sense Interrupt Enable + bit_offset: 22 + bit_size: 1 + - name: ADP_TMOUT_INT + description: ADP Timeout Interrupt Enable + bit_offset: 23 + bit_size: 1 + - name: ADP_PRB_MSK + description: ADP Probe Interrupt Mask + bit_offset: 24 + bit_size: 1 + - name: ADP_TMOUT_MSK + description: ADP Timeout Interrupt Mask + bit_offset: 25 + bit_size: 1 + - name: AR + description: Access Request + bit_offset: 26 + bit_size: 1 fieldset/GOTGCTL: description: Control and status register fields: @@ -1435,7 +1545,7 @@ fieldset/HCCHAR: bit_offset: 22 bit_size: 7 - name: ODDFRM - description: Odd frame + description: Odd frame (request iso/interrupt transaction to be performed on odd micro-frame) bit_offset: 29 bit_size: 1 - name: CHDIS @@ -1457,6 +1567,19 @@ fieldset/HCFG: description: FS- and LS-only support bit_offset: 2 bit_size: 1 + - name: DESCDMA + description: Descriptor DMA-mode enable (qtd) + bit_offset: 23 + bit_size: 1 + - name: FRLISTLEN + description: Frame list length + bit_offset: 24 + bit_size: 2 + enum: FRLISTLEN + - name: PERSCHEDENA + description: Period scheduling enable + bit_offset: 26 + bit_size: 1 fieldset/HCINT: description: Host channel interrupt register fields: @@ -1543,7 +1666,7 @@ fieldset/HCTSIZ: description: Host channel transfer size register fields: - name: XFRSIZ - description: Transfer size + description: Transfer size for non-isochronuous/interrupt pipes bit_offset: 0 bit_size: 19 - name: PKTCNT @@ -1554,6 +1677,29 @@ fieldset/HCTSIZ: description: Data PID bit_offset: 29 bit_size: 2 + - name: NTDL + description: NTD descriptor list length for isochronuous & interrupt pipes (xfrsiz[15:8], note val+1 is actual length) + bit_offset: 8 + bit_size: 8 + - name: SCHEDINFO + description: Schedule info for isochronuous & interrupt pipes (xfrsiz[7:0]) + bit_offset: 0 + bit_size: 8 + - name: DOPING + description: Do Ping + bit_offset: 31 + bit_size: 1 +fieldset/HCDMA: + description: Host channel DMA config register + fields: + - name: CQTD + description: Current QTD (transfer descriptor) index + bit_offset: 3 + bit_size: 6 + - name: QTDADDR + description: QTD list base address + bit_offset: 0 + bit_size: 32 fieldset/HFIR: description: Host frame interval register fields: @@ -1561,6 +1707,10 @@ fieldset/HFIR: description: Frame interval bit_offset: 0 bit_size: 16 + - name: RLDCTRL + description: Dynamic Loading Control + bit_offset: 16 + bit_size: 1 fieldset/HFNUM: description: Host frame number/frame time remaining register fields: @@ -1599,7 +1749,7 @@ fieldset/HPRT: bit_offset: 1 bit_size: 1 - name: PENA - description: Port enable + description: Port enable (W1C) bit_offset: 2 bit_size: 1 - name: PENCHNG @@ -1721,6 +1871,21 @@ enum/PFIVL: - name: FRAME_INTERVAL_95 description: 95% of the frame interval value: 3 +enum/FRLISTLEN: + bit_size: 2 + variants: + - name: LEN8 + description: Length = 8 + value: 0 + - name: LEN16 + description: Length = 16 + value: 1 + - name: LEN32 + description: Length = 32 + value: 2 + - name: LEN64 + description: Length = 64 + value: 3 enum/PKTSTSD: bit_size: 4 variants: diff --git a/data/registers/pwr_u5.yaml b/data/registers/pwr_u5.yaml index 640c77eab..c57af87fe 100644 --- a/data/registers/pwr_u5.yaml +++ b/data/registers/pwr_u5.yaml @@ -467,6 +467,10 @@ fieldset/UCPDR: fieldset/VOSR: description: voltage scaling register fields: + - name: USBBOOSTRDY + description: "OTG_HS EPOD booster ready\r This bit is set to one by hardware when the power booster startup time is reached. The OTG_HS clock can be provided only after this bit is set." + bit_offset: 13 + bit_size: 1 - name: BOOSTRDY description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set." bit_offset: 14 @@ -484,6 +488,18 @@ fieldset/VOSR: description: EPOD booster enable bit_offset: 18 bit_size: 1 + - name: USBPWREN + description: OTG_HS power enable + bit_offset: 19 + bit_size: 1 + - name: USBBOOSTEN + description: OTG_HS EPOD booster enable + bit_offset: 20 + bit_size: 1 + - name: VDD11USBDIS + description: OTG_HS VDD11USB disable + bit_offset: 21 + bit_size: 1 fieldset/WUCR1: description: wakeup control register 1 fields: diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 5b291e64d..829a66409 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -567,8 +567,8 @@ fieldset/APB1ENR: description: SPI3 clock enable bit_offset: 15 bit_size: 1 - - name: SPDIFEN - description: SPDIF-IN clock enable + - name: SPDIFRXEN + description: SPDIF-Rx clock enable bit_offset: 16 bit_size: 1 - name: USART2EN @@ -817,8 +817,8 @@ fieldset/APB1RSTR: description: SPI 3 reset bit_offset: 15 bit_size: 1 - - name: SPDIFRST - description: SPDIF-IN reset + - name: SPDIFRXRST + description: SPDIF-Rx reset bit_offset: 16 bit_size: 1 - name: USART2RST diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 9a226d740..01904088c 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2631,8 +2631,8 @@ enum/LPTIM2SEL: enum/LPTIMSEL: bit_size: 2 variants: - - name: PCLK3 - description: PCLK3 selected + - name: MSIK + description: MSIK selected value: 0 - name: LSI description: LSI selected diff --git a/data/registers/syscfg_u5.yaml b/data/registers/syscfg_u5.yaml index c5cdf3ee0..c20189060 100644 --- a/data/registers/syscfg_u5.yaml +++ b/data/registers/syscfg_u5.yaml @@ -50,6 +50,14 @@ block/SYSCFG: description: USB Type C and Power Delivery register byte_offset: 112 fieldset: UCPDR + - name: OTGHSPHYCR + description: OTG_HS PHY register + byte_offset: 116 + fieldset: OTGHSPHYCR + - name: OTGHSPHYTUNER2 + description: OTG_HS PHY tune register 2 + byte_offset: 124 + fieldset: OTGHSPHYTUNER2 fieldset/CCCR: description: compensation cell code register fields: @@ -238,3 +246,55 @@ fieldset/UCPDR: description: CC2ENRXFILTER bit_offset: 1 bit_size: 1 +fieldset/OTGHSPHYCR: + description: OTG_HS PHY register + fields: + - name: EN + description: PHY Enable + bit_offset: 0 + bit_size: 1 + - name: PDCTRL + description: Common block power-down control + bit_offset: 1 + bit_size: 1 + - name: CLKSEL + description: Reference clock frequency selection + bit_offset: 2 + bit_size: 4 + enum: USBREFCKSEL +fieldset/OTGHSPHYTUNER2: + description: OTG_HS tune register 2 + fields: + - name: COMPDISTUNE + description: Disconnect threshold adjustment + bit_offset: 0 + bit_size: 3 + - name: SQRXTUNE + description: Squelch threshold adjustment + bit_offset: 4 + bit_size: 3 + - name: TXPREEMPAMPTUNE + description: HS transmitter preemphasis current control + bit_offset: 13 + bit_size: 2 +enum/USBREFCKSEL: + bit_size: 4 + variants: + - name: Mhz16 + description: The kernel clock frequency provided to the OTG_HS PHY is 16 MHz. + value: 3 + - name: Mhz19_2 + description: The kernel clock frequency provided to the OTG_HS PHY is 19.2 MHz. + value: 8 + - name: Mhz20 + description: The kernel clock frequency provided to the OTG_HS PHY is 20MHz. + value: 9 + - name: Mhz24 + description: The kernel clock frequency provided to the OTG_HS PHY is 24 MHz (default after reset). + value: 10 + - name: Mhz32 + description: The kernel clock frequency provided to the OTG_HS PHY is 32 MHz. + value: 11 + - name: Mhz26 + description: The kernel clock frequency provided to the OTG_HS PHY is 26 MHz. + value: 14 diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 55819e57f..3ce688026 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -1948,6 +1948,42 @@ enum/TS: - name: ETRF description: External Trigger input value: 7 + - name: ITR4 + description: Internal Trigger 4 + value: 8 + - name: ITR5 + description: Internal Trigger 5 + value: 9 + - name: ITR6 + description: Internal Trigger 6 + value: 10 + - name: ITR7 + description: Internal Trigger 7 + value: 11 + - name: ITR8 + description: Internal Trigger 8 + value: 12 + - name: ITR9 + description: Internal Trigger 9 + value: 13 + - name: ITR10 + description: Internal Trigger 10 + value: 14 + - name: ITR11 + description: Internal Trigger 11 + value: 15 + - name: ITR12 + description: Internal Trigger 12 + value: 16 + - name: ITR13 + description: Internal Trigger 13 + value: 17 + - name: ITR14 + description: Internal Trigger 14 + value: 18 + - name: ITR15 + description: Internal Trigger 15 + value: 19 enum/URS: bit_size: 1 variants: diff --git a/data/registers/ucpd_h5.yaml b/data/registers/ucpd_h5.yaml new file mode 100644 index 000000000..64dac5865 --- /dev/null +++ b/data/registers/ucpd_h5.yaml @@ -0,0 +1,582 @@ +block/UCPD: + description: USB Power Delivery interface + items: + - name: CFGR1 + description: configuration register 1 + byte_offset: 0 + fieldset: CFGR1 + - name: CFGR2 + description: configuration register 2 + byte_offset: 4 + fieldset: CFGR2 + - name: CFGR3 + description: configuration register 3 + byte_offset: 8 + fieldset: CFGR3 + - name: CR + description: control register + byte_offset: 12 + fieldset: CR + - name: IMR + description: interrupt mask register + byte_offset: 16 + fieldset: IMR + - name: SR + description: status register + byte_offset: 20 + fieldset: SR + - name: ICR + description: interrupt clear register + byte_offset: 24 + fieldset: ICR + - name: TX_ORDSETR + description: Tx ordered set type register + byte_offset: 28 + fieldset: TX_ORDSETR + - name: TX_PAYSZR + description: Tx payload size register + byte_offset: 32 + fieldset: TX_PAYSZR + - name: TXDR + description: Tx data register + byte_offset: 36 + fieldset: TXDR + - name: RX_ORDSETR + byte_offset: 40 + fieldset: RX_ORDSETR + - name: RX_PAYSZR + byte_offset: 44 + fieldset: RX_PAYSZR + - name: RXDR + byte_offset: 48 + fieldset: RXDR + - name: RX_ORDEXTR1 + description: Rx ordered set extension register 1 + byte_offset: 52 + fieldset: RX_ORDEXTR1 + - name: RX_ORDEXTR2 + description: Rx ordered set extension register 2 + byte_offset: 56 + fieldset: RX_ORDEXTR2 +fieldset/CFGR1: + description: configuration register 1 + fields: + - name: HBITCLKDIV + description: "Division ratio for producing half-bit clock\r The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk)." + bit_offset: 0 + bit_size: 6 + - name: IFRGAP + description: "Division ratio for producing inter-frame gap timer clock\r The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap).\r The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal." + bit_offset: 6 + bit_size: 5 + - name: TRANSWIN + description: "Transition window duration\r The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval.\r Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting." + bit_offset: 11 + bit_size: 5 + - name: PSC_USBPDCLK + description: "Pre-scaler division ratio for generating clk\r The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk).\r It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz." + bit_offset: 17 + bit_size: 3 + enum: PSC_USBPDCLK + - name: RXORDSETEN + description: "Receiver ordered set enable\r The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function:\r 0bxxxxxxxx1: SOP detect enabled\r 0bxxxxxxx1x: SOP' detect enabled\r 0bxxxxxx1xx: SOP'' detect enabled\r 0bxxxxx1xxx: Hard Reset detect enabled\r 0bxxxx1xxxx: Cable Detect reset enabled\r 0bxxx1xxxxx: SOP'_Debug enabled\r 0bxx1xxxxxx: SOP''_Debug enabled\r 0bx1xxxxxxx: SOP extension#1 enabled\r 0b1xxxxxxxx: SOP extension#2 enabled" + bit_offset: 20 + bit_size: 9 + - name: TXDMAEN + description: "Transmission DMA mode enable\r When set, the bit enables DMA mode for transmission." + bit_offset: 29 + bit_size: 1 + - name: RXDMAEN + description: "Reception DMA mode enable\r When set, the bit enables DMA mode for reception." + bit_offset: 30 + bit_size: 1 + - name: UCPDEN + description: "peripheral enable\r General enable of the peripheral.\r Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state." + bit_offset: 31 + bit_size: 1 +fieldset/CFGR2: + description: configuration register 2 + fields: + - name: RXFILTDIS + description: "BMC decoder Rx pre-filter enable\r The sampling clock is that of the receiver (that is, after pre-scaler)." + bit_offset: 0 + bit_size: 1 + - name: RXFILT2N3 + description: "BMC decoder Rx pre-filter sampling method\r Number of consistent consecutive samples before confirming a new value." + bit_offset: 1 + bit_size: 1 + - name: FORCECLK + description: Force ClkReq clock request + bit_offset: 2 + bit_size: 1 + - name: WUPEN + description: "Wakeup from Stop mode enable\r Setting the bit enables the ASYNC_INT signal." + bit_offset: 3 + bit_size: 1 + - name: RXAFILTEN + description: "Rx analog filter enable\r Setting the bit enables the Rx analog filter required for optimum Power Delivery reception." + bit_offset: 8 + bit_size: 1 +fieldset/CFGR3: + description: configuration register 3 + fields: + - name: TRIM_CC1_RD + description: SW trim value for Rd resistor on the CC1 line + bit_offset: 0 + bit_size: 4 + - name: TRIM_CC1_RP + description: SW trim value for Rp current sources on the CC1 line + bit_offset: 9 + bit_size: 4 + - name: TRIM_CC2_RD + description: SW trim value for Rd resistor on the CC2 line + bit_offset: 16 + bit_size: 4 + - name: TRIM_CC2_RP + description: SW trim value for Rp current sources on the CC2 line + bit_offset: 25 + bit_size: 4 +fieldset/CR: + description: control register + fields: + - name: TXMODE + description: "Type of Tx packet\r Writing the bitfield triggers the action as follows, depending on the value:\r Others: invalid\r From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)." + bit_offset: 0 + bit_size: 2 + enum: TXMODE + - name: TXSEND + description: "Command to send a Tx packet\r The bit is cleared by hardware as soon as the packet transmission begins or is discarded." + bit_offset: 2 + bit_size: 1 + - name: TXHRST + description: "Command to send a Tx Hard Reset\r The bit is cleared by hardware as soon as the message transmission begins or is discarded." + bit_offset: 3 + bit_size: 1 + - name: RXMODE + description: "Receiver mode\r Determines the mode of the receiver.\r When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message." + bit_offset: 4 + bit_size: 1 + - name: PHYRXEN + description: "USB Power Delivery receiver enable\r Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set." + bit_offset: 5 + bit_size: 1 + - name: PHYCCSEL + description: "CC1/CC2 line selector for USB Power Delivery signaling\r The selection depends on the cable orientation as discovered at attach." + bit_offset: 6 + bit_size: 1 + enum: PHYCCSEL + - name: ANASUBMODE + description: "Analog PHY sub-mode\r Refer to TYPEC_VSTATE_CCx for the effect of this bitfield." + bit_offset: 7 + bit_size: 2 + - name: ANAMODE + description: "Analog PHY operating mode\r The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]." + bit_offset: 9 + bit_size: 1 + enum: ANAMODE + - name: CCENABLE + description: "CC line enable\r This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting.\r A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source." + bit_offset: 10 + bit_size: 2 + enum: CCENABLE + - name: FRSRXEN + description: "FRS event detection enable\r Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable\r Clear the bit when the device is attached to an FRS-incapable source/sink." + bit_offset: 16 + bit_size: 1 + - name: FRSTX + description: "FRS Tx signaling enable.\r Setting the bit enables FRS Tx signaling.\r The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0." + bit_offset: 17 + bit_size: 1 + - name: RDCH + description: "Rdch condition drive\r The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE[1:0] bitfield must be set accordingly, too." + bit_offset: 18 + bit_size: 1 + - name: CC1TCDIS + description: "CC1 Type-C detector disable\r The bit disables the Type-C detector on the CC1 line.\r When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]." + bit_offset: 20 + bit_size: 1 + - name: CC2TCDIS + description: "CC2 Type-C detector disable\r The bit disables the Type-C detector on the CC2 line.\r When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]." + bit_offset: 21 + bit_size: 1 +fieldset/ICR: + description: interrupt clear register + fields: + - name: TXMSGDISCCF + description: "Tx message discard flag (TXMSGDISC) clear\r Setting the bit clears the TXMSGDISC flag in the SR register." + bit_offset: 1 + bit_size: 1 + - name: TXMSGSENTCF + description: "Tx message send flag (TXMSGSENT) clear\r Setting the bit clears the TXMSGSENT flag in the SR register." + bit_offset: 2 + bit_size: 1 + - name: TXMSGABTCF + description: "Tx message abort flag (TXMSGABT) clear\r Setting the bit clears the TXMSGABT flag in the SR register." + bit_offset: 3 + bit_size: 1 + - name: HRSTDISCCF + description: "Hard reset discard flag (HRSTDISC) clear\r Setting the bit clears the HRSTDISC flag in the SR register." + bit_offset: 4 + bit_size: 1 + - name: HRSTSENTCF + description: "Hard reset send flag (HRSTSENT) clear\r Setting the bit clears the HRSTSENT flag in the SR register." + bit_offset: 5 + bit_size: 1 + - name: TXUNDCF + description: "Tx underflow flag (TXUND) clear\r Setting the bit clears the TXUND flag in the SR register." + bit_offset: 6 + bit_size: 1 + - name: RXORDDETCF + description: "Rx ordered set detect flag (RXORDDET) clear\r Setting the bit clears the RXORDDET flag in the SR register." + bit_offset: 9 + bit_size: 1 + - name: RXHRSTDETCF + description: "Rx Hard Reset detect flag (RXHRSTDET) clear\r Setting the bit clears the RXHRSTDET flag in the SR register." + bit_offset: 10 + bit_size: 1 + - name: RXOVRCF + description: "Rx overflow flag (RXOVR) clear\r Setting the bit clears the RXOVR flag in the SR register." + bit_offset: 11 + bit_size: 1 + - name: RXMSGENDCF + description: "Rx message received flag (RXMSGEND) clear\r Setting the bit clears the RXMSGEND flag in the SR register." + bit_offset: 12 + bit_size: 1 + - name: TYPECEVT1CF + description: "Type-C CC1 event flag (TYPECEVT1) clear\r Setting the bit clears the TYPECEVT1 flag in the SR register" + bit_offset: 14 + bit_size: 1 + - name: TYPECEVT2CF + description: "Type-C CC2 line event flag (TYPECEVT2) clear\r Setting the bit clears the TYPECEVT2 flag in the SR register" + bit_offset: 15 + bit_size: 1 + - name: FRSEVTCF + description: "FRS event flag (FRSEVT) clear\r Setting the bit clears the FRSEVT flag in the SR register." + bit_offset: 20 + bit_size: 1 +fieldset/IMR: + description: interrupt mask register + fields: + - name: TXISIE + description: TXIS interrupt enable + bit_offset: 0 + bit_size: 1 + - name: TXMSGDISCIE + description: TXMSGDISC interrupt enable + bit_offset: 1 + bit_size: 1 + - name: TXMSGSENTIE + description: TXMSGSENT interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TXMSGABTIE + description: TXMSGABT interrupt enable + bit_offset: 3 + bit_size: 1 + - name: HRSTDISCIE + description: HRSTDISC interrupt enable + bit_offset: 4 + bit_size: 1 + - name: HRSTSENTIE + description: HRSTSENT interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TXUNDIE + description: TXUND interrupt enable + bit_offset: 6 + bit_size: 1 + - name: RXNEIE + description: RXNE interrupt enable + bit_offset: 8 + bit_size: 1 + - name: RXORDDETIE + description: RXORDDET interrupt enable + bit_offset: 9 + bit_size: 1 + - name: RXHRSTDETIE + description: RXHRSTDET interrupt enable + bit_offset: 10 + bit_size: 1 + - name: RXOVRIE + description: RXOVR interrupt enable + bit_offset: 11 + bit_size: 1 + - name: RXMSGENDIE + description: RXMSGEND interrupt enable + bit_offset: 12 + bit_size: 1 + - name: TYPECEVT1IE + description: TYPECEVT1 interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TYPECEVT2IE + description: TYPECEVT2 interrupt enable + bit_offset: 15 + bit_size: 1 + - name: FRSEVTIE + description: FRSEVT interrupt enable + bit_offset: 20 + bit_size: 1 +fieldset/RXDR: + fields: + - name: RXDATA + description: Data byte received + bit_offset: 0 + bit_size: 8 +fieldset/RX_ORDEXTR1: + description: Rx ordered set extension register 1 + fields: + - name: RXSOPX1 + description: "Ordered set 1 received\r The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last." + bit_offset: 0 + bit_size: 20 +fieldset/RX_ORDEXTR2: + description: Rx ordered set extension register 2 + fields: + - name: RXSOPX2 + description: "Ordered set 2 received\r The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last." + bit_offset: 0 + bit_size: 20 +fieldset/RX_ORDSETR: + fields: + - name: RXORDSET + description: Rx ordered set code detected + bit_offset: 0 + bit_size: 3 + enum: RXORDSET + - name: RXSOP3OF4 + description: The bit indicates the number of correct K‑codes. For debug purposes only. + bit_offset: 3 + bit_size: 1 + - name: RXSOPKINVALID + description: "The bitfield is for debug purposes only.\r Others: Invalid" + bit_offset: 4 + bit_size: 3 + enum: RXSOPKINVALID +fieldset/RX_PAYSZR: + fields: + - name: RXPAYSZ + description: "Rx payload size received\r This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled).\r The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low)." + bit_offset: 0 + bit_size: 10 +fieldset/SR: + description: status register + fields: + - name: TXIS + description: "Transmit interrupt status\r The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register." + bit_offset: 0 + bit_size: 1 + - name: TXMSGDISC + description: "Message transmission discarded\r The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit.\r Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle." + bit_offset: 1 + bit_size: 1 + - name: TXMSGSENT + description: "Message transmission completed\r The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit.\r In the event of a message transmission interrupted by a Hard Reset, the flag is not raised." + bit_offset: 2 + bit_size: 1 + - name: TXMSGABT + description: "Transmit message abort\r The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit." + bit_offset: 3 + bit_size: 1 + - name: HRSTDISC + description: "Hard Reset discarded\r The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit." + bit_offset: 4 + bit_size: 1 + - name: HRSTSENT + description: "Hard Reset message sent\r The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit." + bit_offset: 5 + bit_size: 1 + - name: TXUND + description: "Tx data underrun detection\r The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit." + bit_offset: 6 + bit_size: 1 + - name: RXNE + description: "Receive data register not empty detection\r The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR." + bit_offset: 8 + bit_size: 1 + - name: RXORDDET + description: "Rx ordered set (4 K-codes) detection\r The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit." + bit_offset: 9 + bit_size: 1 + - name: RXHRSTDET + description: "Rx Hard Reset receipt detection\r The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit." + bit_offset: 10 + bit_size: 1 + - name: RXOVR + description: "Rx data overflow detection\r The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit.\r The buffer overflow can occur if the received data are not read fast enough." + bit_offset: 11 + bit_size: 1 + - name: RXMSGEND + description: "Rx message received\r The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit.\r The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message." + bit_offset: 12 + bit_size: 1 + - name: RXERR + description: "Receive message error\r The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set." + bit_offset: 13 + bit_size: 1 + - name: TYPECEVT1 + description: "Type-C voltage level event on CC1 line\r The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit." + bit_offset: 14 + bit_size: 1 + - name: TYPECEVT2 + description: "Type-C voltage level event on CC2 line\r The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit." + bit_offset: 15 + bit_size: 1 + - name: TYPEC_VSTATE_CC1 + description: "The status bitfield indicates the voltage level on the CC1 line in its steady state.\r The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value." + bit_offset: 16 + bit_size: 2 + enum: TYPEC_VSTATE_CC + - name: TYPEC_VSTATE_CC2 + description: "CC2 line voltage level\r The status bitfield indicates the voltage level on the CC2 line in its steady state.\r The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value." + bit_offset: 18 + bit_size: 2 + enum: TYPEC_VSTATE_CC + - name: FRSEVT + description: "FRS detection event\r The flag is cleared by setting the FRSEVTCF bit." + bit_offset: 20 + bit_size: 1 +fieldset/TXDR: + description: Tx data register + fields: + - name: TXDATA + description: Data byte to transmit + bit_offset: 0 + bit_size: 8 +fieldset/TX_ORDSETR: + description: Tx ordered set type register + fields: + - name: TXORDSET + description: "Ordered set to transmit\r The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last." + bit_offset: 0 + bit_size: 20 +fieldset/TX_PAYSZR: + description: Tx payload size register + fields: + - name: TXPAYSZ + description: "Payload size yet to transmit\r The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission." + bit_offset: 0 + bit_size: 10 +enum/ANAMODE: + bit_size: 1 + variants: + - name: Source + description: Source + value: 0 + - name: Sink + description: Sink + value: 1 +enum/CCENABLE: + bit_size: 2 + variants: + - name: Disabled + description: Disable both PHYs + value: 0 + - name: Cc1 + description: Enable CC1 PHY + value: 1 + - name: Cc2 + description: Enable CC2 PHY + value: 2 + - name: Both + description: Enable CC1 and CC2 PHY + value: 3 +enum/PHYCCSEL: + bit_size: 1 + variants: + - name: Cc1 + description: Use CC1 IO for Power Delivery communication + value: 0 + - name: Cc2 + description: Use CC2 IO for Power Delivery communication + value: 1 +enum/PSC_USBPDCLK: + bit_size: 3 + variants: + - name: Div1 + description: 1 (bypass) + value: 0 + - name: Div2 + description: '2' + value: 1 + - name: Div4 + description: '4' + value: 2 + - name: Div8 + description: '8' + value: 3 + - name: Div16 + description: '16' + value: 4 +enum/RXORDSET: + bit_size: 3 + variants: + - name: Sop + description: SOP code detected in receiver + value: 0 + - name: SopPrime + description: SOP' code detected in receiver + value: 1 + - name: SopDoublePrime + description: SOP'' code detected in receiver + value: 2 + - name: SopPrimeDebug + description: SOP'_Debug detected in receiver + value: 3 + - name: SopDoublePrimeDebug + description: SOP''_Debug detected in receiver + value: 4 + - name: CableReset + description: Cable Reset detected in receiver + value: 5 + - name: Ext1 + description: SOP extension#1 detected in receiver + value: 6 + - name: Ext2 + description: SOP extension#2 detected in receiver + value: 7 +enum/RXSOPKINVALID: + bit_size: 3 + variants: + - name: None + description: No K‑code corrupted + value: 0 + - name: First + description: First K‑code corrupted + value: 1 + - name: Second + description: Second K‑code corrupted + value: 2 + - name: Third + description: Third K‑code corrupted + value: 3 + - name: Fourth + description: Fourth K‑code corrupted + value: 4 +enum/TXMODE: + bit_size: 2 + variants: + - name: Packet + description: Transmission of Tx packet previously defined in other registers + value: 0 + - name: CableReset + description: Cable Reset sequence + value: 1 + - name: Bist + description: BIST test sequence (BIST Carrier Mode 2) + value: 2 +enum/TYPEC_VSTATE_CC: + bit_size: 2 + variants: + - name: Lowest + description: Lowest + value: 0 + - name: Low + description: Low + value: 1 + - name: High + description: High + value: 2 + - name: Highest + description: Highest + value: 3 diff --git a/rust-toolchain.toml b/rust-toolchain.toml index 6392e0ae8..393e156ce 100644 --- a/rust-toolchain.toml +++ b/rust-toolchain.toml @@ -1,5 +1,5 @@ [toolchain] -channel = "nightly-2023-12-20" +channel = "nightly-2024-09-06" components = [ "rust-src", "rustfmt" ] targets = [ "thumbv6m-none-eabi", diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs index 6cdc6538d..269845bf4 100644 --- a/stm32-data-gen/src/header.rs +++ b/stm32-data-gen/src/header.rs @@ -185,7 +185,7 @@ impl Defines { &["ADC1_COMMON_BASE", "ADC_COMMON_BASE", "ADC1_COMMON", "ADC_COMMON"], ), ("CAN", &["CAN_BASE", "CAN1_BASE"]), - ("FMC", &["FMC_BASE", "FMC_R_BASE"]), + ("FMC", &["FMC_R_BASE", "FMC_R_BASE_NS"]), ("FSMC", &["FSMC_R_BASE"]), ("USB", &["USB_BASE", "USB_DRD_BASE", "USB_BASE_NS", "USB_DRD_BASE_NS"]), ( diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs index 5c691b276..e8f937955 100644 --- a/stm32-data-gen/src/memory.rs +++ b/stm32-data-gen/src/memory.rs @@ -62,6 +62,8 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[ ("STM32C01..6", mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 6 })), ("STM32C03..4", mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 12 })), ("STM32C03..6", mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 12 })), + ("STM32C07..8", mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 24 })), + ("STM32C07..B", mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 24 })), // F0 ("STM32F0...C", mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 32 })), ("STM32F0[35]..8", mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 })), @@ -347,8 +349,7 @@ static FLASH_INFO: RegexMap = RegexMap::new(&[ ("STM32L1.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 256, 0)] }), ("STM32L5.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }), ("STM32U0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }), - ("STM32U5[78].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }), - ("STM32U5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 16*1024, 0)] }), + ("STM32U5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }), ("STM32WBA.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }), ("STM32WB1.*", FlashInfo{ erase_value: 0x00, write_size: 8, erase_size: &[( 2*1024, 0)] }), ("STM32WB.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }), diff --git a/stm32-data-gen/src/perimap.rs b/stm32-data-gen/src/perimap.rs index 2248a2c29..037c178b3 100644 --- a/stm32-data-gen/src/perimap.rs +++ b/stm32-data-gen/src/perimap.rs @@ -74,6 +74,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ (".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1U5", ("i2c", "v2", "I2C")), (".*:I2C:i2c1_v1_0H7RS", ("i2c", "v3", "I2C")), + (".*:FMPI2C:i2c2_v1_1", ("fmpi2c", "v2", "FMPI2C")), ("STM32F10[1357].*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), // Original F1 are v1 (".*:DAC:dacif_v1_1F1", ("dac", "v2", "DAC")), (".*:DAC:F0dacif_v1_1", ("dac", "v2", "DAC")), @@ -99,6 +100,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ (".*:ADC:aditf5_v2_2", ("adc", "v3", "ADC")), (".*:ADC:aditf5_v3_0", ("adc", "v4", "ADC")), (".*:ADC:aditf5_v3_0_H5", ("adc", "h5", "ADC")), + (".*:ADC:aditf512_v3_0_H5", ("adc", "h5", "ADC")), (".*:ADC:aditf5_v3_1", ("adc", "v4", "ADC")), (".*:ADC:aditf5_40v2_U5", ("adc", "u5", "ADC")), (".*:ADC:aditf5_40v1_U5", ("adc", "u5", "ADC")), @@ -459,6 +461,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ ("STM32L4.*:DBGMCU:.*", ("dbgmcu", "l4", "DBGMCU")), ("STM32L5.*:DBGMCU:.*", ("dbgmcu", "l5", "DBGMCU")), ("STM32U5.*:DBGMCU:.*", ("dbgmcu", "u5", "DBGMCU")), + ("STM32U0.*:DBGMCU:.*", ("dbgmcu", "u0", "DBGMCU")), ("STM32WBA.*:DBGMCU:.*", ("dbgmcu", "wba", "DBGMCU")), ("STM32WB.*:DBGMCU:.*", ("dbgmcu", "wb", "DBGMCU")), ("STM32WL.*:DBGMCU:.*", ("dbgmcu", "wl", "DBGMCU")), @@ -508,6 +511,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[ (".*:LCD:lcdc1_v1.3.*", ("lcd", "v2", "LCD")), (".*:LCD:lcdc1_v1.4.*", ("lcd", "v2", "LCD")), (".*:UID:.*", ("uid", "v1", "UID")), + ("STM32H5.*:UCPD:.*", ("ucpd", "h5", "UCPD")), (".*:UCPD:.*", ("ucpd", "v1", "UCPD")), ("STM32G0.*:TAMP:.*", ("tamp", "g0", "TAMP")), ("STM32G4.*:TAMP:.*", ("tamp", "g4", "TAMP")), diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index 81833428b..124432063 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -305,7 +305,7 @@ impl ParsedRccs { ("I2C5", &["I2C1235"]), ("USB", &["USB", "CLK48", "ICLK"]), ("USB_OTG_FS", &["USB", "CLK48", "ICLK"]), - ("USB_OTG_HS", &["USB", "USBPHYC", "CLK48", "ICLK"]), + ("USB_OTG_HS", &["USB", "USBPHYC", "OTGHS", "CLK48", "ICLK"]), ]; let rcc = self.rccs.get(rcc_version)?;