diff --git a/data/registers/adc_u5.yaml b/data/registers/adc_u5.yaml
index 1bb8e1737..d0a96b001 100644
--- a/data/registers/adc_u5.yaml
+++ b/data/registers/adc_u5.yaml
@@ -1,714 +1,1222 @@
 block/ADC:
-  description: ADC.
+  description: ADC1.
   items:
-    - name: ISR
-      description: ADC interrupt and status register.
-      byte_offset: 0
-      fieldset: ISR
-    - name: IER
-      description: ADC interrupt enable register.
-      byte_offset: 4
-      fieldset: IER
-    - name: CR
-      description: ADC control register.
-      byte_offset: 8
-      fieldset: CR
-    - name: CFGR1
-      description: ADC configuration register.
-      byte_offset: 12
-      fieldset: CFGR1
-    - name: CFGR2
-      description: ADC configuration register 2.
-      byte_offset: 16
-      fieldset: CFGR2
-    - name: SMPR
-      description: ADC sample time register.
-      byte_offset: 20
-      fieldset: SMPR
-    - name: AWD1TR
-      description: ADC watchdog threshold register.
-      byte_offset: 32
-      fieldset: AWD1TR
-    - name: AWD2TR
-      description: ADC watchdog threshold register.
-      byte_offset: 36
-      fieldset: AWD2TR
-    - name: CHSELRMOD0
-      description: ADC channel selection register [alternate].
-      byte_offset: 40
-      fieldset: CHSELRMOD0
-    - name: CHSELRMOD1
-      description: ADC channel selection register [alternate].
-      byte_offset: 40
-      fieldset: CHSELRMOD1
-    - name: AWD3TR
-      description: ADC watchdog threshold register.
-      byte_offset: 44
-      fieldset: AWD3TR
-    - name: DR
-      description: ADC data register.
-      byte_offset: 64
-      access: Read
-      fieldset: DR
-    - name: PWRR
-      description: ADC data register.
-      byte_offset: 68
-      fieldset: PWRR
-    - name: AWD2CR
-      description: ADC Analog Watchdog 2 Configuration register.
-      byte_offset: 160
-      fieldset: AWD2CR
-    - name: AWD3CR
-      description: ADC Analog Watchdog 3 Configuration register.
-      byte_offset: 164
-      fieldset: AWD3CR
-    - name: CALFACT
-      description: ADC Calibration factor.
-      byte_offset: 196
-      fieldset: CALFACT
-    - name: OR
-      description: ADC option register.
-      byte_offset: 208
-      fieldset: OR
-    - name: CCR
-      description: ADC common configuration register.
-      byte_offset: 776
-      fieldset: CCR
-fieldset/AWD1TR:
-  description: ADC watchdog threshold register.
-  fields:
-    - name: LT1
-      description: LT1.
-      bit_offset: 0
-      bit_size: 12
-    - name: HT1
-      description: HT1.
-      bit_offset: 16
-      bit_size: 12
-fieldset/AWD2CR:
-  description: ADC Analog Watchdog 2 Configuration register.
-  fields:
-    - name: AWD2CH0
-      description: AWD2CH0.
-      bit_offset: 0
-      bit_size: 1
-    - name: AWD2CH1
-      description: AWD2CH1.
-      bit_offset: 1
-      bit_size: 1
-    - name: AWD2CH2
-      description: AWD2CH2.
-      bit_offset: 2
-      bit_size: 1
-    - name: AWD2CH3
-      description: AWD2CH3.
-      bit_offset: 3
-      bit_size: 1
-    - name: AWD2CH4
-      description: AWD2CH4.
-      bit_offset: 4
-      bit_size: 1
-    - name: AWD2CH5
-      description: AWD2CH5.
-      bit_offset: 5
-      bit_size: 1
-    - name: AWD2CH6
-      description: AWD2CH6.
-      bit_offset: 6
-      bit_size: 1
-    - name: AWD2CH7
-      description: AWD2CH7.
-      bit_offset: 7
-      bit_size: 1
-    - name: AWD2CH8
-      description: AWD2CH8.
-      bit_offset: 8
-      bit_size: 1
-    - name: AWD2CH9
-      description: AWD2CH9.
-      bit_offset: 9
-      bit_size: 1
-    - name: AWD2CH10
-      description: AWD2CH10.
-      bit_offset: 10
-      bit_size: 1
-    - name: AWD2CH11
-      description: AWD2CH11.
-      bit_offset: 11
-      bit_size: 1
-    - name: AWD2CH12
-      description: AWD2CH12.
-      bit_offset: 12
-      bit_size: 1
-    - name: AWD2CH13
-      description: AWD2CH13.
-      bit_offset: 13
-      bit_size: 1
-    - name: AWD2CH14
-      description: AWD2CH14.
-      bit_offset: 14
-      bit_size: 1
-    - name: AWD2CH15
-      description: AWD2CH15.
-      bit_offset: 15
-      bit_size: 1
-    - name: AWD2CH16
-      description: AWD2CH16.
-      bit_offset: 16
-      bit_size: 1
-    - name: AWD2CH17
-      description: AWD2CH17.
-      bit_offset: 17
-      bit_size: 1
-    - name: AWD2CH18
-      description: AWD2CH18.
-      bit_offset: 18
-      bit_size: 1
-    - name: AWD2CH19
-      description: AWD2CH19.
-      bit_offset: 19
-      bit_size: 1
-    - name: AWD2CH20
-      description: AWD2CH20.
-      bit_offset: 20
-      bit_size: 1
-    - name: AWD2CH21
-      description: AWD2CH21.
-      bit_offset: 21
-      bit_size: 1
-    - name: AWD2CH22
-      description: AWD2CH22.
-      bit_offset: 22
-      bit_size: 1
-    - name: AWD2CH23
-      description: AWD2CH23.
-      bit_offset: 23
-      bit_size: 1
-fieldset/AWD2TR:
-  description: ADC watchdog threshold register.
+  - name: ISR
+    description: ADC interrupt and status register.
+    byte_offset: 0
+    fieldset: ISR
+  - name: IER
+    description: ADC interrupt enable register.
+    byte_offset: 4
+    fieldset: IER
+  - name: CR
+    description: ADC control register.
+    byte_offset: 8
+    fieldset: CR
+  - name: CFGR
+    description: ADC configuration register.
+    byte_offset: 12
+    fieldset: CFGR
+  - name: CFGR2
+    description: ADC configuration register 2.
+    byte_offset: 16
+    fieldset: CFGR2
+  - name: SMPR
+    description: sampling time register 1-2
+    array:
+      len: 2
+      stride: 4
+    byte_offset: 20
+    fieldset: SMPR
+  - name: PCSEL
+    description: ADC channel preselection register.
+    byte_offset: 28
+    fieldset: PCSEL
+  - name: SQR1
+    description: ADC regular sequence register 1.
+    byte_offset: 48
+    fieldset: SQR1
+  - name: SQR2
+    description: ADC regular sequence register 2.
+    byte_offset: 52
+    fieldset: SQR2
+  - name: SQR3
+    description: ADC regular sequence register 3.
+    byte_offset: 56
+    fieldset: SQR3
+  - name: SQR4
+    description: ADC regular sequence register 4.
+    byte_offset: 60
+    fieldset: SQR4
+  - name: DR
+    description: ADC regular Data Register.
+    byte_offset: 64
+    access: Read
+    fieldset: DR
+  - name: JSQR
+    description: ADC injected sequence register.
+    byte_offset: 76
+    fieldset: JSQR
+  - name: OFR
+    description: ADC offset register.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 96
+    fieldset: OFR
+  - name: GCOMP
+    description: ADC gain compensation register.
+    byte_offset: 112
+    fieldset: GCOMP
+  - name: JDR
+    description: ADC injected data register.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 128
+    access: Read
+    fieldset: JDR
+  - name: AWD2CR
+    description: ADC analog watchdog 2 configuration register.
+    byte_offset: 160
+    fieldset: AWD2CR
+  - name: AWD3CR
+    description: ADC analog watchdog 3 configuration register.
+    byte_offset: 164
+    fieldset: AWD3CR
+  - name: LTR1
+    description: ADC watchdog threshold register 1.
+    byte_offset: 168
+    fieldset: LTR1
+  - name: HTR1
+    description: ADC watchdog threshold register 1.
+    byte_offset: 172
+    fieldset: HTR1
+  - name: LTR2
+    description: ADC watchdog lower threshold register 2.
+    byte_offset: 176
+    fieldset: LTR2
+  - name: HTR2
+    description: ADC watchdog higher threshold register 2.
+    byte_offset: 180
+    fieldset: HTR2
+  - name: LTR3
+    description: ADC watchdog lower threshold register 3.
+    byte_offset: 184
+    fieldset: LTR3
+  - name: HTR3
+    description: ADC watchdog higher threshold register 3.
+    byte_offset: 188
+    fieldset: HTR3
+  - name: DIFSEL
+    description: ADC differential mode selection register.
+    byte_offset: 192
+    fieldset: DIFSEL
+  - name: CALFACT
+    description: ADC user control register.
+    byte_offset: 196
+    fieldset: CALFACT
+  - name: CALFACT2
+    description: ADC calibration factor register.
+    byte_offset: 200
+    fieldset: CALFACT2
+block/ADC4:
+  description: ADC4.
+  items:
+  - name: ISR
+    description: ADC interrupt and status register.
+    byte_offset: 0
+    fieldset: ADC4_ISR
+  - name: IER
+    description: ADC interrupt enable register.
+    byte_offset: 4
+    fieldset: ADC4_IER
+  - name: CR
+    description: ADC control register.
+    byte_offset: 8
+    fieldset: ADC4_CR
+  - name: CFGR1
+    description: ADC configuration register.
+    byte_offset: 12
+    fieldset: ADC4_CFGR1
+  - name: CFGR2
+    description: ADC configuration register 2.
+    byte_offset: 16
+    fieldset: ADC4_CFGR2
+  - name: SMPR
+    description: ADC sample time register.
+    byte_offset: 20
+    fieldset: ADC4_SMPR
+  - name: AWD1TR
+    description: ADC watchdog threshold register.
+    byte_offset: 32
+    fieldset: ADC4_AWDTR
+  - name: AWD2TR
+    description: ADC watchdog threshold register.
+    byte_offset: 36
+    fieldset: ADC4_AWDTR
+  - name: CHSELRMOD0
+    description: ADC channel selection register [alternate].
+    byte_offset: 40
+    fieldset: ADC4_CHSELRMOD0
+  - name: CHSELRMOD1
+    description: ADC channel selection register [alternate].
+    byte_offset: 40
+    fieldset: ADC4_CHSELRMOD1
+  - name: AWD3TR
+    description: ADC watchdog threshold register.
+    byte_offset: 44
+    fieldset: ADC4_AWDTR
+  - name: DR
+    description: ADC data register.
+    byte_offset: 64
+    access: Read
+    fieldset: ADC4_DR
+  - name: PWRR
+    description: ADC power register.
+    byte_offset: 68
+    fieldset: ADC4_PWRR
+  - name: AWD2CR
+    description: ADC Analog Watchdog 2 Configuration register.
+    byte_offset: 160
+    fieldset: ADC4_AWDCR
+  - name: AWD3CR
+    description: ADC Analog Watchdog 3 Configuration register.
+    byte_offset: 164
+    fieldset: ADC4_AWDCR
+  - name: CALFACT
+    description: ADC Calibration factor.
+    byte_offset: 196
+    fieldset: ADC4_CALFACT
+  - name: OR
+    description: ADC option register.
+    byte_offset: 208
+    fieldset: ADC4_OR
+  - name: CCR
+    description: ADC common configuration register.
+    byte_offset: 776
+    fieldset: ADC4_CCR
+fieldset/ADC4_AWDCR:
+  description: ADC Analog Watchdog Configuration register.
   fields:
-    - name: LT2
-      description: LT2.
-      bit_offset: 0
-      bit_size: 12
-    - name: HT2
-      description: HT2.
-      bit_offset: 16
-      bit_size: 12
-fieldset/AWD3CR:
-  description: ADC Analog Watchdog 3 Configuration register.
-  fields:
-    - name: AWD3CH0
-      description: AWD3CH0.
-      bit_offset: 0
-      bit_size: 1
-    - name: AWD3CH1
-      description: AWD3CH1.
-      bit_offset: 1
-      bit_size: 1
-    - name: AWD3CH2
-      description: AWD3CH2.
-      bit_offset: 2
-      bit_size: 1
-    - name: AWD3CH3
-      description: AWD3CH3.
-      bit_offset: 3
-      bit_size: 1
-    - name: AWD3CH4
-      description: AWD3CH4.
-      bit_offset: 4
-      bit_size: 1
-    - name: AWD3CH5
-      description: AWD3CH5.
-      bit_offset: 5
-      bit_size: 1
-    - name: AWD3CH6
-      description: AWD3CH6.
-      bit_offset: 6
-      bit_size: 1
-    - name: AWD3CH7
-      description: AWD3CH7.
-      bit_offset: 7
-      bit_size: 1
-    - name: AWD3CH8
-      description: AWD3CH8.
-      bit_offset: 8
-      bit_size: 1
-    - name: AWD3CH9
-      description: AWD3CH9.
-      bit_offset: 9
-      bit_size: 1
-    - name: AWD3CH10
-      description: AWD3CH10.
-      bit_offset: 10
-      bit_size: 1
-    - name: AWD3CH11
-      description: AWD3CH11.
-      bit_offset: 11
-      bit_size: 1
-    - name: AWD3CH12
-      description: AWD3CH12.
-      bit_offset: 12
-      bit_size: 1
-    - name: AWD3CH13
-      description: AWD3CH13.
-      bit_offset: 13
-      bit_size: 1
-    - name: AWD3CH14
-      description: AWD3CH14.
-      bit_offset: 14
-      bit_size: 1
-    - name: AWD3CH15
-      description: AWD3CH15.
-      bit_offset: 15
-      bit_size: 1
-    - name: AWD3CH16
-      description: AWD3CH16.
-      bit_offset: 16
-      bit_size: 1
-    - name: AWD3CH17
-      description: AWD3CH17.
-      bit_offset: 17
-      bit_size: 1
-    - name: AWD3CH18
-      description: AWD3CH18.
-      bit_offset: 18
-      bit_size: 1
-    - name: AWD3CH19
-      description: AWD3CH19.
-      bit_offset: 19
-      bit_size: 1
-    - name: AWD3CH20
-      description: AWD3CH20.
-      bit_offset: 20
-      bit_size: 1
-    - name: AWD3CH21
-      description: AWD3CH21.
-      bit_offset: 21
-      bit_size: 1
-    - name: AWD3CH22
-      description: AWD3CH22.
-      bit_offset: 22
-      bit_size: 1
-    - name: AWD3CH23
-      description: AWD3CH23.
-      bit_offset: 23
-      bit_size: 1
-fieldset/AWD3TR:
+  - name: AWDCH
+    description: AWDCH0.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 24
+      stride: 1
+fieldset/ADC4_AWDTR:
   description: ADC watchdog threshold register.
   fields:
-    - name: LT3
-      description: LT3.
-      bit_offset: 0
-      bit_size: 12
-    - name: HT3
-      description: HT3.
-      bit_offset: 16
-      bit_size: 12
-fieldset/CALFACT:
+  - name: LT3
+    description: LT3.
+    bit_offset: 0
+    bit_size: 12
+  - name: HT3
+    description: HT3.
+    bit_offset: 16
+    bit_size: 12
+fieldset/ADC4_CALFACT:
   description: ADC Calibration factor.
   fields:
-    - name: CALFACT
-      description: CALFACT.
-      bit_offset: 0
-      bit_size: 7
-fieldset/CCR:
+  - name: CALFACT
+    description: CALFACT.
+    bit_offset: 0
+    bit_size: 7
+fieldset/ADC4_CCR:
   description: ADC common configuration register.
   fields:
-    - name: PRESC
-      description: PRESC.
-      bit_offset: 18
-      bit_size: 4
-    - name: VREFEN
-      description: VREFEN.
-      bit_offset: 22
-      bit_size: 1
-    - name: VSENSESEL
-      description: VSENSESEL.
-      bit_offset: 23
-      bit_size: 1
-    - name: VBATEN
-      description: VBATEN.
-      bit_offset: 24
-      bit_size: 1
-fieldset/CFGR1:
+  - name: PRESC
+    description: PRESC.
+    bit_offset: 18
+    bit_size: 4
+    enum: ADC4_PRESC
+  - name: VREFEN
+    description: VREFEN.
+    bit_offset: 22
+    bit_size: 1
+  - name: VSENSESEL
+    description: VSENSESEL.
+    bit_offset: 23
+    bit_size: 1
+  - name: VBATEN
+    description: VBATEN.
+    bit_offset: 24
+    bit_size: 1
+fieldset/ADC4_CFGR1:
   description: ADC configuration register.
   fields:
-    - name: DMAEN
-      description: DMAEN.
-      bit_offset: 0
-      bit_size: 1
-    - name: DMACFG
-      description: DMACFG.
-      bit_offset: 1
-      bit_size: 1
-    - name: RES
-      description: RES.
-      bit_offset: 2
-      bit_size: 2
-    - name: SCANDIR
-      description: SCANDIR.
-      bit_offset: 4
-      bit_size: 1
-    - name: ALIGN
-      description: ALIGN.
-      bit_offset: 5
-      bit_size: 1
-    - name: EXTSEL
-      description: EXTSEL.
-      bit_offset: 6
-      bit_size: 3
-    - name: EXTEN
-      description: EXTEN.
-      bit_offset: 10
-      bit_size: 2
-    - name: OVRMOD
-      description: OVRMOD.
-      bit_offset: 12
-      bit_size: 1
-    - name: CONT
-      description: CONT.
-      bit_offset: 13
-      bit_size: 1
-    - name: WAIT
-      description: WAIT.
-      bit_offset: 14
-      bit_size: 1
-    - name: DISCEN
-      description: DISCEN.
-      bit_offset: 16
-      bit_size: 1
-    - name: CHSELRMOD
-      description: CHSELRMOD.
-      bit_offset: 21
-      bit_size: 1
-    - name: AWD1SGL
-      description: AWD1SGL.
-      bit_offset: 22
-      bit_size: 1
-    - name: AWD1EN
-      description: AWD1EN.
-      bit_offset: 23
-      bit_size: 1
-    - name: AWD1CH
-      description: AWD1CH.
-      bit_offset: 26
-      bit_size: 5
-fieldset/CFGR2:
+  - name: DMAEN
+    description: DMAEN.
+    bit_offset: 0
+    bit_size: 1
+  - name: DMACFG
+    description: DMACFG.
+    bit_offset: 1
+    bit_size: 1
+    enum: ADC4_DMACFG
+  - name: RES
+    description: RES.
+    bit_offset: 2
+    bit_size: 2
+    enum: ADC4_RES
+  - name: SCANDIR
+    description: SCANDIR.
+    bit_offset: 4
+    bit_size: 1
+  - name: ALIGN
+    description: ALIGN.
+    bit_offset: 5
+    bit_size: 1
+  - name: EXTSEL
+    description: EXTSEL.
+    bit_offset: 6
+    bit_size: 3
+  - name: EXTEN
+    description: EXTEN.
+    bit_offset: 10
+    bit_size: 2
+    enum: ADC4_EXTEN
+  - name: OVRMOD
+    description: OVRMOD.
+    bit_offset: 12
+    bit_size: 1
+  - name: CONT
+    description: CONT.
+    bit_offset: 13
+    bit_size: 1
+  - name: WAIT
+    description: WAIT.
+    bit_offset: 14
+    bit_size: 1
+  - name: DISCEN
+    description: DISCEN.
+    bit_offset: 16
+    bit_size: 1
+  - name: CHSELRMOD
+    description: CHSELRMOD.
+    bit_offset: 21
+    bit_size: 1
+  - name: AWD1SGL
+    description: AWD1SGL.
+    bit_offset: 22
+    bit_size: 1
+  - name: AWD1EN
+    description: AWD1EN.
+    bit_offset: 23
+    bit_size: 1
+  - name: AWD1CH
+    description: AWD1CH.
+    bit_offset: 26
+    bit_size: 5
+fieldset/ADC4_CFGR2:
   description: ADC configuration register 2.
   fields:
-    - name: OVSE
-      description: OVSE.
-      bit_offset: 0
-      bit_size: 1
-    - name: OVSR
-      description: OVSR.
-      bit_offset: 2
-      bit_size: 3
-    - name: OVSS
-      description: OVSS.
-      bit_offset: 5
-      bit_size: 4
-    - name: TOVS
-      description: TOVS.
-      bit_offset: 9
-      bit_size: 1
-    - name: LFTRIG
-      description: LFTRIG.
-      bit_offset: 29
-      bit_size: 1
-fieldset/CHSELRMOD0:
+  - name: OVSE
+    description: OVSE.
+    bit_offset: 0
+    bit_size: 1
+  - name: OVSR
+    description: OVSR.
+    bit_offset: 2
+    bit_size: 3
+    enum: ADC4_OVERSAMPLING_RATIO
+  - name: OVSS
+    description: OVSS.
+    bit_offset: 5
+    bit_size: 4
+  - name: TOVS
+    description: TOVS.
+    bit_offset: 9
+    bit_size: 1
+  - name: LFTRIG
+    description: LFTRIG.
+    bit_offset: 29
+    bit_size: 1
+fieldset/ADC4_CHSELRMOD0:
   description: ADC channel selection register [alternate].
   fields:
-    - name: CHSEL
-      description: CHSEL.
-      bit_offset: 0
-      bit_size: 24
-fieldset/CHSELRMOD1:
+  - name: CHSEL
+    description: CHSEL.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 24
+      stride: 1
+fieldset/ADC4_CHSELRMOD1:
   description: ADC channel selection register [alternate].
   fields:
-    - name: SQ1
-      description: SQ1.
-      bit_offset: 0
-      bit_size: 4
-    - name: SQ2
-      description: SQ2.
-      bit_offset: 4
-      bit_size: 4
-    - name: SQ3
-      description: SQ3.
-      bit_offset: 8
-      bit_size: 4
-    - name: SQ4
-      description: SQ4.
-      bit_offset: 12
-      bit_size: 4
-    - name: SQ5
-      description: SQ5.
-      bit_offset: 16
-      bit_size: 4
-    - name: SQ6
-      description: SQ6.
-      bit_offset: 20
-      bit_size: 4
-    - name: SQ7
-      description: SQ7.
-      bit_offset: 24
-      bit_size: 4
-    - name: SQ8
-      description: SQ8.
-      bit_offset: 28
-      bit_size: 4
+  - name: SQ
+    description: SQ
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 8
+      stride: 4
+fieldset/ADC4_CR:
+  description: ADC control register.
+  fields:
+  - name: ADEN
+    description: ADEN.
+    bit_offset: 0
+    bit_size: 1
+  - name: ADDIS
+    description: ADDIS.
+    bit_offset: 1
+    bit_size: 1
+  - name: ADSTART
+    description: ADSTART.
+    bit_offset: 2
+    bit_size: 1
+  - name: ADSTP
+    description: ADSTP.
+    bit_offset: 4
+    bit_size: 1
+  - name: ADVREGEN
+    description: ADVREGEN.
+    bit_offset: 28
+    bit_size: 1
+  - name: ADCAL
+    description: ADCAL.
+    bit_offset: 31
+    bit_size: 1
+fieldset/ADC4_DR:
+  description: ADC data register.
+  fields:
+  - name: DATA
+    description: DATA.
+    bit_offset: 0
+    bit_size: 16
+fieldset/ADC4_IER:
+  description: ADC interrupt enable register.
+  fields:
+  - name: ADRDYIE
+    description: ADRDYIE.
+    bit_offset: 0
+    bit_size: 1
+  - name: EOSMPIE
+    description: EOSMPIE.
+    bit_offset: 1
+    bit_size: 1
+  - name: EOCIE
+    description: EOCIE.
+    bit_offset: 2
+    bit_size: 1
+  - name: EOSIE
+    description: EOSIE.
+    bit_offset: 3
+    bit_size: 1
+  - name: OVRIE
+    description: OVRIE.
+    bit_offset: 4
+    bit_size: 1
+  - name: AWDIE
+    description: AWD1IE.
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: EOCALIE
+    description: EOCALIE.
+    bit_offset: 11
+    bit_size: 1
+  - name: LDORDYIE
+    description: LDORDYIE.
+    bit_offset: 12
+    bit_size: 1
+fieldset/ADC4_ISR:
+  description: ADC interrupt and status register.
+  fields:
+  - name: ADRDY
+    description: ADRDY.
+    bit_offset: 0
+    bit_size: 1
+  - name: EOSMP
+    description: EOSMP.
+    bit_offset: 1
+    bit_size: 1
+  - name: EOC
+    description: EOC.
+    bit_offset: 2
+    bit_size: 1
+  - name: EOS
+    description: EOS.
+    bit_offset: 3
+    bit_size: 1
+  - name: OVR
+    description: OVR.
+    bit_offset: 4
+    bit_size: 1
+  - name: AWD
+    description: AWD1.
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: EOCAL
+    description: EOCAL.
+    bit_offset: 11
+    bit_size: 1
+  - name: LDORDY
+    description: LDORDY.
+    bit_offset: 12
+    bit_size: 1
+fieldset/ADC4_OR:
+  description: ADC option register.
+  fields:
+  - name: CHN21SEL
+    description: CHN21SEL.
+    bit_offset: 0
+    bit_size: 1
+fieldset/ADC4_PWRR:
+  description: ADC data register.
+  fields:
+  - name: AUTOFF
+    description: AUTOFF.
+    bit_offset: 0
+    bit_size: 1
+  - name: DPD
+    description: DPD.
+    bit_offset: 1
+    bit_size: 1
+  - name: VREFPROT
+    description: VREFPROT.
+    bit_offset: 2
+    bit_size: 1
+  - name: VREFSECSMP
+    description: VREFSECSMP.
+    bit_offset: 3
+    bit_size: 1
+fieldset/ADC4_SMPR:
+  description: ADC sample time register.
+  fields:
+  - name: SMP
+    description: SMP1.
+    bit_offset: 0
+    bit_size: 3
+    array:
+      len: 2
+      stride: 4
+    enum: ADC4_SAMPLE_TIME
+  - name: SMPSEL
+    description: SMPSEL0.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 24
+      stride: 1
+fieldset/AWD2CR:
+  description: ADC analog watchdog 2 configuration register.
+  fields:
+  - name: AWD2CH
+    description: AWD2CH.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 20
+      stride: 1
+fieldset/AWD3CR:
+  description: ADC analog watchdog 3 configuration register.
+  fields:
+  - name: AWD3CH
+    description: AWD3CH.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 20
+      stride: 1
+fieldset/CALFACT:
+  description: ADC user control register.
+  fields:
+  - name: I_APB_ADDR
+    description: I_APB_ADDR.
+    bit_offset: 0
+    bit_size: 8
+  - name: I_APB_DATA
+    description: I_APB_DATA.
+    bit_offset: 8
+    bit_size: 8
+  - name: VALIDITY
+    description: VALIDITY.
+    bit_offset: 16
+    bit_size: 1
+  - name: LATCH_COEF
+    description: LATCH_COEF.
+    bit_offset: 24
+    bit_size: 1
+  - name: CAPTURE_COEF
+    description: CAPTURE_COEF.
+    bit_offset: 25
+    bit_size: 1
+fieldset/CALFACT2:
+  description: ADC calibration factor register.
+  fields:
+  - name: CALFACT
+    description: CALFACT.
+    bit_offset: 0
+    bit_size: 32
+fieldset/CFGR:
+  description: ADC configuration register.
+  fields:
+  - name: DMNGT
+    description: DMNGT.
+    bit_offset: 0
+    bit_size: 2
+    enum: DMNGT
+  - name: RES
+    description: RES.
+    bit_offset: 2
+    bit_size: 2
+    enum: RES
+  - name: EXTSEL
+    description: EXTSEL.
+    bit_offset: 5
+    bit_size: 5
+  - name: EXTEN
+    description: EXTEN.
+    bit_offset: 10
+    bit_size: 2
+    enum: EXTEN
+  - name: OVRMOD
+    description: OVRMOD.
+    bit_offset: 12
+    bit_size: 1
+  - name: CONT
+    description: CONT.
+    bit_offset: 13
+    bit_size: 1
+  - name: AUTDLY
+    description: AUTDLY.
+    bit_offset: 14
+    bit_size: 1
+  - name: DISCEN
+    description: DISCEN.
+    bit_offset: 16
+    bit_size: 1
+  - name: DISCNUM
+    description: DISCNUM.
+    bit_offset: 17
+    bit_size: 3
+  - name: JDISCEN
+    description: JDISCEN.
+    bit_offset: 20
+    bit_size: 1
+  - name: AWD1SGL
+    description: AWD1SGL.
+    bit_offset: 22
+    bit_size: 1
+  - name: AWD1EN
+    description: AWD1EN.
+    bit_offset: 23
+    bit_size: 1
+  - name: JAWD1EN
+    description: JAWD1EN.
+    bit_offset: 24
+    bit_size: 1
+  - name: JAUTO
+    description: JAUTO.
+    bit_offset: 25
+    bit_size: 1
+  - name: AWD1CH
+    description: AWD1CH.
+    bit_offset: 26
+    bit_size: 5
+fieldset/CFGR2:
+  description: ADC configuration register 2.
+  fields:
+  - name: ROVSE
+    description: ROVSE.
+    bit_offset: 0
+    bit_size: 1
+  - name: JOVSE
+    description: JOVSE.
+    bit_offset: 1
+    bit_size: 1
+  - name: OVSS
+    description: OVSS.
+    bit_offset: 5
+    bit_size: 4
+  - name: TROVS
+    description: TROVS.
+    bit_offset: 9
+    bit_size: 1
+  - name: ROVSM
+    description: ROVSM.
+    bit_offset: 10
+    bit_size: 1
+  - name: BULB
+    description: BULB.
+    bit_offset: 13
+    bit_size: 1
+  - name: SWTRIG
+    description: SWTRIG.
+    bit_offset: 14
+    bit_size: 1
+  - name: SMPTRIG
+    description: SMPTRIG.
+    bit_offset: 15
+    bit_size: 1
+  - name: OSVR
+    description: OSVR.
+    bit_offset: 16
+    bit_size: 10
+  - name: LFTRIG
+    description: LFTRIG.
+    bit_offset: 27
+    bit_size: 1
+  - name: LSHIFT
+    description: LSHIFT.
+    bit_offset: 28
+    bit_size: 4
 fieldset/CR:
   description: ADC control register.
   fields:
-    - name: ADEN
-      description: ADEN.
-      bit_offset: 0
-      bit_size: 1
-    - name: ADDIS
-      description: ADDIS.
-      bit_offset: 1
-      bit_size: 1
-    - name: ADSTART
-      description: ADSTART.
-      bit_offset: 2
-      bit_size: 1
-    - name: ADSTP
-      description: ADSTP.
-      bit_offset: 4
-      bit_size: 1
-    - name: ADVREGEN
-      description: ADVREGEN.
-      bit_offset: 28
-      bit_size: 1
-    - name: ADCAL
-      description: ADCAL.
-      bit_offset: 31
-      bit_size: 1
+  - name: ADEN
+    description: ADEN.
+    bit_offset: 0
+    bit_size: 1
+  - name: ADDIS
+    description: ADDIS.
+    bit_offset: 1
+    bit_size: 1
+  - name: ADSTART
+    description: ADSTART.
+    bit_offset: 2
+    bit_size: 1
+  - name: JADSTART
+    description: JADSTART.
+    bit_offset: 3
+    bit_size: 1
+  - name: ADSTP
+    description: ADSTP.
+    bit_offset: 4
+    bit_size: 1
+    enum: ADSTP
+  - name: JADSTP
+    description: JADSTP.
+    bit_offset: 5
+    bit_size: 1
+  - name: ADCALLIN
+    description: ADCALLIN.
+    bit_offset: 16
+    bit_size: 1
+  - name: CALINDEX
+    description: CALINDEX.
+    bit_offset: 24
+    bit_size: 4
+  - name: ADVREGEN
+    description: ADVREGEN.
+    bit_offset: 28
+    bit_size: 1
+  - name: DEEPPWD
+    description: DEEPPWD.
+    bit_offset: 29
+    bit_size: 1
+  - name: ADCAL
+    description: ADCAL.
+    bit_offset: 31
+    bit_size: 1
+fieldset/DIFSEL:
+  description: ADC differential mode selection register.
+  fields:
+  - name: DIFSEL
+    description: channel differential or single-ended mode for channel
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 20
+      stride: 1
+    enum: DIFSEL
 fieldset/DR:
-  description: ADC data register.
+  description: ADC regular Data Register.
+  fields:
+  - name: RDATA
+    description: RDATA.
+    bit_offset: 0
+    bit_size: 32
+fieldset/GCOMP:
+  description: ADC gain compensation register.
+  fields:
+  - name: GCOMPCOEFF
+    description: GCOMPCOEFF.
+    bit_offset: 0
+    bit_size: 14
+  - name: GCOMP
+    description: GCOMP.
+    bit_offset: 31
+    bit_size: 1
+fieldset/HTR1:
+  description: ADC watchdog threshold register 1.
+  fields:
+  - name: HTR1
+    description: HTR1.
+    bit_offset: 0
+    bit_size: 25
+  - name: AWDFILT1
+    description: AWDFILT1.
+    bit_offset: 29
+    bit_size: 3
+fieldset/HTR2:
+  description: ADC watchdog higher threshold register 2.
   fields:
-    - name: DATA
-      description: DATA.
-      bit_offset: 0
-      bit_size: 16
+  - name: HTR2
+    description: HTR2.
+    bit_offset: 0
+    bit_size: 25
+fieldset/HTR3:
+  description: ADC watchdog higher threshold register 3.
+  fields:
+  - name: HTR3
+    description: HTR3.
+    bit_offset: 0
+    bit_size: 25
 fieldset/IER:
   description: ADC interrupt enable register.
   fields:
-    - name: ADRDYIE
-      description: ADRDYIE.
-      bit_offset: 0
-      bit_size: 1
-    - name: EOSMPIE
-      description: EOSMPIE.
-      bit_offset: 1
-      bit_size: 1
-    - name: EOCIE
-      description: EOCIE.
-      bit_offset: 2
-      bit_size: 1
-    - name: EOSIE
-      description: EOSIE.
-      bit_offset: 3
-      bit_size: 1
-    - name: OVRIE
-      description: OVRIE.
-      bit_offset: 4
-      bit_size: 1
-    - name: AWD1IE
-      description: AWD1IE.
-      bit_offset: 7
-      bit_size: 1
-    - name: AWD2IE
-      description: AWD2IE.
-      bit_offset: 8
-      bit_size: 1
-    - name: AWD3IE
-      description: AWD3IE.
-      bit_offset: 9
-      bit_size: 1
-    - name: EOCALIE
-      description: EOCALIE.
-      bit_offset: 11
-      bit_size: 1
-    - name: LDORDYIE
-      description: LDORDYIE.
-      bit_offset: 12
-      bit_size: 1
+  - name: ADRDYIE
+    description: ADRDYIE.
+    bit_offset: 0
+    bit_size: 1
+  - name: EOSMPIE
+    description: EOSMPIE.
+    bit_offset: 1
+    bit_size: 1
+  - name: EOCIE
+    description: EOCIE.
+    bit_offset: 2
+    bit_size: 1
+  - name: EOSIE
+    description: EOSIE.
+    bit_offset: 3
+    bit_size: 1
+  - name: OVRIE
+    description: OVRIE.
+    bit_offset: 4
+    bit_size: 1
+  - name: JEOCIE
+    description: JEOCIE.
+    bit_offset: 5
+    bit_size: 1
+  - name: JEOSIE
+    description: JEOSIE.
+    bit_offset: 6
+    bit_size: 1
+  - name: AWDIE
+    description: AWD1IE.
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
 fieldset/ISR:
   description: ADC interrupt and status register.
   fields:
-    - name: ADRDY
-      description: ADRDY.
-      bit_offset: 0
-      bit_size: 1
-    - name: EOSMP
-      description: EOSMP.
-      bit_offset: 1
-      bit_size: 1
-    - name: EOC
-      description: EOC.
-      bit_offset: 2
-      bit_size: 1
-    - name: EOS
-      description: EOS.
-      bit_offset: 3
-      bit_size: 1
-    - name: OVR
-      description: OVR.
-      bit_offset: 4
-      bit_size: 1
-    - name: AWD1
-      description: AWD1.
-      bit_offset: 7
-      bit_size: 1
-    - name: AWD2
-      description: AWD2.
-      bit_offset: 8
-      bit_size: 1
-    - name: AWD3
-      description: AWD3.
-      bit_offset: 9
-      bit_size: 1
-    - name: EOCAL
-      description: EOCAL.
-      bit_offset: 11
-      bit_size: 1
-    - name: LDORDY
-      description: LDORDY.
-      bit_offset: 12
-      bit_size: 1
-fieldset/OR:
-  description: ADC option register.
+  - name: ADRDY
+    description: ADRDY.
+    bit_offset: 0
+    bit_size: 1
+  - name: EOSMP
+    description: EOSMP.
+    bit_offset: 1
+    bit_size: 1
+  - name: EOC
+    description: EOC.
+    bit_offset: 2
+    bit_size: 1
+  - name: EOS
+    description: EOS.
+    bit_offset: 3
+    bit_size: 1
+  - name: OVR
+    description: OVR.
+    bit_offset: 4
+    bit_size: 1
+  - name: JEOC
+    description: JEOC.
+    bit_offset: 5
+    bit_size: 1
+  - name: JEOS
+    description: JEOS.
+    bit_offset: 6
+    bit_size: 1
+  - name: AWD
+    description: AWD1.
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: LDORDY
+    description: LDORDY.
+    bit_offset: 12
+    bit_size: 1
+fieldset/JDR:
+  description: ADC injected data register.
   fields:
-    - name: CHN21SEL
-      description: CHN21SEL.
-      bit_offset: 0
-      bit_size: 1
-fieldset/PWRR:
-  description: ADC data register.
+  - name: JDATA
+    description: JDATA.
+    bit_offset: 0
+    bit_size: 32
+fieldset/JSQR:
+  description: ADC injected sequence register.
+  fields:
+  - name: JL
+    description: JL.
+    bit_offset: 0
+    bit_size: 2
+  - name: JEXTSEL
+    description: JEXTSEL.
+    bit_offset: 2
+    bit_size: 5
+  - name: JEXTEN
+    description: JEXTEN.
+    bit_offset: 7
+    bit_size: 2
+  - name: JSQ
+    description: JSQ1.
+    bit_offset: 9
+    bit_size: 5
+    array:
+      len: 4
+      stride: 6
+fieldset/LTR1:
+  description: ADC watchdog threshold register 1.
+  fields:
+  - name: LTR1
+    description: LTR1.
+    bit_offset: 0
+    bit_size: 25
+fieldset/LTR2:
+  description: ADC watchdog lower threshold register 2.
+  fields:
+  - name: LTR2
+    description: LTR2.
+    bit_offset: 0
+    bit_size: 25
+fieldset/LTR3:
+  description: ADC watchdog lower threshold register 3.
+  fields:
+  - name: LTR3
+    description: LTR3.
+    bit_offset: 0
+    bit_size: 25
+fieldset/OFR:
+  description: ADC offset register.
   fields:
-    - name: AUTOFF
-      description: AUTOFF.
-      bit_offset: 0
-      bit_size: 1
-    - name: DPD
-      description: DPD.
-      bit_offset: 1
-      bit_size: 1
-    - name: VREFPROT
-      description: VREFPROT.
-      bit_offset: 2
-      bit_size: 1
-    - name: VREFSECSMP
-      description: VREFSECSMP.
-      bit_offset: 3
-      bit_size: 1
+  - name: OFFSET
+    description: OFFSET.
+    bit_offset: 0
+    bit_size: 24
+  - name: POSOFF
+    description: POSOFF.
+    bit_offset: 24
+    bit_size: 1
+  - name: USAT
+    description: USAT.
+    bit_offset: 25
+    bit_size: 1
+  - name: SSAT
+    description: SSAT.
+    bit_offset: 26
+    bit_size: 1
+  - name: OFFSET_CH
+    description: OFFSET_CH.
+    bit_offset: 27
+    bit_size: 5
+fieldset/PCSEL:
+  description: ADC channel preselection register.
+  fields:
+  - name: PCSEL
+    description: PCSEL.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 20
+      stride: 1
+    enum: PCSEL
 fieldset/SMPR:
-  description: ADC sample time register.
+  description: ADC sample time register 1.
+  fields:
+  - name: SMP
+    description: SMP0.
+    bit_offset: 0
+    bit_size: 3
+    array:
+      len: 10
+      stride: 3
+    enum: SAMPLE_TIME
+fieldset/SQR1:
+  description: ADC regular sequence register 1.
+  fields:
+  - name: L
+    description: L.
+    bit_offset: 0
+    bit_size: 4
+  - name: SQ
+    description: SQ1.
+    bit_offset: 6
+    bit_size: 5
+    array:
+      len: 4
+      stride: 6
+fieldset/SQR2:
+  description: ADC regular sequence register 2.
+  fields:
+  - name: SQ
+    description: SQ5.
+    bit_offset: 0
+    bit_size: 5
+    array:
+      len: 5
+      stride: 6
+fieldset/SQR3:
+  description: ADC regular sequence register 3.
+  fields:
+  - name: SQ
+    description: SQ10.
+    bit_offset: 0
+    bit_size: 5
+    array:
+      len: 5
+      stride: 6
+fieldset/SQR4:
+  description: ADC regular sequence register 4.
   fields:
-    - name: SMP1
-      description: SMP1.
-      bit_offset: 0
-      bit_size: 3
-    - name: SMP2
-      description: SMP2.
-      bit_offset: 4
-      bit_size: 3
-    - name: SMPSEL0
-      description: SMPSEL0.
-      bit_offset: 8
-      bit_size: 1
-    - name: SMPSEL1
-      description: SMPSEL1.
-      bit_offset: 9
-      bit_size: 1
-    - name: SMPSEL2
-      description: SMPSEL2.
-      bit_offset: 10
-      bit_size: 1
-    - name: SMPSEL3
-      description: SMPSEL3.
-      bit_offset: 11
-      bit_size: 1
-    - name: SMPSEL4
-      description: SMPSEL4.
-      bit_offset: 12
-      bit_size: 1
-    - name: SMPSEL5
-      description: SMPSEL5.
-      bit_offset: 13
-      bit_size: 1
-    - name: SMPSEL6
-      description: SMPSEL6.
-      bit_offset: 14
-      bit_size: 1
-    - name: SMPSEL7
-      description: SMPSEL7.
-      bit_offset: 15
-      bit_size: 1
-    - name: SMPSEL8
-      description: SMPSEL8.
-      bit_offset: 16
-      bit_size: 1
-    - name: SMPSEL9
-      description: SMPSEL9.
-      bit_offset: 17
-      bit_size: 1
-    - name: SMPSEL10
-      description: SMPSEL10.
-      bit_offset: 18
-      bit_size: 1
-    - name: SMPSEL11
-      description: SMPSEL11.
-      bit_offset: 19
-      bit_size: 1
-    - name: SMPSEL12
-      description: SMPSEL12.
-      bit_offset: 20
-      bit_size: 1
-    - name: SMPSEL13
-      description: SMPSEL13.
-      bit_offset: 21
-      bit_size: 1
-    - name: SMPSEL14
-      description: SMPSEL14.
-      bit_offset: 22
-      bit_size: 1
-    - name: SMPSEL15
-      description: SMPSEL15.
-      bit_offset: 23
-      bit_size: 1
-    - name: SMPSEL16
-      description: SMPSEL16.
-      bit_offset: 24
-      bit_size: 1
-    - name: SMPSEL17
-      description: SMPSEL17.
-      bit_offset: 25
-      bit_size: 1
-    - name: SMPSEL18
-      description: SMPSEL18.
-      bit_offset: 26
-      bit_size: 1
-    - name: SMPSEL19
-      description: SMPSEL19.
-      bit_offset: 27
-      bit_size: 1
-    - name: SMPSEL20
-      description: SMPSEL20.
-      bit_offset: 28
-      bit_size: 1
-    - name: SMPSEL21
-      description: SMPSEL21.
-      bit_offset: 29
-      bit_size: 1
-    - name: SMPSEL22
-      description: SMPSEL22.
-      bit_offset: 30
-      bit_size: 1
-    - name: SMPSEL23
-      description: SMPSEL23.
-      bit_offset: 31
-      bit_size: 1
+  - name: SQ
+    description: SQ15.
+    bit_offset: 0
+    bit_size: 5
+    array:
+      len: 2
+      stride: 6
+enum/ADC4_DMACFG:
+  bit_size: 1
+  variants:
+  - name: OneShot
+    description: DMA One Shot mode selected
+    value: 0
+  - name: Circular
+    description: DMA Circular mode selected
+    value: 1
+enum/ADC4_EXTEN:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: Trigger detection disabled
+    value: 0
+  - name: RisingEdge
+    description: Trigger detection on the rising edge
+    value: 1
+  - name: FallingEdge
+    description: Trigger detection on the falling edge
+    value: 2
+  - name: BothEdges
+    description: Trigger detection on both the rising and falling edges
+    value: 3
+enum/ADC4_OVERSAMPLING_RATIO:
+  bit_size: 3
+  variants:
+  - name: Oversample2x
+    description: Oversample 2 times
+    value: 0
+  - name: Oversample4x
+    description: Oversample 4 times
+    value: 1
+  - name: Oversample8x
+    description: Oversample 8 times
+    value: 2
+  - name: Oversample16x
+    description: Oversample 16 times
+    value: 3
+  - name: Oversample32x
+    description: Oversample 32 times
+    value: 4
+  - name: Oversample64x
+    description: Oversample 64 times
+    value: 5
+  - name: Oversample128x
+    description: Oversample 128 times
+    value: 6
+  - name: Oversample256x
+    description: Oversample 256 times
+    value: 7
+enum/ADC4_PRESC:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: adc_ker_ck_input not divided
+    value: 0
+  - name: Div2
+    description: adc_ker_ck_input divided by 2
+    value: 1
+  - name: Div4
+    description: adc_ker_ck_input divided by 4
+    value: 2
+  - name: Div6
+    description: adc_ker_ck_input divided by 6
+    value: 3
+  - name: Div8
+    description: adc_ker_ck_input divided by 8
+    value: 4
+  - name: Div10
+    description: adc_ker_ck_input divided by 10
+    value: 5
+  - name: Div12
+    description: adc_ker_ck_input divided by 12
+    value: 6
+  - name: Div16
+    description: adc_ker_ck_input divided by 16
+    value: 7
+  - name: Div32
+    description: adc_ker_ck_input divided by 32
+    value: 8
+  - name: Div64
+    description: adc_ker_ck_input divided by 64
+    value: 9
+  - name: Div128
+    description: adc_ker_ck_input divided by 128
+    value: 10
+  - name: Div256
+    description: adc_ker_ck_input divided by 256
+    value: 11
+enum/ADC4_RES:
+  bit_size: 2
+  variants:
+  - name: Bits12
+    description: 12-bit resolution
+    value: 0
+  - name: Bits10
+    description: 10-bit resolution
+    value: 1
+  - name: Bits8
+    description: 8-bit resolution
+    value: 2
+  - name: Bits6
+    description: 6-bit resolution
+    value: 3
+enum/ADC4_SAMPLE_TIME:
+  bit_size: 3
+  variants:
+  - name: Cycles1_5
+    description: 1.5 ADC cycles
+    value: 0
+  - name: Cycles3_5
+    description: 3.5 ADC cycles
+    value: 1
+  - name: Cycles7_5
+    description: 7.5 ADC cycles
+    value: 2
+  - name: Cycles12_5
+    description: 12.5 ADC cycles
+    value: 3
+  - name: Cycles19_5
+    description: 19.5 ADC cycles
+    value: 4
+  - name: Cycles39_5
+    description: 39.5 ADC cycles
+    value: 5
+  - name: Cycles79_5
+    description: 79.5 ADC cycles
+    value: 6
+  - name: Cycles814_5
+    description: 160.5 ADC cycles
+    value: 7
+enum/ADSTP:
+  bit_size: 1
+  variants:
+  - name: Stop
+    description: Stop conversion of channel
+    value: 1
+enum/DIFSEL:
+  bit_size: 1
+  variants:
+  - name: SingleEnded
+    description: Input channel is configured in single-ended mode
+    value: 0
+  - name: Differential
+    description: Input channel is configured in differential mode
+    value: 1
+enum/DMNGT:
+  bit_size: 2
+  variants:
+  - name: DR
+    description: Store output data in DR only
+    value: 0
+  - name: DMA_OneShot
+    description: DMA One Shot Mode selected
+    value: 1
+  - name: MDF
+    description: MDF mode selected
+    value: 2
+  - name: DMA_Circular
+    description: DMA Circular Mode selected
+    value: 3
+enum/EXTEN:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: Trigger detection disabled
+    value: 0
+  - name: RisingEdge
+    description: Trigger detection on the rising edge
+    value: 1
+  - name: FallingEdge
+    description: Trigger detection on the falling edge
+    value: 2
+  - name: BothEdges
+    description: Trigger detection on both the rising and falling edges
+    value: 3
+enum/PCSEL:
+  bit_size: 1
+  variants:
+  - name: NotPreselected
+    description: Input channel x is not pre-selected
+    value: 0
+  - name: Preselected
+    description: Pre-select input channel x
+    value: 1
+enum/RES:
+  bit_size: 2
+  variants:
+  - name: Bits14
+    description: 14-bit resolution
+    value: 0
+  - name: Bits12
+    description: 12-bit resolution
+    value: 1
+  - name: Bits10
+    description: 10-bit resolution
+    value: 2
+  - name: Bits8
+    description: 8-bit resolution
+    value: 3
+enum/SAMPLE_TIME:
+  bit_size: 3
+  variants:
+  - name: Cycles1_5
+    description: 1.5 ADC cycles
+    value: 0
+  - name: Cycles3_5
+    description: 3.5 ADC cycles
+    value: 1
+  - name: Cycles7_5
+    description: 7.5 ADC cycles
+    value: 2
+  - name: Cycles12_5
+    description: 12.5 ADC cycles
+    value: 3
+  - name: Cycles19_5
+    description: 19.5 ADC cycles
+    value: 4
+  - name: Cycles39_5
+    description: 39.5 ADC cycles
+    value: 5
+  - name: Cycles79_5
+    description: 79.5 ADC cycles
+    value: 6
+  - name: Cycles160_5
+    description: 160.5 ADC cycles
+    value: 7
diff --git a/data/registers/adccommon_u5.yaml b/data/registers/adccommon_u5.yaml
new file mode 100644
index 000000000..9996dc1d9
--- /dev/null
+++ b/data/registers/adccommon_u5.yaml
@@ -0,0 +1,233 @@
+block/ADC_COMMON:
+  description: Analog-to-Digital Converter.
+  items:
+  - name: CSR
+    description: ADC common status register.
+    byte_offset: 0
+    access: Read
+    fieldset: CSR
+  - name: CCR
+    description: ADC_CCR system control register.
+    byte_offset: 8
+    fieldset: CCR
+  - name: CDR
+    description: ADC common regular data register for dual mode.
+    byte_offset: 12
+    access: Read
+    fieldset: CDR
+  - name: CDR2
+    description: ADC common regular data register for 32-bit dual mode.
+    byte_offset: 16
+    access: Read
+    fieldset: CDR2
+fieldset/CCR:
+  description: ADC_CCR system control register.
+  fields:
+  - name: DUAL
+    description: 'Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
+    bit_offset: 0
+    bit_size: 5
+    enum: DUAL
+  - name: DELAY
+    description: 'Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
+    bit_offset: 8
+    bit_size: 4
+  - name: DAMDF
+    description: 'Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
+    bit_offset: 14
+    bit_size: 2
+    enum: DAMDF
+  - name: PRESC
+    description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
+    bit_offset: 18
+    bit_size: 4
+    enum: PRESC
+  - name: VREFEN
+    description: 'VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
+    bit_offset: 22
+    bit_size: 1
+  - name: VSENSEEN
+    description: 'Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
+    bit_offset: 23
+    bit_size: 1
+  - name: VBATEN
+    description: 'VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
+    bit_offset: 24
+    bit_size: 1
+fieldset/CDR:
+  description: ADC common regular data register for dual mode.
+  fields:
+  - name: RDATA_MST
+    description: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF[1:0] = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
+    bit_offset: 0
+    bit_size: 16
+  - name: RDATA_SLV
+    description: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)).
+    bit_offset: 16
+    bit_size: 16
+fieldset/CDR2:
+  description: ADC common regular data register for 32-bit dual mode.
+  fields:
+  - name: RDATA_ALT
+    description: Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT).
+    bit_offset: 0
+    bit_size: 32
+fieldset/CSR:
+  description: ADC common status register.
+  fields:
+  - name: ADRDY_MST
+    description: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
+    bit_offset: 0
+    bit_size: 1
+  - name: EOSMP_MST
+    description: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
+    bit_offset: 1
+    bit_size: 1
+  - name: EOC_MST
+    description: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
+    bit_offset: 2
+    bit_size: 1
+  - name: EOS_MST
+    description: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
+    bit_offset: 3
+    bit_size: 1
+  - name: OVR_MST
+    description: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
+    bit_offset: 4
+    bit_size: 1
+  - name: JEOC_MST
+    description: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
+    bit_offset: 5
+    bit_size: 1
+  - name: JEOS_MST
+    description: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
+    bit_offset: 6
+    bit_size: 1
+  - name: AWD_MST
+    description: Analog watchdog flags of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: LDORDY_MST
+    description: ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register.
+    bit_offset: 12
+    bit_size: 1
+  - name: ADRDY_SLV
+    description: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 16
+    bit_size: 1
+  - name: EOSMP_SLV
+    description: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 17
+    bit_size: 1
+  - name: EOC_SLV
+    description: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 18
+    bit_size: 1
+  - name: EOS_SLV
+    description: End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 19
+    bit_size: 1
+  - name: OVR_SLV
+    description: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 20
+    bit_size: 1
+  - name: JEOC_SLV
+    description: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 21
+    bit_size: 1
+  - name: JEOS_SLV
+    description: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 22
+    bit_size: 1
+  - name: AWD1_SLV
+    description: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register.
+    bit_offset: 23
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+  - name: LDORDY_SLV
+    description: ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register.
+    bit_offset: 28
+    bit_size: 1
+enum/DAMDF:
+  bit_size: 2
+  variants:
+  - name: NoPack
+    description: Without data packing, CDR/CDR2 not used
+    value: 0
+  - name: Format32to10
+    description: CDR formatted for 32-bit down to 10-bit resolution
+    value: 2
+  - name: Format8
+    description: CDR formatted for 8-bit resolution
+    value: 3
+enum/DUAL:
+  bit_size: 5
+  variants:
+  - name: Independent
+    description: Independent mode
+    value: 0
+  - name: DualRJ
+    description: Dual, combined regular simultaneous + injected simultaneous mode
+    value: 1
+  - name: DualRA
+    description: Dual, combined regular simultaneous + alternate trigger mode
+    value: 2
+  - name: DualIJ
+    description: Dual, combined interleaved mode + injected simultaneous mode
+    value: 3
+  - name: DualJ
+    description: Dual, injected simultaneous mode only
+    value: 5
+  - name: DualR
+    description: Dual, regular simultaneous mode only
+    value: 6
+  - name: DualI
+    description: Dual, interleaved mode only
+    value: 7
+  - name: DualA
+    description: Dual, alternate trigger mode only
+    value: 9
+enum/PRESC:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: adc_ker_ck_input not divided
+    value: 0
+  - name: Div2
+    description: adc_ker_ck_input divided by 2
+    value: 1
+  - name: Div4
+    description: adc_ker_ck_input divided by 4
+    value: 2
+  - name: Div6
+    description: adc_ker_ck_input divided by 6
+    value: 3
+  - name: Div8
+    description: adc_ker_ck_input divided by 8
+    value: 4
+  - name: Div10
+    description: adc_ker_ck_input divided by 10
+    value: 5
+  - name: Div12
+    description: adc_ker_ck_input divided by 12
+    value: 6
+  - name: Div16
+    description: adc_ker_ck_input divided by 16
+    value: 7
+  - name: Div32
+    description: adc_ker_ck_input divided by 32
+    value: 8
+  - name: Div64
+    description: adc_ker_ck_input divided by 64
+    value: 9
+  - name: Div128
+    description: adc_ker_ck_input divided by 128
+    value: 10
+  - name: Div256
+    description: adc_ker_ck_input divided by 256
+    value: 11
diff --git a/stm32-data-gen/src/perimap.rs b/stm32-data-gen/src/perimap.rs
index d7afd61dd..03f6349ca 100644
--- a/stm32-data-gen/src/perimap.rs
+++ b/stm32-data-gen/src/perimap.rs
@@ -102,6 +102,9 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[
     (".*:ADC:aditf5_v3_0_H5", ("adc", "h5", "ADC")),
     (".*:ADC:aditf512_v3_0_H5", ("adc", "h5", "ADC")),
     (".*:ADC:aditf5_v3_1", ("adc", "v4", "ADC")),
+    (".*:ADC:aditf5_40v2_U5", ("adc", "u5", "ADC")),
+    (".*:ADC:aditf5_40v1_U5", ("adc", "u5", "ADC")),
+    (".*:ADC:aditf4_v4_U5", ("adc", "u5", "ADC4")),
     ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")),
     ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
     ("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")),
@@ -110,6 +113,7 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[
     ("STM32G0.*:ADC\\d*_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")),
     ("STM32U0.*:ADC\\d*_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")),
     ("STM32G4.*:ADC\\d*_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
+    ("STM32U5.*:ADC\\d*_COMMON:.*", ("adccommon", "u5", "ADC_COMMON")),
     (
         "STM32(L[45]|W[BL]).*:ADC\\d*_COMMON:.*",
         ("adccommon", "v3", "ADC_COMMON"),
@@ -119,7 +123,6 @@ pub static PERIMAP: RegexMap<(&str, &str, &str)> = RegexMap::new(&[
     ("STM32H50.*:ADC\\d*_COMMON:.*", ("adccommon", "h50", "ADC_COMMON")),
     ("STM32H5.*:ADC\\d*_COMMON:.*", ("adccommon", "h5", "ADC_COMMON")),
     ("STM32H7.*:ADC\\d*_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")),
-    ("STM32U5.*:ADC:.*", ("adc", "u5", "ADC")),
     ("STM32F373.*:SDADC:.*", ("sdadc", "v1", "SDADC")),
     ("STM32F301.*:SDADC:.*", ("sdadc", "v1", "SDADC")),
     ("STM32G4.*:OPAMP:G4_tsmc90_fastOpamp", ("opamp", "g4", "OPAMP")),