Added PVIDEO interrupts to PMC

Author: ergo720

src/nxbx/hw/video/gpu/pmc.cpp

@@ -244,6 +244,14 @@ void pmc::Impl::updateIrq()
 		m_int_status &= ~(1 << NV_PMC_INTR_0_PGRAPH);
 	}
 
+	// Check for pending PVIDEO interrupts
+	if (m_pvideo->read32(NV_PVIDEO_INTR) & m_pvideo->read32(NV_PVIDEO_INTR_EN)) {
+		m_int_status |= (1 << NV_PMC_INTR_0_PVIDEO);
+	}
+	else {
+		m_int_status &= ~(1 << NV_PMC_INTR_0_PVIDEO);
+	}
+
 	switch (m_int_enabled)
 	{
 	default:

src/nxbx/hw/video/gpu/pmc.hpp

@@ -21,6 +21,7 @@
 #define NV_PMC_INTR_0 (NV2A_REGISTER_BASE + 0x00000100) // Pending interrupts of all engines
 #define NV_PMC_INTR_0_PFIFO 8
 #define NV_PMC_INTR_0_PGRAPH 12
+#define NV_PMC_INTR_0_PVIDEO 16
 #define NV_PMC_INTR_0_PTIMER 20
 #define NV_PMC_INTR_0_PCRTC 24
 #define NV_PMC_INTR_0_SOFTWARE 31

src/nxbx/hw/video/gpu/pvideo.cpp

@@ -31,6 +31,9 @@ class pvideo::Impl
 	// connected devices
 	pmc *m_pmc;
 	cpu_t *m_lc86cpu;
+	// atomic registers
+	std::atomic_uint32_t m_int_status;
+	std::atomic_uint32_t m_int_enabled;
 	// registers
 	uint32_t debug[11];
 	uint32_t m_regs[24];
@@ -87,6 +90,16 @@ void pvideo::Impl::write32(uint32_t addr, const uint32_t value)
 		debug[(addr - NV_PVIDEO_DEBUG_0) >> 2] = value;
 		break;
 
+	case NV_PVIDEO_INTR:
+		m_int_status &= ~value;
+		m_pmc->updateIrq();
+		break;
+
+	case NV_PVIDEO_INTR_EN:
+		m_int_enabled = value;
+		m_pmc->updateIrq();
+		break;
+
 	case NV_PVIDEO_LUMINANCE(0):
 	case NV_PVIDEO_LUMINANCE(1):
 	case NV_PVIDEO_CHROMINANCE(0):
@@ -132,6 +145,14 @@ uint32_t pvideo::Impl::read32(uint32_t addr)
 		value = debug[(addr - NV_PVIDEO_DEBUG_0) >> 2];
 		break;
 
+	case NV_PVIDEO_INTR:
+		value = m_int_status;
+		break;
+
+	case NV_PVIDEO_INTR_EN:
+		value = m_int_enabled;
+		break;
+
 	case NV_PVIDEO_LUMINANCE(0):
 	case NV_PVIDEO_LUMINANCE(1):
 	case NV_PVIDEO_CHROMINANCE(0):
@@ -207,6 +228,8 @@ void pvideo::Impl::updateIo(bool is_update)
 void
 pvideo::Impl::reset()
 {
+	m_int_status = 0;
+	m_int_enabled = 0;
 	// Values dumped from a Retail 1.0 xbox
 	debug[0] = 0x00000010;
 	debug[1] = 0x00000064;

src/nxbx/hw/video/gpu/pvideo.hpp

@@ -11,17 +11,19 @@
 #define NV_PVIDEO_MMIO_BASE (NV2A_REGISTER_BASE + NV_PVIDEO)
 #define NV_PVIDEO_SIZE 0x1000
 
-#define NV_PVIDEO_DEBUG_0 (NV2A_REGISTER_BASE + 0x00008080) // Unknown
-#define NV_PVIDEO_DEBUG_1 (NV2A_REGISTER_BASE + 0x00008084) // Unknown
-#define NV_PVIDEO_DEBUG_2 (NV2A_REGISTER_BASE + 0x00008088) // Unknown
-#define NV_PVIDEO_DEBUG_3 (NV2A_REGISTER_BASE + 0x0000808C) // Unknown
-#define NV_PVIDEO_DEBUG_4 (NV2A_REGISTER_BASE + 0x00008090) // Unknown
-#define NV_PVIDEO_DEBUG_5 (NV2A_REGISTER_BASE + 0x00008094) // Unknown
-#define NV_PVIDEO_DEBUG_6 (NV2A_REGISTER_BASE + 0x00008098) // Unknown
-#define NV_PVIDEO_DEBUG_7 (NV2A_REGISTER_BASE + 0x0000809C) // Unknown
-#define NV_PVIDEO_DEBUG_8 (NV2A_REGISTER_BASE + 0x000080A0) // Unknown
-#define NV_PVIDEO_DEBUG_9 (NV2A_REGISTER_BASE + 0x000080A4) // Unknown
-#define NV_PVIDEO_DEBUG_10 (NV2A_REGISTER_BASE + 0x000080A8) // Unknown
+#define NV_PVIDEO_DEBUG_0 (NV2A_REGISTER_BASE + 0x00008080) // debug flags 0
+#define NV_PVIDEO_DEBUG_1 (NV2A_REGISTER_BASE + 0x00008084) // debug flags 1
+#define NV_PVIDEO_DEBUG_2 (NV2A_REGISTER_BASE + 0x00008088) // debug flags 2
+#define NV_PVIDEO_DEBUG_3 (NV2A_REGISTER_BASE + 0x0000808C) // debug flags 3
+#define NV_PVIDEO_DEBUG_4 (NV2A_REGISTER_BASE + 0x00008090) // debug flags 4
+#define NV_PVIDEO_DEBUG_5 (NV2A_REGISTER_BASE + 0x00008094) // debug flags 5
+#define NV_PVIDEO_DEBUG_6 (NV2A_REGISTER_BASE + 0x00008098) // debug flags 6
+#define NV_PVIDEO_DEBUG_7 (NV2A_REGISTER_BASE + 0x0000809C) // debug flags 7
+#define NV_PVIDEO_DEBUG_8 (NV2A_REGISTER_BASE + 0x000080A0) // debug flags 8
+#define NV_PVIDEO_DEBUG_9 (NV2A_REGISTER_BASE + 0x000080A4) // debug flags 9
+#define NV_PVIDEO_DEBUG_10 (NV2A_REGISTER_BASE + 0x000080A8) // debug flags 10
+#define NV_PVIDEO_INTR (NV2A_REGISTER_BASE + 0x00008100) // Pending pvideo interrupts. Writing a 0 has no effect, and writing a 1 clears the interrupt
+#define NV_PVIDEO_INTR_EN (NV2A_REGISTER_BASE + 0x00008140) // Enable/disable pvideo interrupts
 #define NV_PVIDEO_BASE(i) (NV2A_REGISTER_BASE + 0x00008900 + (i) * 4) // TODO
 #define NV_PVIDEO_LUMINANCE(i) (NV2A_REGISTER_BASE + 0x00008910 + (i) * 4) // Unknown
 #define NV_PVIDEO_CHROMINANCE(i) (NV2A_REGISTER_BASE + 0x00008918 + (i) * 4) // Unknown