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fix: brightness of pixels
thanks kevtris
1 parent 1a553c9 commit 922ab52

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7 files changed

+6
-11
lines changed

7 files changed

+6
-11
lines changed
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src/fpga/ap_core.qsf

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -760,5 +760,5 @@ set_global_assignment -name QIP_FILE core/mf_pllbase.qip
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set_global_assignment -name SIP_FILE core/mf_pllbase.sip
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set_global_assignment -name QIP_FILE core/rtl/ic.qip
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set_global_assignment -name QIP_FILE core/rtl/sound_delta.qip
763-
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
764-
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
763+
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
764+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

src/fpga/apf/build_id.mif

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ CONTENT
1010
BEGIN
1111

1212
0E0 : 20220909;
13-
0E1 : 00125750;
14-
0E2 : 03eb96c2;
13+
0E1 : 00144039;
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0E2 : 344fee42;
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END;

src/fpga/core/core_top.sv

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -468,10 +468,7 @@ mf_pllbase mp1 (
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wire VIDEO, SCORE;
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wire HSYNC, VSYNC, HBLANK, VBLANK;
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471-
// FIXME: These video settings are not correct, they approximate at best what the original core did.
472-
// trying to use any d value above 100 causes sync issues, and trying to use hex values also causes sync issues.
473-
// Super duper awesome, help wanted.
474-
wire [7:0] video = VIDEO ? 8'd100 : SCORE ? 8'd100 : 8'd0;
471+
wire [7:0] video = (VIDEO ? 8'd255 : (SCORE ? 8'd187 : 8'd0));
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476473
// Does not do anything - just to satisfy the top.
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wire CLK_CORE_VIDEO;
@@ -502,9 +499,7 @@ mf_pllbase mp1 (
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503500
if (~(VBLANK || HBLANK)) begin
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video_de_reg <= 1;
505-
video_rgb_reg[23:16] <= video;
506-
video_rgb_reg[15:8] <= video;
507-
video_rgb_reg[7:0] <= video;
502+
video_rgb_reg <= {3{video}};
508503
end
509504

510505
// Set HSync and VSync to be high for a single cycle on the falling edge of the HSync and VSync coming out of Space Race

src/fpga/output_files/ap_core.rbf

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src/fpga/output_files/ap_core.sof

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