diff --git a/.gitignore b/.gitignore
index 64f2b5b8..96b613ce 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,8 +14,9 @@ target/
 
 # Ignore any files used by text editors or operating systems.
 .vscode/
+.zed/
 .DS_Store
 *.swp
 .idea/
 
-!espflash/src/target
\ No newline at end of file
+!espflash/src/target
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8929b614..392f8d72 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Fixed
 
 - Fix Windows connection issue by aligning reset sequence with `esptool` including RTS/DTR workaround (#999)
+- Fix board-info misreporting the crystal frequency of ESP32-C5 (#1005)
 
 ### Removed
 
diff --git a/espflash/src/target/mod.rs b/espflash/src/target/mod.rs
index 4d1fc0da..ffceed93 100644
--- a/espflash/src/target/mod.rs
+++ b/espflash/src/target/mod.rs
@@ -911,12 +911,14 @@ impl Chip {
             }
             Chip::Esp32c3 => Ok(XtalFrequency::_40Mhz), // Fixed frequency
             Chip::Esp32c5 => {
-                const UART_CLKDIV_REG: u32 = 0x6000_0014; // UART0_BASE_REG + 0x14
-                const UART_CLKDIV_MASK: u32 = 0xfffff;
-                const XTAL_CLK_DIVIDER: u32 = 1;
+                const PCR_SYSCLK_CONF_REG: u32 = 0x6009_6110; // PCR_BASE_REG + 0x110
+                const PCR_CLK_XTAL_FREQ_MASK: u32 = 0x7F;
+                const PCR_CLK_XTAL_FREQ_SHIFT: u32 = 24;
+
+                let sysclk_conf_reg = connection.read_reg(PCR_SYSCLK_CONF_REG)?;
+                let est_xtal =
+                    (sysclk_conf_reg >> PCR_CLK_XTAL_FREQ_SHIFT) & PCR_CLK_XTAL_FREQ_MASK;
 
-                let uart_div = connection.read_reg(UART_CLKDIV_REG)? & UART_CLKDIV_MASK;
-                let est_xtal = (connection.baud()? * uart_div) / 1_000_000 / XTAL_CLK_DIVIDER;
                 let norm_xtal = if est_xtal > 45 {
                     XtalFrequency::_48Mhz
                 } else {