fix: add ESP_VST_128_IP isSchedulingBoundary because instruction scheduling causes register erros

Author: chenqian

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -4329,3 +4329,15 @@ RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
 
   return std::make_unique<RISCVPipelinerLoopInfo>(LHS, RHS, Cond);
 }
+
+bool RISCVInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
+                                          const MachineBasicBlock *MBB,
+                                          const MachineFunction &MF) const {
+  if (MI.getOpcode() == RISCV::ESP_VST_128_IP ||
+      MI.getOpcode() == RISCV::ESP_VST_L_64_IP ||
+      MI.getOpcode() == RISCV::ESP_VST_H_64_IP ||
+      MI.getOpcode() == RISCV::ESP_VLDBC_8_IP ||
+      MI.getOpcode() == RISCV::ESP_ZERO_Q)
+    return true;
+  return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
+}

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -141,6 +141,10 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
+  bool isSchedulingBoundary(const MachineInstr &MI,
+                            const MachineBasicBlock *MBB,
+                            const MachineFunction &MF) const override;
+
   bool optimizeCondBranch(MachineInstr &MI) const override;
 
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;