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erhankurerhankur
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target/espressif: add esp32c61 initial support
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12 files changed

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12 files changed

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‎src/rtos/FreeRTOS.c‎

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@@ -208,6 +208,23 @@ static const struct freertos_params freertos_params_list[] = {
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NULL,
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rtos_freertos_riscv_pick_stacking_info, /* fn to pick stacking_info */
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},
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{
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"esp32c61", /* target_name */
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4, /* thread_count_width; */
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4, /* pointer_width; */
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16, /* list_next_offset; */
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8, /* list_end_offset; */
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20, /* list_width; */
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8, /* list_elem_next_offset; */
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12, /* list_elem_content_offset */
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0, /* thread_stack_offset; */
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52, /* thread_name_offset; */
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4, /* thread_counter_width */
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NULL, /* stacking_info */
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NULL,
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NULL,
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rtos_freertos_riscv_pick_stacking_info, /* fn to pick stacking_info */
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},
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{
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"esp32p4", /* target_name */
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4, /* thread_count_width; */

‎src/target/espressif/CMakeLists.txt‎

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@@ -18,6 +18,7 @@ target_sources(espressif PRIVATE
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esp32h2.c
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esp32p4.c
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esp32c5.c
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esp32c61.c
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esp.c
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esp.h
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esp_riscv.c

‎src/target/espressif/Makefile.am‎

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@@ -17,6 +17,7 @@ noinst_LTLIBRARIES += %D%/libespressif.la
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%D%/esp32c6.c \
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%D%/esp32p4.c \
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%D%/esp32c5.c \
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%D%/esp32c61.c \
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%D%/esp.c \
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%D%/esp.h \
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%D%/esp_riscv.c \

‎src/target/espressif/esp32c61.c‎

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// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* ESP32-C61 target for OpenOCD *
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* Copyright (C) 2024 Espressif Systems Ltd. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/command.h>
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#include <helper/bits.h>
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#include <target/target.h>
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#include <target/target_type.h>
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#include <target/register.h>
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#include <target/semihosting_common.h>
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#include <target/riscv/debug_defines.h>
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#include "esp_semihosting.h"
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#include "esp_riscv_apptrace.h"
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#include "esp_riscv.h"
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/* max supported hw breakpoint and watchpoint count */
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#define ESP32C61_BP_NUM 3
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#define ESP32C61_WP_NUM 3
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/* ASSIST_DEBUG registers */
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#define ESP32C61_ASSIST_DEBUG_CPU0_MON_REG 0xFFFFFFFF//0x600C2000
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#define ESP32C61_DRAM_LOW 0x40800000
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#define ESP32C61_DRAM_HIGH 0x40860000
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static bool esp32c61_is_idram_address(target_addr_t addr)
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{
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return addr >= ESP32C61_DRAM_LOW && addr < ESP32C61_DRAM_HIGH;
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}
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static const struct esp_semihost_ops esp32c61_semihost_ops = {
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.prepare = NULL,
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.post_reset = esp_semihosting_post_reset
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};
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static const struct esp_flash_breakpoint_ops esp32c61_flash_brp_ops = {
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.breakpoint_prepare = esp_algo_flash_breakpoint_prepare,
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.breakpoint_add = esp_algo_flash_breakpoint_add,
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.breakpoint_remove = esp_algo_flash_breakpoint_remove,
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.breakpoint_lazy_process = true,
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};
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static const char *esp32c61_csrs[] = {
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"mideleg", "medeleg", "mie", "mip",
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};
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static int esp32c61_target_create(struct target *target, Jim_Interp *interp)
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{
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struct esp_riscv_common *esp_riscv = calloc(1, sizeof(*esp_riscv));
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if (!esp_riscv)
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return ERROR_FAIL;
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target->arch_info = esp_riscv;
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esp_riscv->assist_debug_cpu0_mon_reg = ESP32C61_ASSIST_DEBUG_CPU0_MON_REG;
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esp_riscv->assist_debug_cpu_offset = 0;
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esp_riscv->max_bp_num = ESP32C61_BP_NUM;
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esp_riscv->max_wp_num = ESP32C61_WP_NUM;
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esp_riscv->rtccntl_reset_state_reg = 0;//ESP32C61_RTCCNTL_RESET_STATE_REG;
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esp_riscv->print_reset_reason = NULL;//&esp32c61_print_reset_reason;
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esp_riscv->existent_csrs = esp32c61_csrs;
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esp_riscv->existent_csr_size = ARRAY_SIZE(esp32c61_csrs);
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esp_riscv->is_dram_address = esp32c61_is_idram_address;
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esp_riscv->is_iram_address = esp32c61_is_idram_address;
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if (esp_riscv_alloc_trigger_addr(target) != ERROR_OK)
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return ERROR_FAIL;
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riscv_info_init(target, &esp_riscv->riscv);
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return ERROR_OK;
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}
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static int esp32c61_init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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int ret = riscv_target.init_target(cmd_ctx, target);
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if (ret != ERROR_OK)
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return ret;
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target->semihosting->user_command_extension = esp_semihosting_common;
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struct esp_riscv_common *esp_riscv = target_to_esp_riscv(target);
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ret = esp_riscv_init_arch_info(target,
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esp_riscv,
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&esp32c61_flash_brp_ops,
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&esp32c61_semihost_ops);
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if (ret != ERROR_OK)
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return ret;
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return ERROR_OK;
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}
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static const struct command_registration esp32c61_command_handlers[] = {
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{
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.usage = "",
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.chain = riscv_command_handlers,
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},
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{
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.name = "esp",
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.usage = "",
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.chain = esp_riscv_command_handlers,
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},
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{
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.name = "esp",
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.usage = "",
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.chain = esp32_apptrace_command_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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struct target_type esp32c61_target = {
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.name = "esp32c61",
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.target_create = esp32c61_target_create,
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.init_target = esp32c61_init_target,
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.deinit_target = esp_riscv_deinit_target,
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.examine = esp_riscv_examine,
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/* poll current target status */
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.poll = esp_riscv_poll,
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.halt = riscv_halt,
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.resume = esp_riscv_resume,
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.step = riscv_openocd_step,
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.assert_reset = riscv_assert_reset,
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.deassert_reset = riscv_deassert_reset,
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.read_memory = esp_riscv_read_memory,
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.write_memory = esp_riscv_write_memory,
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.checksum_memory = riscv_checksum_memory,
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.get_gdb_arch = riscv_get_gdb_arch,
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.get_gdb_reg_list = riscv_get_gdb_reg_list,
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.get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
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.add_breakpoint = esp_riscv_breakpoint_add,
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.remove_breakpoint = esp_riscv_breakpoint_remove,
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.add_watchpoint = riscv_add_watchpoint,
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.remove_watchpoint = riscv_remove_watchpoint,
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.hit_watchpoint = esp_riscv_hit_watchpoint,
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.arch_state = riscv_arch_state,
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.run_algorithm = esp_riscv_run_algorithm,
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.start_algorithm = esp_riscv_start_algorithm,
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.wait_algorithm = esp_riscv_wait_algorithm,
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.commands = esp32c61_command_handlers,
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.address_bits = riscv_xlen_nonconst,
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};

‎src/target/target.c‎

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@@ -95,6 +95,7 @@ static struct target_type *target_types[] = {
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&esp32c3_target,
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&esp32c6_target,
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&esp32c5_target,
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&esp32c61_target,
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&esp32p4_target,
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&or1k_target,
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&quark_x10xx_target,

‎src/target/target_type.h‎

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@@ -340,6 +340,7 @@ extern struct target_type esp32c3_target;
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extern struct target_type esp32c6_target;
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extern struct target_type esp32p4_target;
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extern struct target_type esp32c5_target;
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extern struct target_type esp32c61_target;
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extern struct target_type fa526_target;
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extern struct target_type feroceon_target;
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extern struct target_type hla_target;

‎tcl/board/esp32c61-bridge.cfg‎

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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Example OpenOCD configuration file for ESP32-C61 connected via ESP USB Bridge board
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#
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# For example, OpenOCD can be started for ESP32-C61 debugging on
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#
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# openocd -f board/esp32c61-bridge.cfg
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#
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# Source the JTAG interface configuration file
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source [find interface/esp_usb_bridge.cfg]
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# ESP32C61 chip id defined in the idf esp_chip_model_t
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espusbjtag chip_id 20
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# Source the ESP32-C61 configuration file
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source [find target/esp32c61.cfg]

‎tcl/board/esp32c61-builtin.cfg‎

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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Example OpenOCD configuration file for ESP32-C61 connected via builtin USB-JTAG adapter.
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#
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# For example, OpenOCD can be started for ESP32-C61 debugging on
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#
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# openocd -f board/esp32c61-builtin.cfg
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#
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# Source the JTAG interface configuration file
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source [find interface/esp_usb_jtag.cfg]
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# Source the ESP32-C61 configuration file
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source [find target/esp32c61.cfg]

‎tcl/board/esp32c61-ftdi.cfg‎

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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Example OpenOCD configuration file for ESP32-C61 connected via ESP-Prog.
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#
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# For example, OpenOCD can be started for ESP32-C61 debugging on
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#
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# openocd -f board/esp32c61-ftdi.cfg
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#
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# Source the JTAG interface configuration file
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source [find interface/ftdi/esp32_devkitj_v1.cfg]
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# Source the ESP32-C61 configuration file
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source [find target/esp32c61.cfg]

‎tcl/esp-config-schema.json‎

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@@ -136,6 +136,7 @@
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"esp32c3",
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"esp32c5",
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"esp32c6",
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"esp32c61",
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"esp32h2",
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"esp32p4"
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]

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