{"payload":{"header_redesign_enabled":false,"results":[{"id":"279968526","archived":false,"color":"#DAE1C2","followers":70,"has_funding_file":false,"hl_name":"f4pga/prjuray","hl_trunc_description":"Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.","language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":279968526,"name":"prjuray","owner_id":94862021,"owner_login":"f4pga","updated_at":"2022-02-09T08:43:26.180Z","has_issues":true}},"sponsorable":false,"topics":["fpga","xilinx","vivado","fuzzer","xilinx-fpga","bitstream","ultrascale","symbiflow","ultrascale-plus"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":77,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Af4pga%252Fprjuray%2B%2Blanguage%253ASystemVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/f4pga/prjuray/star":{"post":"GShU11oXPw6QOAIa7XIZ8wvEOhSpE-3ZezNW-RnTAKQu-hm3zKbW1lhB9u_D5Yz2cfqXPfKLDGjeXWpn1Wfmzw"},"/f4pga/prjuray/unstar":{"post":"Ki54MjoUQrcuJEf2vIeXQtHdYl-4RkdRv6fKBMkShqz_4I65s6EAoTmgBPItH9wVCcZP-V28IWJwF8hhxcdJrg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"81wiymbJ8aU8NPzVLI80GMSM06pDIP18lVoZ5NQ0hldtwc9bsWJIy2-YiO_DCWFC_j1Ih2UknpW3dpxNVuEa9g"}}},"title":"Repository search results"}