last_edittttttted_today.txt

.global asm_main
.align 4
memory: .space 2000000 ;@ 2MB reserved for own use throughout program
.align 4
Zmem: .space 2000000 ;@ 2MB for uploading Zprogram
.align 4
Zstack: .space 1000000 ;@ 1MB for Zstack
.align 4
FZreg: .space 1000000 ;@ 1MB for function local Zregisters
.align 4
temp: .space 256 ;@ 256B temporary storage for holding temp
;@ operands to variable operand count instructions
.align 4

asm_main:

;@ Set up transmitter to what TeraTerm is expecting
;@ receiver is already set up
LDR R9, =0x20

LDR R4, =0xE0001004 ;@ Mode Register -- Tera Term transmitter
STR R9, [R4, #0]

;@ Start Baud rate setup
LDR R9, =0x3E ;@ 62 in decimal value
LDR R4, =0xE0001018 ;@ Baud rate generator
STR R9, [R4, #0]

;@ Complete baud rate setup
LDR R9, =0x6
LDR R4, =0xE0001034 ;@ Baud rate divider
STR R9, [R4, #0]

;@ Enable and reset the UART
LDR R9, =0x117
LDR R4, =0xE0001000 ;@ Control register
STR R9, [R4, #0]

  LDR R7, =Zmem
  MOV R4, #0
  LDRB R8, =0b10110010
  STRB R8, [R7, R4]
  ADD R4, R4, #1
  LDRB R8, =0b00100011
  STRB R8, [R7, R4]
  ADD R4, R4, #1
  LDRB R8, =0b01101101
  STRB R8, [R7, R4]
  ADD R4, R4, #1
  LDRB R8, =0b10100000
  STRB R8, [R7, R4]
  ADD R4, R4, #1
  LDRB R8, =0b11110011
  STRB R8, [R7, R4]
  MOV R4, #0

decode_instructions_loop:
  LDRB R8, [R7, R4] ;@ Fetch byte from Zmem at ZPC -- Opcode instruction type bits
  ADD R4, R4, #1
  LSR R9, R8, #6 ;@ shift the bits we want to the right end
  CMP R9, #3 ;@ C-Type - 11
  BEQ c_type
  CMP R9, #2 ;@ A-Type - 10
  BEQ a_type
  CMP R9, #1 ;@ B-Type - 01
  BEQ b_type

a_type:
  LDR R10, =15 ;@ instruction indicator -- bits 3 - 0
  AND R9, R8, R10
  PUSH { R9 }
  LDR R10, =48 ;@ bits 5 & 4
  AND R9, R8, R10
  CMP R9, #48 ;@ operand count is zero - 11
  BEQ no_operands
  CMP R9, #0 ;@ two byte constant - 00
  BLEQ sixteen_bit_fetch
  CMP R9, #16 ;@ one byte constant - 01
  BLEQ eight_bit_fetch
  CMP R9, #32 ;@ one byte register indicator - 10
  BLEQ eight_bit_fetch

sixteen_bit_fetch_for_a_type:
  LDR R12, =temp
  LDRB R10, [R7, R4]
  ADD R4, R4, #1
  LSL R10, R10, #8
  LDRB R11, [R7, R4]
  ADD R4, R4, #1
  ADD R0, R10, R11
  MOVEQ PC, LR




/*
a_type_fetch: //this function will be called from the Zprocedures that have one operand
  LDRB R10, [R7, R4]
  ADD R4, R4, #1
  LDR R11,= 0b11000000
*/
b_type:
  LDR R10, =64
  AND R11, R8, R10
  CMP R11, #0 ;@ 1st operand: one byte constant
  CMP R11, #64 ;@ 1st operand: operand in a register
  LDR R10, =32
  AND R11, R8, R10
  CMP R11, #0 ;@ 2nd operand: one byte constant
  CMP R11, #32 ;@ 2nd operand: operand in register

c_type:
  LDR R10, =31
  AND R9, R8, R10
  PUSH {R9} ;@ instruction indicator
  LDR R10, =32
  AND R9, R8, R10
  CMP R9, #0 ;@ two operands
//  BEQ two_operands
//  BNE var_operands ;@ variable operand count




no_operands:
;@ for basic points
  POP {R9} ;@ R9 is the instruction indicator
  CMP R9, #2
  BEQ OP0_2
  BNE no_operands
OP0_2: ;@ PRINT
  LDRB R8, [R7, R4]
  ADD R4, R4, #1
  LDRB R9, [R7, R4]
  ADD R4, R4, #1
  LSL R8, #8
  ADD R8, R8, R9
  read:
    LDR R9, =#31744
	AND R10, R8, R9
	LSR R12, R10, #10
	PUSH {R8-R12}
	BL Check_transmitter_fifo_and_print
	POP {R8-R12}
	LDR R9, =#992
	AND R10, R8, R9
	LSR R12, R10, #5
	PUSH {R8-R12}
	BL Check_transmitter_fifo_and_print
	POP {R8-R12}
	LDR R9, =#31
	AND R10, R8, R9
	PUSH {R8-R12}
	BL Check_transmitter_fifo_and_print
	POP {R8-R12}
	LDR R9, =#32768
	CMP R8, R9
    BEQ done
    BNE OP0_2

Check_transmitter_fifo_and_print:
  LDR R9, =0xE000102C ;@  XUARTPS_SR_OFFSET
  LDRB R11, [R9]
  TST R11, #8
  BEQ Check_transmitter_fifo_and_print
  BNE print
  print:
  LDR R10, =0xE0001030
  CMP R12, #0
  MOVEQ R12, #32
  STREQ R12, [R10]
  CMP R12, #1
  MOVEQ R12, #10
  STREQ R12, [R12]
  ADD R12, R12, #91
  MOV R11, #97
  which_letter:
    CMP R11, R12
	STREQ R12, [R10]
	ADDPL R11, R11, #1
    CMP R11, #122
	BNE which_letter
	MOV R12, #63
	STR R12, [R10]
    MOV PC, LR


/*
print:
  LDR R10, =0xE0001030
  CMP R12, #0
  MOVEQ R12, #32
  STREQ R12, [R10]
  CMP R12, #1
  MOVEQ R12, #10
  STREQ R12, [R12]
  ADD R12, R12, #91
  MOV R11, #97
  which_letter:
    TST R12, R11
	STRNE R12, [R10]
	ADDEQ R11, R11, #1
    CMP R11, #122
	BNE which_letter
	MOV R12, #63
	STR R12, [R10]
    MOV PC, LR

*/


/*
OP0_8: ;@ RET_POPPED
CMP R9, #13
OP0_D: ;@ VERIFY

one_operand:
;@ for basic points
OP1_5: ;@ INC
OP1_6: ;@ DEC
OP1_B: ;@ RET


fetch_for_C:
  LDRB R10, [R7, R4] ;@ fetching a byte from Zmem at ZPC
  ADD R4, R4,#1 ;@ incrementing ZPC
  MOV R8, #0 ;@ temp memory counter
  LDR R11,= 0b11000000
  loop:
	AND R12, R11, R10
	CMP R12, #0
	BEQ sbit_constant
	CMP R12, #1
	BEQ ebit_constant
	CMP R12, #2
	BEQ op_in_reg
	CMP R12, #3
	;@BEQ return Most likely MOV PC, LR
      sbit_constant:
        LDR R12, =temp
        LDRB R9, [R7, R4]
	    ADD R4, R4, #1
	    STRB R9, [R12, R8] ;@ possible logical error
	    ADD R8, R8, #1
        LDRB R9, [R7, R4]
	    ADD R4, R4, #1
	    STRB R9, [R12, R8] ;@ possible logical error
	    ADD R8, R8, #1
	    LSR R11, #2
	    B loop
      ebit_constant:
        LDR R12, =temp
	    LDR R9, [R7, R4]
	    ADD R4, R4, #2
	    STR R9, [R12, R8]
	    ADD R8, R8, #4
	    LSR R11, #2
	    B loop
      op_in_reg:
	    LDR R12, =temp






*/







/*

two_operands:
  POP {R9}
;@ Basic points
  LDR R10, =#0x01
  CMP R9, R10
  BEQ OP2_01 ;@ JE
  LDR R10, =#0x02
  CMP R9, R10
  BEQ OP2_02 ;@ JL
  LDR R10, =#0x03
  CMP R9, R10
  BEQ OP2_03 ;@ JG
  LDR R10, =#0x0A
  CMP R9, R10
  BEQ OP2_0A ;@ TEST_ATTR
  LDR R10, =#0x0B
  CMP R9, R10
  BEQ OP2_0B ;@ SET_ATTR
  LDR R10, =#0x0C
  CMP R9, R10
  BEQ OP2_0C ;@ CLEAR_ATTR
  LDR R10, =#0x14
  CMP R9, R10
  BEQ OP2_14 ;@ ADD
  LDR R10, =#0x15
  CMP R9, R10
  BEQ OP2_15 ;@ SUB
  LDR R10, =#0x16
  CMP R9, R10
  BEQ OP2_16 ;@ MUL
  LDR R10, =#0x17
  CMP R9, R10
  BEQ OP2_17 ;@ DIV
  LDR R10, =#0x18
  CMP R9, R10
  BEQ OP2_18 ;@ MOD
  LDR R10, =#0x19
  CMP R9, R10
  BEQ OP2_19 ;@ CALL_2S
  LDR R10, =#0x1A
  CMP R9, R10
  BEQ OP2_1A ;@ CALL_2N

*/

  /* ;@all go to crash mode
  LDR R10, =#0x00
  CMP R9, R10
  BEQ crash_mode ;@ Illegal instruction
  LDR R10, =#0x04
  CMP R9, R10
  BEQ crash_mode ;@ DEC_CHK
  LDR R10, =#0x05
  CMP R9, R10
  BEQ crash_mode ;@ INC_CHK
  LDR R10, =#0x1C
  CMP R9, R10
  BEQ crash_mode ;@ crash_mode
  LDR R10, =#0x1D
  CMP R9, R10
  BEQ crash_mode ;@ crash_mode
  LDR R10, =#0x1E
  CMP R9, R10
  BEQ OP2_1E ;@ crash_mode
  LDR R10, =#0x1F
  CMP R9, R10
  BEQ crash_mode ;@ crash_mode
*/

OP2_01: ;@ JE
OP2_02: ;@ JL
OP2_03: ;@ JG
OP2_0A: ;@ TEST_ATTR
OP2_0B: ;@ SET_ATTR
OP2_0C: ;@ CLEAR_ATTR

/*
OP2_14: ;@ ADD
  ADD R4, R4, #1
  LDR R8, [R7, R4]
  MOV R10, #6
  PUSH {R8-R12}
  BL fetch_next
  POP {R8-R12}
*/
/*
var_operands:
  POP {R9}
  ;@ for basic points
  CMP R9, #5
  BEQ VAR_05 ;@ PRINT_CHAR
  CMP R9, #0x08
  BEQ PUSH
  CMP R9, #0x09
  BEQ PULL
  CMP R9, #0x18
  BEQ NOT
  BNE var_operands

  ;@BNE carsh
*/
VAR_05: ;@ PRINT_CHAR
  //ADD R4, R4, #2
  LDR R4,=2
  LDR R8, [R7, R4]
  LDR R12, =0xE0001030
  STR R8, [R12,#0]
  B done

done:
  B done