diff --git a/electron22/electron22-deps-parser.py b/electron22/electron22-deps-parser.py new file mode 100644 index 000000000..b040f9b55 --- /dev/null +++ b/electron22/electron22-deps-parser.py @@ -0,0 +1,31 @@ +from importlib.util import spec_from_loader, module_from_spec +from importlib.machinery import SourceFileLoader +import sys +import re + +spec = spec_from_loader("deps", SourceFileLoader("deps", sys.argv[2])) +deps = module_from_spec(spec) + +# The DEPS file is not a standard python file +# Let's apply some hacks to trick the interpreter. +deps.Str = str +deps.Var = str + +spec.loader.exec_module(deps) + +match sys.argv[1]: + case 'infra': + # Return the commit of infra repo + infra_rev = deps.vars['luci_go'] + print(infra_rev.split(':')[-1]) + case 'luci_go': + # Return the commit of luci repo + luci_go_rev = deps.deps["infra/go/src/go.chromium.org/luci"] + print(luci_go_rev.split('@')[-1]) + case 'esbuild': + esbuild_ver_full = deps.deps["src/third_party/devtools-frontend/src/third_party/esbuild"]["packages"][0]["version"] + esbuild_ver = re.match("^(.+)\.chromium.*$", esbuild_ver_full.split("@")[-1])[1] + print(esbuild_ver) + case _: + print("Unsupported arguments!", file=sys.stderr) + sys.exit(-1) diff --git a/electron22/electron22-extensions-common-api-runtime.json-support-riscv64.patch b/electron22/electron22-extensions-common-api-runtime.json-support-riscv64.patch new file mode 100644 index 000000000..3e2945f43 --- /dev/null +++ b/electron22/electron22-extensions-common-api-runtime.json-support-riscv64.patch @@ -0,0 +1,19 @@ +--- extensions/common/api/runtime.json.orig 2023-07-11 07:42:27.856148697 -0400 ++++ extensions/common/api/runtime.json 2023-07-11 07:43:54.566062017 -0400 +@@ -92,14 +92,14 @@ + { + "id": "PlatformArch", + "type": "string", +- "enum": ["arm", "arm64", "x86-32", "x86-64", "mips", "mips64"], ++ "enum": ["arm", "arm64", "x86-32", "x86-64", "mips", "mips64", "riscv64"], + "description": "The machine's processor architecture." + }, + { + "id": "PlatformNaclArch", + "description": "The native client architecture. This may be different from arch on some platforms.", + "type": "string", +- "enum": ["arm", "x86-32", "x86-64", "mips", "mips64"] ++ "enum": ["arm", "x86-32", "x86-64", "mips", "mips64", "riscv64"] + }, + { + "id": "PlatformInfo", diff --git a/electron22/electron22-grab-commit.py b/electron22/electron22-grab-commit.py deleted file mode 100644 index 12de4435a..000000000 --- a/electron22/electron22-grab-commit.py +++ /dev/null @@ -1,25 +0,0 @@ -from importlib.util import spec_from_loader, module_from_spec -from importlib.machinery import SourceFileLoader -import sys - -spec = spec_from_loader("deps", SourceFileLoader("deps", sys.argv[2])) -deps = module_from_spec(spec) - -# The DEPS file is not a standard python file -# Let's apply some hacks to trick the interpreter. -deps.Str = str -deps.Var = str - -spec.loader.exec_module(deps) - -if sys.argv[1] == 'infra': - # Return the commit of infra repo - infra_rev = deps.vars['luci_go'] - print(infra_rev.split(':')[-1]) -elif sys.argv[1] == 'luci_go': - # Return the commit of luci repo - luci_go_rev = deps.deps["infra/go/src/go.chromium.org/luci"] - print(luci_go_rev.split('@')[-1]) -else: - print("Unsupported arguments!", file=sys.stderr) - sys.exit(-1) diff --git a/electron22/electron22-relax-constraints-on-VirtualCursor-layout.patch b/electron22/electron22-relax-constraints-on-VirtualCursor-layout.patch new file mode 100644 index 000000000..2510d1000 --- /dev/null +++ b/electron22/electron22-relax-constraints-on-VirtualCursor-layout.patch @@ -0,0 +1,46 @@ +From 7d1394bd639e3bcf68082ac3fc33eeed6a00d2e6 Mon Sep 17 00:00:00 2001 +From: Elly Fong-Jones +Date: Thu, 02 Mar 2023 00:15:11 +0000 +Subject: [PATCH] sql: relax constraints on VirtualCursor layout + +VirtualCursor::FromSqliteCursor required that VirtualCursor had a +standard layout, but in fact VirtualCursor shouldn't have a standard +layout, and the fact that it does with libc++ is a deviation from the +C++ standard. This change: + +1. Relaxes the requirement that VirtualCursor has a standard layout, and +2. Relaxes the requirement that the sqlite_cursor_ field has to be at + offset 0 + +by use of offsetof() and pointer subtraction. This change both improves +standards compliance and makes this code build with libstdc++. + +Bug: 1380656 +Change-Id: I9c47abd9197b187da0360ca5619ccf7dadab4f33 +Reviewed-on: https://chromium-review.googlesource.com/c/chromium/src/+/4292313 +Reviewed-by: Austin Sullivan +Commit-Queue: Elly Fong-Jones +Cr-Commit-Position: refs/heads/main@{#1111925} +--- + +diff --git a/sql/recover_module/cursor.h b/sql/recover_module/cursor.h +index 1970bdca..4cb0655 100644 +--- a/sql/recover_module/cursor.h ++++ b/sql/recover_module/cursor.h +@@ -63,12 +63,10 @@ + // |sqlite_cursor| must have been returned by VirtualTable::SqliteCursor(). + static inline VirtualCursor* FromSqliteCursor( + sqlite3_vtab_cursor* sqlite_cursor) { +- static_assert(std::is_standard_layout::value, +- "needed for the reinterpret_cast below"); +- static_assert(offsetof(VirtualCursor, sqlite_cursor_) == 0, +- "sqlite_cursor_ must be the first member of the class"); +- VirtualCursor* result = reinterpret_cast(sqlite_cursor); +- DCHECK_EQ(sqlite_cursor, &result->sqlite_cursor_); ++ VirtualCursor* result = reinterpret_cast( ++ (reinterpret_cast(sqlite_cursor) - ++ offsetof(VirtualCursor, sqlite_cursor_))); ++ CHECK_EQ(sqlite_cursor, &result->sqlite_cursor_); + return result; + } + diff --git a/electron22/electron22-riscv-crashpad.patch b/electron22/electron22-riscv-crashpad.patch index 19de06253..42c3cb859 100644 --- a/electron22/electron22-riscv-crashpad.patch +++ b/electron22/electron22-riscv-crashpad.patch @@ -1,54 +1,87 @@ -Index: src/third_party/crashpad/crashpad/minidump/minidump_context.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/minidump/minidump_context.h -+++ src/third_party/crashpad/crashpad/minidump/minidump_context.h -@@ -637,6 +637,41 @@ struct MinidumpContextMIPS64 { +From 4f5dd672296e82f7bccc245125e6cd77d6e56528 Mon Sep 17 00:00:00 2001 +From: Thomas Gales +Date: Thu, 08 Jun 2023 21:08:54 +0000 +Subject: [PATCH] [riscv] Add RISC-V Linux support + +Only RV64GC is supported. + +Bug: fuchsia:127655 + +Tested: `python build/run_tests.py` on RISC-V emulator +Tested: Created minidump via self-induced crash on RISC-V emulator, +ran through Breakpad stackwalker + +Change-Id: I713797cd623b0a758269048e01696cbce502ca6c +Reviewed-on: https://chromium-review.googlesource.com/c/crashpad/crashpad/+/4581050 +Reviewed-by: Joshua Peraza +--- + +diff --git a/minidump/minidump_context.h b/minidump/minidump_context.h +index 30988d8..12413de 100644 +--- a/minidump/minidump_context.h ++++ b/minidump/minidump_context.h +@@ -637,6 +637,56 @@ uint64_t fir; }; -+//! \brief 64bit RISC-V-specifc flags for MinidumpContextRISCV64::context_flags. -+//! Based on minidump_cpu_riscv64.h from breakpad ++//! \brief 64-bit RISCV-specific flags for ++//! MinidumpContextRISCV64::context_flags. +enum MinidumpContextRISCV64Flags : uint32_t { + //! \brief Identifies the context structure as RISCV64. -+ kMinidumpContextRISCV64 = 0x00080000, ++ kMinidumpContextRISCV64 = 0x08000000, + + //! \brief Indicates the validity of integer registers. + //! -+ //! Registers `x1`-`x31` and pc are valid. -+ kMinidumpContextRISCV64Integer = kMinidumpContextRISCV64 | 0x00000002, ++ //! Registers 'pc' and `x1`-`x31` are valid. ++ kMinidumpContextRISCV64Integer = kMinidumpContextRISCV64 | 0x00000001, + + //! \brief Indicates the validity of floating point registers. + //! -+ //! Floating point registers `f0`-`f31`, and `fcsr` are valid -+ kMinidumpContextRISCV64FloatingPoint = kMinidumpContextRISCV64 | 0x00000004, ++ //! Floating point registers `f0`-`f31` are valid. ++ kMinidumpContextRISCV64FloatingPoint = kMinidumpContextRISCV64 | 0x00000002, + + //! \brief Indicates the validity of all registers. + kMinidumpContextRISCV64All = kMinidumpContextRISCV64Integer | -+ kMinidumpContextRISCV64FloatingPoint, ++ kMinidumpContextRISCV64FloatingPoint, +}; + -+//! \brief A 64bit RISCV CPU context (register state) carried in a minidump file. ++//! \brief A 64-bit RISC-V CPU context (register state) carried in a minidump ++//! file. ++//! ++//! This structure is versioned. Increment |kVersion| when changing this ++//! structure. +struct MinidumpContextRISCV64 { -+ uint64_t context_flags; + -+ //! \brief General purpose registers. -+ uint64_t regs[32]; ++ //! \brief The structure’s currently-defined version number. ++ static constexpr uint32_t kVersion = 1; ++ ++ //! \brief Indicates the validity of fields in this structure. ++ uint32_t context_flags; ++ ++ //! \brief The structure’s version number. ++ uint32_t version; ++ ++ //! \brief The program counter register. ++ uint64_t pc; ++ ++ //! \brief The integer registers, x1 through x31. ++ uint64_t regs[31]; + -+ //! \brief FPU registers. ++ //! \brief The floating point registers. + uint64_t fpregs[32]; + -+ //! \brief FPU status register. -+ uint64_t fcsr; ++ //! \brief The floating point control and status register. ++ uint32_t fcsr; +}; + } // namespace crashpad #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ -Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc -+++ src/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc -@@ -102,6 +102,13 @@ MinidumpContextWriter::CreateFromSnapsho +diff --git a/minidump/minidump_context_writer.cc b/minidump/minidump_context_writer.cc +index 5f741ed..84c0148 100644 +--- a/minidump/minidump_context_writer.cc ++++ b/minidump/minidump_context_writer.cc +@@ -102,6 +102,13 @@ break; } @@ -62,14 +95,14 @@ Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc default: { LOG(ERROR) << "unknown context architecture " << context_snapshot->architecture; -@@ -555,5 +562,42 @@ size_t MinidumpContextMIPS64Writer::Cont - DCHECK_GE(state(), kStateFrozen); +@@ -556,4 +563,42 @@ return sizeof(context_); } -+ + +MinidumpContextRISCV64Writer::MinidumpContextRISCV64Writer() + : MinidumpContextWriter(), context_() { + context_.context_flags = kMinidumpContextRISCV64; ++ context_.version = MinidumpContextRISCV64::kVersion; +} + +MinidumpContextRISCV64Writer::~MinidumpContextRISCV64Writer() = default; @@ -80,6 +113,8 @@ Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc + DCHECK_EQ(context_.context_flags, kMinidumpContextRISCV64); + + context_.context_flags = kMinidumpContextRISCV64All; ++ context_.version = MinidumpContextRISCV64::kVersion; ++ context_.pc = context_snapshot->pc; + + static_assert(sizeof(context_.regs) == sizeof(context_snapshot->regs), + "GPRs size mismatch"); @@ -87,9 +122,7 @@ Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc + + static_assert(sizeof(context_.fpregs) == sizeof(context_snapshot->fpregs), + "FPRs size mismatch"); -+ memcpy(context_.fpregs, -+ context_snapshot->fpregs, -+ sizeof(context_.fpregs)); ++ memcpy(context_.fpregs, context_snapshot->fpregs, sizeof(context_.fpregs)); + context_.fcsr = context_snapshot->fcsr; +} + @@ -103,13 +136,13 @@ Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc + DCHECK_GE(state(), kStateFrozen); + return sizeof(context_); +} - ++ } // namespace crashpad -Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/minidump/minidump_context_writer.h -+++ src/third_party/crashpad/crashpad/minidump/minidump_context_writer.h -@@ -369,6 +369,49 @@ class MinidumpContextMIPS64Writer final +diff --git a/minidump/minidump_context_writer.h b/minidump/minidump_context_writer.h +index 6660be4..8e39c66 100644 +--- a/minidump/minidump_context_writer.h ++++ b/minidump/minidump_context_writer.h +@@ -369,6 +369,50 @@ MinidumpContextMIPS64 context_; }; @@ -124,7 +157,8 @@ Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.h + + ~MinidumpContextRISCV64Writer() override; + -+ //! \brief Initializes the MinidumpContextRISCV based on \a context_snapshot. ++ //! \brief Initializes the MinidumpContextRISCV64 based on \a ++ //! context_snapshot. + //! + //! \param[in] context_snapshot The context snapshot to use as source data. + //! @@ -159,66 +193,272 @@ Index: src/third_party/crashpad/crashpad/minidump/minidump_context_writer.h } // namespace crashpad #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_WRITER_H_ -Index: src/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc -+++ src/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc -@@ -175,6 +175,10 @@ std::string MinidumpMiscInfoDebugBuildSt +diff --git a/minidump/minidump_context_writer_test.cc b/minidump/minidump_context_writer_test.cc +index e2a04d1..9eebe81 100644 +--- a/minidump/minidump_context_writer_test.cc ++++ b/minidump/minidump_context_writer_test.cc +@@ -143,6 +143,49 @@ + } + } + ++TYPED_TEST(MinidumpContextWriter, MinidumpContextRISCV64Writer) { ++ { ++ // Make sure that a heap-allocated context writer has the proper alignment, ++ // because it may be nonstandard. ++ auto context_writer = std::make_unique(); ++ EXPECT_EQ(reinterpret_cast(context_writer.get()) & ++ (alignof(MinidumpContextRISCV64Writer) - 1), ++ 0u); ++ } ++ ++ StringFile string_file; ++ ++ { ++ // Make sure that a context writer that’s untouched writes a zeroed-out ++ // context. ++ SCOPED_TRACE("zero"); ++ ++ EmptyContextTest(ExpectMinidumpContextRISCV64); ++ } ++ ++ { ++ SCOPED_TRACE("nonzero"); ++ ++ string_file.Reset(); ++ constexpr uint32_t kSeed = 0x808664; ++ ++ MinidumpContextRISCV64Writer context_writer; ++ InitializeMinidumpContextRISCV64(context_writer.context(), kSeed); ++ ++ EXPECT_TRUE(context_writer.WriteEverything(&string_file)); ++ ASSERT_EQ(string_file.string().size(), sizeof(MinidumpContextRISCV64)); ++ ++ const MinidumpContextRISCV64* observed = ++ MinidumpWritableAtRVA(string_file.string(), ++ TypeParam(0)); ++ ASSERT_TRUE(observed); ++ ++ ExpectMinidumpContextRISCV64(kSeed, observed, false); ++ } ++} ++ + template + void FromSnapshotTest(const CPUContext& snapshot_context, + void (*expect_context)(uint32_t, const Context*, bool), +@@ -268,6 +311,23 @@ + TypeParam>(context, ExpectMinidumpContextMIPS64, kSeed); + } + ++TYPED_TEST(MinidumpContextWriter, RISCV64_Zeros) { ++ EmptyContextTest(ExpectMinidumpContextRISCV64); ++} ++ ++TYPED_TEST(MinidumpContextWriter, RISCV64_FromSnapshot) { ++ constexpr uint32_t kSeed = 64; ++ CPUContextRISCV64 context_riscv64; ++ CPUContext context; ++ context.riscv64 = &context_riscv64; ++ InitializeCPUContextRISCV64(&context, kSeed); ++ FromSnapshotTest(context, ExpectMinidumpContextRISCV64, kSeed); ++} ++ + } // namespace + } // namespace test + } // namespace crashpad +diff --git a/minidump/minidump_extensions.h b/minidump/minidump_extensions.h +index f96cf25..a5f442b 100644 +--- a/minidump/minidump_extensions.h ++++ b/minidump/minidump_extensions.h +@@ -210,6 +210,9 @@ + //! \deprecated Use #kMinidumpCPUArchitectureARM64 instead. + kMinidumpCPUArchitectureARM64Breakpad = 0x8003, + ++ //! \brief Used by Breakpad for 64-bit RISC-V. ++ kMinidumpCPUArchitectureRISCV64Breakpad = 0x8006, ++ + //! \brief Unknown CPU architecture. + kMinidumpCPUArchitectureUnknown = PROCESSOR_ARCHITECTURE_UNKNOWN, + }; +diff --git a/minidump/minidump_misc_info_writer.cc b/minidump/minidump_misc_info_writer.cc +index 133ae30..1abb46c 100644 +--- a/minidump/minidump_misc_info_writer.cc ++++ b/minidump/minidump_misc_info_writer.cc +@@ -175,6 +175,8 @@ static constexpr char kCPU[] = "mips"; #elif defined(ARCH_CPU_MIPS64EL) static constexpr char kCPU[] = "mips64"; -+#elif defined(ARCH_CPU_RISCV32) -+ static constexpr char kCPU[] = "riscv32"; +#elif defined(ARCH_CPU_RISCV64) + static constexpr char kCPU[] = "riscv64"; #else #error define kCPU for this CPU #endif -Index: src/third_party/crashpad/crashpad/snapshot/capture_memory.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/capture_memory.cc -+++ src/third_party/crashpad/crashpad/snapshot/capture_memory.cc -@@ -117,6 +117,16 @@ void CaptureMemory::PointedToByContext(c +diff --git a/minidump/minidump_system_info_writer.cc b/minidump/minidump_system_info_writer.cc +index 4468c41..e2ab775 100644 +--- a/minidump/minidump_system_info_writer.cc ++++ b/minidump/minidump_system_info_writer.cc +@@ -132,6 +132,9 @@ + case kCPUArchitectureARM64: + cpu_architecture = kMinidumpCPUArchitectureARM64; + break; ++ case kCPUArchitectureRISCV64: ++ cpu_architecture = kMinidumpCPUArchitectureRISCV64Breakpad; ++ break; + default: + NOTREACHED(); + cpu_architecture = kMinidumpCPUArchitectureUnknown; +diff --git a/minidump/test/minidump_context_test_util.cc b/minidump/test/minidump_context_test_util.cc +index 5746e4c..b40558c 100644 +--- a/minidump/test/minidump_context_test_util.cc ++++ b/minidump/test/minidump_context_test_util.cc +@@ -272,6 +272,31 @@ + context->dsp_control = value++; + } + ++void InitializeMinidumpContextRISCV64(MinidumpContextRISCV64* context, ++ uint32_t seed) { ++ if (seed == 0) { ++ memset(context, 0, sizeof(*context)); ++ context->context_flags = kMinidumpContextRISCV64; ++ context->version = MinidumpContextRISCV64::kVersion; ++ return; ++ } ++ ++ context->context_flags = kMinidumpContextRISCV64All; ++ context->version = MinidumpContextRISCV64::kVersion; ++ ++ uint32_t value = seed; ++ ++ context->pc = value++; ++ for (size_t index = 0; index < std::size(context->regs); ++index) { ++ context->regs[index] = value++; ++ } ++ ++ for (size_t index = 0; index < std::size(context->fpregs); ++index) { ++ context->fpregs[index] = value++; ++ } ++ context->fcsr = value++; ++} ++ + namespace { + + // Using Google Test assertions, compares |expected| to |observed|. This is +@@ -601,5 +626,24 @@ + EXPECT_EQ(observed->dsp_control, expected.dsp_control); + } + ++void ExpectMinidumpContextRISCV64(uint32_t expect_seed, ++ const MinidumpContextRISCV64* observed, ++ bool snapshot) { ++ MinidumpContextRISCV64 expected; ++ InitializeMinidumpContextRISCV64(&expected, expect_seed); ++ ++ EXPECT_EQ(observed->context_flags, expected.context_flags); ++ EXPECT_EQ(observed->version, expected.version); ++ ++ for (size_t index = 0; index < std::size(expected.regs); ++index) { ++ EXPECT_EQ(observed->regs[index], expected.regs[index]); ++ } ++ ++ for (size_t index = 0; index < std::size(expected.fpregs); ++index) { ++ EXPECT_EQ(observed->fpregs[index], expected.fpregs[index]); ++ } ++ EXPECT_EQ(observed->fcsr, expected.fcsr); ++} ++ + } // namespace test + } // namespace crashpad +diff --git a/minidump/test/minidump_context_test_util.h b/minidump/test/minidump_context_test_util.h +index 793e2c3..4ce5c1e 100644 +--- a/minidump/test/minidump_context_test_util.h ++++ b/minidump/test/minidump_context_test_util.h +@@ -47,6 +47,8 @@ + void InitializeMinidumpContextMIPS(MinidumpContextMIPS* context, uint32_t seed); + void InitializeMinidumpContextMIPS64(MinidumpContextMIPS* context, + uint32_t seed); ++void InitializeMinidumpContextRISCV64(MinidumpContextRISCV64* context, ++ uint32_t seed); + //! \} + + //! \brief Verifies, via Google Test assertions, that a context structure +@@ -85,6 +87,9 @@ + void ExpectMinidumpContextMIPS64(uint32_t expect_seed, + const MinidumpContextMIPS64* observed, + bool snapshot); ++void ExpectMinidumpContextRISCV64(uint32_t expect_seed, ++ const MinidumpContextRISCV64* observed, ++ bool snapshot); + //! \} + + } // namespace test +diff --git a/snapshot/capture_memory.cc b/snapshot/capture_memory.cc +index 0a465d2..c1c6fba 100644 +--- a/snapshot/capture_memory.cc ++++ b/snapshot/capture_memory.cc +@@ -117,6 +117,11 @@ for (size_t i = 0; i < std::size(context.mipsel->regs); ++i) { MaybeCaptureMemoryAround(delegate, context.mipsel->regs[i]); } -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ if (context.architecture == kCPUArchitectureRISCV64) { -+ for (size_t i = 0; i < std::size(context.riscv64->regs); ++i) { -+ MaybeCaptureMemoryAround(delegate, context.riscv64->regs[i]); -+ } -+ } else { -+ for (size_t i = 0; i < std::size(context.riscv32->regs); ++i) { -+ MaybeCaptureMemoryAround(delegate, context.riscv32->regs[i]); -+ } ++#elif defined(ARCH_CPU_RISCV64) ++ MaybeCaptureMemoryAround(delegate, context.riscv64->pc); ++ for (size_t i = 0; i < std::size(context.riscv64->regs); ++i) { ++ MaybeCaptureMemoryAround(delegate, context.riscv64->regs[i]); + } #else #error Port. #endif -Index: src/third_party/crashpad/crashpad/snapshot/cpu_architecture.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/cpu_architecture.h -+++ src/third_party/crashpad/crashpad/snapshot/cpu_architecture.h -@@ -43,7 +43,13 @@ enum CPUArchitecture { +diff --git a/snapshot/cpu_architecture.h b/snapshot/cpu_architecture.h +index 4003a92..26d45f8 100644 +--- a/snapshot/cpu_architecture.h ++++ b/snapshot/cpu_architecture.h +@@ -43,7 +43,10 @@ kCPUArchitectureMIPSEL, //! \brief 64-bit MIPSEL. - kCPUArchitectureMIPS64EL + kCPUArchitectureMIPS64EL, + -+ //! \brief 32-bit RISCV. -+ kCPUArchitectureRISCV32, -+ -+ //! \brief 64-bit RISCV. -+ kCPUArchitectureRISCV64 ++ //! \brief 64-bit RISC-V. ++ kCPUArchitectureRISCV64, }; } // namespace crashpad -Index: src/third_party/crashpad/crashpad/snapshot/cpu_context.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/cpu_context.cc -+++ src/third_party/crashpad/crashpad/snapshot/cpu_context.cc -@@ -226,10 +226,12 @@ bool CPUContext::Is64Bit() const { +diff --git a/snapshot/cpu_context.cc b/snapshot/cpu_context.cc +index 6eaa853..492a0f7 100644 +--- a/snapshot/cpu_context.cc ++++ b/snapshot/cpu_context.cc +@@ -20,6 +20,7 @@ + #include + + #include "base/notreached.h" ++#include "cpu_architecture.h" + #include "util/misc/arraysize.h" + #include "util/misc/implicit_cast.h" + +@@ -170,6 +171,8 @@ + return arm->pc; + case kCPUArchitectureARM64: + return arm64->pc; ++ case kCPUArchitectureRISCV64: ++ return riscv64->pc; + default: + NOTREACHED(); + return ~0ull; +@@ -186,6 +189,8 @@ + return arm->sp; + case kCPUArchitectureARM64: + return arm64->sp; ++ case kCPUArchitectureRISCV64: ++ return riscv64->regs[1]; + default: + NOTREACHED(); + return ~0ull; +@@ -226,6 +231,7 @@ case kCPUArchitectureX86_64: case kCPUArchitectureARM64: case kCPUArchitectureMIPS64EL: @@ -226,29 +466,19 @@ Index: src/third_party/crashpad/crashpad/snapshot/cpu_context.cc return true; case kCPUArchitectureX86: case kCPUArchitectureARM: - case kCPUArchitectureMIPSEL: -+ case kCPUArchitectureRISCV32: - return false; - default: - NOTREACHED(); -Index: src/third_party/crashpad/crashpad/snapshot/cpu_context.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/cpu_context.h -+++ src/third_party/crashpad/crashpad/snapshot/cpu_context.h -@@ -362,6 +362,20 @@ struct CPUContextMIPS64 { +diff --git a/snapshot/cpu_context.h b/snapshot/cpu_context.h +index 7bc252b..c3640c3 100644 +--- a/snapshot/cpu_context.h ++++ b/snapshot/cpu_context.h +@@ -362,6 +362,15 @@ uint64_t fir; }; -+//! \brief A context structure carrying RISCV32 CPU state. -+struct CPUContextRISCV32 { -+ uint32_t regs[32]; -+ uint64_t fpregs[32]; -+ uint32_t fcsr; -+}; -+ +//! \brief A context structure carrying RISCV64 CPU state. +struct CPUContextRISCV64 { -+ uint64_t regs[32]; ++ uint64_t pc; ++ uint64_t regs[31]; ++ + uint64_t fpregs[32]; + uint32_t fcsr; +}; @@ -256,521 +486,787 @@ Index: src/third_party/crashpad/crashpad/snapshot/cpu_context.h //! \brief A context structure capable of carrying the context of any supported //! CPU architecture. struct CPUContext { -@@ -402,6 +416,8 @@ struct CPUContext { +@@ -402,6 +411,7 @@ CPUContextARM64* arm64; CPUContextMIPS* mipsel; CPUContextMIPS64* mips64; -+ CPUContextRISCV32* riscv32; + CPUContextRISCV64* riscv64; }; }; -Index: src/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc -+++ src/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc -@@ -266,6 +266,30 @@ void InitializeCPUContextARM64_OnlyFPSIM +diff --git a/snapshot/elf/elf_image_reader.cc b/snapshot/elf/elf_image_reader.cc +index 30e8b98..dcab025 100644 +--- a/snapshot/elf/elf_image_reader.cc ++++ b/snapshot/elf/elf_image_reader.cc +@@ -733,8 +733,11 @@ + if (!dynamic_array_->GetValue(tag, log, address)) { + return false; + } +-#if BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_FUCHSIA) +- // The GNU loader updates the dynamic array according to the load bias. ++ ++#if BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_FUCHSIA) || \ ++ (defined(__GLIBC__) && defined(ARCH_CPU_RISCV64)) ++ // The GNU loader updates the dynamic array according to the load bias (except ++ // for RISC-V: https://sourceware.org/bugzilla/show_bug.cgi?id=24484). + // The Android and Fuchsia loaders only update the debug address. + if (tag != DT_DEBUG) { + *address += GetLoadBias(); +diff --git a/snapshot/linux/cpu_context_linux.cc b/snapshot/linux/cpu_context_linux.cc +index 21db234..6c4cb3e 100644 +--- a/snapshot/linux/cpu_context_linux.cc ++++ b/snapshot/linux/cpu_context_linux.cc +@@ -266,6 +266,21 @@ context->fpcr = float_context.fpcr; } -+#elif defined(ARCH_CPU_RISCV_FAMILY) ++#elif defined(ARCH_CPU_RISCV64) + -+template -+void InitializeCPUContextRISCV( -+ const typename Traits::SignalThreadContext& thread_context, -+ const typename Traits::SignalFloatContext& float_context, -+ typename Traits::CPUContext* context) { -+ static_assert(sizeof(context->regs) == sizeof(thread_context), -+ "registers size mismatch"); -+ static_assert(sizeof(context->fpregs) == sizeof(float_context.f), -+ "fp registers size mismatch"); -+ memcpy(&context->regs, &thread_context, sizeof(context->regs)); -+ memcpy(&context->fpregs, &float_context.f, sizeof(context->fpregs)); ++void InitializeCPUContextRISCV64(const ThreadContext::t64_t& thread_context, ++ const FloatContext::f64_t& float_context, ++ CPUContextRISCV64* context) { ++ context->pc = thread_context.pc; ++ ++ static_assert(sizeof(context->regs) == sizeof(thread_context.regs)); ++ memcpy(context->regs, thread_context.regs, sizeof(context->regs)); ++ ++ static_assert(sizeof(context->fpregs) == sizeof(float_context.fpregs)); ++ memcpy(context->fpregs, float_context.fpregs, sizeof(context->fpregs)); + context->fcsr = float_context.fcsr; +} -+template void InitializeCPUContextRISCV( -+ const ContextTraits32::SignalThreadContext& thread_context, -+ const ContextTraits32::SignalFloatContext& float_context, -+ ContextTraits32::CPUContext* context); -+template void InitializeCPUContextRISCV( -+ const ContextTraits64::SignalThreadContext& thread_context, -+ const ContextTraits64::SignalFloatContext& float_context, -+ ContextTraits64::CPUContext* context); + #endif // ARCH_CPU_X86_FAMILY } // namespace internal -Index: src/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h -+++ src/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h -@@ -174,6 +174,22 @@ void InitializeCPUContextMIPS( +diff --git a/snapshot/linux/cpu_context_linux.h b/snapshot/linux/cpu_context_linux.h +index 1ea5eec..507d1b4 100644 +--- a/snapshot/linux/cpu_context_linux.h ++++ b/snapshot/linux/cpu_context_linux.h +@@ -174,6 +174,20 @@ #endif // ARCH_CPU_MIPS_FAMILY || DOXYGEN -+#if defined(ARCH_CPU_RISCV_FAMILY) || DOXYGEN ++#if defined(ARCH_CPU_RISCV64) || DOXYGEN + -+//! \brief Initializes a CPUContextRISCV structure from native context ++//! \brief Initializes a CPUContextRISCV64 structure from native context +//! structures on Linux. +//! +//! \param[in] thread_context The native thread context. +//! \param[in] float_context The native float context. -+//! \param[out] context The CPUContextRISCV structure to initialize. -+template -+void InitializeCPUContextRISCV( -+ const typename Traits::SignalThreadContext& thread_context, -+ const typename Traits::SignalFloatContext& float_context, -+ typename Traits::CPUContext* context); ++//! \param[out] context The CPUContextRISCV64 structure to initialize. ++void InitializeCPUContextRISCV64(const ThreadContext::t64_t& thread_context, ++ const FloatContext::f64_t& float_context, ++ CPUContextRISCV64* context); + -+#endif // ARCH_CPU_RISCV_FAMILY || DOXYGEN ++#endif // ARCH_CPU_RISCV64 || DOXYGEN + } // namespace internal } // namespace crashpad -Index: src/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc -+++ src/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc -@@ -325,6 +325,61 @@ bool ExceptionSnapshotLinux::ReadContext +diff --git a/snapshot/linux/exception_snapshot_linux.cc b/snapshot/linux/exception_snapshot_linux.cc +index 4e6ec11..677afda 100644 +--- a/snapshot/linux/exception_snapshot_linux.cc ++++ b/snapshot/linux/exception_snapshot_linux.cc +@@ -325,6 +325,48 @@ reader, context_address, context_.mips64); } -+#elif defined(ARCH_CPU_RISCV_FAMILY) ++#elif defined(ARCH_CPU_RISCV64) + -+template +static bool ReadContext(ProcessReaderLinux* reader, + LinuxVMAddress context_address, -+ typename Traits::CPUContext* dest_context) { ++ typename ContextTraits64::CPUContext* dest_context) { + const ProcessMemory* memory = reader->Memory(); + + LinuxVMAddress gregs_address = context_address + -+ offsetof(UContext, mcontext) + -+ offsetof(typename Traits::MContext, gregs); ++ offsetof(UContext, mcontext) + ++ offsetof(MContext64, regs); + -+ typename Traits::SignalThreadContext thread_context; ++ typename ContextTraits64::SignalThreadContext thread_context; + if (!memory->Read(gregs_address, sizeof(thread_context), &thread_context)) { + LOG(ERROR) << "Couldn't read gregs"; + return false; + } + -+ LinuxVMAddress fpregs_address = context_address + -+ offsetof(UContext, mcontext) + -+ offsetof(typename Traits::MContext, fpregs); ++ LinuxVMAddress fpregs_address = ++ context_address + offsetof(UContext, mcontext) + ++ offsetof(MContext64, fpregs); + -+ typename Traits::SignalFloatContext fp_context; ++ typename ContextTraits64::SignalFloatContext fp_context; + if (!memory->Read(fpregs_address, sizeof(fp_context), &fp_context)) { + LOG(ERROR) << "Couldn't read fpregs"; + return false; + } + -+ InitializeCPUContextRISCV(thread_context, fp_context, dest_context); ++ InitializeCPUContextRISCV64(thread_context, fp_context, dest_context); + + return true; +} + +template <> -+bool ExceptionSnapshotLinux::ReadContext( -+ ProcessReaderLinux* reader, -+ LinuxVMAddress context_address) { -+ context_.architecture = kCPUArchitectureRISCV32; -+ context_.riscv32 = &context_union_.riscv32; -+ -+ return internal::ReadContext( -+ reader, context_address, context_.riscv32); -+} -+ -+template <> +bool ExceptionSnapshotLinux::ReadContext( + ProcessReaderLinux* reader, + LinuxVMAddress context_address) { + context_.architecture = kCPUArchitectureRISCV64; + context_.riscv64 = &context_union_.riscv64; + -+ return internal::ReadContext( -+ reader, context_address, context_.riscv64); ++ return internal::ReadContext(reader, context_address, context_.riscv64); +} + #endif // ARCH_CPU_X86_FAMILY bool ExceptionSnapshotLinux::Initialize( -Index: src/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h -+++ src/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h -@@ -89,6 +89,9 @@ class ExceptionSnapshotLinux final : pub +@@ -355,10 +397,12 @@ + return false; + } + } else { ++#if !defined(ARCH_CPU_RISCV64) + if (!ReadContext(process_reader, context_address) || + !ReadSiginfo(process_reader, siginfo_address)) { + return false; + } ++#endif + } + + CaptureMemoryDelegateLinux capture_memory_delegate( +diff --git a/snapshot/linux/exception_snapshot_linux.h b/snapshot/linux/exception_snapshot_linux.h +index 3ea3d93..f931d33 100644 +--- a/snapshot/linux/exception_snapshot_linux.h ++++ b/snapshot/linux/exception_snapshot_linux.h +@@ -89,6 +89,8 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) CPUContextMIPS mipsel; CPUContextMIPS64 mips64; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ CPUContextRISCV32 riscv32; ++#elif defined(ARCH_CPU_RISCV64) + CPUContextRISCV64 riscv64; #endif } context_union_; CPUContext context_; -Index: src/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc -+++ src/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc -@@ -127,6 +127,9 @@ void ProcessReaderLinux::Thread::Initial +diff --git a/snapshot/linux/exception_snapshot_linux_test.cc b/snapshot/linux/exception_snapshot_linux_test.cc +index 0f5e21a..94f45f1 100644 +--- a/snapshot/linux/exception_snapshot_linux_test.cc ++++ b/snapshot/linux/exception_snapshot_linux_test.cc +@@ -297,6 +297,34 @@ + #undef CPU_ARCH_NAME + } + ++#elif defined(ARCH_CPU_RISCV64) ++using NativeCPUContext = ucontext_t; ++ ++void InitializeContext(NativeCPUContext* context) { ++ for (size_t reg = 0; reg < std::size(context->uc_mcontext.__gregs); ++reg) { ++ context->uc_mcontext.__gregs[reg] = reg; ++ } ++ ++ memset(&context->uc_mcontext.__fpregs, ++ 44, ++ sizeof(context->uc_mcontext.__fpregs)); ++} ++ ++void ExpectContext(const CPUContext& actual, const NativeCPUContext& expected) { ++ EXPECT_EQ(actual.architecture, kCPUArchitectureRISCV64); ++ ++ EXPECT_EQ(actual.riscv64->pc, expected.uc_mcontext.__gregs[0]); ++ ++ for (size_t reg = 0; reg < std::size(actual.riscv64->regs); ++reg) { ++ EXPECT_EQ(actual.riscv64->regs[reg], expected.uc_mcontext.__gregs[reg + 1]); ++ } ++ ++ EXPECT_EQ(memcmp(&actual.riscv64->fpregs, ++ &expected.uc_mcontext.__fpregs, ++ sizeof(actual.riscv64->fpregs)), ++ 0); ++} ++ + #else + #error Port. + #endif +diff --git a/snapshot/linux/process_reader_linux.cc b/snapshot/linux/process_reader_linux.cc +index 8ec0edc..4571338 100644 +--- a/snapshot/linux/process_reader_linux.cc ++++ b/snapshot/linux/process_reader_linux.cc +@@ -127,6 +127,8 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.regs[29] : thread_info.thread_context.t32.regs[29]; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.sp -+ : thread_info.thread_context.t32.sp; ++#elif defined(ARCH_CPU_RISCV64) ++ stack_pointer = thread_info.thread_context.t64.regs[1]; #else #error Port. #endif -Index: src/third_party/crashpad/crashpad/snapshot/linux/signal_context.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/signal_context.h -+++ src/third_party/crashpad/crashpad/snapshot/linux/signal_context.h -@@ -422,6 +422,67 @@ static_assert(offsetof(UContext +struct UContext { + typename Traits::ULong flags; + typename Traits::Address link; + SignalStack stack; + Sigset sigmask; -+ char padding[128 - sizeof(sigmask)]; -+ typename Traits::Char_64Only padding2[8]; -+ typename Traits::MContext mcontext; ++ char alignment_padding_[8]; ++ char padding[128 - sizeof(Sigset)]; ++ MContext64 mcontext; +}; + -+#if defined(ARCH_CPU_RISCV32) -+static_assert(offsetof(UContext, mcontext) == -+ offsetof(ucontext_t, uc_mcontext), -+ "context offset mismatch"); -+static_assert(offsetof(UContext, mcontext.gregs) == -+ offsetof(ucontext_t, uc_mcontext.__gregs), -+ "context offset mismatch"); -+static_assert(offsetof(UContext, mcontext.fpregs) == -+ offsetof(ucontext_t, uc_mcontext.__fpregs), -+ "context offset mismatch"); -+#elif defined(ARCH_CPU_RISCV64) +static_assert(offsetof(UContext, mcontext) == + offsetof(ucontext_t, uc_mcontext), + "context offset mismatch"); -+static_assert(offsetof(UContext, mcontext.gregs) == ++static_assert(offsetof(UContext, mcontext.regs) == + offsetof(ucontext_t, uc_mcontext.__gregs), + "context offset mismatch"); +static_assert(offsetof(UContext, mcontext.fpregs) == + offsetof(ucontext_t, uc_mcontext.__fpregs), + "context offset mismatch"); -+#endif + #else #error Port. #endif // ARCH_CPU_X86_FAMILY -Index: src/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc -+++ src/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc -@@ -205,6 +205,9 @@ CPUArchitecture SystemSnapshotLinux::Get +diff --git a/snapshot/linux/system_snapshot_linux.cc b/snapshot/linux/system_snapshot_linux.cc +index 8487155..20b95fb 100644 +--- a/snapshot/linux/system_snapshot_linux.cc ++++ b/snapshot/linux/system_snapshot_linux.cc +@@ -205,6 +205,8 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) return process_reader_->Is64Bit() ? kCPUArchitectureMIPS64EL : kCPUArchitectureMIPSEL; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ return process_reader_->Is64Bit() ? kCPUArchitectureRISCV64 -+ : kCPUArchitectureRISCV32; ++#elif defined(ARCH_CPU_RISCV64) ++ return kCPUArchitectureRISCV64; #else #error port to your architecture #endif -@@ -220,6 +223,9 @@ uint32_t SystemSnapshotLinux::CPURevisio +@@ -220,6 +222,9 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) // Not implementable on MIPS return 0; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ // Not implementable on RISCV ++#elif defined(ARCH_CPU_RISCV64) ++ // Not implemented + return 0; #else #error port to your architecture #endif -@@ -240,6 +246,9 @@ std::string SystemSnapshotLinux::CPUVend +@@ -240,6 +245,9 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) // Not implementable on MIPS return std::string(); -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ // Not implementable on RISCV ++#elif defined(ARCH_CPU_RISCV64) ++ // Not implemented + return std::string(); #else #error port to your architecture #endif -@@ -373,6 +382,9 @@ bool SystemSnapshotLinux::NXEnabled() co +@@ -373,6 +381,9 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) // Not implementable on MIPS return false; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ // Not implementable on RISCV ++#elif defined(ARCH_CPU_RISCV64) ++ // Not implemented + return false; #else #error Port. #endif // ARCH_CPU_X86_FAMILY -Index: src/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc -+++ src/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc -@@ -190,6 +190,22 @@ bool ThreadSnapshotLinux::Initialize( +diff --git a/snapshot/linux/test_modules.cc b/snapshot/linux/test_modules.cc +index 7d9d08d..c03cbaa 100644 +--- a/snapshot/linux/test_modules.cc ++++ b/snapshot/linux/test_modules.cc +@@ -110,6 +110,13 @@ + module.ehdr.e_machine = EM_AARCH64; + #elif defined(ARCH_CPU_MIPSEL) || defined(ARCH_CPU_MIPS64EL) + module.ehdr.e_machine = EM_MIPS; ++#elif defined(ARCH_CPU_RISCV64) ++ module.ehdr.e_machine = EM_RISCV; ++#endif ++ ++#if defined(ARCH_CPU_RISCV64) ++ // Crashpad supports RV64GC ++ module.ehdr.e_flags = EF_RISCV_RVC | EF_RISCV_FLOAT_ABI_DOUBLE; + #endif + + module.ehdr.e_version = EV_CURRENT; +diff --git a/snapshot/linux/thread_snapshot_linux.cc b/snapshot/linux/thread_snapshot_linux.cc +index ba33401..85882e8 100644 +--- a/snapshot/linux/thread_snapshot_linux.cc ++++ b/snapshot/linux/thread_snapshot_linux.cc +@@ -190,6 +190,12 @@ thread.thread_info.float_context.f32, context_.mipsel); } -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ if (process_reader->Is64Bit()) { -+ context_.architecture = kCPUArchitectureRISCV64; -+ context_.riscv64 = &context_union_.riscv64; -+ InitializeCPUContextRISCV( -+ thread.thread_info.thread_context.t64, -+ thread.thread_info.float_context.f64, -+ context_.riscv64); -+ } else { -+ context_.architecture = kCPUArchitectureRISCV32; -+ context_.riscv32 = &context_union_.riscv32; -+ InitializeCPUContextRISCV( -+ thread.thread_info.thread_context.t32, -+ thread.thread_info.float_context.f32, -+ context_.riscv32); -+ } ++#elif defined(ARCH_CPU_RISCV64) ++ context_.architecture = kCPUArchitectureRISCV64; ++ context_.riscv64 = &context_union_.riscv64; ++ InitializeCPUContextRISCV64(thread.thread_info.thread_context.t64, ++ thread.thread_info.float_context.f64, ++ context_.riscv64); #else #error Port. #endif -Index: src/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h -+++ src/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h -@@ -74,6 +74,9 @@ class ThreadSnapshotLinux final : public +diff --git a/snapshot/linux/thread_snapshot_linux.h b/snapshot/linux/thread_snapshot_linux.h +index bd03f58..5795bfb 100644 +--- a/snapshot/linux/thread_snapshot_linux.h ++++ b/snapshot/linux/thread_snapshot_linux.h +@@ -74,6 +74,8 @@ #elif defined(ARCH_CPU_MIPS_FAMILY) CPUContextMIPS mipsel; CPUContextMIPS64 mips64; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ CPUContextRISCV32 riscv32; ++#elif defined(ARCH_CPU_RISCV64) + CPUContextRISCV64 riscv64; #else #error Port. #endif // ARCH_CPU_X86_FAMILY -Index: src/third_party/crashpad/crashpad/util/linux/ptracer.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/util/linux/ptracer.cc -+++ src/third_party/crashpad/crashpad/util/linux/ptracer.cc -@@ -398,6 +398,51 @@ bool GetThreadArea64(pid_t tid, - return true; +diff --git a/snapshot/minidump/minidump_context_converter.cc b/snapshot/minidump/minidump_context_converter.cc +index f2fa2ab..ec02dff 100644 +--- a/snapshot/minidump/minidump_context_converter.cc ++++ b/snapshot/minidump/minidump_context_converter.cc +@@ -266,6 +266,33 @@ + context_.mips64->fir = src->fir; + + memcpy(&context_.mips64->fpregs, &src->fpregs, sizeof(src->fpregs)); ++ } else if (context_.architecture == ++ CPUArchitecture::kCPUArchitectureRISCV64) { ++ context_memory_.resize(sizeof(CPUContextRISCV64)); ++ context_.riscv64 = ++ reinterpret_cast(context_memory_.data()); ++ const MinidumpContextRISCV64* src = ++ reinterpret_cast( ++ minidump_context.data()); ++ if (minidump_context.size() < sizeof(MinidumpContextRISCV64)) { ++ return false; ++ } ++ ++ if (!(src->context_flags & kMinidumpContextRISCV64)) { ++ return false; ++ } ++ ++ context_.riscv64->pc = src->pc; ++ ++ static_assert(sizeof(context_.riscv64->regs) == sizeof(src->regs), ++ "GPR size mismatch"); ++ memcpy(&context_.riscv64->regs, &src->regs, sizeof(src->regs)); ++ ++ static_assert(sizeof(context_.riscv64->fpregs) == sizeof(src->fpregs), ++ "FPR size mismatch"); ++ memcpy(&context_.riscv64->fpregs, &src->fpregs, sizeof(src->fpregs)); ++ ++ context_.riscv64->fcsr = src->fcsr; + } else { + // Architecture is listed as "unknown". + DLOG(ERROR) << "Unknown architecture"; +diff --git a/snapshot/minidump/system_snapshot_minidump.cc b/snapshot/minidump/system_snapshot_minidump.cc +index abccda3..58bd7b3 100644 +--- a/snapshot/minidump/system_snapshot_minidump.cc ++++ b/snapshot/minidump/system_snapshot_minidump.cc +@@ -68,6 +68,8 @@ + case kMinidumpCPUArchitectureMIPS: + return kCPUArchitectureMIPSEL; + // No word on how MIPS64 is signalled ++ case kMinidumpCPUArchitectureRISCV64Breakpad: ++ return kCPUArchitectureRISCV64; + + default: + return CPUArchitecture::kCPUArchitectureUnknown; +diff --git a/snapshot/test/test_cpu_context.cc b/snapshot/test/test_cpu_context.cc +index 7efbf5a..9982294 100644 +--- a/snapshot/test/test_cpu_context.cc ++++ b/snapshot/test/test_cpu_context.cc +@@ -295,5 +295,27 @@ + mips64->dsp_control = value++; } -+#elif defined(ARCH_CPU_RISCV_FAMILY) ++void InitializeCPUContextRISCV64(CPUContext* context, uint32_t seed) { ++ context->architecture = kCPUArchitectureRISCV64; ++ CPUContextRISCV64* riscv64 = context->riscv64; + -+template -+bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) { -+ iovec iov; -+ iov.iov_base = dest; -+ iov.iov_len = sizeof(*dest); -+ if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast(set), &iov) != 0) { -+ PLOG_IF(ERROR, can_log) << "ptrace"; -+ return false; ++ if (seed == 0) { ++ memset(riscv64, 0, sizeof(*riscv64)); ++ return; + } -+ if (iov.iov_len != sizeof(*dest)) { -+ LOG_IF(ERROR, can_log) << "Unexpected registers size"; -+ return false; ++ ++ uint32_t value = seed; ++ ++ riscv64->pc = value++; ++ for (size_t index = 0; index < std::size(riscv64->regs); ++index) { ++ riscv64->regs[index] = value++; + } -+ return true; -+} + -+bool GetFloatingPointRegisters32(pid_t tid, -+ FloatContext* context, -+ bool can_log) { -+ return false; ++ for (size_t index = 0; index < std::size(riscv64->fpregs); ++index) { ++ riscv64->fpregs[index] = value++; ++ } ++ riscv64->fcsr = value++; +} ++ + } // namespace test + } // namespace crashpad +diff --git a/snapshot/test/test_cpu_context.h b/snapshot/test/test_cpu_context.h +index e4372ce..053dec2 100644 +--- a/snapshot/test/test_cpu_context.h ++++ b/snapshot/test/test_cpu_context.h +@@ -63,6 +63,7 @@ + void InitializeCPUContextARM64(CPUContext* context, uint32_t seed); + void InitializeCPUContextMIPS(CPUContext* context, uint32_t seed); + void InitializeCPUContextMIPS64(CPUContext* context, uint32_t seed); ++void InitializeCPUContextRISCV64(CPUContext* context, uint32_t seed); + //! \} + + } // namespace test +diff --git a/test/linux/get_tls.cc b/test/linux/get_tls.cc +index c8147f0..405976e 100644 +--- a/test/linux/get_tls.cc ++++ b/test/linux/get_tls.cc +@@ -49,6 +49,8 @@ + : "=r"(tls) + : + : "$3"); ++#elif defined(ARCH_CPU_RISCV64) ++ asm("mv %0, tp" : "=r"(tls)); + #else + #error Port. + #endif // ARCH_CPU_ARMEL +diff --git a/util/linux/auxiliary_vector_test.cc b/util/linux/auxiliary_vector_test.cc +index 0455497..0c97781 100644 +--- a/util/linux/auxiliary_vector_test.cc ++++ b/util/linux/auxiliary_vector_test.cc +@@ -96,10 +96,15 @@ + + ProcessMemoryLinux memory(&connection); + ++// AT_PLATFORM is null for RISC-V: ++// https://elixir.bootlin.com/linux/v6.4-rc4/C/ident/ELF_PLATFORM ++#if !defined(ARCH_CPU_RISCV64) + LinuxVMAddress platform_addr; + ASSERT_TRUE(aux.GetValue(AT_PLATFORM, &platform_addr)); + std::string platform; + ASSERT_TRUE(memory.ReadCStringSizeLimited(platform_addr, 10, &platform)); ++#endif // ARCH_CPU_RISCV64 ++ + #if defined(ARCH_CPU_X86) + EXPECT_STREQ(platform.c_str(), "i686"); + #elif defined(ARCH_CPU_X86_64) +diff --git a/util/linux/ptracer.cc b/util/linux/ptracer.cc +index 25c89ea..d8129ad 100644 +--- a/util/linux/ptracer.cc ++++ b/util/linux/ptracer.cc +@@ -398,6 +398,37 @@ + return true; + } + ++#elif defined(ARCH_CPU_RISCV64) + +bool GetFloatingPointRegisters64(pid_t tid, + FloatContext* context, + bool can_log) { -+ return GetRegisterSet(tid, NT_PRFPREG, &context->f64.f, can_log); -+} -+ -+bool GetThreadArea32(pid_t tid, -+ const ThreadContext& context, -+ LinuxVMAddress* address, -+ bool can_log) { -+ return false; ++ iovec iov; ++ iov.iov_base = context; ++ iov.iov_len = sizeof(*context); ++ if (ptrace( ++ PTRACE_GETREGSET, tid, reinterpret_cast(NT_PRFPREG), &iov) != ++ 0) { ++ PLOG_IF(ERROR, can_log) << "ptrace"; ++ return false; ++ } ++ if (iov.iov_len != sizeof(context->f64)) { ++ LOG_IF(ERROR, can_log) << "Unexpected registers size " << iov.iov_len ++ << " != " << sizeof(context->f64); ++ return false; ++ } ++ return true; +} + +bool GetThreadArea64(pid_t tid, + const ThreadContext& context, + LinuxVMAddress* address, + bool can_log) { -+ *address = context.t64.tp; ++ // Thread pointer register ++ *address = context.t64.regs[3]; + return true; +} + #else #error Port. #endif // ARCH_CPU_X86_FAMILY -Index: src/third_party/crashpad/crashpad/util/linux/thread_info.h -=================================================================== ---- src.orig/third_party/crashpad/crashpad/util/linux/thread_info.h -+++ src/third_party/crashpad/crashpad/util/linux/thread_info.h -@@ -79,6 +79,40 @@ union ThreadContext { +@@ -426,6 +457,7 @@ + return iov.iov_len; + } + ++#if !defined(ARCH_CPU_RISCV64) + bool GetGeneralPurposeRegisters32(pid_t tid, + ThreadContext* context, + bool can_log) { +@@ -437,6 +469,7 @@ + } + return true; + } ++#endif + + bool GetGeneralPurposeRegisters64(pid_t tid, + ThreadContext* context, +@@ -500,12 +533,16 @@ + can_log_); + } + ++#if !defined(ARCH_CPU_RISCV64) + return GetGeneralPurposeRegisters32(tid, &info->thread_context, can_log_) && + GetFloatingPointRegisters32(tid, &info->float_context, can_log_) && + GetThreadArea32(tid, + info->thread_context, + &info->thread_specific_data_address, + can_log_); ++#else ++ return false; ++#endif + } + + ssize_t Ptracer::ReadUpTo(pid_t pid, +diff --git a/util/linux/thread_info.h b/util/linux/thread_info.h +index 9f60bd3..808b35a 100644 +--- a/util/linux/thread_info.h ++++ b/util/linux/thread_info.h +@@ -29,6 +29,11 @@ + #include + #endif + ++// x86_64 has compilation errors if asm/ptrace.h is #included. ++#if defined(ARCH_CPU_RISCV64) ++#include ++#endif ++ + namespace crashpad { + + //! \brief The set of general purpose registers for an architecture family. +@@ -80,6 +85,8 @@ uint32_t cp0_status; uint32_t cp0_cause; uint32_t padding1_; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ // Reflects user_regs_struct in asm/ptrace.h. -+ uint32_t pc; -+ uint32_t ra; -+ uint32_t sp; -+ uint32_t gp; -+ uint32_t tp; -+ uint32_t t0; -+ uint32_t t1; -+ uint32_t t2; -+ uint32_t s0; -+ uint32_t s1; -+ uint32_t a0; -+ uint32_t a1; -+ uint32_t a2; -+ uint32_t a3; -+ uint32_t a4; -+ uint32_t a5; -+ uint32_t a6; -+ uint32_t a7; -+ uint32_t s2; -+ uint32_t s3; -+ uint32_t s4; -+ uint32_t s5; -+ uint32_t s6; -+ uint32_t s7; -+ uint32_t s8; -+ uint32_t s9; -+ uint32_t s10; -+ uint32_t s11; -+ uint32_t t3; -+ uint32_t t4; -+ uint32_t t5; -+ uint32_t t6; ++#elif defined(ARCH_CPU_RISCV64) ++ // 32 bit RISC-V not supported #else #error Port. #endif // ARCH_CPU_X86_FAMILY -@@ -132,6 +166,40 @@ union ThreadContext { +@@ -133,12 +140,17 @@ uint64_t cp0_badvaddr; uint64_t cp0_status; uint64_t cp0_cause; -+#elif defined(ARCH_CPU_RISCV_FAMILY) ++#elif defined(ARCH_CPU_RISCV64) + // Reflects user_regs_struct in asm/ptrace.h. + uint64_t pc; -+ uint64_t ra; -+ uint64_t sp; -+ uint64_t gp; -+ uint64_t tp; -+ uint64_t t0; -+ uint64_t t1; -+ uint64_t t2; -+ uint64_t s0; -+ uint64_t s1; -+ uint64_t a0; -+ uint64_t a1; -+ uint64_t a2; -+ uint64_t a3; -+ uint64_t a4; -+ uint64_t a5; -+ uint64_t a6; -+ uint64_t a7; -+ uint64_t s2; -+ uint64_t s3; -+ uint64_t s4; -+ uint64_t s5; -+ uint64_t s6; -+ uint64_t s7; -+ uint64_t s8; -+ uint64_t s9; -+ uint64_t s10; -+ uint64_t s11; -+ uint64_t t3; -+ uint64_t t4; -+ uint64_t t5; -+ uint64_t t6; ++ uint64_t regs[31]; #else #error Port. #endif // ARCH_CPU_X86_FAMILY -@@ -143,11 +211,12 @@ union ThreadContext { + } t64; + +-#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM64) ++#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM64) || \ ++ defined(ARCH_CPU_RISCV64) + using NativeThreadContext = user_regs_struct; + #elif defined(ARCH_CPU_ARMEL) using NativeThreadContext = user_regs; - #elif defined(ARCH_CPU_MIPS_FAMILY) +@@ -146,7 +158,7 @@ // No appropriate NativeThreadsContext type available for MIPS -+#elif defined(ARCH_CPU_RISCV_FAMILY) #else #error Port. - #endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64 +-#endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64 ++#endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64 || ARCH_CPU_RISCV64 --#if !defined(ARCH_CPU_MIPS_FAMILY) -+#if !defined(ARCH_CPU_MIPS_FAMILY) && !defined(ARCH_CPU_RISCV_FAMILY) + #if !defined(ARCH_CPU_MIPS_FAMILY) #if defined(ARCH_CPU_32_BITS) - static_assert(sizeof(t32_t) == sizeof(NativeThreadContext), "Size mismatch"); - #else // ARCH_CPU_64_BITS -@@ -218,6 +287,9 @@ union FloatContext { +@@ -219,6 +231,8 @@ } fpregs[32]; uint32_t fpcsr; uint32_t fpu_id; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ uint64_t f[32]; -+ uint32_t fcsr; ++#elif defined(ARCH_CPU_RISCV64) ++ // 32 bit RISC-V not supported #else #error Port. #endif // ARCH_CPU_X86_FAMILY -@@ -252,6 +324,9 @@ union FloatContext { +@@ -253,6 +267,10 @@ double fpregs[32]; uint32_t fpcsr; uint32_t fpu_id; -+#elif defined(ARCH_CPU_RISCV_FAMILY) -+ uint64_t f[32]; -+ uint32_t fcsr; ++#elif defined(ARCH_CPU_RISCV64) ++ // Reflects __riscv_d_ext_state in asm/ptrace.h ++ uint64_t fpregs[32]; ++ uint64_t fcsr; #else #error Port. #endif // ARCH_CPU_X86_FAMILY -@@ -281,6 +356,7 @@ union FloatContext { +@@ -282,6 +300,8 @@ static_assert(sizeof(f64) == sizeof(user_fpsimd_struct), "Size mismatch"); #elif defined(ARCH_CPU_MIPS_FAMILY) // No appropriate floating point context native type for available MIPS. -+#elif defined(ARCH_CPU_RISCV_FAMILY) ++#elif defined(ARCH_CPU_RISCV64) ++ static_assert(sizeof(f64) == sizeof(__riscv_d_ext_state), "Size mismatch"); #else #error Port. #endif // ARCH_CPU_X86 -Index: src/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc -=================================================================== ---- src.orig/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc -+++ src/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc -@@ -237,6 +237,8 @@ std::string UserAgent() { +diff --git a/util/misc/capture_context.h b/util/misc/capture_context.h +index a5503d6..e838dba 100644 +--- a/util/misc/capture_context.h ++++ b/util/misc/capture_context.h +@@ -69,6 +69,7 @@ + //! macOS/Linux/Fuchsia | x86_64 | `%%rdi` + //! Linux | ARM/ARM64 | `r0`/`x0` + //! Linux | MIPS/MIPS64 | `$a0` ++//! Linux | RISCV64 | `a0` + //! + //! Additionally, the value `LR` on ARM/ARM64 will be the return address of + //! this function. +diff --git a/util/misc/capture_context_linux.S b/util/misc/capture_context_linux.S +index 9c3a726..cfad857 100644 +--- a/util/misc/capture_context_linux.S ++++ b/util/misc/capture_context_linux.S +@@ -36,6 +36,8 @@ + .type CAPTURECONTEXT_SYMBOL2, %function + #elif defined(__mips__) + .balign 4, 0x0 ++#elif defined(__riscv) ++ .balign 4, 0x0 + #endif + + CAPTURECONTEXT_SYMBOL: +@@ -427,4 +429,85 @@ + jr $ra + + .set at ++ ++#elif defined(__riscv) ++ ++ #define MCONTEXT_GREGS_OFFSET 176 ++ ++ // x1/ra is the return address. Store it as the pc. ++ // The original x10/a0 can't be recovered. ++ sd x1, (0 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x1, (1 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x2, (2 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x3, (3 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x4, (4 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x5, (5 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x6, (6 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x7, (7 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x8, (8 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x9, (9 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x10, (10 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x11, (11 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x12, (12 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x13, (13 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x14, (14 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x15, (15 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x16, (16 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x17, (17 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x18, (18 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x19, (19 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x20, (20 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x21, (21 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x22, (22 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x23, (23 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x24, (24 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x25, (25 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x26, (26 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x27, (27 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x28, (28 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x29, (29 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x30, (30 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ sd x31, (31 * 8 + MCONTEXT_GREGS_OFFSET)(a0) ++ ++ #define MCONTEXT_FPREGS_OFFSET MCONTEXT_GREGS_OFFSET + 32*8 ++ ++ // Use x31/t6 as scratch register. ++ frcsr x31 ++ sw x31, (32 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ ++ fsd f0, (0 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f1, (1 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f2, (2 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f3, (3 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f4, (4 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f5, (5 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f6, (6 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f7, (7 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f8, (8 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f9, (9 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f10, (10 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f11, (11 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f12, (12 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f13, (13 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f14, (14 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f15, (15 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f16, (16 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f17, (17 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f18, (18 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f19, (19 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f20, (20 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f21, (21 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f22, (22 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f23, (23 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f24, (24 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f25, (25 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f26, (26 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f27, (27 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f28, (28 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f29, (29 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f30, (30 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ fsd f31, (31 * 8 + MCONTEXT_FPREGS_OFFSET)(a0) ++ ++ ret ++ + #endif // __i386__ +diff --git a/util/misc/capture_context_test_util_linux.cc b/util/misc/capture_context_test_util_linux.cc +index 35751bf..55820b9 100644 +--- a/util/misc/capture_context_test_util_linux.cc ++++ b/util/misc/capture_context_test_util_linux.cc +@@ -35,6 +35,9 @@ + EXPECT_EQ(context.uc_mcontext.regs[0], FromPointerCast(&context)); + #elif defined(ARCH_CPU_MIPS_FAMILY) + EXPECT_EQ(context.uc_mcontext.gregs[4], FromPointerCast(&context)); ++#elif defined(ARCH_CPU_RISCV64) ++ EXPECT_EQ(context.uc_mcontext.__gregs[10], ++ FromPointerCast(&context)); + #endif + } + +@@ -49,6 +52,8 @@ + return context.uc_mcontext.pc; + #elif defined(ARCH_CPU_MIPS_FAMILY) + return context.uc_mcontext.pc; ++#elif defined(ARCH_CPU_RISCV64) ++ return context.uc_mcontext.__gregs[0]; + #endif + } + +@@ -63,6 +68,8 @@ + return context.uc_mcontext.sp; + #elif defined(ARCH_CPU_MIPS_FAMILY) + return context.uc_mcontext.gregs[29]; ++#elif defined(ARCH_CPU_RISCV64) ++ return context.uc_mcontext.__gregs[2]; + #endif + } + +diff --git a/util/net/http_transport_libcurl.cc b/util/net/http_transport_libcurl.cc +index d5c9177..df63a77 100644 +--- a/util/net/http_transport_libcurl.cc ++++ b/util/net/http_transport_libcurl.cc +@@ -237,6 +237,8 @@ #elif defined(ARCH_CPU_BIG_ENDIAN) static constexpr char arch[] = "aarch64_be"; #endif -+#elif defined(ARCH_CPU_RISCV64) ++#elif defined (ARCH_CPU_RISCV64) + static constexpr char arch[] = "riscv64"; #else #error Port diff --git a/electron22/electron22-support-riscv64-in-electron_runtime_api_delegate.cc.patch b/electron22/electron22-support-riscv64-in-electron_runtime_api_delegate.cc.patch new file mode 100644 index 000000000..989f5a960 --- /dev/null +++ b/electron22/electron22-support-riscv64-in-electron_runtime_api_delegate.cc.patch @@ -0,0 +1,20 @@ +--- electron/shell/browser/extensions/api/runtime/electron_runtime_api_delegate.cc.orig 2023-07-11 06:59:25.878690844 -0400 ++++ electron/shell/browser/extensions/api/runtime/electron_runtime_api_delegate.cc 2023-07-11 07:47:22.725853930 -0400 +@@ -66,6 +66,8 @@ + info->arch = extensions::api::runtime::PLATFORM_ARCH_X86_32; + } else if (strcmp(arch, "x64") == 0) { + info->arch = extensions::api::runtime::PLATFORM_ARCH_X86_64; ++ } else if (strcmp(arch, "riscv64") == 0) { ++ info->arch = extensions::api::runtime::PLATFORM_ARCH_RISCV64; + } else { + NOTREACHED(); + return false; +@@ -81,6 +83,8 @@ + info->nacl_arch = extensions::api::runtime::PLATFORM_NACL_ARCH_X86_32; + } else if (strcmp(nacl_arch, "x86-64") == 0) { + info->nacl_arch = extensions::api::runtime::PLATFORM_NACL_ARCH_X86_64; ++ } else if (strcmp(nacl_arch, "riscv64") == 0) { ++ info->nacl_arch = extensions::api::runtime::PLATFORM_NACL_ARCH_RISCV64; + } else { + NOTREACHED(); + return false; diff --git a/electron22/partition-alloc-forward-add-cstdint.patch b/electron22/partition-alloc-forward-add-cstdint.patch new file mode 100644 index 000000000..da019d5f2 --- /dev/null +++ b/electron22/partition-alloc-forward-add-cstdint.patch @@ -0,0 +1,12 @@ +diff --git a/base/allocator/partition_allocator/partition_alloc_forward.h b/base/allocator/partition_allocator/partition_alloc_forward.h +index fd62e11e3e38e..5d6e614a56ba6 100644 +--- a/base/allocator/partition_allocator/partition_alloc_forward.h ++++ b/base/allocator/partition_allocator/partition_alloc_forward.h +@@ -7,6 +7,7 @@ + + #include + #include ++#include + + #include "base/allocator/partition_allocator/partition_alloc_base/compiler_specific.h" + #include "base/allocator/partition_allocator/partition_alloc_base/component_export.h" diff --git a/electron22/riscv64.patch b/electron22/riscv64.patch index e3af4830b..7ab2f6edf 100644 --- a/electron22/riscv64.patch +++ b/electron22/riscv64.patch @@ -1,75 +1,97 @@ --- PKGBUILD +++ PKGBUILD -@@ -34,7 +34,8 @@ depends=('c-ares' 'gtk3' 'libevent' 'nss' 'wayland') +@@ -13,7 +13,9 @@ _gcc_patchset=2 + # shellcheck disable=SC2034 + pkgrel=1 + ++_build_profile=Release + _major_ver=${pkgver%%.*} ++_electron="electron$_major_ver" + if [[ ${_use_suffix} != 0 ]]; then + pkgname="electron${_major_ver}" + else +@@ -34,7 +36,8 @@ depends=('c-ares' 'gtk3' 'libevent' 'nss' 'wayland') makedepends=('clang' 'git' 'gn' 'gperf' 'harfbuzz-icu' 'http-parser' 'qt5-base' 'java-runtime-headless' 'libnotify' 'lld' 'llvm' 'ninja' 'npm' 'pciutils' 'pipewire' 'python' 'python-httplib2' - 'python-pyparsing' 'python-six' 'wget' 'yarn' 'patchutils') + 'python-pyparsing' 'python-six' 'wget' 'yarn' 'patchutils' -+ 'esbuild' 'go' 'p7zip' 'bazel' 'jdk11-openjdk' 'llvm' 'llvm-libs') ++ 'go' 'p7zip' 'bazel' 'jdk11-openjdk' 'llvm') # shellcheck disable=SC2034 optdepends=('kde-cli-tools: file deletion support (kioclient5)' 'libappindicator-gtk3: StatusNotifierItem support' -@@ -87,6 +88,15 @@ source=("git+https://github.com/electron/electron.git#tag=v$pkgver" +@@ -87,6 +90,19 @@ source=("git+https://github.com/electron/electron.git#tag=v$pkgver" 'REVERT-roll-src-third_party-ffmpeg-m102.patch' 'REVERT-roll-src-third_party-ffmpeg-m106.patch' 'angle-wayland-include-protocol.patch' -+ "$pkgname-riscv-angle.patch" -+ "$pkgname-riscv-sandbox.patch" -+ "$pkgname-riscv-crashpad.patch" -+ "$pkgname-riscv-dav1d.patch" -+ "$pkgname-swiftshader-use-system-llvm.patch" -+ "$pkgname-swiftshader-LLVMJIT-AddressSanitizerPass-dead-code-remove.patch" -+ "$pkgname-gclient-ignore-prebuilt-platform-specific-deps.patch" -+ "$pkgname-grab-commit.py" ++ "partition-alloc-forward-add-cstdint.patch" ++ "$_electron-relax-constraints-on-VirtualCursor-layout.patch" ++ "$_electron-support-riscv64-in-electron_runtime_api_delegate.cc.patch" ++ "$_electron-extensions-common-api-runtime.json-support-riscv64.patch" ++ "$_electron-riscv-angle.patch" ++ "$_electron-riscv-sandbox.patch" ++ "$_electron-riscv-crashpad.patch" ++ "$_electron-riscv-dav1d.patch" ++ "$_electron-swiftshader-use-system-llvm.patch" ++ "$_electron-swiftshader-LLVMJIT-AddressSanitizerPass-dead-code-remove.patch" ++ "$_electron-gclient-ignore-prebuilt-platform-specific-deps.patch" ++ "$_electron-deps-parser.py" + "git+https://chromium.googlesource.com/infra/infra" ) # shellcheck disable=SC2034 sha256sums=('SKIP' -@@ -124,7 +134,16 @@ sha256sums=('SKIP' +@@ -124,7 +140,20 @@ sha256sums=('SKIP' 'bfafedebd915e1824562329a3afc8589401342eff87dba53c78502b869023b7e' '30df59a9e2d95dcb720357ec4a83d9be51e59cc5551365da4c0073e68ccdec44' '4c12d31d020799d31355faa7d1fe2a5a807f7458e7f0c374adf55edb37032152' - 'cd0d9d2a1d6a522d47c3c0891dabe4ad72eabbebc0fe5642b9e22efa3d5ee572') + 'cd0d9d2a1d6a522d47c3c0891dabe4ad72eabbebc0fe5642b9e22efa3d5ee572' ++ '772a25129d6770e4d03e7a9cc86e2bde3da5486762a88a655100d9d1518f3ed9' ++ '41eac75fca36730a13f8c368c8153a0db64ee80e11e97868fdbf0adf1d87d136' ++ 'b2bee22e96fceb794bfe16a670251959ee9ca7c87ed5048c9eb6cebd6e3b4bc3' ++ '840947515347933da383408711696150cf8020b35d7abe1265b87084dfe1f3df' + 'a191ef5190e5f823e6be078df53ed1a888558673040985d79347a26644c39b63' + '378ab9fd608cf6a9b2f3631798001a836997f13bcd296940afb538448e0f8b9d' -+ 'cf233d17326e0aa59bd395971478df9982059b18d237068c3906e4716903d533' ++ '85644fd6b1a64e7cf76f690f1427010cdf773938987f7e1a93b2977873707a4f' + '32811636eecd187dd386bbdd0fa1216728d6010f96fae8f1714dded04a95a5f4' + 'd901e905a9b4303e6334bf39475bcbcdf22959796954de66507857108d53570f' + 'cf80c0d70f8933a4495c71d7be681c1457a69d26e95d2ad41da4bb02b7cbee4c' + 'b28b64181c46549e94e8c26d5401b0036991c18c60040c444a262484addd0d0d' -+ '13c47f8e085ba44739760b94dd0170a6ec5bd7e32645ba2f9e1467079dfe612e' ++ 'cb8c2d8d620f95053e5de17b2234099b56c8ae6fa5868a38dbb0dbaf322e19a5' + 'SKIP') # Possible replacements are listed in build/linux/unbundle/replace_gn_files.py # Keys are the names in the above script; values are the dependencies in Arch -@@ -188,11 +207,32 @@ EOF +@@ -188,11 +217,36 @@ EOF echo "Linking chromium from sources..." ln -s chromium-mirror src + echo "Building build tools that doesn't have prebuilt binaries for riscv64..." -+ export GOBIN=/build/bin -+ export PATH="$PATH:/build/bin" -+ ++ export GOBIN="$HOME/bin" ++ export PATH="$PATH:$HOME/bin" ++ + # Install the build tools -+ local infra_rev=$(python "$pkgname-grab-commit.py" infra chromium-mirror/DEPS) ++ local infra_rev=$(python "$_electron-deps-parser.py" infra src/DEPS) + git -C infra checkout "$infra_rev" -+ local luci_go_rev=$(python "$pkgname-grab-commit.py" luci_go infra/DEPS) -+ go install "go.chromium.org/luci/swarming/cmd/...@$luci_go_rev" -+ go install "go.chromium.org/luci/client/cmd/...@$luci_go_rev" -+ go install "go.chromium.org/luci/cipd/client/cmd/...@$luci_go_rev" ++ local luci_go_rev=$(python "$_electron-deps-parser.py" luci_go infra/DEPS) ++ go install "go.chromium.org/luci/swarming/cmd/...@$luci_go_rev" # not sure if it really get used ++ go install "go.chromium.org/luci/client/cmd/...@$luci_go_rev" # not sure if it really get used ++ go install "go.chromium.org/luci/cipd/client/cmd/...@$luci_go_rev" # usage confirmed + + # Fix .cipd-bin problem + mkdir depot_tools/.cipd_bin + GOBIN=$(realpath depot_tools/.cipd_bin) go install "go.chromium.org/luci/auth/client/cmd/...@$luci_go_rev" + -+ patch -Np0 -i $pkgname-gclient-ignore-prebuilt-platform-specific-deps.patch ++ patch -Np0 -i $_electron-gclient-ignore-prebuilt-platform-specific-deps.patch depot_tools/gclient.py sync -D \ --nohooks \ --with_branch_heads \ --with_tags ++ # Install esbuild (version needs to be locked, not feasible to add it to make dependencies) ++ local esbuild_ver=$(python "$_electron-deps-parser.py" esbuild src/DEPS) ++ GOBIN=$(realpath src/third_party/devtools-frontend/src/third_party/esbuild/) go install "github.com/evanw/esbuild/cmd/esbuild@v$esbuild_ver" ++ + # Replace the bundled x86_64 JDK with system JDK11 + rm -rf src/third_party/jdk/current + ln -s /usr/lib/jvm/java-11-openjdk src/third_party/jdk/current @@ -77,19 +99,79 @@ ( cd src/electron || exit patch -Np1 -i ../../std-vector-non-const.patch -@@ -254,6 +294,15 @@ EOF +@@ -248,11 +302,24 @@ EOF + filterdiff -p1 -x include/GLSLANG/ShaderLang.h < ../5d1ac2e0d5f61913aad62dadb65a7fea6f1b93ae.patch | patch -Np1 -d third_party/angle + patch -Np1 <../dawn-tint-add-cstdint.patch -d third_party/dawn + patch -Np1 -i ../comp-viz-add-cstdint.patch ++ patch -Np1 -i ../partition-alloc-forward-add-cstdint.patch # Perhaps only for testing build + + # Upstream fixes + patch -Np1 -i ../re-fix-TFLite-build-error-on-linux-with-system-zlib.patch patch -Np1 -i ../chromium-icu72.patch patch -Np1 -d v8 <../v8-enhance-Date-parser-to-take-Unicode-SPACE.patch - ++ patch -Np1 -i ../$_electron-relax-constraints-on-VirtualCursor-layout.patch ++ + # RISC-V Patches -+ patch -Np1 -i ../$pkgname-riscv-angle.patch -+ patch -Np1 -i ../$pkgname-riscv-sandbox.patch -+ patch -Np1 -i ../$pkgname-riscv-crashpad.patch -+ patch -Np1 -i ../$pkgname-riscv-dav1d.patch ++ patch -Np1 -d third_party/crashpad/crashpad < "${srcdir}/$_electron-riscv-crashpad.patch" ++ patch -Np1 -i ../$_electron-riscv-angle.patch ++ patch -Np1 -i ../$_electron-riscv-sandbox.patch ++ patch -Np1 -i ../$_electron-riscv-dav1d.patch ++ patch -Np0 -i ../$_electron-support-riscv64-in-electron_runtime_api_delegate.cc.patch ++ patch -Np0 -i ../$_electron-extensions-common-api-runtime.json-support-riscv64.patch + # Build failes with the bundled LLVM 10. -+ patch -Np1 -i ../$pkgname-swiftshader-use-system-llvm.patch -+ patch -Np1 -i ../$pkgname-swiftshader-LLVMJIT-AddressSanitizerPass-dead-code-remove.patch -+ ++ patch -Np1 -i ../$_electron-swiftshader-use-system-llvm.patch ++ patch -Np1 -i ../$_electron-swiftshader-LLVMJIT-AddressSanitizerPass-dead-code-remove.patch + # Revert ffmpeg roll requiring new channel layout API support # https://crbug.com/1325301 - patch -Rp1 -i ../REVERT-roll-src-third_party-ffmpeg-m102.patch +@@ -302,14 +369,15 @@ build() { + export CXX=clang++ + export AR=ar + export NM=nm ++ unset LDFLAGS + + # https://github.com/webpack/webpack/issues/14532 + export NODE_OPTIONS=--openssl-legacy-provider + + # Facilitate deterministic builds (taken from build/config/compiler/BUILD.gn) +- CFLAGS+=' -Wno-builtin-macro-redefined' +- CXXFLAGS+=' -Wno-builtin-macro-redefined' +- CPPFLAGS+=' -D__DATE__= -D__TIME__= -D__TIMESTAMP__=' ++ export CFLAGS=' -Wno-builtin-macro-redefined' ++ export CXXFLAGS=' -Wno-builtin-macro-redefined' ++ export CPPFLAGS=' -D__DATE__= -D__TIME__= -D__TIMESTAMP__=' + + # Let Chromium set its own symbol level + CFLAGS=${CFLAGS/-g } +@@ -340,7 +408,6 @@ build() { + host_toolchain = "//build/toolchain/linux/unbundle:default" + clang_base_path = "/usr" + clang_use_chrome_plugins = false +- symbol_level = 0 # sufficient for backtraces on x86(_64) + chrome_pgo_phase = 0 + treat_warnings_as_errors = false + disable_fieldtrial_testing_config = true +@@ -355,17 +422,18 @@ build() { + use_system_wayland_scanner = true + icu_use_data_file = false + is_component_ffmpeg = false ++ symbol_level = 1 + ' +- gn gen out/Release \ +- --args="import(\"//electron/build/args/release.gn\") ${GN_EXTRA_ARGS}" +- ninja -C out/Release electron +- ninja -C out/Release electron_dist_zip ++ gn gen out/$_build_profile \ ++ --args="import(\"//electron/build/args/${_build_profile,,}.gn\") ${GN_EXTRA_ARGS}" ++ ninja -C out/$_build_profile electron ++ ninja -C out/$_build_profile electron_dist_zip + # ninja -C out/Release third_party/electron_node:headers + } + + package() { + install -dm755 "${pkgdir:?}/usr/lib/${pkgname}" +- bsdtar -xf src/out/Release/dist.zip -C "${pkgdir}/usr/lib/${pkgname}" ++ bsdtar -xf src/out/$_build_profile/dist.zip -C "${pkgdir}/usr/lib/${pkgname}" + + chmod u+s "${pkgdir}/usr/lib/${pkgname}/chrome-sandbox" +