someting wrong happend in vitis 2019.2 when i try to use the build-vitis.bat to programe build-vitis.tcl

[liweizheng-name]

hello sir,I have done the vivado project in vivado 2019.2,and export hardware.but when i try to creat the vitis project ,sonething wrong happed ,The window console is garbled

[liweizheng-name]

[liweizheng-name]

[fpgadeveloper]

Hi, Your images are not showing. Please try copying and pasting the text from the console, rather than sending me an image. Please also let me know your setup (Windows 10, Ubuntu, etc).

[liweizheng-name]

Thank you, Sir. I am using Win10 system. I have built the hardware project and generated the.xsa file.
When I want to use the build-vitis.bat to programe build-vitis.tcl, the Win10 terminal shows the following:

Building the local Vitis repo from original sources
Copying files from D:/vivado2019.2/Vitis/2019.2/data/embeddedsw/ThirdParty/sw_services/lwip211_v1_0 to ../EmbeddedSw/ThirdParty/sw_services/lwip211_v1_09
Copying files from D:/vivado2019.2/Vitis/2019.2/data/embeddedsw/ThirdParty/sw_services/lwip211_v1_1 to ../EmbeddedSw/ThirdParty/sw_services/lwip211_v1_19
Copying files from D:/vivado2019.2/Vitis/2019.2/data/embeddedsw/lib/sw_apps/zynqmp_fsbl to ../EmbeddedSw/lib/sw_apps/zynqmp_fsbl
Creating the Vitis workspace
There were 1 exported project(s) found in the ../Vivado directory.
Creating Vitis workspace.
Adding Vitis repo to the workspace.
Starting vitis.bat. This could take few seconds...done
INFO: [Hsi 55-2053] elapsed time for repository (D:/vivado2019.2/Vitis/2019.2/data\embeddedsw) loading 0 seconds
Creating Platform for zcu104_qgige.
Opening the hardware design, this may take few seconds.
㩄瘯癩摡㉯㄰⸹⼲楖楴⽳〲㤱㈮术畮洯捩潲汢穡⽥瑮

40 minutes after the Win10 terminal displayed this message, I shut down the Win10 terminal (time is 10:00:50) because it did not respond, and then I found that the Vitis project was not fully generated,and the IDE.log shows:

09:20:30 INFO : Registering command handlers for Vitis TCF services
09:20:30 INFO : Successfully done query RDI_DATADIR
09:20:30 INFO : Adding 'E:/360XZ/ethernet-fmc-zynq-gem-master/EmbeddedSw/lib' as a new local repository.
09:20:30 INFO : Adding 'E:/360XZ/ethernet-fmc-zynq-gem-master/EmbeddedSw' as a new local repository.
10:00:50 ERROR : xsct server communication channel has closed unexpectedly.
java.net.SocketException: Connection reset
at java.base/java.net.SocketInputStream.read(Unknown Source)
at java.base/java.net.SocketInputStream.read(Unknown Source)
at java.base/java.io.BufferedInputStream.read1(Unknown Source)
at java.base/java.io.BufferedInputStream.read(Unknown Source)
at java.base/java.io.FilterInputStream.read(Unknown Source)
at org.eclipse.tcf.core.ChannelTCP.get(ChannelTCP.java:186)
at org.eclipse.tcf.core.StreamChannel.read(StreamChannel.java:85)
at org.eclipse.tcf.core.AbstractChannel$1.run(AbstractChannel.java:329)

[liweizheng-name]

I changed vivado2018.2 to generate the project ,sdk project generated success.The environment configuration is ZCU104 and FMC sub-card (including four network ports), the network cable is connected to the computer and the network port on the sub-card.I set the computer's IP to 192.168.1.11 and found that the ping command between the computer and the board failed, indicating that the target host cannot be accessed.Thank you for your answer.
The fellowing is the output of sdk uart:

-----lwIP TCP echo server ------

TCP packets sent to port 6001 will be echoed back

Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
autonegotiation complete
link speed for phy address 0: 1000
DHCP Timeout
Configuring default IP of 192.168.1.10
Board IP: 192.168.1.10

Netmask : 255.255.255.0

Gateway : 192.168.1.1

TCP echo server started @ port 7

[fpgadeveloper]

Did you apply the patch to Vitis 2019.2 as described here?
https://github.com/fpgadeveloper/ethernet-fmc-zynq-gem/tree/master/Vitis
https://www.xilinx.com/support/answers/73252.html

[liweizheng-name]

Thank you very much for your reply. I did not install the patch of Vitis2019.2. I will try it next time.
I follow the README. File, and the configuration is basically according to the documentation, but the above problem still occurs: I print the basic information, but the ping does not work. I find the link speed for PHY address: 0:100, 0 means that the PHY chip address is not recognized.
Is this the problem?

[fpgadeveloper]

Please try the 2019.2 release and let me know if you have the same problem.

[1126447820]

hello，I had the same problem, ping failed！

[liweizheng-name]

I have installed the patch of Vitis2019.2,but still failed to genetate the vitis project.

[fpgadeveloper]

Do you have the same error message? Or a different one this time?

[liweizheng-name]

yes，the same error like before

[fpgadeveloper]

This seems to be an error with the Vitis tools. Please contact Xilinx for support.