Testing on some designs from Opencores

[Chopper455]

Used msys2 32bit in Windows 7 to integrate everything together.
I've compiled ghdl 81905a8c.
Then used ghdl-yosys-plugin 0b687cd.
In-compiled it directly into the yosys 334ec5fa.
fails.zip
I hope this will help you to make this piece of work even better:)

Used several designs from opencores.org, to check if they really can be synthesized used Quartus Prime Lite Edition 16.1.
Some designs where ghdl falls with "GHDL Bug occurred" weren't checked in Quartus.

https://opencores.org/projects/8b10b_encdec
Command:
ghdl ./8b10_enc.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "enc_8b10b"

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-755-g81905a8c-dirty) [Dunoon edition]
Compiled with unknown compiler version
Target: i686-w64-mingw32
C:\Programs\FreeEDA\ghdl_git!fails\8b10b_encdec
Command line:
C:\Programs\FreeEDA\yosys-master\yosys_bin\bin\yosys.exe
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : netlists-memories.adb:2578

---

ERROR: vhdl import failed.

https://opencores.org/projects/802154phycore
In Quartus used "ieee_802_15_4_phy" top-module, but in ghdl used a lower level module.
Command:
ghdl -fsynopsys -fexplicit ./chip_gen.vhd ./upsampler.vhd ./tx_fir.vhd ./tx_core.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "tx_core"
   ./chip_gen.vhd:65:62: unhandled predefined IEEE operator "rol"
   ../../src/ieee/v93/numeric_std.vhdl:645:12: declared here
   ./chip_gen.vhd:66:62: unhandled predefined IEEE operator "rol"
   ../../src/ieee/v93/numeric_std.vhdl:645:12: declared here
   ./tx_fir.vhd:82:47: unhandled (static) function: IIR_PREDEFINED_IEEE_NUMERIC_STD_RESIZE_SGN_NAT

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-755-g81905a8c-dirty) [Dunoon edition]
Compiled with unknown compiler version
Target: i686-w64-mingw32
C:\Programs\FreeEDA\ghdl_git!fails\802154phycore
Command line:
C:\Programs\FreeEDA\yosys-master\yosys_bin\bin\yosys.exe
Exception CONSTRAINT_ERROR raised
Exception information:
raised CONSTRAINT_ERROR : synth-expr.adb:793 access check failed

---

ERROR: vhdl import failed.

https://opencores.org/projects/avs_aes
Quartus compiled fine the AES_CORE top-module.
Command:
ghdl --work=avs_aes_lib ./addroundkey.vhd ./aes_core.vhd ./aes_fsm_decrypt.vhd ./aes_fsm_encrypt.vhd ./avs_aes.vhd ./avs_aes_pkg.vhd ./keyexpansionV2.vhd ./memory_word.vhd ./mixcol.vhd ./mixcol_fwd.vhd ./mixcol_inv.vhd ./mux3.vhd ./sbox.vhd ./sbox_arch1.vhd ./shiftrow.vhd ./shiftrow_fwd.vhd ./shiftrow_inv.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "avs_aes"
   ./aes_core.vhd:122:24:warning: instance "multiplex" of component "mux2" is not bound [-Wbinding]
   ./aes_core.vhd:75:14:warning: (in default configuration of aes_core(arch1))
   ./aes_core.vhd:133:16:warning: instance "keyindexmux" of component "mux2" is not bound [-Wbinding]
   ./aes_core.vhd:75:14:warning: (in default configuration of aes_core(arch1))
   ./keyexpansionV2.vhd:160:24:warning: instance "loadmux" of component "mux2" is not bound [-Wbinding]
   ./keyexpansionV2.vhd:89:14:warning: (in default configuration of keyexpansionv2(ach1))
   ./keyexpansionV2.vhd:181:24:warning: instance "lastw_loadmux" of component "mux2" is not bound [-Wbinding]
   ./keyexpansionV2.vhd:89:14:warning: (in default configuration of keyexpansionv2(ach1))
   ./keyexpansionV2.vhd:272:16:warning: instance "nk8_sboxmux" of component "mux2" is not bound [-Wbinding]
   ./keyexpansionV2.vhd:89:14:warning: (in default configuration of keyexpansionv2(ach1))
   ./keyexpansionV2.vhd:323:8:warning: instance "mux_wi_1" of component "mux2" is not bound [-Wbinding]
   ./keyexpansionV2.vhd:89:14:warning: (in default configuration of keyexpansionv2(ach1))
   ./keyexpansionV2.vhd:339:16:warning: instance "nk8_mux_wi_1" of component "mux2" is not bound [-Wbinding]
   ./keyexpansionV2.vhd:89:14:warning: (in default configuration of keyexpansionv2(ach1))
   ./aes_core.vhd:300:24:warning: instance "mux" of component "mux2" is not bound [-Wbinding]
   ./aes_core.vhd:75:14:warning: (in default configuration of aes_core(arch1))
   ./aes_core.vhd:332:24:warning: instance "mux" of component "mux2" is not bound [-Wbinding]
   ./aes_core.vhd:75:14:warning: (in default configuration of aes_core(arch1))
   ./keyexpansionV2.vhd:102:15:note: found RAM "keymem", width: 128 bits, depth: 16
   ./keyexpansionV2.vhd:445:68:note: found ROM "n651", width: 8 bits, depth: 8
   ./sbox_arch1.vhd:129:15:note: found ROM "sboxrom", width: 8 bits, depth: 256
   ./sbox_arch1.vhd:129:15:note: found ROM "sboxrom", width: 8 bits, depth: 256
   Importing module avs_AES.
   ERROR: wire not found for $posedge
   ERROR: Assert `GetSize(ports) >= it.second->port_id' failed in kernel/rtlil.cc:1432.

https://opencores.org/projects/cordic
Command:
ghdl -fsynopsys ./r2p_pre.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "r2p_pre"
   ./r2p_pre.vhd:46:55: unhandled predefined IEEE operator "abs"
   ../../src/synopsys/std_logic_arith.vhdl:82:14: declared here
   ../../src/synopsys/std_logic_arith.vhdl:1215:21: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_SUB_INT_SGN_SGN
   ./r2p_pre.vhd:49:55: unhandled predefined IEEE operator "abs"
   ../../src/synopsys/std_logic_arith.vhdl:82:14: declared here
   ../../src/synopsys/std_logic_arith.vhdl:1215:21: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_SUB_INT_SGN_SGN
   ./r2p_pre.vhd:61:26: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_GT_UNS_UNS
   ./r2p_pre.vhd:36:27:warning: signal "swap" is never assigned and has no default value
   ERROR: vhdl import failed.

Command:
ghdl -fsynopsys ./r2p_post.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "r2p_post"
   ./r2p_post.vhd:51:60: unhandled call to ieee function "conv_signed"

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-755-g81905a8c-dirty) [Dunoon edition]
Compiled with unknown compiler version
Target: i686-w64-mingw32
C:\Programs\FreeEDA\ghdl_git!fails\cordic
Command line:
C:\Programs\FreeEDA\yosys-master\yosys_bin\bin\yosys.exe
Exception CONSTRAINT_ERROR raised
Exception information:
raised CONSTRAINT_ERROR : synth-context.adb:378 discriminant check failed

---

ERROR: vhdl import failed.

https://opencores.org/projects/fft_fir_filter
Command:
ghdl -fsynopsys ./alfft_core_slip.vhd -e
Result:

1. Executing GHDL.
   ./alfft_core_slip.vhd:328:23: entity name expected, found component "control"

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-755-g81905a8c-dirty) [Dunoon edition]
Compiled with unknown compiler version
Target: i686-w64-mingw32
C:\Programs\FreeEDA\ghdl_git!fails\fft_fir_filter
Command line:
C:\Programs\FreeEDA\yosys-master\yosys_bin\bin\yosys.exe
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : vhdl-utils.adb:1424

---

ERROR: vhdl import failed.

https://opencores.org/projects/fpu_double
Command:
ghdl -fsynopsys -fexplicit ./fpupack.vhd ./fpu_sub.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "fpu_sub"
   ./fpu_sub.vhd:194:40: unhandled call to ieee function "shr"
   ./fpu_sub.vhd:214:42: unhandled call to ieee function "shl"
   ./fpu_sub.vhd:217:42: unhandled call to ieee function "shl"
   ./fpu_sub.vhd:226:48: unhandled call to ieee function "shr"
   ERROR: vhdl import failed.

https://opencores.org/projects/hilbert_transformer
Command:
ghdl -fsynopsys ./fsf_comb_filter.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "fsf_comb_filter"
   ./fsf_comb_filter.vhd:74:31: unhandled call to ieee function "conv_integer"
   ./fsf_comb_filter.vhd:66:8:warning: signal "yc" is never assigned and has no default value
   ERROR: vhdl import failed.

https://opencores.org/projects/i2c_master_slave
Command:
ghdl -fsynopsys ./i2c_core_v02.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "i2c_core_v02"
   ./i2c_core_v02.vhd:137:46: unhandled call to ieee function "to_x01"
   ./i2c_core_v02.vhd:149:61: unhandled call to ieee function "to_x01"
   ./i2c_core_v02.vhd:150:61: unhandled call to ieee function "to_x01"
   ./i2c_core_v02.vhd:45:6:warning: no assignment for port "slv_int"
   ERROR: vhdl import failed.

https://opencores.org/projects/iicmb
Command:
ghdl ./iicmb_int_pkg.vhd ./mbit.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "mbit"
   ./mbit.vhd:253:29:note: found ROM "n83", width: 256 bits, depth: 1

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-755-g81905a8c-dirty) [Dunoon edition]
Compiled with unknown compiler version
Target: i686-w64-mingw32
C:\Programs\FreeEDA\ghdl_git!fails\iicmb
Command line:
C:\Programs\FreeEDA\yosys-master\yosys_bin\bin\yosys.exe
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : netlists-memories.adb:331

---

ERROR: vhdl import failed.

https://opencores.org/projects/neo430
Command:
ghdl --work=neo430 ./neo430_package.vhd ./neo430_timer.vhd -e
Result:

1. Executing GHDL.
   ./neo430_timer.vhd:115:16: choice must be locally static expression
   ./neo430_timer.vhd:117:16: choice must be locally static expression
   ./neo430_timer.vhd:154:16: choice must be locally static expression
   ./neo430_timer.vhd:161:16: choice must be locally static expression
   note: top entity is "neo430_timer"
   ERROR: vhdl import failed.

https://opencores.org/projects/plasma
Command:
ghdl -fsynopsys -fexplicit ./mlite_pack.vhd ./ram.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "ram"
   ./ram.vhd:99:7:warning: instance "lpm_ram_io_component0" of component "lpm_ram_dq" is not bound [-Wbinding]
   ./ram.vhd:33:14:warning: (in default configuration of ram(logic))
   ./ram.vhd:117:7:warning: instance "lpm_ram_io_component1" of component "lpm_ram_dq" is not bound [-Wbinding]
   ./ram.vhd:33:14:warning: (in default configuration of ram(logic))
   ./ram.vhd:135:7:warning: instance "lpm_ram_io_component2" of component "lpm_ram_dq" is not bound [-Wbinding]
   ./ram.vhd:33:14:warning: (in default configuration of ram(logic))
   ./ram.vhd:153:7:warning: instance "lpm_ram_io_component3" of component "lpm_ram_dq" is not bound [-Wbinding]
   ./ram.vhd:33:14:warning: (in default configuration of ram(logic))
   ./ram.vhd:47:30: limits of range are not constant

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-755-g81905a8c-dirty) [Dunoon edition]
Compiled with unknown compiler version
Target: i686-w64-mingw32
C:\Programs\FreeEDA\ghdl_git!fails\plasma
Command line:
C:\Programs\FreeEDA\yosys-master\yosys_bin\bin\yosys.exe
Exception TYPES.INTERNAL_ERROR raised
Exception information:
raised TYPES.INTERNAL_ERROR : synth-expr.adb:448

---

ERROR: vhdl import failed.

https://opencores.org/projects/cpu6502_true_cycle
Command:
ghdl -fsynopsys ./fsm_execution_unit.vhd -e
Result:

1. Executing GHDL.
   note: top entity is "fsm_execution_unit"
   ./fsm_execution_unit.vhd:3089:87: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_ADD_UNS_INT_SLV
   ./fsm_execution_unit.vhd:3271:87: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_ADD_UNS_INT_SLV
   ./fsm_execution_unit.vhd:3326:87: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_ADD_UNS_INT_SLV
   ERROR: vhdl import failed.

https://opencores.org/projects/usb11_phy_translation
Command:
ghdl -fsynopsys -fexplicit ./usb_tx_phy.vhdl -e
Result:

1. Executing GHDL.
   note: top entity is "usb_tx_phy"
   ./usb_tx_phy.vhdl:379:38: synth_dyadic_operation: unhandled IIR_PREDEFINED_IEEE_STD_LOGIC_ARITH_ADD_UNS_INT_SLV
   ERROR: vhdl import failed.

https://opencores.org/projects/viterbi_decoder_axi4s
Quartus sythesized with "dec_viterbi" as a top-module, maybe I just set library name incorrectly.
Command:
ghdl -fsynopsys --work=dec_viterbi ./acs.vhd ./axi4s_buffer.vhd ./branch_distance.vhd ./dec_viterbi.vhd ./generic_sp_ram.vhd ./pkg_components.vhd ./pkg_helper.vhd ./pkg_param.vhd ./pkg_param_derived.vhd ./pkg_trellis.vhd ./pkg_types.vhd ./ram_ctrl.vhd ./recursion.vhd ./reorder.vhd ./traceback.vhd -e
Result:

1. Executing GHDL.
   ./dec_viterbi.vhd:29:8: identifier "dec_viterbi" already used for a declaration
   libraries:1:1: previous declaration: library "dec_viterbi"
   ./dec_viterbi.vhd:29:8: identifier "dec_viterbi" already used for a declaration
   libraries:1:1: previous declaration: library "dec_viterbi"
   ./dec_viterbi.vhd:321:33: component name expected, found if generate statement
   note: top entity is "dec_viterbi"
   ERROR: vhdl import failed.

renamed the entity, tried again
Command:
ghdl -fsynopsys --work=dec_viterbi ./acs.vhd ./axi4s_buffer.vhd ./branch_distance.vhd ./dec_viterbi_rename.vhd ./generic_sp_ram.vhd ./pkg_components.vhd ./pkg_helper.vhd ./pkg_param.vhd ./pkg_param_derived.vhd ./pkg_trellis.vhd ./pkg_types.vhd ./ram_ctrl.vhd ./recursion.vhd ./reorder.vhd ./traceback.vhd -e
Result:

1. Executing GHDL.
   ./dec_viterbi_rename.vhd:321:33: component name expected, found if generate statement
   note: top entity is "dec_viterbi_rename"
   ERROR: vhdl import failed.

[eine]

In-compiled it directly into the yosys 334ec5fa.

Does this mean that you tried https://github.com/ghdl/ghdl-yosys-plugin#build-as-part-of-yosys-not-recommended instead of https://github.com/ghdl/ghdl-yosys-plugin#build-as-a-module-shared-library?

[tgingold]

I will first fix the missing features, but:

• I am not sure what to do with the invalid vhdl.
• I think it is better to create one issue per project as it is easier to track progress and status.

[Chopper455]

yes, i've tried #build-as-part-of-yosys-not-recommended because i couldn't compile it as module because of missing yosys symbols during linking, it was easier for me just to integrate it in yosys to make symbols visible.
In the future i'll create separate issues, thank you.

[Chopper455]

i'm not in a VHDL camp so i'm not familiar with lexical/syntax rules in standard, i consulted Quartus to verify them for me.