Lower function invocations to Verilog module instantiations #646
joachimschmidt557
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This wouldn't be too hard to implement. We already have the IR nodes and construct for module instantiation (they are not used at the moment). Codegen would have to walk the call graph and emit all the dependent modules first. To prevent inlining of the call sites, one could disable inlining entirely or add an attribute at the on functions DSLX level (and reflected in the IR) which disables inlining. Currently we don't do any global (cross-function) optimizations so not inlining functions could potentially have some qor ramifications. |
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Hi! I was wondering whether it would be possible to lower DSLX function invocations to module instantiations in the codegen pass. A small example:
Converted to XLS IR, this produces
Currently, when the
invoke
IR instruction is encountered bycodegen_main
, an error message is emitted. Would it be possible to convert thatinvoke
instruction into a Verilog module instantiation and thus "preserve the function/module hierarchy"? Like this:Beta Was this translation helpful? Give feedback.
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