Skip to content

Commit 5449327

Browse files
committedMar 11, 2025
Merge tag 'samsung-clk-fixes-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-fixes
Pull Samsung clk driver fixes from Krzysztof Kozlowski: - Google GS101: Fix synchronous external abort during system suspend. The driver access registers not available for OS, although issue would not be visible in earlier kernels due to missing suspend support. - Tesla FSD: Correct PLL142XX lock time * tag 'samsung-clk-fixes-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: update PLL locktime for PLL142XX used on FSD platform clk: samsung: gs101: fix synchronous external abort in samsung_clk_save()
2 parents b8501fe + 53517a7 commit 5449327

File tree

2 files changed

+6
-9
lines changed

2 files changed

+6
-9
lines changed
 

‎drivers/clk/samsung/clk-gs101.c

-8
Original file line numberDiff line numberDiff line change
@@ -382,17 +382,9 @@ static const unsigned long cmu_top_clk_regs[] __initconst = {
382382
EARLY_WAKEUP_DPU_DEST,
383383
EARLY_WAKEUP_CSIS_DEST,
384384
EARLY_WAKEUP_SW_TRIG_APM,
385-
EARLY_WAKEUP_SW_TRIG_APM_SET,
386-
EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
387385
EARLY_WAKEUP_SW_TRIG_CLUSTER0,
388-
EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
389-
EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
390386
EARLY_WAKEUP_SW_TRIG_DPU,
391-
EARLY_WAKEUP_SW_TRIG_DPU_SET,
392-
EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
393387
EARLY_WAKEUP_SW_TRIG_CSIS,
394-
EARLY_WAKEUP_SW_TRIG_CSIS_SET,
395-
EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
396388
CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
397389
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
398390
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,

‎drivers/clk/samsung/clk-pll.c

+6-1
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
206206
*/
207207
/* Maximum lock time can be 270 * PDIV cycles */
208208
#define PLL35XX_LOCK_FACTOR (270)
209+
#define PLL142XX_LOCK_FACTOR (150)
209210

210211
#define PLL35XX_MDIV_MASK (0x3FF)
211212
#define PLL35XX_PDIV_MASK (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
272273
}
273274

274275
/* Set PLL lock time. */
275-
writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
276+
if (pll->type == pll_142xx)
277+
writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
278+
pll->lock_reg);
279+
else
280+
writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
276281
pll->lock_reg);
277282

278283
/* Change PLL PMS values */

0 commit comments

Comments
 (0)
Please sign in to comment.