Update README.md

Author: gupta409

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 # Processor-UVM-Verification
 System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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+# Documentation:
+Please refer to the project report [here](https://github.com/gupta409/Processor-UVM-Verification/blob/5327a338f16e9e19dc1a45fefaef597633526cbc/Documentation/Report.pdf)
+
+# Contributions:
+Contibuted by [@rpjayaraman](https://github.com/rpjayaraman): The project can be access live on EDA Playground [here](https://www.edaplayground.com/x/aevr)