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Anish
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‎Code/Makefile.vcs

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include $(UVM_HOME)/Makefile.vcs
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UVM_VERBOSITY = UVM_HIGH
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DUT_DIR = ./Processor
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TEST_DIR = .
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TEST_NAME = processor_test
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SEED = 14788478
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DUT_SOURCES = \
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+incdir+$(DUT_DIR) $(DUT_DIR)/Main_Processor.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/Adder.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/adder_internal.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/ALU.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/black_box.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/comp.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/Control_Unit.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/data_mem.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/full_adder.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/grey_box.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/halfadder.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/Hazard_ControlUnit.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/inst_mem.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/mux2_1_1bit.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/mux4_1_16bit.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/reg_file.v \
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+incdir+$(DUT_DIR) $(DUT_DIR)/wallace_8bit.v
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DUT_TEST = \
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+incdir+$(DUT_DIR) $(DUT_DIR)/stg_final.v
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TEST_SOURCES = \
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+incdir+$(TEST_DIR) $(TEST_DIR)/top.sv \
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+incdir+$(TEST_DIR) $(TEST_DIR)/processor_interface.sv
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all: comp runnurg
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comp:
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$(VCS) -cm line+cond+fsm -Mupdate +v2k -sverilog -timescale=1ps/1ps $(DUT_SOURCES) $(TEST_SOURCES) -l compile.log +vcs+dupvars+verilog.vpd -debug_all
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run:
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$(SIMV) -cm line+cond+fsm +ntb_random_seed=$(SEED) +UVM_TESTNAME=$(TEST_NAME)
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runnurg: run
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urg -dir simv.vdb
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runncheck: run
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$(CHECK)
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‎Code/Processor/ALU.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:48:12 02/12/2015
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// Design Name:
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// Module Name: ALU
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ALU(
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input [15:0]a,
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input [15:0]b,
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input [1:0]alu_sel, //use of alu_sel
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input [1:0]s, // 4 bits
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input sel,
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input [1:0]mul,
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output [15:0]y,
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output cout
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);
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wire [15:0]ar1,ar2,l1,l2,l3,l4,l5,l6,l7,l8,sh1,sh2,sh3,w1,w2,mul1;
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wire k_mov=alu_sel[1]&~alu_sel[0]&~s[1]&s[0]; //For move;
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//Arithmetic
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assign ar1=((~({16{s[0]}}))&b)|((({16{s[0]}})^({16{s[1]}}))&~b)&({16{~k_mov}});
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Adder a1(a,ar1,(s[0]&(~k_mov)),ar2,cout);
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//Logical
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assign l1=a&b;
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assign l2=a|b;
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assign l3=a^b;
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assign l4=a;
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mux2_1_1bit m1[15:0](l1,l2,s[0],l5);
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mux2_1_1bit m2[15:0](l3,l4,s[0],l6);
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mux2_1_1bit m3[15:0](l5,l6,s[1],l7);
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assign l8=l7^({16{sel}});
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//Mulitplication
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wire[7:0] wmul1,wmul2,wmul11,wmul22;
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mux2_1_1bit mmul1[7:0](a[7:0],a[15:8],~mul[0],wmul1);
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mux2_1_1bit mmul2[7:0](b[7:0],b[15:8],~mul[0],wmul2);
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mux2_1_1bit mmul3[7:0]({8{1'b0}},wmul1,mul[0]|mul[1],wmul11);
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mux2_1_1bit mmul4[7:0]({8{1'b0}},wmul2,mul[0]|mul[1],wmul22);
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wallace_8bit m4(wmul11,wmul22,mul1);
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//Shifter
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assign sh1=a<<b;
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assign sh2=a>>b;
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mux2_1_1bit m5[15:0](sh1,sh2,sel,sh3);
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//Final Mux_logic
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mux2_1_1bit m6[15:0](ar2,l8,alu_sel[0],w1);
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mux2_1_1bit m7[15:0](mul1,sh3,alu_sel[0],w2);
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mux2_1_1bit m8[15:0](w1,w2,alu_sel[1]&(~k_mov),y);
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endmodule

‎Code/Processor/Adder.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:
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// Design Name:
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// Module Name: Adder
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Adder(
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input [15:0] a,
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input [15:0] b,
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input cin,
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output [15:0] s,
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output cout
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);
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wire [15:0]g,p,GG;
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//Bitwise Generate And Propogate Signals.
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assign g=a&b;
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assign p=a^b;
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//Group Generate And Propogate Signals.
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assign GG[0]=g[0]|(p[0]&cin);
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black_box b1(g[15],p[15],g[14],p[14],g1,p1);
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black_box b2(g[14],p[14],g[13],p[13],g2,p2);
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black_box b3(g[13],p[13],g[12],p[12],g3,p3);
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black_box b4(g[12],p[12],g[11],p[11],g4,p4);
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black_box b5(g[11],p[11],g[10],p[10],g5,p5);
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black_box b6(g[10],p[10],g[9],p[9],g6,p6);
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black_box b7(g[9],p[9],g[8],p[8],g7,p7);
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black_box b8(g[8],p[8],g[7],p[7],g8,p8);
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black_box b9(g[7],p[7],g[6],p[6],g9,p9);
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black_box b10(g[6],p[6],g[5],p[5],g10,p10);
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black_box b11(g[5],p[5],g[4],p[4],g11,p11);
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black_box b12(g[4],p[4],g[3],p[3],g12,p12);
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black_box b13(g[3],p[3],g[2],p[2],g13,p13);
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black_box b14(g[2],p[2],g[1],p[1],g14,p14);
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gray_box gb1(g[1],p[1],GG[0],GG[1]);
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black_box b15(g1,p1,g3,p3,g15,p15);
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black_box b16(g2,p2,g4,p4,g16,p16);
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black_box b17(g3,p3,g5,p5,g17,p17);
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black_box b18(g4,p4,g6,p6,g18,p18);
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black_box b19(g5,p5,g7,p7,g19,p19);
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black_box b20(g6,p6,g8,p8,g20,p20);
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black_box b21(g7,p7,g9,p9,g21,p21);
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black_box b22(g8,p8,g10,p10,g22,p22);
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black_box b23(g9,p9,g11,p11,g23,p23);
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black_box b24(g10,p10,g12,p12,g24,p24);
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black_box b25(g11,p11,g13,p13,g25,p25);
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black_box b26(g12,p12,g14,p14,g26,p26);
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gray_box gb3(g13,p13,GG[1],GG[3]);
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gray_box gb2(g14,p14,GG[0],GG[2]);
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black_box b27(g15,p15,g19,p19,g27,p27);
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black_box b28(g16,p16,g20,p20,g28,p28);
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black_box b29(g17,p17,g21,p21,g29,p29);
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black_box b30(g18,p18,g22,p22,g30,p30);
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black_box b31(g19,p19,g23,p23,g31,p31);
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black_box b32(g20,p20,g24,p24,g32,p32);
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black_box b33(g21,p21,g25,p25,g33,p33);
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black_box b34(g22,p22,g26,p26,g34,p34);
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gray_box gb7(g23,p23,GG[3],GG[7]);
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gray_box gb6(g24,p24,GG[2],GG[6]);
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gray_box gb5(g25,p25,GG[1],GG[5]);
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gray_box gb4(g26,p26,GG[0],GG[4]);
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gray_box gb15(g27,p27,GG[7],GG[15]);
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gray_box gb14(g28,p28,GG[6],GG[14]);
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gray_box gb13(g29,p29,GG[5],GG[13]);
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gray_box gb12(g30,p30,GG[4],GG[12]);
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gray_box gb11(g31,p31,GG[3],GG[11]);
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gray_box gb10(g32,p32,GG[2],GG[10]);
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gray_box gb9(g33,p33,GG[1],GG[9]);
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gray_box gb8(g34,p34,GG[0],GG[8]);
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//Final Sum And Cout.
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assign s[0]=p[0]^cin;
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assign s[1]=p[1]^GG[0];
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assign s[2]=p[2]^GG[1];
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assign s[3]=p[3]^GG[2];
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assign s[4]=p[4]^GG[3];
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assign s[5]=p[5]^GG[4];
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assign s[6]=p[6]^GG[5];
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assign s[7]=p[7]^GG[6];
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assign s[8]=p[8]^GG[7];
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assign s[9]=p[9]^GG[8];
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assign s[10]=p[10]^GG[9];
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assign s[11]=p[11]^GG[10];
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assign s[12]=p[12]^GG[11];
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assign s[13]=p[13]^GG[12];
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assign s[14]=p[14]^GG[13];
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assign s[15]=p[15]^GG[14];
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assign cout=GG[15];
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endmodule
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‎Code/Processor/Control_Unit.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:26:49 02/02/2015
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// Design Name:
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// Module Name: Control_Unit
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Control_Unit(
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input [3:0]op,
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input ctrl,
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input [1:0]re_config,
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output jmp,eop,ctrl_sel,mem_wr,wr_bk_sel,
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output [1:0]reg_wr,
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output [3:0]alu_sel,
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output [1:0]dir_val
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);
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wire w1,w2,w3,w4,k,shiftv;
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//Regwr
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assign w1=(op[3]&~op[2]&op[1]&op[0]); //store
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assign w2=(op[3]&op[2]&~op[1]&op[0]); //jump
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assign w3=(op[3]&op[2]&op[1]&~op[0]); //NOP
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assign w4=(op[3]&op[2]&op[1]&op[0]); //EOP
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assign k=w1|w2|w3|w4;
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assign shiftv=re_config[1]&re_config[0]&op[3]&op[2]&~op[1]&~op[0];
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assign reg_wr[1]=(re_config[1]|(op[3]&~op[2]&~op[1]&~op[0])|shiftv)&(~k);
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assign reg_wr[0]=(re_config[0]|(op[3]&~op[2]&~op[1]&~op[0])|shiftv)&(~k);
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//Memwr
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assign mem_wr=w1;
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//Write Back Select
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assign wr_bk_sel=(op[3]&~op[2]&op[1]&~op[0]);
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//Dual select in ALU
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assign ctrl_sel=ctrl&~w3;
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//Jump
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assign jmp=(op[3]&op[2]&~op[1]&op[0]);
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//EOP
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assign eop=(op[3]&op[2]&op[1]&op[0]);
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//Direct Value
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assign dir_val[1]=op[3]&~op[2]&~op[1]&op[0]&ctrl;
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assign dir_val[0]=op[3]&op[2]&~op[1]&~op[0];
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//ALU select
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assign alu_sel=(op&{4{~w3}})|({~op[3],op[2],op[1],~op[0]}&{4{w3}});
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endmodule
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