extend for other 3rd gen ryzen cpus? #1

spektren · 2021-02-14T12:32:31Z

Thanks for your work!

How did you obtain the info for the pmtable's content mapping provided in the current version (0x380804, for the 5900X you're running)?

I modified it (by guessing and comparing to 3700) to fit for my 5600X. In my eyes it doesn't look too bad but honestly I'm not very familiar with the expected values for this kind of setup and some data may be completely off without me noticing it all^^

Would you like me to clean my data below and add a pull request with the whole addition of 5600X or are you content with providing ryzen_monitor as is?

Cheers,
Paul

void pm_table_0x380904(pm_table *pmt, void* base_addr) {
    // loosely tested with:
    // Ryzen 5600X on ASUS B550-I, bios 1803, SMU FW v56.45.0, AGESA 1.2.0.0

    pmt->version = 0x380904;
    pmt->max_cores = 8; //Number of cores supported by this PM table version
    pmt->zen_version = 3; //Zen3

    /* Legend for notes in comments:
     * o = ok. I'm confident this is the right value.
     * s = static. Does not change unter load.
     * z = always zero
     * c = changes under load. Don't know if the value is correct.
     */

    pmt->PPT_LIMIT = pm_element( 0); //o
    pmt->PPT_VALUE = pm_element( 1); //o
    pmt->TDC_LIMIT = pm_element( 2); //o
    pmt->TDC_VALUE = pm_element( 3); //o
    pmt->THM_LIMIT = pm_element( 4); //o
    pmt->THM_VALUE = pm_element( 5); //o
    pmt->FIT_LIMIT = pm_element( 6); //o
    pmt->FIT_VALUE = pm_element( 7); //o
    pmt->EDC_LIMIT = pm_element( 8); //o
    pmt->EDC_VALUE = pm_element( 9); //o
    pmt->VID_LIMIT = pm_element(10); //o
    pmt->VID_VALUE = pm_element(11); //o

    pmt->PPT_WC     = pm_element(12);
    pmt->PPT_ACTUAL = pm_element(13); //o
    pmt->TDC_WC     = pm_element(14);
    pmt->TDC_ACTUAL = pm_element(15); //o
    pmt->THM_WC     = pm_element(16);
    pmt->THM_ACTUAL = pm_element(17); //o
    pmt->FIT_WC     = pm_element(18);
    pmt->FIT_ACTUAL = pm_element(19); //o
    pmt->EDC_WC     = pm_element(20);
    pmt->EDC_ACTUAL = pm_element(21); //o
    pmt->VID_WC     = pm_element(22);
    pmt->VID_ACTUAL = pm_element(23); //o

    pmt->VDDCR_CPU_POWER = pm_element(24); //o
    pmt->VDDCR_SOC_POWER = pm_element(25); //o
    pmt->VDDIO_MEM_POWER = pm_element(26); //o
    pmt->VDD18_POWER     = pm_element(27); //o
    pmt->ROC_POWER       = pm_element(28); //s
    pmt->SOCKET_POWER    = pm_element(29); //o

    pmt->PPT_FREQUENCY     = pm_element(30);
    pmt->TDC_FREQUENCY     = pm_element(31);
    pmt->THM_FREQUENCY     = pm_element(32);
    pmt->PROCHOT_FREQUENCY = pm_element(33);
    pmt->VOLTAGE_FREQUENCY = pm_element(34);
    pmt->CCA_FREQUENCY     = pm_element(35);

    pmt->FIT_VOLTAGE            = pm_element(36);
    pmt->FIT_PRE_VOLTAGE        = pm_element(37);
    pmt->LATCHUP_VOLTAGE        = pm_element(38);
    pmt->CPU_SET_VOLTAGE        = pm_element(39); //os
    pmt->CPU_TELEMETRY_VOLTAGE  = pm_element(40);
    pmt->CPU_TELEMETRY_VOLTAGE2 = pm_element(41);
    pmt->CPU_TELEMETRY_CURRENT  = pm_element(42); //o
    pmt->CPU_TELEMETRY_POWER    = pm_element(43); //o
    pmt->SOC_SET_VOLTAGE        = pm_element(44); //os
    pmt->SOC_TELEMETRY_VOLTAGE  = pm_element(45); //o
    pmt->SOC_TELEMETRY_CURRENT  = pm_element(46); //o
    pmt->SOC_TELEMETRY_POWER    = pm_element(47); //o

    pmt->FCLK_FREQ          = pm_element(48); //o
    pmt->FCLK_FREQ_EFF      = pm_element(49); //o
    pmt->UCLK_FREQ          = pm_element(50); //o
    pmt->MEMCLK_FREQ        = pm_element(51); //o
    pmt->FCLK_DRAM_SETPOINT = pm_element(52);
    pmt->FCLK_DRAM_BUSY     = pm_element(53);
    pmt->FCLK_GMI_SETPOINT  = pm_element(54);
    pmt->FCLK_GMI_BUSY      = pm_element(55);
    pmt->FCLK_IOHC_SETPOINT = pm_element(56);
    pmt->FCLK_IOHC_BUSY     = pm_element(57);
    pmt->FCLK_XGMI_SETPOINT = pm_element(58);
    pmt->FCLK_XGMI_BUSY     = pm_element(59);

    pmt->CCM_READS     = pm_element(60);
    pmt->CCM_WRITES    = pm_element(61);
    pmt->IOMS          = pm_element(62);
    pmt->XGMI          = pm_element(63);
    pmt->CS_UMC_READS  = pm_element(64);
    pmt->CS_UMC_WRITES = pm_element(65);
    //unknown: 66 .. 69
    assign_pm_elements_4(pmt->FCLK_RESIDENCY,     70,  71,  72,  73);
    assign_pm_elements_4(pmt->FCLK_FREQ_TABLE,    74,  75,  76,  77);
    assign_pm_elements_4(pmt->UCLK_FREQ_TABLE,    78,  79,  80,  81);
    assign_pm_elements_4(pmt->MEMCLK_FREQ_TABLE,  82,  83,  84,  85);
    assign_pm_elements_4(pmt->FCLK_VOLTAGE,       86,  87,  88,  89);

    assign_pm_elements_4(pmt->LCLK_SETPOINT,  90,  98, 106, 114);
    assign_pm_elements_4(pmt->LCLK_BUSY,      91,  99, 107, 115);
    assign_pm_elements_4(pmt->LCLK_unk1,      92, 100, 108, 116);
    assign_pm_elements_4(pmt->LCLK_unk2,      93, 101, 109, 117);
    assign_pm_elements_4(pmt->LCLK_FREQ,      94, 102, 110, 118);
    assign_pm_elements_4(pmt->LCLK_FREQ_EFF,  95, 103, 111, 119);
    assign_pm_elements_4(pmt->LCLK_MAX_DPM,   96, 104, 112, 120);
    assign_pm_elements_4(pmt->LCLK_MIN_DPM,   97, 105, 113, 121);

    pmt->XGMI_SETPOINT   = pm_element(122);
    pmt->XGMI_BUSY       = pm_element(123);
    pmt->XGMI_LANE_WIDTH = pm_element(124);
    pmt->XGMI_DATA_RATE  = pm_element(125);

    pmt->SOC_POWER           = pm_element(126); //x
    pmt->SOC_TEMP            = pm_element(127); //o?
    pmt->DDR_VDDP_POWER      = pm_element(128);
    pmt->DDR_VDDIO_MEM_POWER = pm_element(129);
    pmt->GMI2_VDDG_POWER     = pm_element(130);
    pmt->IO_VDDCR_SOC_POWER  = pm_element(131);
    pmt->IOD_VDDIO_MEM_POWER = pm_element(132);
    pmt->IO_VDD18_POWER      = pm_element(133); 
    pmt->TDP                 = pm_element(134);
    pmt->DETERMINISM         = pm_element(135);
    pmt->V_VDDM              = pm_element(136);
    pmt->V_VDDP              = pm_element(137);
    pmt->V_VDDG              = pm_element(138);
    pmt->V_unk1              = pm_element(139);

    pmt->PEAK_TEMP      = pm_element(140); //o
    pmt->PEAK_VOLTAGE   = pm_element(141); //o
    pmt->unk_power      = pm_element(142); //maybe power?
    pmt->AVG_CORE_COUNT = pm_element(143);
    pmt->CCLK_LIMIT     = pm_element(144); //o GHz
    pmt->MAX_VOLTAGE    = pm_element(145); //o
    pmt->DC_BTC         = pm_element(146);
    pmt->PACKAGE_POWER  = pm_element(147); //?
    //unkown 148, 149
    pmt->CSTATE_BOOST   = pm_element(150);
    pmt->PROCHOT        = pm_element(151);
    pmt->PC6            = pm_element(152);
    pmt->PWM            = pm_element(153);

    //pmt->unk_0268 = pm_element(154);
    //pmt->clk_026c = pm_element(155);
    //pmt->clk_0270 = pm_element(156);
    pmt->SOCCLK   = pm_element(157);
    pmt->SHUBCLK  = pm_element(158);
    pmt->MP0CLK   = pm_element(159);
    pmt->MP1CLK   = pm_element(160);
    pmt->MP5CLK   = pm_element(161);
    pmt->SMNCLK   = pm_element(162);
    pmt->TWIXCLK  = pm_element(163);
    pmt->clk_0290 = pm_element(164);
    pmt->WAFLCLK  = pm_element(165); //0 in https://chart-studio.plotly.com/~brettdram/16/

    pmt->DPM_BUSY = pm_element(166);
    pmt->MP1_BUSY = pm_element(167);
    pmt->MP5_BUSY = pm_element(168);

    assign_pm_elements_16_consec(pmt->CORE_POWER       , 169+0*8);
    assign_pm_elements_16_consec(pmt->CORE_VOLTAGE     , 185-1*8);
    assign_pm_elements_16_consec(pmt->CORE_TEMP        , 201-2*8);
    assign_pm_elements_16_consec(pmt->CORE_FIT         , 217-3*8);
    assign_pm_elements_16_consec(pmt->CORE_IDDMAX      , 233-4*8);
    assign_pm_elements_16_consec(pmt->CORE_FREQ        , 249-5*8);
    assign_pm_elements_16_consec(pmt->CORE_FREQEFF     , 265-6*8);
    assign_pm_elements_16_consec(pmt->CORE_C0          , 281-7*8);
    assign_pm_elements_16_consec(pmt->CORE_CC1         , 297-8*8);
    assign_pm_elements_16_consec(pmt->CORE_CC6         , 313-9*8);
    assign_pm_elements_16_consec(pmt->CORE_CKS_FDD     , 329-10*8);
    assign_pm_elements_16_consec(pmt->CORE_CI_FDD      , 345-11*8);
    assign_pm_elements_16_consec(pmt->CORE_IRM         , 361-12*8);
    assign_pm_elements_16_consec(pmt->CORE_PSTATE      , 377-13*8);
//    assign_pm_elements_16_consec(pmt->CORE_FREQ_LIM_MAX, 393-14*8);
//    assign_pm_elements_16_consec(pmt->CORE_FREQ_LIM_MIN, 409-15*8);
    assign_pm_elements_16_consec(pmt->CORE_CPPC_MAX    , 425-16-16*8);
    assign_pm_elements_16_consec(pmt->CORE_CPPC_MIN    , 441-16-17*8);
//    assign_pm_elements_16_consec(pmt->CORE_unk         , 457-18*8);
    assign_pm_elements_16_consec(pmt->CORE_SC_LIMIT    , 473-24-19*8);
    assign_pm_elements_16_consec(pmt->CORE_SC_CAC      , 489-24-24-20*8);
    assign_pm_elements_16_consec(pmt->CORE_SC_RESIDENCY, 505-24-21*8);


    assign_pm_elements_2(pmt->L3_LOGIC_POWER   , 521-24-22*8, 522-24-22*8);
    assign_pm_elements_2(pmt->L3_VDDM_POWER    , 523-24-22*8, 524-24-22*8);
    assign_pm_elements_2(pmt->L3_TEMP          , 525-24-22*8, 526-24-22*8);
    assign_pm_elements_2(pmt->L3_FIT           , 527-24-22*8, 528-24-22*8);
    assign_pm_elements_2(pmt->L3_IDDMAX        , 529-24-22*8, 530-24-22*8);
    assign_pm_elements_2(pmt->L3_FREQ          , 531-24-22*8, 532-24-22*8);
    assign_pm_elements_2(pmt->L3_CKS_FDD       , 533-24-22*8, 534-24-22*8);
    assign_pm_elements_2(pmt->L3_CCA_THRESHOLD , 535-24-22*8, 536-24-22*8);
    assign_pm_elements_2(pmt->L3_CCA_CAC       , 537-24-22*8, 538-24-22*8);
    assign_pm_elements_2(pmt->L3_CCA_ACTIVATION, 539-24-22*8, 540-24-22*8);
    assign_pm_elements_2(pmt->L3_EDC_LIMIT     , 541-24-22*8, 542-24-22*8);
    assign_pm_elements_2(pmt->L3_EDC_CAC       , 543-24-22*8, 544-24-22*8);
    assign_pm_elements_2(pmt->L3_EDC_RESIDENCY , 545-24-22*8, 546-24-22*8);

    //[2] //z
    //[2] //(s)(1)
    //[2] //c 21->31

    pmt->min_size = (547-24-22*8)*4; //(Highest element we access + 1)*4.
                           //Needed to avoid illegal memory access
}

╭───────────────────────────────────────────────┬────────────────────────────────────────────────╮
│                                     CPU Model │             AMD Ryzen 5 5600X 6-Core Processor │
│                           Processor Code Name │                                        Vermeer │
│                                         Cores │                                              6 │
│                                     Core CCDs │                                              1 │
│                                 Cores Per CCD │                                              6 │
│                                SMU FW Version │                                       v56.45.0 │
│                                MP1 IF Version │                                            v11 │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭─────────┬────────────┬──────────┬─────────┬──────────┬─────────────┬─────────────┬─────────────╮
│  Core 0 │ s  198 MHz |  0.176 W | 0.369 V |  32.31 C | C0:   2.7 % | C1:  22.4 % | C6:  75.0 % │
│  Core 1 │ s  183 MHz |  0.158 W | 0.371 V |  32.11 C | C0:   2.8 % | C1:  22.8 % | C6:  74.8 % │
│  Core 2 │ s   78 MHz |  0.068 W | 0.256 V |  32.00 C | C0:   0.4 % | C1:   8.0 % | C6:  91.8 % │
│  Core 3 │ s  367 MHz |  0.279 W | 0.320 V |  32.31 C | C0:   3.5 % | C1:  14.3 % | C6:  82.3 % │
│  Core 4 │ s   86 MHz |  0.063 W | 0.208 V |  31.97 C | C0:   0.3 % | C1:   1.1 % | C6:  98.8 % │
│  Core 5 │ s  123 MHz |  0.084 W | 0.235 V |  31.94 C | C0:   0.6 % | C1:   4.8 % | C6:  94.8 % │
╰─────────┴────────────┴──────────┴─────────┴──────────┴─────────────┴─────────────┴─────────────╯
╭── Core Statistics (Calculated) ───────────────┬────────────────────────────────────────────────╮
│              Highest Effective Core Frequency │                                        367 MHz │
│                      Highest Core Temperature │                                        32.31 C │
│                          Highest Core Voltage │                                        0.371 V │
│                          Average Core Voltage │                                        0.293 V │
│                              Average Core CC6 │                                        86.25 % │
│                          Total Core Power Sum │                                       0.8280 W │
├── Reported by SMU ────────────────────────────┼────────────────────────────────────────────────┤
│                             Peak Core Voltage │                                        0.565 V │
│                                   Package CC6 │                                        46.13 % │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭── Electrical & Thermal Constraints ───────────┬────────────────────────────────────────────────╮
│                              Peak Temperature │                                        47.00 C │
│                               SoC Temperature │                                        32.09 C │
│                         Voltage from Core VRM │               0.885 V |   1.450 V |    61.00 % │
│                                           PPT │              18.707 W |      64 W |    29.23 % │
│                                     TDC Value │               1.021 A |      64 A |     1.59 % │
│                                    TDC Actual │               1.194 A |      64 A |     1.87 % │
│                                           EDC │               1.021 A |      96 A |     1.06 % │
│                                           THM │               32.83 C |      84 C |    39.08 % │
│                                           FIT │                   0   |   12944   |     0.00 % │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭── Memory Interface ───────────────────────────┬────────────────────────────────────────────────╮
│                                  Coupled Mode │                                             ON │
│                        Fabric Clock (Average) │                                        874 MHz │
│                                  Fabric Clock │                                       1600 MHz │
│                                  Uncore Clock │                                       1600 MHz │
│                                  Memory Clock │                                       1600 MHz │
│                                     cLDO_VDDM │                                       0.9504 V │
│                                     cLDO_VDDP │                                       0.9002 V │
│                                     cLDO_VDDG │                                       0.9002 V │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭── Power Consumption ──────────────────────────┬────────────────────────────────────────────────╮
│                          Total Core Power Sum │                                       0.8280 W │
│                               VDDCR_SOC Power │                                       4.9001 W │
│                               GMI2_VDDG Power │                                       2.5178 W │
│                                L3 Logic Power │                0.553 W +  0.6384 W =  1.1912 W │
│                                 L3 VDDM Power │                0.000 W +  0.0000 W =  0.0000 W │
│                                               │                                                │
│                               VDDIO_MEM Power │                                      10.9027 W │
│                           IOD_VDDIO_MEM Power │                                       1.7730 W │
│                                DDR_VDDP Power │                                       4.7454 W │
│                                   VDD18 Power │                                       0.9322 W │
│                                               │                                                │
│                     Calculated Thermal Output │                                      27.7904 W │
├── Additional Reports ─────────────────────────┼────────────────────────────────────────────────┤
│                              SoC Power (SVI2) │               1.000 V |   4.901 A |    4.900 W │
│                             Core Power (SVI2) │               0.565 V |   1.020 A |    0.972 W │
│                              Core Power (SMU) │                                        0.972 W │
│                            Socket Power (SMU) │                                      18.7066 W │
│                           Package Power (SMU) │                                      18.7123 W │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯

The text was updated successfully, but these errors were encountered:

hattedsquirrel · 2021-02-14T13:58:40Z

Hey Paul,
thanks for the work you put in :D Yes, pleaso go ahead with the pull request.

Two quick notes:

Since your table reports only 8 cores, using assign_pm_elements_8_consec for the core-related values would be more suiteable. That way cores 9-15 stay marked as "not available" for the rest of the program.
Your screenshot shows two power values for L3 Logic Power, and none for L3 VDDM Power. Your CPU should only have one L3 (Zen3 has one unified L3 cache per CCD). I suspect your pm-table might only report the dataset for one L3 as consecutive values instead of interleaved with a second set. Like this:

pmt->L3_LOGIC_POWER[0] = pm_element(521-24-22*8);
pmt->L3_VDDM_POWER[0] = pm_element(522-24-22*8);
pmt->L3_TEMP[0] = pm_element(523-24-22*8);
...

Can you check if that makes sense with the values you see in the pm table dumps?

My process for reverse-engineering the table was very similar to yours:
I compared my table dumps to the table for 3700X and did some educated guesses. Basically i took a baseline snapshot with no load and a few more for 1, 2 and all threads loaded. For some of the non-cpu-core related fields it might be possible to provoke changes by changing settings in your BIOS, for example the various voltages. But that is a lot of effort for dimishing returns and I'm happy to accept that those values are not fully tested.

For reference, my process for generating human readable dumps is:

cat /sys/kernel/ryzen_smu_drv/pm_table > dump.bin
./read_dump.py > dump_baseline.txt

read_dump.py is provided by ryzen_smu: https://gitlab.com/leogx9r/ryzen_smu/-/blob/master/scripts/read_dump.py
Then i use pr -m -t dump_baseline.txt dump_load_2threads.txt > dump_sbs.txt to have baseline and load side-by-side. That makes it easy to spot changes. The (line number - 1) is the "element number" in pm_tables.c.

hattedsquirrel · 2021-02-15T19:55:20Z

Paul, would you be willing to provide me with a pm_table dump file of a fully loaded system? I'd like to take a look myself and see what I can make out of the numbers.

Copy and paste help: ;-)

for i in {1..16}; do (yes > /dev/null &); done
sleep 5
cat /sys/kernel/ryzen_smu_drv/pm_table > dump.bin
killall yes

Then attach the dump.bin. Thanks.

spektren · 2021-02-15T22:42:23Z

Thanks for giving me a head start on how to get the smu block, to translate it to physical values and easily make a sbs comparison.

I already started and made some progress:
The disabled cores are present (in my case as cores 2 and 3 aka. 3rd and 4th).
Removing the additional values of the second CCD (which isn't present in the 5600x) and re-adding some previously randomly^^ omitted values matches the expected size of 360 values quite well. The absence of the second CCD has to be accounted for in monitor.c as well.

dumps side by side (tab separated):
smu_dump_5600x.txt
first three are stock (idle, core123busy, allbusy). The 4th is all core load under prime95 tt2 load with modified bios settings.

Ofc, I can provide bin files if preferred.
__

I did just start to find out how to change some of the CPU's settings from the OS (ryzen_smu or corefreq). Maybe this will enable some further progress.

Cheers,
Paul

One of two similar changes to ryzen_monitor.c (lines ~480 and ~500) because of single CCD in 5600X:

        if (ccds == 2) {
		print_line("L3 Logic Power", "%7.3f W + %7.4f W = %7.4f W", pmta(L3_LOGIC_POWER[0]), pmta(L3_LOGIC_POWER[1]),
		        pmta(L3_LOGIC_POWER[0])+pmta(L3_LOGIC_POWER[1]));
		print_line("L3 VDDM Power", "%7.3f W + %7.4f W = %7.4f W", pmta(L3_VDDM_POWER[0]), pmta(L3_VDDM_POWER[1]),
		        pmta(L3_VDDM_POWER[0])+pmta(L3_VDDM_POWER[1]));
	} else if (ccds == 1) {
		print_line("L3 Logic Power", "%7.4f W", pmta(L3_LOGIC_POWER[0]));
		print_line("L3 VDDM Power", "%7.4f W", pmta(L3_VDDM_POWER[0]));
	}

current state of pm table 5600X 6-core [0x380904]


void pm_table_0x380904(pm_table *pmt, void* base_addr) {
    // loosely tested with:
    // Ryzen 5600X on ASUS B550-I, bios 1803, SMU FW v56.45.0, AGESA 1.2.0.0


    pmt->version = 0x380904;
    pmt->max_cores = 8; //Number of cores supported by this PM table version
    pmt->zen_version = 3; //Zen3

    /* CAREFUL -- 
    confidence classification copied from hattedsquirrel's work on 5900X
     -- it may not apply to 5600X */
    
    /* Legend for notes in comments:
     * o = ok. I'm confident this is the right value.
     * s = static. Does not change unter load.
     * z = always zero
     * c = changes under load. Don't know if the value is correct.
     */

	pmt->PPT_LIMIT =                    pm_element(0); //o
	pmt->PPT_VALUE =                    pm_element(1); //o
	pmt->TDC_LIMIT =                    pm_element(2); //o
	pmt->TDC_VALUE =                    pm_element(3); //o
	pmt->THM_LIMIT =                    pm_element(4); //o
	pmt->THM_VALUE =                    pm_element(5); //o
	pmt->FIT_LIMIT =                    pm_element(6); //o
	pmt->FIT_VALUE =                    pm_element(7); //o
	pmt->EDC_LIMIT =                    pm_element(8); //o
	pmt->EDC_VALUE =                    pm_element(9); //o
	pmt->VID_LIMIT =                    pm_element(10); //o
	pmt->VID_VALUE =                    pm_element(11); //o
	pmt->PPT_WC =                       pm_element(12);
	pmt->PPT_ACTUAL =                   pm_element(13); //o
	pmt->TDC_WC =                       pm_element(14);
	pmt->TDC_ACTUAL =                   pm_element(15); //o
	pmt->THM_WC =                       pm_element(16);
	pmt->THM_ACTUAL =                   pm_element(17); //o
	pmt->FIT_WC =                       pm_element(18);
	pmt->FIT_ACTUAL =                   pm_element(19); //o
	pmt->EDC_WC =                       pm_element(20);
	pmt->EDC_ACTUAL =                   pm_element(21); //o
	pmt->VID_WC =                       pm_element(22);
	pmt->VID_ACTUAL =                   pm_element(23); //o
	pmt->VDDCR_CPU_POWER =              pm_element(24); //o
	pmt->VDDCR_SOC_POWER =              pm_element(25); //o
	pmt->VDDIO_MEM_POWER =              pm_element(26); //o
	pmt->VDD18_POWER =                  pm_element(27); //o
	pmt->ROC_POWER =                    pm_element(28); //s
	pmt->SOCKET_POWER =                 pm_element(29); //o
	pmt->PPT_FREQUENCY =                pm_element(30);
	pmt->TDC_FREQUENCY =                pm_element(31);
	pmt->THM_FREQUENCY =                pm_element(32);
	pmt->PROCHOT_FREQUENCY =            pm_element(33);
	pmt->VOLTAGE_FREQUENCY =            pm_element(34);
	pmt->CCA_FREQUENCY =                pm_element(35);
	pmt->FIT_VOLTAGE =                  pm_element(36);
	pmt->FIT_PRE_VOLTAGE =              pm_element(37);
	pmt->LATCHUP_VOLTAGE =              pm_element(38);
	pmt->CPU_SET_VOLTAGE =              pm_element(39); //os
	pmt->CPU_TELEMETRY_VOLTAGE =        pm_element(40);
	pmt->CPU_TELEMETRY_VOLTAGE2 =       pm_element(41);
	pmt->CPU_TELEMETRY_CURRENT =        pm_element(42); //o
	pmt->CPU_TELEMETRY_POWER =          pm_element(43); //o
	pmt->SOC_SET_VOLTAGE =              pm_element(44); //os
	pmt->SOC_TELEMETRY_VOLTAGE =        pm_element(45); //o
	pmt->SOC_TELEMETRY_CURRENT =        pm_element(46); //o
	pmt->SOC_TELEMETRY_POWER =          pm_element(47); //o
	pmt->FCLK_FREQ =                    pm_element(48); //o
	pmt->FCLK_FREQ_EFF =                pm_element(49); //o
	pmt->UCLK_FREQ =                    pm_element(50); //o
	pmt->MEMCLK_FREQ =                  pm_element(51); //o
	pmt->FCLK_DRAM_SETPOINT =           pm_element(52);
	pmt->FCLK_DRAM_BUSY =               pm_element(53);
	pmt->FCLK_GMI_SETPOINT =            pm_element(54);
	pmt->FCLK_GMI_BUSY =                pm_element(55);
	pmt->FCLK_IOHC_SETPOINT =           pm_element(56);
	pmt->FCLK_IOHC_BUSY =               pm_element(57);
	pmt->FCLK_XGMI_SETPOINT =           pm_element(58);
	pmt->FCLK_XGMI_BUSY =               pm_element(59);
	pmt->CCM_READS =                    pm_element(60);
	pmt->CCM_WRITES =                   pm_element(61);
	pmt->IOMS =                         pm_element(62);
	pmt->XGMI =                         pm_element(63);
	pmt->CS_UMC_READS =                 pm_element(64);
	pmt->CS_UMC_WRITES =                pm_element(65);
	//unknown: 66 .. 69
	//unknown: 66 .. 69
	//unknown: 66 .. 69
	//unknown: 66 .. 69
	assign_pm_elements_4(pmt->FCLK_RESIDENCY        , 70, 71, 72, 73);
	assign_pm_elements_4(pmt->FCLK_FREQ_TABLE       , 74, 75, 76, 77);
	assign_pm_elements_4(pmt->UCLK_FREQ_TABLE       , 78, 79, 80, 81);
	assign_pm_elements_4(pmt->MEMCLK_FREQ_TABLE     , 82, 83, 84, 85);
	assign_pm_elements_4(pmt->FCLK_VOLTAGE          , 86, 87, 88, 89);
	assign_pm_elements_4(pmt->LCLK_SETPOINT         , 90, 91, 92, 93);
	assign_pm_elements_4(pmt->LCLK_BUSY             , 94, 95, 96, 97);
	assign_pm_elements_4(pmt->LCLK_unk1             , 98, 99, 100, 101);
	assign_pm_elements_4(pmt->LCLK_unk2             , 102, 103, 104, 105);
	assign_pm_elements_4(pmt->LCLK_FREQ             , 106, 107, 108, 109);
	assign_pm_elements_4(pmt->LCLK_FREQ_EFF         , 110, 111, 112, 113);
	assign_pm_elements_4(pmt->LCLK_MAX_DPM          , 114, 115, 116, 117);
	assign_pm_elements_4(pmt->LCLK_MIN_DPM          , 118, 119, 120, 121);
	pmt->XGMI_SETPOINT =                pm_element(122);
	pmt->XGMI_BUSY =                    pm_element(123);
	pmt->XGMI_LANE_WIDTH =              pm_element(124);
	pmt->XGMI_DATA_RATE =               pm_element(125);
	pmt->SOC_POWER =                    pm_element(126); //x
	pmt->SOC_TEMP =                     pm_element(127); //o?
	pmt->DDR_VDDP_POWER =               pm_element(128);
	pmt->DDR_VDDIO_MEM_POWER =          pm_element(129);
	pmt->GMI2_VDDG_POWER =              pm_element(130);
	pmt->IO_VDDCR_SOC_POWER =           pm_element(131);
	pmt->IOD_VDDIO_MEM_POWER =          pm_element(132);
	pmt->IO_VDD18_POWER =               pm_element(133); 
	pmt->TDP =                          pm_element(134);
	pmt->DETERMINISM =                  pm_element(135);
	pmt->V_VDDM =                       pm_element(136);
	pmt->V_VDDP =                       pm_element(137);
	pmt->V_VDDG =                       pm_element(138);
	pmt->V_unk1 =                       pm_element(139);
	pmt->PEAK_TEMP =                    pm_element(140); //o
	pmt->PEAK_VOLTAGE =                 pm_element(141); //o
	pmt->unk_power =                    pm_element(142); //maybe power?
	pmt->AVG_CORE_COUNT =               pm_element(143);
	pmt->CCLK_LIMIT =                   pm_element(144); //o GHz
	pmt->MAX_VOLTAGE =                  pm_element(145); //o
	pmt->DC_BTC =                       pm_element(146);
	pmt->PACKAGE_POWER =                pm_element(147); //?
	//unkown 148, 149
	//unkown 148, 149
	pmt->CSTATE_BOOST =                 pm_element(150);
	pmt->PROCHOT =                      pm_element(151);
	pmt->PC6 =                          pm_element(152);
	pmt->PWM =                          pm_element(153);
	//pmt->unk_0268 =                   pm_element(154);
	//pmt->clk_026c =                   pm_element(155);
	//pmt->clk_0270 =                   pm_element(156);
	pmt->SOCCLK =                       pm_element(157);
	pmt->SHUBCLK =                      pm_element(158);
	pmt->MP0CLK =                       pm_element(159);
	pmt->MP1CLK =                       pm_element(160);
	pmt->MP5CLK =                       pm_element(161);
	pmt->SMNCLK =                       pm_element(162);
	pmt->TWIXCLK =                      pm_element(163);
	pmt->clk_0290 =                     pm_element(164);
	pmt->WAFLCLK =                      pm_element(165); //0 in https://chart-studio.plotly.com/~brettdram/16/
	pmt->DPM_BUSY =                     pm_element(166);
	pmt->MP1_BUSY =                     pm_element(167);
	pmt->MP5_BUSY =                     pm_element(168);
	assign_pm_elements_8_consec(pmt->CORE_POWER                    , 169);
	assign_pm_elements_8_consec(pmt->CORE_VOLTAGE                  , 177);
	assign_pm_elements_8_consec(pmt->CORE_TEMP                     , 185);
	assign_pm_elements_8_consec(pmt->CORE_FIT                      , 193);
	assign_pm_elements_8_consec(pmt->CORE_IDDMAX                   , 201);
	assign_pm_elements_8_consec(pmt->CORE_FREQ                     , 209);
	assign_pm_elements_8_consec(pmt->CORE_FREQEFF                  , 217);
	assign_pm_elements_8_consec(pmt->CORE_C0                       , 225);
	assign_pm_elements_8_consec(pmt->CORE_CC1                      , 233);
	assign_pm_elements_8_consec(pmt->CORE_CC6                      , 241);
	assign_pm_elements_8_consec(pmt->CORE_CKS_FDD                  , 249);
	assign_pm_elements_8_consec(pmt->CORE_CI_FDD                   , 257);
	assign_pm_elements_8_consec(pmt->CORE_IRM                      , 265);
	assign_pm_elements_8_consec(pmt->CORE_PSTATE                   , 273);
	assign_pm_elements_8_consec(pmt->CORE_FREQ_LIM_MAX             , 281);
	assign_pm_elements_8_consec(pmt->CORE_FREQ_LIM_MIN             , 289);
	assign_pm_elements_8_consec(pmt->CORE_CPPC_MAX                 , 297);
	assign_pm_elements_8_consec(pmt->CORE_CPPC_MIN                 , 305);
	assign_pm_elements_8_consec(pmt->CORE_unk                      , 313);
	assign_pm_elements_8_consec(pmt->CORE_SC_LIMIT                 , 321);
	assign_pm_elements_8_consec(pmt->CORE_SC_CAC                   , 329);
	assign_pm_elements_8_consec(pmt->CORE_SC_RESIDENCY             , 337);
	pmt->L3_LOGIC_POWER[0] =                pm_element(345);
	pmt->L3_VDDM_POWER[0] =                 pm_element(346);
	pmt->L3_TEMP[0] =                       pm_element(347);
	pmt->L3_FIT[0] =                        pm_element(348);
	pmt->L3_IDDMAX[0] =                     pm_element(349);
	pmt->L3_FREQ[0] =                       pm_element(350);
	pmt->L3_CKS_FDD[0] =                    pm_element(351);
	pmt->L3_CCA_THRESHOLD[0] =              pm_element(352);
	pmt->L3_CCA_CAC[0] =                    pm_element(353);
	pmt->L3_CCA_ACTIVATION[0] =             pm_element(354);
	pmt->L3_EDC_LIMIT[0] =                  pm_element(355);
	pmt->L3_EDC_CAC[0] =                    pm_element(356);
	pmt->L3_EDC_RESIDENCY[0] =              pm_element(357);
	//unkown 358, 359, 360
	//unkown 358, 359, 360
	//unkown 358, 359, 360
	
	pmt->min_size = 361*4; //(Highest element we access + 1)*4.
	//Needed to avoid illegal memory access

}

output

───────────────────────────────────────────────┬────────────────────────────────────────────────╮
│                                     CPU Model │             AMD Ryzen 5 5600X 6-Core Processor │
│                           Processor Code Name │                                        Vermeer │
│                                         Cores │                                              6 │
│                                     Core CCDs │                                              1 │
│                                 Cores Per CCD │                                              6 │
│                                SMU FW Version │                                       v56.45.0 │
│                                MP1 IF Version │                                            v11 │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭─────────┬────────────┬──────────┬─────────┬──────────┬─────────────┬─────────────┬─────────────╮
│  Core 0 │ s   79 MHz |  1.052 W | 1.364 V |  39.68 C | C0:   2.0 % | C1:  98.0 % | C6:   0.0 % │
│  Core 1 │ s   56 MHz |  0.356 W | 0.510 V |  37.20 C | C0:   1.3 % | C1:  25.3 % | C6:  73.4 % │
│  Core 2 │   4800 MHz |  8.949 W | 1.364 V |  52.33 C | C0: 100.0 % | C1:   0.0 % | C6:   0.0 % │
│  Core 3 │ s   73 MHz |  0.734 W | 0.996 V |  38.09 C | C0:   1.9 % | C1:  66.5 % | C6:  31.6 % │
│  Core 4 │ s  158 MHz |  0.776 W | 0.789 V |  41.13 C | C0:   4.1 % | C1:  46.5 % | C6:  49.4 % │
│  Core 5 │    267 MHz |  0.931 W | 0.702 V |  39.37 C | C0:   6.2 % | C1:  36.9 % | C6:  56.9 % │
╰─────────┴────────────┴──────────┴─────────┴──────────┴─────────────┴─────────────┴─────────────╯
╭── Core Statistics (Calculated) ───────────────┬────────────────────────────────────────────────╮
│              Highest Effective Core Frequency │                                       4800 MHz │
│                      Highest Core Temperature │                                        52.33 C │
│                          Highest Core Voltage │                                        1.364 V │
│                          Average Core Voltage │                                        0.954 V │
│                              Average Core CC6 │                                        35.21 % │
│                          Total Core Power Sum │                                      12.7982 W │
├── Reported by SMU ────────────────────────────┼────────────────────────────────────────────────┤
│                             Peak Core Voltage │                                        1.364 V │
│                                   Package CC6 │                                         0.00 % │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭── Electrical & Thermal Constraints ───────────┬────────────────────────────────────────────────╮
│                              Peak Temperature │                                        61.75 C │
│                               SoC Temperature │                                        37.41 C │
│                         Voltage from Core VRM │               1.364 V |   1.450 V |    94.08 % │
│                                           PPT │              38.437 W |      71 W |    54.14 % │
│                                     TDC Value │              11.668 A |      64 A |    18.23 % │
│                                    TDC Actual │              10.531 A |      64 A |    16.46 % │
│                                           EDC │              16.443 A |      96 A |    17.13 % │
│                                           THM │               52.62 C |      84 C |    62.64 % │
│                                           FIT │                 121   |   12944   |     0.94 % │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭── Memory Interface ───────────────────────────┬────────────────────────────────────────────────╮
│                                  Coupled Mode │                                             ON │
│                        Fabric Clock (Average) │                                       1600 MHz │
│                                  Fabric Clock │                                       1600 MHz │
│                                  Uncore Clock │                                       1600 MHz │
│                                  Memory Clock │                                       1600 MHz │
│                                     cLDO_VDDM │                                       0.9504 V │
│                                     cLDO_VDDP │                                       0.9002 V │
│                                     cLDO_VDDG │                                       0.9002 V │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯
╭── Power Consumption ──────────────────────────┬────────────────────────────────────────────────╮
│                          Total Core Power Sum │                                      12.7982 W │
│                               VDDCR_SOC Power │                                       6.8898 W │
│                               GMI2_VDDG Power │                                       3.9058 W │
│                                L3 Logic Power │                                       1.5792 W │
│                                 L3 VDDM Power │                                       0.4057 W │
│                                               │                                                │
│                               VDDIO_MEM Power │                                      13.6475 W │
│                           IOD_VDDIO_MEM Power │                                       2.3083 W │
│                                DDR_VDDP Power │                                       5.2722 W │
│                                   VDD18 Power │                                       0.9721 W │
│                                               │                                                │
│                     Calculated Thermal Output │                                      47.7787 W │
├── Additional Reports ─────────────────────────┼────────────────────────────────────────────────┤
│                              SoC Power (SVI2) │               0.999 V |   6.897 A |    6.890 W │
│                             Core Power (SVI2) │               1.364 V |  11.690 A |   15.957 W │
│                              Core Power (SMU) │                                       15.957 W │
│                            Socket Power (SMU) │                                      38.4669 W │
│                           Package Power (SMU) │                                      38.1503 W │
╰───────────────────────────────────────────────┴────────────────────────────────────────────────╯

hattedsquirrel · 2021-02-16T02:01:56Z

Looks very good to me. I cross-checked your actual values with my system and it all matches very nicely. So that is reassuring. I have 6 unknown values at the end of my table, that matches as well. Probably something for L3 but who knows what...

On the side of ryzen_monitor.c I already committed some changes for the work on #2. Long story short, there is a new int within pm_tables named max_l3. pmt->max_l3 = 1; would be the line to add in pm_table_0x380904(...).

If you feel you are ready, say so and I'll get that code in :)

spektren · 2021-02-16T06:23:53Z

Please add it.
If extra knowledge is gained we can improve later...

Adding code provided by spektren in #1

hattedsquirrel · 2021-02-16T18:30:53Z

A simple copy and paste later... I think it should work now.

spektren · 2021-02-16T20:50:03Z

Yes it does.
Thank you and happy computing.

PJVol · 2021-05-01T11:06:41Z

pmt->V_unk1 = pm_element(139) VDDG_CCD ?

hattedsquirrel · 2021-05-01T16:52:22Z

@vol2020 Can you elaborate a bit more? How did you determine this element ist VDDG_CCD, what is it for and how does is differ ro V_VDDG? Thanks.

PJVol · 2021-05-01T21:51:56Z

There's two voltages in Zen3. VDDG_IOD and VDDG_CCD. VDDG_CCD seem to power CCD-IOD part of data fabric, while the former supposedly powering IOD-UMC part (I may be wrong here)
As for how I know, I use debug option in Ivan's project (ZenTimings) - it even refreshes PM Table dump when clicking on that button, and the value at 022C is what I set vddg_ccd to in bios.
I'd like to know what voltage is at 0220.

As explained by vol2020 in #1. Also fixed memory initialisation.

hattedsquirrel · 2021-05-03T19:33:54Z

That indeed makes sense. I just added it in the newest commit.

PJVol · 2021-05-14T16:39:59Z

That indeed makes sense. I just added it in the newest commit.

There's one more thing, here.

I think, instead of

	assign_pm_elements_4(pmt->LCLK_SETPOINT      , 90, 91, 92, 93);
	assign_pm_elements_4(pmt->LCLK_BUSY          , 94, 95, 96, 97);
	assign_pm_elements_4(pmt->LCLK_unk1          , 98, 99, 100, 101);
	assign_pm_elements_4(pmt->LCLK_unk2          , 102, 103, 104, 105);
	assign_pm_elements_4(pmt->LCLK_FREQ          , 106, 107, 108, 109);
	assign_pm_elements_4(pmt->LCLK_FREQ_EFF      , 110, 111, 112, 113);
	assign_pm_elements_4(pmt->LCLK_MAX_DPM       , 114, 115, 116, 117);
	assign_pm_elements_4(pmt->LCLK_MIN_DPM       , 118, 119, 120, 121);

there should actually be:

	assign_pm_elements_4(pmt->LCLK_SETPOINT       , 90, 98, 106, 114);
	assign_pm_elements_4(pmt->LCLK_BUSY           , 91, 99, 107, 115);
	assign_pm_elements_4(pmt->LCLK_FREQ           , 92, 100, 108, 116);
	assign_pm_elements_4(pmt->LCLK_FREQ_EFF       , 93, 101, 109, 117);
	assign_pm_elements_4(pmt->LCLK_MAX_DPM        , 94, 102, 110, 118);
	assign_pm_elements_4(pmt->LCLK_MIN_DPM        , 95, 103, 111, 119);
	assign_pm_elements_4(pmt->unknown             , 96, 104, 112, 120);
	assign_pm_elements_4(pmt->unknown             , 97, 105, 113, 121);

PS: Had to change user name to a more familiar one, since it turns out I had 2 accounts, and accidentially logged in with the wrong one (vol2020).

PJVol · 2021-05-14T17:15:21Z

And, if you don't know yet, its still quite common to encounter 2-chiplet versions of 5600X and 5800X, in which case there will be generated 2CCD version of metrics table, such as 00380805 (from 56.50.0)

Pointed out by PJVol in #1, double-checked with existing logs.

hattedsquirrel · 2021-05-15T14:22:54Z

Thanks for pointing that out. I just comitted the changes.

Regarding the 2CCD 5600X: I didn't know they exist, but it makes sense, I guess. I'd expect them to use the same PM Table as a 5900X, tough. Maybe the 00380805 is just a newer version of 00380804. I'll update my BIOS later and see if I get a 00380805 table with the new version.

But if you have any knowledge on what changed between 00380804 and 00380805, or have access to any PMTable dumps for the systems in question, feel free to post them here.

PJVol · 2021-05-15T17:51:02Z

Here is 380804 pm table, asked a local forum member with "dual CCD" 5600X to post. I think 08 and 09 are related to 2ccd and 1ccd versions, the last byte could mean AGESA release version, not sure though. 1200 and 1202 are not much different
ZT debug report 2ccd 5600X.TXT

hattedsquirrel · 2021-05-16T14:20:09Z

I just added 00380805 and 00380905. It works fine on my 5900X. Happy testing :)

From the dump you provided, the dual CCD 5600X should work just fine.
Sidenote: It got me puzzled a bit, though: The first 8 cores are all disabled but report temperatues (as is usual for disabled/broken cores). So the first CCD is there, just completely disabled. All 6 enabled cores are on the second CCD. I have no explanation why they installed the first CCD at all, but... maybe that's just how it is done sometimes.

insunaa · 2021-06-23T06:57:16Z

I'm on AMD AM4 AGESA V2 PI 1.2.0.1 Patch A and ryzen_monitor gives me the following error:

ryzen_smu version string: 0.1.2
SMU Driver Version Incompatible With Library Version

Using the latest version from this github.
CPU I use is a 5950x. Anything I can do to help get that CPU/AGESA supported?

hattedsquirrel · 2021-06-23T07:14:48Z

Hum. That is puzzling. Version 0.1.2 should be supported.
What does cat /sys/kernel/ryzen_smu_drv/drv_version report?

insunaa · 2021-06-23T07:20:48Z

Thanks for the quick reply!

it reports

0.1.2

insunaa · 2021-06-23T07:28:05Z

OK, this was my bad, I had a contaminated compile! :( I'm sorry for wasting your time and I thank you very much for responding so quickly anyway!

hattedsquirrel · 2021-06-23T07:28:38Z

Ok, no problem. I'm happy it works for you now :)

insunaa · 2021-06-23T08:27:29Z

What does happen tho even with a completely decontaminated compile is that sudo ./ryzen_monitor -m never returns for me. Or at least not within 5 minutes, as I haven't tested it over time periods longer than that. Should I open a separate issue or is this also unique to zen3?

Edit: If I insert debug fprintfs in ryzen_monitor.c just where print_memory_timings() is called and another debug fprintf just within readinfo.c just at the top of the print_memory_timings() option, they are not printed either, until I interrupt execution with ^C

hattedsquirrel · 2021-06-23T16:47:07Z

Yip, this one is on me. Good catch. I just pushed a bugfix. It should work now.

spektren · 2021-06-25T15:48:55Z

something's off with the l3_logic_power (100w+) on my single ccd 5600x after the bios update to agesa 1.2.0.3 A (updated to bios 2403 asus b550i + ryzen_smu 0.1.2 + current ryzen_monitor). now data is pulled from the ...905 table.
<<

progress:
i think the new unknown 8-field entry is missing in 380905:

assign_pm_elements_8_consec(pmt->CORE_FREQ_LIM_MIN  , 292);
assign_pm_elements_8_consec(pmt->CORE_unk           , 300); //z, missing for 380905
assign_pm_elements_8_consec(pmt->CORE_SC_LIMIT      , 300+8);
assign_pm_elements_8_consec(pmt->CORE_SC_CAC        , 308+8);
assign_pm_elements_8_consec(pmt->CORE_SC_RESIDENCY  , 316+8);
assign_pm_elements_8_consec(pmt->CORE_UOPS_CLK      , 324+8);
assign_pm_elements_8_consec(pmt->CORE_UOPS          , 332+8);
assign_pm_elements_8_consec(pmt->CORE_MEM_LATECY    , 340+8);
	
pmt->L3_LOGIC_POWER[0] =                pm_element(348+8);
pmt->L3_VDDM_POWER[0] =                 pm_element(349+8);
pmt->L3_TEMP[0] =                       pm_element(350+8);
pmt->L3_FIT[0] =                        pm_element(351+8);
pmt->L3_IDDMAX[0] =                     pm_element(352+8);
pmt->L3_FREQ[0] =                       pm_element(353+8);
pmt->L3_FREQ_EFF[0] =                   pm_element(354+8);
pmt->L3_CKS_FDD[0] =                    pm_element(355+8);
pmt->L3_CCA_THRESHOLD[0] =              pm_element(356+8);
pmt->L3_CCA_CAC[0] =                    pm_element(357+8);
pmt->L3_CCA_ACTIVATION[0] =             pm_element(358+8);
pmt->L3_EDC_LIMIT[0] =                  pm_element(359+8);
pmt->L3_EDC_CAC[0] =                    pm_element(360+8);
pmt->L3_EDC_RESIDENCY[0] =              pm_element(361+8);
pmt->L3_FLL_BTC[0] =                    pm_element(362+8);
//unkown 363
	
pmt->min_size = (363+8)*4; //(Highest element we access + 1)*4.
//Needed to avoid illegal memory access

dump_sbs_5600x_1203a_no_load_vs._8thr.txt

i'll try to prepare a merge next week.
cheerio

Kudos to spektren for pointing this out. #1

hattedsquirrel · 2021-06-27T11:06:27Z

You are absoluetly right! I made that table up from the changes I saw in the other tables and have no hardware to test it with. Must have missed that field while copy&pasting.
I just pushed a fix. Would be great if you could test it. Thanks.

PJVol · 2021-06-27T12:47:52Z

What the pm_table version is on 1.2.0.3b ?

hattedsquirrel · 2021-06-27T14:46:51Z

What the pm_table version is on 1.2.0.3b ?

I don't know because I don't have a board with a bios that contains that vesion. But you can find out for yourself by reading /sys/kernel/ryzen_smu_drv/pm_table_version

PJVol · 2021-06-27T16:44:05Z

But you can find out for yourself

Had I 1.2.0.3b bios flashed, I won't ask.

spektren · 2021-06-27T19:35:20Z

@hattedsquirrel
Looks great. Thank you!

@PJVol
Sorry, there is no newer bios than 1.2.0.3 Patch A for my ASUS b550i neither

PJVol · 2022-01-18T22:18:14Z

@hattedsquirrel

In case you guys are still supporting the project, i wanted to note that in a pm_tables.c there are 2 missing limiter frequencies in a 8 freq. block, lines 502-507, offsets 0x78 - 0x94.
Not sure about the 2nd one, but the first is definitely Global Frequency. The last two supposedly Voltage and CCA, since the former can be observed in a monitoring tools and it is the one that drive the Global Limiter when the seven remaining ones are unreachable.
so I'd suggest
pmt->GLOBAL_FREQUENCY = pm_element(30);
pmt->PPT_FREQUENCY = pm_element(31);
pmt->TDC_FREQUENCY = pm_element(32);
pmt->THM_FREQUENCY = pm_element(33);
pmt->PROCHOT_FREQUENCY = pm_element(34);
pmt->?? (supposedly HTCFrequency) = pm_element(35);
pmt->VOLTAGE_FREQUENCY = pm_element(36);
pmt->CCA_FREQUENCY = pm_element(37);

irusanov · 2022-01-21T02:18:21Z

You're on the right path, I think this should be correct:

    pmt->CCLK_GLOBAL_FREQ  = pm_element(30);
    pmt->PPT_FREQUENCY     = pm_element(31);
    pmt->TDC_FREQUENCY     = pm_element(32);
    pmt->THM_FREQUENCY     = pm_element(33);
    pmt->HTFMAX_FREQUENCY  = pm_element(34);
    pmt->PROCHOT_FREQUENCY = pm_element(35);
    pmt->VOLTAGE_FREQUENCY = pm_element(36);
    pmt->CCA_FREQUENCY     = pm_element(37);

I've also submitted a merge request, but if you decide to get info from it, please double check it.
It can't be merged automatically since I've changed too many things.

PJVol · 2022-01-31T13:35:09Z

@hattedsquirrel @irusanov

You're on the right path, I think this should be correct:
    pmt->CCLK_GLOBAL_FREQ  = pm_element(30);
    pmt->PPT_FREQUENCY     = pm_element(31);
    pmt->TDC_FREQUENCY     = pm_element(32);
    pmt->THM_FREQUENCY     = pm_element(33);
    pmt->HTFMAX_FREQUENCY  = pm_element(34);
    pmt->PROCHOT_FREQUENCY = pm_element(35);
    pmt->VOLTAGE_FREQUENCY = pm_element(36);
    pmt->CCA_FREQUENCY     = pm_element(37);
I've also submitted a merge request, but if you decide to get info from it, please double check it. It can't be merged automatically since I've changed too many things.

I have done some experiments observing their behavior on Vermeer and Cezanne (have both) and have come to the conclusion that the following order is more likely:

> pmt->CCLK_GLOBAL_FREQ  = pm_element(30);
> pmt->PPT_FREQUENCY     = pm_element(31);
> pmt->TDC_FREQUENCY     = pm_element(32);
> pmt->THM_FREQUENCY     = pm_element(33);
> pmt->VOLTAGE_FREQUENCY = pm_element(36);
> pmt->HTFMAX_FREQUENCY  = pm_element(34);
> pmt->PROCHOT_FREQUENCY = pm_element(35);
> pmt->CCA_FREQUENCY     = pm_element(37);

hattedsquirrel · 2022-03-12T12:03:53Z

@irusanov I know it has been a while, but I finally managed to pull in your changes. Many thanks for all the work you invested.

[I haven't had access to my only Ryzen system for over half a year now, so I'm doing it blindly, but from what I can test with existing binary dump files, I cross my fingers to not have broken anything in the process.]

irusanov · 2022-03-13T21:57:12Z

@hattedsquirrel I'm not 100% sure these are entirely correct, it's possible something is not quite right with labels/definitions, but should be an improvement.

KeithMyers mentioned this issue Feb 15, 2021

Incompatible with Ryzen 9 3950X #2

Open

spektren changed the title ~~extend for other 3rd ryzen cpus?~~ extend for other 3rd gen ryzen cpus? Feb 15, 2021

hattedsquirrel added a commit that referenced this issue Feb 16, 2021

Support for Ryzen 5600X ( #1 )

46f477d

Adding code provided by spektren in #1

hattedsquirrel closed this as completed Feb 16, 2021

PJVol mentioned this issue May 1, 2021

zen3 #4

Closed

hattedsquirrel added a commit that referenced this issue May 3, 2021

Add VDDG_CCD

484fa62

As explained by vol2020 in #1. Also fixed memory initialisation.

hattedsquirrel added a commit that referenced this issue May 15, 2021

Corrected LCLK block in 0x380904 and 0x380804

1e7c3ac

Pointed out by PJVol in #1, double-checked with existing logs.

hattedsquirrel added a commit that referenced this issue Jun 27, 2021

Fixed copy&paste mistake in Table 380905 (Ryzen 5600X)

d153d4b

Kudos to spektren for pointing this out. #1

spektren mentioned this issue Jul 24, 2021

Incompatible with Ryzen PRO 4750G #7

Open

reagentoo mentioned this issue Sep 6, 2021

5700G support #9

Open

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