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Clock Domain Crossing

SystemVerilog modules for clock domain crossing on an FPGA.

Build Status

First-in First-out Buffer (FIFO)

A FIFO is a technique especially for high data rate transfer, backed by dual-clock RAM.

Why?

Intel's dc_fifo just wasn't working for me.

Usage

  1. Take files from src/ and add them to your own project. If you use hdlmake, you can add this repository itself as a remote module.
  2. Other helpful modules are also available in this GitHub organization.
  3. Consult the testbench in tets/fifo_tb.sv for example usage.
  4. Read through the parameter descriptions in fifo.sv and tailor any instantiations to your situation.
  5. Please create an issue if you run into a problem or have any questions.

Features

  • Overflow and underflow protection behavior

To-do List

  • Confirm metastability handling is 100% correct
    • If you have experience with clock domain crossing, I would appreciate it if you took a look!