From 0521b7303f3b705271717623485f14a19221c399 Mon Sep 17 00:00:00 2001
From: "maximilian.koschay" <mkoschay@web.de>
Date: Wed, 5 May 2021 12:09:08 +0200
Subject: [PATCH] Exclude substrate ground connections for Simulation

Solves efabless/caravel#54
---
 verilog/rtl/mgmt_protect_hv.v | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index 23d9cf60f..bedba4931 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -45,8 +45,11 @@ module mgmt_protect_hv (
 `ifdef USE_POWER_PINS
     // This is to emulate the substrate shorting grounds together for LVS
     // purposes
-    assign vssa2 = vssa1;
-    assign vssa1 = vssd;
+    `ifndef SIM
+        assign vssa2 = vssa1;
+        assign vssa1 = vssd;
+    `endif
+    
 `endif
 
     // Logic high in the VDDA (3.3V) domains