diff --git a/hls4ml/templates/supported_boards.json b/hls4ml/templates/supported_boards.json index 8f45dbad2..584705f19 100644 --- a/hls4ml/templates/supported_boards.json +++ b/hls4ml/templates/supported_boards.json @@ -28,5 +28,21 @@ "tcl_scripts": {"axi_master": "axi_master_design.tcl"}, "python_drivers": {}, "c_drivers": { "axi_master": "axi_master_design.c"} + }, + + "vcu128": { + "part": "xcvu37p-fsvh2892-2L-e", + "tcl_scripts": {"axi_master": "axi_master_design.tcl"}, + "python_drivers": {}, + "c_drivers": { "axi_master": "axi_master_design.c"} + }, + + "zcu104": { + "part": "xczu7ev-ffvc1156-2-e", + "tcl_scripts": {"axi_stream": "axi_stream_design.tcl"}, + "python_drivers": {"axi_stream": "axi_stream_driver.py"}, + "c_drivers": {} } + + } diff --git a/hls4ml/templates/vivado_accelerator/vcu128/Readme.md b/hls4ml/templates/vivado_accelerator/vcu128/Readme.md new file mode 100644 index 000000000..785d69b84 --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/Readme.md @@ -0,0 +1 @@ +This is the test for adding VCU128 board to HLS4ML template. diff --git a/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/Makefile b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/Makefile new file mode 100644 index 000000000..03ab9b8de --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/Makefile @@ -0,0 +1,33 @@ +DESIGN := design_1 + +help: + @echo "INFO: make to show targets" +.PHONY: help + +--setup: + xsct ./setup.tcl $(DESIGN) +.PHONY: --setup + +sdk: --setup + rm -f $(DESIGN)_standalone/src/helloworld.c + cd $(DESIGN)_standalone/src && ln -s ../../common/main.c main.c + cd $(DESIGN)_standalone/src && ln -s ../../common/data.h data.h +.PHONY: sdk + +gui: + xsdk --workspace . & +.PHONY: gui + +clean: + rm -rf $(DESIGN)_platform + rm -rf $(DESIGN)_standalone + rm -rf $(DESIGN)_standalone_bsp + rm -rf RemoteSystemsTempFiles + rm -rf .Xil + rm -rf .metadata + rm -f *.log +.PHONY: clean + +ultraclean: clean + rm -rf hdf/*.hdf +.PHONY: ultraclean diff --git a/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/common/main.c b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/common/main.c new file mode 100644 index 000000000..84e3aa3d0 --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/common/main.c @@ -0,0 +1,350 @@ +/** + * + * Set Heap Size in ldscript.ld to 0x1000000 (16MB) + * + */ + +#include "xmyproject_axi.h" /* TODO: design-dependent name */ +#include "stdio.h" /* PRINTF */ +#include "unistd.h" /* sleep */ +#include "stdlib.h" +#include "malloc.h" +#include "assert.h" +#include "xil_io.h" /* peripheral read/write wrappers */ +#include "platform.h" /* platform init/cleanup functions */ +#include "xil_cache.h" /* enable/disable caches etc */ +#include "xil_printf.h" /* UART debug print functions */ +#include "xparameters.h" /* peripherals base addresses */ +#include "xtmrctr.h" /* timer, Xilinx IP Timer Counter */ + +#include "data.h" + +/*#define EEMBC_POWER 1 + +#ifdef EEMBC_POWER +#include "xgpio.h" /* AXI GPIO drivers */ + +/*#define PIN 0x01 +#define GPIO_PMOD_PIN_DEVICE_ID XPAR_GPIO_0_DEVICE_ID + +#define set_pin_high(InstancePtr, Mask) \ + XGpio_DiscreteWrite(InstancePtr, 1, Mask) + +#define set_pin_low(InstancePtr, Mask) \ + XGpio_DiscreteClear(InstancePtr, 1, Mask) + +XGpio Gpio; +#endif +*/ + +//#define __DEBUG__ + +#define MAX_PRINT_ELEMENTS (16) + +#define PRINTF printf + +const unsigned INPUT_N_ELEMENTS = N_SAMPLES * N_X_INPUTS; +const unsigned OUTPUT_N_ELEMENTS = N_SAMPLES * N_Y_OUTPUTS; + +#if 1 +/* Accelerator verification */ +#define REFERENCE_OUTPUTS data_y_hls_outputs +#else +/* Accelerator validation */ +#define REFERENCE_OUTPUTS data_y_outputs +//#define REFERENCE_OUTPUTS data_y_keras_outputs +#endif + +unsigned get_max(float *data, unsigned n_elements) { + float max_value = 0.0; + unsigned max_index = 0; + for (unsigned i = 0; i < n_elements; i++) + if (data[i] >= max_value) { + max_index = i; + max_value = data[i]; + } + return max_index; +} + +float *inputs_mem = NULL; +float *outputs_mem = NULL; +float *reference_mem = NULL; + +/* Accelerator configuration */ +XMyproject_axi accelerator; /* TODO: design-dependent name */ +XMyproject_axi_Config *accelerator_cfg; /* TODO: design-dependent name */ + +/* Accelerator initialization routine */ +void init_accelerators() { + PRINTF("INFO: Initializing accelerator\r\n"); + accelerator_cfg = XMyproject_axi_LookupConfig(XPAR_MYPROJECT_AXI_0_DEVICE_ID); /* TODO: design-dependent name */ + if (accelerator_cfg) { + int status = XMyproject_axi_CfgInitialize(&accelerator, accelerator_cfg); /* TODO: design-dependent name */ + if (status != XST_SUCCESS) { + PRINTF("ERROR: Initializing accelerator\r\n"); + } + } +} + +/* Reference implementation of the accelerator in software */ +int sw_reference_implementation(float *sw_inputs_mem, float *sw_outputs_mem, unsigned n_samples, unsigned n_X_inputs, unsigned n_y_ouputs) { +#ifdef __DEBUG__ + PRINTF("INFO: Reference outputs are pre-compiled. It would be nice to run a software model here.\r\n"); +#endif + /* See data.h for inputs and outputs */ + for (unsigned i = 0; i < n_samples * n_y_ouputs; i++) { + sw_outputs_mem[i] = REFERENCE_OUTPUTS[i]; + } + return 0; +} + +/* Profiling utilities */ +static XTmrCtr TimerCounterInst; +#define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID +#define TIMER_CNTR_0 0 +#define TIMER_CNTR_1 1 + +void start_64b_counter() { + XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_0); + XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_1); +} + +void stop_64b_counter() { + XTmrCtr_Stop(&TimerCounterInst, TIMER_CNTR_0); + XTmrCtr_Stop(&TimerCounterInst, TIMER_CNTR_1); +} + +u64 get_64b_counter_value() { + //printf("bytes %u\n\r", sizeof(u64)); + u64 lo_counter = XTmrCtr_GetValue(&TimerCounterInst, TIMER_CNTR_0); + u64 hi_counter = XTmrCtr_GetValue(&TimerCounterInst, TIMER_CNTR_1); + u64 counter = (hi_counter << 32) | lo_counter; + //printf("INFO: hi = %lu, lo = %lu, total = %lu\n\r", hi_counter, lo_counter, counter); + return counter; +} + +#if 0 +double get_elapsed_time(u64 clk_start, u64 clk_stop) { + return ((clk_stop-clk_start) * (1.0/XPAR_AXI_TIMER_MCU_CLOCK_FREQ_HZ)); +} +#endif + +float get_elapsed_time_ns(u64 clks) { + return clks * 1000000000.0/XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ; +} + + +/* Dump data to the console */ +void dump_data(const char* label, float* data, unsigned n_samples, unsigned feature_count) { + PRINTF("INFO: %s[%u][%u]:\r\n", label, n_samples, feature_count); + /* Print at most MAX_PRINT_ELEMENTS */ + for (unsigned i = 0; i < n_samples && i < MAX_PRINT_ELEMENTS; i++) { + PRINTF("INFO: [%u] ", i); + for (unsigned j = 0; j < feature_count; j++) { + unsigned index = i * feature_count + j; + PRINTF("%f ", data[index]); + } + PRINTF("\r\n"); + } +} + +/* The top of the hill :-) */ +int main(int argc, char** argv) { + + int status; + u64 calibration_time; + double __attribute__ ((unused)) sw_elapsed = 0; + u64 hw_elapsed = 0; + u64 cache_elapsed = 0; + unsigned hw_errors; + + char __attribute__ ((unused)) dummy; /* dummy input */ + + /* Initialize platform (uart and caches) */ + init_platform(); + + PRINTF("\r\n"); + PRINTF("INFO: ==================================================\r\n"); + PRINTF("INFO: XMyproject_axi (w/ polling)\r\n"); /* TODO: design-dependent name */ + PRINTF("INFO: ==================================================\r\n"); + + init_accelerators(); + + /* Timer Counter */ + status = XTmrCtr_Initialize(&TimerCounterInst, TMRCTR_DEVICE_ID); + if (status != XST_SUCCESS){ + print("ERROR: Timer counter initialization failed \r\n"); + return status; + } + + XTmrCtr_SetOptions(&TimerCounterInst, TIMER_CNTR_0, + XTC_AUTO_RELOAD_OPTION | + XTC_CASCADE_MODE_OPTION); + + print("INFO: Timer counter initialized\r\n"); + + inputs_mem = malloc(INPUT_N_ELEMENTS * sizeof(float)); + outputs_mem = malloc(OUTPUT_N_ELEMENTS * sizeof(float)); + reference_mem = malloc(OUTPUT_N_ELEMENTS * sizeof(float)); + + /* Calibration */ + start_64b_counter(); + sleep(1); + stop_64b_counter(); + calibration_time = get_64b_counter_value(); + PRINTF("INFO: Time calibration for one second (%lf sec, %llu clk)\r\n", get_elapsed_time_ns(calibration_time), calibration_time); + + /* Initialize memory */ + PRINTF("INFO: Initialize memory\r\n"); + PRINTF("INFO: - Samples count: %u\r\n", N_SAMPLES); /* Same as dst_SAMPLE_COUNT */ + PRINTF("INFO: - Inputs count: %u\r\n", N_X_INPUTS); + PRINTF("INFO: - Outputs count: %u\r\n", N_Y_OUTPUTS); + PRINTF("INFO: - Data size: %u B\r\n", sizeof(float)); + PRINTF("INFO: - Total input size: %u B, %.2f KB, %.2f MB\r\n", N_X_INPUTS * N_SAMPLES * sizeof(float), (N_X_INPUTS * N_SAMPLES * sizeof(float)) / (float)1024, (N_X_INPUTS * N_SAMPLES * sizeof(float)) / (float)(1024*1024)); + PRINTF("INFO: - Total output size: %u B, %.2f KB, %.2f MB\r\n", N_Y_OUTPUTS * N_SAMPLES * sizeof(float), (N_Y_OUTPUTS * N_SAMPLES * sizeof(float)) / (float)1024, (N_Y_OUTPUTS * N_SAMPLES * sizeof(float)) / (float)(1024*1024)); + + // Set Heap Size in ldscript.ld to 0x1000000 (16MB) + //malloc_stats(); + + for (int i = 0; i < INPUT_N_ELEMENTS; i++) { + inputs_mem[i] = data_X_inputs[i]; + } + for (int i = 0; i < OUTPUT_N_ELEMENTS; i++) { + outputs_mem[i] = 0x0; + } + + /* ****** SW REFERENCE ****** */ + PRINTF("INFO: ==================================================\r\n"); + PRINTF("INFO: Start SW reference implementation\r\n"); + start_64b_counter(); + sw_reference_implementation(inputs_mem, reference_mem, N_SAMPLES, N_X_INPUTS, N_Y_OUTPUTS); + stop_64b_counter(); + sw_elapsed = get_64b_counter_value(); + PRINTF("INFO: ==================================================\r\n"); + PRINTF("INFO: Press any key to start:\r\n"); + dummy = inbyte(); + //PRINTF("INFO:"); + + /* ****** HW ACCELERATOR ****** */ + PRINTF("INFO: Start HW accelerator\r\n"); + start_64b_counter(); + Xil_DCacheFlushRange((UINTPTR)inputs_mem, INPUT_N_ELEMENTS * sizeof(float)); + Xil_DCacheFlushRange((UINTPTR)outputs_mem, OUTPUT_N_ELEMENTS * sizeof(float)); + Xil_DCacheFlushRange((UINTPTR)reference_mem, OUTPUT_N_ELEMENTS * sizeof(float)); + stop_64b_counter(); + cache_elapsed = get_64b_counter_value(); + + for (unsigned j = 0; j < N_SAMPLES; j++) { + float *inputs_mem_i = inputs_mem + j * N_X_INPUTS; + float *outputs_mem_i = outputs_mem + j * N_Y_OUTPUTS; + + /* Configure the accelerator */ + start_64b_counter(); + XMyproject_axi_Set_in_r(&accelerator, (unsigned)inputs_mem_i); /* TODO: design-dependent name */ + XMyproject_axi_Set_out_r(&accelerator, (unsigned)outputs_mem_i); /* TODO: design-dependent name */ + + XMyproject_axi_Start(&accelerator); /* TODO: design-dependent name */ + + /* Polling */ + while (!XMyproject_axi_IsDone(&accelerator)); /* TODO: design-dependent name */ + + /* Get error status */ + //hw_flags = XMyproject_axi_Get_return(&accelerator); /* TODO: design-dependent name */ + stop_64b_counter(); + hw_elapsed += get_64b_counter_value(); + } + + start_64b_counter(); + Xil_DCacheFlushRange((UINTPTR)outputs_mem, OUTPUT_N_ELEMENTS * sizeof(float)); + stop_64b_counter(); + cache_elapsed += get_64b_counter_value(); + + PRINTF("INFO: HW accelerator done!\r\n"); + + /* ****** VALIDATION ****** */ + PRINTF("INFO: ================== Verification ==================\r\n"); +#ifdef __DEBUG__ + PRINTF("INFO: Dump data\r\n"); + dump_data("inputs_mem", inputs_mem, N_SAMPLES, N_X_INPUTS); + dump_data("outputs_mem", outputs_mem, N_SAMPLES, N_Y_OUTPUTS); + dump_data("reference_mem", reference_mem, N_SAMPLES, N_Y_OUTPUTS); +#endif + +#ifdef __DEBUG__ + PRINTF("INFO: SW execution time: %f sec\r\n", sw_elapsed); +#endif + PRINTF("INFO: HW-acceleration exec. time (%d inferences):\r\n", N_SAMPLES); + PRINTF("INFO: - total %f sec\r\n", get_elapsed_time_ns(hw_elapsed)); + PRINTF("INFO: - per-inference %.12f sec (%f ns)\r\n", get_elapsed_time_ns(hw_elapsed) / (N_SAMPLES), (get_elapsed_time_ns(hw_elapsed)*1000.0) / (N_SAMPLES)); + PRINTF("INFO: Cache flush time: %f sec\r\n", get_elapsed_time_ns(cache_elapsed)); +#ifdef __DEBUG__ + PRINTF("INFO: HW/SW speedup (the software is fake so this does not count...): %.2f X\r\n", (sw_elapsed >= (hw_elapsed+cache_elapsed))?(sw_elapsed/(hw_elapsed+cache_elapsed)):-((hw_elapsed+cache_elapsed)/sw_elapsed)); +#endif + + hw_errors = 0; +#if 1 + /* Accelerator verification */ + for (int i = 0; i < OUTPUT_N_ELEMENTS; i++) { + if (outputs_mem[i] != reference_mem[i]) { + PRINTF("ERROR: [%d]: Accelerator HW %f != SW %f\r\n", i, outputs_mem[i], reference_mem[i]); + hw_errors++; + } + } + PRINTF("INFO: Total errors = %d (out of %d elements)\r\n", hw_errors, OUTPUT_N_ELEMENTS); + if (hw_errors > 0) + PRINTF("INFO: Verification: FAIL\r\n"); + else + PRINTF("INFO: Verification: PASS!\r\n"); +#else + /* Accelerator validation */ + for (unsigned s = 0; s < N_SAMPLES; s++) { + unsigned ref_digit = get_max(reference_mem + s * N_Y_OUTPUTS, N_Y_OUTPUTS); + unsigned hw_digit = get_max(outputs_mem + s * N_Y_OUTPUTS, N_Y_OUTPUTS); + if (hw_digit != ref_digit) { +#ifdef __DEBUG__ + PRINTF("ERROR: [%d]: Accelerator HW %u != SW %u\r\n", s, hw_digit, ref_digit); +#endif + hw_errors++; + } + } + float error_rate = (hw_errors / (float)(N_SAMPLES)) * 100.0; + float accuracy = 100 - ((hw_errors / (float)(N_SAMPLES)) * 100.0); + PRINTF("INFO: Total errors = %d (out of %d digits)\r\n", hw_errors, N_SAMPLES); + PRINTF("INFO: Error rate = %.2f %%\r\n", error_rate); + PRINTF("INFO: Accuracy = %.2f %%\r\n", accuracy); +#endif + + PRINTF("INFO: ==================================================\r\n"); + + +#ifdef EEMBC_POWER + /* Initialize the GPIO driver */ + status = XGpio_Initialize(&Gpio, GPIO_PMOD_PIN_DEVICE_ID); + if (status != XST_SUCCESS) { + xil_printf("GPIO Initialization Failed\r\n"); + return XST_FAILURE; + } + + set_pin_low(&Gpio, PIN); + + PRINTF("INFO: Connect logic analyzer to the pin 3 of Pmod D\r\n"); + PRINTF("INFO: Press any key to start:\r\n"); + dummy = inbyte(); + + /* Loop forever */ + for (unsigned i; i < 100; i++) { + set_pin_high(&Gpio, PIN); + + sleep(1); + + set_pin_low(&Gpio, PIN); + + sleep(1); + } +#endif + + cleanup_platform(); + + return 0; +} + diff --git a/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/setup.tcl b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/setup.tcl new file mode 100644 index 000000000..383bf39cf --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/setup.tcl @@ -0,0 +1,14 @@ +# See +# https://www.xilinx.com/html_docs/xilinx2019_1/SDK_Doc/xsct/intro/xsct_introduction.html + +setws . +if { $::argc == 1 } { + set myproject [lindex $::argv 0] + createhw -name ${myproject}\_platform -hwspec ../hdf/${myproject}\_wrapper.hdf + createapp -name ${myproject}\_standalone -app {Hello World} -proc microblaze_mcu -hwproject ${myproject}\_platform -os standalone + configapp -app ${myproject}\_standalone build-config release + #configapp -app ${myproject}\_standalone -add linker-misc {-Wl,--defsym=_HEAP_SIZE=0x1000000} + #configapp -app ${myproject}\_standalone -add linker-misc {-Wl,--defsym=_STACK_SIZE=0x40000} + projects -build + #configapp -app ${myproject}\_standalone -add define-compiler-symbols {FLAG=VALUE} +} diff --git a/hls4ml/templates/vivado_accelerator/vcu128/tcl_scripts/axi_master_design.tcl b/hls4ml/templates/vivado_accelerator/vcu128/tcl_scripts/axi_master_design.tcl new file mode 100644 index 000000000..a0540bcb5 --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/tcl_scripts/axi_master_design.tcl @@ -0,0 +1,537 @@ + +################################################################ +# +# MIT License +# +# Copyright (c) 2022 University of Sherbrooke +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# Author : Mehdi Rahimifar +# Last update : 2022-08-25 +# Description : This contains the tcl scripts to generate the right block design for VCU128 and the accelerator from hls4ml in Vivado +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + + + +set tcldir [file dirname [info script]] +source [file join $tcldir project.tcl] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + + + +set project_name "project_1" +set design_name "design_1" +set hls_solution_name "solution1" +#set acc_name "${myproject}_axi" +set part_name "xcvu37p-fsvh2892-2L-e" +set board_name "xilinx.com:vcu128:part0:1.0" + + + + + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 ${myproject}_vivado_accelerator -part xcvu37p-fsvh2892-2L-e -force + set_property BOARD_PART xilinx.com:vcu128:part0:1.0 [current_project] +} + + + + +# Setup IP repo +set_property ip_repo_paths ${myproject}_prj/${hls_solution_name}/impl/ip [current_project] +#set_property ip_repo_paths /home/subnugler/Desktop/MICROBLAZE_TEST/Microblaze/myproject_prj/${hls_solution_name}/impl/ip [current_project] +update_ip_catalog + + + + + + +#CHANGED HERE!!!!!!!!!!! + +# CHANGE DESIGN NAME HERE +#variable design_name +#set design_name design_1 + + + + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:axi_timer:2.0\ +xilinx.com:ip:axi_uart16550:2.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:mdm:3.2\ +xilinx.com:ip:microblaze:11.0\ +xilinx.com:hls:myproject_axi:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:lmb_bram_if_cntlr:4.0\ +xilinx.com:ip:lmb_v10:3.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: microblaze_0_local_memory +proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB + + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB + + + # Create pins + create_bd_pin -dir I -type clk LMB_Clk + create_bd_pin -dir I -type rst SYS_Rst + + # Create instance: dlmb_bram_if_cntlr, and set properties + set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $dlmb_bram_if_cntlr + + # Create instance: dlmb_v10, and set properties + set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] + + # Create instance: ilmb_bram_if_cntlr, and set properties + set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $ilmb_bram_if_cntlr + + # Create instance: ilmb_v10, and set properties + set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] + + # Create instance: lmb_bram, and set properties + set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] + set_property -dict [ list \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $lmb_bram + + # Create interface connections + connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] + + # Create port connections + connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram ] + + set default_100mhz_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_100mhz_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $default_100mhz_clk + + set rs232_uart_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart_0 ] + + + # Create ports + set dummy_port_in [ create_bd_port -dir I -type rst dummy_port_in ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $dummy_port_in + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {4} \ + ] $axi_smc + + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + + # Create instance: axi_uart16550_0, and set properties + set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] + set_property -dict [ list \ + CONFIG.UART_BOARD_INTERFACE {rs232_uart_0} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_uart16550_0 + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKOUT1_JITTER {166.057} \ + CONFIG.CLKOUT1_PHASE_ERROR {298.404} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {125.000} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $clk_wiz_0 + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_100mhz_clk} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ + CONFIG.RESET_BOARD_INTERFACE {dummy_port_in} \ + ] $ddr4_0 + + # Create instance: mdm_1, and set properties + set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] + + # Create instance: microblaze_0, and set properties + set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 microblaze_0 ] + set_property -dict [ list \ + CONFIG.C_ADDR_TAG_BITS {16} \ + CONFIG.C_CACHE_BYTE_SIZE {32768} \ + CONFIG.C_DCACHE_ADDR_TAG {16} \ + CONFIG.C_DCACHE_BYTE_SIZE {32768} \ + CONFIG.C_DCACHE_USE_WRITEBACK {1} \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_DIV_ZERO_EXCEPTION {1} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_D_LMB {1} \ + CONFIG.C_FPU_EXCEPTION {1} \ + CONFIG.C_ICACHE_LINE_LEN {8} \ + CONFIG.C_ICACHE_STREAMS {1} \ + CONFIG.C_ICACHE_VICTIMS {8} \ + CONFIG.C_ILL_OPCODE_EXCEPTION {1} \ + CONFIG.C_I_LMB {1} \ + CONFIG.C_MMU_ZONES {2} \ + CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \ + CONFIG.C_NUMBER_OF_PC_BRK {2} \ + CONFIG.C_NUMBER_OF_RD_ADDR_BRK {1} \ + CONFIG.C_NUMBER_OF_WR_ADDR_BRK {1} \ + CONFIG.C_OPCODE_0x0_ILLEGAL {1} \ + CONFIG.C_PVR {2} \ + CONFIG.C_UNALIGNED_EXCEPTIONS {1} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_DCACHE {1} \ + CONFIG.C_USE_DIV {1} \ + CONFIG.C_USE_FPU {1} \ + CONFIG.C_USE_HW_MUL {2} \ + CONFIG.C_USE_ICACHE {1} \ + CONFIG.C_USE_MMU {3} \ + CONFIG.C_USE_MSR_INSTR {1} \ + CONFIG.C_USE_PCMP_INSTR {1} \ + CONFIG.G_TEMPLATE_LIST {10} \ + CONFIG.G_USE_EXCEPTIONS {1} \ + ] $microblaze_0 + + # Create instance: microblaze_0_axi_periph, and set properties + set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {4} \ + ] $microblaze_0_axi_periph + + # Create instance: microblaze_0_local_memory + create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory + + # Create instance: myproject_axi_0, and set properties + set myproject_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:myproject_axi:1.0 myproject_axi_0 ] + + # Create instance: rst_clk_wiz_0_100M, and set properties + set rst_clk_wiz_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_0_100M ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_clk_wiz_0_100M + + # Create instance: rst_ddr4_0_333M, and set properties + set rst_ddr4_0_333M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4_0_333M ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports rs232_uart_0] [get_bd_intf_pins axi_uart16550_0/UART] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] [get_bd_intf_pins myproject_axi_0/s_axi_CTRL_BUS] + connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] + connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] + connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] + connect_bd_intf_net -intf_net myproject_axi_0_m_axi_IN_BUS [get_bd_intf_pins axi_smc/S02_AXI] [get_bd_intf_pins myproject_axi_0/m_axi_IN_BUS] + connect_bd_intf_net -intf_net myproject_axi_0_m_axi_OUT_BUS [get_bd_intf_pins axi_smc/S03_AXI] [get_bd_intf_pins myproject_axi_0/m_axi_OUT_BUS] + + # Create port connections + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_clk_wiz_0_100M/dcm_locked] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_smc/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins rst_ddr4_0_333M/slowest_sync_clk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins rst_clk_wiz_0_100M/ext_reset_in] [get_bd_pins rst_ddr4_0_333M/ext_reset_in] + connect_bd_net -net dummy_port_in_1 [get_bd_ports dummy_port_in] [get_bd_pins ddr4_0/sys_rst] + connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_0_100M/mb_debug_sys_rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_smc/aclk1] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins myproject_axi_0/ap_clk] [get_bd_pins rst_clk_wiz_0_100M/slowest_sync_clk] + connect_bd_net -net rst_clk_wiz_0_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_clk_wiz_0_100M/bus_struct_reset] + connect_bd_net -net rst_clk_wiz_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_0_100M/mb_reset] + connect_bd_net -net rst_clk_wiz_0_100M_peripheral_aresetn [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins myproject_axi_0/ap_rst_n] [get_bd_pins rst_clk_wiz_0_100M/peripheral_aresetn] + connect_bd_net -net rst_ddr4_0_333M_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins rst_ddr4_0_333M/peripheral_aresetn] + + # Create address segments + assign_bd_address -offset 0x41C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force + assign_bd_address -offset 0x44A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x44B00000 -range 0x00100000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] -force + assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] -force + assign_bd_address -offset 0x44A10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs myproject_axi_0/s_axi_CTRL_BUS/Reg] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces myproject_axi_0/Data_m_axi_IN_BUS] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces myproject_axi_0/Data_m_axi_OUT_BUS] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + +############################################################################################################# + +#WRAP THE MODEL + +make_wrapper -files [get_files ./${myproject}_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/design_1.bd] -top + +add_files -norecurse ./${myproject}_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v + +reset_run impl_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 6 +wait_on_run -timeout 360 impl_1 + +#open_run impl_1 +report_utilization -file util.rpt -hierarchical -hierarchical_percentages + + + + + + + + + + + + + + + + + diff --git a/hls4ml/templates/vivado_accelerator/vcu128/verilog_wrappers/design_1_wrapper.v b/hls4ml/templates/vivado_accelerator/vcu128/verilog_wrappers/design_1_wrapper.v new file mode 100644 index 000000000..aa944e12a --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/verilog_wrappers/design_1_wrapper.v @@ -0,0 +1,92 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +//Date : Wed Oct 5 16:49:36 2022 +//Host : subnugler running 64-bit Ubuntu 22.04.1 LTS +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (ddr4_sdram_act_n, + ddr4_sdram_adr, + ddr4_sdram_ba, + ddr4_sdram_bg, + ddr4_sdram_ck_c, + ddr4_sdram_ck_t, + ddr4_sdram_cke, + ddr4_sdram_cs_n, + ddr4_sdram_dm_n, + ddr4_sdram_dq, + ddr4_sdram_dqs_c, + ddr4_sdram_dqs_t, + ddr4_sdram_odt, + ddr4_sdram_reset_n, + default_100mhz_clk_clk_n, + default_100mhz_clk_clk_p, + dummy_port_in, + rs232_uart_0_rxd, + rs232_uart_0_txd); + output ddr4_sdram_act_n; + output [16:0]ddr4_sdram_adr; + output [1:0]ddr4_sdram_ba; + output ddr4_sdram_bg; + output ddr4_sdram_ck_c; + output ddr4_sdram_ck_t; + output ddr4_sdram_cke; + output [1:0]ddr4_sdram_cs_n; + inout [8:0]ddr4_sdram_dm_n; + inout [71:0]ddr4_sdram_dq; + inout [8:0]ddr4_sdram_dqs_c; + inout [8:0]ddr4_sdram_dqs_t; + output ddr4_sdram_odt; + output ddr4_sdram_reset_n; + input default_100mhz_clk_clk_n; + input default_100mhz_clk_clk_p; + input dummy_port_in; + input rs232_uart_0_rxd; + output rs232_uart_0_txd; + + wire ddr4_sdram_act_n; + wire [16:0]ddr4_sdram_adr; + wire [1:0]ddr4_sdram_ba; + wire ddr4_sdram_bg; + wire ddr4_sdram_ck_c; + wire ddr4_sdram_ck_t; + wire ddr4_sdram_cke; + wire [1:0]ddr4_sdram_cs_n; + wire [8:0]ddr4_sdram_dm_n; + wire [71:0]ddr4_sdram_dq; + wire [8:0]ddr4_sdram_dqs_c; + wire [8:0]ddr4_sdram_dqs_t; + wire ddr4_sdram_odt; + wire ddr4_sdram_reset_n; + wire default_100mhz_clk_clk_n; + wire default_100mhz_clk_clk_p; + wire dummy_port_in; + wire rs232_uart_0_rxd; + wire rs232_uart_0_txd; + + design_1 design_1_i + (.ddr4_sdram_act_n(ddr4_sdram_act_n), + .ddr4_sdram_adr(ddr4_sdram_adr), + .ddr4_sdram_ba(ddr4_sdram_ba), + .ddr4_sdram_bg(ddr4_sdram_bg), + .ddr4_sdram_ck_c(ddr4_sdram_ck_c), + .ddr4_sdram_ck_t(ddr4_sdram_ck_t), + .ddr4_sdram_cke(ddr4_sdram_cke), + .ddr4_sdram_cs_n(ddr4_sdram_cs_n), + .ddr4_sdram_dm_n(ddr4_sdram_dm_n), + .ddr4_sdram_dq(ddr4_sdram_dq), + .ddr4_sdram_dqs_c(ddr4_sdram_dqs_c), + .ddr4_sdram_dqs_t(ddr4_sdram_dqs_t), + .ddr4_sdram_odt(ddr4_sdram_odt), + .ddr4_sdram_reset_n(ddr4_sdram_reset_n), + .default_100mhz_clk_clk_n(default_100mhz_clk_clk_n), + .default_100mhz_clk_clk_p(default_100mhz_clk_clk_p), + .dummy_port_in(dummy_port_in), + .rs232_uart_0_rxd(rs232_uart_0_rxd), + .rs232_uart_0_txd(rs232_uart_0_txd)); +endmodule diff --git a/hls4ml/templates/vivado_accelerator/zcu104/python_drivers/axi_stream_driver.py b/hls4ml/templates/vivado_accelerator/zcu104/python_drivers/axi_stream_driver.py new file mode 100644 index 000000000..4adb187ab --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/zcu104/python_drivers/axi_stream_driver.py @@ -0,0 +1,75 @@ +from pynq import DefaultHierarchy, DefaultIP, allocate +from pynq import Overlay +from datetime import datetime +import pynq.lib.dma +import numpy as np + + +class NeuralNetworkOverlay(Overlay): + def __init__(self, bitfile_name, x_shape, y_shape, dtype=np.float32, dtbo=None, download=True, ignore_version=False, + device=None): + super().__init__(bitfile_name, dtbo=None, download=True, ignore_version=False, device=None) + self.sendchannel = self.hier_0.axi_dma_0.sendchannel + self.recvchannel = self.hier_0.axi_dma_0.recvchannel + self.input_buffer = allocate(shape=x_shape, dtype=dtype) + self.output_buffer = allocate(shape=y_shape, dtype=dtype) + + def _print_dt(self, timea, timeb, N): + dt = (timeb - timea) + dts = dt.seconds + dt.microseconds * 10 ** -6 + rate = N / dts + print("Classified {} samples in {} seconds ({} inferences / s)".format(N, dts, rate)) + return dts, rate + + def predict(self, X, debug=False, profile=False, encode=None, decode=None): + """ + Obtain the predictions of the NN implemented in the FPGA. + Parameters: + - X : the input vector. Should be numpy ndarray. + - dtype : the data type of the elements of the input/output vectors. + Note: it should be set depending on the interface of the accelerator; if it uses 'float' + types for the 'data' AXI-Stream field, 'np.float32' dtype is the correct one to use. + Instead if it uses 'ap_fixed', 'np.intA' is the correct one to use (note that A cannot + any integer value, but it can assume {..., 8, 16, 32, ...} values. Check `numpy` + doc for more info). + In this case the encoding/decoding has to be computed by the PS. For example for + 'ap_fixed<16,6>' type the following 2 functions are the correct one to use for encode/decode + 'float' -> 'ap_fixed<16,6>': + ``` + def encode(xi): + return np.int16(round(xi * 2**10)) # note 2**10 = 2**(A-B) + def decode(yi): + return yi * 2**-10 + encode_v = np.vectorize(encode) # to apply them element-wise + decode_v = np.vectorize(decode) + ``` + - profile : boolean. Set it to `True` to print the performance of the algorithm in term of `inference/s`. + - encode/decode: function pointers. See `dtype` section for more information. + - return: an output array based on `np.ndarray` with a shape equal to `y_shape` and a `dtype` equal to + the namesake parameter. + """ + if profile: + timea = datetime.now() + if encode is not None: + X = encode(X) + self.input_buffer[:] = X + self.sendchannel.transfer(self.input_buffer) + self.recvchannel.transfer(self.output_buffer) + if debug: + print("Transfer OK") + self.sendchannel.wait() + if debug: + print("Send OK") + self.recvchannel.wait() + if debug: + print("Receive OK") + # result = self.output_buffer.copy() + if decode is not None: + self.output_buffer = decode(self.output_buffer) + + if profile: + timeb = datetime.now() + dts, rate = self._print_dt(timea, timeb, len(X)) + return self.output_buffer, dts, rate + else: + return self.output_buffer \ No newline at end of file diff --git a/hls4ml/templates/vivado_accelerator/zcu104/tcl_scripts/axi_stream_design.tcl b/hls4ml/templates/vivado_accelerator/zcu104/tcl_scripts/axi_stream_design.tcl new file mode 100644 index 000000000..4a35d1bb5 --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/zcu104/tcl_scripts/axi_stream_design.tcl @@ -0,0 +1,1795 @@ + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + + + + +set tcldir [file dirname [info script]] +source [file join $tcldir project.tcl] +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +#set scripts_vivado_version 2019.1 +#set current_vivado_version [version -short] + +#if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { +# puts "" +# catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + # return 1 +#} + +############################################################### +# START +############################################################### + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + + + +set project_name "project_1" +set design_name "design_1" +set hls_solution_name "solution1" +#set acc_name "${myproject}_axi" +set part_name "xczu7ev-ffvc1156-2-e" +set board_name "xilinx.com:zcu104:part0:1.1" + + + + + + + + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 ${myproject}_vivado_accelerator -part xczu7ev-ffvc1156-2-e -force + set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project] +} + + + +# Setup IP repo +set_property ip_repo_paths ${myproject}_prj/${hls_solution_name}/impl/ip [current_project] +#set_property ip_repo_paths /home/subnugler/Desktop/MICROBLAZE_TEST/Microblaze/myproject_prj/${hls_solution_name}/impl/ip [current_project] +update_ip_catalog + + + + + + +# CHANGE DESIGN NAME HERE +#variable design_name +#set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:hls:myproject_axi:1.0\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: hier_0 +proc create_hier_cell_hier_0 { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_hier_0() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE + + + # Create pins + create_bd_pin -dir I -type rst ap_rst_n + create_bd_pin -dir I -type clk m_axi_mm2s_aclk + + # Create instance: axi_dma_0, and set properties + set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] + set_property -dict [ list \ + CONFIG.c_include_sg {0} \ + CONFIG.c_m_axi_mm2s_data_width {32} \ + CONFIG.c_m_axi_s2mm_data_width {32} \ + CONFIG.c_m_axis_mm2s_tdata_width {32} \ + CONFIG.c_mm2s_burst_size {256} \ + CONFIG.c_s2mm_burst_size {256} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_0 + + # Create instance: myproject_axi_1, and set properties + set myproject_axi_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:myproject_axi:1.0 myproject_axi_1 ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins myproject_axi_1/in_r] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] + connect_bd_intf_net -intf_net myproject_axi_1_out_r [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins myproject_axi_1/out_r] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_dma_0/S_AXI_LITE] + + # Create port connections + connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins ap_rst_n] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins myproject_axi_1/ap_rst_n] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins myproject_axi_1/ap_clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {2} \ + ] $axi_smc + + # Create instance: hier_0 + create_hier_cell_hier_0 [current_bd_instance .] hier_0 + + # Create instance: ps8_0_axi_periph, and set properties + set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $ps8_0_axi_periph + + # Create instance: rst_ps8_0_99M, and set properties + set rst_ps8_0_99M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_99M ] + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {out} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {in} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {out} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {in} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {out} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {in} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {out} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {out} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {out} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {in} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {out} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.560059} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.880127} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.280029} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.940063} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.997501} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.783037} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.970032} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.940063} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.950043} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.280029} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.950043} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.995003} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.950043} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.850098} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.987511} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.950043} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.481262} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.987511} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.481262} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.975021} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.998001} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DEVICE_TYPE {EV} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Single Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.990005} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {0} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {1} \ + CONFIG.PSU__GPU_PP1__POWER__ON {1} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.990005} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.990005} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \ + CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \ + CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {0x0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {1} \ + CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \ + CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \ + CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \ + CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {0x0} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.330} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {1} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {32} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD0__RESET__ENABLE {0} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB0__RESET__ENABLE {0} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB1__RESET__ENABLE {0} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {0} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__USE__M_AXI_GP1 {1} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $zynq_ultra_ps_e_0 + + # Create interface connections + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins hier_0/M_AXI_MM2S] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins hier_0/M_AXI_S2MM] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins hier_0/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins ps8_0_axi_periph/S01_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD] + + # Create port connections + connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_smc/aresetn] [get_bd_pins hier_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins ps8_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps8_0_99M/peripheral_aresetn] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_smc/aclk] [get_bd_pins hier_0/m_axi_mm2s_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins ps8_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps8_0_99M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] + connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_99M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + + # Create address segments + create_bd_addr_seg -range 0x00001000 -offset 0xA0000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs hier_0/axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HPC0_DDR_LOW + create_bd_addr_seg -range 0x10000000 -offset 0xE0000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_PCIE_LOW] SEG_zynq_ultra_ps_e_0_HPC0_PCIE_LOW + create_bd_addr_seg -range 0x10000000 -offset 0xE0000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_PCIE_LOW] SEG_zynq_ultra_ps_e_0_HPC0_PCIE_LOW + create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI + create_bd_addr_seg -range 0x20000000 -offset 0xC0000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] SEG_zynq_ultra_ps_e_0_HPC0_QSPI + + # Exclude Address Segments + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM + exclude_bd_addr_seg [get_bd_addr_segs hier_0/axi_dma_0/Data_MM2S/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] + + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces hier_0/axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM + exclude_bd_addr_seg [get_bd_addr_segs hier_0/axi_dma_0/Data_S2MM/SEG_zynq_ultra_ps_e_0_HPC0_LPS_OCM] + + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + + + +#WRAP THE MODEL + +make_wrapper -files [get_files ./${myproject}_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/design_1.bd] -top + +add_files -norecurse ./${myproject}_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v + +reset_run impl_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 6 +wait_on_run -timeout 360 impl_1 + +#open_run impl_1 +report_utilization -file util.rpt -hierarchical -hierarchical_percentages