From 43133e4b934be1453575cccd556c3cc8e711ea5e Mon Sep 17 00:00:00 2001 From: icmor Date: Fri, 17 May 2024 17:52:59 -0600 Subject: [PATCH] Random-access memory --- sequentialChips/RAM16K.hdl | 22 ++++++++++++++++++++++ sequentialChips/RAM4K.hdl | 26 ++++++++++++++++++++++++++ sequentialChips/RAM512.hdl | 26 ++++++++++++++++++++++++++ sequentialChips/RAM64.hdl | 26 ++++++++++++++++++++++++++ sequentialChips/RAM8.hdl | 26 ++++++++++++++++++++++++++ 5 files changed, 126 insertions(+) create mode 100644 sequentialChips/RAM16K.hdl create mode 100644 sequentialChips/RAM4K.hdl create mode 100644 sequentialChips/RAM512.hdl create mode 100644 sequentialChips/RAM64.hdl create mode 100644 sequentialChips/RAM8.hdl diff --git a/sequentialChips/RAM16K.hdl b/sequentialChips/RAM16K.hdl new file mode 100644 index 0000000..72a7523 --- /dev/null +++ b/sequentialChips/RAM16K.hdl @@ -0,0 +1,22 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/3/b/RAM16K.hdl +/** + * Memory of 16K 16-bit registers. + * If load is asserted, the value of the register selected by + * address is set to in; Otherwise, the value does not change. + * The value of the selected register is emitted by out. + */ +CHIP RAM16K { + IN in[16], load, address[14]; + OUT out[16]; + + PARTS: + DMux4Way(in=load, sel=address[12..13], a=l0, b=l1, c=l2, d=l3); + RAM4K(in=in, load=l0, address=address[0..11], out=r0); + RAM4K(in=in, load=l1, address=address[0..11], out=r1); + RAM4K(in=in, load=l2, address=address[0..11], out=r2); + RAM4K(in=in, load=l3, address=address[0..11], out=r3); + Mux4Way16(a=r0, b=r1, c=r2, d=r3, sel=address[12..13], out=out); +} diff --git a/sequentialChips/RAM4K.hdl b/sequentialChips/RAM4K.hdl new file mode 100644 index 0000000..a58d678 --- /dev/null +++ b/sequentialChips/RAM4K.hdl @@ -0,0 +1,26 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/3/b/RAM4K.hdl +/** + * Memory of 4K 16-bit registers. + * If load is asserted, the value of the register selected by + * address is set to in; Otherwise, the value does not change. + * The value of the selected register is emitted by out. + */ +CHIP RAM4K { + IN in[16], load, address[12]; + OUT out[16]; + + PARTS: + DMux8Way(in=load, sel=address[9..11], a=l0, b=l1, c=l2, d=l3, e=l4, f=l5, g=l6, h=l7); + RAM512(in=in, load=l0, address=address[0..8], out=r0); + RAM512(in=in, load=l1, address=address[0..8], out=r1); + RAM512(in=in, load=l2, address=address[0..8], out=r2); + RAM512(in=in, load=l3, address=address[0..8], out=r3); + RAM512(in=in, load=l4, address=address[0..8], out=r4); + RAM512(in=in, load=l5, address=address[0..8], out=r5); + RAM512(in=in, load=l6, address=address[0..8], out=r6); + RAM512(in=in, load=l7, address=address[0..8], out=r7); + Mux8Way16(a=r0, b=r1, c=r2, d=r3, e=r4, f=r5, g=r6, h=r7, sel=address[9..11], out=out); +} diff --git a/sequentialChips/RAM512.hdl b/sequentialChips/RAM512.hdl new file mode 100644 index 0000000..a328169 --- /dev/null +++ b/sequentialChips/RAM512.hdl @@ -0,0 +1,26 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/3/b/RAM512.hdl +/** + * Memory of 512 16-bit registers. + * If load is asserted, the value of the register selected by + * address is set to in; Otherwise, the value does not change. + * The value of the selected register is emitted by out. + */ +CHIP RAM512 { + IN in[16], load, address[9]; + OUT out[16]; + + PARTS: + DMux8Way(in=load, sel=address[6..8], a=l0, b=l1, c=l2, d=l3, e=l4, f=l5, g=l6, h=l7); + RAM64(in=in, load=l0, address=address[0..5], out=r0); + RAM64(in=in, load=l1, address=address[0..5], out=r1); + RAM64(in=in, load=l2, address=address[0..5], out=r2); + RAM64(in=in, load=l3, address=address[0..5], out=r3); + RAM64(in=in, load=l4, address=address[0..5], out=r4); + RAM64(in=in, load=l5, address=address[0..5], out=r5); + RAM64(in=in, load=l6, address=address[0..5], out=r6); + RAM64(in=in, load=l7, address=address[0..5], out=r7); + Mux8Way16(a=r0, b=r1, c=r2, d=r3, e=r4, f=r5, g=r6, h=r7, sel=address[6..8], out=out); +} diff --git a/sequentialChips/RAM64.hdl b/sequentialChips/RAM64.hdl new file mode 100644 index 0000000..bc09e33 --- /dev/null +++ b/sequentialChips/RAM64.hdl @@ -0,0 +1,26 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/3/a/RAM64.hdl +/** + * Memory of sixty four 16-bit registers. + * If load is asserted, the value of the register selected by + * address is set to in; Otherwise, the value does not change. + * The value of the selected register is emitted by out. + */ +CHIP RAM64 { + IN in[16], load, address[6]; + OUT out[16]; + + PARTS: + DMux8Way(in=load, sel=address[3..5], a=l0, b=l1, c=l2, d=l3, e=l4, f=l5, g=l6, h=l7); + RAM8(in=in, load=l0, address=address[0..2], out=r0); + RAM8(in=in, load=l1, address=address[0..2], out=r1); + RAM8(in=in, load=l2, address=address[0..2], out=r2); + RAM8(in=in, load=l3, address=address[0..2], out=r3); + RAM8(in=in, load=l4, address=address[0..2], out=r4); + RAM8(in=in, load=l5, address=address[0..2], out=r5); + RAM8(in=in, load=l6, address=address[0..2], out=r6); + RAM8(in=in, load=l7, address=address[0..2], out=r7); + Mux8Way16(a=r0, b=r1, c=r2, d=r3, e=r4, f=r5, g=r6, h=r7, sel=address[3..5], out=out); +} diff --git a/sequentialChips/RAM8.hdl b/sequentialChips/RAM8.hdl new file mode 100644 index 0000000..03e8e89 --- /dev/null +++ b/sequentialChips/RAM8.hdl @@ -0,0 +1,26 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/3/a/RAM8.hdl +/** + * Memory of eight 16-bit registers. + * If load is asserted, the value of the register selected by + * address is set to in; Otherwise, the value does not change. + * The value of the selected register is emitted by out. + */ +CHIP RAM8 { + IN in[16], load, address[3]; + OUT out[16]; + + PARTS: + DMux8Way(in=load, sel=address, a=l0, b=l1, c=l2, d=l3, e=l4, f=l5, g=l6, h=l7); + Register(in=in, load=l0, out=r0); + Register(in=in, load=l1, out=r1); + Register(in=in, load=l2, out=r2); + Register(in=in, load=l3, out=r3); + Register(in=in, load=l4, out=r4); + Register(in=in, load=l5, out=r5); + Register(in=in, load=l6, out=r6); + Register(in=in, load=l7, out=r7); + Mux8Way16(a=r0, b=r1, c=r2, d=r3, e=r4, f=r5, g=r6, h=r7, sel=address, out=out); +}